From 1d895781095267c5f22d945a8f4a685303c1ff3b Mon Sep 17 00:00:00 2001 From: GoldBr1987 Date: Sat, 4 Sep 2021 17:56:49 +0800 Subject: [PATCH] =?UTF-8?q?HC32F460PETB=E7=A7=BB=E6=A4=8Drt-thread?= =?UTF-8?q?=E3=80=82=E7=A7=BB=E6=A4=8D=E9=AA=8C=E8=AF=81=E9=80=9A=E8=BF=87?= =?UTF-8?q?pin=E9=A9=B1=E5=8A=A8=EF=BC=8Cuart=E9=A9=B1=E5=8A=A8=EF=BC=88?= =?UTF-8?q?=E5=8C=85=E5=90=ABuart1=EF=BC=8C2=EF=BC=8C3=EF=BC=8C4=EF=BC=89?= =?UTF-8?q?=EF=BC=8C=E9=BB=98=E8=AE=A4=E4=BD=BF=E7=94=A8uart4=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/Copyright_Notice.md | 12 + bsp/hc32f460/.config | 600 + bsp/hc32f460/.gitignore | 42 + bsp/hc32f460/.ignore_format.yml | 8 + bsp/hc32f460/EventRecorderStub.scvd | 9 + bsp/hc32f460/Kconfig | 23 + .../Device/HDSC/HC32F460/Include/ddl_config.h | 159 + .../HDSC/HC32F460/Include/hc32_common.h | 234 + .../Device/HDSC/HC32F460/Include/hc32_ddl.h | 262 + .../Device/HDSC/HC32F460/Include/hc32f460.h | 30601 ++++++++++++++++ .../HDSC/HC32F460/Include/system_hc32f460.h | 105 + .../HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR | Bin 0 -> 1620497 bytes .../HC32F460/Source/ARM/startup_hc32f460.s | 621 + .../HC32F460/Source/GCC/startup_hc32f460.S | 538 + .../HDSC/HC32F460/Source/system_hc32f460.c | 117 + .../Libraries/CMSIS/Include/cmsis_armcc.h | 894 + .../Libraries/CMSIS/Include/cmsis_armclang.h | 1444 + .../CMSIS/Include/cmsis_armclang_ltm.h | 1891 + .../Libraries/CMSIS/Include/cmsis_compiler.h | 283 + .../Libraries/CMSIS/Include/cmsis_gcc.h | 2168 ++ .../Libraries/CMSIS/Include/cmsis_iccarm.h | 964 + .../Libraries/CMSIS/Include/cmsis_version.h | 39 + .../Libraries/CMSIS/Include/core_armv81mml.h | 2968 ++ .../Libraries/CMSIS/Include/core_armv8mbl.h | 1921 + .../Libraries/CMSIS/Include/core_armv8mml.h | 2835 ++ .../Libraries/CMSIS/Include/core_cm0.h | 952 + .../Libraries/CMSIS/Include/core_cm0plus.h | 1085 + .../Libraries/CMSIS/Include/core_cm1.h | 979 + .../Libraries/CMSIS/Include/core_cm23.h | 1996 + .../Libraries/CMSIS/Include/core_cm3.h | 1937 + .../Libraries/CMSIS/Include/core_cm33.h | 2910 ++ .../Libraries/CMSIS/Include/core_cm35p.h | 2910 ++ .../Libraries/CMSIS/Include/core_cm4.h | 2124 ++ .../Libraries/CMSIS/Include/core_cm7.h | 2725 ++ .../Libraries/CMSIS/Include/core_sc000.h | 1025 + .../Libraries/CMSIS/Include/core_sc300.h | 1912 + .../Libraries/CMSIS/Include/mpu_armv7.h | 272 + .../Libraries/CMSIS/Include/mpu_armv8.h | 346 + .../Libraries/CMSIS/Include/tz_context.h | 70 + .../inc/hc32f460_adc.h | 509 + .../inc/hc32f460_aes.h | 81 + .../inc/hc32f460_can.h | 514 + .../inc/hc32f460_clk.h | 647 + .../inc/hc32f460_cmp.h | 279 + .../inc/hc32f460_crc.h | 118 + .../inc/hc32f460_dcu.h | 216 + .../inc/hc32f460_dmac.h | 363 + .../inc/hc32f460_efm.h | 209 + .../inc/hc32f460_emb.h | 205 + .../inc/hc32f460_event_port.h | 176 + .../inc/hc32f460_exint_nmi_swi.h | 257 + .../inc/hc32f460_gpio.h | 294 + .../inc/hc32f460_hash.h | 72 + .../inc/hc32f460_i2c.h | 270 + .../inc/hc32f460_i2s.h | 206 + .../inc/hc32f460_icg.h | 400 + .../inc/hc32f460_interrupts.h | 570 + .../inc/hc32f460_keyscan.h | 191 + .../inc/hc32f460_mpu.h | 293 + .../inc/hc32f460_ots.h | 139 + .../inc/hc32f460_pwc.h | 567 + .../inc/hc32f460_qspi.h | 402 + .../inc/hc32f460_rmu.h | 96 + .../inc/hc32f460_rtc.h | 274 + .../inc/hc32f460_sdioc.h | 559 + .../inc/hc32f460_spi.h | 426 + .../inc/hc32f460_sram.h | 190 + .../inc/hc32f460_swdt.h | 86 + .../inc/hc32f460_timer0.h | 209 + .../inc/hc32f460_timer4_cnt.h | 209 + .../inc/hc32f460_timer4_emb.h | 115 + .../inc/hc32f460_timer4_oco.h | 273 + .../inc/hc32f460_timer4_pwm.h | 158 + .../inc/hc32f460_timer4_sevt.h | 221 + .../inc/hc32f460_timer6.h | 734 + .../inc/hc32f460_timera.h | 493 + .../inc/hc32f460_trng.h | 100 + .../inc/hc32f460_usart.h | 359 + .../inc/hc32f460_utility.h | 108 + .../inc/hc32f460_wdt.h | 162 + .../src/hc32f460_adc.c | 1739 + .../src/hc32f460_aes.c | 311 + .../src/hc32f460_can.c | 532 + .../src/hc32f460_clk.c | 1813 + .../src/hc32f460_cmp.c | 1046 + .../src/hc32f460_crc.c | 327 + .../src/hc32f460_dcu.c | 975 + .../src/hc32f460_dmac.c | 1827 + .../src/hc32f460_efm.c | 942 + .../src/hc32f460_emb.c | 487 + .../src/hc32f460_event_port.c | 468 + .../src/hc32f460_exint_nmi_swi.c | 337 + .../src/hc32f460_gpio.c | 671 + .../src/hc32f460_hash.c | 301 + .../src/hc32f460_i2c.c | 1318 + .../src/hc32f460_i2s.c | 437 + .../src/hc32f460_icg.c | 83 + .../src/hc32f460_interrupts.c | 3844 ++ .../src/hc32f460_keyscan.c | 207 + .../src/hc32f460_mpu.c | 1057 + .../src/hc32f460_ots.c | 386 + .../src/hc32f460_pwc.c | 2025 + .../src/hc32f460_qspi.c | 756 + .../src/hc32f460_rmu.c | 143 + .../src/hc32f460_rtc.c | 978 + .../src/hc32f460_sdioc.c | 2222 ++ .../src/hc32f460_spi.c | 1132 + .../src/hc32f460_sram.c | 286 + .../src/hc32f460_swdt.c | 170 + .../src/hc32f460_timer0.c | 967 + .../src/hc32f460_timer4_cnt.c | 842 + .../src/hc32f460_timer4_emb.c | 278 + .../src/hc32f460_timer4_oco.c | 1295 + .../src/hc32f460_timer4_pwm.c | 600 + .../src/hc32f460_timer4_sevt.c | 593 + .../src/hc32f460_timer6.c | 1786 + .../src/hc32f460_timera.c | 1972 + .../src/hc32f460_trng.c | 263 + .../src/hc32f460_usart.c | 1640 + .../src/hc32f460_utility.c | 531 + .../src/hc32f460_wdt.c | 254 + bsp/hc32f460/Libraries/LICENSE | 29 + bsp/hc32f460/Libraries/SConscript | 47 + bsp/hc32f460/README.md | 59 + bsp/hc32f460/SConscript | 15 + bsp/hc32f460/SConstruct | 45 + bsp/hc32f460/applications/SConscript | 12 + bsp/hc32f460/applications/main.c | 61 + bsp/hc32f460/board/Kconfig | 41 + bsp/hc32f460/board/SConscript | 16 + bsp/hc32f460/board/board.c | 129 + bsp/hc32f460/board/board.h | 45 + bsp/hc32f460/board/board_config.c | 60 + bsp/hc32f460/board/board_config.h | 137 + bsp/hc32f460/board/linker_scripts/link.icf | 59 + bsp/hc32f460/board/linker_scripts/link.lds | 200 + bsp/hc32f460/board/linker_scripts/link.sct | 15 + bsp/hc32f460/drivers/SConscript | 21 + bsp/hc32f460/drivers/drv_gpio.c | 488 + bsp/hc32f460/drivers/drv_gpio.h | 151 + bsp/hc32f460/drivers/drv_irq.c | 46 + bsp/hc32f460/drivers/drv_irq.h | 37 + bsp/hc32f460/drivers/drv_usart.c | 527 + bsp/hc32f460/drivers/drv_usart.h | 19 + bsp/hc32f460/project.uvoptx | 1149 + bsp/hc32f460/project.uvprojx | 823 + bsp/hc32f460/rtconfig.h | 188 + bsp/hc32f460/rtconfig.py | 132 + bsp/hc32f460/template.uvopt | 162 + bsp/hc32f460/template.uvoptx | 189 + bsp/hc32f460/template.uvprojx | 406 + 151 files changed, 124880 insertions(+) create mode 100644 bsp/hc32f460/.config create mode 100644 bsp/hc32f460/.gitignore create mode 100644 bsp/hc32f460/.ignore_format.yml create mode 100644 bsp/hc32f460/EventRecorderStub.scvd create mode 100644 bsp/hc32f460/Kconfig create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S create mode 100644 bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h create mode 100644 bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer4_cnt.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer4_emb.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer4_oco.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer4_pwm.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer4_sevt.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer6.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c create mode 100644 bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c create mode 100644 bsp/hc32f460/Libraries/LICENSE create mode 100644 bsp/hc32f460/Libraries/SConscript create mode 100644 bsp/hc32f460/README.md create mode 100644 bsp/hc32f460/SConscript create mode 100644 bsp/hc32f460/SConstruct create mode 100644 bsp/hc32f460/applications/SConscript create mode 100644 bsp/hc32f460/applications/main.c create mode 100644 bsp/hc32f460/board/Kconfig create mode 100644 bsp/hc32f460/board/SConscript create mode 100644 bsp/hc32f460/board/board.c create mode 100644 bsp/hc32f460/board/board.h create mode 100644 bsp/hc32f460/board/board_config.c create mode 100644 bsp/hc32f460/board/board_config.h create mode 100644 bsp/hc32f460/board/linker_scripts/link.icf create mode 100644 bsp/hc32f460/board/linker_scripts/link.lds create mode 100644 bsp/hc32f460/board/linker_scripts/link.sct create mode 100644 bsp/hc32f460/drivers/SConscript create mode 100644 bsp/hc32f460/drivers/drv_gpio.c create mode 100644 bsp/hc32f460/drivers/drv_gpio.h create mode 100644 bsp/hc32f460/drivers/drv_irq.c create mode 100644 bsp/hc32f460/drivers/drv_irq.h create mode 100644 bsp/hc32f460/drivers/drv_usart.c create mode 100644 bsp/hc32f460/drivers/drv_usart.h create mode 100644 bsp/hc32f460/project.uvoptx create mode 100644 bsp/hc32f460/project.uvprojx create mode 100644 bsp/hc32f460/rtconfig.h create mode 100644 bsp/hc32f460/rtconfig.py create mode 100644 bsp/hc32f460/template.uvopt create mode 100644 bsp/hc32f460/template.uvoptx create mode 100644 bsp/hc32f460/template.uvprojx diff --git a/bsp/Copyright_Notice.md b/bsp/Copyright_Notice.md index 8ec2687a7..061969f09 100644 --- a/bsp/Copyright_Notice.md +++ b/bsp/Copyright_Notice.md @@ -216,6 +216,18 @@ Path: - bsp/hc32f4a0/Libraries/CMSIS - bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver +### hc32f460 + +License: bsd-new + +Copyright: Copyright (c) 2020, Huada Semiconductor Co., Ltd. + +Path: + +- bsp/hc32f460/Libraries/CMSIS +- bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver + + ### hk32 License: free-unknown diff --git a/bsp/hc32f460/.config b/bsp/hc32f460/.config new file mode 100644 index 000000000..e9037464e --- /dev/null +++ b/bsp/hc32f460/.config @@ -0,0 +1,600 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set + +# +# Hardware Drivers Config +# +CONFIG_MCU_HC32F460=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_UART4=y diff --git a/bsp/hc32f460/.gitignore b/bsp/hc32f460/.gitignore new file mode 100644 index 000000000..7221bde01 --- /dev/null +++ b/bsp/hc32f460/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32f460/.ignore_format.yml b/bsp/hc32f460/.ignore_format.yml new file mode 100644 index 000000000..13a5e1985 --- /dev/null +++ b/bsp/hc32f460/.ignore_format.yml @@ -0,0 +1,8 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + +dir_path: +- Libraries \ No newline at end of file diff --git a/bsp/hc32f460/EventRecorderStub.scvd b/bsp/hc32f460/EventRecorderStub.scvd new file mode 100644 index 000000000..2956b2968 --- /dev/null +++ b/bsp/hc32f460/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/hc32f460/Kconfig b/bsp/hc32f460/Kconfig new file mode 100644 index 000000000..f4ed99b3f --- /dev/null +++ b/bsp/hc32f460/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + + + diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h new file mode 100644 index 000000000..7bddac1a1 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file ddl_config.h + ** + ** A detailed description is available at + ** @link DdlConfigGroup Ddl Config description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library config. + ** + ******************************************************************************/ +#ifndef __DDL_CONFIG_H__ +#define __DDL_CONFIG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Chip module on-off define */ +#define DDL_ON (1u) +#define DDL_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of modules to be used in the device driver library + ** Select the modules you need to use to DDL_ON. + ** + ** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + ** properly. + ** + ** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + ** Library. + ** + ** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + ******************************************************************************/ +#define DDL_ICG_ENABLE (DDL_ON) +#define DDL_UTILITY_ENABLE (DDL_ON) +#define DDL_PRINT_ENABLE (DDL_ON) + +#define DDL_ADC_ENABLE (DDL_OFF) +#define DDL_AES_ENABLE (DDL_OFF) +#define DDL_CAN_ENABLE (DDL_OFF) +#define DDL_CLK_ENABLE (DDL_ON) +#define DDL_CMP_ENABLE (DDL_OFF) +#define DDL_CRC_ENABLE (DDL_OFF) +#define DDL_DCU_ENABLE (DDL_OFF) +#define DDL_DMAC_ENABLE (DDL_ON) +#define DDL_EFM_ENABLE (DDL_ON) +#define DDL_EMB_ENABLE (DDL_OFF) +#define DDL_EVENT_PORT_ENABLE (DDL_OFF) +#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON) +#define DDL_GPIO_ENABLE (DDL_ON) +#define DDL_HASH_ENABLE (DDL_OFF) +#define DDL_I2C_ENABLE (DDL_OFF) +#define DDL_I2S_ENABLE (DDL_OFF) +#define DDL_INTERRUPTS_ENABLE (DDL_ON) +#define DDL_KEYSCAN_ENABLE (DDL_OFF) +#define DDL_MPU_ENABLE (DDL_OFF) +#define DDL_OTS_ENABLE (DDL_OFF) +#define DDL_PWC_ENABLE (DDL_ON) +#define DDL_QSPI_ENABLE (DDL_OFF) +#define DDL_RMU_ENABLE (DDL_OFF) +#define DDL_RTC_ENABLE (DDL_OFF) +#define DDL_SDIOC_ENABLE (DDL_OFF) +#define DDL_SPI_ENABLE (DDL_OFF) +#define DDL_SRAM_ENABLE (DDL_ON) +#define DDL_SWDT_ENABLE (DDL_OFF) +#define DDL_TIMER0_ENABLE (DDL_ON) +#define DDL_TIMER4_CNT_ENABLE (DDL_OFF) +#define DDL_TIMER4_EMB_ENABLE (DDL_OFF) +#define DDL_TIMER4_OCO_ENABLE (DDL_OFF) +#define DDL_TIMER4_PWM_ENABLE (DDL_OFF) +#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF) +#define DDL_TIMER6_ENABLE (DDL_OFF) +#define DDL_TIMERA_ENABLE (DDL_OFF) +#define DDL_TRNG_ENABLE (DDL_OFF) +#define DDL_USART_ENABLE (DDL_ON) +#define DDL_USBFS_ENABLE (DDL_OFF) +#define DDL_WDT_ENABLE (DDL_OFF) + + +/*! Midware module on-off define */ +#define MW_ON (1u) +#define MW_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of Midware modules to use + ** Select the modules you need to use to MW_ON. + ******************************************************************************/ +#define MW_SD_CARD_ENABLE (MW_OFF) +#define MW_FS_ENABLE (MW_OFF) +#define MW_W25QXX_ENABLE (MW_OFF) +#define MW_WM8731_ENABLE (MW_OFF) + +/* BSP on-off define */ +#define BSP_ON (1u) +#define BSP_OFF (0u) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F460_LQFP100_V1 (1u) +#define BSP_EV_HC32F460_LQFP100_V2 (2u) + +/** + * @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to BSP_EV_HC32F460. + */ +#define BSP_EV_HC32F460 (BSP_EV_HC32F460) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // DdlConfigGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_CONFIG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h new file mode 100644 index 000000000..6de31bc85 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h @@ -0,0 +1,234 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_common.h + ** + ** A detailed description is available at + ** @link Hc32CommonGroup Hc32 Series Comm Part description @endlink + ** + ** - 2018-10-18 CDT First version for Hc32 Series of common part. + ** + ******************************************************************************/ +#ifndef __HC32_COMMON_H__ +#define __HC32_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32CommonGroup Hc32 Series Common Part(HC32COMMON) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief single precision floating point number (4 byte) + ******************************************************************************/ +typedef float float32_t; + +/** + ******************************************************************************* + ** \brief double precision floating point number (8 byte) + ******************************************************************************/ +typedef double float64_t; + +/** + ******************************************************************************* + ** \brief function pointer type to void/void function + ******************************************************************************/ +typedef void (*func_ptr_t)(void); + +/** + ******************************************************************************* + ** \brief function pointer type to void/uint8_t function + ******************************************************************************/ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** + ******************************************************************************* + ** \brief functional state + ******************************************************************************/ +typedef enum en_functional_state +{ + Disable = 0u, + Enable = 1u, +} en_functional_state_t; + +/** + ******************************************************************************* + ** \brief flag status + ******************************************************************************/ +typedef enum en_flag_status +{ + Reset = 0u, + Set = 1u, +} en_flag_status_t, en_int_status_t; + +/** + ******************************************************************************* + ** \brief generic error codes + ******************************************************************************/ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u, ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Device include + ******************************************************************************/ +#if defined(HC32F460) +#include "hc32f460.h" +#include "system_hc32f460.h" +#elif defined(HC32xxxx) +#include "hc32xxxx.h" +#include "system_hc32xxxx.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/*! Weak and Align compiler definition */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __attribute__((aligned (4))) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif /* __UNUSED */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) + /* Usage: void __RAM_FUNC foo(void) */ + #endif /* __RAM_FUNC */ +#elif defined (__ICCARM__) ///< IAR Compiler +#define __WEAKDEF __weak +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#define __NOINLINE _Pragma("optimize = no_inline") +#define __UNUSED __attribute__((unused)) +#define __RAM_FUNC __ramfunc +#elif defined (__CC_ARM) ///< ARM Compiler +#define __WEAKDEF __attribute__((weak)) +#define __ALIGN_BEGIN __align(4) +#define __NOINLINE __attribute__((noinline)) +#define __UNUSED __attribute__((unused)) +/* RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. */ +#define __RAM_FUNC +#else +#error "unsupported compiler!!" +#endif /* __GNUC__ */ + +/*! Pointer correspond to zero value */ +#if !defined (NULL) +#define NULL (0) +#endif + +/*! Memory clear */ +#define MEM_ZERO_STRUCT(x) do { \ + memset((void*)&(x), 0l, (sizeof(x))); \ + }while(0) + +/*! Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10u) << 4u) + ((x) % 10u)) + +/*! BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4u) * 10u) + ((x) & 0x0Fu)) + +/*! Returns the minimum value out of two values */ +#define MIN(x, y) ((x) < (y) ? (x) : (y)) + +/*! Returns the maximum value out of two values */ +#define MAX(x, y) ((x) > (y) ? (x) : (y)) + +/*! Returns the dimension of an array */ +#define ARRAY_SZ(X) (sizeof((X)) / sizeof((X)[0])) + +/*! Check if it is a functional state */ +#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable)) + +#define BIT_SET(value,bit) ((value) |= (bit)) + +#define BIT_CLEAR(value,bit) ((value) &= ~(bit)) + +#define BIT_READ(value,bit) ((value) & (bit)) + +#define BIT_VALUE(index) (1ul << (index)) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK))))) +#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK))))) +#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK))))) + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32CommonGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h new file mode 100644 index 000000000..4a9a1228f --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h @@ -0,0 +1,262 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_ddl.h + ** + ** A detailed description is available at + ** @link Hc32DdlGroup Hc32 Series Ddl description @endlink + ** + ** - 2018-9-28 CDT First version for Hc32 Series Device Driver + ** Library. + ** + ******************************************************************************/ +#ifndef __HC32_DDL_H__ +#define __HC32_DDL_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32DdlGroup Hc32 Series Device Driver Library(HC32DDL) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Defined use device driver library */ +#if !defined (USE_DEVICE_DRIVER_LIB) +/** + ******************************************************************************* + ** \brief Comment the line below if you will not use the device driver library. + ** In this case, the application code will be based on direct access to + ** peripherals registers. + ******************************************************************************/ + /* #define USE_DEVICE_DRIVER_LIB */ +#endif /* USE_DEVICE_DRIVER_LIB */ + +/** + ******************************************************************************* + ** \brief Hc32 Series device driver library version number v1.0.0 + ******************************************************************************/ +#define HC32_DDL_VERSION_MAIN 0x01u ///< [31:24] main version +#define HC32_DDL_VERSION_SUB1 0x00u ///< [23:16] sub1 version +#define HC32_DDL_VERSION_SUB2 0x00u ///< [15:8] sub2 version +#define HC32_DDL_VERSION_RC 0x00u ///< [7:0] release candidate +#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \ + (HC32_DDL_VERSION_SUB1 << 16) | \ + (HC32_DDL_VERSION_SUB2 << 8 ) | \ + (HC32_DDL_VERSION_RC)) + +/*! Use device driver library */ +#if defined (USE_DEVICE_DRIVER_LIB) +/** + ******************************************************************************* + ** \brief Include module's header file + ******************************************************************************/ +#if (DDL_ADC_ENABLE == DDL_ON) +#include "hc32f460_adc.h" +#endif /* DDL_ADC_ENABLE */ + +#if (DDL_AES_ENABLE == DDL_ON) +#include "hc32f460_aes.h" +#endif /* DDL_AES_ENABLE */ + +#if (DDL_CAN_ENABLE == DDL_ON) +#include "hc32f460_can.h" +#endif /* DDL_CAN_ENABLE */ + +#if (DDL_CMP_ENABLE == DDL_ON) +#include "hc32f460_cmp.h" +#endif /* DDL_CMP_ENABLE */ + +#if (DDL_CLK_ENABLE == DDL_ON) +#include "hc32f460_clk.h" +#endif /* DDL_CLK_ENABLE */ + +#if (DDL_DCU_ENABLE == DDL_ON) +#include "hc32f460_dcu.h" +#endif /* DDL_DCU_ENABLE */ + +#if (DDL_DMAC_ENABLE == DDL_ON) +#include "hc32f460_dmac.h" +#endif /* DDL_DMAC_ENABLE */ + +#if (DDL_EFM_ENABLE == DDL_ON) +#include "hc32f460_efm.h" +#endif /* DDL_EFM_ENABLE */ + +#if (DDL_EMB_ENABLE == DDL_ON) +#include "hc32f460_emb.h" +#endif /* DDL_EMB_ENABLE */ + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) +#include "hc32f460_exint_nmi_swi.h" +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +#if (DDL_GPIO_ENABLE == DDL_ON) +#include "hc32f460_gpio.h" +#endif /* DDL_GPIO_ENABLE */ + +#if (DDL_HASH_ENABLE == DDL_ON) +#include "hc32f460_hash.h" +#endif /* DDL_HASH_ENABLE */ + +#if (DDL_I2C_ENABLE == DDL_ON) +#include "hc32f460_i2c.h" +#endif /* DDL_I2C_ENABLE */ + +#if (DDL_I2S_ENABLE == DDL_ON) +#include "hc32f460_i2s.h" +#endif /* DDL_I2S_ENABLE */ + +#if (DDL_ICG_ENABLE == DDL_ON) +#include "hc32f460_icg.h" +#endif /* DDL_ICG_ENABLE */ + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32f460_interrupts.h" +#endif /* DDL_INTERRUPTS_ENABLE */ + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32f460_keyscan.h" +#endif /* DDL_KEYSCAN_ENABLE */ + +#if (DDL_MPU_ENABLE == DDL_ON) +#include "hc32f460_mpu.h" +#endif /* DDL_MPU_ENABLE */ + +#if (DDL_OTS_ENABLE == DDL_ON) +#include "hc32f460_ots.h" +#endif /* DDL_OTS_ENABLE */ + +#if (DDL_PGA_ENABLE == DDL_ON) +#include "hc32f460_pga.h" +#endif /* DDL_PGA_ENABLE */ + +#if (DDL_PWC_ENABLE == DDL_ON) +#include "hc32f460_pwc.h" +#endif /* DDL_PWC_ENABLE */ + +#if (DDL_QSPI_ENABLE == DDL_ON) +#include "hc32f460_qspi.h" +#endif /* DDL_QSPI_ENABLE */ + +#if (DDL_RMU_ENABLE == DDL_ON) +#include "hc32f460_rmu.h" +#endif /* DDL_RMU_ENABLE */ + +#if (DDL_RTC_ENABLE == DDL_ON) +#include "hc32f460_rtc.h" +#endif /* DDL_RTC_ENABLE */ + +#if (DDL_SDIOC_ENABLE == DDL_ON) +#include "hc32f460_sdioc.h" +#endif /* DDL_SDIOC_ENABLE */ + +#if (DDL_SPI_ENABLE == DDL_ON) +#include "hc32f460_spi.h" +#endif /* DDL_SPI_ENABLE */ + +#if (DDL_SRAM_ENABLE == DDL_ON) +#include "hc32f460_sram.h" +#endif /* DDL_SRAM_ENABLE */ + +#if (DDL_SWDT_ENABLE == DDL_ON) +#include "hc32f460_swdt.h" +#endif /* DDL_SWDT_ENABLE */ + +#if (DDL_TIMER0_ENABLE == DDL_ON) +#include "hc32f460_timer0.h" +#endif /* DDL_TIMER0_ENABLE */ + +#if (DDL_TIMER4_CNT_ENABLE == DDL_ON) +#include "hc32f460_timer4_cnt.h" +#endif /* DDL_TIMER4_CNT_ENABLE */ + +#if (DDL_TIMER4_EMB_ENABLE == DDL_ON) +#include "hc32f460_timer4_emb.h" +#endif /* DDL_TIMER4_EMB_ENABLE */ + +#if (DDL_TIMER4_OCO_ENABLE == DDL_ON) +#include "hc32f460_timer4_oco.h" +#endif /* DDL_TIMER4_OCO_ENABLE */ + +#if (DDL_TIMER4_PWM_ENABLE == DDL_ON) +#include "hc32f460_timer4_pwm.h" +#endif /* DDL_TIMER4_PWM_ENABLE */ + +#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON) +#include "hc32f460_timer4_sevt.h" +#endif /* DDL_TIMER4_SEVT_ENABLE */ + +#if (DDL_TIMER6_ENABLE == DDL_ON) +#include "hc32f460_timer6.h" +#endif /* DDL_TIMER6_ENABLE */ + +#if (DDL_TIMERA_ENABLE == DDL_ON) +#include "hc32f460_timera.h" +#endif /* DDL_TIMERA_ENABLE */ + +#if (DDL_TRNG_ENABLE == DDL_ON) +#include "hc32f460_trng.h" +#endif /* DDL_TRNG_ENABLE */ + +#if (DDL_USART_ENABLE == DDL_ON) +#include "hc32f460_usart.h" +#endif /* DDL_USART_ENABLE */ + +#if (DDL_USBFS_ENABLE == DDL_ON) +#include "hc32f460_usbfs.h" +#endif /* DDL_USBFS_ENABLE */ + +#if (DDL_UTILITY_ENABLE == DDL_ON) +#include "hc32f460_utility.h" +#endif /* DDL_UTILITY_ENABLE */ + +#if (DDL_WDT_ENABLE == DDL_ON) +#include "hc32f460_wdt.h" +#endif /* DDL_WDT_ENABLE */ + +#endif /* USE_DEVICE_DRIVER_LIB */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32DdlGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h new file mode 100644 index 000000000..a62c8418e --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h @@ -0,0 +1,30601 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file HC32F460.h + ** + ** Auto generate. + ** Headerfile for HC32F460 series MCU + ** + ** History: + ** + ** - 2020-12-16 1.03 First version for Device Driver Library of HC32F460 series MCU. + ** + ******************************************************************************/ + +#ifndef __HC32F460_H__ +#define __HC32F460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< HC32F460 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DM_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + Int000_IRQn = 0, + Int001_IRQn = 1, + Int002_IRQn = 2, + Int003_IRQn = 3, + Int004_IRQn = 4, + Int005_IRQn = 5, + Int006_IRQn = 6, + Int007_IRQn = 7, + Int008_IRQn = 8, + Int009_IRQn = 9, + Int010_IRQn = 10, + Int011_IRQn = 11, + Int012_IRQn = 12, + Int013_IRQn = 13, + Int014_IRQn = 14, + Int015_IRQn = 15, + Int016_IRQn = 16, + Int017_IRQn = 17, + Int018_IRQn = 18, + Int019_IRQn = 19, + Int020_IRQn = 20, + Int021_IRQn = 21, + Int022_IRQn = 22, + Int023_IRQn = 23, + Int024_IRQn = 24, + Int025_IRQn = 25, + Int026_IRQn = 26, + Int027_IRQn = 27, + Int028_IRQn = 28, + Int029_IRQn = 29, + Int030_IRQn = 30, + Int031_IRQn = 31, + Int032_IRQn = 32, + Int033_IRQn = 33, + Int034_IRQn = 34, + Int035_IRQn = 35, + Int036_IRQn = 36, + Int037_IRQn = 37, + Int038_IRQn = 38, + Int039_IRQn = 39, + Int040_IRQn = 40, + Int041_IRQn = 41, + Int042_IRQn = 42, + Int043_IRQn = 43, + Int044_IRQn = 44, + Int045_IRQn = 45, + Int046_IRQn = 46, + Int047_IRQn = 47, + Int048_IRQn = 48, + Int049_IRQn = 49, + Int050_IRQn = 50, + Int051_IRQn = 51, + Int052_IRQn = 52, + Int053_IRQn = 53, + Int054_IRQn = 54, + Int055_IRQn = 55, + Int056_IRQn = 56, + Int057_IRQn = 57, + Int058_IRQn = 58, + Int059_IRQn = 59, + Int060_IRQn = 60, + Int061_IRQn = 61, + Int062_IRQn = 62, + Int063_IRQn = 63, + Int064_IRQn = 64, + Int065_IRQn = 65, + Int066_IRQn = 66, + Int067_IRQn = 67, + Int068_IRQn = 68, + Int069_IRQn = 69, + Int070_IRQn = 70, + Int071_IRQn = 71, + Int072_IRQn = 72, + Int073_IRQn = 73, + Int074_IRQn = 74, + Int075_IRQn = 75, + Int076_IRQn = 76, + Int077_IRQn = 77, + Int078_IRQn = 78, + Int079_IRQn = 79, + Int080_IRQn = 80, + Int081_IRQn = 81, + Int082_IRQn = 82, + Int083_IRQn = 83, + Int084_IRQn = 84, + Int085_IRQn = 85, + Int086_IRQn = 86, + Int087_IRQn = 87, + Int088_IRQn = 88, + Int089_IRQn = 89, + Int090_IRQn = 90, + Int091_IRQn = 91, + Int092_IRQn = 92, + Int093_IRQn = 93, + Int094_IRQn = 94, + Int095_IRQn = 95, + Int096_IRQn = 96, + Int097_IRQn = 97, + Int098_IRQn = 98, + Int099_IRQn = 99, + Int100_IRQn = 100, + Int101_IRQn = 101, + Int102_IRQn = 102, + Int103_IRQn = 103, + Int104_IRQn = 104, + Int105_IRQn = 105, + Int106_IRQn = 106, + Int107_IRQn = 107, + Int108_IRQn = 108, + Int109_IRQn = 109, + Int110_IRQn = 110, + Int111_IRQn = 111, + Int112_IRQn = 112, + Int113_IRQn = 113, + Int114_IRQn = 114, + Int115_IRQn = 115, + Int116_IRQn = 116, + Int117_IRQn = 117, + Int118_IRQn = 118, + Int119_IRQn = 119, + Int120_IRQn = 120, + Int121_IRQn = 121, + Int122_IRQn = 122, + Int123_IRQn = 123, + Int124_IRQn = 124, + Int125_IRQn = 125, + Int126_IRQn = 126, + Int127_IRQn = 127, + Int128_IRQn = 128, + Int129_IRQn = 129, + Int130_IRQn = 130, + Int131_IRQn = 131, + Int132_IRQn = 132, + Int133_IRQn = 133, + Int134_IRQn = 134, + Int135_IRQn = 135, + Int136_IRQn = 136, + Int137_IRQn = 137, + Int138_IRQn = 138, + Int139_IRQn = 139, + Int140_IRQn = 140, + Int141_IRQn = 141, + Int142_IRQn = 142, + Int143_IRQn = 143, + +}IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum en_event_src +{ + EVT_SWI_IRQ0 = 0u, + EVT_SWI_IRQ1 = 1u, + EVT_SWI_IRQ2 = 2u, + EVT_SWI_IRQ3 = 3u, + EVT_SWI_IRQ4 = 4u, + EVT_SWI_IRQ5 = 5u, + EVT_SWI_IRQ6 = 6u, + EVT_SWI_IRQ7 = 7u, + EVT_SWI_IRQ8 = 8u, + EVT_SWI_IRQ9 = 9u, + EVT_SWI_IRQ10 = 10u, + EVT_SWI_IRQ11 = 11u, + EVT_SWI_IRQ12 = 12u, + EVT_SWI_IRQ13 = 13u, + EVT_SWI_IRQ14 = 14u, + EVT_SWI_IRQ15 = 15u, + EVT_SWI_IRQ16 = 16u, + EVT_SWI_IRQ17 = 17u, + EVT_SWI_IRQ18 = 18u, + EVT_SWI_IRQ19 = 19u, + EVT_SWI_IRQ20 = 20u, + EVT_SWI_IRQ21 = 21u, + EVT_SWI_IRQ22 = 22u, + EVT_SWI_IRQ23 = 23u, + EVT_SWI_IRQ24 = 24u, + EVT_SWI_IRQ25 = 25u, + EVT_SWI_IRQ26 = 26u, + EVT_SWI_IRQ27 = 27u, + EVT_SWI_IRQ28 = 28u, + EVT_SWI_IRQ29 = 29u, + EVT_SWI_IRQ30 = 30u, + EVT_SWI_IRQ31 = 31u, + + /* External Interrupt. */ + EVT_PORT_EIRQ0 = 0u, + EVT_PORT_EIRQ1 = 1u, + EVT_PORT_EIRQ2 = 2u, + EVT_PORT_EIRQ3 = 3u, + EVT_PORT_EIRQ4 = 4u, + EVT_PORT_EIRQ5 = 5u, + EVT_PORT_EIRQ6 = 6u, + EVT_PORT_EIRQ7 = 7u, + EVT_PORT_EIRQ8 = 8u, + EVT_PORT_EIRQ9 = 9u, + EVT_PORT_EIRQ10 = 10u, + EVT_PORT_EIRQ11 = 11u, + EVT_PORT_EIRQ12 = 12u, + EVT_PORT_EIRQ13 = 13u, + EVT_PORT_EIRQ14 = 14u, + EVT_PORT_EIRQ15 = 15u, + + /* DMAC */ + EVT_DMA1_TC0 = 32u, + EVT_DMA1_TC1 = 33u, + EVT_DMA1_TC2 = 34u, + EVT_DMA1_TC3 = 35u, + EVT_DMA2_TC0 = 36u, + EVT_DMA2_TC1 = 37u, + EVT_DMA2_TC2 = 38u, + EVT_DMA2_TC3 = 39u, + EVT_DMA1_BTC0 = 40u, + EVT_DMA1_BTC1 = 41u, + EVT_DMA1_BTC2 = 42u, + EVT_DMA1_BTC3 = 43u, + EVT_DMA2_BTC0 = 44u, + EVT_DMA2_BTC1 = 45u, + EVT_DMA2_BTC2 = 46u, + EVT_DMA2_BTC3 = 47u, + + /* EFM */ + EVT_EFM_OPTEND = 52u, + + /* USB SOF */ + EVT_USBFS_SOF = 53u, + + /* DCU */ + EVT_DCU1 = 55u, + EVT_DCU2 = 56u, + EVT_DCU3 = 57u, + EVT_DCU4 = 58u, + + /* TIMER 0 */ + EVT_TMR01_GCMA = 64u, + EVT_TMR01_GCMB = 65u, + EVT_TMR02_GCMA = 66u, + EVT_TMR02_GCMB = 67u, + + /* RTC */ + EVT_RTC_ALM = 81u, + EVT_RTC_PRD = 82u, + + /* TIMER 6 */ + EVT_TMR61_GCMA = 96u, + EVT_TMR61_GCMB = 97u, + EVT_TMR61_GCMC = 98u, + EVT_TMR61_GCMD = 99u, + EVT_TMR61_GCME = 100u, + EVT_TMR61_GCMF = 101u, + EVT_TMR61_GOVF = 102u, + EVT_TMR61_GUDF = 103u, + EVT_TMR61_SCMA = 107u, + EVT_TMR61_SCMB = 108u, + EVT_TMR62_GCMA = 112u, + EVT_TMR62_GCMB = 113u, + EVT_TMR62_GCMC = 114u, + EVT_TMR62_GCMD = 115u, + EVT_TMR62_GCME = 116u, + EVT_TMR62_GCMF = 117u, + EVT_TMR62_GOVF = 118u, + EVT_TMR62_GUDF = 119u, + EVT_TMR62_SCMA = 123u, + EVT_TMR62_SCMB = 124u, + EVT_TMR63_GCMA = 128u, + EVT_TMR63_GCMB = 129u, + EVT_TMR63_GCMC = 130u, + EVT_TMR63_GCMD = 131u, + EVT_TMR63_GCME = 132u, + EVT_TMR63_GCMF = 133u, + EVT_TMR63_GOVF = 134u, + EVT_TMR63_GUDF = 135u, + EVT_TMR63_SCMA = 139u, + EVT_TMR63_SCMB = 140u, + + /* TIMER A */ + EVT_TMRA1_OVF = 256u, + EVT_TMRA1_UDF = 257u, + EVT_TMRA1_CMP = 258u, + EVT_TMRA2_OVF = 259u, + EVT_TMRA2_UDF = 260u, + EVT_TMRA2_CMP = 261u, + EVT_TMRA3_OVF = 262u, + EVT_TMRA3_UDF = 263u, + EVT_TMRA3_CMP = 264u, + EVT_TMRA4_OVF = 265u, + EVT_TMRA4_UDF = 266u, + EVT_TMRA4_CMP = 267u, + EVT_TMRA5_OVF = 268u, + EVT_TMRA5_UDF = 269u, + EVT_TMRA5_CMP = 270u, + EVT_TMRA6_OVF = 272u, + EVT_TMRA6_UDF = 273u, + EVT_TMRA6_CMP = 274u, + + /* USART */ + EVT_USART1_EI = 278u, + EVT_USART1_RI = 279u, + EVT_USART1_TI = 280u, + EVT_USART1_TCI = 281u, + EVT_USART1_RTO = 282u, + EVT_USART2_EI = 283u, + EVT_USART2_RI = 284u, + EVT_USART2_TI = 285u, + EVT_USART2_TCI = 286u, + EVT_USART2_RTO = 287u, + EVT_USART3_EI = 288u, + EVT_USART3_RI = 289u, + EVT_USART3_TI = 290u, + EVT_USART3_TCI = 291u, + EVT_USART3_RTO = 292u, + EVT_USART4_EI = 293u, + EVT_USART4_RI = 294u, + EVT_USART4_TI = 295u, + EVT_USART4_TCI = 296u, + EVT_USART4_RTO = 297u, + + /* SPI */ + EVT_SPI1_SPRI = 299u, + EVT_SPI1_SPTI = 300u, + EVT_SPI1_SPII = 301u, + EVT_SPI1_SPEI = 302u, + EVT_SPI1_SPTEND = 303u, + EVT_SPI2_SPRI = 304u, + EVT_SPI2_SPTI = 305u, + EVT_SPI2_SPII = 306u, + EVT_SPI2_SPEI = 307u, + EVT_SPI2_SPTEND = 308u, + EVT_SPI3_SPRI = 309u, + EVT_SPI3_SPTI = 310u, + EVT_SPI3_SPII = 311u, + EVT_SPI3_SPEI = 312u, + EVT_SPI3_SPTEND = 313u, + EVT_SPI4_SPRI = 314u, + EVT_SPI4_SPTI = 315u, + EVT_SPI4_SPII = 316u, + EVT_SPI4_SPEI = 317u, + EVT_SPI4_SPTEND = 318u, + + /* AOS */ + EVT_AOS_STRG = 319u, + + /* TIMER 4 */ + EVT_TMR41_SCMUH = 368u, + EVT_TMR41_SCMUL = 369u, + EVT_TMR41_SCMVH = 370u, + EVT_TMR41_SCMVL = 371u, + EVT_TMR41_SCMWH = 372u, + EVT_TMR41_SCMWL = 373u, + EVT_TMR42_SCMUH = 374u, + EVT_TMR42_SCMUL = 375u, + EVT_TMR42_SCMVH = 376u, + EVT_TMR42_SCMVL = 377u, + EVT_TMR42_SCMWH = 378u, + EVT_TMR42_SCMWL = 379u, + EVT_TMR43_SCMUH = 384u, + EVT_TMR43_SCMUL = 385u, + EVT_TMR43_SCMVH = 386u, + EVT_TMR43_SCMVL = 387u, + EVT_TMR43_SCMWH = 388u, + EVT_TMR43_SCMWL = 389u, + + /* EVENT PORT */ + EVT_EVENT_PORT1 = 394u, + EVT_EVENT_PORT2 = 395u, + EVT_EVENT_PORT3 = 396u, + EVT_EVENT_PORT4 = 397u, + + /* I2S */ + EVT_I2S1_TXIRQOUT = 400u, + EVT_I2S1_RXIRQOUT = 401u, + EVT_I2S2_TXIRQOUT = 403u, + EVT_I2S2_RXIRQOUT = 404u, + EVT_I2S3_TXIRQOUT = 406u, + EVT_I2S3_RXIRQOUT = 407u, + EVT_I2S4_TXIRQOUT = 409u, + EVT_I2S4_RXIRQOUT = 410u, + + /* COMPARATOR */ + EVT_ACMP1 = 416u, + EVT_ACMP2 = 417u, + EVT_ACMP3 = 418u, + + /* I2C */ + EVT_I2C1_RXI = 420u, + EVT_I2C1_TXI = 421u, + EVT_I2C1_TEI = 422u, + EVT_I2C1_EEI = 423u, + EVT_I2C2_RXI = 424u, + EVT_I2C2_TXI = 425u, + EVT_I2C2_TEI = 426u, + EVT_I2C2_EEI = 427u, + EVT_I2C3_RXI = 428u, + EVT_I2C3_TXI = 429u, + EVT_I2C3_TEI = 430u, + EVT_I2C3_EEI = 431u, + + /* PVD */ + EVT_PVD_PVD1 = 433u, + EVT_PVD_PVD2 = 434u, + + /* OTS */ + EVT_OTS = 435u, + + /* WDT */ + EVT_WDT_REFUDF = 439u, + + /* ADC */ + EVT_ADC1_EOCA = 448u, + EVT_ADC1_EOCB = 449u, + EVT_ADC1_CHCMP = 450u, + EVT_ADC1_SEQCMP = 451u, + EVT_ADC2_EOCA = 452u, + EVT_ADC2_EOCB = 453u, + EVT_ADC2_CHCMP = 454u, + EVT_ADC2_SEQCMP = 455u, + + /* TRNG */ + EVT_TRNG_END = 456u, + + /* SDIO */ + EVT_SDIOC1_DMAR = 480u, + EVT_SDIOC1_DMAW = 481u, + EVT_SDIOC2_DMAR = 483u, + EVT_SDIOC2_DMAW = 484u, + EVT_MAX = 511u, +}en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum en_int_src +{ + INT_SWI_IRQ0 = 0u, + INT_SWI_IRQ1 = 1u, + INT_SWI_IRQ2 = 2u, + INT_SWI_IRQ3 = 3u, + INT_SWI_IRQ4 = 4u, + INT_SWI_IRQ5 = 5u, + INT_SWI_IRQ6 = 6u, + INT_SWI_IRQ7 = 7u, + INT_SWI_IRQ8 = 8u, + INT_SWI_IRQ9 = 9u, + INT_SWI_IRQ10 = 10u, + INT_SWI_IRQ11 = 11u, + INT_SWI_IRQ12 = 12u, + INT_SWI_IRQ13 = 13u, + INT_SWI_IRQ14 = 14u, + INT_SWI_IRQ15 = 15u, + INT_SWI_IRQ16 = 16u, + INT_SWI_IRQ17 = 17u, + INT_SWI_IRQ18 = 18u, + INT_SWI_IRQ19 = 19u, + INT_SWI_IRQ20 = 20u, + INT_SWI_IRQ21 = 21u, + INT_SWI_IRQ22 = 22u, + INT_SWI_IRQ23 = 23u, + INT_SWI_IRQ24 = 24u, + INT_SWI_IRQ25 = 25u, + INT_SWI_IRQ26 = 26u, + INT_SWI_IRQ27 = 27u, + INT_SWI_IRQ28 = 28u, + INT_SWI_IRQ29 = 29u, + INT_SWI_IRQ30 = 30u, + INT_SWI_IRQ31 = 31u, + + /* External Interrupt. */ + INT_PORT_EIRQ0 = 0u, + INT_PORT_EIRQ1 = 1u, + INT_PORT_EIRQ2 = 2u, + INT_PORT_EIRQ3 = 3u, + INT_PORT_EIRQ4 = 4u, + INT_PORT_EIRQ5 = 5u, + INT_PORT_EIRQ6 = 6u, + INT_PORT_EIRQ7 = 7u, + INT_PORT_EIRQ8 = 8u, + INT_PORT_EIRQ9 = 9u, + INT_PORT_EIRQ10 = 10u, + INT_PORT_EIRQ11 = 11u, + INT_PORT_EIRQ12 = 12u, + INT_PORT_EIRQ13 = 13u, + INT_PORT_EIRQ14 = 14u, + INT_PORT_EIRQ15 = 15u, + + /* DMAC */ + INT_DMA1_TC0 = 32u, + INT_DMA1_TC1 = 33u, + INT_DMA1_TC2 = 34u, + INT_DMA1_TC3 = 35u, + INT_DMA2_TC0 = 36u, + INT_DMA2_TC1 = 37u, + INT_DMA2_TC2 = 38u, + INT_DMA2_TC3 = 39u, + INT_DMA1_BTC0 = 40u, + INT_DMA1_BTC1 = 41u, + INT_DMA1_BTC2 = 42u, + INT_DMA1_BTC3 = 43u, + INT_DMA2_BTC0 = 44u, + INT_DMA2_BTC1 = 45u, + INT_DMA2_BTC2 = 46u, + INT_DMA2_BTC3 = 47u, + INT_DMA1_ERR = 48u, + INT_DMA2_ERR = 49u, + + /* EFM */ + INT_EFM_PEERR = 50u, + INT_EFM_COLERR = 51u, + INT_EFM_OPTEND = 52u, + + /* QSPI */ + INT_QSPI_INTR = 54u, + + /* DCU */ + INT_DCU1 = 55u, + INT_DCU2 = 56u, + INT_DCU3 = 57u, + INT_DCU4 = 58u, + + /* TIMER 0 */ + INT_TMR01_GCMA = 64u, + INT_TMR01_GCMB = 65u, + INT_TMR02_GCMA = 66u, + INT_TMR02_GCMB = 67u, + + /* RTC */ + INT_RTC_ALM = 81u, + INT_RTC_PRD = 82u, + + /* XTAL32 stop */ + INT_XTAL32_STOP = 84u, + + /* XTAL stop */ + INT_XTAL_STOP = 85u, + + /* wake-up timer */ + INT_WKTM_PRD = 86u, + + /* SWDT */ + INT_SWDT_REFUDF = 87u, + + /* TIMER 6 */ + INT_TMR61_GCMA = 96u, + INT_TMR61_GCMB = 97u, + INT_TMR61_GCMC = 98u, + INT_TMR61_GCMD = 99u, + INT_TMR61_GCME = 100u, + INT_TMR61_GCMF = 101u, + INT_TMR61_GOVF = 102u, + INT_TMR61_GUDF = 103u, + INT_TMR61_GDTE = 104u, + INT_TMR61_SCMA = 107u, + INT_TMR61_SCMB = 108u, + INT_TMR62_GCMA = 112u, + INT_TMR62_GCMB = 113u, + INT_TMR62_GCMC = 114u, + INT_TMR62_GCMD = 115u, + INT_TMR62_GCME = 116u, + INT_TMR62_GCMF = 117u, + INT_TMR62_GOVF = 118u, + INT_TMR62_GUDF = 119u, + INT_TMR62_GDTE = 120u, + INT_TMR62_SCMA = 123u, + INT_TMR62_SCMB = 124u, + INT_TMR63_GCMA = 128u, + INT_TMR63_GCMB = 129u, + INT_TMR63_GCMC = 130u, + INT_TMR63_GCMD = 131u, + INT_TMR63_GCME = 132u, + INT_TMR63_GCMF = 133u, + INT_TMR63_GOVF = 134u, + INT_TMR63_GUDF = 135u, + INT_TMR63_GDTE = 136u, + INT_TMR63_SCMA = 139u, + INT_TMR63_SCMB = 140u, + + /* TIMER A */ + INT_TMRA1_OVF = 256u, + INT_TMRA1_UDF = 257u, + INT_TMRA1_CMP = 258u, + INT_TMRA2_OVF = 259u, + INT_TMRA2_UDF = 260u, + INT_TMRA2_CMP = 261u, + INT_TMRA3_OVF = 262u, + INT_TMRA3_UDF = 263u, + INT_TMRA3_CMP = 264u, + INT_TMRA4_OVF = 265u, + INT_TMRA4_UDF = 266u, + INT_TMRA4_CMP = 267u, + INT_TMRA5_OVF = 268u, + INT_TMRA5_UDF = 269u, + INT_TMRA5_CMP = 270u, + INT_TMRA6_OVF = 272u, + INT_TMRA6_UDF = 273u, + INT_TMRA6_CMP = 274u, + + /* USB FS */ + INT_USBFS_GLB = 275u, + + /* USRAT */ + INT_USART1_EI = 278u, + INT_USART1_RI = 279u, + INT_USART1_TI = 280u, + INT_USART1_TCI = 281u, + INT_USART1_RTO = 282u, + INT_USART1_WUPI = 432u, + INT_USART2_EI = 283u, + INT_USART2_RI = 284u, + INT_USART2_TI = 285u, + INT_USART2_TCI = 286u, + INT_USART2_RTO = 287u, + INT_USART3_EI = 288u, + INT_USART3_RI = 289u, + INT_USART3_TI = 290u, + INT_USART3_TCI = 291u, + INT_USART3_RTO = 292u, + INT_USART4_EI = 293u, + INT_USART4_RI = 294u, + INT_USART4_TI = 295u, + INT_USART4_TCI = 296u, + INT_USART4_RTO = 297u, + + /* SPI */ + INT_SPI1_SPRI = 299u, + INT_SPI1_SPTI = 300u, + INT_SPI1_SPII = 301u, + INT_SPI1_SPEI = 302u, + INT_SPI2_SPRI = 304u, + INT_SPI2_SPTI = 305u, + INT_SPI2_SPII = 306u, + INT_SPI2_SPEI = 307u, + INT_SPI3_SPRI = 309u, + INT_SPI3_SPTI = 310u, + INT_SPI3_SPII = 311u, + INT_SPI3_SPEI = 312u, + INT_SPI4_SPRI = 314u, + INT_SPI4_SPTI = 315u, + INT_SPI4_SPII = 316u, + INT_SPI4_SPEI = 317u, + + /* TIMER 4 */ + INT_TMR41_GCMUH = 320u, + INT_TMR41_GCMUL = 321u, + INT_TMR41_GCMVH = 322u, + INT_TMR41_GCMVL = 323u, + INT_TMR41_GCMWH = 324u, + INT_TMR41_GCMWL = 325u, + INT_TMR41_GOVF = 326u, + INT_TMR41_GUDF = 327u, + INT_TMR41_RLOU = 328u, + INT_TMR41_RLOV = 329u, + INT_TMR41_RLOW = 330u, + INT_TMR42_GCMUH = 336u, + INT_TMR42_GCMUL = 337u, + INT_TMR42_GCMVH = 338u, + INT_TMR42_GCMVL = 339u, + INT_TMR42_GCMWH = 340u, + INT_TMR42_GCMWL = 341u, + INT_TMR42_GOVF = 342u, + INT_TMR42_GUDF = 343u, + INT_TMR42_RLOU = 344u, + INT_TMR42_RLOV = 345u, + INT_TMR42_RLOW = 346u, + INT_TMR43_GCMUH = 352u, + INT_TMR43_GCMUL = 353u, + INT_TMR43_GCMVH = 354u, + INT_TMR43_GCMVL = 355u, + INT_TMR43_GCMWH = 356u, + INT_TMR43_GCMWL = 357u, + INT_TMR43_GOVF = 358u, + INT_TMR43_GUDF = 359u, + INT_TMR43_RLOU = 360u, + INT_TMR43_RLOV = 361u, + INT_TMR43_RLOW = 362u, + + /* EMB */ + INT_EMB_GR0 = 390u, + INT_EMB_GR1 = 391u, + INT_EMB_GR2 = 392u, + INT_EMB_GR3 = 393u, + + /* EVENT PORT */ + INT_EVENT_PORT1 = 394u, + INT_EVENT_PORT2 = 395u, + INT_EVENT_PORT3 = 396u, + INT_EVENT_PORT4 = 397u, + + /* I2S */ + INT_I2S1_TXIRQOUT = 400u, + INT_I2S1_RXIRQOUT = 401u, + INT_I2S1_ERRIRQOUT = 402u, + INT_I2S2_TXIRQOUT = 403u, + INT_I2S2_RXIRQOUT = 404u, + INT_I2S2_ERRIRQOUT = 405u, + INT_I2S3_TXIRQOUT = 406u, + INT_I2S3_RXIRQOUT = 407u, + INT_I2S3_ERRIRQOUT = 408u, + INT_I2S4_TXIRQOUT = 409u, + INT_I2S4_RXIRQOUT = 410u, + INT_I2S4_ERRIRQOUT = 411u, + + /* COMPARATOR */ + INT_ACMP1 = 416u, + INT_ACMP2 = 417u, + INT_ACMP3 = 418u, + + /* I2C */ + INT_I2C1_RXI = 420u, + INT_I2C1_TXI = 421u, + INT_I2C1_TEI = 422u, + INT_I2C1_EEI = 423u, + INT_I2C2_RXI = 424u, + INT_I2C2_TXI = 425u, + INT_I2C2_TEI = 426u, + INT_I2C2_EEI = 427u, + INT_I2C3_RXI = 428u, + INT_I2C3_TXI = 429u, + INT_I2C3_TEI = 430u, + INT_I2C3_EEI = 431u, + + /* PVD */ + INT_PVD_PVD1 = 433u, + INT_PVD_PVD2 = 434u, + + /* Temp. sensor */ + INT_OTS = 435u, + + /* FCM */ + INT_FCMFERRI = 436u, + INT_FCMMENDI = 437u, + INT_FCMCOVFI = 438u, + + /* WDT */ + INT_WDT_REFUDF = 439u, + + /* ADC */ + INT_ADC1_EOCA = 448u, + INT_ADC1_EOCB = 449u, + INT_ADC1_CHCMP = 450u, + INT_ADC1_SEQCMP = 451u, + INT_ADC2_EOCA = 452u, + INT_ADC2_EOCB = 453u, + INT_ADC2_CHCMP = 454u, + INT_ADC2_SEQCMP = 455u, + + /* TRNG */ + INT_TRNG_END = 456u, + + /* SDIOC */ + INT_SDIOC1_SD = 482u, + INT_SDIOC2_SD = 485u, + + /* CAN */ + INT_CAN_INT = 486u, + + INT_MAX = 511u, +}en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint8_t STRT : 1; + uint8_t RESERVED1 : 7; +} stc_adc_str_field_t; + +typedef struct +{ + __IO uint16_t MS : 2; + uint16_t RESERVED2 : 2; + __IO uint16_t ACCSEL : 2; + __IO uint16_t CLREN : 1; + __IO uint16_t DFMT : 1; + __IO uint16_t AVCNT : 3; + uint16_t RESERVED11 : 5; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 2; + __IO uint16_t RSCHSEL : 1; + uint16_t RESERVED3 :13; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint16_t TRGSELA : 3; + uint16_t RESERVED3 : 4; + __IO uint16_t TRGENA : 1; + __IO uint16_t TRGSELB : 3; + uint16_t RESERVED11 : 4; + __IO uint16_t TRGENB : 1; +} stc_adc_trgsr_field_t; + +typedef struct +{ + __IO uint16_t CHSELA16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselra1_field_t; + +typedef struct +{ + __IO uint16_t CHSELB16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselrb1_field_t; + +typedef struct +{ + __IO uint16_t AVCHSEL16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_avchselr1_field_t; + +typedef struct +{ + __IO uint16_t CH00MUX : 4; + __IO uint16_t CH01MUX : 4; + __IO uint16_t CH02MUX : 4; + __IO uint16_t CH03MUX : 4; +} stc_adc_chmuxr0_field_t; + +typedef struct +{ + __IO uint16_t CH04MUX : 4; + __IO uint16_t CH05MUX : 4; + __IO uint16_t CH06MUX : 4; + __IO uint16_t CH07MUX : 4; +} stc_adc_chmuxr1_field_t; + +typedef struct +{ + __IO uint16_t CH08MUX : 4; + __IO uint16_t CH09MUX : 4; + __IO uint16_t CH10MUX : 4; + __IO uint16_t CH11MUX : 4; +} stc_adc_chmuxr2_field_t; + +typedef struct +{ + __IO uint16_t CH12MUX : 4; + __IO uint16_t CH13MUX : 4; + __IO uint16_t CH14MUX : 4; + __IO uint16_t CH15MUX : 4; +} stc_adc_chmuxr3_field_t; + +typedef struct +{ + __IO uint8_t EOCAF : 1; + __IO uint8_t EOCBF : 1; + uint8_t RESERVED2 : 6; +} stc_adc_isr_field_t; + +typedef struct +{ + __IO uint8_t EOCAIEN : 1; + __IO uint8_t EOCBIEN : 1; + uint8_t RESERVED2 : 6; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint16_t SYNCEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t SYNCMD : 3; + uint16_t RESERVED7 : 1; + __IO uint16_t SYNCDLY : 8; +} stc_adc_synccr_field_t; + +typedef struct +{ + __IO uint16_t AWDEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t AWDMD : 1; + uint16_t RESERVED5 : 1; + __IO uint16_t AWDSS : 2; + __IO uint16_t AWDIEN : 1; + uint16_t RESERVED9 : 7; +} stc_adc_awdcr_field_t; + +typedef struct +{ + __IO uint16_t AWDCH16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdchsr1_field_t; + +typedef struct +{ + __IO uint16_t AWDF16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdsr1_field_t; + +typedef struct +{ + __IO uint16_t PGACTL : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgacr_field_t; + +typedef struct +{ + __IO uint16_t GAIN : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgagsr_field_t; + +typedef struct +{ + __IO uint16_t PGAINSEL : 9; + uint16_t RESERVED9 : 7; +} stc_adc_pgainsr0_field_t; + +typedef struct +{ + __IO uint16_t PGAVSSEN : 1; + uint16_t RESERVED1 :15; +} stc_adc_pgainsr1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; + uint32_t RESERVED2 :30; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t STRG : 1; + uint32_t RESERVED1 :31; +} stc_aos_int_sfttrg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu3_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu4_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel3_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma_trgselrc_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr6_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr0_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_port_pevnttrgsr12_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_port_pevnttrgsr34_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmra_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_ots_trg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc1_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc2_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg1_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg2_field_t; + +typedef struct +{ + __IO uint32_t PDIR00 : 1; + __IO uint32_t PDIR01 : 1; + __IO uint32_t PDIR02 : 1; + __IO uint32_t PDIR03 : 1; + __IO uint32_t PDIR04 : 1; + __IO uint32_t PDIR05 : 1; + __IO uint32_t PDIR06 : 1; + __IO uint32_t PDIR07 : 1; + __IO uint32_t PDIR08 : 1; + __IO uint32_t PDIR09 : 1; + __IO uint32_t PDIR10 : 1; + __IO uint32_t PDIR11 : 1; + __IO uint32_t PDIR12 : 1; + __IO uint32_t PDIR13 : 1; + __IO uint32_t PDIR14 : 1; + __IO uint32_t PDIR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntdirr_field_t; + +typedef struct +{ + __IO uint32_t PIN00 : 1; + __IO uint32_t PIN01 : 1; + __IO uint32_t PIN02 : 1; + __IO uint32_t PIN03 : 1; + __IO uint32_t PIN04 : 1; + __IO uint32_t PIN05 : 1; + __IO uint32_t PIN06 : 1; + __IO uint32_t PIN07 : 1; + __IO uint32_t PIN08 : 1; + __IO uint32_t PIN09 : 1; + __IO uint32_t PIN10 : 1; + __IO uint32_t PIN11 : 1; + __IO uint32_t PIN12 : 1; + __IO uint32_t PIN13 : 1; + __IO uint32_t PIN14 : 1; + __IO uint32_t PIN15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntidr_field_t; + +typedef struct +{ + __IO uint32_t POUT00 : 1; + __IO uint32_t POUT01 : 1; + __IO uint32_t POUT02 : 1; + __IO uint32_t POUT03 : 1; + __IO uint32_t POUT04 : 1; + __IO uint32_t POUT05 : 1; + __IO uint32_t POUT06 : 1; + __IO uint32_t POUT07 : 1; + __IO uint32_t POUT08 : 1; + __IO uint32_t POUT09 : 1; + __IO uint32_t POUT10 : 1; + __IO uint32_t POUT11 : 1; + __IO uint32_t POUT12 : 1; + __IO uint32_t POUT13 : 1; + __IO uint32_t POUT14 : 1; + __IO uint32_t POUT15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntodr_field_t; + +typedef struct +{ + __IO uint32_t POR00 : 1; + __IO uint32_t POR01 : 1; + __IO uint32_t POR02 : 1; + __IO uint32_t POR03 : 1; + __IO uint32_t POR04 : 1; + __IO uint32_t POR05 : 1; + __IO uint32_t POR06 : 1; + __IO uint32_t POR07 : 1; + __IO uint32_t POR08 : 1; + __IO uint32_t POR09 : 1; + __IO uint32_t POR10 : 1; + __IO uint32_t POR11 : 1; + __IO uint32_t POR12 : 1; + __IO uint32_t POR13 : 1; + __IO uint32_t POR14 : 1; + __IO uint32_t POR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntorr_field_t; + +typedef struct +{ + __IO uint32_t POS00 : 1; + __IO uint32_t POS01 : 1; + __IO uint32_t POS02 : 1; + __IO uint32_t POS03 : 1; + __IO uint32_t POS04 : 1; + __IO uint32_t POS05 : 1; + __IO uint32_t POS06 : 1; + __IO uint32_t POS07 : 1; + __IO uint32_t POS08 : 1; + __IO uint32_t POS09 : 1; + __IO uint32_t POS10 : 1; + __IO uint32_t POS11 : 1; + __IO uint32_t POS12 : 1; + __IO uint32_t POS13 : 1; + __IO uint32_t POS14 : 1; + __IO uint32_t POS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntosr_field_t; + +typedef struct +{ + __IO uint32_t RIS00 : 1; + __IO uint32_t RIS01 : 1; + __IO uint32_t RIS02 : 1; + __IO uint32_t RIS03 : 1; + __IO uint32_t RIS04 : 1; + __IO uint32_t RIS05 : 1; + __IO uint32_t RIS06 : 1; + __IO uint32_t RIS07 : 1; + __IO uint32_t RIS08 : 1; + __IO uint32_t RIS09 : 1; + __IO uint32_t RIS10 : 1; + __IO uint32_t RIS11 : 1; + __IO uint32_t RIS12 : 1; + __IO uint32_t RIS13 : 1; + __IO uint32_t RIS14 : 1; + __IO uint32_t RIS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntrisr_field_t; + +typedef struct +{ + __IO uint32_t FAL00 : 1; + __IO uint32_t FAL01 : 1; + __IO uint32_t FAL02 : 1; + __IO uint32_t FAL03 : 1; + __IO uint32_t FAL04 : 1; + __IO uint32_t FAL05 : 1; + __IO uint32_t FAL06 : 1; + __IO uint32_t FAL07 : 1; + __IO uint32_t FAL08 : 1; + __IO uint32_t FAL09 : 1; + __IO uint32_t FAL10 : 1; + __IO uint32_t FAL11 : 1; + __IO uint32_t FAL12 : 1; + __IO uint32_t FAL13 : 1; + __IO uint32_t FAL14 : 1; + __IO uint32_t FAL15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntfal_field_t; + +typedef struct +{ + __IO uint32_t NFEN1 : 1; + __IO uint32_t DIVS1 : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NFEN2 : 1; + __IO uint32_t DIVS2 : 2; + uint32_t RESERVED11 : 5; + __IO uint32_t NFEN3 : 1; + __IO uint32_t DIVS3 : 2; + uint32_t RESERVED19 : 5; + __IO uint32_t NFEN4 : 1; + __IO uint32_t DIVS4 : 2; + uint32_t RESERVED27 : 5; +} stc_aos_pevntnfcr_field_t; + +typedef struct +{ + __IO uint8_t BUSOFF : 1; + __IO uint8_t TACTIVE : 1; + __IO uint8_t RACTIVE : 1; + __IO uint8_t TSSS : 1; + __IO uint8_t TPSS : 1; + __IO uint8_t LBMI : 1; + __IO uint8_t LBME : 1; + __IO uint8_t RESET : 1; +} stc_can_cfg_stat_field_t; + +typedef struct +{ + __IO uint8_t TSA : 1; + __IO uint8_t TSALL : 1; + __IO uint8_t TSONE : 1; + __IO uint8_t TPA : 1; + __IO uint8_t TPE : 1; + __IO uint8_t STBY : 1; + __IO uint8_t LOM : 1; + __IO uint8_t TBSEL : 1; +} stc_can_tcmd_field_t; + +typedef struct +{ + __IO uint8_t TSSTAT : 2; + uint8_t RESERVED2 : 2; + __IO uint8_t TTBM : 1; + __IO uint8_t TSMODE : 1; + __IO uint8_t TSNEXT : 1; + uint8_t RESERVED7 : 1; +} stc_can_tctrl_field_t; + +typedef struct +{ + __IO uint8_t RSSTAT : 2; + uint8_t RESERVED2 : 1; + __IO uint8_t RBALL : 1; + __IO uint8_t RREL : 1; + __IO uint8_t ROV : 1; + __IO uint8_t ROM : 1; + __IO uint8_t SACK : 1; +} stc_can_rctrl_field_t; + +typedef struct +{ + __IO uint8_t TSFF : 1; + __IO uint8_t EIE : 1; + __IO uint8_t TSIE : 1; + __IO uint8_t TPIE : 1; + __IO uint8_t RAFIE : 1; + __IO uint8_t RFIE : 1; + __IO uint8_t ROIE : 1; + __IO uint8_t RIE : 1; +} stc_can_rtie_field_t; + +typedef struct +{ + __IO uint8_t AIF : 1; + __IO uint8_t EIF : 1; + __IO uint8_t TSIF : 1; + __IO uint8_t TPIF : 1; + __IO uint8_t RAFIF : 1; + __IO uint8_t RFIF : 1; + __IO uint8_t ROIF : 1; + __IO uint8_t RIF : 1; +} stc_can_rtif_field_t; + +typedef struct +{ + __IO uint8_t BEIF : 1; + __IO uint8_t BEIE : 1; + __IO uint8_t ALIF : 1; + __IO uint8_t ALIE : 1; + __IO uint8_t EPIF : 1; + __IO uint8_t EPIE : 1; + __IO uint8_t EPASS : 1; + __IO uint8_t EWARN : 1; +} stc_can_errint_field_t; + +typedef struct +{ + __IO uint8_t EWL : 4; + __IO uint8_t AFWL : 4; +} stc_can_limit_field_t; + +typedef struct +{ + __IO uint32_t SEG_1 : 8; + __IO uint32_t SEG_2 : 7; + uint32_t RESERVED15 : 1; + __IO uint32_t SJW : 7; + uint32_t RESERVED23 : 1; + __IO uint32_t PRESC : 8; +} stc_can_bt_field_t; + +typedef struct +{ + __IO uint8_t ALC : 5; + __IO uint8_t KOER : 3; +} stc_can_ealcap_field_t; + +typedef struct +{ + __IO uint8_t ACFADR : 4; + uint8_t RESERVED4 : 1; + __IO uint8_t SELMASK : 1; + uint8_t RESERVED6 : 2; +} stc_can_acfctrl_field_t; + +typedef struct +{ + __IO uint8_t AE_1 : 1; + __IO uint8_t AE_2 : 1; + __IO uint8_t AE_3 : 1; + __IO uint8_t AE_4 : 1; + __IO uint8_t AE_5 : 1; + __IO uint8_t AE_6 : 1; + __IO uint8_t AE_7 : 1; + __IO uint8_t AE_8 : 1; +} stc_can_acfen_field_t; + +typedef struct +{ + __IO uint32_t ACODEORAMASK :29; + __IO uint32_t AIDE : 1; + __IO uint32_t AIDEE : 1; + uint32_t RESERVED31 : 1; +} stc_can_acf_field_t; + +typedef struct +{ + __IO uint8_t TBPTR : 6; + __IO uint8_t TBF : 1; + __IO uint8_t TBE : 1; +} stc_can_tbslot_field_t; + +typedef struct +{ + __IO uint8_t TTEN : 1; + __IO uint8_t T_PRESC : 2; + __IO uint8_t TTIF : 1; + __IO uint8_t TTIE : 1; + __IO uint8_t TEIF : 1; + __IO uint8_t WTIF : 1; + __IO uint8_t WTIE : 1; +} stc_can_ttcfg_field_t; + +typedef struct +{ + __IO uint32_t REF_ID :29; + uint32_t RESERVED29 : 2; + __IO uint32_t REF_IDE : 1; +} stc_can_ref_msg_field_t; + +typedef struct +{ + __IO uint16_t TTPTR : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t TTYPE : 3; + uint16_t RESERVED11 : 1; + __IO uint16_t TEW : 4; +} stc_can_trg_cfg_field_t; + +typedef struct +{ + __IO uint16_t FLTSL : 3; + uint16_t RESERVED3 : 2; + __IO uint16_t EDGSL : 2; + __IO uint16_t IEN : 1; + __IO uint16_t CVSEN : 1; + uint16_t RESERVED9 : 3; + __IO uint16_t OUTEN : 1; + __IO uint16_t INV : 1; + __IO uint16_t CMPOE : 1; + __IO uint16_t CMPON : 1; +} stc_cmp_ctrl_field_t; + +typedef struct +{ + __IO uint16_t RVSL : 4; + uint16_t RESERVED4 : 4; + __IO uint16_t CVSL : 4; + __IO uint16_t C4SL : 3; + uint16_t RESERVED15 : 1; +} stc_cmp_vltsel_field_t; + +typedef struct +{ + __IO uint16_t OMON : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t CVST : 4; + uint16_t RESERVED12 : 4; +} stc_cmp_mon_field_t; + +typedef struct +{ + __IO uint16_t STB : 4; + uint16_t RESERVED4 :12; +} stc_cmp_cvsstb_field_t; + +typedef struct +{ + __IO uint16_t PRD : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cvsprd_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr1_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr2_field_t; + +typedef struct +{ + __IO uint16_t DA1EN : 1; + __IO uint16_t DA2EN : 1; + uint16_t RESERVED2 :14; +} stc_cmp_cr_dacr_field_t; + +typedef struct +{ + __IO uint16_t DA1SW : 1; + __IO uint16_t DA2SW : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t VREFSW : 1; + uint16_t RESERVED5 : 3; + __IO uint16_t WPRT : 8; +} stc_cmp_cr_rvadc_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t CRC_SEL : 1; + __IO uint32_t REFIN : 1; + __IO uint32_t REFOUT : 1; + __IO uint32_t XOROUT : 1; + uint32_t RESERVED5 :27; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t FLAG : 1; + uint32_t RESERVED1 :31; +} stc_crc_flg_field_t; + +typedef struct +{ + __IO uint32_t AUTH : 1; + __IO uint32_t REMVLOCK : 1; + __IO uint32_t SAFTYLOCK1 : 1; + __IO uint32_t SAFTYLOCK2 : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t CPUSTOP : 1; + __IO uint32_t CPUSLEEP : 1; + uint32_t RESERVED10 :22; +} stc_dbgc_mcustat_field_t; + +typedef struct +{ + __IO uint32_t EDBGRQ : 1; + __IO uint32_t RESTART : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t DIRQ : 1; + uint32_t RESERVED9 :23; +} stc_dbgc_mcuctl_field_t; + +typedef struct +{ + __IO uint32_t ERASEREQ : 1; + __IO uint32_t ERASEACK : 1; + __IO uint32_t ERASEERR : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_fmcctl_field_t; + +typedef struct +{ + __IO uint32_t CDBGPWRUPREQ : 1; + __IO uint32_t CDBGPWRUPACK : 1; + uint32_t RESERVED2 :30; +} stc_dbgc_mcudbgstat_field_t; + +typedef struct +{ + __IO uint32_t SWDTSTP : 1; + __IO uint32_t WDTSTP : 1; + __IO uint32_t RTCSTP : 1; + __IO uint32_t PVD0STP : 1; + __IO uint32_t PVD1STP : 1; + __IO uint32_t PVD2STP : 1; + uint32_t RESERVED6 : 8; + __IO uint32_t TMR01STP : 1; + __IO uint32_t TMR02STP : 1; + uint32_t RESERVED16 : 4; + __IO uint32_t TMR41STP : 1; + __IO uint32_t TMR42STP : 1; + __IO uint32_t TMR43STP : 1; + __IO uint32_t TM61STP : 1; + __IO uint32_t TM62STP : 1; + __IO uint32_t TMR63STP : 1; + __IO uint32_t TMRA1STP : 1; + __IO uint32_t TMRA2STP : 1; + __IO uint32_t TMRA3STP : 1; + __IO uint32_t TMRA4STP : 1; + __IO uint32_t TMRA5STP : 1; + __IO uint32_t TMRA6STP : 1; +} stc_dbgc_mcustpctl_field_t; + +typedef struct +{ + __IO uint32_t TRACEMODE : 2; + __IO uint32_t TRACEIOEN : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_mcutracectl_field_t; + +typedef struct +{ + __IO uint32_t MODE : 3; + __IO uint32_t DATASIZE : 2; + uint32_t RESERVED5 : 3; + __IO uint32_t COMP_TRG : 1; + uint32_t RESERVED9 :22; + __IO uint32_t INTEN : 1; +} stc_dcu_ctl_field_t; + +typedef struct +{ + __IO uint32_t FLAG_OP : 1; + __IO uint32_t FLAG_LS2 : 1; + __IO uint32_t FLAG_EQ2 : 1; + __IO uint32_t FLAG_GT2 : 1; + __IO uint32_t FLAG_LS1 : 1; + __IO uint32_t FLAG_EQ1 : 1; + __IO uint32_t FLAG_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flag_field_t; + +typedef struct +{ + __IO uint32_t CLR_OP : 1; + __IO uint32_t CLR_LS2 : 1; + __IO uint32_t CLR_EQ2 : 1; + __IO uint32_t CLR_GT2 : 1; + __IO uint32_t CLR_LS1 : 1; + __IO uint32_t CLR_EQ1 : 1; + __IO uint32_t CLR_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flagclr_field_t; + +typedef struct +{ + __IO uint32_t INT_OP : 1; + __IO uint32_t INT_LS2 : 1; + __IO uint32_t INT_EQ2 : 1; + __IO uint32_t INT_GT2 : 1; + __IO uint32_t INT_LS1 : 1; + __IO uint32_t INT_EQ1 : 1; + __IO uint32_t INT_GT1 : 1; + __IO uint32_t INT_WIN : 2; + uint32_t RESERVED9 :23; +} stc_dcu_intsel_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 :31; +} stc_dma_en_field_t; + +typedef struct +{ + __IO uint32_t TRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t REQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat0_field_t; + +typedef struct +{ + __IO uint32_t TC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t BTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat1_field_t; + +typedef struct +{ + __IO uint32_t MSKTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask0_field_t; + +typedef struct +{ + __IO uint32_t MSKTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask1_field_t; + +typedef struct +{ + __IO uint32_t CLRTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t CLRREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr0_field_t; + +typedef struct +{ + __IO uint32_t CLRTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t CLRBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr1_field_t; + +typedef struct +{ + __IO uint32_t CHEN : 4; + uint32_t RESERVED4 :28; +} stc_dma_chen_field_t; + +typedef struct +{ + __IO uint32_t DMAACT : 1; + __IO uint32_t RCFGACT : 1; + uint32_t RESERVED2 :14; + __IO uint32_t CHACT : 4; + uint32_t RESERVED20 :12; +} stc_dma_chstat_field_t; + +typedef struct +{ + __IO uint32_t RCFGEN : 1; + __IO uint32_t RCFGLLP : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t RCFGCHS : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SARMD : 2; + __IO uint32_t DARMD : 2; + __IO uint32_t CNTMD : 2; + uint32_t RESERVED22 :10; +} stc_dma_rcfgctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_dtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_rpt_field_t; + +typedef struct +{ + __IO uint32_t SRPTB :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPTB :10; + uint32_t RESERVED26 : 6; +} stc_dma_rptb_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_snseqctl_field_t; + +typedef struct +{ + __IO uint32_t SNSDIST :20; + __IO uint32_t SNSCNTB :12; +} stc_dma_snseqctlb_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_dnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DNSDIST :20; + __IO uint32_t DNSCNTB :12; +} stc_dma_dnseqctlb_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t LLP :30; +} stc_dma_llp_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch0ctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_mondtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_monrpt_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_monsnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_mondnseqctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch1ctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch2ctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch3ctl_field_t; + +typedef struct +{ + __IO uint32_t FAPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_faprt_field_t; + +typedef struct +{ + __IO uint32_t FSTP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fstp_field_t; + +typedef struct +{ + __IO uint32_t SLPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t FLWT : 4; + __IO uint32_t LVM : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t CACHE : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t CRST : 1; + uint32_t RESERVED25 : 7; +} stc_efm_frmc_field_t; + +typedef struct +{ + __IO uint32_t PEMODE : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t PEMOD : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t BUSHLDCTL : 1; + uint32_t RESERVED9 :23; +} stc_efm_fwmc_field_t; + +typedef struct +{ + __IO uint32_t PEWERR : 1; + __IO uint32_t PEPRTERR : 1; + __IO uint32_t PGSZERR : 1; + __IO uint32_t PGMISMTCH : 1; + __IO uint32_t OPTEND : 1; + __IO uint32_t COLERR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t RDY : 1; + uint32_t RESERVED9 :23; +} stc_efm_fsr_field_t; + +typedef struct +{ + __IO uint32_t PEWERRCLR : 1; + __IO uint32_t PEPRTERRCLR : 1; + __IO uint32_t PGSZERRCLR : 1; + __IO uint32_t PGMISMTCHCLR : 1; + __IO uint32_t OPTENDCLR : 1; + __IO uint32_t COLERRCLR : 1; + uint32_t RESERVED6 :26; +} stc_efm_fsclr_field_t; + +typedef struct +{ + __IO uint32_t PEERRITE : 1; + __IO uint32_t OPTENDITE : 1; + __IO uint32_t COLERRITE : 1; + uint32_t RESERVED3 :29; +} stc_efm_fite_field_t; + +typedef struct +{ + __IO uint32_t FSWP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fswp_field_t; + +typedef struct +{ + __IO uint32_t FPMTSW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtsw_field_t; + +typedef struct +{ + __IO uint32_t FPMTEW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtew_field_t; + +typedef struct +{ + __IO uint32_t REMPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_mmf_remprt_field_t; + +typedef struct +{ + __IO uint32_t RM0SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM0TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN0 : 1; +} stc_efm_mmf_remcr0_field_t; + +typedef struct +{ + __IO uint32_t RM1SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM1TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN1 : 1; +} stc_efm_mmf_remcr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t FRANDS :14; + uint32_t RESERVED15 : 1; + __IO uint32_t FRANDFG : 1; + uint32_t RESERVED17 :15; +} stc_efm_efm_frands_field_t; + +typedef struct +{ + __IO uint32_t PORTINEN : 1; + __IO uint32_t CMPEN : 3; + uint32_t RESERVED4 : 1; + __IO uint32_t OSCSTPEN : 1; + __IO uint32_t PWMSEN : 3; + uint32_t RESERVED9 :19; + __IO uint32_t NFSEL : 2; + __IO uint32_t NFEN : 1; + __IO uint32_t INVSEL : 1; +} stc_emb_ctl_field_t; + +typedef struct +{ + __IO uint32_t PWMLV : 3; + uint32_t RESERVED3 :29; +} stc_emb_pwmlv_field_t; + +typedef struct +{ + __IO uint32_t SOE : 1; + uint32_t RESERVED1 :31; +} stc_emb_soe_field_t; + +typedef struct +{ + __IO uint32_t PORTINF : 1; + __IO uint32_t PWMSF : 1; + __IO uint32_t CMPF : 1; + __IO uint32_t OSF : 1; + __IO uint32_t PORTINST : 1; + __IO uint32_t PWMST : 1; + uint32_t RESERVED6 :26; +} stc_emb_stat_field_t; + +typedef struct +{ + __IO uint32_t PORTINFCLR : 1; + __IO uint32_t PWMSFCLR : 1; + __IO uint32_t CMPFCLR : 1; + __IO uint32_t OSFCLR : 1; + uint32_t RESERVED4 :28; +} stc_emb_statclr_field_t; + +typedef struct +{ + __IO uint32_t PORTINTEN : 1; + __IO uint32_t PWMINTEN : 1; + __IO uint32_t CMPINTEN : 1; + __IO uint32_t OSINTEN : 1; + uint32_t RESERVED4 :28; +} stc_emb_inten_field_t; + +typedef struct +{ + __IO uint32_t LVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_lvr_field_t; + +typedef struct +{ + __IO uint32_t UVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_uvr_field_t; + +typedef struct +{ + __IO uint32_t CNTR :16; + uint32_t RESERVED16 :16; +} stc_fcm_cntr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :31; +} stc_fcm_str_field_t; + +typedef struct +{ + __IO uint32_t MDIVS : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t MCKS : 4; + uint32_t RESERVED8 :24; +} stc_fcm_mccr_field_t; + +typedef struct +{ + __IO uint32_t RDIVS : 2; + uint32_t RESERVED2 : 1; + __IO uint32_t RCKS : 4; + __IO uint32_t INEXS : 1; + __IO uint32_t DNFS : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t EDGES : 2; + uint32_t RESERVED14 : 1; + __IO uint32_t EXREFE : 1; + uint32_t RESERVED16 :16; +} stc_fcm_rccr_field_t; + +typedef struct +{ + __IO uint32_t ERRIE : 1; + __IO uint32_t MENDIE : 1; + __IO uint32_t OVFIE : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t ERRINTRS : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ERRE : 1; + uint32_t RESERVED8 :24; +} stc_fcm_rier_field_t; + +typedef struct +{ + __IO uint32_t ERRF : 1; + __IO uint32_t MENDF : 1; + __IO uint32_t OVF : 1; + uint32_t RESERVED3 :29; +} stc_fcm_sr_field_t; + +typedef struct +{ + __IO uint32_t ERRFCLR : 1; + __IO uint32_t MENDFCLR : 1; + __IO uint32_t OVFCLR : 1; + uint32_t RESERVED3 :29; +} stc_fcm_clr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t FST_GRP : 1; + uint32_t RESERVED2 :30; +} stc_hash_cr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t SMBUS : 1; + __IO uint32_t SMBALRTEN : 1; + __IO uint32_t SMBDEFAULTEN : 1; + __IO uint32_t SMBHOSTEN : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ENGC : 1; + __IO uint32_t RESTART : 1; + __IO uint32_t START : 1; + __IO uint32_t STOP : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t SWRST : 1; + uint32_t RESERVED16 :16; +} stc_i2c_cr1_field_t; + +typedef struct +{ + __IO uint32_t STARTIE : 1; + __IO uint32_t SLADDR0IE : 1; + __IO uint32_t SLADDR1IE : 1; + __IO uint32_t TENDIE : 1; + __IO uint32_t STOPIE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLIE : 1; + __IO uint32_t TEMPTYIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOIE : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKIE : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTIE : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLIE : 1; + __IO uint32_t SMBDEFAULTIE : 1; + __IO uint32_t SMBHOSTIE : 1; + __IO uint32_t SMBALRTIE : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_cr2_field_t; + +typedef struct +{ + __IO uint32_t TMOUTEN : 1; + __IO uint32_t LTMOUT : 1; + __IO uint32_t HTMOUT : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t FACKEN : 1; + uint32_t RESERVED8 :24; +} stc_i2c_cr3_field_t; + +typedef struct +{ + __IO uint32_t SLADDR0 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR0EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD0 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr0_field_t; + +typedef struct +{ + __IO uint32_t SLADDR1 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR1EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD1 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr1_field_t; + +typedef struct +{ + __IO uint32_t TOUTLOW :16; + __IO uint32_t TOUTHIGH :16; +} stc_i2c_sltr_field_t; + +typedef struct +{ + __IO uint32_t STARTF : 1; + __IO uint32_t SLADDR0F : 1; + __IO uint32_t SLADDR1F : 1; + __IO uint32_t TENDF : 1; + __IO uint32_t STOPF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLF : 1; + __IO uint32_t TEMPTYF : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOF : 1; + __IO uint32_t ACKRF : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t NACKF : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTF : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t MSL : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t TRA : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t GENCALLF : 1; + __IO uint32_t SMBDEFAULTF : 1; + __IO uint32_t SMBHOSTF : 1; + __IO uint32_t SMBALRTF : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_sr_field_t; + +typedef struct +{ + __IO uint32_t STARTFCLR : 1; + __IO uint32_t SLADDR0FCLR : 1; + __IO uint32_t SLADDR1FCLR : 1; + __IO uint32_t TENDFCLR : 1; + __IO uint32_t STOPFCLR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLFCLR : 1; + __IO uint32_t TEMPTYFCLR : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOFCLR : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKFCLR : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTFCLR : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLFCLR : 1; + __IO uint32_t SMBDEFAULTFCLR : 1; + __IO uint32_t SMBHOSTFCLR : 1; + __IO uint32_t SMBALRTFCLR : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_clr_field_t; + +typedef struct +{ + __IO uint8_t DT : 8; +} stc_i2c_dtr_field_t; + +typedef struct +{ + __IO uint8_t DR : 8; +} stc_i2c_drr_field_t; + +typedef struct +{ + __IO uint32_t SLOWW : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t SHIGHW : 5; + uint32_t RESERVED13 : 3; + __IO uint32_t FREQ : 3; + uint32_t RESERVED19 :13; +} stc_i2c_ccr_field_t; + +typedef struct +{ + __IO uint32_t DNF : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t DNFEN : 1; + __IO uint32_t ANFEN : 1; + uint32_t RESERVED6 :26; +} stc_i2c_fltr_field_t; + +typedef struct +{ + __IO uint32_t TXE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t WMS : 1; + __IO uint32_t ODD : 1; + __IO uint32_t MCKOE : 1; + __IO uint32_t TXBIRQWL : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t RXBIRQWL : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t FIFOR : 1; + __IO uint32_t CODECRC : 1; + __IO uint32_t I2SPLLSEL : 1; + __IO uint32_t SDOE : 1; + __IO uint32_t LRCKOE : 1; + __IO uint32_t CKOE : 1; + __IO uint32_t DUPLEX : 1; + __IO uint32_t CLKSEL : 1; + uint32_t RESERVED24 : 8; +} stc_i2s_ctrl_field_t; + +typedef struct +{ + __IO uint32_t TXBA : 1; + __IO uint32_t RXBA : 1; + __IO uint32_t TXBE : 1; + __IO uint32_t TXBF : 1; + __IO uint32_t RXBE : 1; + __IO uint32_t RXBF : 1; + uint32_t RESERVED6 :26; +} stc_i2s_sr_field_t; + +typedef struct +{ + __IO uint32_t TXERR : 1; + __IO uint32_t RXERR : 1; + uint32_t RESERVED2 :30; +} stc_i2s_er_field_t; + +typedef struct +{ + __IO uint32_t I2SSTD : 2; + __IO uint32_t DATLEN : 2; + __IO uint32_t CHLEN : 1; + __IO uint32_t PCMSYNC : 1; + uint32_t RESERVED6 :26; +} stc_i2s_cfgr_field_t; + +typedef struct +{ + __IO uint32_t I2SDIV : 8; + uint32_t RESERVED8 :24; +} stc_i2s_pr_field_t; + +typedef struct +{ + __IO uint32_t SWDTAUTS : 1; + __IO uint32_t SWDTITS : 1; + __IO uint32_t SWDTPERI : 2; + __IO uint32_t SWDTCKS : 4; + __IO uint32_t SWDTWDPT : 4; + __IO uint32_t SWDTSLPOFF : 1; + uint32_t RESERVED13 : 3; + __IO uint32_t WDTAUTS : 1; + __IO uint32_t WDTITS : 1; + __IO uint32_t WDTPERI : 2; + __IO uint32_t WDTCKS : 4; + __IO uint32_t WDTWDPT : 4; + __IO uint32_t WDTSLPOFF : 1; + uint32_t RESERVED29 : 3; +} stc_icg_icg0_field_t; + +typedef struct +{ + __IO uint32_t HRCFREQSEL : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t HRCSTOP : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t BOR_LEV : 2; + __IO uint32_t BORDIS : 1; + uint32_t RESERVED19 : 7; + __IO uint32_t SMPCLK : 2; + __IO uint32_t NMITRG : 1; + __IO uint32_t NMIENR : 1; + __IO uint32_t NFEN : 1; + __IO uint32_t NMIICGENA : 1; +} stc_icg_icg1_field_t; + +typedef struct +{ + __IO uint32_t NMITRG : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t NSMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t NFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_nmicr_field_t; + +typedef struct +{ + __IO uint32_t NMIENR : 1; + __IO uint32_t SWDTENR : 1; + __IO uint32_t PVD1ENR : 1; + __IO uint32_t PVD2ENR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPENR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPENR : 1; + __IO uint32_t RECCENR : 1; + __IO uint32_t BUSMENR : 1; + __IO uint32_t WDTENR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmienr_field_t; + +typedef struct +{ + __IO uint32_t NMIFR : 1; + __IO uint32_t SWDTFR : 1; + __IO uint32_t PVD1FR : 1; + __IO uint32_t PVD2FR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPFR : 1; + __IO uint32_t RECCFR : 1; + __IO uint32_t BUSMFR : 1; + __IO uint32_t WDTFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmifr_field_t; + +typedef struct +{ + __IO uint32_t NMICFR : 1; + __IO uint32_t SWDTCFR : 1; + __IO uint32_t PVD1CFR : 1; + __IO uint32_t PVD2CFR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPCFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPCFR : 1; + __IO uint32_t RECCCFR : 1; + __IO uint32_t BUSMCFR : 1; + __IO uint32_t WDTCFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmicfr_field_t; + +typedef struct +{ + __IO uint32_t EIRQTRG : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t EISMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t EFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_eirqcr_field_t; + +typedef struct +{ + __IO uint32_t EIRQWUEN :16; + __IO uint32_t SWDTWUEN : 1; + __IO uint32_t PVD1WUEN : 1; + __IO uint32_t PVD2WUEN : 1; + __IO uint32_t CMPI0WUEN : 1; + __IO uint32_t WKTMWUEN : 1; + __IO uint32_t RTCALMWUEN : 1; + __IO uint32_t RTCPRDWUEN : 1; + __IO uint32_t TMR0WUEN : 1; + uint32_t RESERVED24 : 1; + __IO uint32_t RXWUEN : 1; + uint32_t RESERVED26 : 6; +} stc_intc_wupen_field_t; + +typedef struct +{ + __IO uint32_t EIFR0 : 1; + __IO uint32_t EIFR1 : 1; + __IO uint32_t EIFR2 : 1; + __IO uint32_t EIFR3 : 1; + __IO uint32_t EIFR4 : 1; + __IO uint32_t EIFR5 : 1; + __IO uint32_t EIFR6 : 1; + __IO uint32_t EIFR7 : 1; + __IO uint32_t EIFR8 : 1; + __IO uint32_t EIFR9 : 1; + __IO uint32_t EIFR10 : 1; + __IO uint32_t EIFR11 : 1; + __IO uint32_t EIFR12 : 1; + __IO uint32_t EIFR13 : 1; + __IO uint32_t EIFR14 : 1; + __IO uint32_t EIFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eifr_field_t; + +typedef struct +{ + __IO uint32_t EICFR0 : 1; + __IO uint32_t EICFR1 : 1; + __IO uint32_t EICFR2 : 1; + __IO uint32_t EICFR3 : 1; + __IO uint32_t EICFR4 : 1; + __IO uint32_t EICFR5 : 1; + __IO uint32_t EICFR6 : 1; + __IO uint32_t EICFR7 : 1; + __IO uint32_t EICFR8 : 1; + __IO uint32_t EICFR9 : 1; + __IO uint32_t EICFR10 : 1; + __IO uint32_t EICFR11 : 1; + __IO uint32_t EICFR12 : 1; + __IO uint32_t EICFR13 : 1; + __IO uint32_t EICFR14 : 1; + __IO uint32_t EICFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eicfr_field_t; + +typedef struct +{ + __IO uint32_t INTSEL : 9; + uint32_t RESERVED9 :23; +} stc_intc_sel_field_t; + +typedef struct +{ + __IO uint32_t VSEL0 : 1; + __IO uint32_t VSEL1 : 1; + __IO uint32_t VSEL2 : 1; + __IO uint32_t VSEL3 : 1; + __IO uint32_t VSEL4 : 1; + __IO uint32_t VSEL5 : 1; + __IO uint32_t VSEL6 : 1; + __IO uint32_t VSEL7 : 1; + __IO uint32_t VSEL8 : 1; + __IO uint32_t VSEL9 : 1; + __IO uint32_t VSEL10 : 1; + __IO uint32_t VSEL11 : 1; + __IO uint32_t VSEL12 : 1; + __IO uint32_t VSEL13 : 1; + __IO uint32_t VSEL14 : 1; + __IO uint32_t VSEL15 : 1; + __IO uint32_t VSEL16 : 1; + __IO uint32_t VSEL17 : 1; + __IO uint32_t VSEL18 : 1; + __IO uint32_t VSEL19 : 1; + __IO uint32_t VSEL20 : 1; + __IO uint32_t VSEL21 : 1; + __IO uint32_t VSEL22 : 1; + __IO uint32_t VSEL23 : 1; + __IO uint32_t VSEL24 : 1; + __IO uint32_t VSEL25 : 1; + __IO uint32_t VSEL26 : 1; + __IO uint32_t VSEL27 : 1; + __IO uint32_t VSEL28 : 1; + __IO uint32_t VSEL29 : 1; + __IO uint32_t VSEL30 : 1; + __IO uint32_t VSEL31 : 1; +} stc_intc_vssel_field_t; + +typedef struct +{ + __IO uint32_t SWIE0 : 1; + __IO uint32_t SWIE1 : 1; + __IO uint32_t SWIE2 : 1; + __IO uint32_t SWIE3 : 1; + __IO uint32_t SWIE4 : 1; + __IO uint32_t SWIE5 : 1; + __IO uint32_t SWIE6 : 1; + __IO uint32_t SWIE7 : 1; + __IO uint32_t SWIE8 : 1; + __IO uint32_t SWIE9 : 1; + __IO uint32_t SWIE10 : 1; + __IO uint32_t SWIE11 : 1; + __IO uint32_t SWIE12 : 1; + __IO uint32_t SWIE13 : 1; + __IO uint32_t SWIE14 : 1; + __IO uint32_t SWIE15 : 1; + __IO uint32_t SWIE16 : 1; + __IO uint32_t SWIE17 : 1; + __IO uint32_t SWIE18 : 1; + __IO uint32_t SWIE19 : 1; + __IO uint32_t SWIE20 : 1; + __IO uint32_t SWIE21 : 1; + __IO uint32_t SWIE22 : 1; + __IO uint32_t SWIE23 : 1; + __IO uint32_t SWIE24 : 1; + __IO uint32_t SWIE25 : 1; + __IO uint32_t SWIE26 : 1; + __IO uint32_t SWIE27 : 1; + __IO uint32_t SWIE28 : 1; + __IO uint32_t SWIE29 : 1; + __IO uint32_t SWIE30 : 1; + __IO uint32_t SWIE31 : 1; +} stc_intc_swier_field_t; + +typedef struct +{ + __IO uint32_t EVTE0 : 1; + __IO uint32_t EVTE1 : 1; + __IO uint32_t EVTE2 : 1; + __IO uint32_t EVTE3 : 1; + __IO uint32_t EVTE4 : 1; + __IO uint32_t EVTE5 : 1; + __IO uint32_t EVTE6 : 1; + __IO uint32_t EVTE7 : 1; + __IO uint32_t EVTE8 : 1; + __IO uint32_t EVTE9 : 1; + __IO uint32_t EVTE10 : 1; + __IO uint32_t EVTE11 : 1; + __IO uint32_t EVTE12 : 1; + __IO uint32_t EVTE13 : 1; + __IO uint32_t EVTE14 : 1; + __IO uint32_t EVTE15 : 1; + __IO uint32_t EVTE16 : 1; + __IO uint32_t EVTE17 : 1; + __IO uint32_t EVTE18 : 1; + __IO uint32_t EVTE19 : 1; + __IO uint32_t EVTE20 : 1; + __IO uint32_t EVTE21 : 1; + __IO uint32_t EVTE22 : 1; + __IO uint32_t EVTE23 : 1; + __IO uint32_t EVTE24 : 1; + __IO uint32_t EVTE25 : 1; + __IO uint32_t EVTE26 : 1; + __IO uint32_t EVTE27 : 1; + __IO uint32_t EVTE28 : 1; + __IO uint32_t EVTE29 : 1; + __IO uint32_t EVTE30 : 1; + __IO uint32_t EVTE31 : 1; +} stc_intc_evter_field_t; + +typedef struct +{ + __IO uint32_t IER0 : 1; + __IO uint32_t IER1 : 1; + __IO uint32_t IER2 : 1; + __IO uint32_t IER3 : 1; + __IO uint32_t IER4 : 1; + __IO uint32_t IER5 : 1; + __IO uint32_t IER6 : 1; + __IO uint32_t IER7 : 1; + __IO uint32_t IER8 : 1; + __IO uint32_t IER9 : 1; + __IO uint32_t IER10 : 1; + __IO uint32_t IER11 : 1; + __IO uint32_t IER12 : 1; + __IO uint32_t IER13 : 1; + __IO uint32_t IER14 : 1; + __IO uint32_t IER15 : 1; + __IO uint32_t IER16 : 1; + __IO uint32_t IER17 : 1; + __IO uint32_t IER18 : 1; + __IO uint32_t IER19 : 1; + __IO uint32_t IER20 : 1; + __IO uint32_t IER21 : 1; + __IO uint32_t IER22 : 1; + __IO uint32_t IER23 : 1; + __IO uint32_t IER24 : 1; + __IO uint32_t IER25 : 1; + __IO uint32_t IER26 : 1; + __IO uint32_t IER27 : 1; + __IO uint32_t IER28 : 1; + __IO uint32_t IER29 : 1; + __IO uint32_t IER30 : 1; + __IO uint32_t IER31 : 1; +} stc_intc_ier_field_t; + +typedef struct +{ + __IO uint32_t KEYINSEL :16; + __IO uint32_t KEYOUTSEL : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t CKSEL : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t T_LLEVEL : 5; + __IO uint32_t T_HIZ : 3; +} stc_keyscan_scr_field_t; + +typedef struct +{ + __IO uint32_t SEN : 1; + uint32_t RESERVED1 :31; +} stc_keyscan_ser_field_t; + +typedef struct +{ + __IO uint32_t INDEX : 3; + uint32_t RESERVED3 :29; +} stc_keyscan_ssr_field_t; + +typedef struct +{ + __IO uint32_t MPURG0SIZE : 5; + __IO uint32_t MPURG0ADDR :27; +} stc_mpu_rgd0_field_t; + +typedef struct +{ + __IO uint32_t MPURG1SIZE : 5; + __IO uint32_t MPURG1ADDR :27; +} stc_mpu_rgd1_field_t; + +typedef struct +{ + __IO uint32_t MPURG2SIZE : 5; + __IO uint32_t MPURG2ADDR :27; +} stc_mpu_rgd2_field_t; + +typedef struct +{ + __IO uint32_t MPURG3SIZE : 5; + __IO uint32_t MPURG3ADDR :27; +} stc_mpu_rgd3_field_t; + +typedef struct +{ + __IO uint32_t MPURG4SIZE : 5; + __IO uint32_t MPURG4ADDR :27; +} stc_mpu_rgd4_field_t; + +typedef struct +{ + __IO uint32_t MPURG5SIZE : 5; + __IO uint32_t MPURG5ADDR :27; +} stc_mpu_rgd5_field_t; + +typedef struct +{ + __IO uint32_t MPURG6SIZE : 5; + __IO uint32_t MPURG6ADDR :27; +} stc_mpu_rgd6_field_t; + +typedef struct +{ + __IO uint32_t MPURG7SIZE : 5; + __IO uint32_t MPURG7ADDR :27; +} stc_mpu_rgd7_field_t; + +typedef struct +{ + __IO uint32_t MPURG8SIZE : 5; + __IO uint32_t MPURG8ADDR :27; +} stc_mpu_rgd8_field_t; + +typedef struct +{ + __IO uint32_t MPURG9SIZE : 5; + __IO uint32_t MPURG9ADDR :27; +} stc_mpu_rgd9_field_t; + +typedef struct +{ + __IO uint32_t MPURG10SIZE : 5; + __IO uint32_t MPURG10ADDR :27; +} stc_mpu_rgd10_field_t; + +typedef struct +{ + __IO uint32_t MPURG11SIZE : 5; + __IO uint32_t MPURG11ADDR :27; +} stc_mpu_rgd11_field_t; + +typedef struct +{ + __IO uint32_t MPURG12SIZE : 5; + __IO uint32_t MPURG12ADDR :27; +} stc_mpu_rgd12_field_t; + +typedef struct +{ + __IO uint32_t MPURG13SIZE : 5; + __IO uint32_t MPURG13ADDR :27; +} stc_mpu_rgd13_field_t; + +typedef struct +{ + __IO uint32_t MPURG14SIZE : 5; + __IO uint32_t MPURG14ADDR :27; +} stc_mpu_rgd14_field_t; + +typedef struct +{ + __IO uint32_t MPURG15SIZE : 5; + __IO uint32_t MPURG15ADDR :27; +} stc_mpu_rgd15_field_t; + +typedef struct +{ + __IO uint32_t S2RG0RP : 1; + __IO uint32_t S2RG0WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG0E : 1; + __IO uint32_t S1RG0RP : 1; + __IO uint32_t S1RG0WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG0E : 1; + __IO uint32_t FRG0RP : 1; + __IO uint32_t FRG0WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG0E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr0_field_t; + +typedef struct +{ + __IO uint32_t S2RG1RP : 1; + __IO uint32_t S2RG1WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG1E : 1; + __IO uint32_t S1RG1RP : 1; + __IO uint32_t S1RG1WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG1E : 1; + __IO uint32_t FRG1RP : 1; + __IO uint32_t FRG1WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG1E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr1_field_t; + +typedef struct +{ + __IO uint32_t S2RG2RP : 1; + __IO uint32_t S2RG2WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG2E : 1; + __IO uint32_t S1RG2RP : 1; + __IO uint32_t S1RG2WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG2E : 1; + __IO uint32_t FRG2RP : 1; + __IO uint32_t FRG2WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG2E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr2_field_t; + +typedef struct +{ + __IO uint32_t S2RG3RP : 1; + __IO uint32_t S2RG3WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG3E : 1; + __IO uint32_t S1RG3RP : 1; + __IO uint32_t S1RG3WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG3E : 1; + __IO uint32_t FRG3RP : 1; + __IO uint32_t FRG3WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG3E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr3_field_t; + +typedef struct +{ + __IO uint32_t S2RG4RP : 1; + __IO uint32_t S2RG4WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG4E : 1; + __IO uint32_t S1RG4RP : 1; + __IO uint32_t S1RG4WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG4E : 1; + __IO uint32_t FRG4RP : 1; + __IO uint32_t FRG4WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG4E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr4_field_t; + +typedef struct +{ + __IO uint32_t S2RG5RP : 1; + __IO uint32_t S2RG5WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG5E : 1; + __IO uint32_t S1RG5RP : 1; + __IO uint32_t S1RG5WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG5E : 1; + __IO uint32_t FRG5RP : 1; + __IO uint32_t FRG5WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG5E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr5_field_t; + +typedef struct +{ + __IO uint32_t S2RG6RP : 1; + __IO uint32_t S2RG6WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG6E : 1; + __IO uint32_t S1RG6RP : 1; + __IO uint32_t S1RG6WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG6E : 1; + __IO uint32_t FRG6RP : 1; + __IO uint32_t FRG6WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG6E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr6_field_t; + +typedef struct +{ + __IO uint32_t S2RG7RP : 1; + __IO uint32_t S2RG7WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG7E : 1; + __IO uint32_t S1RG7RP : 1; + __IO uint32_t S1RG7WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG7E : 1; + __IO uint32_t FRG7RP : 1; + __IO uint32_t FRG7WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG7E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr7_field_t; + +typedef struct +{ + __IO uint32_t S2RG8RP : 1; + __IO uint32_t S2RG8WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG8E : 1; + __IO uint32_t S1RG8RP : 1; + __IO uint32_t S1RG8WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG8E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr8_field_t; + +typedef struct +{ + __IO uint32_t S2RG9RP : 1; + __IO uint32_t S2RG9WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG9E : 1; + __IO uint32_t S1RG9RP : 1; + __IO uint32_t S1RG9WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG9E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr9_field_t; + +typedef struct +{ + __IO uint32_t S2RG10RP : 1; + __IO uint32_t S2RG10WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG10E : 1; + __IO uint32_t S1RG10RP : 1; + __IO uint32_t S1RG10WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG10E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr10_field_t; + +typedef struct +{ + __IO uint32_t S2RG11RP : 1; + __IO uint32_t S2RG11WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG11E : 1; + __IO uint32_t S1RG11RP : 1; + __IO uint32_t S1RG11WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG11E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr11_field_t; + +typedef struct +{ + __IO uint32_t S2RG12RP : 1; + __IO uint32_t S2RG12WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG12E : 1; + __IO uint32_t S1RG12RP : 1; + __IO uint32_t S1RG12WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG12E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr12_field_t; + +typedef struct +{ + __IO uint32_t S2RG13RP : 1; + __IO uint32_t S2RG13WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG13E : 1; + __IO uint32_t S1RG13RP : 1; + __IO uint32_t S1RG13WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG13E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr13_field_t; + +typedef struct +{ + __IO uint32_t S2RG14RP : 1; + __IO uint32_t S2RG14WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG14E : 1; + __IO uint32_t S1RG14RP : 1; + __IO uint32_t S1RG14WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG14E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr14_field_t; + +typedef struct +{ + __IO uint32_t S2RG15RP : 1; + __IO uint32_t S2RG15WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG15E : 1; + __IO uint32_t S1RG15RP : 1; + __IO uint32_t S1RG15WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG15E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr15_field_t; + +typedef struct +{ + __IO uint32_t SMPU2BRP : 1; + __IO uint32_t SMPU2BWP : 1; + __IO uint32_t SMPU2ACT : 2; + uint32_t RESERVED4 : 3; + __IO uint32_t SMPU2E : 1; + __IO uint32_t SMPU1BRP : 1; + __IO uint32_t SMPU1BWP : 1; + __IO uint32_t SMPU1ACT : 2; + uint32_t RESERVED12 : 3; + __IO uint32_t SMPU1E : 1; + __IO uint32_t FMPUBRP : 1; + __IO uint32_t FMPUBWP : 1; + __IO uint32_t FMPUACT : 2; + uint32_t RESERVED20 : 3; + __IO uint32_t FMPUE : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_cr_field_t; + +typedef struct +{ + __IO uint32_t SMPU2EAF : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SMPU1EAF : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t FMPUEAF : 1; + uint32_t RESERVED17 :15; +} stc_mpu_sr_field_t; + +typedef struct +{ + __IO uint32_t SMPU2ECLR : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SMPU1ECLR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t FMPUECLR : 1; + uint32_t RESERVED17 :15; +} stc_mpu_eclr_field_t; + +typedef struct +{ + __IO uint32_t MPUWE : 1; + __IO uint32_t WKEY :15; + uint32_t RESERVED16 :16; +} stc_mpu_wp_field_t; + +typedef struct +{ + __IO uint32_t SRAMH : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t SRAM12 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t SRAM3 : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SRAMRET : 1; + uint32_t RESERVED11 : 3; + __IO uint32_t DMA1 : 1; + __IO uint32_t DMA2 : 1; + __IO uint32_t FCM : 1; + __IO uint32_t AOS : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t AES : 1; + __IO uint32_t HASH : 1; + __IO uint32_t TRNG : 1; + __IO uint32_t CRC : 1; + __IO uint32_t DCU1 : 1; + __IO uint32_t DCU2 : 1; + __IO uint32_t DCU3 : 1; + __IO uint32_t DCU4 : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t KEY : 1; +} stc_mstp_fcg0_field_t; + +typedef struct +{ + __IO uint32_t CAN : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t QSPI : 1; + __IO uint32_t IIC1 : 1; + __IO uint32_t IIC2 : 1; + __IO uint32_t IIC3 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t USBFS : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SDIOC1 : 1; + __IO uint32_t SDIOC2 : 1; + __IO uint32_t I2S1 : 1; + __IO uint32_t I2S2 : 1; + __IO uint32_t I2S3 : 1; + __IO uint32_t I2S4 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t SPI2 : 1; + __IO uint32_t SPI3 : 1; + __IO uint32_t SPI4 : 1; + uint32_t RESERVED20 : 4; + __IO uint32_t USART1 : 1; + __IO uint32_t USART2 : 1; + __IO uint32_t USART3 : 1; + __IO uint32_t USART4 : 1; + uint32_t RESERVED28 : 4; +} stc_mstp_fcg1_field_t; + +typedef struct +{ + __IO uint32_t TIMER0_1 : 1; + __IO uint32_t TIMER0_2 : 1; + __IO uint32_t TIMERA_1 : 1; + __IO uint32_t TIMERA_2 : 1; + __IO uint32_t TIMERA_3 : 1; + __IO uint32_t TIMERA_4 : 1; + __IO uint32_t TIMERA_5 : 1; + __IO uint32_t TIMERA_6 : 1; + __IO uint32_t TIMER4_1 : 1; + __IO uint32_t TIMER4_2 : 1; + __IO uint32_t TIMER4_3 : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t EMB : 1; + __IO uint32_t TIMER6_1 : 1; + __IO uint32_t TIMER6_2 : 1; + __IO uint32_t TIMER6_3 : 1; + uint32_t RESERVED19 :13; +} stc_mstp_fcg2_field_t; + +typedef struct +{ + __IO uint32_t ADC1 : 1; + __IO uint32_t ADC2 : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t CMP : 1; + uint32_t RESERVED9 : 3; + __IO uint32_t OTS : 1; + uint32_t RESERVED13 :19; +} stc_mstp_fcg3_field_t; + +typedef struct +{ + __IO uint32_t PRT0 : 1; + uint32_t RESERVED1 :15; + __IO uint32_t FCG0PCWE :16; +} stc_mstp_fcg0pc_field_t; + +typedef struct +{ + __IO uint16_t OTSST : 1; + __IO uint16_t OTSCK : 1; + __IO uint16_t OTSIE : 1; + __IO uint16_t TSSTP : 1; + uint16_t RESERVED4 :12; +} stc_ots_ctl_field_t; + +typedef struct +{ + __IO uint32_t TSOFS : 8; + __IO uint32_t TSSLP :24; +} stc_ots_lpr_field_t; + +typedef struct +{ + __IO uint32_t DFB : 1; + __IO uint32_t SOFEN : 1; + uint32_t RESERVED2 :30; +} stc_peric_usbfs_syctlreg_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t SELMMC1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SELMMC2 : 1; + uint32_t RESERVED4 :28; +} stc_peric_sdioc_syctlreg_field_t; + +typedef struct +{ + __IO uint16_t PIN00 : 1; + __IO uint16_t PIN01 : 1; + __IO uint16_t PIN02 : 1; + __IO uint16_t PIN03 : 1; + __IO uint16_t PIN04 : 1; + __IO uint16_t PIN05 : 1; + __IO uint16_t PIN06 : 1; + __IO uint16_t PIN07 : 1; + __IO uint16_t PIN08 : 1; + __IO uint16_t PIN09 : 1; + __IO uint16_t PIN10 : 1; + __IO uint16_t PIN11 : 1; + __IO uint16_t PIN12 : 1; + __IO uint16_t PIN13 : 1; + __IO uint16_t PIN14 : 1; + __IO uint16_t PIN15 : 1; +} stc_port_pidr_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + __IO uint16_t POUT03 : 1; + __IO uint16_t POUT04 : 1; + __IO uint16_t POUT05 : 1; + __IO uint16_t POUT06 : 1; + __IO uint16_t POUT07 : 1; + __IO uint16_t POUT08 : 1; + __IO uint16_t POUT09 : 1; + __IO uint16_t POUT10 : 1; + __IO uint16_t POUT11 : 1; + __IO uint16_t POUT12 : 1; + __IO uint16_t POUT13 : 1; + __IO uint16_t POUT14 : 1; + __IO uint16_t POUT15 : 1; +} stc_port_podr_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + __IO uint16_t POUTE03 : 1; + __IO uint16_t POUTE04 : 1; + __IO uint16_t POUTE05 : 1; + __IO uint16_t POUTE06 : 1; + __IO uint16_t POUTE07 : 1; + __IO uint16_t POUTE08 : 1; + __IO uint16_t POUTE09 : 1; + __IO uint16_t POUTE10 : 1; + __IO uint16_t POUTE11 : 1; + __IO uint16_t POUTE12 : 1; + __IO uint16_t POUTE13 : 1; + __IO uint16_t POUTE14 : 1; + __IO uint16_t POUTE15 : 1; +} stc_port_poer_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + __IO uint16_t POS03 : 1; + __IO uint16_t POS04 : 1; + __IO uint16_t POS05 : 1; + __IO uint16_t POS06 : 1; + __IO uint16_t POS07 : 1; + __IO uint16_t POS08 : 1; + __IO uint16_t POS09 : 1; + __IO uint16_t POS10 : 1; + __IO uint16_t POS11 : 1; + __IO uint16_t POS12 : 1; + __IO uint16_t POS13 : 1; + __IO uint16_t POS14 : 1; + __IO uint16_t POS15 : 1; +} stc_port_posr_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + __IO uint16_t POR03 : 1; + __IO uint16_t POR04 : 1; + __IO uint16_t POR05 : 1; + __IO uint16_t POR06 : 1; + __IO uint16_t POR07 : 1; + __IO uint16_t POR08 : 1; + __IO uint16_t POR09 : 1; + __IO uint16_t POR10 : 1; + __IO uint16_t POR11 : 1; + __IO uint16_t POR12 : 1; + __IO uint16_t POR13 : 1; + __IO uint16_t POR14 : 1; + __IO uint16_t POR15 : 1; +} stc_port_porr_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + __IO uint16_t POT03 : 1; + __IO uint16_t POT04 : 1; + __IO uint16_t POT05 : 1; + __IO uint16_t POT06 : 1; + __IO uint16_t POT07 : 1; + __IO uint16_t POT08 : 1; + __IO uint16_t POT09 : 1; + __IO uint16_t POT10 : 1; + __IO uint16_t POT11 : 1; + __IO uint16_t POT12 : 1; + __IO uint16_t POT13 : 1; + __IO uint16_t POT14 : 1; + __IO uint16_t POT15 : 1; +} stc_port_potr_field_t; + +typedef struct +{ + __IO uint16_t PIN00 : 1; + __IO uint16_t PIN01 : 1; + __IO uint16_t PIN02 : 1; + uint16_t RESERVED3 :13; +} stc_port_pidrh_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_podrh_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + uint16_t RESERVED3 :13; +} stc_port_poerh_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + uint16_t RESERVED3 :13; +} stc_port_posrh_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + uint16_t RESERVED3 :13; +} stc_port_porrh_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_potrh_field_t; + +typedef struct +{ + __IO uint16_t SPFE : 5; + uint16_t RESERVED5 :11; +} stc_port_pspcr_field_t; + +typedef struct +{ + __IO uint16_t BFSEL : 4; + uint16_t RESERVED4 :10; + __IO uint16_t RDWT : 2; +} stc_port_pccr_field_t; + +typedef struct +{ + __IO uint16_t PINAE : 6; + uint16_t RESERVED6 :10; +} stc_port_pinaer_field_t; + +typedef struct +{ + __IO uint16_t WE : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t WP : 8; +} stc_port_pwpr_field_t; + +typedef struct +{ + __IO uint16_t POUT : 1; + __IO uint16_t POUTE : 1; + __IO uint16_t NOD : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t DRV : 2; + __IO uint16_t PUU : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t PIN : 1; + __IO uint16_t INVE : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t INTE : 1; + uint16_t RESERVED13 : 1; + __IO uint16_t LTE : 1; + __IO uint16_t DDIS : 1; +} stc_port_pcr_field_t; + +typedef struct +{ + __IO uint16_t FSEL : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t BFE : 1; + uint16_t RESERVED9 : 7; +} stc_port_pfsr_field_t; + +typedef struct +{ + __IO uint32_t MDSEL : 3; + __IO uint32_t PFE : 1; + __IO uint32_t PFSAE : 1; + __IO uint32_t DCOME : 1; + __IO uint32_t XIPE : 1; + __IO uint32_t SPIMD3 : 1; + __IO uint32_t IPRSL : 2; + __IO uint32_t APRSL : 2; + __IO uint32_t DPRSL : 2; + uint32_t RESERVED14 : 2; + __IO uint32_t DIV : 6; + uint32_t RESERVED22 :10; +} stc_qspi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSHW : 4; + __IO uint32_t SSNW : 2; + uint32_t RESERVED6 :26; +} stc_qspi_cscr_field_t; + +typedef struct +{ + __IO uint32_t AWSL : 2; + __IO uint32_t FOUR_BIC : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t SSNHD : 1; + __IO uint32_t SSNLD : 1; + __IO uint32_t WPOL : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t DMCYCN : 4; + uint32_t RESERVED12 : 3; + __IO uint32_t DUTY : 1; + uint32_t RESERVED16 :16; +} stc_qspi_fcr_field_t; + +typedef struct +{ + __IO uint32_t BUSY : 1; + uint32_t RESERVED1 : 5; + __IO uint32_t XIPF : 1; + __IO uint32_t RAER : 1; + __IO uint32_t PFNUM : 5; + uint32_t RESERVED13 : 1; + __IO uint32_t PFFUL : 1; + __IO uint32_t PFAN : 1; + uint32_t RESERVED16 :16; +} stc_qspi_sr_field_t; + +typedef struct +{ + __IO uint32_t DCOM : 8; + uint32_t RESERVED8 :24; +} stc_qspi_dcom_field_t; + +typedef struct +{ + __IO uint32_t RIC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_ccmd_field_t; + +typedef struct +{ + __IO uint32_t XIPMC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_xcmd_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 7; + __IO uint32_t RAERCLR : 1; + uint32_t RESERVED8 :24; +} stc_qspi_sr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 :26; + __IO uint32_t EXADR : 6; +} stc_qspi_exar_field_t; + +typedef struct +{ + __IO uint32_t RESET : 1; + uint32_t RESERVED1 :31; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + __IO uint32_t ALMFCLR : 1; + __IO uint32_t ONEHZOE : 1; + __IO uint32_t ONEHZSEL : 1; + __IO uint32_t START : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t RWREQ : 1; + __IO uint32_t RWEN : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t PRDIE : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALME : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t LRCEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t RCKSEL : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr3_field_t; + +typedef struct +{ + __IO uint32_t SECU : 4; + __IO uint32_t SECD : 3; + uint32_t RESERVED7 :25; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINU : 4; + __IO uint32_t MIND : 3; + uint32_t RESERVED7 :25; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURU : 4; + __IO uint32_t HOURD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; + uint32_t RESERVED3 :29; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYU : 4; + __IO uint32_t DAYD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; + uint32_t RESERVED5 :27; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARU : 4; + __IO uint32_t YEARD : 4; + uint32_t RESERVED8 :24; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINU : 4; + __IO uint32_t ALMMIND : 3; + uint32_t RESERVED7 :25; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURU : 4; + __IO uint32_t ALMHOURD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; + uint32_t RESERVED7 :25; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t COMP8 : 1; + uint32_t RESERVED1 : 6; + __IO uint32_t COMPEN : 1; + uint32_t RESERVED8 :24; +} stc_rtc_errcrh_field_t; + +typedef struct +{ + __IO uint32_t COMP : 8; + uint32_t RESERVED8 :24; +} stc_rtc_errcrl_field_t; + +typedef struct +{ + __IO uint16_t TBS :12; + uint16_t RESERVED12 : 4; +} stc_sdioc_blksize_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 1; + __IO uint16_t BCE : 1; + __IO uint16_t ATCEN : 2; + __IO uint16_t DDIR : 1; + __IO uint16_t MULB : 1; + uint16_t RESERVED6 :10; +} stc_sdioc_transmode_field_t; + +typedef struct +{ + __IO uint16_t RESTYP : 2; + uint16_t RESERVED2 : 1; + __IO uint16_t CCE : 1; + __IO uint16_t ICE : 1; + __IO uint16_t DAT : 1; + __IO uint16_t TYP : 2; + __IO uint16_t IDX : 6; + uint16_t RESERVED14 : 2; +} stc_sdioc_cmd_field_t; + +typedef struct +{ + __IO uint32_t CIC : 1; + __IO uint32_t CID : 1; + __IO uint32_t DA : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t WTA : 1; + __IO uint32_t RTA : 1; + __IO uint32_t BWE : 1; + __IO uint32_t BRE : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t CIN : 1; + __IO uint32_t CSS : 1; + __IO uint32_t CDL : 1; + __IO uint32_t WPL : 1; + __IO uint32_t DATL : 4; + __IO uint32_t CMDL : 1; + uint32_t RESERVED25 : 7; +} stc_sdioc_pstat_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 1; + __IO uint8_t DW : 1; + __IO uint8_t HSEN : 1; + uint8_t RESERVED3 : 2; + __IO uint8_t EXDW : 1; + __IO uint8_t CDTL : 1; + __IO uint8_t CDSS : 1; +} stc_sdioc_hostcon_field_t; + +typedef struct +{ + __IO uint8_t PWON : 1; + uint8_t RESERVED1 : 7; +} stc_sdioc_pwrcon_field_t; + +typedef struct +{ + __IO uint8_t SABGR : 1; + __IO uint8_t CR : 1; + __IO uint8_t RWC : 1; + __IO uint8_t IABG : 1; + uint8_t RESERVED4 : 4; +} stc_sdioc_blkgpcon_field_t; + +typedef struct +{ + __IO uint16_t ICE : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t CE : 1; + uint16_t RESERVED3 : 5; + __IO uint16_t FS : 8; +} stc_sdioc_clkcon_field_t; + +typedef struct +{ + __IO uint8_t DTO : 4; + uint8_t RESERVED4 : 4; +} stc_sdioc_toutcon_field_t; + +typedef struct +{ + __IO uint8_t RSTA : 1; + __IO uint8_t RSTC : 1; + __IO uint8_t RSTD : 1; + uint8_t RESERVED3 : 5; +} stc_sdioc_sftrst_field_t; + +typedef struct +{ + __IO uint16_t CC : 1; + __IO uint16_t TC : 1; + __IO uint16_t BGE : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWR : 1; + __IO uint16_t BRR : 1; + __IO uint16_t CIST : 1; + __IO uint16_t CRM : 1; + __IO uint16_t CINT : 1; + uint16_t RESERVED9 : 6; + __IO uint16_t EI : 1; +} stc_sdioc_norintst_field_t; + +typedef struct +{ + __IO uint16_t CTOE : 1; + __IO uint16_t CCE : 1; + __IO uint16_t CEBE : 1; + __IO uint16_t CIE : 1; + __IO uint16_t DTOE : 1; + __IO uint16_t DCE : 1; + __IO uint16_t DEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintst_field_t; + +typedef struct +{ + __IO uint16_t CCEN : 1; + __IO uint16_t TCEN : 1; + __IO uint16_t BGEEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWREN : 1; + __IO uint16_t BRREN : 1; + __IO uint16_t CISTEN : 1; + __IO uint16_t CRMEN : 1; + __IO uint16_t CINTEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsten_field_t; + +typedef struct +{ + __IO uint16_t CTOEEN : 1; + __IO uint16_t CCEEN : 1; + __IO uint16_t CEBEEN : 1; + __IO uint16_t CIEEN : 1; + __IO uint16_t DTOEEN : 1; + __IO uint16_t DCEEN : 1; + __IO uint16_t DEBEEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACEEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsten_field_t; + +typedef struct +{ + __IO uint16_t CCSEN : 1; + __IO uint16_t TCSEN : 1; + __IO uint16_t BGESEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWRSEN : 1; + __IO uint16_t BRRSEN : 1; + __IO uint16_t CISTSEN : 1; + __IO uint16_t CRMSEN : 1; + __IO uint16_t CINTSEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsgen_field_t; + +typedef struct +{ + __IO uint16_t CTOESEN : 1; + __IO uint16_t CCESEN : 1; + __IO uint16_t CEBESEN : 1; + __IO uint16_t CIESEN : 1; + __IO uint16_t DTOESEN : 1; + __IO uint16_t DCESEN : 1; + __IO uint16_t DEBESEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACESEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsgen_field_t; + +typedef struct +{ + __IO uint16_t NE : 1; + __IO uint16_t TOE : 1; + __IO uint16_t CE : 1; + __IO uint16_t EBE : 1; + __IO uint16_t IE : 1; + uint16_t RESERVED5 : 2; + __IO uint16_t CMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_atcerrst_field_t; + +typedef struct +{ + __IO uint16_t FNE : 1; + __IO uint16_t FTOE : 1; + __IO uint16_t FCE : 1; + __IO uint16_t FEBE : 1; + __IO uint16_t FIE : 1; + uint16_t RESERVED5 : 2; + __IO uint16_t FCMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_fea_field_t; + +typedef struct +{ + __IO uint16_t FCTOE : 1; + __IO uint16_t FCCE : 1; + __IO uint16_t FCEBE : 1; + __IO uint16_t FCIE : 1; + __IO uint16_t FDTOE : 1; + __IO uint16_t FDCE : 1; + __IO uint16_t FDEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t FACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_fee_field_t; + +typedef struct +{ + __IO uint32_t SPIMDS : 1; + __IO uint32_t TXMDS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t MSTR : 1; + __IO uint32_t SPLPBK : 1; + __IO uint32_t SPLPBK2 : 1; + __IO uint32_t SPE : 1; + __IO uint32_t CSUSPE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t IDIE : 1; + __IO uint32_t MODFE : 1; + __IO uint32_t PATE : 1; + __IO uint32_t PAOE : 1; + __IO uint32_t PAE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cr1_field_t; + +typedef struct +{ + __IO uint32_t FTHLV : 2; + uint32_t RESERVED2 : 4; + __IO uint32_t SPRDTD : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SS0PV : 1; + __IO uint32_t SS1PV : 1; + __IO uint32_t SS2PV : 1; + __IO uint32_t SS3PV : 1; + uint32_t RESERVED12 : 8; + __IO uint32_t MSSI : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t MSSDL : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t MIDI : 3; + uint32_t RESERVED31 : 1; +} stc_spi_cfg1_field_t; + +typedef struct +{ + __IO uint32_t OVRERF : 1; + __IO uint32_t IDLNF : 1; + __IO uint32_t MODFERF : 1; + __IO uint32_t PERF : 1; + __IO uint32_t UDRERF : 1; + __IO uint32_t TDEF : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t RDFF : 1; + uint32_t RESERVED8 :24; +} stc_spi_sr_field_t; + +typedef struct +{ + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MBR : 3; + __IO uint32_t SSA : 3; + __IO uint32_t DSIZE : 4; + __IO uint32_t LSBF : 1; + __IO uint32_t MIDIE : 1; + __IO uint32_t MSSDLE : 1; + __IO uint32_t MSSIE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cfg2_field_t; + +typedef struct +{ + __IO uint32_t SRAM12_RWT : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t SRAM12_WWT : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t SRAM3_RWT : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t SRAM3_WWT : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t SRAMH_RWT : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t SRAMH_WWT : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t SRAMR_RWT : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t SRAMR_WWT : 3; + uint32_t RESERVED31 : 1; +} stc_sramc_wtcr_field_t; + +typedef struct +{ + __IO uint32_t WTPRC : 1; + __IO uint32_t WTPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_wtpr_field_t; + +typedef struct +{ + __IO uint32_t PYOAD : 1; + uint32_t RESERVED1 :15; + __IO uint32_t ECCOAD : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t ECCMOD : 2; + uint32_t RESERVED26 : 6; +} stc_sramc_ckcr_field_t; + +typedef struct +{ + __IO uint32_t CKPRC : 1; + __IO uint32_t CKPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_ckpr_field_t; + +typedef struct +{ + __IO uint32_t SRAM3_1ERR : 1; + __IO uint32_t SRAM3_2ERR : 1; + __IO uint32_t SRAM12_PYERR : 1; + __IO uint32_t SRAMH_PYERR : 1; + __IO uint32_t SRAMR_PYERR : 1; + uint32_t RESERVED5 :27; +} stc_sramc_cksr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_swdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_swdt_rr_field_t; + +typedef struct +{ + __IO uint16_t FLNWT : 1; + __IO uint16_t CKSMRC : 1; + uint16_t RESERVED2 :13; + __IO uint16_t STOP : 1; +} stc_sysreg_pwr_stpmcr_field_t; + +typedef struct +{ + __IO uint16_t PERICKSEL : 4; + uint16_t RESERVED4 :12; +} stc_sysreg_cmu_pericksel_field_t; + +typedef struct +{ + __IO uint16_t I2S1CKSEL : 4; + __IO uint16_t I2S2CKSEL : 4; + __IO uint16_t I2S3CKSEL : 4; + __IO uint16_t I2S4CKSEL : 4; +} stc_sysreg_cmu_i2scksel_field_t; + +typedef struct +{ + __IO uint32_t RAMPDC0 : 1; + __IO uint32_t RAMPDC1 : 1; + __IO uint32_t RAMPDC2 : 1; + __IO uint32_t RAMPDC3 : 1; + __IO uint32_t RAMPDC4 : 1; + __IO uint32_t RAMPDC5 : 1; + __IO uint32_t RAMPDC6 : 1; + __IO uint32_t RAMPDC7 : 1; + __IO uint32_t RAMPDC8 : 1; + uint32_t RESERVED9 :23; +} stc_sysreg_pwr_rampc0_field_t; + +typedef struct +{ + __IO uint32_t AESRDP : 1; + __IO uint32_t AESWRP : 1; + __IO uint32_t HASHRDP : 1; + __IO uint32_t HASHWRP : 1; + __IO uint32_t TRNGRDP : 1; + __IO uint32_t TRNGWRP : 1; + __IO uint32_t CRCRDP : 1; + __IO uint32_t CRCWRP : 1; + __IO uint32_t FMCRDP : 1; + __IO uint32_t FMCWRP : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t WDTRDP : 1; + __IO uint32_t WDTWRP : 1; + __IO uint32_t SWDTRDP : 1; + __IO uint32_t SWDTWRP : 1; + __IO uint32_t BKSRAMRDP : 1; + __IO uint32_t BKSRAMWRP : 1; + __IO uint32_t RTCRDP : 1; + __IO uint32_t RTCWRP : 1; + __IO uint32_t DMPURDP : 1; + __IO uint32_t DMPUWRP : 1; + __IO uint32_t SRAMCRDP : 1; + __IO uint32_t SRAMCWRP : 1; + __IO uint32_t INTCRDP : 1; + __IO uint32_t INTCWRP : 1; + __IO uint32_t SYSCRDP : 1; + __IO uint32_t SYSCWRP : 1; + __IO uint32_t MSTPRDP : 1; + __IO uint32_t MSTPWRP : 1; + uint32_t RESERVED30 : 1; + __IO uint32_t BUSERRE : 1; +} stc_sysreg_mpu_ippr_field_t; + +typedef struct +{ + __IO uint32_t PCLK0S : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t PCLK1S : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t PCLK2S : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t PCLK3S : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t PCLK4S : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t EXCKS : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t HCLKS : 3; + uint32_t RESERVED27 : 5; +} stc_sysreg_cmu_scfgr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t USBCKS : 4; +} stc_sysreg_cmu_ufsckcfgr_field_t; + +typedef struct +{ + __IO uint8_t CKSW : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_ckswr_field_t; + +typedef struct +{ + __IO uint8_t MPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_pllcr_field_t; + +typedef struct +{ + __IO uint8_t UPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_upllcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalcr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_hrccr_field_t; + +typedef struct +{ + __IO uint8_t MRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_mrccr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTBF : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t XTALSTBF : 1; + uint8_t RESERVED4 : 1; + __IO uint8_t MPLLSTBF : 1; + __IO uint8_t UPLLSTBF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_cmu_oscstbsr_field_t; + +typedef struct +{ + __IO uint8_t MCO1SEL : 4; + __IO uint8_t MCO1DIV : 3; + __IO uint8_t MCO1EN : 1; +} stc_sysreg_cmu_mco1cfgr_field_t; + +typedef struct +{ + __IO uint8_t MCO2SEL : 4; + __IO uint8_t MCO2DIV : 3; + __IO uint8_t MCO2EN : 1; +} stc_sysreg_cmu_mco2cfgr_field_t; + +typedef struct +{ + __IO uint8_t TPIUCKS : 2; + uint8_t RESERVED2 : 5; + __IO uint8_t TPIUCKOE : 1; +} stc_sysreg_cmu_tpiuckcfgr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDIE : 1; + __IO uint8_t XTALSTDRE : 1; + __IO uint8_t XTALSTDRIS : 1; + uint8_t RESERVED3 : 4; + __IO uint8_t XTALSTDE : 1; +} stc_sysreg_cmu_xtalstdcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalstdsr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTB : 4; + uint8_t RESERVED4 : 4; +} stc_sysreg_cmu_xtalstbcr_field_t; + +typedef struct +{ + __IO uint16_t PORF : 1; + __IO uint16_t PINRF : 1; + __IO uint16_t BORF : 1; + __IO uint16_t PVD1RF : 1; + __IO uint16_t PVD2RF : 1; + __IO uint16_t WDRF : 1; + __IO uint16_t SWDRF : 1; + __IO uint16_t PDRF : 1; + __IO uint16_t SWRF : 1; + __IO uint16_t MPUERF : 1; + __IO uint16_t RAPERF : 1; + __IO uint16_t RAECRF : 1; + __IO uint16_t CKFERF : 1; + __IO uint16_t XTALERF : 1; + __IO uint16_t MULTIRF : 1; + __IO uint16_t CLRF : 1; +} stc_sysreg_rmu_rstf0_field_t; + +typedef struct +{ + __IO uint8_t PVD1NMIS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t PVD2NMIS : 1; + uint8_t RESERVED5 : 3; +} stc_sysreg_pwr_pvdicr_field_t; + +typedef struct +{ + __IO uint8_t PVD1MON : 1; + __IO uint8_t PVD1DETFLG : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t PVD2MON : 1; + __IO uint8_t PVD2DETFLG : 1; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pvddsr_field_t; + +typedef struct +{ + __IO uint32_t MPLLM : 5; + uint32_t RESERVED5 : 2; + __IO uint32_t PLLSRC : 1; + __IO uint32_t MPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t MPLLR : 4; + __IO uint32_t MPLLQ : 4; + __IO uint32_t MPLLP : 4; +} stc_sysreg_cmu_pllcfgr_field_t; + +typedef struct +{ + __IO uint32_t UPLLM : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t UPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t UPLLR : 4; + __IO uint32_t UPLLQ : 4; + __IO uint32_t UPLLP : 4; +} stc_sysreg_cmu_upllcfgr_field_t; + +typedef struct +{ + __IO uint16_t FPRCB0 : 1; + __IO uint16_t FPRCB1 : 1; + __IO uint16_t FPRCB2 : 1; + __IO uint16_t FPRCB3 : 1; + uint16_t RESERVED4 : 4; + __IO uint16_t FPRCWE : 8; +} stc_sysreg_pwr_fprc_field_t; + +typedef struct +{ + __IO uint8_t PDMDS : 2; + __IO uint8_t VVDRSD : 1; + __IO uint8_t RETRAMSD : 1; + __IO uint8_t IORTN : 2; + uint8_t RESERVED6 : 1; + __IO uint8_t PWDN : 1; +} stc_sysreg_pwr_pwrc0_field_t; + +typedef struct +{ + __IO uint8_t VPLLSD : 1; + __IO uint8_t VHRCSD : 1; + uint8_t RESERVED2 : 4; + __IO uint8_t STPDAS : 2; +} stc_sysreg_pwr_pwrc1_field_t; + +typedef struct +{ + __IO uint8_t DDAS : 4; + __IO uint8_t DVS : 2; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pwrc2_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 2; + __IO uint8_t PDTS : 1; + uint8_t RESERVED3 : 5; +} stc_sysreg_pwr_pwrc3_field_t; + +typedef struct +{ + __IO uint8_t WKE00 : 1; + __IO uint8_t WKE01 : 1; + __IO uint8_t WKE02 : 1; + __IO uint8_t WKE03 : 1; + __IO uint8_t WKE10 : 1; + __IO uint8_t WKE11 : 1; + __IO uint8_t WKE12 : 1; + __IO uint8_t WKE13 : 1; +} stc_sysreg_pwr_pdwke0_field_t; + +typedef struct +{ + __IO uint8_t WKE20 : 1; + __IO uint8_t WKE21 : 1; + __IO uint8_t WKE22 : 1; + __IO uint8_t WKE23 : 1; + __IO uint8_t WKE30 : 1; + __IO uint8_t WKE31 : 1; + __IO uint8_t WKE32 : 1; + __IO uint8_t WKE33 : 1; +} stc_sysreg_pwr_pdwke1_field_t; + +typedef struct +{ + __IO uint8_t VD1WKE : 1; + __IO uint8_t VD2WKE : 1; + __IO uint8_t NMIWKE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t RTCPRDWKE : 1; + __IO uint8_t RTCALMWKE : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKE : 1; +} stc_sysreg_pwr_pdwke2_field_t; + +typedef struct +{ + __IO uint8_t WK0EGS : 1; + __IO uint8_t WK1EGS : 1; + __IO uint8_t WK2EGS : 1; + __IO uint8_t WK3EGS : 1; + __IO uint8_t VD1EGS : 1; + __IO uint8_t VD2EGS : 1; + __IO uint8_t NMIEGS : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkes_field_t; + +typedef struct +{ + __IO uint8_t PTWK0F : 1; + __IO uint8_t PTWK1F : 1; + __IO uint8_t PTWK2F : 1; + __IO uint8_t PTWK3F : 1; + __IO uint8_t VD1WKF : 1; + __IO uint8_t VD2WKF : 1; + __IO uint8_t NMIWKF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkf0_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t RTCPRDWKF : 1; + __IO uint8_t RTCALMWKF : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKF : 1; +} stc_sysreg_pwr_pdwkf1_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t ADBUFE : 1; +} stc_sysreg_pwr_pwcmr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t XTALDRV : 2; + __IO uint8_t XTALMS : 1; + __IO uint8_t SUPDRV : 1; +} stc_sysreg_cmu_xtalcfgr_field_t; + +typedef struct +{ + __IO uint8_t EXVCCINEN : 1; + uint8_t RESERVED1 : 4; + __IO uint8_t PVD1EN : 1; + __IO uint8_t PVD2EN : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr0_field_t; + +typedef struct +{ + __IO uint8_t PVD1IRE : 1; + __IO uint8_t PVD1IRS : 1; + __IO uint8_t PVD1CMPOE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2IRE : 1; + __IO uint8_t PVD2IRS : 1; + __IO uint8_t PVD2CMPOE : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr1_field_t; + +typedef struct +{ + __IO uint8_t PVD1NFDIS : 1; + __IO uint8_t PVD1NFCKS : 2; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2NFDIS : 1; + __IO uint8_t PVD2NFCKS : 2; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdfcr_field_t; + +typedef struct +{ + __IO uint8_t PVD1LVL : 3; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2LVL : 3; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdlcr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32STP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtal32cr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32DRV : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_xtal32cfgr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32NF : 2; + uint8_t RESERVED2 : 6; +} stc_sysreg_cmu_xtal32nfr_field_t; + +typedef struct +{ + __IO uint8_t LRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_lrccr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t CSDIS : 1; +} stc_sysreg_pwr_xtal32cs_field_t; + +typedef struct +{ + __IO uint32_t CNTA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntar_field_t; + +typedef struct +{ + __IO uint32_t CNTB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntbr_field_t; + +typedef struct +{ + __IO uint32_t CMPA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpar_field_t; + +typedef struct +{ + __IO uint32_t CMPB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpbr_field_t; + +typedef struct +{ + __IO uint32_t CSTA : 1; + __IO uint32_t CAPMDA : 1; + __IO uint32_t INTENA : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t CKDIVA : 4; + __IO uint32_t SYNSA : 1; + __IO uint32_t SYNCLKA : 1; + __IO uint32_t ASYNCLKA : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HSTAA : 1; + __IO uint32_t HSTPA : 1; + __IO uint32_t HCLEA : 1; + __IO uint32_t HICPA : 1; + __IO uint32_t CSTB : 1; + __IO uint32_t CAPMDB : 1; + __IO uint32_t INTENB : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t CKDIVB : 4; + __IO uint32_t SYNSB : 1; + __IO uint32_t SYNCLKB : 1; + __IO uint32_t ASYNCLKB : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t HSTAB : 1; + __IO uint32_t HSTPB : 1; + __IO uint32_t HCLEB : 1; + __IO uint32_t HICPB : 1; +} stc_tmr0_bconr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + uint32_t RESERVED1 :15; + __IO uint32_t CMBF : 1; + uint32_t RESERVED17 :15; +} stc_tmr0_stflr_field_t; + +typedef struct +{ + __IO uint16_t OCEH : 1; + __IO uint16_t OCEL : 1; + __IO uint16_t OCPH : 1; + __IO uint16_t OCPL : 1; + __IO uint16_t OCIEH : 1; + __IO uint16_t OCIEL : 1; + __IO uint16_t OCFH : 1; + __IO uint16_t OCFL : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ocsr_field_t; + +typedef struct +{ + __IO uint16_t CHBUFEN : 2; + __IO uint16_t CLBUFEN : 2; + __IO uint16_t MHBUFEN : 2; + __IO uint16_t MLBUFEN : 2; + __IO uint16_t LMCH : 1; + __IO uint16_t LMCL : 1; + __IO uint16_t LMMH : 1; + __IO uint16_t LMML : 1; + __IO uint16_t MCECH : 1; + __IO uint16_t MCECL : 1; + uint16_t RESERVED14 : 2; +} stc_tmr4_ocer_field_t; + +typedef struct +{ + __IO uint16_t OCFDCH : 1; + __IO uint16_t OCFPKH : 1; + __IO uint16_t OCFUCH : 1; + __IO uint16_t OCFZRH : 1; + __IO uint16_t OPDCH : 2; + __IO uint16_t OPPKH : 2; + __IO uint16_t OPUCH : 2; + __IO uint16_t OPZRH : 2; + __IO uint16_t OPNPKH : 2; + __IO uint16_t OPNZRH : 2; +} stc_tmr4_ocmrh_field_t; + +typedef struct +{ + __IO uint32_t OCFDCL : 1; + __IO uint32_t OCFPKL : 1; + __IO uint32_t OCFUCL : 1; + __IO uint32_t OCFZRL : 1; + __IO uint32_t OPDCL : 2; + __IO uint32_t OPPKL : 2; + __IO uint32_t OPUCL : 2; + __IO uint32_t OPZRL : 2; + __IO uint32_t OPNPKL : 2; + __IO uint32_t OPNZRL : 2; + __IO uint32_t EOPNDCL : 2; + __IO uint32_t EOPNUCL : 2; + __IO uint32_t EOPDCL : 2; + __IO uint32_t EOPPKL : 2; + __IO uint32_t EOPUCL : 2; + __IO uint32_t EOPZRL : 2; + __IO uint32_t EOPNPKL : 2; + __IO uint32_t EOPNZRL : 2; +} stc_tmr4_ocmrl_field_t; + +typedef struct +{ + __IO uint16_t CKDIV : 4; + __IO uint16_t CLEAR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BUFEN : 1; + __IO uint16_t IRQPEN : 1; + __IO uint16_t IRQPF : 1; + uint16_t RESERVED10 : 3; + __IO uint16_t IRQZEN : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKEN : 1; +} stc_tmr4_ccsr_field_t; + +typedef struct +{ + __IO uint16_t ZIM : 4; + __IO uint16_t PIM : 4; + __IO uint16_t ZIC : 4; + __IO uint16_t PIC : 4; +} stc_tmr4_cvpr_field_t; + +typedef struct +{ + __IO uint16_t DIVCK : 4; + __IO uint16_t PWMMD : 2; + __IO uint16_t LVLS : 2; + uint16_t RESERVED8 : 8; +} stc_tmr4_pocr_field_t; + +typedef struct +{ + __IO uint16_t RTIDU : 1; + __IO uint16_t RTIDV : 1; + __IO uint16_t RTIDW : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t RTIFU : 1; + __IO uint16_t RTICU : 1; + __IO uint16_t RTEU : 1; + __IO uint16_t RTSU : 1; + __IO uint16_t RTIFV : 1; + __IO uint16_t RTICV : 1; + __IO uint16_t RTEV : 1; + __IO uint16_t RTSV : 1; + __IO uint16_t RTIFW : 1; + __IO uint16_t RTICW : 1; + __IO uint16_t RTEW : 1; + __IO uint16_t RTSW : 1; +} stc_tmr4_rcsr_field_t; + +typedef struct +{ + __IO uint16_t BUFEN : 2; + __IO uint16_t EVTOS : 3; + __IO uint16_t LMC : 1; + uint16_t RESERVED6 : 2; + __IO uint16_t EVTMS : 1; + __IO uint16_t EVTDS : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t DEN : 1; + __IO uint16_t PEN : 1; + __IO uint16_t UEN : 1; + __IO uint16_t ZEN : 1; +} stc_tmr4_scsr_field_t; + +typedef struct +{ + __IO uint16_t AMC : 4; + uint16_t RESERVED4 : 2; + __IO uint16_t MZCE : 1; + __IO uint16_t MPCE : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_scmr_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 7; + __IO uint16_t HOLD : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ecsr_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer1_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer2_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer3_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmr6_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perbr_field_t; + +typedef struct +{ + __IO uint32_t PERC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_percr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t GCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmer_field_t; + +typedef struct +{ + __IO uint32_t GCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmfr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmbr_field_t; + +typedef struct +{ + __IO uint32_t SCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmcr_field_t; + +typedef struct +{ + __IO uint32_t SCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmdr_field_t; + +typedef struct +{ + __IO uint32_t SCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmer_field_t; + +typedef struct +{ + __IO uint32_t SCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmfr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdar_field_t; + +typedef struct +{ + __IO uint32_t DTUB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtubr_field_t; + +typedef struct +{ + __IO uint32_t DTDB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdbr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSKVAL : 2; + uint32_t RESERVED20 :12; +} stc_tmr6_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + __IO uint32_t INTENE : 1; + __IO uint32_t INTENF : 1; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDTE : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; + uint32_t RESERVED20 :12; +} stc_tmr6_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMDA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t EMBVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPMDB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + uint32_t RESERVED25 : 2; + __IO uint32_t EMBVALB : 2; + uint32_t RESERVED29 : 3; +} stc_tmr6_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + __IO uint32_t BSEA : 1; + __IO uint32_t BENB : 1; + __IO uint32_t BSEB : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t BENP : 1; + __IO uint32_t BSEP : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t BENSPA : 1; + __IO uint32_t BSESPA : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t BTRSPA : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t BENSPB : 1; + __IO uint32_t BSESPB : 1; + uint32_t RESERVED26 : 2; + __IO uint32_t BTRSPB : 2; + uint32_t RESERVED30 : 2; +} stc_tmr6_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTBENU : 1; + __IO uint32_t DTBEND : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t SEPA : 1; + uint32_t RESERVED9 :23; +} stc_tmr6_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 9; +} stc_tmr6_fconr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t SPPERIA : 1; + __IO uint32_t SPPERIB : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; + uint32_t RESERVED21 :11; +} stc_tmr6_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + __IO uint32_t CMEF : 1; + __IO uint32_t CMFF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tmr6_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STARTS : 1; +} stc_tmr6_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STOPS : 1; +} stc_tmr6_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + __IO uint32_t HCLE7 : 1; + __IO uint32_t HCLE8 : 1; + __IO uint32_t HCLE9 : 1; + __IO uint32_t HCLE10 : 1; + __IO uint32_t HCLE11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t CLEARS : 1; +} stc_tmr6_hclrr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcdor_field_t; + +typedef struct +{ + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; + __IO uint32_t SSTA3 : 1; + uint32_t RESERVED3 :13; + __IO uint32_t RESV0 : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t RESV : 1; + uint32_t RESERVED25 : 7; +} stc_tmr6_cr_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; + __IO uint32_t SSTP3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLE1 : 1; + __IO uint32_t SCLE2 : 1; + __IO uint32_t SCLE3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmra_cnter_field_t; + +typedef struct +{ + __IO uint32_t PER :16; + uint32_t RESERVED16 :16; +} stc_tmra_perar_field_t; + +typedef struct +{ + __IO uint32_t CMP :16; + uint32_t RESERVED16 :16; +} stc_tmra_cmpar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t DIR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t SYNST : 1; + __IO uint32_t CKDIV : 4; + uint32_t RESERVED8 : 4; + __IO uint32_t ITENOVF : 1; + __IO uint32_t ITENUDF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + uint32_t RESERVED16 :16; +} stc_tmra_bcstr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + __IO uint32_t HCLE2 : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HCLE3 : 1; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + uint32_t RESERVED16 :16; +} stc_tmra_hconr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + uint32_t RESERVED13 :19; +} stc_tmra_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + uint32_t RESERVED13 :19; +} stc_tmra_hcdor_field_t; + +typedef struct +{ + __IO uint32_t ITEN1 : 1; + __IO uint32_t ITEN2 : 1; + __IO uint32_t ITEN3 : 1; + __IO uint32_t ITEN4 : 1; + __IO uint32_t ITEN5 : 1; + __IO uint32_t ITEN6 : 1; + __IO uint32_t ITEN7 : 1; + __IO uint32_t ITEN8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_iconr_field_t; + +typedef struct +{ + __IO uint32_t ETEN1 : 1; + __IO uint32_t ETEN2 : 1; + __IO uint32_t ETEN3 : 1; + __IO uint32_t ETEN4 : 1; + __IO uint32_t ETEN5 : 1; + __IO uint32_t ETEN6 : 1; + __IO uint32_t ETEN7 : 1; + __IO uint32_t ETEN8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_econr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENTG : 1; + __IO uint32_t NOFICKTG : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NOFIENCA : 1; + __IO uint32_t NOFICKCA : 2; + uint32_t RESERVED11 : 1; + __IO uint32_t NOFIENCB : 1; + __IO uint32_t NOFICKCB : 2; + uint32_t RESERVED15 :17; +} stc_tmra_fconr_field_t; + +typedef struct +{ + __IO uint32_t CMPF1 : 1; + __IO uint32_t CMPF2 : 1; + __IO uint32_t CMPF3 : 1; + __IO uint32_t CMPF4 : 1; + __IO uint32_t CMPF5 : 1; + __IO uint32_t CMPF6 : 1; + __IO uint32_t CMPF7 : 1; + __IO uint32_t CMPF8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_stflr_field_t; + +typedef struct +{ + __IO uint32_t BEN : 1; + __IO uint32_t BSE0 : 1; + __IO uint32_t BSE1 : 1; + uint32_t RESERVED3 :29; +} stc_tmra_bconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t HICP0 : 1; + __IO uint32_t HICP1 : 1; + __IO uint32_t HICP2 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t HICP3 : 1; + __IO uint32_t HICP4 : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NOFIENCP : 1; + __IO uint32_t NOFICKCP : 2; + uint32_t RESERVED15 :17; +} stc_tmra_cconr_field_t; + +typedef struct +{ + __IO uint32_t STAC : 2; + __IO uint32_t STPC : 2; + __IO uint32_t CMPC : 2; + __IO uint32_t PERC : 2; + __IO uint32_t FORC : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t OUTEN : 1; + uint32_t RESERVED13 :19; +} stc_tmra_pconr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t RUN : 1; + uint32_t RESERVED2 :30; +} stc_trng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CNT : 3; + uint32_t RESERVED5 :27; +} stc_trng_mr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t FE : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t ORE : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TC : 1; + __IO uint32_t TXE : 1; + __IO uint32_t RTOF : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t MPB : 1; + uint32_t RESERVED17 :15; +} stc_usart_sr_field_t; + +typedef struct +{ + __IO uint32_t TDR : 9; + __IO uint32_t MPID : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t RDR : 9; + uint32_t RESERVED25 : 7; +} stc_usart_dr_field_t; + +typedef struct +{ + __IO uint32_t DIV_FRACTION : 7; + uint32_t RESERVED7 : 1; + __IO uint32_t DIV_INTEGER : 8; + uint32_t RESERVED16 :16; +} stc_usart_brr_field_t; + +typedef struct +{ + __IO uint32_t RTOE : 1; + __IO uint32_t RTOIE : 1; + __IO uint32_t RE : 1; + __IO uint32_t TE : 1; + __IO uint32_t SLME : 1; + __IO uint32_t RIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t TXEIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t PS : 1; + __IO uint32_t PCE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t M : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t OVER8 : 1; + __IO uint32_t CPE : 1; + __IO uint32_t CFE : 1; + uint32_t RESERVED18 : 1; + __IO uint32_t CORE : 1; + __IO uint32_t CRTOF : 1; + uint32_t RESERVED21 : 3; + __IO uint32_t MS : 1; + uint32_t RESERVED25 : 3; + __IO uint32_t ML : 1; + __IO uint32_t FBME : 1; + __IO uint32_t NFE : 1; + __IO uint32_t SBS : 1; +} stc_usart_cr1_field_t; + +typedef struct +{ + __IO uint32_t MPE : 1; + uint32_t RESERVED1 :10; + __IO uint32_t CLKC : 2; + __IO uint32_t STOP : 1; + uint32_t RESERVED14 :18; +} stc_usart_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t SCEN : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t CTSE : 1; + uint32_t RESERVED10 :11; + __IO uint32_t BCN : 3; + uint32_t RESERVED24 : 8; +} stc_usart_cr3_field_t; + +typedef struct +{ + __IO uint32_t PSC : 2; + uint32_t RESERVED2 :30; +} stc_usart_pr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 6; + __IO uint32_t VBUSOVEN : 1; + __IO uint32_t VBUSVAL : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_usbfs_gvbuscfg_field_t; + +typedef struct +{ + __IO uint32_t GINTMSK : 1; + __IO uint32_t HBSTLEN : 4; + __IO uint32_t DMAEN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXFELVL : 1; + __IO uint32_t PTXFELVL : 1; + uint32_t RESERVED9 :23; +} stc_usbfs_gahbcfg_field_t; + +typedef struct +{ + __IO uint32_t TOCAL : 3; + uint32_t RESERVED3 : 3; + __IO uint32_t PHYSEL : 1; + uint32_t RESERVED7 : 3; + __IO uint32_t TRDT : 4; + uint32_t RESERVED14 :15; + __IO uint32_t FHMOD : 1; + __IO uint32_t FDMOD : 1; + uint32_t RESERVED31 : 1; +} stc_usbfs_gusbcfg_field_t; + +typedef struct +{ + __IO uint32_t CSRST : 1; + __IO uint32_t HSRST : 1; + __IO uint32_t FCRST : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t RXFFLSH : 1; + __IO uint32_t TXFFLSH : 1; + __IO uint32_t TXFNUM : 5; + uint32_t RESERVED11 :19; + __IO uint32_t DMAREQ : 1; + __IO uint32_t AHBIDL : 1; +} stc_usbfs_grstctl_field_t; + +typedef struct +{ + __IO uint32_t CMOD : 1; + __IO uint32_t MMIS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOF : 1; + __IO uint32_t RXFNE : 1; + __IO uint32_t NPTXFE : 1; + __IO uint32_t GINAKEFF : 1; + __IO uint32_t GONAKEFF : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSP : 1; + __IO uint32_t USBSUSP : 1; + __IO uint32_t USBRST : 1; + __IO uint32_t ENUMDNE : 1; + __IO uint32_t ISOODRP : 1; + __IO uint32_t EOPF : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPINT : 1; + __IO uint32_t OEPINT : 1; + __IO uint32_t IISOIXFR : 1; + __IO uint32_t IPXFR_INCOMPISOOUT : 1; + __IO uint32_t DATAFSUSP : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTINT : 1; + __IO uint32_t HCINT : 1; + __IO uint32_t PTXFE : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHG : 1; + __IO uint32_t DISCINT : 1; + __IO uint32_t VBUSVINT : 1; + __IO uint32_t WKUINT : 1; +} stc_usbfs_gintsts_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t MMISM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOFM : 1; + __IO uint32_t RXFNEM : 1; + __IO uint32_t NPTXFEM : 1; + __IO uint32_t GINAKEFFM : 1; + __IO uint32_t GONAKEFFM : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSPM : 1; + __IO uint32_t USBSUSPM : 1; + __IO uint32_t USBRSTM : 1; + __IO uint32_t ENUMDNEM : 1; + __IO uint32_t ISOODRPM : 1; + __IO uint32_t EOPFM : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPIM : 1; + __IO uint32_t OEPIM : 1; + __IO uint32_t IISOIXFRM : 1; + __IO uint32_t IPXFRM_INCOMPISOOUTM : 1; + __IO uint32_t DATAFSUSPM : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTIM : 1; + __IO uint32_t HCIM : 1; + __IO uint32_t PTXFEM : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHGM : 1; + __IO uint32_t DISCIM : 1; + __IO uint32_t VBUSVIM : 1; + __IO uint32_t WKUIM : 1; +} stc_usbfs_gintmsk_field_t; + +typedef struct +{ + __IO uint32_t CHNUM_EPNUM : 4; + __IO uint32_t BCNT :11; + __IO uint32_t DPID : 2; + __IO uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsr_field_t; + +typedef struct +{ + __IO uint32_t CHNUM_EPNUM : 4; + __IO uint32_t BCNT :11; + __IO uint32_t DPID : 2; + __IO uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsp_field_t; + +typedef struct +{ + __IO uint32_t RXFD :11; + uint32_t RESERVED11 :21; +} stc_usbfs_grxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSA :16; + __IO uint32_t NPTXFD :16; +} stc_usbfs_hnptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSAV :16; + __IO uint32_t NPTQXSAV : 8; + __IO uint32_t NPTXQTOP : 7; + uint32_t RESERVED31 : 1; +} stc_usbfs_hnptxsts_field_t; + +typedef struct +{ + __IO uint32_t PTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t PTXFD :11; + uint32_t RESERVED27 : 5; +} stc_usbfs_hptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t INEPTXFD :10; + uint32_t RESERVED26 : 6; +} stc_usbfs_dieptxf_field_t; + +typedef struct +{ + __IO uint32_t FSLSPCS : 2; + __IO uint32_t FSLSS : 1; + uint32_t RESERVED3 :29; +} stc_usbfs_hcfg_field_t; + +typedef struct +{ + __IO uint32_t FRIVL :16; + uint32_t RESERVED16 :16; +} stc_usbfs_hfir_field_t; + +typedef struct +{ + __IO uint32_t FRNUM :16; + __IO uint32_t FTREM :16; +} stc_usbfs_hfnum_field_t; + +typedef struct +{ + __IO uint32_t PTXFSAVL :16; + __IO uint32_t PTXQSAV : 8; + __IO uint32_t PTXQTOP : 8; +} stc_usbfs_hptxsts_field_t; + +typedef struct +{ + __IO uint32_t HAINT :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haint_field_t; + +typedef struct +{ + __IO uint32_t HAINTM :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haintmsk_field_t; + +typedef struct +{ + __IO uint32_t PCSTS : 1; + __IO uint32_t PCDET : 1; + __IO uint32_t PENA : 1; + __IO uint32_t PENCHNG : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t PRES : 1; + __IO uint32_t PSUSP : 1; + __IO uint32_t PRST : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t PLSTS : 2; + __IO uint32_t PWPR : 1; + uint32_t RESERVED13 : 4; + __IO uint32_t PSPD : 2; + uint32_t RESERVED19 :13; +} stc_usbfs_hprt_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + __IO uint32_t EPNUM : 4; + __IO uint32_t EPDIR : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t LSDEV : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 2; + __IO uint32_t DAD : 7; + __IO uint32_t ODDFRM : 1; + __IO uint32_t CHDIS : 1; + __IO uint32_t CHENA : 1; +} stc_usbfs_hcchar_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t CHH : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t NAK : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERR : 1; + __IO uint32_t BBERR : 1; + __IO uint32_t FRMOR : 1; + __IO uint32_t DTERR : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcint_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t CHHM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALLM : 1; + __IO uint32_t NAKM : 1; + __IO uint32_t ACKM : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERRM : 1; + __IO uint32_t BBERRM : 1; + __IO uint32_t FRMORM : 1; + __IO uint32_t DTERRM : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcintmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + __IO uint32_t DPID : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_hctsiz_field_t; + +typedef struct +{ + __IO uint32_t DSPD : 2; + __IO uint32_t NZLSOHSK : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t DAD : 7; + __IO uint32_t PFIVL : 2; + uint32_t RESERVED13 :19; +} stc_usbfs_dcfg_field_t; + +typedef struct +{ + __IO uint32_t RWUSIG : 1; + __IO uint32_t SDIS : 1; + __IO uint32_t GINSTS : 1; + __IO uint32_t GONSTS : 1; + uint32_t RESERVED4 : 3; + __IO uint32_t SGINAK : 1; + __IO uint32_t CGINAK : 1; + __IO uint32_t SGONAK : 1; + __IO uint32_t CGONAK : 1; + __IO uint32_t POPRGDNE : 1; + uint32_t RESERVED12 :20; +} stc_usbfs_dctl_field_t; + +typedef struct +{ + __IO uint32_t SUSPSTS : 1; + __IO uint32_t ENUMSPD : 2; + __IO uint32_t EERR : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t FNSOF :14; + uint32_t RESERVED22 :10; +} stc_usbfs_dsts_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOM : 1; + __IO uint32_t ITTXFEMSK : 1; + __IO uint32_t INEPNMM : 1; + __IO uint32_t INEPNEM : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_diepmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUPM : 1; + __IO uint32_t OTEPDM : 1; + uint32_t RESERVED5 :27; +} stc_usbfs_doepmsk_field_t; + +typedef struct +{ + __IO uint32_t IEPINT : 6; + uint32_t RESERVED6 :10; + __IO uint32_t OEPINT : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daint_field_t; + +typedef struct +{ + __IO uint32_t IEPINTM : 6; + uint32_t RESERVED6 :10; + __IO uint32_t OEPINTM : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daintmsk_field_t; + +typedef struct +{ + __IO uint32_t INEPTXFEM : 6; + uint32_t RESERVED6 :26; +} stc_usbfs_diepempmsk_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __IO uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __IO uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint0_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 2; + uint32_t RESERVED21 :11; +} stc_usbfs_dieptsiz0_field_t; + +typedef struct +{ + __IO uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __IO uint32_t USBAEP : 1; + __IO uint32_t EONUM_DPID : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + __IO uint32_t SD0PID_SEVNFRM : 1; + __IO uint32_t SODDFRM : 1; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __IO uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_dieptsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __IO uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUP : 1; + __IO uint32_t OTEPDIS : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t B2BSTUP : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_doepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 1; + uint32_t RESERVED20 : 9; + __IO uint32_t STUPCNT : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_doeptsiz0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __IO uint32_t USBAEP : 1; + __IO uint32_t DPID : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + __IO uint32_t SD0PID : 1; + __IO uint32_t SD1PID : 1; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_doeptsiz_field_t; + +typedef struct +{ + __IO uint32_t STPPCLK : 1; + __IO uint32_t GATEHCLK : 1; + uint32_t RESERVED2 :30; +} stc_usbfs_pcgcctl_field_t; + +typedef struct +{ + __IO uint32_t PERI : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t CKS : 4; + __IO uint32_t WDPT : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SLPOFF : 1; + uint32_t RESERVED17 :14; + __IO uint32_t ITS : 1; +} stc_wdt_cr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_wdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_wdt_rr_field_t; + +typedef struct +{ + __IO uint16_t WKTMCMP :12; + __IO uint16_t WKOVF : 1; + __IO uint16_t WKCKS : 2; + __IO uint16_t WKTCE : 1; +} stc_wktm_cr_field_t; + + +typedef struct +{ + union + { + __IO uint8_t STR; + stc_adc_str_field_t STR_f; + }; + uint8_t RESERVED1[1]; + union + { + __IO uint16_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint16_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint16_t TRGSR; + stc_adc_trgsr_field_t TRGSR_f; + }; + __IO uint16_t CHSELRA0; + union + { + __IO uint16_t CHSELRA1; + stc_adc_chselra1_field_t CHSELRA1_f; + }; + __IO uint16_t CHSELRB0; + union + { + __IO uint16_t CHSELRB1; + stc_adc_chselrb1_field_t CHSELRB1_f; + }; + __IO uint16_t AVCHSELR0; + union + { + __IO uint16_t AVCHSELR1; + stc_adc_avchselr1_field_t AVCHSELR1_f; + }; + uint8_t RESERVED10[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED27[7]; + union + { + __IO uint16_t CHMUXR0; + stc_adc_chmuxr0_field_t CHMUXR0_f; + }; + union + { + __IO uint16_t CHMUXR1; + stc_adc_chmuxr1_field_t CHMUXR1_f; + }; + union + { + __IO uint16_t CHMUXR2; + stc_adc_chmuxr2_field_t CHMUXR2_f; + }; + union + { + __IO uint16_t CHMUXR3; + stc_adc_chmuxr3_field_t CHMUXR3_f; + }; + uint8_t RESERVED31[6]; + union + { + __IO uint8_t ISR; + stc_adc_isr_field_t ISR_f; + }; + union + { + __IO uint8_t ICR; + stc_adc_icr_field_t ICR_f; + }; + uint8_t RESERVED33[4]; + union + { + __IO uint16_t SYNCCR; + stc_adc_synccr_field_t SYNCCR_f; + }; + uint8_t RESERVED34[2]; + __IO uint16_t DR0; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t DR3; + __IO uint16_t DR4; + __IO uint16_t DR5; + __IO uint16_t DR6; + __IO uint16_t DR7; + __IO uint16_t DR8; + __IO uint16_t DR9; + __IO uint16_t DR10; + __IO uint16_t DR11; + __IO uint16_t DR12; + __IO uint16_t DR13; + __IO uint16_t DR14; + __IO uint16_t DR15; + __IO uint16_t DR16; + uint8_t RESERVED51[46]; + union + { + __IO uint16_t AWDCR; + stc_adc_awdcr_field_t AWDCR_f; + }; + uint8_t RESERVED52[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED54[4]; + __IO uint16_t AWDCHSR0; + union + { + __IO uint16_t AWDCHSR1; + stc_adc_awdchsr1_field_t AWDCHSR1_f; + }; + __IO uint16_t AWDSR0; + union + { + __IO uint16_t AWDSR1; + stc_adc_awdsr1_field_t AWDSR1_f; + }; + uint8_t RESERVED58[12]; + union + { + __IO uint16_t PGACR; + stc_adc_pgacr_field_t PGACR_f; + }; + union + { + __IO uint16_t PGAGSR; + stc_adc_pgagsr_field_t PGAGSR_f; + }; + uint8_t RESERVED60[8]; + union + { + __IO uint16_t PGAINSR0; + stc_adc_pgainsr0_field_t PGAINSR0_f; + }; + union + { + __IO uint16_t PGAINSR1; + stc_adc_pgainsr1_field_t PGAINSR1_f; + }; +}M4_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +}M4_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t INT_SFTTRG; + stc_aos_int_sfttrg_field_t INT_SFTTRG_f; + }; + union + { + __IO uint32_t DCU1_TRGSEL; + stc_aos_dcu1_trgsel_field_t DCU1_TRGSEL_f; + }; + union + { + __IO uint32_t DCU2_TRGSEL; + stc_aos_dcu2_trgsel_field_t DCU2_TRGSEL_f; + }; + union + { + __IO uint32_t DCU3_TRGSEL; + stc_aos_dcu3_trgsel_field_t DCU3_TRGSEL_f; + }; + union + { + __IO uint32_t DCU4_TRGSEL; + stc_aos_dcu4_trgsel_field_t DCU4_TRGSEL_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL0; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL1; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL2; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL3; + stc_aos_dma1_trgsel3_field_t DMA1_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL0; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL1; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL2; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL3; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA_TRGSELRC; + stc_aos_dma_trgselrc_field_t DMA_TRGSELRC_f; + }; + union + { + __IO uint32_t TMR6_HTSSR1; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR1_f; + }; + union + { + __IO uint32_t TMR6_HTSSR2; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR2_f; + }; + union + { + __IO uint32_t TMR0_HTSSR; + stc_aos_tmr0_htssr_field_t TMR0_HTSSR_f; + }; + union + { + __IO uint32_t PORT_PEVNTTRGSR12; + stc_aos_port_pevnttrgsr12_field_t PORT_PEVNTTRGSR12_f; + }; + union + { + __IO uint32_t PORT_PEVNTTRGSR34; + stc_aos_port_pevnttrgsr34_field_t PORT_PEVNTTRGSR34_f; + }; + union + { + __IO uint32_t TMRA_HTSSR0; + stc_aos_tmra_htssr_field_t TMRA_HTSSR0_f; + }; + union + { + __IO uint32_t TMRA_HTSSR1; + stc_aos_tmra_htssr_field_t TMRA_HTSSR1_f; + }; + union + { + __IO uint32_t OTS_TRG; + stc_aos_ots_trg_field_t OTS_TRG_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR0; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR1; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR1_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR0; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR1; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR1_f; + }; + union + { + __IO uint32_t COMTRG1; + stc_aos_comtrg1_field_t COMTRG1_f; + }; + union + { + __IO uint32_t COMTRG2; + stc_aos_comtrg2_field_t COMTRG2_f; + }; + uint8_t RESERVED28[144]; + union + { + __IO uint32_t PEVNTDIRR1; + stc_aos_pevntdirr_field_t PEVNTDIRR1_f; + }; + union + { + __IO uint32_t PEVNTIDR1; + stc_aos_pevntidr_field_t PEVNTIDR1_f; + }; + union + { + __IO uint32_t PEVNTODR1; + stc_aos_pevntodr_field_t PEVNTODR1_f; + }; + union + { + __IO uint32_t PEVNTORR1; + stc_aos_pevntorr_field_t PEVNTORR1_f; + }; + union + { + __IO uint32_t PEVNTOSR1; + stc_aos_pevntosr_field_t PEVNTOSR1_f; + }; + union + { + __IO uint32_t PEVNTRISR1; + stc_aos_pevntrisr_field_t PEVNTRISR1_f; + }; + union + { + __IO uint32_t PEVNTFAL1; + stc_aos_pevntfal_field_t PEVNTFAL1_f; + }; + union + { + __IO uint32_t PEVNTDIRR2; + stc_aos_pevntdirr_field_t PEVNTDIRR2_f; + }; + union + { + __IO uint32_t PEVNTIDR2; + stc_aos_pevntidr_field_t PEVNTIDR2_f; + }; + union + { + __IO uint32_t PEVNTODR2; + stc_aos_pevntodr_field_t PEVNTODR2_f; + }; + union + { + __IO uint32_t PEVNTORR2; + stc_aos_pevntorr_field_t PEVNTORR2_f; + }; + union + { + __IO uint32_t PEVNTOSR2; + stc_aos_pevntosr_field_t PEVNTOSR2_f; + }; + union + { + __IO uint32_t PEVNTRISR2; + stc_aos_pevntrisr_field_t PEVNTRISR2_f; + }; + union + { + __IO uint32_t PEVNTFAL2; + stc_aos_pevntfal_field_t PEVNTFAL2_f; + }; + union + { + __IO uint32_t PEVNTDIRR3; + stc_aos_pevntdirr_field_t PEVNTDIRR3_f; + }; + union + { + __IO uint32_t PEVNTIDR3; + stc_aos_pevntidr_field_t PEVNTIDR3_f; + }; + union + { + __IO uint32_t PEVNTODR3; + stc_aos_pevntodr_field_t PEVNTODR3_f; + }; + union + { + __IO uint32_t PEVNTORR3; + stc_aos_pevntorr_field_t PEVNTORR3_f; + }; + union + { + __IO uint32_t PEVNTOSR3; + stc_aos_pevntosr_field_t PEVNTOSR3_f; + }; + union + { + __IO uint32_t PEVNTRISR3; + stc_aos_pevntrisr_field_t PEVNTRISR3_f; + }; + union + { + __IO uint32_t PEVNTFAL3; + stc_aos_pevntfal_field_t PEVNTFAL3_f; + }; + union + { + __IO uint32_t PEVNTDIRR4; + stc_aos_pevntdirr_field_t PEVNTDIRR4_f; + }; + union + { + __IO uint32_t PEVNTIDR4; + stc_aos_pevntidr_field_t PEVNTIDR4_f; + }; + union + { + __IO uint32_t PEVNTODR4; + stc_aos_pevntodr_field_t PEVNTODR4_f; + }; + union + { + __IO uint32_t PEVNTORR4; + stc_aos_pevntorr_field_t PEVNTORR4_f; + }; + union + { + __IO uint32_t PEVNTOSR4; + stc_aos_pevntosr_field_t PEVNTOSR4_f; + }; + union + { + __IO uint32_t PEVNTRISR4; + stc_aos_pevntrisr_field_t PEVNTRISR4_f; + }; + union + { + __IO uint32_t PEVNTFAL4; + stc_aos_pevntfal_field_t PEVNTFAL4_f; + }; + union + { + __IO uint32_t PEVNTNFCR; + stc_aos_pevntnfcr_field_t PEVNTNFCR_f; + }; +}M4_AOS_TypeDef; + +typedef struct +{ + __IO uint32_t RBUF; + uint8_t RESERVED1[76]; + __IO uint32_t TBUF; + uint8_t RESERVED2[76]; + union + { + __IO uint8_t CFG_STAT; + stc_can_cfg_stat_field_t CFG_STAT_f; + }; + union + { + __IO uint8_t TCMD; + stc_can_tcmd_field_t TCMD_f; + }; + union + { + __IO uint8_t TCTRL; + stc_can_tctrl_field_t TCTRL_f; + }; + union + { + __IO uint8_t RCTRL; + stc_can_rctrl_field_t RCTRL_f; + }; + union + { + __IO uint8_t RTIE; + stc_can_rtie_field_t RTIE_f; + }; + union + { + __IO uint8_t RTIF; + stc_can_rtif_field_t RTIF_f; + }; + union + { + __IO uint8_t ERRINT; + stc_can_errint_field_t ERRINT_f; + }; + union + { + __IO uint8_t LIMIT; + stc_can_limit_field_t LIMIT_f; + }; + union + { + __IO uint32_t BT; + stc_can_bt_field_t BT_f; + }; + uint8_t RESERVED11[4]; + union + { + __IO uint8_t EALCAP; + stc_can_ealcap_field_t EALCAP_f; + }; + uint8_t RESERVED12[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + union + { + __IO uint8_t ACFCTRL; + stc_can_acfctrl_field_t ACFCTRL_f; + }; + uint8_t RESERVED15[1]; + union + { + __IO uint8_t ACFEN; + stc_can_acfen_field_t ACFEN_f; + }; + uint8_t RESERVED16[1]; + union + { + __IO uint32_t ACF; + stc_can_acf_field_t ACF_f; + }; + uint8_t RESERVED17[2]; + union + { + __IO uint8_t TBSLOT; + stc_can_tbslot_field_t TBSLOT_f; + }; + union + { + __IO uint8_t TTCFG; + stc_can_ttcfg_field_t TTCFG_f; + }; + union + { + __IO uint32_t REF_MSG; + stc_can_ref_msg_field_t REF_MSG_f; + }; + union + { + __IO uint16_t TRG_CFG; + stc_can_trg_cfg_field_t TRG_CFG_f; + }; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +}M4_CAN_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CTRL; + stc_cmp_ctrl_field_t CTRL_f; + }; + union + { + __IO uint16_t VLTSEL; + stc_cmp_vltsel_field_t VLTSEL_f; + }; + union + { + __IO uint16_t MON; + stc_cmp_mon_field_t MON_f; + }; + union + { + __IO uint16_t CVSSTB; + stc_cmp_cvsstb_field_t CVSSTB_f; + }; + union + { + __IO uint16_t CVSPRD; + stc_cmp_cvsprd_field_t CVSPRD_f; + }; +}M4_CMP_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[256]; + union + { + __IO uint16_t DADR1; + stc_cmp_cr_dadr1_field_t DADR1_f; + }; + union + { + __IO uint16_t DADR2; + stc_cmp_cr_dadr2_field_t DADR2_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint16_t DACR; + stc_cmp_cr_dacr_field_t DACR_f; + }; + uint8_t RESERVED3[2]; + union + { + __IO uint16_t RVADC; + stc_cmp_cr_rvadc_field_t RVADC_f; + }; +}M4_CMP_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + __IO uint32_t RESLT; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t FLG; + stc_crc_flg_field_t FLG_f; + }; + uint8_t RESERVED3[112]; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; +}M4_CRC_TypeDef; + +typedef struct +{ + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __IO uint32_t RESV0; + union + { + __IO uint32_t MCUSTAT; + stc_dbgc_mcustat_field_t MCUSTAT_f; + }; + union + { + __IO uint32_t MCUCTL; + stc_dbgc_mcuctl_field_t MCUCTL_f; + }; + union + { + __IO uint32_t FMCCTL; + stc_dbgc_fmcctl_field_t FMCCTL_f; + }; + union + { + __IO uint32_t MCUDBGSTAT; + stc_dbgc_mcudbgstat_field_t MCUDBGSTAT_f; + }; + union + { + __IO uint32_t MCUSTPCTL; + stc_dbgc_mcustpctl_field_t MCUSTPCTL_f; + }; + union + { + __IO uint32_t MCUTRACECTL; + stc_dbgc_mcutracectl_field_t MCUTRACECTL_f; + }; +}M4_DBGC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_dcu_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t FLAG; + stc_dcu_flag_field_t FLAG_f; + }; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + union + { + __IO uint32_t FLAGCLR; + stc_dcu_flagclr_field_t FLAGCLR_f; + }; + union + { + __IO uint32_t INTSEL; + stc_dcu_intsel_field_t INTSEL_f; + }; +}M4_DCU_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t EN; + stc_dma_en_field_t EN_f; + }; + union + { + __IO uint32_t INTSTAT0; + stc_dma_intstat0_field_t INTSTAT0_f; + }; + union + { + __IO uint32_t INTSTAT1; + stc_dma_intstat1_field_t INTSTAT1_f; + }; + union + { + __IO uint32_t INTMASK0; + stc_dma_intmask0_field_t INTMASK0_f; + }; + union + { + __IO uint32_t INTMASK1; + stc_dma_intmask1_field_t INTMASK1_f; + }; + union + { + __IO uint32_t INTCLR0; + stc_dma_intclr0_field_t INTCLR0_f; + }; + union + { + __IO uint32_t INTCLR1; + stc_dma_intclr1_field_t INTCLR1_f; + }; + union + { + __IO uint32_t CHEN; + stc_dma_chen_field_t CHEN_f; + }; + uint8_t RESERVED8[4]; + union + { + __IO uint32_t CHSTAT; + stc_dma_chstat_field_t CHSTAT_f; + }; + uint8_t RESERVED9[4]; + union + { + __IO uint32_t RCFGCTL; + stc_dma_rcfgctl_field_t RCFGCTL_f; + }; + uint8_t RESERVED10[16]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + union + { + __IO uint32_t DTCTL0; + stc_dma_dtctl_field_t DTCTL0_f; + }; + union + { + __IO uint32_t RPT0; + stc_dma_rpt_field_t RPT0_f; + __IO uint32_t RPTB0; + stc_dma_rptb_field_t RPTB0_f; + }; + union + { + __IO uint32_t SNSEQCTL0; + stc_dma_snseqctl_field_t SNSEQCTL0_f; + __IO uint32_t SNSEQCTLB0; + stc_dma_snseqctlb_field_t SNSEQCTLB0_f; + }; + union + { + __IO uint32_t DNSEQCTL0; + stc_dma_dnseqctl_field_t DNSEQCTL0_f; + __IO uint32_t DNSEQCTLB0; + stc_dma_dnseqctlb_field_t DNSEQCTLB0_f; + }; + union + { + __IO uint32_t LLP0; + stc_dma_llp_field_t LLP0_f; + }; + union + { + __IO uint32_t CH0CTL; + stc_dma_ch0ctl_field_t CH0CTL_f; + }; + __IO uint32_t MONSAR0; + __IO uint32_t MONDAR0; + union + { + __IO uint32_t MONDTCTL0; + stc_dma_mondtctl_field_t MONDTCTL0_f; + }; + union + { + __IO uint32_t MONRPT0; + stc_dma_monrpt_field_t MONRPT0_f; + }; + union + { + __IO uint32_t MONSNSEQCTL0; + stc_dma_monsnseqctl_field_t MONSNSEQCTL0_f; + }; + union + { + __IO uint32_t MONDNSEQCTL0; + stc_dma_mondnseqctl_field_t MONDNSEQCTL0_f; + }; + uint8_t RESERVED27[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + union + { + __IO uint32_t DTCTL1; + stc_dma_dtctl_field_t DTCTL1_f; + }; + union + { + __IO uint32_t RPT1; + stc_dma_rpt_field_t RPT1_f; + __IO uint32_t RPTB1; + stc_dma_rptb_field_t RPTB1_f; + }; + union + { + __IO uint32_t SNSEQCTL1; + stc_dma_snseqctl_field_t SNSEQCTL1_f; + __IO uint32_t SNSEQCTLB1; + stc_dma_snseqctlb_field_t SNSEQCTLB1_f; + }; + union + { + __IO uint32_t DNSEQCTL1; + stc_dma_dnseqctl_field_t DNSEQCTL1_f; + __IO uint32_t DNSEQCTLB1; + stc_dma_dnseqctlb_field_t DNSEQCTLB1_f; + }; + union + { + __IO uint32_t LLP1; + stc_dma_llp_field_t LLP1_f; + }; + union + { + __IO uint32_t CH1CTL; + stc_dma_ch1ctl_field_t CH1CTL_f; + }; + __IO uint32_t MONSAR1; + __IO uint32_t MONDAR1; + union + { + __IO uint32_t MONDTCTL1; + stc_dma_mondtctl_field_t MONDTCTL1_f; + }; + union + { + __IO uint32_t MONRPT1; + stc_dma_monrpt_field_t MONRPT1_f; + }; + union + { + __IO uint32_t MONSNSEQCTL1; + stc_dma_monsnseqctl_field_t MONSNSEQCTL1_f; + }; + union + { + __IO uint32_t MONDNSEQCTL1; + stc_dma_mondnseqctl_field_t MONDNSEQCTL1_f; + }; + uint8_t RESERVED44[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + union + { + __IO uint32_t DTCTL2; + stc_dma_dtctl_field_t DTCTL2_f; + }; + union + { + __IO uint32_t RPT2; + stc_dma_rpt_field_t RPT2_f; + __IO uint32_t RPTB2; + stc_dma_rptb_field_t RPTB2_f; + }; + union + { + __IO uint32_t SNSEQCTL2; + stc_dma_snseqctl_field_t SNSEQCTL2_f; + __IO uint32_t SNSEQCTLB2; + stc_dma_snseqctlb_field_t SNSEQCTLB2_f; + }; + union + { + __IO uint32_t DNSEQCTL2; + stc_dma_dnseqctl_field_t DNSEQCTL2_f; + __IO uint32_t DNSEQCTLB2; + stc_dma_dnseqctlb_field_t DNSEQCTLB2_f; + }; + union + { + __IO uint32_t LLP2; + stc_dma_llp_field_t LLP2_f; + }; + union + { + __IO uint32_t CH2CTL; + stc_dma_ch2ctl_field_t CH2CTL_f; + }; + __IO uint32_t MONSAR2; + __IO uint32_t MONDAR2; + union + { + __IO uint32_t MONDTCTL2; + stc_dma_mondtctl_field_t MONDTCTL2_f; + }; + union + { + __IO uint32_t MONRPT2; + stc_dma_monrpt_field_t MONRPT2_f; + }; + union + { + __IO uint32_t MONSNSEQCTL2; + stc_dma_monsnseqctl_field_t MONSNSEQCTL2_f; + }; + union + { + __IO uint32_t MONDNSEQCTL2; + stc_dma_mondnseqctl_field_t MONDNSEQCTL2_f; + }; + uint8_t RESERVED61[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + union + { + __IO uint32_t DTCTL3; + stc_dma_dtctl_field_t DTCTL3_f; + }; + union + { + __IO uint32_t RPT3; + stc_dma_rpt_field_t RPT3_f; + __IO uint32_t RPTB3; + stc_dma_rptb_field_t RPTB3_f; + }; + union + { + __IO uint32_t SNSEQCTL3; + stc_dma_snseqctl_field_t SNSEQCTL3_f; + __IO uint32_t SNSEQCTLB3; + stc_dma_snseqctlb_field_t SNSEQCTLB3_f; + }; + union + { + __IO uint32_t DNSEQCTL3; + stc_dma_dnseqctl_field_t DNSEQCTL3_f; + __IO uint32_t DNSEQCTLB3; + stc_dma_dnseqctlb_field_t DNSEQCTLB3_f; + }; + union + { + __IO uint32_t LLP3; + stc_dma_llp_field_t LLP3_f; + }; + union + { + __IO uint32_t CH3CTL; + stc_dma_ch3ctl_field_t CH3CTL_f; + }; + __IO uint32_t MONSAR3; + __IO uint32_t MONDAR3; + union + { + __IO uint32_t MONDTCTL3; + stc_dma_mondtctl_field_t MONDTCTL3_f; + }; + union + { + __IO uint32_t MONRPT3; + stc_dma_monrpt_field_t MONRPT3_f; + }; + union + { + __IO uint32_t MONSNSEQCTL3; + stc_dma_monsnseqctl_field_t MONSNSEQCTL3_f; + }; + union + { + __IO uint32_t MONDNSEQCTL3; + stc_dma_mondnseqctl_field_t MONDNSEQCTL3_f; + }; +}M4_DMA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t FAPRT; + stc_efm_faprt_field_t FAPRT_f; + }; + union + { + __IO uint32_t FSTP; + stc_efm_fstp_field_t FSTP_f; + }; + union + { + __IO uint32_t FRMC; + stc_efm_frmc_field_t FRMC_f; + }; + union + { + __IO uint32_t FWMC; + stc_efm_fwmc_field_t FWMC_f; + }; + union + { + __IO uint32_t FSR; + stc_efm_fsr_field_t FSR_f; + }; + union + { + __IO uint32_t FSCLR; + stc_efm_fsclr_field_t FSCLR_f; + }; + union + { + __IO uint32_t FITE; + stc_efm_fite_field_t FITE_f; + }; + union + { + __IO uint32_t FSWP; + stc_efm_fswp_field_t FSWP_f; + }; + union + { + __IO uint32_t FPMTSW; + stc_efm_fpmtsw_field_t FPMTSW_f; + }; + union + { + __IO uint32_t FPMTEW; + stc_efm_fpmtew_field_t FPMTEW_f; + }; + uint8_t RESERVED10[40]; + __IO uint32_t UQID1; + __IO uint32_t UQID2; + __IO uint32_t UQID3; + uint8_t RESERVED13[164]; + union + { + __IO uint32_t MMF_REMPRT; + stc_efm_mmf_remprt_field_t MMF_REMPRT_f; + }; + union + { + __IO uint32_t MMF_REMCR0; + stc_efm_mmf_remcr0_field_t MMF_REMCR0_f; + }; + union + { + __IO uint32_t MMF_REMCR1; + stc_efm_mmf_remcr1_field_t MMF_REMCR1_f; + }; + uint8_t RESERVED16[248]; + union + { + __IO uint32_t EFM_FRANDS; + stc_efm_efm_frands_field_t EFM_FRANDS_f; + }; +}M4_EFM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_emb_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t PWMLV; + stc_emb_pwmlv_field_t PWMLV_f; + }; + union + { + __IO uint32_t SOE; + stc_emb_soe_field_t SOE_f; + }; + union + { + __IO uint32_t STAT; + stc_emb_stat_field_t STAT_f; + }; + union + { + __IO uint32_t STATCLR; + stc_emb_statclr_field_t STATCLR_f; + }; + union + { + __IO uint32_t INTEN; + stc_emb_inten_field_t INTEN_f; + }; +}M4_EMB_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t LVR; + stc_fcm_lvr_field_t LVR_f; + }; + union + { + __IO uint32_t UVR; + stc_fcm_uvr_field_t UVR_f; + }; + union + { + __IO uint32_t CNTR; + stc_fcm_cntr_field_t CNTR_f; + }; + union + { + __IO uint32_t STR; + stc_fcm_str_field_t STR_f; + }; + union + { + __IO uint32_t MCCR; + stc_fcm_mccr_field_t MCCR_f; + }; + union + { + __IO uint32_t RCCR; + stc_fcm_rccr_field_t RCCR_f; + }; + union + { + __IO uint32_t RIER; + stc_fcm_rier_field_t RIER_f; + }; + union + { + __IO uint32_t SR; + stc_fcm_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_fcm_clr_field_t CLR_f; + }; +}M4_FCM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_hash_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED9[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +}M4_HASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR1; + stc_i2c_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_i2c_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_i2c_cr3_field_t CR3_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t SLR0; + stc_i2c_slr0_field_t SLR0_f; + }; + union + { + __IO uint32_t SLR1; + stc_i2c_slr1_field_t SLR1_f; + }; + union + { + __IO uint32_t SLTR; + stc_i2c_sltr_field_t SLTR_f; + }; + union + { + __IO uint32_t SR; + stc_i2c_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_i2c_clr_field_t CLR_f; + }; + union + { + __IO uint8_t DTR; + stc_i2c_dtr_field_t DTR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t DRR; + stc_i2c_drr_field_t DRR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint32_t CCR; + stc_i2c_ccr_field_t CCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_i2c_fltr_field_t FLTR_f; + }; +}M4_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTRL; + stc_i2s_ctrl_field_t CTRL_f; + }; + union + { + __IO uint32_t SR; + stc_i2s_sr_field_t SR_f; + }; + union + { + __IO uint32_t ER; + stc_i2s_er_field_t ER_f; + }; + union + { + __IO uint32_t CFGR; + stc_i2s_cfgr_field_t CFGR_f; + }; + __IO uint32_t TXBUF; + __IO uint32_t RXBUF; + union + { + __IO uint32_t PR; + stc_i2s_pr_field_t PR_f; + }; +}M4_I2S_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ICG0; + stc_icg_icg0_field_t ICG0_f; + }; + union + { + __IO uint32_t ICG1; + stc_icg_icg1_field_t ICG1_f; + }; + __IO uint32_t ICG2; + __IO uint32_t ICG3; + __IO uint32_t ICG4; + __IO uint32_t ICG5; + __IO uint32_t ICG6; + __IO uint32_t ICG7; +}M4_ICG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t NMICR; + stc_intc_nmicr_field_t NMICR_f; + }; + union + { + __IO uint32_t NMIENR; + stc_intc_nmienr_field_t NMIENR_f; + }; + union + { + __IO uint32_t NMIFR; + stc_intc_nmifr_field_t NMIFR_f; + }; + union + { + __IO uint32_t NMICFR; + stc_intc_nmicfr_field_t NMICFR_f; + }; + union + { + __IO uint32_t EIRQCR0; + stc_intc_eirqcr_field_t EIRQCR0_f; + }; + union + { + __IO uint32_t EIRQCR1; + stc_intc_eirqcr_field_t EIRQCR1_f; + }; + union + { + __IO uint32_t EIRQCR2; + stc_intc_eirqcr_field_t EIRQCR2_f; + }; + union + { + __IO uint32_t EIRQCR3; + stc_intc_eirqcr_field_t EIRQCR3_f; + }; + union + { + __IO uint32_t EIRQCR4; + stc_intc_eirqcr_field_t EIRQCR4_f; + }; + union + { + __IO uint32_t EIRQCR5; + stc_intc_eirqcr_field_t EIRQCR5_f; + }; + union + { + __IO uint32_t EIRQCR6; + stc_intc_eirqcr_field_t EIRQCR6_f; + }; + union + { + __IO uint32_t EIRQCR7; + stc_intc_eirqcr_field_t EIRQCR7_f; + }; + union + { + __IO uint32_t EIRQCR8; + stc_intc_eirqcr_field_t EIRQCR8_f; + }; + union + { + __IO uint32_t EIRQCR9; + stc_intc_eirqcr_field_t EIRQCR9_f; + }; + union + { + __IO uint32_t EIRQCR10; + stc_intc_eirqcr_field_t EIRQCR10_f; + }; + union + { + __IO uint32_t EIRQCR11; + stc_intc_eirqcr_field_t EIRQCR11_f; + }; + union + { + __IO uint32_t EIRQCR12; + stc_intc_eirqcr_field_t EIRQCR12_f; + }; + union + { + __IO uint32_t EIRQCR13; + stc_intc_eirqcr_field_t EIRQCR13_f; + }; + union + { + __IO uint32_t EIRQCR14; + stc_intc_eirqcr_field_t EIRQCR14_f; + }; + union + { + __IO uint32_t EIRQCR15; + stc_intc_eirqcr_field_t EIRQCR15_f; + }; + union + { + __IO uint32_t WUPEN; + stc_intc_wupen_field_t WUPEN_f; + }; + union + { + __IO uint32_t EIFR; + stc_intc_eifr_field_t EIFR_f; + }; + union + { + __IO uint32_t EICFR; + stc_intc_eicfr_field_t EICFR_f; + }; + union + { + __IO uint32_t SEL0; + stc_intc_sel_field_t SEL0_f; + }; + union + { + __IO uint32_t SEL1; + stc_intc_sel_field_t SEL1_f; + }; + union + { + __IO uint32_t SEL2; + stc_intc_sel_field_t SEL2_f; + }; + union + { + __IO uint32_t SEL3; + stc_intc_sel_field_t SEL3_f; + }; + union + { + __IO uint32_t SEL4; + stc_intc_sel_field_t SEL4_f; + }; + union + { + __IO uint32_t SEL5; + stc_intc_sel_field_t SEL5_f; + }; + union + { + __IO uint32_t SEL6; + stc_intc_sel_field_t SEL6_f; + }; + union + { + __IO uint32_t SEL7; + stc_intc_sel_field_t SEL7_f; + }; + union + { + __IO uint32_t SEL8; + stc_intc_sel_field_t SEL8_f; + }; + union + { + __IO uint32_t SEL9; + stc_intc_sel_field_t SEL9_f; + }; + union + { + __IO uint32_t SEL10; + stc_intc_sel_field_t SEL10_f; + }; + union + { + __IO uint32_t SEL11; + stc_intc_sel_field_t SEL11_f; + }; + union + { + __IO uint32_t SEL12; + stc_intc_sel_field_t SEL12_f; + }; + union + { + __IO uint32_t SEL13; + stc_intc_sel_field_t SEL13_f; + }; + union + { + __IO uint32_t SEL14; + stc_intc_sel_field_t SEL14_f; + }; + union + { + __IO uint32_t SEL15; + stc_intc_sel_field_t SEL15_f; + }; + union + { + __IO uint32_t SEL16; + stc_intc_sel_field_t SEL16_f; + }; + union + { + __IO uint32_t SEL17; + stc_intc_sel_field_t SEL17_f; + }; + union + { + __IO uint32_t SEL18; + stc_intc_sel_field_t SEL18_f; + }; + union + { + __IO uint32_t SEL19; + stc_intc_sel_field_t SEL19_f; + }; + union + { + __IO uint32_t SEL20; + stc_intc_sel_field_t SEL20_f; + }; + union + { + __IO uint32_t SEL21; + stc_intc_sel_field_t SEL21_f; + }; + union + { + __IO uint32_t SEL22; + stc_intc_sel_field_t SEL22_f; + }; + union + { + __IO uint32_t SEL23; + stc_intc_sel_field_t SEL23_f; + }; + union + { + __IO uint32_t SEL24; + stc_intc_sel_field_t SEL24_f; + }; + union + { + __IO uint32_t SEL25; + stc_intc_sel_field_t SEL25_f; + }; + union + { + __IO uint32_t SEL26; + stc_intc_sel_field_t SEL26_f; + }; + union + { + __IO uint32_t SEL27; + stc_intc_sel_field_t SEL27_f; + }; + union + { + __IO uint32_t SEL28; + stc_intc_sel_field_t SEL28_f; + }; + union + { + __IO uint32_t SEL29; + stc_intc_sel_field_t SEL29_f; + }; + union + { + __IO uint32_t SEL30; + stc_intc_sel_field_t SEL30_f; + }; + union + { + __IO uint32_t SEL31; + stc_intc_sel_field_t SEL31_f; + }; + union + { + __IO uint32_t SEL32; + stc_intc_sel_field_t SEL32_f; + }; + union + { + __IO uint32_t SEL33; + stc_intc_sel_field_t SEL33_f; + }; + union + { + __IO uint32_t SEL34; + stc_intc_sel_field_t SEL34_f; + }; + union + { + __IO uint32_t SEL35; + stc_intc_sel_field_t SEL35_f; + }; + union + { + __IO uint32_t SEL36; + stc_intc_sel_field_t SEL36_f; + }; + union + { + __IO uint32_t SEL37; + stc_intc_sel_field_t SEL37_f; + }; + union + { + __IO uint32_t SEL38; + stc_intc_sel_field_t SEL38_f; + }; + union + { + __IO uint32_t SEL39; + stc_intc_sel_field_t SEL39_f; + }; + union + { + __IO uint32_t SEL40; + stc_intc_sel_field_t SEL40_f; + }; + union + { + __IO uint32_t SEL41; + stc_intc_sel_field_t SEL41_f; + }; + union + { + __IO uint32_t SEL42; + stc_intc_sel_field_t SEL42_f; + }; + union + { + __IO uint32_t SEL43; + stc_intc_sel_field_t SEL43_f; + }; + union + { + __IO uint32_t SEL44; + stc_intc_sel_field_t SEL44_f; + }; + union + { + __IO uint32_t SEL45; + stc_intc_sel_field_t SEL45_f; + }; + union + { + __IO uint32_t SEL46; + stc_intc_sel_field_t SEL46_f; + }; + union + { + __IO uint32_t SEL47; + stc_intc_sel_field_t SEL47_f; + }; + union + { + __IO uint32_t SEL48; + stc_intc_sel_field_t SEL48_f; + }; + union + { + __IO uint32_t SEL49; + stc_intc_sel_field_t SEL49_f; + }; + union + { + __IO uint32_t SEL50; + stc_intc_sel_field_t SEL50_f; + }; + union + { + __IO uint32_t SEL51; + stc_intc_sel_field_t SEL51_f; + }; + union + { + __IO uint32_t SEL52; + stc_intc_sel_field_t SEL52_f; + }; + union + { + __IO uint32_t SEL53; + stc_intc_sel_field_t SEL53_f; + }; + union + { + __IO uint32_t SEL54; + stc_intc_sel_field_t SEL54_f; + }; + union + { + __IO uint32_t SEL55; + stc_intc_sel_field_t SEL55_f; + }; + union + { + __IO uint32_t SEL56; + stc_intc_sel_field_t SEL56_f; + }; + union + { + __IO uint32_t SEL57; + stc_intc_sel_field_t SEL57_f; + }; + union + { + __IO uint32_t SEL58; + stc_intc_sel_field_t SEL58_f; + }; + union + { + __IO uint32_t SEL59; + stc_intc_sel_field_t SEL59_f; + }; + union + { + __IO uint32_t SEL60; + stc_intc_sel_field_t SEL60_f; + }; + union + { + __IO uint32_t SEL61; + stc_intc_sel_field_t SEL61_f; + }; + union + { + __IO uint32_t SEL62; + stc_intc_sel_field_t SEL62_f; + }; + union + { + __IO uint32_t SEL63; + stc_intc_sel_field_t SEL63_f; + }; + union + { + __IO uint32_t SEL64; + stc_intc_sel_field_t SEL64_f; + }; + union + { + __IO uint32_t SEL65; + stc_intc_sel_field_t SEL65_f; + }; + union + { + __IO uint32_t SEL66; + stc_intc_sel_field_t SEL66_f; + }; + union + { + __IO uint32_t SEL67; + stc_intc_sel_field_t SEL67_f; + }; + union + { + __IO uint32_t SEL68; + stc_intc_sel_field_t SEL68_f; + }; + union + { + __IO uint32_t SEL69; + stc_intc_sel_field_t SEL69_f; + }; + union + { + __IO uint32_t SEL70; + stc_intc_sel_field_t SEL70_f; + }; + union + { + __IO uint32_t SEL71; + stc_intc_sel_field_t SEL71_f; + }; + union + { + __IO uint32_t SEL72; + stc_intc_sel_field_t SEL72_f; + }; + union + { + __IO uint32_t SEL73; + stc_intc_sel_field_t SEL73_f; + }; + union + { + __IO uint32_t SEL74; + stc_intc_sel_field_t SEL74_f; + }; + union + { + __IO uint32_t SEL75; + stc_intc_sel_field_t SEL75_f; + }; + union + { + __IO uint32_t SEL76; + stc_intc_sel_field_t SEL76_f; + }; + union + { + __IO uint32_t SEL77; + stc_intc_sel_field_t SEL77_f; + }; + union + { + __IO uint32_t SEL78; + stc_intc_sel_field_t SEL78_f; + }; + union + { + __IO uint32_t SEL79; + stc_intc_sel_field_t SEL79_f; + }; + union + { + __IO uint32_t SEL80; + stc_intc_sel_field_t SEL80_f; + }; + union + { + __IO uint32_t SEL81; + stc_intc_sel_field_t SEL81_f; + }; + union + { + __IO uint32_t SEL82; + stc_intc_sel_field_t SEL82_f; + }; + union + { + __IO uint32_t SEL83; + stc_intc_sel_field_t SEL83_f; + }; + union + { + __IO uint32_t SEL84; + stc_intc_sel_field_t SEL84_f; + }; + union + { + __IO uint32_t SEL85; + stc_intc_sel_field_t SEL85_f; + }; + union + { + __IO uint32_t SEL86; + stc_intc_sel_field_t SEL86_f; + }; + union + { + __IO uint32_t SEL87; + stc_intc_sel_field_t SEL87_f; + }; + union + { + __IO uint32_t SEL88; + stc_intc_sel_field_t SEL88_f; + }; + union + { + __IO uint32_t SEL89; + stc_intc_sel_field_t SEL89_f; + }; + union + { + __IO uint32_t SEL90; + stc_intc_sel_field_t SEL90_f; + }; + union + { + __IO uint32_t SEL91; + stc_intc_sel_field_t SEL91_f; + }; + union + { + __IO uint32_t SEL92; + stc_intc_sel_field_t SEL92_f; + }; + union + { + __IO uint32_t SEL93; + stc_intc_sel_field_t SEL93_f; + }; + union + { + __IO uint32_t SEL94; + stc_intc_sel_field_t SEL94_f; + }; + union + { + __IO uint32_t SEL95; + stc_intc_sel_field_t SEL95_f; + }; + union + { + __IO uint32_t SEL96; + stc_intc_sel_field_t SEL96_f; + }; + union + { + __IO uint32_t SEL97; + stc_intc_sel_field_t SEL97_f; + }; + union + { + __IO uint32_t SEL98; + stc_intc_sel_field_t SEL98_f; + }; + union + { + __IO uint32_t SEL99; + stc_intc_sel_field_t SEL99_f; + }; + union + { + __IO uint32_t SEL100; + stc_intc_sel_field_t SEL100_f; + }; + union + { + __IO uint32_t SEL101; + stc_intc_sel_field_t SEL101_f; + }; + union + { + __IO uint32_t SEL102; + stc_intc_sel_field_t SEL102_f; + }; + union + { + __IO uint32_t SEL103; + stc_intc_sel_field_t SEL103_f; + }; + union + { + __IO uint32_t SEL104; + stc_intc_sel_field_t SEL104_f; + }; + union + { + __IO uint32_t SEL105; + stc_intc_sel_field_t SEL105_f; + }; + union + { + __IO uint32_t SEL106; + stc_intc_sel_field_t SEL106_f; + }; + union + { + __IO uint32_t SEL107; + stc_intc_sel_field_t SEL107_f; + }; + union + { + __IO uint32_t SEL108; + stc_intc_sel_field_t SEL108_f; + }; + union + { + __IO uint32_t SEL109; + stc_intc_sel_field_t SEL109_f; + }; + union + { + __IO uint32_t SEL110; + stc_intc_sel_field_t SEL110_f; + }; + union + { + __IO uint32_t SEL111; + stc_intc_sel_field_t SEL111_f; + }; + union + { + __IO uint32_t SEL112; + stc_intc_sel_field_t SEL112_f; + }; + union + { + __IO uint32_t SEL113; + stc_intc_sel_field_t SEL113_f; + }; + union + { + __IO uint32_t SEL114; + stc_intc_sel_field_t SEL114_f; + }; + union + { + __IO uint32_t SEL115; + stc_intc_sel_field_t SEL115_f; + }; + union + { + __IO uint32_t SEL116; + stc_intc_sel_field_t SEL116_f; + }; + union + { + __IO uint32_t SEL117; + stc_intc_sel_field_t SEL117_f; + }; + union + { + __IO uint32_t SEL118; + stc_intc_sel_field_t SEL118_f; + }; + union + { + __IO uint32_t SEL119; + stc_intc_sel_field_t SEL119_f; + }; + union + { + __IO uint32_t SEL120; + stc_intc_sel_field_t SEL120_f; + }; + union + { + __IO uint32_t SEL121; + stc_intc_sel_field_t SEL121_f; + }; + union + { + __IO uint32_t SEL122; + stc_intc_sel_field_t SEL122_f; + }; + union + { + __IO uint32_t SEL123; + stc_intc_sel_field_t SEL123_f; + }; + union + { + __IO uint32_t SEL124; + stc_intc_sel_field_t SEL124_f; + }; + union + { + __IO uint32_t SEL125; + stc_intc_sel_field_t SEL125_f; + }; + union + { + __IO uint32_t SEL126; + stc_intc_sel_field_t SEL126_f; + }; + union + { + __IO uint32_t SEL127; + stc_intc_sel_field_t SEL127_f; + }; + union + { + __IO uint32_t VSSEL128; + stc_intc_vssel_field_t VSSEL128_f; + }; + union + { + __IO uint32_t VSSEL129; + stc_intc_vssel_field_t VSSEL129_f; + }; + union + { + __IO uint32_t VSSEL130; + stc_intc_vssel_field_t VSSEL130_f; + }; + union + { + __IO uint32_t VSSEL131; + stc_intc_vssel_field_t VSSEL131_f; + }; + union + { + __IO uint32_t VSSEL132; + stc_intc_vssel_field_t VSSEL132_f; + }; + union + { + __IO uint32_t VSSEL133; + stc_intc_vssel_field_t VSSEL133_f; + }; + union + { + __IO uint32_t VSSEL134; + stc_intc_vssel_field_t VSSEL134_f; + }; + union + { + __IO uint32_t VSSEL135; + stc_intc_vssel_field_t VSSEL135_f; + }; + union + { + __IO uint32_t VSSEL136; + stc_intc_vssel_field_t VSSEL136_f; + }; + union + { + __IO uint32_t VSSEL137; + stc_intc_vssel_field_t VSSEL137_f; + }; + union + { + __IO uint32_t VSSEL138; + stc_intc_vssel_field_t VSSEL138_f; + }; + union + { + __IO uint32_t VSSEL139; + stc_intc_vssel_field_t VSSEL139_f; + }; + union + { + __IO uint32_t VSSEL140; + stc_intc_vssel_field_t VSSEL140_f; + }; + union + { + __IO uint32_t VSSEL141; + stc_intc_vssel_field_t VSSEL141_f; + }; + union + { + __IO uint32_t VSSEL142; + stc_intc_vssel_field_t VSSEL142_f; + }; + union + { + __IO uint32_t VSSEL143; + stc_intc_vssel_field_t VSSEL143_f; + }; + union + { + __IO uint32_t SWIER; + stc_intc_swier_field_t SWIER_f; + }; + union + { + __IO uint32_t EVTER; + stc_intc_evter_field_t EVTER_f; + }; + union + { + __IO uint32_t IER; + stc_intc_ier_field_t IER_f; + }; +}M4_INTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SCR; + stc_keyscan_scr_field_t SCR_f; + }; + union + { + __IO uint32_t SER; + stc_keyscan_ser_field_t SER_f; + }; + union + { + __IO uint32_t SSR; + stc_keyscan_ssr_field_t SSR_f; + }; +}M4_KEYSCAN_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RGD0; + stc_mpu_rgd0_field_t RGD0_f; + }; + union + { + __IO uint32_t RGD1; + stc_mpu_rgd1_field_t RGD1_f; + }; + union + { + __IO uint32_t RGD2; + stc_mpu_rgd2_field_t RGD2_f; + }; + union + { + __IO uint32_t RGD3; + stc_mpu_rgd3_field_t RGD3_f; + }; + union + { + __IO uint32_t RGD4; + stc_mpu_rgd4_field_t RGD4_f; + }; + union + { + __IO uint32_t RGD5; + stc_mpu_rgd5_field_t RGD5_f; + }; + union + { + __IO uint32_t RGD6; + stc_mpu_rgd6_field_t RGD6_f; + }; + union + { + __IO uint32_t RGD7; + stc_mpu_rgd7_field_t RGD7_f; + }; + union + { + __IO uint32_t RGD8; + stc_mpu_rgd8_field_t RGD8_f; + }; + union + { + __IO uint32_t RGD9; + stc_mpu_rgd9_field_t RGD9_f; + }; + union + { + __IO uint32_t RGD10; + stc_mpu_rgd10_field_t RGD10_f; + }; + union + { + __IO uint32_t RGD11; + stc_mpu_rgd11_field_t RGD11_f; + }; + union + { + __IO uint32_t RGD12; + stc_mpu_rgd12_field_t RGD12_f; + }; + union + { + __IO uint32_t RGD13; + stc_mpu_rgd13_field_t RGD13_f; + }; + union + { + __IO uint32_t RGD14; + stc_mpu_rgd14_field_t RGD14_f; + }; + union + { + __IO uint32_t RGD15; + stc_mpu_rgd15_field_t RGD15_f; + }; + union + { + __IO uint32_t RGCR0; + stc_mpu_rgcr0_field_t RGCR0_f; + }; + union + { + __IO uint32_t RGCR1; + stc_mpu_rgcr1_field_t RGCR1_f; + }; + union + { + __IO uint32_t RGCR2; + stc_mpu_rgcr2_field_t RGCR2_f; + }; + union + { + __IO uint32_t RGCR3; + stc_mpu_rgcr3_field_t RGCR3_f; + }; + union + { + __IO uint32_t RGCR4; + stc_mpu_rgcr4_field_t RGCR4_f; + }; + union + { + __IO uint32_t RGCR5; + stc_mpu_rgcr5_field_t RGCR5_f; + }; + union + { + __IO uint32_t RGCR6; + stc_mpu_rgcr6_field_t RGCR6_f; + }; + union + { + __IO uint32_t RGCR7; + stc_mpu_rgcr7_field_t RGCR7_f; + }; + union + { + __IO uint32_t RGCR8; + stc_mpu_rgcr8_field_t RGCR8_f; + }; + union + { + __IO uint32_t RGCR9; + stc_mpu_rgcr9_field_t RGCR9_f; + }; + union + { + __IO uint32_t RGCR10; + stc_mpu_rgcr10_field_t RGCR10_f; + }; + union + { + __IO uint32_t RGCR11; + stc_mpu_rgcr11_field_t RGCR11_f; + }; + union + { + __IO uint32_t RGCR12; + stc_mpu_rgcr12_field_t RGCR12_f; + }; + union + { + __IO uint32_t RGCR13; + stc_mpu_rgcr13_field_t RGCR13_f; + }; + union + { + __IO uint32_t RGCR14; + stc_mpu_rgcr14_field_t RGCR14_f; + }; + union + { + __IO uint32_t RGCR15; + stc_mpu_rgcr15_field_t RGCR15_f; + }; + union + { + __IO uint32_t CR; + stc_mpu_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_mpu_sr_field_t SR_f; + }; + union + { + __IO uint32_t ECLR; + stc_mpu_eclr_field_t ECLR_f; + }; + union + { + __IO uint32_t WP; + stc_mpu_wp_field_t WP_f; + }; +}M4_MPU_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t FCG0; + stc_mstp_fcg0_field_t FCG0_f; + }; + union + { + __IO uint32_t FCG1; + stc_mstp_fcg1_field_t FCG1_f; + }; + union + { + __IO uint32_t FCG2; + stc_mstp_fcg2_field_t FCG2_f; + }; + union + { + __IO uint32_t FCG3; + stc_mstp_fcg3_field_t FCG3_f; + }; + union + { + __IO uint32_t FCG0PC; + stc_mstp_fcg0pc_field_t FCG0PC_f; + }; +}M4_MSTP_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CTL; + stc_ots_ctl_field_t CTL_f; + }; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; + union + { + __IO uint32_t LPR; + stc_ots_lpr_field_t LPR_f; + }; +}M4_OTS_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t USBFS_SYCTLREG; + stc_peric_usbfs_syctlreg_field_t USBFS_SYCTLREG_f; + }; + union + { + __IO uint32_t SDIOC_SYCTLREG; + stc_peric_sdioc_syctlreg_field_t SDIOC_SYCTLREG_f; + }; +}M4_PERIC_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t PIDRA; + stc_port_pidr_field_t PIDRA_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t PODRA; + stc_port_podr_field_t PODRA_f; + }; + union + { + __IO uint16_t POERA; + stc_port_poer_field_t POERA_f; + }; + union + { + __IO uint16_t POSRA; + stc_port_posr_field_t POSRA_f; + }; + union + { + __IO uint16_t PORRA; + stc_port_porr_field_t PORRA_f; + }; + union + { + __IO uint16_t POTRA; + stc_port_potr_field_t POTRA_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint16_t PIDRB; + stc_port_pidr_field_t PIDRB_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t PODRB; + stc_port_podr_field_t PODRB_f; + }; + union + { + __IO uint16_t POERB; + stc_port_poer_field_t POERB_f; + }; + union + { + __IO uint16_t POSRB; + stc_port_posr_field_t POSRB_f; + }; + union + { + __IO uint16_t PORRB; + stc_port_porr_field_t PORRB_f; + }; + union + { + __IO uint16_t POTRB; + stc_port_potr_field_t POTRB_f; + }; + uint8_t RESERVED12[2]; + union + { + __IO uint16_t PIDRC; + stc_port_pidr_field_t PIDRC_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint16_t PODRC; + stc_port_podr_field_t PODRC_f; + }; + union + { + __IO uint16_t POERC; + stc_port_poer_field_t POERC_f; + }; + union + { + __IO uint16_t POSRC; + stc_port_posr_field_t POSRC_f; + }; + union + { + __IO uint16_t PORRC; + stc_port_porr_field_t PORRC_f; + }; + union + { + __IO uint16_t POTRC; + stc_port_potr_field_t POTRC_f; + }; + uint8_t RESERVED18[2]; + union + { + __IO uint16_t PIDRD; + stc_port_pidr_field_t PIDRD_f; + }; + uint8_t RESERVED19[2]; + union + { + __IO uint16_t PODRD; + stc_port_podr_field_t PODRD_f; + }; + union + { + __IO uint16_t POERD; + stc_port_poer_field_t POERD_f; + }; + union + { + __IO uint16_t POSRD; + stc_port_posr_field_t POSRD_f; + }; + union + { + __IO uint16_t PORRD; + stc_port_porr_field_t PORRD_f; + }; + union + { + __IO uint16_t POTRD; + stc_port_potr_field_t POTRD_f; + }; + uint8_t RESERVED24[2]; + union + { + __IO uint16_t PIDRE; + stc_port_pidr_field_t PIDRE_f; + }; + uint8_t RESERVED25[2]; + union + { + __IO uint16_t PODRE; + stc_port_podr_field_t PODRE_f; + }; + union + { + __IO uint16_t POERE; + stc_port_poer_field_t POERE_f; + }; + union + { + __IO uint16_t POSRE; + stc_port_posr_field_t POSRE_f; + }; + union + { + __IO uint16_t PORRE; + stc_port_porr_field_t PORRE_f; + }; + union + { + __IO uint16_t POTRE; + stc_port_potr_field_t POTRE_f; + }; + uint8_t RESERVED30[2]; + union + { + __IO uint16_t PIDRH; + stc_port_pidrh_field_t PIDRH_f; + }; + uint8_t RESERVED31[2]; + union + { + __IO uint16_t PODRH; + stc_port_podrh_field_t PODRH_f; + }; + union + { + __IO uint16_t POERH; + stc_port_poerh_field_t POERH_f; + }; + union + { + __IO uint16_t POSRH; + stc_port_posrh_field_t POSRH_f; + }; + union + { + __IO uint16_t PORRH; + stc_port_porrh_field_t PORRH_f; + }; + union + { + __IO uint16_t POTRH; + stc_port_potrh_field_t POTRH_f; + }; + uint8_t RESERVED36[918]; + union + { + __IO uint16_t PSPCR; + stc_port_pspcr_field_t PSPCR_f; + }; + uint8_t RESERVED37[2]; + union + { + __IO uint16_t PCCR; + stc_port_pccr_field_t PCCR_f; + }; + union + { + __IO uint16_t PINAER; + stc_port_pinaer_field_t PINAER_f; + }; + union + { + __IO uint16_t PWPR; + stc_port_pwpr_field_t PWPR_f; + }; + uint8_t RESERVED40[2]; + union + { + __IO uint16_t PCRA0; + stc_port_pcr_field_t PCRA0_f; + }; + union + { + __IO uint16_t PFSRA0; + stc_port_pfsr_field_t PFSRA0_f; + }; + union + { + __IO uint16_t PCRA1; + stc_port_pcr_field_t PCRA1_f; + }; + union + { + __IO uint16_t PFSRA1; + stc_port_pfsr_field_t PFSRA1_f; + }; + union + { + __IO uint16_t PCRA2; + stc_port_pcr_field_t PCRA2_f; + }; + union + { + __IO uint16_t PFSRA2; + stc_port_pfsr_field_t PFSRA2_f; + }; + union + { + __IO uint16_t PCRA3; + stc_port_pcr_field_t PCRA3_f; + }; + union + { + __IO uint16_t PFSRA3; + stc_port_pfsr_field_t PFSRA3_f; + }; + union + { + __IO uint16_t PCRA4; + stc_port_pcr_field_t PCRA4_f; + }; + union + { + __IO uint16_t PFSRA4; + stc_port_pfsr_field_t PFSRA4_f; + }; + union + { + __IO uint16_t PCRA5; + stc_port_pcr_field_t PCRA5_f; + }; + union + { + __IO uint16_t PFSRA5; + stc_port_pfsr_field_t PFSRA5_f; + }; + union + { + __IO uint16_t PCRA6; + stc_port_pcr_field_t PCRA6_f; + }; + union + { + __IO uint16_t PFSRA6; + stc_port_pfsr_field_t PFSRA6_f; + }; + union + { + __IO uint16_t PCRA7; + stc_port_pcr_field_t PCRA7_f; + }; + union + { + __IO uint16_t PFSRA7; + stc_port_pfsr_field_t PFSRA7_f; + }; + union + { + __IO uint16_t PCRA8; + stc_port_pcr_field_t PCRA8_f; + }; + union + { + __IO uint16_t PFSRA8; + stc_port_pfsr_field_t PFSRA8_f; + }; + union + { + __IO uint16_t PCRA9; + stc_port_pcr_field_t PCRA9_f; + }; + union + { + __IO uint16_t PFSRA9; + stc_port_pfsr_field_t PFSRA9_f; + }; + union + { + __IO uint16_t PCRA10; + stc_port_pcr_field_t PCRA10_f; + }; + union + { + __IO uint16_t PFSRA10; + stc_port_pfsr_field_t PFSRA10_f; + }; + union + { + __IO uint16_t PCRA11; + stc_port_pcr_field_t PCRA11_f; + }; + union + { + __IO uint16_t PFSRA11; + stc_port_pfsr_field_t PFSRA11_f; + }; + union + { + __IO uint16_t PCRA12; + stc_port_pcr_field_t PCRA12_f; + }; + union + { + __IO uint16_t PFSRA12; + stc_port_pfsr_field_t PFSRA12_f; + }; + union + { + __IO uint16_t PCRA13; + stc_port_pcr_field_t PCRA13_f; + }; + union + { + __IO uint16_t PFSRA13; + stc_port_pfsr_field_t PFSRA13_f; + }; + union + { + __IO uint16_t PCRA14; + stc_port_pcr_field_t PCRA14_f; + }; + union + { + __IO uint16_t PFSRA14; + stc_port_pfsr_field_t PFSRA14_f; + }; + union + { + __IO uint16_t PCRA15; + stc_port_pcr_field_t PCRA15_f; + }; + union + { + __IO uint16_t PFSRA15; + stc_port_pfsr_field_t PFSRA15_f; + }; + union + { + __IO uint16_t PCRB0; + stc_port_pcr_field_t PCRB0_f; + }; + union + { + __IO uint16_t PFSRB0; + stc_port_pfsr_field_t PFSRB0_f; + }; + union + { + __IO uint16_t PCRB1; + stc_port_pcr_field_t PCRB1_f; + }; + union + { + __IO uint16_t PFSRB1; + stc_port_pfsr_field_t PFSRB1_f; + }; + union + { + __IO uint16_t PCRB2; + stc_port_pcr_field_t PCRB2_f; + }; + union + { + __IO uint16_t PFSRB2; + stc_port_pfsr_field_t PFSRB2_f; + }; + union + { + __IO uint16_t PCRB3; + stc_port_pcr_field_t PCRB3_f; + }; + union + { + __IO uint16_t PFSRB3; + stc_port_pfsr_field_t PFSRB3_f; + }; + union + { + __IO uint16_t PCRB4; + stc_port_pcr_field_t PCRB4_f; + }; + union + { + __IO uint16_t PFSRB4; + stc_port_pfsr_field_t PFSRB4_f; + }; + union + { + __IO uint16_t PCRB5; + stc_port_pcr_field_t PCRB5_f; + }; + union + { + __IO uint16_t PFSRB5; + stc_port_pfsr_field_t PFSRB5_f; + }; + union + { + __IO uint16_t PCRB6; + stc_port_pcr_field_t PCRB6_f; + }; + union + { + __IO uint16_t PFSRB6; + stc_port_pfsr_field_t PFSRB6_f; + }; + union + { + __IO uint16_t PCRB7; + stc_port_pcr_field_t PCRB7_f; + }; + union + { + __IO uint16_t PFSRB7; + stc_port_pfsr_field_t PFSRB7_f; + }; + union + { + __IO uint16_t PCRB8; + stc_port_pcr_field_t PCRB8_f; + }; + union + { + __IO uint16_t PFSRB8; + stc_port_pfsr_field_t PFSRB8_f; + }; + union + { + __IO uint16_t PCRB9; + stc_port_pcr_field_t PCRB9_f; + }; + union + { + __IO uint16_t PFSRB9; + stc_port_pfsr_field_t PFSRB9_f; + }; + union + { + __IO uint16_t PCRB10; + stc_port_pcr_field_t PCRB10_f; + }; + union + { + __IO uint16_t PFSRB10; + stc_port_pfsr_field_t PFSRB10_f; + }; + union + { + __IO uint16_t PCRB11; + stc_port_pcr_field_t PCRB11_f; + }; + union + { + __IO uint16_t PFSRB11; + stc_port_pfsr_field_t PFSRB11_f; + }; + union + { + __IO uint16_t PCRB12; + stc_port_pcr_field_t PCRB12_f; + }; + union + { + __IO uint16_t PFSRB12; + stc_port_pfsr_field_t PFSRB12_f; + }; + union + { + __IO uint16_t PCRB13; + stc_port_pcr_field_t PCRB13_f; + }; + union + { + __IO uint16_t PFSRB13; + stc_port_pfsr_field_t PFSRB13_f; + }; + union + { + __IO uint16_t PCRB14; + stc_port_pcr_field_t PCRB14_f; + }; + union + { + __IO uint16_t PFSRB14; + stc_port_pfsr_field_t PFSRB14_f; + }; + union + { + __IO uint16_t PCRB15; + stc_port_pcr_field_t PCRB15_f; + }; + union + { + __IO uint16_t PFSRB15; + stc_port_pfsr_field_t PFSRB15_f; + }; + union + { + __IO uint16_t PCRC0; + stc_port_pcr_field_t PCRC0_f; + }; + union + { + __IO uint16_t PFSRC0; + stc_port_pfsr_field_t PFSRC0_f; + }; + union + { + __IO uint16_t PCRC1; + stc_port_pcr_field_t PCRC1_f; + }; + union + { + __IO uint16_t PFSRC1; + stc_port_pfsr_field_t PFSRC1_f; + }; + union + { + __IO uint16_t PCRC2; + stc_port_pcr_field_t PCRC2_f; + }; + union + { + __IO uint16_t PFSRC2; + stc_port_pfsr_field_t PFSRC2_f; + }; + union + { + __IO uint16_t PCRC3; + stc_port_pcr_field_t PCRC3_f; + }; + union + { + __IO uint16_t PFSRC3; + stc_port_pfsr_field_t PFSRC3_f; + }; + union + { + __IO uint16_t PCRC4; + stc_port_pcr_field_t PCRC4_f; + }; + union + { + __IO uint16_t PFSRC4; + stc_port_pfsr_field_t PFSRC4_f; + }; + union + { + __IO uint16_t PCRC5; + stc_port_pcr_field_t PCRC5_f; + }; + union + { + __IO uint16_t PFSRC5; + stc_port_pfsr_field_t PFSRC5_f; + }; + union + { + __IO uint16_t PCRC6; + stc_port_pcr_field_t PCRC6_f; + }; + union + { + __IO uint16_t PFSRC6; + stc_port_pfsr_field_t PFSRC6_f; + }; + union + { + __IO uint16_t PCRC7; + stc_port_pcr_field_t PCRC7_f; + }; + union + { + __IO uint16_t PFSRC7; + stc_port_pfsr_field_t PFSRC7_f; + }; + union + { + __IO uint16_t PCRC8; + stc_port_pcr_field_t PCRC8_f; + }; + union + { + __IO uint16_t PFSRC8; + stc_port_pfsr_field_t PFSRC8_f; + }; + union + { + __IO uint16_t PCRC9; + stc_port_pcr_field_t PCRC9_f; + }; + union + { + __IO uint16_t PFSRC9; + stc_port_pfsr_field_t PFSRC9_f; + }; + union + { + __IO uint16_t PCRC10; + stc_port_pcr_field_t PCRC10_f; + }; + union + { + __IO uint16_t PFSRC10; + stc_port_pfsr_field_t PFSRC10_f; + }; + union + { + __IO uint16_t PCRC11; + stc_port_pcr_field_t PCRC11_f; + }; + union + { + __IO uint16_t PFSRC11; + stc_port_pfsr_field_t PFSRC11_f; + }; + union + { + __IO uint16_t PCRC12; + stc_port_pcr_field_t PCRC12_f; + }; + union + { + __IO uint16_t PFSRC12; + stc_port_pfsr_field_t PFSRC12_f; + }; + union + { + __IO uint16_t PCRC13; + stc_port_pcr_field_t PCRC13_f; + }; + union + { + __IO uint16_t PFSRC13; + stc_port_pfsr_field_t PFSRC13_f; + }; + union + { + __IO uint16_t PCRC14; + stc_port_pcr_field_t PCRC14_f; + }; + union + { + __IO uint16_t PFSRC14; + stc_port_pfsr_field_t PFSRC14_f; + }; + union + { + __IO uint16_t PCRC15; + stc_port_pcr_field_t PCRC15_f; + }; + union + { + __IO uint16_t PFSRC15; + stc_port_pfsr_field_t PFSRC15_f; + }; + union + { + __IO uint16_t PCRD0; + stc_port_pcr_field_t PCRD0_f; + }; + union + { + __IO uint16_t PFSRD0; + stc_port_pfsr_field_t PFSRD0_f; + }; + union + { + __IO uint16_t PCRD1; + stc_port_pcr_field_t PCRD1_f; + }; + union + { + __IO uint16_t PFSRD1; + stc_port_pfsr_field_t PFSRD1_f; + }; + union + { + __IO uint16_t PCRD2; + stc_port_pcr_field_t PCRD2_f; + }; + union + { + __IO uint16_t PFSRD2; + stc_port_pfsr_field_t PFSRD2_f; + }; + union + { + __IO uint16_t PCRD3; + stc_port_pcr_field_t PCRD3_f; + }; + union + { + __IO uint16_t PFSRD3; + stc_port_pfsr_field_t PFSRD3_f; + }; + union + { + __IO uint16_t PCRD4; + stc_port_pcr_field_t PCRD4_f; + }; + union + { + __IO uint16_t PFSRD4; + stc_port_pfsr_field_t PFSRD4_f; + }; + union + { + __IO uint16_t PCRD5; + stc_port_pcr_field_t PCRD5_f; + }; + union + { + __IO uint16_t PFSRD5; + stc_port_pfsr_field_t PFSRD5_f; + }; + union + { + __IO uint16_t PCRD6; + stc_port_pcr_field_t PCRD6_f; + }; + union + { + __IO uint16_t PFSRD6; + stc_port_pfsr_field_t PFSRD6_f; + }; + union + { + __IO uint16_t PCRD7; + stc_port_pcr_field_t PCRD7_f; + }; + union + { + __IO uint16_t PFSRD7; + stc_port_pfsr_field_t PFSRD7_f; + }; + union + { + __IO uint16_t PCRD8; + stc_port_pcr_field_t PCRD8_f; + }; + union + { + __IO uint16_t PFSRD8; + stc_port_pfsr_field_t PFSRD8_f; + }; + union + { + __IO uint16_t PCRD9; + stc_port_pcr_field_t PCRD9_f; + }; + union + { + __IO uint16_t PFSRD9; + stc_port_pfsr_field_t PFSRD9_f; + }; + union + { + __IO uint16_t PCRD10; + stc_port_pcr_field_t PCRD10_f; + }; + union + { + __IO uint16_t PFSRD10; + stc_port_pfsr_field_t PFSRD10_f; + }; + union + { + __IO uint16_t PCRD11; + stc_port_pcr_field_t PCRD11_f; + }; + union + { + __IO uint16_t PFSRD11; + stc_port_pfsr_field_t PFSRD11_f; + }; + union + { + __IO uint16_t PCRD12; + stc_port_pcr_field_t PCRD12_f; + }; + union + { + __IO uint16_t PFSRD12; + stc_port_pfsr_field_t PFSRD12_f; + }; + union + { + __IO uint16_t PCRD13; + stc_port_pcr_field_t PCRD13_f; + }; + union + { + __IO uint16_t PFSRD13; + stc_port_pfsr_field_t PFSRD13_f; + }; + union + { + __IO uint16_t PCRD14; + stc_port_pcr_field_t PCRD14_f; + }; + union + { + __IO uint16_t PFSRD14; + stc_port_pfsr_field_t PFSRD14_f; + }; + union + { + __IO uint16_t PCRD15; + stc_port_pcr_field_t PCRD15_f; + }; + union + { + __IO uint16_t PFSRD15; + stc_port_pfsr_field_t PFSRD15_f; + }; + union + { + __IO uint16_t PCRE0; + stc_port_pcr_field_t PCRE0_f; + }; + union + { + __IO uint16_t PFSRE0; + stc_port_pfsr_field_t PFSRE0_f; + }; + union + { + __IO uint16_t PCRE1; + stc_port_pcr_field_t PCRE1_f; + }; + union + { + __IO uint16_t PFSRE1; + stc_port_pfsr_field_t PFSRE1_f; + }; + union + { + __IO uint16_t PCRE2; + stc_port_pcr_field_t PCRE2_f; + }; + union + { + __IO uint16_t PFSRE2; + stc_port_pfsr_field_t PFSRE2_f; + }; + union + { + __IO uint16_t PCRE3; + stc_port_pcr_field_t PCRE3_f; + }; + union + { + __IO uint16_t PFSRE3; + stc_port_pfsr_field_t PFSRE3_f; + }; + union + { + __IO uint16_t PCRE4; + stc_port_pcr_field_t PCRE4_f; + }; + union + { + __IO uint16_t PFSRE4; + stc_port_pfsr_field_t PFSRE4_f; + }; + union + { + __IO uint16_t PCRE5; + stc_port_pcr_field_t PCRE5_f; + }; + union + { + __IO uint16_t PFSRE5; + stc_port_pfsr_field_t PFSRE5_f; + }; + union + { + __IO uint16_t PCRE6; + stc_port_pcr_field_t PCRE6_f; + }; + union + { + __IO uint16_t PFSRE6; + stc_port_pfsr_field_t PFSRE6_f; + }; + union + { + __IO uint16_t PCRE7; + stc_port_pcr_field_t PCRE7_f; + }; + union + { + __IO uint16_t PFSRE7; + stc_port_pfsr_field_t PFSRE7_f; + }; + union + { + __IO uint16_t PCRE8; + stc_port_pcr_field_t PCRE8_f; + }; + union + { + __IO uint16_t PFSRE8; + stc_port_pfsr_field_t PFSRE8_f; + }; + union + { + __IO uint16_t PCRE9; + stc_port_pcr_field_t PCRE9_f; + }; + union + { + __IO uint16_t PFSRE9; + stc_port_pfsr_field_t PFSRE9_f; + }; + union + { + __IO uint16_t PCRE10; + stc_port_pcr_field_t PCRE10_f; + }; + union + { + __IO uint16_t PFSRE10; + stc_port_pfsr_field_t PFSRE10_f; + }; + union + { + __IO uint16_t PCRE11; + stc_port_pcr_field_t PCRE11_f; + }; + union + { + __IO uint16_t PFSRE11; + stc_port_pfsr_field_t PFSRE11_f; + }; + union + { + __IO uint16_t PCRE12; + stc_port_pcr_field_t PCRE12_f; + }; + union + { + __IO uint16_t PFSRE12; + stc_port_pfsr_field_t PFSRE12_f; + }; + union + { + __IO uint16_t PCRE13; + stc_port_pcr_field_t PCRE13_f; + }; + union + { + __IO uint16_t PFSRE13; + stc_port_pfsr_field_t PFSRE13_f; + }; + union + { + __IO uint16_t PCRE14; + stc_port_pcr_field_t PCRE14_f; + }; + union + { + __IO uint16_t PFSRE14; + stc_port_pfsr_field_t PFSRE14_f; + }; + union + { + __IO uint16_t PCRE15; + stc_port_pcr_field_t PCRE15_f; + }; + union + { + __IO uint16_t PFSRE15; + stc_port_pfsr_field_t PFSRE15_f; + }; + union + { + __IO uint16_t PCRH0; + stc_port_pcr_field_t PCRH0_f; + }; + union + { + __IO uint16_t PFSRH0; + stc_port_pfsr_field_t PFSRH0_f; + }; + union + { + __IO uint16_t PCRH1; + stc_port_pcr_field_t PCRH1_f; + }; + union + { + __IO uint16_t PFSRH1; + stc_port_pfsr_field_t PFSRH1_f; + }; + union + { + __IO uint16_t PCRH2; + stc_port_pcr_field_t PCRH2_f; + }; + union + { + __IO uint16_t PFSRH2; + stc_port_pfsr_field_t PFSRH2_f; + }; +}M4_PORT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_qspi_cr_field_t CR_f; + }; + union + { + __IO uint32_t CSCR; + stc_qspi_cscr_field_t CSCR_f; + }; + union + { + __IO uint32_t FCR; + stc_qspi_fcr_field_t FCR_f; + }; + union + { + __IO uint32_t SR; + stc_qspi_sr_field_t SR_f; + }; + union + { + __IO uint32_t DCOM; + stc_qspi_dcom_field_t DCOM_f; + }; + union + { + __IO uint32_t CCMD; + stc_qspi_ccmd_field_t CCMD_f; + }; + union + { + __IO uint32_t XCMD; + stc_qspi_xcmd_field_t XCMD_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SR2; + stc_qspi_sr2_field_t SR2_f; + }; + uint8_t RESERVED8[2012]; + union + { + __IO uint32_t EXAR; + stc_qspi_exar_field_t EXAR_f; + }; +}M4_QSPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_rtc_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_rtc_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t ERRCRH; + stc_rtc_errcrh_field_t ERRCRH_f; + }; + union + { + __IO uint32_t ERRCRL; + stc_rtc_errcrl_field_t ERRCRL_f; + }; +}M4_RTC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint16_t BLKSIZE; + stc_sdioc_blksize_field_t BLKSIZE_f; + }; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + union + { + __IO uint16_t TRANSMODE; + stc_sdioc_transmode_field_t TRANSMODE_f; + }; + union + { + __IO uint16_t CMD; + stc_sdioc_cmd_field_t CMD_f; + }; + __IO uint16_t RESP0; + __IO uint16_t RESP1; + __IO uint16_t RESP2; + __IO uint16_t RESP3; + __IO uint16_t RESP4; + __IO uint16_t RESP5; + __IO uint16_t RESP6; + __IO uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + union + { + __IO uint32_t PSTAT; + stc_sdioc_pstat_field_t PSTAT_f; + }; + union + { + __IO uint8_t HOSTCON; + stc_sdioc_hostcon_field_t HOSTCON_f; + }; + union + { + __IO uint8_t PWRCON; + stc_sdioc_pwrcon_field_t PWRCON_f; + }; + union + { + __IO uint8_t BLKGPCON; + stc_sdioc_blkgpcon_field_t BLKGPCON_f; + }; + uint8_t RESERVED20[1]; + union + { + __IO uint16_t CLKCON; + stc_sdioc_clkcon_field_t CLKCON_f; + }; + union + { + __IO uint8_t TOUTCON; + stc_sdioc_toutcon_field_t TOUTCON_f; + }; + union + { + __IO uint8_t SFTRST; + stc_sdioc_sftrst_field_t SFTRST_f; + }; + union + { + __IO uint16_t NORINTST; + stc_sdioc_norintst_field_t NORINTST_f; + }; + union + { + __IO uint16_t ERRINTST; + stc_sdioc_errintst_field_t ERRINTST_f; + }; + union + { + __IO uint16_t NORINTSTEN; + stc_sdioc_norintsten_field_t NORINTSTEN_f; + }; + union + { + __IO uint16_t ERRINTSTEN; + stc_sdioc_errintsten_field_t ERRINTSTEN_f; + }; + union + { + __IO uint16_t NORINTSGEN; + stc_sdioc_norintsgen_field_t NORINTSGEN_f; + }; + union + { + __IO uint16_t ERRINTSGEN; + stc_sdioc_errintsgen_field_t ERRINTSGEN_f; + }; + union + { + __IO uint16_t ATCERRST; + stc_sdioc_atcerrst_field_t ATCERRST_f; + }; + uint8_t RESERVED30[18]; + union + { + __IO uint16_t FEA; + stc_sdioc_fea_field_t FEA_f; + }; + union + { + __IO uint16_t FEE; + stc_sdioc_fee_field_t FEE_f; + }; +}M4_SDIOC_TypeDef; + +typedef struct +{ + __IO uint32_t DR; + union + { + __IO uint32_t CR1; + stc_spi_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CFG1; + stc_spi_cfg1_field_t CFG1_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t SR; + stc_spi_sr_field_t SR_f; + }; + union + { + __IO uint32_t CFG2; + stc_spi_cfg2_field_t CFG2_f; + }; +}M4_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t WTCR; + stc_sramc_wtcr_field_t WTCR_f; + }; + union + { + __IO uint32_t WTPR; + stc_sramc_wtpr_field_t WTPR_f; + }; + union + { + __IO uint32_t CKCR; + stc_sramc_ckcr_field_t CKCR_f; + }; + union + { + __IO uint32_t CKPR; + stc_sramc_ckpr_field_t CKPR_f; + }; + union + { + __IO uint32_t CKSR; + stc_sramc_cksr_field_t CKSR_f; + }; +}M4_SRAMC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t SR; + stc_swdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_swdt_rr_field_t RR_f; + }; +}M4_SWDT_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[12]; + union + { + __IO uint16_t PWR_STPMCR; + stc_sysreg_pwr_stpmcr_field_t PWR_STPMCR_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t CMU_PERICKSEL; + stc_sysreg_cmu_pericksel_field_t CMU_PERICKSEL_f; + }; + union + { + __IO uint16_t CMU_I2SCKSEL; + stc_sysreg_cmu_i2scksel_field_t CMU_I2SCKSEL_f; + }; + union + { + __IO uint32_t PWR_RAMPC0; + stc_sysreg_pwr_rampc0_field_t PWR_RAMPC0_f; + }; + __IO uint16_t PWR_RAMOPM; + uint8_t RESERVED5[2]; + union + { + __IO uint32_t MPU_IPPR; + stc_sysreg_mpu_ippr_field_t MPU_IPPR_f; + }; + union + { + __IO uint32_t CMU_SCFGR; + stc_sysreg_cmu_scfgr_field_t CMU_SCFGR_f; + }; + union + { + __IO uint8_t CMU_UFSCKCFGR; + stc_sysreg_cmu_ufsckcfgr_field_t CMU_UFSCKCFGR_f; + }; + uint8_t RESERVED8[1]; + union + { + __IO uint8_t CMU_CKSWR; + stc_sysreg_cmu_ckswr_field_t CMU_CKSWR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t CMU_PLLCR; + stc_sysreg_cmu_pllcr_field_t CMU_PLLCR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint8_t CMU_UPLLCR; + stc_sysreg_cmu_upllcr_field_t CMU_UPLLCR_f; + }; + uint8_t RESERVED11[3]; + union + { + __IO uint8_t CMU_XTALCR; + stc_sysreg_cmu_xtalcr_field_t CMU_XTALCR_f; + }; + uint8_t RESERVED12[3]; + union + { + __IO uint8_t CMU_HRCCR; + stc_sysreg_cmu_hrccr_field_t CMU_HRCCR_f; + }; + uint8_t RESERVED13[1]; + union + { + __IO uint8_t CMU_MRCCR; + stc_sysreg_cmu_mrccr_field_t CMU_MRCCR_f; + }; + uint8_t RESERVED14[3]; + union + { + __IO uint8_t CMU_OSCSTBSR; + stc_sysreg_cmu_oscstbsr_field_t CMU_OSCSTBSR_f; + }; + union + { + __IO uint8_t CMU_MCO1CFGR; + stc_sysreg_cmu_mco1cfgr_field_t CMU_MCO1CFGR_f; + }; + union + { + __IO uint8_t CMU_MCO2CFGR; + stc_sysreg_cmu_mco2cfgr_field_t CMU_MCO2CFGR_f; + }; + union + { + __IO uint8_t CMU_TPIUCKCFGR; + stc_sysreg_cmu_tpiuckcfgr_field_t CMU_TPIUCKCFGR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDCR; + stc_sysreg_cmu_xtalstdcr_field_t CMU_XTALSTDCR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDSR; + stc_sysreg_cmu_xtalstdsr_field_t CMU_XTALSTDSR_f; + }; + uint8_t RESERVED20[31]; + __IO uint8_t CMU_MRCTRM; + __IO uint8_t CMU_HRCTRM; + uint8_t RESERVED22[63]; + union + { + __IO uint8_t CMU_XTALSTBCR; + stc_sysreg_cmu_xtalstbcr_field_t CMU_XTALSTBCR_f; + }; + uint8_t RESERVED23[29]; + union + { + __IO uint16_t RMU_RSTF0; + stc_sysreg_rmu_rstf0_field_t RMU_RSTF0_f; + }; + uint8_t RESERVED24[30]; + union + { + __IO uint8_t PWR_PVDICR; + stc_sysreg_pwr_pvdicr_field_t PWR_PVDICR_f; + }; + union + { + __IO uint8_t PWR_PVDDSR; + stc_sysreg_pwr_pvddsr_field_t PWR_PVDDSR_f; + }; + uint8_t RESERVED26[30]; + union + { + __IO uint32_t CMU_PLLCFGR; + stc_sysreg_cmu_pllcfgr_field_t CMU_PLLCFGR_f; + }; + union + { + __IO uint32_t CMU_UPLLCFGR; + stc_sysreg_cmu_upllcfgr_field_t CMU_UPLLCFGR_f; + }; + uint8_t RESERVED28[758]; + union + { + __IO uint16_t PWR_FPRC; + stc_sysreg_pwr_fprc_field_t PWR_FPRC_f; + }; + union + { + __IO uint8_t PWR_PWRC0; + stc_sysreg_pwr_pwrc0_field_t PWR_PWRC0_f; + }; + union + { + __IO uint8_t PWR_PWRC1; + stc_sysreg_pwr_pwrc1_field_t PWR_PWRC1_f; + }; + union + { + __IO uint8_t PWR_PWRC2; + stc_sysreg_pwr_pwrc2_field_t PWR_PWRC2_f; + }; + union + { + __IO uint8_t PWR_PWRC3; + stc_sysreg_pwr_pwrc3_field_t PWR_PWRC3_f; + }; + union + { + __IO uint8_t PWR_PDWKE0; + stc_sysreg_pwr_pdwke0_field_t PWR_PDWKE0_f; + }; + union + { + __IO uint8_t PWR_PDWKE1; + stc_sysreg_pwr_pdwke1_field_t PWR_PDWKE1_f; + }; + union + { + __IO uint8_t PWR_PDWKE2; + stc_sysreg_pwr_pdwke2_field_t PWR_PDWKE2_f; + }; + union + { + __IO uint8_t PWR_PDWKES; + stc_sysreg_pwr_pdwkes_field_t PWR_PDWKES_f; + }; + union + { + __IO uint8_t PWR_PDWKF0; + stc_sysreg_pwr_pdwkf0_field_t PWR_PDWKF0_f; + }; + union + { + __IO uint8_t PWR_PDWKF1; + stc_sysreg_pwr_pdwkf1_field_t PWR_PDWKF1_f; + }; + union + { + __IO uint8_t PWR_PWCMR; + stc_sysreg_pwr_pwcmr_field_t PWR_PWCMR_f; + }; + uint8_t RESERVED40[4]; + __IO uint8_t PWR_MDSWCR; + union + { + __IO uint8_t CMU_XTALCFGR; + stc_sysreg_cmu_xtalcfgr_field_t CMU_XTALCFGR_f; + }; + uint8_t RESERVED42[1]; + union + { + __IO uint8_t PWR_PVDCR0; + stc_sysreg_pwr_pvdcr0_field_t PWR_PVDCR0_f; + }; + union + { + __IO uint8_t PWR_PVDCR1; + stc_sysreg_pwr_pvdcr1_field_t PWR_PVDCR1_f; + }; + union + { + __IO uint8_t PWR_PVDFCR; + stc_sysreg_pwr_pvdfcr_field_t PWR_PVDFCR_f; + }; + union + { + __IO uint8_t PWR_PVDLCR; + stc_sysreg_pwr_pvdlcr_field_t PWR_PVDLCR_f; + }; + uint8_t RESERVED46[10]; + union + { + __IO uint8_t CMU_XTAL32CR; + stc_sysreg_cmu_xtal32cr_field_t CMU_XTAL32CR_f; + }; + union + { + __IO uint8_t CMU_XTAL32CFGR; + stc_sysreg_cmu_xtal32cfgr_field_t CMU_XTAL32CFGR_f; + }; + uint8_t RESERVED48[3]; + union + { + __IO uint8_t CMU_XTAL32NFR; + stc_sysreg_cmu_xtal32nfr_field_t CMU_XTAL32NFR_f; + }; + uint8_t RESERVED49[1]; + union + { + __IO uint8_t CMU_LRCCR; + stc_sysreg_cmu_lrccr_field_t CMU_LRCCR_f; + }; + uint8_t RESERVED50[1]; + __IO uint8_t CMU_LRCTRM; + uint8_t RESERVED51[1]; + union + { + __IO uint8_t PWR_XTAL32CS; + stc_sysreg_pwr_xtal32cs_field_t PWR_XTAL32CS_f; + }; +}M4_SYSREG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTAR; + stc_tmr0_cntar_field_t CNTAR_f; + }; + union + { + __IO uint32_t CNTBR; + stc_tmr0_cntbr_field_t CNTBR_f; + }; + union + { + __IO uint32_t CMPAR; + stc_tmr0_cmpar_field_t CMPAR_f; + }; + union + { + __IO uint32_t CMPBR; + stc_tmr0_cmpbr_field_t CMPBR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr0_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr0_stflr_field_t STFLR_f; + }; +}M4_TMR0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + union + { + __IO uint16_t OCSRU; + stc_tmr4_ocsr_field_t OCSRU_f; + }; + union + { + __IO uint16_t OCERU; + stc_tmr4_ocer_field_t OCERU_f; + }; + union + { + __IO uint16_t OCSRV; + stc_tmr4_ocsr_field_t OCSRV_f; + }; + union + { + __IO uint16_t OCERV; + stc_tmr4_ocer_field_t OCERV_f; + }; + union + { + __IO uint16_t OCSRW; + stc_tmr4_ocsr_field_t OCSRW_f; + }; + union + { + __IO uint16_t OCERW; + stc_tmr4_ocer_field_t OCERW_f; + }; + union + { + __IO uint16_t OCMRHUH; + stc_tmr4_ocmrh_field_t OCMRHUH_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint32_t OCMRLUL; + stc_tmr4_ocmrl_field_t OCMRLUL_f; + }; + union + { + __IO uint16_t OCMRHVH; + stc_tmr4_ocmrh_field_t OCMRHVH_f; + }; + uint8_t RESERVED15[2]; + union + { + __IO uint32_t OCMRLVL; + stc_tmr4_ocmrl_field_t OCMRLVL_f; + }; + union + { + __IO uint16_t OCMRHWH; + stc_tmr4_ocmrh_field_t OCMRHWH_f; + }; + uint8_t RESERVED17[2]; + union + { + __IO uint32_t OCMRLWL; + stc_tmr4_ocmrl_field_t OCMRLWL_f; + }; + uint8_t RESERVED18[6]; + __IO uint16_t CPSR; + uint8_t RESERVED19[2]; + __IO uint16_t CNTR; + union + { + __IO uint16_t CCSR; + stc_tmr4_ccsr_field_t CCSR_f; + }; + union + { + __IO uint16_t CVPR; + stc_tmr4_cvpr_field_t CVPR_f; + }; + uint8_t RESERVED22[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED25[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED28[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + union + { + __IO uint16_t POCRU; + stc_tmr4_pocr_field_t POCRU_f; + }; + uint8_t RESERVED32[2]; + union + { + __IO uint16_t POCRV; + stc_tmr4_pocr_field_t POCRV_f; + }; + uint8_t RESERVED33[2]; + union + { + __IO uint16_t POCRW; + stc_tmr4_pocr_field_t POCRW_f; + }; + uint8_t RESERVED34[2]; + union + { + __IO uint16_t RCSR; + stc_tmr4_rcsr_field_t RCSR_f; + }; + uint8_t RESERVED35[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED36[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED37[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED38[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED39[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED40[2]; + __IO uint16_t SCCRWL; + union + { + __IO uint16_t SCSRUH; + stc_tmr4_scsr_field_t SCSRUH_f; + }; + union + { + __IO uint16_t SCMRUH; + stc_tmr4_scmr_field_t SCMRUH_f; + }; + union + { + __IO uint16_t SCSRUL; + stc_tmr4_scsr_field_t SCSRUL_f; + }; + union + { + __IO uint16_t SCMRUL; + stc_tmr4_scmr_field_t SCMRUL_f; + }; + union + { + __IO uint16_t SCSRVH; + stc_tmr4_scsr_field_t SCSRVH_f; + }; + union + { + __IO uint16_t SCMRVH; + stc_tmr4_scmr_field_t SCMRVH_f; + }; + union + { + __IO uint16_t SCSRVL; + stc_tmr4_scsr_field_t SCSRVL_f; + }; + union + { + __IO uint16_t SCMRVL; + stc_tmr4_scmr_field_t SCMRVL_f; + }; + union + { + __IO uint16_t SCSRWH; + stc_tmr4_scsr_field_t SCSRWH_f; + }; + union + { + __IO uint16_t SCMRWH; + stc_tmr4_scmr_field_t SCMRWH_f; + }; + union + { + __IO uint16_t SCSRWL; + stc_tmr4_scsr_field_t SCSRWL_f; + }; + union + { + __IO uint16_t SCMRWL; + stc_tmr4_scmr_field_t SCMRWL_f; + }; + uint8_t RESERVED53[16]; + union + { + __IO uint16_t ECSR; + stc_tmr4_ecsr_field_t ECSR_f; + }; +}M4_TMR4_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t ECER1; + stc_tmr4_cr_ecer1_field_t ECER1_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t ECER2; + stc_tmr4_cr_ecer2_field_t ECER2_f; + }; + uint8_t RESERVED2[2]; + union + { + __IO uint16_t ECER3; + stc_tmr4_cr_ecer3_field_t ECER3_f; + }; +}M4_TMR4_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmr6_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmr6_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tmr6_perbr_field_t PERBR_f; + }; + union + { + __IO uint32_t PERCR; + stc_tmr6_percr_field_t PERCR_f; + }; + union + { + __IO uint32_t GCMAR; + stc_tmr6_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tmr6_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tmr6_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tmr6_gcmdr_field_t GCMDR_f; + }; + union + { + __IO uint32_t GCMER; + stc_tmr6_gcmer_field_t GCMER_f; + }; + union + { + __IO uint32_t GCMFR; + stc_tmr6_gcmfr_field_t GCMFR_f; + }; + union + { + __IO uint32_t SCMAR; + stc_tmr6_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tmr6_scmbr_field_t SCMBR_f; + }; + union + { + __IO uint32_t SCMCR; + stc_tmr6_scmcr_field_t SCMCR_f; + }; + union + { + __IO uint32_t SCMDR; + stc_tmr6_scmdr_field_t SCMDR_f; + }; + union + { + __IO uint32_t SCMER; + stc_tmr6_scmer_field_t SCMER_f; + }; + union + { + __IO uint32_t SCMFR; + stc_tmr6_scmfr_field_t SCMFR_f; + }; + union + { + __IO uint32_t DTUAR; + stc_tmr6_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tmr6_dtdar_field_t DTDAR_f; + }; + union + { + __IO uint32_t DTUBR; + stc_tmr6_dtubr_field_t DTUBR_f; + }; + union + { + __IO uint32_t DTDBR; + stc_tmr6_dtdbr_field_t DTDBR_f; + }; + union + { + __IO uint32_t GCONR; + stc_tmr6_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmr6_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tmr6_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr6_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tmr6_dconr_field_t DCONR_f; + }; + uint8_t RESERVED25[4]; + union + { + __IO uint32_t FCONR; + stc_tmr6_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tmr6_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr6_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tmr6_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tmr6_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCLRR; + stc_tmr6_hclrr_field_t HCLRR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tmr6_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tmr6_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmr6_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmr6_hcdor_field_t HCDOR_f; + }; +}M4_TMR6_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[1012]; + union + { + __IO uint32_t SSTAR; + stc_tmr6_cr_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tmr6_cr_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tmr6_cr_sclrr_field_t SCLRR_f; + }; +}M4_TMR6_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmra_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmra_perar_field_t PERAR_f; + }; + uint8_t RESERVED2[56]; + union + { + __IO uint32_t CMPAR1; + stc_tmra_cmpar_field_t CMPAR1_f; + }; + union + { + __IO uint32_t CMPAR2; + stc_tmra_cmpar_field_t CMPAR2_f; + }; + union + { + __IO uint32_t CMPAR3; + stc_tmra_cmpar_field_t CMPAR3_f; + }; + union + { + __IO uint32_t CMPAR4; + stc_tmra_cmpar_field_t CMPAR4_f; + }; + union + { + __IO uint32_t CMPAR5; + stc_tmra_cmpar_field_t CMPAR5_f; + }; + union + { + __IO uint32_t CMPAR6; + stc_tmra_cmpar_field_t CMPAR6_f; + }; + union + { + __IO uint32_t CMPAR7; + stc_tmra_cmpar_field_t CMPAR7_f; + }; + union + { + __IO uint32_t CMPAR8; + stc_tmra_cmpar_field_t CMPAR8_f; + }; + uint8_t RESERVED10[32]; + union + { + __IO uint32_t BCSTR; + stc_tmra_bcstr_field_t BCSTR_f; + }; + union + { + __IO uint32_t HCONR; + stc_tmra_hconr_field_t HCONR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmra_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmra_hcdor_field_t HCDOR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmra_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t ECONR; + stc_tmra_econr_field_t ECONR_f; + }; + union + { + __IO uint32_t FCONR; + stc_tmra_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmra_stflr_field_t STFLR_f; + }; + uint8_t RESERVED18[32]; + union + { + __IO uint32_t BCONR1; + stc_tmra_bconr_field_t BCONR1_f; + }; + uint8_t RESERVED19[4]; + union + { + __IO uint32_t BCONR2; + stc_tmra_bconr_field_t BCONR2_f; + }; + uint8_t RESERVED20[4]; + union + { + __IO uint32_t BCONR3; + stc_tmra_bconr_field_t BCONR3_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t BCONR4; + stc_tmra_bconr_field_t BCONR4_f; + }; + uint8_t RESERVED22[36]; + union + { + __IO uint32_t CCONR1; + stc_tmra_cconr_field_t CCONR1_f; + }; + union + { + __IO uint32_t CCONR2; + stc_tmra_cconr_field_t CCONR2_f; + }; + union + { + __IO uint32_t CCONR3; + stc_tmra_cconr_field_t CCONR3_f; + }; + union + { + __IO uint32_t CCONR4; + stc_tmra_cconr_field_t CCONR4_f; + }; + union + { + __IO uint32_t CCONR5; + stc_tmra_cconr_field_t CCONR5_f; + }; + union + { + __IO uint32_t CCONR6; + stc_tmra_cconr_field_t CCONR6_f; + }; + union + { + __IO uint32_t CCONR7; + stc_tmra_cconr_field_t CCONR7_f; + }; + union + { + __IO uint32_t CCONR8; + stc_tmra_cconr_field_t CCONR8_f; + }; + uint8_t RESERVED30[32]; + union + { + __IO uint32_t PCONR1; + stc_tmra_pconr_field_t PCONR1_f; + }; + union + { + __IO uint32_t PCONR2; + stc_tmra_pconr_field_t PCONR2_f; + }; + union + { + __IO uint32_t PCONR3; + stc_tmra_pconr_field_t PCONR3_f; + }; + union + { + __IO uint32_t PCONR4; + stc_tmra_pconr_field_t PCONR4_f; + }; + union + { + __IO uint32_t PCONR5; + stc_tmra_pconr_field_t PCONR5_f; + }; + union + { + __IO uint32_t PCONR6; + stc_tmra_pconr_field_t PCONR6_f; + }; + union + { + __IO uint32_t PCONR7; + stc_tmra_pconr_field_t PCONR7_f; + }; + union + { + __IO uint32_t PCONR8; + stc_tmra_pconr_field_t PCONR8_f; + }; +}M4_TMRA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_trng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MR; + stc_trng_mr_field_t MR_f; + }; + uint8_t RESERVED2[4]; + __IO uint32_t DR0; + __IO uint32_t DR1; +}M4_TRNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SR; + stc_usart_sr_field_t SR_f; + }; + union + { + __IO uint32_t DR; + stc_usart_dr_field_t DR_f; + }; + union + { + __IO uint32_t BRR; + stc_usart_brr_field_t BRR_f; + }; + union + { + __IO uint32_t CR1; + stc_usart_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_usart_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_usart_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t PR; + stc_usart_pr_field_t PR_f; + }; +}M4_USART_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t USBFS_GVBUSCFG; + stc_usbfs_usbfs_gvbuscfg_field_t USBFS_GVBUSCFG_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t GAHBCFG; + stc_usbfs_gahbcfg_field_t GAHBCFG_f; + }; + union + { + __IO uint32_t GUSBCFG; + stc_usbfs_gusbcfg_field_t GUSBCFG_f; + }; + union + { + __IO uint32_t GRSTCTL; + stc_usbfs_grstctl_field_t GRSTCTL_f; + }; + union + { + __IO uint32_t GINTSTS; + stc_usbfs_gintsts_field_t GINTSTS_f; + }; + union + { + __IO uint32_t GINTMSK; + stc_usbfs_gintmsk_field_t GINTMSK_f; + }; + union + { + __IO uint32_t GRXSTSR; + stc_usbfs_grxstsr_field_t GRXSTSR_f; + }; + union + { + __IO uint32_t GRXSTSP; + stc_usbfs_grxstsp_field_t GRXSTSP_f; + }; + union + { + __IO uint32_t GRXFSIZ; + stc_usbfs_grxfsiz_field_t GRXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXFSIZ; + stc_usbfs_hnptxfsiz_field_t HNPTXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXSTS; + stc_usbfs_hnptxsts_field_t HNPTXSTS_f; + }; + uint8_t RESERVED11[12]; + __IO uint32_t CID; + uint8_t RESERVED12[192]; + union + { + __IO uint32_t HPTXFSIZ; + stc_usbfs_hptxfsiz_field_t HPTXFSIZ_f; + }; + union + { + __IO uint32_t DIEPTXF1; + stc_usbfs_dieptxf_field_t DIEPTXF1_f; + }; + union + { + __IO uint32_t DIEPTXF2; + stc_usbfs_dieptxf_field_t DIEPTXF2_f; + }; + union + { + __IO uint32_t DIEPTXF3; + stc_usbfs_dieptxf_field_t DIEPTXF3_f; + }; + union + { + __IO uint32_t DIEPTXF4; + stc_usbfs_dieptxf_field_t DIEPTXF4_f; + }; + union + { + __IO uint32_t DIEPTXF5; + stc_usbfs_dieptxf_field_t DIEPTXF5_f; + }; + uint8_t RESERVED18[744]; + union + { + __IO uint32_t HCFG; + stc_usbfs_hcfg_field_t HCFG_f; + }; + union + { + __IO uint32_t HFIR; + stc_usbfs_hfir_field_t HFIR_f; + }; + union + { + __IO uint32_t HFNUM; + stc_usbfs_hfnum_field_t HFNUM_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t HPTXSTS; + stc_usbfs_hptxsts_field_t HPTXSTS_f; + }; + union + { + __IO uint32_t HAINT; + stc_usbfs_haint_field_t HAINT_f; + }; + union + { + __IO uint32_t HAINTMSK; + stc_usbfs_haintmsk_field_t HAINTMSK_f; + }; + uint8_t RESERVED24[36]; + union + { + __IO uint32_t HPRT; + stc_usbfs_hprt_field_t HPRT_f; + }; + uint8_t RESERVED25[188]; + union + { + __IO uint32_t HCCHAR0; + stc_usbfs_hcchar_field_t HCCHAR0_f; + }; + uint8_t RESERVED26[4]; + union + { + __IO uint32_t HCINT0; + stc_usbfs_hcint_field_t HCINT0_f; + }; + union + { + __IO uint32_t HCINTMSK0; + stc_usbfs_hcintmsk_field_t HCINTMSK0_f; + }; + union + { + __IO uint32_t HCTSIZ0; + stc_usbfs_hctsiz_field_t HCTSIZ0_f; + }; + __IO uint32_t HCDMA0; + uint8_t RESERVED30[8]; + union + { + __IO uint32_t HCCHAR1; + stc_usbfs_hcchar_field_t HCCHAR1_f; + }; + uint8_t RESERVED31[4]; + union + { + __IO uint32_t HCINT1; + stc_usbfs_hcint_field_t HCINT1_f; + }; + union + { + __IO uint32_t HCINTMSK1; + stc_usbfs_hcintmsk_field_t HCINTMSK1_f; + }; + union + { + __IO uint32_t HCTSIZ1; + stc_usbfs_hctsiz_field_t HCTSIZ1_f; + }; + __IO uint32_t HCDMA1; + uint8_t RESERVED35[8]; + union + { + __IO uint32_t HCCHAR2; + stc_usbfs_hcchar_field_t HCCHAR2_f; + }; + uint8_t RESERVED36[4]; + union + { + __IO uint32_t HCINT2; + stc_usbfs_hcint_field_t HCINT2_f; + }; + union + { + __IO uint32_t HCINTMSK2; + stc_usbfs_hcintmsk_field_t HCINTMSK2_f; + }; + union + { + __IO uint32_t HCTSIZ2; + stc_usbfs_hctsiz_field_t HCTSIZ2_f; + }; + __IO uint32_t HCDMA2; + uint8_t RESERVED40[8]; + union + { + __IO uint32_t HCCHAR3; + stc_usbfs_hcchar_field_t HCCHAR3_f; + }; + uint8_t RESERVED41[4]; + union + { + __IO uint32_t HCINT3; + stc_usbfs_hcint_field_t HCINT3_f; + }; + union + { + __IO uint32_t HCINTMSK3; + stc_usbfs_hcintmsk_field_t HCINTMSK3_f; + }; + union + { + __IO uint32_t HCTSIZ3; + stc_usbfs_hctsiz_field_t HCTSIZ3_f; + }; + __IO uint32_t HCDMA3; + uint8_t RESERVED45[8]; + union + { + __IO uint32_t HCCHAR4; + stc_usbfs_hcchar_field_t HCCHAR4_f; + }; + uint8_t RESERVED46[4]; + union + { + __IO uint32_t HCINT4; + stc_usbfs_hcint_field_t HCINT4_f; + }; + union + { + __IO uint32_t HCINTMSK4; + stc_usbfs_hcintmsk_field_t HCINTMSK4_f; + }; + union + { + __IO uint32_t HCTSIZ4; + stc_usbfs_hctsiz_field_t HCTSIZ4_f; + }; + __IO uint32_t HCDMA4; + uint8_t RESERVED50[8]; + union + { + __IO uint32_t HCCHAR5; + stc_usbfs_hcchar_field_t HCCHAR5_f; + }; + uint8_t RESERVED51[4]; + union + { + __IO uint32_t HCINT5; + stc_usbfs_hcint_field_t HCINT5_f; + }; + union + { + __IO uint32_t HCINTMSK5; + stc_usbfs_hcintmsk_field_t HCINTMSK5_f; + }; + union + { + __IO uint32_t HCTSIZ5; + stc_usbfs_hctsiz_field_t HCTSIZ5_f; + }; + __IO uint32_t HCDMA5; + uint8_t RESERVED55[8]; + union + { + __IO uint32_t HCCHAR6; + stc_usbfs_hcchar_field_t HCCHAR6_f; + }; + uint8_t RESERVED56[4]; + union + { + __IO uint32_t HCINT6; + stc_usbfs_hcint_field_t HCINT6_f; + }; + union + { + __IO uint32_t HCINTMSK6; + stc_usbfs_hcintmsk_field_t HCINTMSK6_f; + }; + union + { + __IO uint32_t HCTSIZ6; + stc_usbfs_hctsiz_field_t HCTSIZ6_f; + }; + __IO uint32_t HCDMA6; + uint8_t RESERVED60[8]; + union + { + __IO uint32_t HCCHAR7; + stc_usbfs_hcchar_field_t HCCHAR7_f; + }; + uint8_t RESERVED61[4]; + union + { + __IO uint32_t HCINT7; + stc_usbfs_hcint_field_t HCINT7_f; + }; + union + { + __IO uint32_t HCINTMSK7; + stc_usbfs_hcintmsk_field_t HCINTMSK7_f; + }; + union + { + __IO uint32_t HCTSIZ7; + stc_usbfs_hctsiz_field_t HCTSIZ7_f; + }; + __IO uint32_t HCDMA7; + uint8_t RESERVED65[8]; + union + { + __IO uint32_t HCCHAR8; + stc_usbfs_hcchar_field_t HCCHAR8_f; + }; + uint8_t RESERVED66[4]; + union + { + __IO uint32_t HCINT8; + stc_usbfs_hcint_field_t HCINT8_f; + }; + union + { + __IO uint32_t HCINTMSK8; + stc_usbfs_hcintmsk_field_t HCINTMSK8_f; + }; + union + { + __IO uint32_t HCTSIZ8; + stc_usbfs_hctsiz_field_t HCTSIZ8_f; + }; + __IO uint32_t HCDMA8; + uint8_t RESERVED70[8]; + union + { + __IO uint32_t HCCHAR9; + stc_usbfs_hcchar_field_t HCCHAR9_f; + }; + uint8_t RESERVED71[4]; + union + { + __IO uint32_t HCINT9; + stc_usbfs_hcint_field_t HCINT9_f; + }; + union + { + __IO uint32_t HCINTMSK9; + stc_usbfs_hcintmsk_field_t HCINTMSK9_f; + }; + union + { + __IO uint32_t HCTSIZ9; + stc_usbfs_hctsiz_field_t HCTSIZ9_f; + }; + __IO uint32_t HCDMA9; + uint8_t RESERVED75[8]; + union + { + __IO uint32_t HCCHAR10; + stc_usbfs_hcchar_field_t HCCHAR10_f; + }; + uint8_t RESERVED76[4]; + union + { + __IO uint32_t HCINT10; + stc_usbfs_hcint_field_t HCINT10_f; + }; + union + { + __IO uint32_t HCINTMSK10; + stc_usbfs_hcintmsk_field_t HCINTMSK10_f; + }; + union + { + __IO uint32_t HCTSIZ10; + stc_usbfs_hctsiz_field_t HCTSIZ10_f; + }; + __IO uint32_t HCDMA10; + uint8_t RESERVED80[8]; + union + { + __IO uint32_t HCCHAR11; + stc_usbfs_hcchar_field_t HCCHAR11_f; + }; + uint8_t RESERVED81[4]; + union + { + __IO uint32_t HCINT11; + stc_usbfs_hcint_field_t HCINT11_f; + }; + union + { + __IO uint32_t HCINTMSK11; + stc_usbfs_hcintmsk_field_t HCINTMSK11_f; + }; + union + { + __IO uint32_t HCTSIZ11; + stc_usbfs_hctsiz_field_t HCTSIZ11_f; + }; + __IO uint32_t HCDMA11; + uint8_t RESERVED85[392]; + union + { + __IO uint32_t DCFG; + stc_usbfs_dcfg_field_t DCFG_f; + }; + union + { + __IO uint32_t DCTL; + stc_usbfs_dctl_field_t DCTL_f; + }; + union + { + __IO uint32_t DSTS; + stc_usbfs_dsts_field_t DSTS_f; + }; + uint8_t RESERVED88[4]; + union + { + __IO uint32_t DIEPMSK; + stc_usbfs_diepmsk_field_t DIEPMSK_f; + }; + union + { + __IO uint32_t DOEPMSK; + stc_usbfs_doepmsk_field_t DOEPMSK_f; + }; + union + { + __IO uint32_t DAINT; + stc_usbfs_daint_field_t DAINT_f; + }; + union + { + __IO uint32_t DAINTMSK; + stc_usbfs_daintmsk_field_t DAINTMSK_f; + }; + uint8_t RESERVED92[20]; + union + { + __IO uint32_t DIEPEMPMSK; + stc_usbfs_diepempmsk_field_t DIEPEMPMSK_f; + }; + uint8_t RESERVED93[200]; + union + { + __IO uint32_t DIEPCTL0; + stc_usbfs_diepctl0_field_t DIEPCTL0_f; + }; + uint8_t RESERVED94[4]; + union + { + __IO uint32_t DIEPINT0; + stc_usbfs_diepint0_field_t DIEPINT0_f; + }; + uint8_t RESERVED95[4]; + union + { + __IO uint32_t DIEPTSIZ0; + stc_usbfs_dieptsiz0_field_t DIEPTSIZ0_f; + }; + __IO uint32_t DIEPDMA0; + union + { + __IO uint32_t DTXFSTS0; + stc_usbfs_dtxfsts0_field_t DTXFSTS0_f; + }; + uint8_t RESERVED98[4]; + union + { + __IO uint32_t DIEPCTL1; + stc_usbfs_diepctl_field_t DIEPCTL1_f; + }; + uint8_t RESERVED99[4]; + union + { + __IO uint32_t DIEPINT1; + stc_usbfs_diepint_field_t DIEPINT1_f; + }; + uint8_t RESERVED100[4]; + union + { + __IO uint32_t DIEPTSIZ1; + stc_usbfs_dieptsiz_field_t DIEPTSIZ1_f; + }; + __IO uint32_t DIEPDMA1; + union + { + __IO uint32_t DTXFSTS1; + stc_usbfs_dtxfsts_field_t DTXFSTS1_f; + }; + uint8_t RESERVED103[4]; + union + { + __IO uint32_t DIEPCTL2; + stc_usbfs_diepctl_field_t DIEPCTL2_f; + }; + uint8_t RESERVED104[4]; + union + { + __IO uint32_t DIEPINT2; + stc_usbfs_diepint_field_t DIEPINT2_f; + }; + uint8_t RESERVED105[4]; + union + { + __IO uint32_t DIEPTSIZ2; + stc_usbfs_dieptsiz_field_t DIEPTSIZ2_f; + }; + __IO uint32_t DIEPDMA2; + union + { + __IO uint32_t DTXFSTS2; + stc_usbfs_dtxfsts_field_t DTXFSTS2_f; + }; + uint8_t RESERVED108[4]; + union + { + __IO uint32_t DIEPCTL3; + stc_usbfs_diepctl_field_t DIEPCTL3_f; + }; + uint8_t RESERVED109[4]; + union + { + __IO uint32_t DIEPINT3; + stc_usbfs_diepint_field_t DIEPINT3_f; + }; + uint8_t RESERVED110[4]; + union + { + __IO uint32_t DIEPTSIZ3; + stc_usbfs_dieptsiz_field_t DIEPTSIZ3_f; + }; + __IO uint32_t DIEPDMA3; + union + { + __IO uint32_t DTXFSTS3; + stc_usbfs_dtxfsts_field_t DTXFSTS3_f; + }; + uint8_t RESERVED113[4]; + union + { + __IO uint32_t DIEPCTL4; + stc_usbfs_diepctl_field_t DIEPCTL4_f; + }; + uint8_t RESERVED114[4]; + union + { + __IO uint32_t DIEPINT4; + stc_usbfs_diepint_field_t DIEPINT4_f; + }; + uint8_t RESERVED115[4]; + union + { + __IO uint32_t DIEPTSIZ4; + stc_usbfs_dieptsiz_field_t DIEPTSIZ4_f; + }; + __IO uint32_t DIEPDMA4; + union + { + __IO uint32_t DTXFSTS4; + stc_usbfs_dtxfsts_field_t DTXFSTS4_f; + }; + uint8_t RESERVED118[4]; + union + { + __IO uint32_t DIEPCTL5; + stc_usbfs_diepctl_field_t DIEPCTL5_f; + }; + uint8_t RESERVED119[4]; + union + { + __IO uint32_t DIEPINT5; + stc_usbfs_diepint_field_t DIEPINT5_f; + }; + uint8_t RESERVED120[4]; + union + { + __IO uint32_t DIEPTSIZ5; + stc_usbfs_dieptsiz_field_t DIEPTSIZ5_f; + }; + __IO uint32_t DIEPDMA5; + union + { + __IO uint32_t DTXFSTS5; + stc_usbfs_dtxfsts_field_t DTXFSTS5_f; + }; + uint8_t RESERVED123[324]; + union + { + __IO uint32_t DOEPCTL0; + stc_usbfs_doepctl0_field_t DOEPCTL0_f; + }; + uint8_t RESERVED124[4]; + union + { + __IO uint32_t DOEPINT0; + stc_usbfs_doepint_field_t DOEPINT0_f; + }; + uint8_t RESERVED125[4]; + union + { + __IO uint32_t DOEPTSIZ0; + stc_usbfs_doeptsiz0_field_t DOEPTSIZ0_f; + }; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED127[8]; + union + { + __IO uint32_t DOEPCTL1; + stc_usbfs_doepctl_field_t DOEPCTL1_f; + }; + uint8_t RESERVED128[4]; + union + { + __IO uint32_t DOEPINT1; + stc_usbfs_doepint_field_t DOEPINT1_f; + }; + uint8_t RESERVED129[4]; + union + { + __IO uint32_t DOEPTSIZ1; + stc_usbfs_doeptsiz_field_t DOEPTSIZ1_f; + }; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED131[8]; + union + { + __IO uint32_t DOEPCTL2; + stc_usbfs_doepctl_field_t DOEPCTL2_f; + }; + uint8_t RESERVED132[4]; + union + { + __IO uint32_t DOEPINT2; + stc_usbfs_doepint_field_t DOEPINT2_f; + }; + uint8_t RESERVED133[4]; + union + { + __IO uint32_t DOEPTSIZ2; + stc_usbfs_doeptsiz_field_t DOEPTSIZ2_f; + }; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED135[8]; + union + { + __IO uint32_t DOEPCTL3; + stc_usbfs_doepctl_field_t DOEPCTL3_f; + }; + uint8_t RESERVED136[4]; + union + { + __IO uint32_t DOEPINT3; + stc_usbfs_doepint_field_t DOEPINT3_f; + }; + uint8_t RESERVED137[4]; + union + { + __IO uint32_t DOEPTSIZ3; + stc_usbfs_doeptsiz_field_t DOEPTSIZ3_f; + }; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED139[8]; + union + { + __IO uint32_t DOEPCTL4; + stc_usbfs_doepctl_field_t DOEPCTL4_f; + }; + uint8_t RESERVED140[4]; + union + { + __IO uint32_t DOEPINT4; + stc_usbfs_doepint_field_t DOEPINT4_f; + }; + uint8_t RESERVED141[4]; + union + { + __IO uint32_t DOEPTSIZ4; + stc_usbfs_doeptsiz_field_t DOEPTSIZ4_f; + }; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED143[8]; + union + { + __IO uint32_t DOEPCTL5; + stc_usbfs_doepctl_field_t DOEPCTL5_f; + }; + uint8_t RESERVED144[4]; + union + { + __IO uint32_t DOEPINT5; + stc_usbfs_doepint_field_t DOEPINT5_f; + }; + uint8_t RESERVED145[4]; + union + { + __IO uint32_t DOEPTSIZ5; + stc_usbfs_doeptsiz_field_t DOEPTSIZ5_f; + }; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED147[584]; + union + { + __IO uint32_t PCGCCTL; + stc_usbfs_pcgcctl_field_t PCGCCTL_f; + }; +}M4_USBFS_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_wdt_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_wdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_wdt_rr_field_t RR_f; + }; +}M4_WDT_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CR; + stc_wktm_cr_field_t CR_f; + }; +}M4_WKTM_TypeDef; + + + +#define M4_ADC1 ((M4_ADC_TypeDef *)0x40040000UL) +#define M4_ADC2 ((M4_ADC_TypeDef *)0x40040400UL) +#define M4_AES ((M4_AES_TypeDef *)0x40008000UL) +#define M4_AOS ((M4_AOS_TypeDef *)0x40010800UL) +#define M4_CAN ((M4_CAN_TypeDef *)0x40070400UL) +#define M4_CMP1 ((M4_CMP_TypeDef *)0x4004A000UL) +#define M4_CMP2 ((M4_CMP_TypeDef *)0x4004A010UL) +#define M4_CMP3 ((M4_CMP_TypeDef *)0x4004A020UL) +#define M4_CMP_CR ((M4_CMP_CR_TypeDef *)0x4004A000UL) +#define M4_CRC ((M4_CRC_TypeDef *)0x40008C00UL) +#define M4_DBGC ((M4_DBGC_TypeDef *)0xE0042000UL) +#define M4_DCU1 ((M4_DCU_TypeDef *)0x40052000UL) +#define M4_DCU2 ((M4_DCU_TypeDef *)0x40052400UL) +#define M4_DCU3 ((M4_DCU_TypeDef *)0x40052800UL) +#define M4_DCU4 ((M4_DCU_TypeDef *)0x40052C00UL) +#define M4_DMA1 ((M4_DMA_TypeDef *)0x40053000UL) +#define M4_DMA2 ((M4_DMA_TypeDef *)0x40053400UL) +#define M4_EFM ((M4_EFM_TypeDef *)0x40010400UL) +#define M4_EMB1 ((M4_EMB_TypeDef *)0x40017C00UL) +#define M4_EMB2 ((M4_EMB_TypeDef *)0x40017C20UL) +#define M4_EMB3 ((M4_EMB_TypeDef *)0x40017C40UL) +#define M4_EMB4 ((M4_EMB_TypeDef *)0x40017C60UL) +#define M4_FCM ((M4_FCM_TypeDef *)0x40048400UL) +#define M4_HASH ((M4_HASH_TypeDef *)0x40008400UL) +#define M4_I2C1 ((M4_I2C_TypeDef *)0x4004E000UL) +#define M4_I2C2 ((M4_I2C_TypeDef *)0x4004E400UL) +#define M4_I2C3 ((M4_I2C_TypeDef *)0x4004E800UL) +#define M4_I2S1 ((M4_I2S_TypeDef *)0x4001E000UL) +#define M4_I2S2 ((M4_I2S_TypeDef *)0x4001E400UL) +#define M4_I2S3 ((M4_I2S_TypeDef *)0x40022000UL) +#define M4_I2S4 ((M4_I2S_TypeDef *)0x40022400UL) +#define M4_ICG ((M4_ICG_TypeDef *)0x00000400UL) +#define M4_INTC ((M4_INTC_TypeDef *)0x40051000UL) +#define M4_KEYSCAN ((M4_KEYSCAN_TypeDef *)0x40050C00UL) +#define M4_MPU ((M4_MPU_TypeDef *)0x40050000UL) +#define M4_MSTP ((M4_MSTP_TypeDef *)0x40048000UL) +#define M4_OTS ((M4_OTS_TypeDef *)0x4004A400UL) +#define M4_PERIC ((M4_PERIC_TypeDef *)0x40055400UL) +#define M4_PORT ((M4_PORT_TypeDef *)0x40053800UL) +#define M4_QSPI ((M4_QSPI_TypeDef *)0x9C000000UL) +#define M4_RTC ((M4_RTC_TypeDef *)0x4004C000UL) +#define M4_SDIOC1 ((M4_SDIOC_TypeDef *)0x4006FC00UL) +#define M4_SDIOC2 ((M4_SDIOC_TypeDef *)0x40070000UL) +#define M4_SPI1 ((M4_SPI_TypeDef *)0x4001C000UL) +#define M4_SPI2 ((M4_SPI_TypeDef *)0x4001C400UL) +#define M4_SPI3 ((M4_SPI_TypeDef *)0x40020000UL) +#define M4_SPI4 ((M4_SPI_TypeDef *)0x40020400UL) +#define M4_SRAMC ((M4_SRAMC_TypeDef *)0x40050800UL) +#define M4_SWDT ((M4_SWDT_TypeDef *)0x40049400UL) +#define M4_SYSREG ((M4_SYSREG_TypeDef *)0x40054000UL) +#define M4_TMR01 ((M4_TMR0_TypeDef *)0x40024000UL) +#define M4_TMR02 ((M4_TMR0_TypeDef *)0x40024400UL) +#define M4_TMR41 ((M4_TMR4_TypeDef *)0x40017000UL) +#define M4_TMR42 ((M4_TMR4_TypeDef *)0x40024800UL) +#define M4_TMR43 ((M4_TMR4_TypeDef *)0x40024C00UL) +#define M4_TMR4_CR ((M4_TMR4_CR_TypeDef *)0x40055408UL) +#define M4_TMR61 ((M4_TMR6_TypeDef *)0x40018000UL) +#define M4_TMR62 ((M4_TMR6_TypeDef *)0x40018400UL) +#define M4_TMR63 ((M4_TMR6_TypeDef *)0x40018800UL) +#define M4_TMR6_CR ((M4_TMR6_CR_TypeDef *)0x40018000UL) +#define M4_TMRA1 ((M4_TMRA_TypeDef *)0x40015000UL) +#define M4_TMRA2 ((M4_TMRA_TypeDef *)0x40015400UL) +#define M4_TMRA3 ((M4_TMRA_TypeDef *)0x40015800UL) +#define M4_TMRA4 ((M4_TMRA_TypeDef *)0x40015C00UL) +#define M4_TMRA5 ((M4_TMRA_TypeDef *)0x40016000UL) +#define M4_TMRA6 ((M4_TMRA_TypeDef *)0x40016400UL) +#define M4_TRNG ((M4_TRNG_TypeDef *)0x40041000UL) +#define M4_USART1 ((M4_USART_TypeDef *)0x4001D000UL) +#define M4_USART2 ((M4_USART_TypeDef *)0x4001D400UL) +#define M4_USART3 ((M4_USART_TypeDef *)0x40021000UL) +#define M4_USART4 ((M4_USART_TypeDef *)0x40021400UL) +#define M4_USBFS ((M4_USBFS_TypeDef *)0x400C0000UL) +#define M4_WDT ((M4_WDT_TypeDef *)0x40049000UL) +#define M4_WKTM ((M4_WKTM_TypeDef *)0x4004C400UL) + + +#define bM4_ADC1_STR_STRT (*((volatile unsigned int*)(0x42800000UL))) +#define bM4_ADC1_CR0_MS0 (*((volatile unsigned int*)(0x42800040UL))) +#define bM4_ADC1_CR0_MS1 (*((volatile unsigned int*)(0x42800044UL))) +#define bM4_ADC1_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42800050UL))) +#define bM4_ADC1_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42800054UL))) +#define bM4_ADC1_CR0_CLREN (*((volatile unsigned int*)(0x42800058UL))) +#define bM4_ADC1_CR0_DFMT (*((volatile unsigned int*)(0x4280005CUL))) +#define bM4_ADC1_CR0_AVCNT0 (*((volatile unsigned int*)(0x42800060UL))) +#define bM4_ADC1_CR0_AVCNT1 (*((volatile unsigned int*)(0x42800064UL))) +#define bM4_ADC1_CR0_AVCNT2 (*((volatile unsigned int*)(0x42800068UL))) +#define bM4_ADC1_CR1_RSCHSEL (*((volatile unsigned int*)(0x42800088UL))) +#define bM4_ADC1_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42800140UL))) +#define bM4_ADC1_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42800144UL))) +#define bM4_ADC1_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42800148UL))) +#define bM4_ADC1_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280015CUL))) +#define bM4_ADC1_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42800160UL))) +#define bM4_ADC1_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42800164UL))) +#define bM4_ADC1_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42800168UL))) +#define bM4_ADC1_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280017CUL))) +#define bM4_ADC1_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428001C0UL))) +#define bM4_ADC1_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42800240UL))) +#define bM4_ADC1_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428002C0UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42800700UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42800704UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42800708UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280070CUL))) +#define bM4_ADC1_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42800710UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42800714UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42800718UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280071CUL))) +#define bM4_ADC1_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42800720UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42800724UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42800728UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280072CUL))) +#define bM4_ADC1_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42800730UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42800734UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42800738UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280073CUL))) +#define bM4_ADC1_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42800740UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42800744UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42800748UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280074CUL))) +#define bM4_ADC1_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42800750UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42800754UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42800758UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280075CUL))) +#define bM4_ADC1_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42800760UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42800764UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42800768UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280076CUL))) +#define bM4_ADC1_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42800770UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42800774UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42800778UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280077CUL))) +#define bM4_ADC1_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42800780UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42800784UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42800788UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280078CUL))) +#define bM4_ADC1_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42800790UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42800794UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42800798UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280079CUL))) +#define bM4_ADC1_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428007A0UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428007A4UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428007A8UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428007ACUL))) +#define bM4_ADC1_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428007B0UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428007B4UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428007B8UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428007BCUL))) +#define bM4_ADC1_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428007C0UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428007C4UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428007C8UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428007CCUL))) +#define bM4_ADC1_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428007D0UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428007D4UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428007D8UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428007DCUL))) +#define bM4_ADC1_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428007E0UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428007E4UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428007E8UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428007ECUL))) +#define bM4_ADC1_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428007F0UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428007F4UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428007F8UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428007FCUL))) +#define bM4_ADC1_ISR_EOCAF (*((volatile unsigned int*)(0x428008C0UL))) +#define bM4_ADC1_ISR_EOCBF (*((volatile unsigned int*)(0x428008C4UL))) +#define bM4_ADC1_ICR_EOCAIEN (*((volatile unsigned int*)(0x428008E0UL))) +#define bM4_ADC1_ICR_EOCBIEN (*((volatile unsigned int*)(0x428008E4UL))) +#define bM4_ADC1_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42800980UL))) +#define bM4_ADC1_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42800990UL))) +#define bM4_ADC1_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42800994UL))) +#define bM4_ADC1_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42800998UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428009A0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428009A4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428009A8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428009ACUL))) +#define bM4_ADC1_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428009B0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428009B4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428009B8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428009BCUL))) +#define bM4_ADC1_AWDCR_AWDEN (*((volatile unsigned int*)(0x42801400UL))) +#define bM4_ADC1_AWDCR_AWDMD (*((volatile unsigned int*)(0x42801410UL))) +#define bM4_ADC1_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42801418UL))) +#define bM4_ADC1_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280141CUL))) +#define bM4_ADC1_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42801420UL))) +#define bM4_ADC1_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428015C0UL))) +#define bM4_ADC1_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42801640UL))) +#define bM4_ADC1_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42801800UL))) +#define bM4_ADC1_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42801804UL))) +#define bM4_ADC1_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42801808UL))) +#define bM4_ADC1_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280180CUL))) +#define bM4_ADC1_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42801840UL))) +#define bM4_ADC1_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42801844UL))) +#define bM4_ADC1_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42801848UL))) +#define bM4_ADC1_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280184CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42801980UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42801984UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42801988UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280198CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42801990UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42801994UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42801998UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280199CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428019A0UL))) +#define bM4_ADC1_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428019C0UL))) +#define bM4_ADC2_STR_STRT (*((volatile unsigned int*)(0x42808000UL))) +#define bM4_ADC2_CR0_MS0 (*((volatile unsigned int*)(0x42808040UL))) +#define bM4_ADC2_CR0_MS1 (*((volatile unsigned int*)(0x42808044UL))) +#define bM4_ADC2_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42808050UL))) +#define bM4_ADC2_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42808054UL))) +#define bM4_ADC2_CR0_CLREN (*((volatile unsigned int*)(0x42808058UL))) +#define bM4_ADC2_CR0_DFMT (*((volatile unsigned int*)(0x4280805CUL))) +#define bM4_ADC2_CR0_AVCNT0 (*((volatile unsigned int*)(0x42808060UL))) +#define bM4_ADC2_CR0_AVCNT1 (*((volatile unsigned int*)(0x42808064UL))) +#define bM4_ADC2_CR0_AVCNT2 (*((volatile unsigned int*)(0x42808068UL))) +#define bM4_ADC2_CR1_RSCHSEL (*((volatile unsigned int*)(0x42808088UL))) +#define bM4_ADC2_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42808140UL))) +#define bM4_ADC2_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42808144UL))) +#define bM4_ADC2_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42808148UL))) +#define bM4_ADC2_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280815CUL))) +#define bM4_ADC2_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42808160UL))) +#define bM4_ADC2_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42808164UL))) +#define bM4_ADC2_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42808168UL))) +#define bM4_ADC2_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280817CUL))) +#define bM4_ADC2_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428081C0UL))) +#define bM4_ADC2_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42808240UL))) +#define bM4_ADC2_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428082C0UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42808700UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42808704UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42808708UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280870CUL))) +#define bM4_ADC2_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42808710UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42808714UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42808718UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280871CUL))) +#define bM4_ADC2_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42808720UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42808724UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42808728UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280872CUL))) +#define bM4_ADC2_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42808730UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42808734UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42808738UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280873CUL))) +#define bM4_ADC2_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42808740UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42808744UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42808748UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280874CUL))) +#define bM4_ADC2_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42808750UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42808754UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42808758UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280875CUL))) +#define bM4_ADC2_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42808760UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42808764UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42808768UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280876CUL))) +#define bM4_ADC2_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42808770UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42808774UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42808778UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280877CUL))) +#define bM4_ADC2_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42808780UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42808784UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42808788UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280878CUL))) +#define bM4_ADC2_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42808790UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42808794UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42808798UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280879CUL))) +#define bM4_ADC2_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428087A0UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428087A4UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428087A8UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428087ACUL))) +#define bM4_ADC2_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428087B0UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428087B4UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428087B8UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428087BCUL))) +#define bM4_ADC2_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428087C0UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428087C4UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428087C8UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428087CCUL))) +#define bM4_ADC2_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428087D0UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428087D4UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428087D8UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428087DCUL))) +#define bM4_ADC2_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428087E0UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428087E4UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428087E8UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428087ECUL))) +#define bM4_ADC2_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428087F0UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428087F4UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428087F8UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428087FCUL))) +#define bM4_ADC2_ISR_EOCAF (*((volatile unsigned int*)(0x428088C0UL))) +#define bM4_ADC2_ISR_EOCBF (*((volatile unsigned int*)(0x428088C4UL))) +#define bM4_ADC2_ICR_EOCAIEN (*((volatile unsigned int*)(0x428088E0UL))) +#define bM4_ADC2_ICR_EOCBIEN (*((volatile unsigned int*)(0x428088E4UL))) +#define bM4_ADC2_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42808980UL))) +#define bM4_ADC2_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42808990UL))) +#define bM4_ADC2_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42808994UL))) +#define bM4_ADC2_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42808998UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428089A0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428089A4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428089A8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428089ACUL))) +#define bM4_ADC2_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428089B0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428089B4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428089B8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428089BCUL))) +#define bM4_ADC2_AWDCR_AWDEN (*((volatile unsigned int*)(0x42809400UL))) +#define bM4_ADC2_AWDCR_AWDMD (*((volatile unsigned int*)(0x42809410UL))) +#define bM4_ADC2_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42809418UL))) +#define bM4_ADC2_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280941CUL))) +#define bM4_ADC2_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42809420UL))) +#define bM4_ADC2_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428095C0UL))) +#define bM4_ADC2_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42809640UL))) +#define bM4_ADC2_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42809800UL))) +#define bM4_ADC2_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42809804UL))) +#define bM4_ADC2_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42809808UL))) +#define bM4_ADC2_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280980CUL))) +#define bM4_ADC2_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42809840UL))) +#define bM4_ADC2_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42809844UL))) +#define bM4_ADC2_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42809848UL))) +#define bM4_ADC2_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280984CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42809980UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42809984UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42809988UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280998CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42809990UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42809994UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42809998UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280999CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428099A0UL))) +#define bM4_ADC2_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428099C0UL))) +#define bM4_AES_CR_START (*((volatile unsigned int*)(0x42100000UL))) +#define bM4_AES_CR_MODE (*((volatile unsigned int*)(0x42100004UL))) +#define bM4_AOS_INT_SFTTRG_STRG (*((volatile unsigned int*)(0x42210000UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210080UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210084UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210088UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221008CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210090UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210094UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210098UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221009CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422100A0UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422100F8UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422100FCUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210100UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210104UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210108UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221010CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210110UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210114UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210118UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221011CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210120UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210178UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221017CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210180UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210184UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210188UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221018CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210190UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210194UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210198UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221019CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422101A0UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422101F8UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422101FCUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210200UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210204UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210208UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221020CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210210UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210214UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210218UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221021CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210220UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210278UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221027CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210280UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210284UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210288UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221028CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210290UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210294UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210298UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221029CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422102A0UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422102F8UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422102FCUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210300UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210304UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210308UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221030CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210310UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210314UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210318UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221031CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210320UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210378UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221037CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210380UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210384UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210388UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221038CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210390UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210394UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210398UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221039CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422103A0UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422103F8UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422103FCUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210400UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210404UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210408UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221040CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210410UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210414UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210418UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221041CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210420UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210478UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221047CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210480UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210484UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210488UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221048CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210490UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210494UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210498UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221049CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422104A0UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422104F8UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422104FCUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210500UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210504UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210508UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221050CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210510UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210514UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210518UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221051CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210520UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210578UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221057CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210580UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210584UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210588UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221058CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210590UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210594UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210598UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221059CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422105A0UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422105F8UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422105FCUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210600UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210604UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210608UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221060CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210610UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210614UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210618UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221061CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210620UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210678UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221067CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL0 (*((volatile unsigned int*)(0x42210680UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL1 (*((volatile unsigned int*)(0x42210684UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL2 (*((volatile unsigned int*)(0x42210688UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL3 (*((volatile unsigned int*)(0x4221068CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL4 (*((volatile unsigned int*)(0x42210690UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL5 (*((volatile unsigned int*)(0x42210694UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL6 (*((volatile unsigned int*)(0x42210698UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL7 (*((volatile unsigned int*)(0x4221069CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL8 (*((volatile unsigned int*)(0x422106A0UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN0 (*((volatile unsigned int*)(0x422106F8UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN1 (*((volatile unsigned int*)(0x422106FCUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210700UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210704UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210708UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x4221070CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210710UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210714UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210718UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x4221071CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210720UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210778UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221077CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL0 (*((volatile unsigned int*)(0x42210780UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL1 (*((volatile unsigned int*)(0x42210784UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL2 (*((volatile unsigned int*)(0x42210788UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL3 (*((volatile unsigned int*)(0x4221078CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL4 (*((volatile unsigned int*)(0x42210790UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL5 (*((volatile unsigned int*)(0x42210794UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL6 (*((volatile unsigned int*)(0x42210798UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL7 (*((volatile unsigned int*)(0x4221079CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL8 (*((volatile unsigned int*)(0x422107A0UL))) +#define bM4_AOS_TMR6_HTSSR2_COMTRG_EN0 (*((volatile unsigned int*)(0x422107F8UL))) +#define bM4_AOS_TMR6_HTSSR2_COMTRG_EN1 (*((volatile unsigned int*)(0x422107FCUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL0 (*((volatile unsigned int*)(0x42210800UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL1 (*((volatile unsigned int*)(0x42210804UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL2 (*((volatile unsigned int*)(0x42210808UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL3 (*((volatile unsigned int*)(0x4221080CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL4 (*((volatile unsigned int*)(0x42210810UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL5 (*((volatile unsigned int*)(0x42210814UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL6 (*((volatile unsigned int*)(0x42210818UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL7 (*((volatile unsigned int*)(0x4221081CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL8 (*((volatile unsigned int*)(0x42210820UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN0 (*((volatile unsigned int*)(0x42210878UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN1 (*((volatile unsigned int*)(0x4221087CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL0 (*((volatile unsigned int*)(0x42210880UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL1 (*((volatile unsigned int*)(0x42210884UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL2 (*((volatile unsigned int*)(0x42210888UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL3 (*((volatile unsigned int*)(0x4221088CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL4 (*((volatile unsigned int*)(0x42210890UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL5 (*((volatile unsigned int*)(0x42210894UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL6 (*((volatile unsigned int*)(0x42210898UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL7 (*((volatile unsigned int*)(0x4221089CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL8 (*((volatile unsigned int*)(0x422108A0UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_COMTRG_EN0 (*((volatile unsigned int*)(0x422108F8UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_COMTRG_EN1 (*((volatile unsigned int*)(0x422108FCUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL0 (*((volatile unsigned int*)(0x42210900UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL1 (*((volatile unsigned int*)(0x42210904UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL2 (*((volatile unsigned int*)(0x42210908UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL3 (*((volatile unsigned int*)(0x4221090CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL4 (*((volatile unsigned int*)(0x42210910UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL5 (*((volatile unsigned int*)(0x42210914UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL6 (*((volatile unsigned int*)(0x42210918UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL7 (*((volatile unsigned int*)(0x4221091CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL8 (*((volatile unsigned int*)(0x42210920UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_COMTRG_EN0 (*((volatile unsigned int*)(0x42210978UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_COMTRG_EN1 (*((volatile unsigned int*)(0x4221097CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL0 (*((volatile unsigned int*)(0x42210980UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL1 (*((volatile unsigned int*)(0x42210984UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL2 (*((volatile unsigned int*)(0x42210988UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL3 (*((volatile unsigned int*)(0x4221098CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL4 (*((volatile unsigned int*)(0x42210990UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL5 (*((volatile unsigned int*)(0x42210994UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL6 (*((volatile unsigned int*)(0x42210998UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL7 (*((volatile unsigned int*)(0x4221099CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL8 (*((volatile unsigned int*)(0x422109A0UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN0 (*((volatile unsigned int*)(0x422109F8UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN1 (*((volatile unsigned int*)(0x422109FCUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210A00UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210A04UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210A08UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x42210A0CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210A10UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210A14UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210A18UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x42210A1CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210A20UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210A78UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210A7CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL0 (*((volatile unsigned int*)(0x42210A80UL))) +#define bM4_AOS_OTS_TRG_TRGSEL1 (*((volatile unsigned int*)(0x42210A84UL))) +#define bM4_AOS_OTS_TRG_TRGSEL2 (*((volatile unsigned int*)(0x42210A88UL))) +#define bM4_AOS_OTS_TRG_TRGSEL3 (*((volatile unsigned int*)(0x42210A8CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL4 (*((volatile unsigned int*)(0x42210A90UL))) +#define bM4_AOS_OTS_TRG_TRGSEL5 (*((volatile unsigned int*)(0x42210A94UL))) +#define bM4_AOS_OTS_TRG_TRGSEL6 (*((volatile unsigned int*)(0x42210A98UL))) +#define bM4_AOS_OTS_TRG_TRGSEL7 (*((volatile unsigned int*)(0x42210A9CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL8 (*((volatile unsigned int*)(0x42210AA0UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN0 (*((volatile unsigned int*)(0x42210AF8UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN1 (*((volatile unsigned int*)(0x42210AFCUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210B00UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210B04UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210B08UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210B0CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210B10UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210B14UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210B18UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210B1CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210B20UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210B78UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210B7CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210B80UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210B84UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210B88UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210B8CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210B90UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210B94UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210B98UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210B9CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210BA0UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210BF8UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210BFCUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210C00UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210C04UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210C08UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210C0CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210C10UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210C14UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210C18UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210C1CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210C20UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210C78UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210C7CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210C80UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210C84UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210C88UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210C8CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210C90UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210C94UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210C98UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210C9CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210CA0UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210CF8UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210CFCUL))) +#define bM4_AOS_COMTRG1_TRGSEL0 (*((volatile unsigned int*)(0x42210D00UL))) +#define bM4_AOS_COMTRG1_TRGSEL1 (*((volatile unsigned int*)(0x42210D04UL))) +#define bM4_AOS_COMTRG1_TRGSEL2 (*((volatile unsigned int*)(0x42210D08UL))) +#define bM4_AOS_COMTRG1_TRGSEL3 (*((volatile unsigned int*)(0x42210D0CUL))) +#define bM4_AOS_COMTRG1_TRGSEL4 (*((volatile unsigned int*)(0x42210D10UL))) +#define bM4_AOS_COMTRG1_TRGSEL5 (*((volatile unsigned int*)(0x42210D14UL))) +#define bM4_AOS_COMTRG1_TRGSEL6 (*((volatile unsigned int*)(0x42210D18UL))) +#define bM4_AOS_COMTRG1_TRGSEL7 (*((volatile unsigned int*)(0x42210D1CUL))) +#define bM4_AOS_COMTRG1_TRGSEL8 (*((volatile unsigned int*)(0x42210D20UL))) +#define bM4_AOS_COMTRG2_TRGSEL0 (*((volatile unsigned int*)(0x42210D80UL))) +#define bM4_AOS_COMTRG2_TRGSEL1 (*((volatile unsigned int*)(0x42210D84UL))) +#define bM4_AOS_COMTRG2_TRGSEL2 (*((volatile unsigned int*)(0x42210D88UL))) +#define bM4_AOS_COMTRG2_TRGSEL3 (*((volatile unsigned int*)(0x42210D8CUL))) +#define bM4_AOS_COMTRG2_TRGSEL4 (*((volatile unsigned int*)(0x42210D90UL))) +#define bM4_AOS_COMTRG2_TRGSEL5 (*((volatile unsigned int*)(0x42210D94UL))) +#define bM4_AOS_COMTRG2_TRGSEL6 (*((volatile unsigned int*)(0x42210D98UL))) +#define bM4_AOS_COMTRG2_TRGSEL7 (*((volatile unsigned int*)(0x42210D9CUL))) +#define bM4_AOS_COMTRG2_TRGSEL8 (*((volatile unsigned int*)(0x42210DA0UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR00 (*((volatile unsigned int*)(0x42212000UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR01 (*((volatile unsigned int*)(0x42212004UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR02 (*((volatile unsigned int*)(0x42212008UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR03 (*((volatile unsigned int*)(0x4221200CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR04 (*((volatile unsigned int*)(0x42212010UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR05 (*((volatile unsigned int*)(0x42212014UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR06 (*((volatile unsigned int*)(0x42212018UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR07 (*((volatile unsigned int*)(0x4221201CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR08 (*((volatile unsigned int*)(0x42212020UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR09 (*((volatile unsigned int*)(0x42212024UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR10 (*((volatile unsigned int*)(0x42212028UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR11 (*((volatile unsigned int*)(0x4221202CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR12 (*((volatile unsigned int*)(0x42212030UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR13 (*((volatile unsigned int*)(0x42212034UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR14 (*((volatile unsigned int*)(0x42212038UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR15 (*((volatile unsigned int*)(0x4221203CUL))) +#define bM4_AOS_PEVNTIDR1_PIN00 (*((volatile unsigned int*)(0x42212080UL))) +#define bM4_AOS_PEVNTIDR1_PIN01 (*((volatile unsigned int*)(0x42212084UL))) +#define bM4_AOS_PEVNTIDR1_PIN02 (*((volatile unsigned int*)(0x42212088UL))) +#define bM4_AOS_PEVNTIDR1_PIN03 (*((volatile unsigned int*)(0x4221208CUL))) +#define bM4_AOS_PEVNTIDR1_PIN04 (*((volatile unsigned int*)(0x42212090UL))) +#define bM4_AOS_PEVNTIDR1_PIN05 (*((volatile unsigned int*)(0x42212094UL))) +#define bM4_AOS_PEVNTIDR1_PIN06 (*((volatile unsigned int*)(0x42212098UL))) +#define bM4_AOS_PEVNTIDR1_PIN07 (*((volatile unsigned int*)(0x4221209CUL))) +#define bM4_AOS_PEVNTIDR1_PIN08 (*((volatile unsigned int*)(0x422120A0UL))) +#define bM4_AOS_PEVNTIDR1_PIN09 (*((volatile unsigned int*)(0x422120A4UL))) +#define bM4_AOS_PEVNTIDR1_PIN10 (*((volatile unsigned int*)(0x422120A8UL))) +#define bM4_AOS_PEVNTIDR1_PIN11 (*((volatile unsigned int*)(0x422120ACUL))) +#define bM4_AOS_PEVNTIDR1_PIN12 (*((volatile unsigned int*)(0x422120B0UL))) +#define bM4_AOS_PEVNTIDR1_PIN13 (*((volatile unsigned int*)(0x422120B4UL))) +#define bM4_AOS_PEVNTIDR1_PIN14 (*((volatile unsigned int*)(0x422120B8UL))) +#define bM4_AOS_PEVNTIDR1_PIN15 (*((volatile unsigned int*)(0x422120BCUL))) +#define bM4_AOS_PEVNTODR1_POUT00 (*((volatile unsigned int*)(0x42212100UL))) +#define bM4_AOS_PEVNTODR1_POUT01 (*((volatile unsigned int*)(0x42212104UL))) +#define bM4_AOS_PEVNTODR1_POUT02 (*((volatile unsigned int*)(0x42212108UL))) +#define bM4_AOS_PEVNTODR1_POUT03 (*((volatile unsigned int*)(0x4221210CUL))) +#define bM4_AOS_PEVNTODR1_POUT04 (*((volatile unsigned int*)(0x42212110UL))) +#define bM4_AOS_PEVNTODR1_POUT05 (*((volatile unsigned int*)(0x42212114UL))) +#define bM4_AOS_PEVNTODR1_POUT06 (*((volatile unsigned int*)(0x42212118UL))) +#define bM4_AOS_PEVNTODR1_POUT07 (*((volatile unsigned int*)(0x4221211CUL))) +#define bM4_AOS_PEVNTODR1_POUT08 (*((volatile unsigned int*)(0x42212120UL))) +#define bM4_AOS_PEVNTODR1_POUT09 (*((volatile unsigned int*)(0x42212124UL))) +#define bM4_AOS_PEVNTODR1_POUT10 (*((volatile unsigned int*)(0x42212128UL))) +#define bM4_AOS_PEVNTODR1_POUT11 (*((volatile unsigned int*)(0x4221212CUL))) +#define bM4_AOS_PEVNTODR1_POUT12 (*((volatile unsigned int*)(0x42212130UL))) +#define bM4_AOS_PEVNTODR1_POUT13 (*((volatile unsigned int*)(0x42212134UL))) +#define bM4_AOS_PEVNTODR1_POUT14 (*((volatile unsigned int*)(0x42212138UL))) +#define bM4_AOS_PEVNTODR1_POUT15 (*((volatile unsigned int*)(0x4221213CUL))) +#define bM4_AOS_PEVNTORR1_POR00 (*((volatile unsigned int*)(0x42212180UL))) +#define bM4_AOS_PEVNTORR1_POR01 (*((volatile unsigned int*)(0x42212184UL))) +#define bM4_AOS_PEVNTORR1_POR02 (*((volatile unsigned int*)(0x42212188UL))) +#define bM4_AOS_PEVNTORR1_POR03 (*((volatile unsigned int*)(0x4221218CUL))) +#define bM4_AOS_PEVNTORR1_POR04 (*((volatile unsigned int*)(0x42212190UL))) +#define bM4_AOS_PEVNTORR1_POR05 (*((volatile unsigned int*)(0x42212194UL))) +#define bM4_AOS_PEVNTORR1_POR06 (*((volatile unsigned int*)(0x42212198UL))) +#define bM4_AOS_PEVNTORR1_POR07 (*((volatile unsigned int*)(0x4221219CUL))) +#define bM4_AOS_PEVNTORR1_POR08 (*((volatile unsigned int*)(0x422121A0UL))) +#define bM4_AOS_PEVNTORR1_POR09 (*((volatile unsigned int*)(0x422121A4UL))) +#define bM4_AOS_PEVNTORR1_POR10 (*((volatile unsigned int*)(0x422121A8UL))) +#define bM4_AOS_PEVNTORR1_POR11 (*((volatile unsigned int*)(0x422121ACUL))) +#define bM4_AOS_PEVNTORR1_POR12 (*((volatile unsigned int*)(0x422121B0UL))) +#define bM4_AOS_PEVNTORR1_POR13 (*((volatile unsigned int*)(0x422121B4UL))) +#define bM4_AOS_PEVNTORR1_POR14 (*((volatile unsigned int*)(0x422121B8UL))) +#define bM4_AOS_PEVNTORR1_POR15 (*((volatile unsigned int*)(0x422121BCUL))) +#define bM4_AOS_PEVNTOSR1_POS00 (*((volatile unsigned int*)(0x42212200UL))) +#define bM4_AOS_PEVNTOSR1_POS01 (*((volatile unsigned int*)(0x42212204UL))) +#define bM4_AOS_PEVNTOSR1_POS02 (*((volatile unsigned int*)(0x42212208UL))) +#define bM4_AOS_PEVNTOSR1_POS03 (*((volatile unsigned int*)(0x4221220CUL))) +#define bM4_AOS_PEVNTOSR1_POS04 (*((volatile unsigned int*)(0x42212210UL))) +#define bM4_AOS_PEVNTOSR1_POS05 (*((volatile unsigned int*)(0x42212214UL))) +#define bM4_AOS_PEVNTOSR1_POS06 (*((volatile unsigned int*)(0x42212218UL))) +#define bM4_AOS_PEVNTOSR1_POS07 (*((volatile unsigned int*)(0x4221221CUL))) +#define bM4_AOS_PEVNTOSR1_POS08 (*((volatile unsigned int*)(0x42212220UL))) +#define bM4_AOS_PEVNTOSR1_POS09 (*((volatile unsigned int*)(0x42212224UL))) +#define bM4_AOS_PEVNTOSR1_POS10 (*((volatile unsigned int*)(0x42212228UL))) +#define bM4_AOS_PEVNTOSR1_POS11 (*((volatile unsigned int*)(0x4221222CUL))) +#define bM4_AOS_PEVNTOSR1_POS12 (*((volatile unsigned int*)(0x42212230UL))) +#define bM4_AOS_PEVNTOSR1_POS13 (*((volatile unsigned int*)(0x42212234UL))) +#define bM4_AOS_PEVNTOSR1_POS14 (*((volatile unsigned int*)(0x42212238UL))) +#define bM4_AOS_PEVNTOSR1_POS15 (*((volatile unsigned int*)(0x4221223CUL))) +#define bM4_AOS_PEVNTRISR1_RIS00 (*((volatile unsigned int*)(0x42212280UL))) +#define bM4_AOS_PEVNTRISR1_RIS01 (*((volatile unsigned int*)(0x42212284UL))) +#define bM4_AOS_PEVNTRISR1_RIS02 (*((volatile unsigned int*)(0x42212288UL))) +#define bM4_AOS_PEVNTRISR1_RIS03 (*((volatile unsigned int*)(0x4221228CUL))) +#define bM4_AOS_PEVNTRISR1_RIS04 (*((volatile unsigned int*)(0x42212290UL))) +#define bM4_AOS_PEVNTRISR1_RIS05 (*((volatile unsigned int*)(0x42212294UL))) +#define bM4_AOS_PEVNTRISR1_RIS06 (*((volatile unsigned int*)(0x42212298UL))) +#define bM4_AOS_PEVNTRISR1_RIS07 (*((volatile unsigned int*)(0x4221229CUL))) +#define bM4_AOS_PEVNTRISR1_RIS08 (*((volatile unsigned int*)(0x422122A0UL))) +#define bM4_AOS_PEVNTRISR1_RIS09 (*((volatile unsigned int*)(0x422122A4UL))) +#define bM4_AOS_PEVNTRISR1_RIS10 (*((volatile unsigned int*)(0x422122A8UL))) +#define bM4_AOS_PEVNTRISR1_RIS11 (*((volatile unsigned int*)(0x422122ACUL))) +#define bM4_AOS_PEVNTRISR1_RIS12 (*((volatile unsigned int*)(0x422122B0UL))) +#define bM4_AOS_PEVNTRISR1_RIS13 (*((volatile unsigned int*)(0x422122B4UL))) +#define bM4_AOS_PEVNTRISR1_RIS14 (*((volatile unsigned int*)(0x422122B8UL))) +#define bM4_AOS_PEVNTRISR1_RIS15 (*((volatile unsigned int*)(0x422122BCUL))) +#define bM4_AOS_PEVNTFAL1_FAL00 (*((volatile unsigned int*)(0x42212300UL))) +#define bM4_AOS_PEVNTFAL1_FAL01 (*((volatile unsigned int*)(0x42212304UL))) +#define bM4_AOS_PEVNTFAL1_FAL02 (*((volatile unsigned int*)(0x42212308UL))) +#define bM4_AOS_PEVNTFAL1_FAL03 (*((volatile unsigned int*)(0x4221230CUL))) +#define bM4_AOS_PEVNTFAL1_FAL04 (*((volatile unsigned int*)(0x42212310UL))) +#define bM4_AOS_PEVNTFAL1_FAL05 (*((volatile unsigned int*)(0x42212314UL))) +#define bM4_AOS_PEVNTFAL1_FAL06 (*((volatile unsigned int*)(0x42212318UL))) +#define bM4_AOS_PEVNTFAL1_FAL07 (*((volatile unsigned int*)(0x4221231CUL))) +#define bM4_AOS_PEVNTFAL1_FAL08 (*((volatile unsigned int*)(0x42212320UL))) +#define bM4_AOS_PEVNTFAL1_FAL09 (*((volatile unsigned int*)(0x42212324UL))) +#define bM4_AOS_PEVNTFAL1_FAL10 (*((volatile unsigned int*)(0x42212328UL))) +#define bM4_AOS_PEVNTFAL1_FAL11 (*((volatile unsigned int*)(0x4221232CUL))) +#define bM4_AOS_PEVNTFAL1_FAL12 (*((volatile unsigned int*)(0x42212330UL))) +#define bM4_AOS_PEVNTFAL1_FAL13 (*((volatile unsigned int*)(0x42212334UL))) +#define bM4_AOS_PEVNTFAL1_FAL14 (*((volatile unsigned int*)(0x42212338UL))) +#define bM4_AOS_PEVNTFAL1_FAL15 (*((volatile unsigned int*)(0x4221233CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR00 (*((volatile unsigned int*)(0x42212380UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR01 (*((volatile unsigned int*)(0x42212384UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR02 (*((volatile unsigned int*)(0x42212388UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR03 (*((volatile unsigned int*)(0x4221238CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR04 (*((volatile unsigned int*)(0x42212390UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR05 (*((volatile unsigned int*)(0x42212394UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR06 (*((volatile unsigned int*)(0x42212398UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR07 (*((volatile unsigned int*)(0x4221239CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR08 (*((volatile unsigned int*)(0x422123A0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR09 (*((volatile unsigned int*)(0x422123A4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR10 (*((volatile unsigned int*)(0x422123A8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR11 (*((volatile unsigned int*)(0x422123ACUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR12 (*((volatile unsigned int*)(0x422123B0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR13 (*((volatile unsigned int*)(0x422123B4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR14 (*((volatile unsigned int*)(0x422123B8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR15 (*((volatile unsigned int*)(0x422123BCUL))) +#define bM4_AOS_PEVNTIDR2_PIN00 (*((volatile unsigned int*)(0x42212400UL))) +#define bM4_AOS_PEVNTIDR2_PIN01 (*((volatile unsigned int*)(0x42212404UL))) +#define bM4_AOS_PEVNTIDR2_PIN02 (*((volatile unsigned int*)(0x42212408UL))) +#define bM4_AOS_PEVNTIDR2_PIN03 (*((volatile unsigned int*)(0x4221240CUL))) +#define bM4_AOS_PEVNTIDR2_PIN04 (*((volatile unsigned int*)(0x42212410UL))) +#define bM4_AOS_PEVNTIDR2_PIN05 (*((volatile unsigned int*)(0x42212414UL))) +#define bM4_AOS_PEVNTIDR2_PIN06 (*((volatile unsigned int*)(0x42212418UL))) +#define bM4_AOS_PEVNTIDR2_PIN07 (*((volatile unsigned int*)(0x4221241CUL))) +#define bM4_AOS_PEVNTIDR2_PIN08 (*((volatile unsigned int*)(0x42212420UL))) +#define bM4_AOS_PEVNTIDR2_PIN09 (*((volatile unsigned int*)(0x42212424UL))) +#define bM4_AOS_PEVNTIDR2_PIN10 (*((volatile unsigned int*)(0x42212428UL))) +#define bM4_AOS_PEVNTIDR2_PIN11 (*((volatile unsigned int*)(0x4221242CUL))) +#define bM4_AOS_PEVNTIDR2_PIN12 (*((volatile unsigned int*)(0x42212430UL))) +#define bM4_AOS_PEVNTIDR2_PIN13 (*((volatile unsigned int*)(0x42212434UL))) +#define bM4_AOS_PEVNTIDR2_PIN14 (*((volatile unsigned int*)(0x42212438UL))) +#define bM4_AOS_PEVNTIDR2_PIN15 (*((volatile unsigned int*)(0x4221243CUL))) +#define bM4_AOS_PEVNTODR2_POUT00 (*((volatile unsigned int*)(0x42212480UL))) +#define bM4_AOS_PEVNTODR2_POUT01 (*((volatile unsigned int*)(0x42212484UL))) +#define bM4_AOS_PEVNTODR2_POUT02 (*((volatile unsigned int*)(0x42212488UL))) +#define bM4_AOS_PEVNTODR2_POUT03 (*((volatile unsigned int*)(0x4221248CUL))) +#define bM4_AOS_PEVNTODR2_POUT04 (*((volatile unsigned int*)(0x42212490UL))) +#define bM4_AOS_PEVNTODR2_POUT05 (*((volatile unsigned int*)(0x42212494UL))) +#define bM4_AOS_PEVNTODR2_POUT06 (*((volatile unsigned int*)(0x42212498UL))) +#define bM4_AOS_PEVNTODR2_POUT07 (*((volatile unsigned int*)(0x4221249CUL))) +#define bM4_AOS_PEVNTODR2_POUT08 (*((volatile unsigned int*)(0x422124A0UL))) +#define bM4_AOS_PEVNTODR2_POUT09 (*((volatile unsigned int*)(0x422124A4UL))) +#define bM4_AOS_PEVNTODR2_POUT10 (*((volatile unsigned int*)(0x422124A8UL))) +#define bM4_AOS_PEVNTODR2_POUT11 (*((volatile unsigned int*)(0x422124ACUL))) +#define bM4_AOS_PEVNTODR2_POUT12 (*((volatile unsigned int*)(0x422124B0UL))) +#define bM4_AOS_PEVNTODR2_POUT13 (*((volatile unsigned int*)(0x422124B4UL))) +#define bM4_AOS_PEVNTODR2_POUT14 (*((volatile unsigned int*)(0x422124B8UL))) +#define bM4_AOS_PEVNTODR2_POUT15 (*((volatile unsigned int*)(0x422124BCUL))) +#define bM4_AOS_PEVNTORR2_POR00 (*((volatile unsigned int*)(0x42212500UL))) +#define bM4_AOS_PEVNTORR2_POR01 (*((volatile unsigned int*)(0x42212504UL))) +#define bM4_AOS_PEVNTORR2_POR02 (*((volatile unsigned int*)(0x42212508UL))) +#define bM4_AOS_PEVNTORR2_POR03 (*((volatile unsigned int*)(0x4221250CUL))) +#define bM4_AOS_PEVNTORR2_POR04 (*((volatile unsigned int*)(0x42212510UL))) +#define bM4_AOS_PEVNTORR2_POR05 (*((volatile unsigned int*)(0x42212514UL))) +#define bM4_AOS_PEVNTORR2_POR06 (*((volatile unsigned int*)(0x42212518UL))) +#define bM4_AOS_PEVNTORR2_POR07 (*((volatile unsigned int*)(0x4221251CUL))) +#define bM4_AOS_PEVNTORR2_POR08 (*((volatile unsigned int*)(0x42212520UL))) +#define bM4_AOS_PEVNTORR2_POR09 (*((volatile unsigned int*)(0x42212524UL))) +#define bM4_AOS_PEVNTORR2_POR10 (*((volatile unsigned int*)(0x42212528UL))) +#define bM4_AOS_PEVNTORR2_POR11 (*((volatile unsigned int*)(0x4221252CUL))) +#define bM4_AOS_PEVNTORR2_POR12 (*((volatile unsigned int*)(0x42212530UL))) +#define bM4_AOS_PEVNTORR2_POR13 (*((volatile unsigned int*)(0x42212534UL))) +#define bM4_AOS_PEVNTORR2_POR14 (*((volatile unsigned int*)(0x42212538UL))) +#define bM4_AOS_PEVNTORR2_POR15 (*((volatile unsigned int*)(0x4221253CUL))) +#define bM4_AOS_PEVNTOSR2_POS00 (*((volatile unsigned int*)(0x42212580UL))) +#define bM4_AOS_PEVNTOSR2_POS01 (*((volatile unsigned int*)(0x42212584UL))) +#define bM4_AOS_PEVNTOSR2_POS02 (*((volatile unsigned int*)(0x42212588UL))) +#define bM4_AOS_PEVNTOSR2_POS03 (*((volatile unsigned int*)(0x4221258CUL))) +#define bM4_AOS_PEVNTOSR2_POS04 (*((volatile unsigned int*)(0x42212590UL))) +#define bM4_AOS_PEVNTOSR2_POS05 (*((volatile unsigned int*)(0x42212594UL))) +#define bM4_AOS_PEVNTOSR2_POS06 (*((volatile unsigned int*)(0x42212598UL))) +#define bM4_AOS_PEVNTOSR2_POS07 (*((volatile unsigned int*)(0x4221259CUL))) +#define bM4_AOS_PEVNTOSR2_POS08 (*((volatile unsigned int*)(0x422125A0UL))) +#define bM4_AOS_PEVNTOSR2_POS09 (*((volatile unsigned int*)(0x422125A4UL))) +#define bM4_AOS_PEVNTOSR2_POS10 (*((volatile unsigned int*)(0x422125A8UL))) +#define bM4_AOS_PEVNTOSR2_POS11 (*((volatile unsigned int*)(0x422125ACUL))) +#define bM4_AOS_PEVNTOSR2_POS12 (*((volatile unsigned int*)(0x422125B0UL))) +#define bM4_AOS_PEVNTOSR2_POS13 (*((volatile unsigned int*)(0x422125B4UL))) +#define bM4_AOS_PEVNTOSR2_POS14 (*((volatile unsigned int*)(0x422125B8UL))) +#define bM4_AOS_PEVNTOSR2_POS15 (*((volatile unsigned int*)(0x422125BCUL))) +#define bM4_AOS_PEVNTRISR2_RIS00 (*((volatile unsigned int*)(0x42212600UL))) +#define bM4_AOS_PEVNTRISR2_RIS01 (*((volatile unsigned int*)(0x42212604UL))) +#define bM4_AOS_PEVNTRISR2_RIS02 (*((volatile unsigned int*)(0x42212608UL))) +#define bM4_AOS_PEVNTRISR2_RIS03 (*((volatile unsigned int*)(0x4221260CUL))) +#define bM4_AOS_PEVNTRISR2_RIS04 (*((volatile unsigned int*)(0x42212610UL))) +#define bM4_AOS_PEVNTRISR2_RIS05 (*((volatile unsigned int*)(0x42212614UL))) +#define bM4_AOS_PEVNTRISR2_RIS06 (*((volatile unsigned int*)(0x42212618UL))) +#define bM4_AOS_PEVNTRISR2_RIS07 (*((volatile unsigned int*)(0x4221261CUL))) +#define bM4_AOS_PEVNTRISR2_RIS08 (*((volatile unsigned int*)(0x42212620UL))) +#define bM4_AOS_PEVNTRISR2_RIS09 (*((volatile unsigned int*)(0x42212624UL))) +#define bM4_AOS_PEVNTRISR2_RIS10 (*((volatile unsigned int*)(0x42212628UL))) +#define bM4_AOS_PEVNTRISR2_RIS11 (*((volatile unsigned int*)(0x4221262CUL))) +#define bM4_AOS_PEVNTRISR2_RIS12 (*((volatile unsigned int*)(0x42212630UL))) +#define bM4_AOS_PEVNTRISR2_RIS13 (*((volatile unsigned int*)(0x42212634UL))) +#define bM4_AOS_PEVNTRISR2_RIS14 (*((volatile unsigned int*)(0x42212638UL))) +#define bM4_AOS_PEVNTRISR2_RIS15 (*((volatile unsigned int*)(0x4221263CUL))) +#define bM4_AOS_PEVNTFAL2_FAL00 (*((volatile unsigned int*)(0x42212680UL))) +#define bM4_AOS_PEVNTFAL2_FAL01 (*((volatile unsigned int*)(0x42212684UL))) +#define bM4_AOS_PEVNTFAL2_FAL02 (*((volatile unsigned int*)(0x42212688UL))) +#define bM4_AOS_PEVNTFAL2_FAL03 (*((volatile unsigned int*)(0x4221268CUL))) +#define bM4_AOS_PEVNTFAL2_FAL04 (*((volatile unsigned int*)(0x42212690UL))) +#define bM4_AOS_PEVNTFAL2_FAL05 (*((volatile unsigned int*)(0x42212694UL))) +#define bM4_AOS_PEVNTFAL2_FAL06 (*((volatile unsigned int*)(0x42212698UL))) +#define bM4_AOS_PEVNTFAL2_FAL07 (*((volatile unsigned int*)(0x4221269CUL))) +#define bM4_AOS_PEVNTFAL2_FAL08 (*((volatile unsigned int*)(0x422126A0UL))) +#define bM4_AOS_PEVNTFAL2_FAL09 (*((volatile unsigned int*)(0x422126A4UL))) +#define bM4_AOS_PEVNTFAL2_FAL10 (*((volatile unsigned int*)(0x422126A8UL))) +#define bM4_AOS_PEVNTFAL2_FAL11 (*((volatile unsigned int*)(0x422126ACUL))) +#define bM4_AOS_PEVNTFAL2_FAL12 (*((volatile unsigned int*)(0x422126B0UL))) +#define bM4_AOS_PEVNTFAL2_FAL13 (*((volatile unsigned int*)(0x422126B4UL))) +#define bM4_AOS_PEVNTFAL2_FAL14 (*((volatile unsigned int*)(0x422126B8UL))) +#define bM4_AOS_PEVNTFAL2_FAL15 (*((volatile unsigned int*)(0x422126BCUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR00 (*((volatile unsigned int*)(0x42212700UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR01 (*((volatile unsigned int*)(0x42212704UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR02 (*((volatile unsigned int*)(0x42212708UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR03 (*((volatile unsigned int*)(0x4221270CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR04 (*((volatile unsigned int*)(0x42212710UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR05 (*((volatile unsigned int*)(0x42212714UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR06 (*((volatile unsigned int*)(0x42212718UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR07 (*((volatile unsigned int*)(0x4221271CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR08 (*((volatile unsigned int*)(0x42212720UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR09 (*((volatile unsigned int*)(0x42212724UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR10 (*((volatile unsigned int*)(0x42212728UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR11 (*((volatile unsigned int*)(0x4221272CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR12 (*((volatile unsigned int*)(0x42212730UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR13 (*((volatile unsigned int*)(0x42212734UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR14 (*((volatile unsigned int*)(0x42212738UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR15 (*((volatile unsigned int*)(0x4221273CUL))) +#define bM4_AOS_PEVNTIDR3_PIN00 (*((volatile unsigned int*)(0x42212780UL))) +#define bM4_AOS_PEVNTIDR3_PIN01 (*((volatile unsigned int*)(0x42212784UL))) +#define bM4_AOS_PEVNTIDR3_PIN02 (*((volatile unsigned int*)(0x42212788UL))) +#define bM4_AOS_PEVNTIDR3_PIN03 (*((volatile unsigned int*)(0x4221278CUL))) +#define bM4_AOS_PEVNTIDR3_PIN04 (*((volatile unsigned int*)(0x42212790UL))) +#define bM4_AOS_PEVNTIDR3_PIN05 (*((volatile unsigned int*)(0x42212794UL))) +#define bM4_AOS_PEVNTIDR3_PIN06 (*((volatile unsigned int*)(0x42212798UL))) +#define bM4_AOS_PEVNTIDR3_PIN07 (*((volatile unsigned int*)(0x4221279CUL))) +#define bM4_AOS_PEVNTIDR3_PIN08 (*((volatile unsigned int*)(0x422127A0UL))) +#define bM4_AOS_PEVNTIDR3_PIN09 (*((volatile unsigned int*)(0x422127A4UL))) +#define bM4_AOS_PEVNTIDR3_PIN10 (*((volatile unsigned int*)(0x422127A8UL))) +#define bM4_AOS_PEVNTIDR3_PIN11 (*((volatile unsigned int*)(0x422127ACUL))) +#define bM4_AOS_PEVNTIDR3_PIN12 (*((volatile unsigned int*)(0x422127B0UL))) +#define bM4_AOS_PEVNTIDR3_PIN13 (*((volatile unsigned int*)(0x422127B4UL))) +#define bM4_AOS_PEVNTIDR3_PIN14 (*((volatile unsigned int*)(0x422127B8UL))) +#define bM4_AOS_PEVNTIDR3_PIN15 (*((volatile unsigned int*)(0x422127BCUL))) +#define bM4_AOS_PEVNTODR3_POUT00 (*((volatile unsigned int*)(0x42212800UL))) +#define bM4_AOS_PEVNTODR3_POUT01 (*((volatile unsigned int*)(0x42212804UL))) +#define bM4_AOS_PEVNTODR3_POUT02 (*((volatile unsigned int*)(0x42212808UL))) +#define bM4_AOS_PEVNTODR3_POUT03 (*((volatile unsigned int*)(0x4221280CUL))) +#define bM4_AOS_PEVNTODR3_POUT04 (*((volatile unsigned int*)(0x42212810UL))) +#define bM4_AOS_PEVNTODR3_POUT05 (*((volatile unsigned int*)(0x42212814UL))) +#define bM4_AOS_PEVNTODR3_POUT06 (*((volatile unsigned int*)(0x42212818UL))) +#define bM4_AOS_PEVNTODR3_POUT07 (*((volatile unsigned int*)(0x4221281CUL))) +#define bM4_AOS_PEVNTODR3_POUT08 (*((volatile unsigned int*)(0x42212820UL))) +#define bM4_AOS_PEVNTODR3_POUT09 (*((volatile unsigned int*)(0x42212824UL))) +#define bM4_AOS_PEVNTODR3_POUT10 (*((volatile unsigned int*)(0x42212828UL))) +#define bM4_AOS_PEVNTODR3_POUT11 (*((volatile unsigned int*)(0x4221282CUL))) +#define bM4_AOS_PEVNTODR3_POUT12 (*((volatile unsigned int*)(0x42212830UL))) +#define bM4_AOS_PEVNTODR3_POUT13 (*((volatile unsigned int*)(0x42212834UL))) +#define bM4_AOS_PEVNTODR3_POUT14 (*((volatile unsigned int*)(0x42212838UL))) +#define bM4_AOS_PEVNTODR3_POUT15 (*((volatile unsigned int*)(0x4221283CUL))) +#define bM4_AOS_PEVNTORR3_POR00 (*((volatile unsigned int*)(0x42212880UL))) +#define bM4_AOS_PEVNTORR3_POR01 (*((volatile unsigned int*)(0x42212884UL))) +#define bM4_AOS_PEVNTORR3_POR02 (*((volatile unsigned int*)(0x42212888UL))) +#define bM4_AOS_PEVNTORR3_POR03 (*((volatile unsigned int*)(0x4221288CUL))) +#define bM4_AOS_PEVNTORR3_POR04 (*((volatile unsigned int*)(0x42212890UL))) +#define bM4_AOS_PEVNTORR3_POR05 (*((volatile unsigned int*)(0x42212894UL))) +#define bM4_AOS_PEVNTORR3_POR06 (*((volatile unsigned int*)(0x42212898UL))) +#define bM4_AOS_PEVNTORR3_POR07 (*((volatile unsigned int*)(0x4221289CUL))) +#define bM4_AOS_PEVNTORR3_POR08 (*((volatile unsigned int*)(0x422128A0UL))) +#define bM4_AOS_PEVNTORR3_POR09 (*((volatile unsigned int*)(0x422128A4UL))) +#define bM4_AOS_PEVNTORR3_POR10 (*((volatile unsigned int*)(0x422128A8UL))) +#define bM4_AOS_PEVNTORR3_POR11 (*((volatile unsigned int*)(0x422128ACUL))) +#define bM4_AOS_PEVNTORR3_POR12 (*((volatile unsigned int*)(0x422128B0UL))) +#define bM4_AOS_PEVNTORR3_POR13 (*((volatile unsigned int*)(0x422128B4UL))) +#define bM4_AOS_PEVNTORR3_POR14 (*((volatile unsigned int*)(0x422128B8UL))) +#define bM4_AOS_PEVNTORR3_POR15 (*((volatile unsigned int*)(0x422128BCUL))) +#define bM4_AOS_PEVNTOSR3_POS00 (*((volatile unsigned int*)(0x42212900UL))) +#define bM4_AOS_PEVNTOSR3_POS01 (*((volatile unsigned int*)(0x42212904UL))) +#define bM4_AOS_PEVNTOSR3_POS02 (*((volatile unsigned int*)(0x42212908UL))) +#define bM4_AOS_PEVNTOSR3_POS03 (*((volatile unsigned int*)(0x4221290CUL))) +#define bM4_AOS_PEVNTOSR3_POS04 (*((volatile unsigned int*)(0x42212910UL))) +#define bM4_AOS_PEVNTOSR3_POS05 (*((volatile unsigned int*)(0x42212914UL))) +#define bM4_AOS_PEVNTOSR3_POS06 (*((volatile unsigned int*)(0x42212918UL))) +#define bM4_AOS_PEVNTOSR3_POS07 (*((volatile unsigned int*)(0x4221291CUL))) +#define bM4_AOS_PEVNTOSR3_POS08 (*((volatile unsigned int*)(0x42212920UL))) +#define bM4_AOS_PEVNTOSR3_POS09 (*((volatile unsigned int*)(0x42212924UL))) +#define bM4_AOS_PEVNTOSR3_POS10 (*((volatile unsigned int*)(0x42212928UL))) +#define bM4_AOS_PEVNTOSR3_POS11 (*((volatile unsigned int*)(0x4221292CUL))) +#define bM4_AOS_PEVNTOSR3_POS12 (*((volatile unsigned int*)(0x42212930UL))) +#define bM4_AOS_PEVNTOSR3_POS13 (*((volatile unsigned int*)(0x42212934UL))) +#define bM4_AOS_PEVNTOSR3_POS14 (*((volatile unsigned int*)(0x42212938UL))) +#define bM4_AOS_PEVNTOSR3_POS15 (*((volatile unsigned int*)(0x4221293CUL))) +#define bM4_AOS_PEVNTRISR3_RIS00 (*((volatile unsigned int*)(0x42212980UL))) +#define bM4_AOS_PEVNTRISR3_RIS01 (*((volatile unsigned int*)(0x42212984UL))) +#define bM4_AOS_PEVNTRISR3_RIS02 (*((volatile unsigned int*)(0x42212988UL))) +#define bM4_AOS_PEVNTRISR3_RIS03 (*((volatile unsigned int*)(0x4221298CUL))) +#define bM4_AOS_PEVNTRISR3_RIS04 (*((volatile unsigned int*)(0x42212990UL))) +#define bM4_AOS_PEVNTRISR3_RIS05 (*((volatile unsigned int*)(0x42212994UL))) +#define bM4_AOS_PEVNTRISR3_RIS06 (*((volatile unsigned int*)(0x42212998UL))) +#define bM4_AOS_PEVNTRISR3_RIS07 (*((volatile unsigned int*)(0x4221299CUL))) +#define bM4_AOS_PEVNTRISR3_RIS08 (*((volatile unsigned int*)(0x422129A0UL))) +#define bM4_AOS_PEVNTRISR3_RIS09 (*((volatile unsigned int*)(0x422129A4UL))) +#define bM4_AOS_PEVNTRISR3_RIS10 (*((volatile unsigned int*)(0x422129A8UL))) +#define bM4_AOS_PEVNTRISR3_RIS11 (*((volatile unsigned int*)(0x422129ACUL))) +#define bM4_AOS_PEVNTRISR3_RIS12 (*((volatile unsigned int*)(0x422129B0UL))) +#define bM4_AOS_PEVNTRISR3_RIS13 (*((volatile unsigned int*)(0x422129B4UL))) +#define bM4_AOS_PEVNTRISR3_RIS14 (*((volatile unsigned int*)(0x422129B8UL))) +#define bM4_AOS_PEVNTRISR3_RIS15 (*((volatile unsigned int*)(0x422129BCUL))) +#define bM4_AOS_PEVNTFAL3_FAL00 (*((volatile unsigned int*)(0x42212A00UL))) +#define bM4_AOS_PEVNTFAL3_FAL01 (*((volatile unsigned int*)(0x42212A04UL))) +#define bM4_AOS_PEVNTFAL3_FAL02 (*((volatile unsigned int*)(0x42212A08UL))) +#define bM4_AOS_PEVNTFAL3_FAL03 (*((volatile unsigned int*)(0x42212A0CUL))) +#define bM4_AOS_PEVNTFAL3_FAL04 (*((volatile unsigned int*)(0x42212A10UL))) +#define bM4_AOS_PEVNTFAL3_FAL05 (*((volatile unsigned int*)(0x42212A14UL))) +#define bM4_AOS_PEVNTFAL3_FAL06 (*((volatile unsigned int*)(0x42212A18UL))) +#define bM4_AOS_PEVNTFAL3_FAL07 (*((volatile unsigned int*)(0x42212A1CUL))) +#define bM4_AOS_PEVNTFAL3_FAL08 (*((volatile unsigned int*)(0x42212A20UL))) +#define bM4_AOS_PEVNTFAL3_FAL09 (*((volatile unsigned int*)(0x42212A24UL))) +#define bM4_AOS_PEVNTFAL3_FAL10 (*((volatile unsigned int*)(0x42212A28UL))) +#define bM4_AOS_PEVNTFAL3_FAL11 (*((volatile unsigned int*)(0x42212A2CUL))) +#define bM4_AOS_PEVNTFAL3_FAL12 (*((volatile unsigned int*)(0x42212A30UL))) +#define bM4_AOS_PEVNTFAL3_FAL13 (*((volatile unsigned int*)(0x42212A34UL))) +#define bM4_AOS_PEVNTFAL3_FAL14 (*((volatile unsigned int*)(0x42212A38UL))) +#define bM4_AOS_PEVNTFAL3_FAL15 (*((volatile unsigned int*)(0x42212A3CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR00 (*((volatile unsigned int*)(0x42212A80UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR01 (*((volatile unsigned int*)(0x42212A84UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR02 (*((volatile unsigned int*)(0x42212A88UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR03 (*((volatile unsigned int*)(0x42212A8CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR04 (*((volatile unsigned int*)(0x42212A90UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR05 (*((volatile unsigned int*)(0x42212A94UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR06 (*((volatile unsigned int*)(0x42212A98UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR07 (*((volatile unsigned int*)(0x42212A9CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR08 (*((volatile unsigned int*)(0x42212AA0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR09 (*((volatile unsigned int*)(0x42212AA4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR10 (*((volatile unsigned int*)(0x42212AA8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR11 (*((volatile unsigned int*)(0x42212AACUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR12 (*((volatile unsigned int*)(0x42212AB0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR13 (*((volatile unsigned int*)(0x42212AB4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR14 (*((volatile unsigned int*)(0x42212AB8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR15 (*((volatile unsigned int*)(0x42212ABCUL))) +#define bM4_AOS_PEVNTIDR4_PIN00 (*((volatile unsigned int*)(0x42212B00UL))) +#define bM4_AOS_PEVNTIDR4_PIN01 (*((volatile unsigned int*)(0x42212B04UL))) +#define bM4_AOS_PEVNTIDR4_PIN02 (*((volatile unsigned int*)(0x42212B08UL))) +#define bM4_AOS_PEVNTIDR4_PIN03 (*((volatile unsigned int*)(0x42212B0CUL))) +#define bM4_AOS_PEVNTIDR4_PIN04 (*((volatile unsigned int*)(0x42212B10UL))) +#define bM4_AOS_PEVNTIDR4_PIN05 (*((volatile unsigned int*)(0x42212B14UL))) +#define bM4_AOS_PEVNTIDR4_PIN06 (*((volatile unsigned int*)(0x42212B18UL))) +#define bM4_AOS_PEVNTIDR4_PIN07 (*((volatile unsigned int*)(0x42212B1CUL))) +#define bM4_AOS_PEVNTIDR4_PIN08 (*((volatile unsigned int*)(0x42212B20UL))) +#define bM4_AOS_PEVNTIDR4_PIN09 (*((volatile unsigned int*)(0x42212B24UL))) +#define bM4_AOS_PEVNTIDR4_PIN10 (*((volatile unsigned int*)(0x42212B28UL))) +#define bM4_AOS_PEVNTIDR4_PIN11 (*((volatile unsigned int*)(0x42212B2CUL))) +#define bM4_AOS_PEVNTIDR4_PIN12 (*((volatile unsigned int*)(0x42212B30UL))) +#define bM4_AOS_PEVNTIDR4_PIN13 (*((volatile unsigned int*)(0x42212B34UL))) +#define bM4_AOS_PEVNTIDR4_PIN14 (*((volatile unsigned int*)(0x42212B38UL))) +#define bM4_AOS_PEVNTIDR4_PIN15 (*((volatile unsigned int*)(0x42212B3CUL))) +#define bM4_AOS_PEVNTODR4_POUT00 (*((volatile unsigned int*)(0x42212B80UL))) +#define bM4_AOS_PEVNTODR4_POUT01 (*((volatile unsigned int*)(0x42212B84UL))) +#define bM4_AOS_PEVNTODR4_POUT02 (*((volatile unsigned int*)(0x42212B88UL))) +#define bM4_AOS_PEVNTODR4_POUT03 (*((volatile unsigned int*)(0x42212B8CUL))) +#define bM4_AOS_PEVNTODR4_POUT04 (*((volatile unsigned int*)(0x42212B90UL))) +#define bM4_AOS_PEVNTODR4_POUT05 (*((volatile unsigned int*)(0x42212B94UL))) +#define bM4_AOS_PEVNTODR4_POUT06 (*((volatile unsigned int*)(0x42212B98UL))) +#define bM4_AOS_PEVNTODR4_POUT07 (*((volatile unsigned int*)(0x42212B9CUL))) +#define bM4_AOS_PEVNTODR4_POUT08 (*((volatile unsigned int*)(0x42212BA0UL))) +#define bM4_AOS_PEVNTODR4_POUT09 (*((volatile unsigned int*)(0x42212BA4UL))) +#define bM4_AOS_PEVNTODR4_POUT10 (*((volatile unsigned int*)(0x42212BA8UL))) +#define bM4_AOS_PEVNTODR4_POUT11 (*((volatile unsigned int*)(0x42212BACUL))) +#define bM4_AOS_PEVNTODR4_POUT12 (*((volatile unsigned int*)(0x42212BB0UL))) +#define bM4_AOS_PEVNTODR4_POUT13 (*((volatile unsigned int*)(0x42212BB4UL))) +#define bM4_AOS_PEVNTODR4_POUT14 (*((volatile unsigned int*)(0x42212BB8UL))) +#define bM4_AOS_PEVNTODR4_POUT15 (*((volatile unsigned int*)(0x42212BBCUL))) +#define bM4_AOS_PEVNTORR4_POR00 (*((volatile unsigned int*)(0x42212C00UL))) +#define bM4_AOS_PEVNTORR4_POR01 (*((volatile unsigned int*)(0x42212C04UL))) +#define bM4_AOS_PEVNTORR4_POR02 (*((volatile unsigned int*)(0x42212C08UL))) +#define bM4_AOS_PEVNTORR4_POR03 (*((volatile unsigned int*)(0x42212C0CUL))) +#define bM4_AOS_PEVNTORR4_POR04 (*((volatile unsigned int*)(0x42212C10UL))) +#define bM4_AOS_PEVNTORR4_POR05 (*((volatile unsigned int*)(0x42212C14UL))) +#define bM4_AOS_PEVNTORR4_POR06 (*((volatile unsigned int*)(0x42212C18UL))) +#define bM4_AOS_PEVNTORR4_POR07 (*((volatile unsigned int*)(0x42212C1CUL))) +#define bM4_AOS_PEVNTORR4_POR08 (*((volatile unsigned int*)(0x42212C20UL))) +#define bM4_AOS_PEVNTORR4_POR09 (*((volatile unsigned int*)(0x42212C24UL))) +#define bM4_AOS_PEVNTORR4_POR10 (*((volatile unsigned int*)(0x42212C28UL))) +#define bM4_AOS_PEVNTORR4_POR11 (*((volatile unsigned int*)(0x42212C2CUL))) +#define bM4_AOS_PEVNTORR4_POR12 (*((volatile unsigned int*)(0x42212C30UL))) +#define bM4_AOS_PEVNTORR4_POR13 (*((volatile unsigned int*)(0x42212C34UL))) +#define bM4_AOS_PEVNTORR4_POR14 (*((volatile unsigned int*)(0x42212C38UL))) +#define bM4_AOS_PEVNTORR4_POR15 (*((volatile unsigned int*)(0x42212C3CUL))) +#define bM4_AOS_PEVNTOSR4_POS00 (*((volatile unsigned int*)(0x42212C80UL))) +#define bM4_AOS_PEVNTOSR4_POS01 (*((volatile unsigned int*)(0x42212C84UL))) +#define bM4_AOS_PEVNTOSR4_POS02 (*((volatile unsigned int*)(0x42212C88UL))) +#define bM4_AOS_PEVNTOSR4_POS03 (*((volatile unsigned int*)(0x42212C8CUL))) +#define bM4_AOS_PEVNTOSR4_POS04 (*((volatile unsigned int*)(0x42212C90UL))) +#define bM4_AOS_PEVNTOSR4_POS05 (*((volatile unsigned int*)(0x42212C94UL))) +#define bM4_AOS_PEVNTOSR4_POS06 (*((volatile unsigned int*)(0x42212C98UL))) +#define bM4_AOS_PEVNTOSR4_POS07 (*((volatile unsigned int*)(0x42212C9CUL))) +#define bM4_AOS_PEVNTOSR4_POS08 (*((volatile unsigned int*)(0x42212CA0UL))) +#define bM4_AOS_PEVNTOSR4_POS09 (*((volatile unsigned int*)(0x42212CA4UL))) +#define bM4_AOS_PEVNTOSR4_POS10 (*((volatile unsigned int*)(0x42212CA8UL))) +#define bM4_AOS_PEVNTOSR4_POS11 (*((volatile unsigned int*)(0x42212CACUL))) +#define bM4_AOS_PEVNTOSR4_POS12 (*((volatile unsigned int*)(0x42212CB0UL))) +#define bM4_AOS_PEVNTOSR4_POS13 (*((volatile unsigned int*)(0x42212CB4UL))) +#define bM4_AOS_PEVNTOSR4_POS14 (*((volatile unsigned int*)(0x42212CB8UL))) +#define bM4_AOS_PEVNTOSR4_POS15 (*((volatile unsigned int*)(0x42212CBCUL))) +#define bM4_AOS_PEVNTRISR4_RIS00 (*((volatile unsigned int*)(0x42212D00UL))) +#define bM4_AOS_PEVNTRISR4_RIS01 (*((volatile unsigned int*)(0x42212D04UL))) +#define bM4_AOS_PEVNTRISR4_RIS02 (*((volatile unsigned int*)(0x42212D08UL))) +#define bM4_AOS_PEVNTRISR4_RIS03 (*((volatile unsigned int*)(0x42212D0CUL))) +#define bM4_AOS_PEVNTRISR4_RIS04 (*((volatile unsigned int*)(0x42212D10UL))) +#define bM4_AOS_PEVNTRISR4_RIS05 (*((volatile unsigned int*)(0x42212D14UL))) +#define bM4_AOS_PEVNTRISR4_RIS06 (*((volatile unsigned int*)(0x42212D18UL))) +#define bM4_AOS_PEVNTRISR4_RIS07 (*((volatile unsigned int*)(0x42212D1CUL))) +#define bM4_AOS_PEVNTRISR4_RIS08 (*((volatile unsigned int*)(0x42212D20UL))) +#define bM4_AOS_PEVNTRISR4_RIS09 (*((volatile unsigned int*)(0x42212D24UL))) +#define bM4_AOS_PEVNTRISR4_RIS10 (*((volatile unsigned int*)(0x42212D28UL))) +#define bM4_AOS_PEVNTRISR4_RIS11 (*((volatile unsigned int*)(0x42212D2CUL))) +#define bM4_AOS_PEVNTRISR4_RIS12 (*((volatile unsigned int*)(0x42212D30UL))) +#define bM4_AOS_PEVNTRISR4_RIS13 (*((volatile unsigned int*)(0x42212D34UL))) +#define bM4_AOS_PEVNTRISR4_RIS14 (*((volatile unsigned int*)(0x42212D38UL))) +#define bM4_AOS_PEVNTRISR4_RIS15 (*((volatile unsigned int*)(0x42212D3CUL))) +#define bM4_AOS_PEVNTFAL4_FAL00 (*((volatile unsigned int*)(0x42212D80UL))) +#define bM4_AOS_PEVNTFAL4_FAL01 (*((volatile unsigned int*)(0x42212D84UL))) +#define bM4_AOS_PEVNTFAL4_FAL02 (*((volatile unsigned int*)(0x42212D88UL))) +#define bM4_AOS_PEVNTFAL4_FAL03 (*((volatile unsigned int*)(0x42212D8CUL))) +#define bM4_AOS_PEVNTFAL4_FAL04 (*((volatile unsigned int*)(0x42212D90UL))) +#define bM4_AOS_PEVNTFAL4_FAL05 (*((volatile unsigned int*)(0x42212D94UL))) +#define bM4_AOS_PEVNTFAL4_FAL06 (*((volatile unsigned int*)(0x42212D98UL))) +#define bM4_AOS_PEVNTFAL4_FAL07 (*((volatile unsigned int*)(0x42212D9CUL))) +#define bM4_AOS_PEVNTFAL4_FAL08 (*((volatile unsigned int*)(0x42212DA0UL))) +#define bM4_AOS_PEVNTFAL4_FAL09 (*((volatile unsigned int*)(0x42212DA4UL))) +#define bM4_AOS_PEVNTFAL4_FAL10 (*((volatile unsigned int*)(0x42212DA8UL))) +#define bM4_AOS_PEVNTFAL4_FAL11 (*((volatile unsigned int*)(0x42212DACUL))) +#define bM4_AOS_PEVNTFAL4_FAL12 (*((volatile unsigned int*)(0x42212DB0UL))) +#define bM4_AOS_PEVNTFAL4_FAL13 (*((volatile unsigned int*)(0x42212DB4UL))) +#define bM4_AOS_PEVNTFAL4_FAL14 (*((volatile unsigned int*)(0x42212DB8UL))) +#define bM4_AOS_PEVNTFAL4_FAL15 (*((volatile unsigned int*)(0x42212DBCUL))) +#define bM4_AOS_PEVNTNFCR_NFEN1 (*((volatile unsigned int*)(0x42212E00UL))) +#define bM4_AOS_PEVNTNFCR_DIVS10 (*((volatile unsigned int*)(0x42212E04UL))) +#define bM4_AOS_PEVNTNFCR_DIVS11 (*((volatile unsigned int*)(0x42212E08UL))) +#define bM4_AOS_PEVNTNFCR_NFEN2 (*((volatile unsigned int*)(0x42212E20UL))) +#define bM4_AOS_PEVNTNFCR_DIVS20 (*((volatile unsigned int*)(0x42212E24UL))) +#define bM4_AOS_PEVNTNFCR_DIVS21 (*((volatile unsigned int*)(0x42212E28UL))) +#define bM4_AOS_PEVNTNFCR_NFEN3 (*((volatile unsigned int*)(0x42212E40UL))) +#define bM4_AOS_PEVNTNFCR_DIVS30 (*((volatile unsigned int*)(0x42212E44UL))) +#define bM4_AOS_PEVNTNFCR_DIVS31 (*((volatile unsigned int*)(0x42212E48UL))) +#define bM4_AOS_PEVNTNFCR_NFEN4 (*((volatile unsigned int*)(0x42212E60UL))) +#define bM4_AOS_PEVNTNFCR_DIVS40 (*((volatile unsigned int*)(0x42212E64UL))) +#define bM4_AOS_PEVNTNFCR_DIVS41 (*((volatile unsigned int*)(0x42212E68UL))) +#define bM4_CAN_CFG_STAT_BUSOFF (*((volatile unsigned int*)(0x42E09400UL))) +#define bM4_CAN_CFG_STAT_TACTIVE (*((volatile unsigned int*)(0x42E09404UL))) +#define bM4_CAN_CFG_STAT_RACTIVE (*((volatile unsigned int*)(0x42E09408UL))) +#define bM4_CAN_CFG_STAT_TSSS (*((volatile unsigned int*)(0x42E0940CUL))) +#define bM4_CAN_CFG_STAT_TPSS (*((volatile unsigned int*)(0x42E09410UL))) +#define bM4_CAN_CFG_STAT_LBMI (*((volatile unsigned int*)(0x42E09414UL))) +#define bM4_CAN_CFG_STAT_LBME (*((volatile unsigned int*)(0x42E09418UL))) +#define bM4_CAN_CFG_STAT_RESET (*((volatile unsigned int*)(0x42E0941CUL))) +#define bM4_CAN_TCMD_TSA (*((volatile unsigned int*)(0x42E09420UL))) +#define bM4_CAN_TCMD_TSALL (*((volatile unsigned int*)(0x42E09424UL))) +#define bM4_CAN_TCMD_TSONE (*((volatile unsigned int*)(0x42E09428UL))) +#define bM4_CAN_TCMD_TPA (*((volatile unsigned int*)(0x42E0942CUL))) +#define bM4_CAN_TCMD_TPE (*((volatile unsigned int*)(0x42E09430UL))) +#define bM4_CAN_TCMD_STBY (*((volatile unsigned int*)(0x42E09434UL))) +#define bM4_CAN_TCMD_LOM (*((volatile unsigned int*)(0x42E09438UL))) +#define bM4_CAN_TCMD_TBSEL (*((volatile unsigned int*)(0x42E0943CUL))) +#define bM4_CAN_TCTRL_TSSTAT0 (*((volatile unsigned int*)(0x42E09440UL))) +#define bM4_CAN_TCTRL_TSSTAT1 (*((volatile unsigned int*)(0x42E09444UL))) +#define bM4_CAN_TCTRL_TTBM (*((volatile unsigned int*)(0x42E09450UL))) +#define bM4_CAN_TCTRL_TSMODE (*((volatile unsigned int*)(0x42E09454UL))) +#define bM4_CAN_TCTRL_TSNEXT (*((volatile unsigned int*)(0x42E09458UL))) +#define bM4_CAN_RCTRL_RSSTAT0 (*((volatile unsigned int*)(0x42E09460UL))) +#define bM4_CAN_RCTRL_RSSTAT1 (*((volatile unsigned int*)(0x42E09464UL))) +#define bM4_CAN_RCTRL_RBALL (*((volatile unsigned int*)(0x42E0946CUL))) +#define bM4_CAN_RCTRL_RREL (*((volatile unsigned int*)(0x42E09470UL))) +#define bM4_CAN_RCTRL_ROV (*((volatile unsigned int*)(0x42E09474UL))) +#define bM4_CAN_RCTRL_ROM (*((volatile unsigned int*)(0x42E09478UL))) +#define bM4_CAN_RCTRL_SACK (*((volatile unsigned int*)(0x42E0947CUL))) +#define bM4_CAN_RTIE_TSFF (*((volatile unsigned int*)(0x42E09480UL))) +#define bM4_CAN_RTIE_EIE (*((volatile unsigned int*)(0x42E09484UL))) +#define bM4_CAN_RTIE_TSIE (*((volatile unsigned int*)(0x42E09488UL))) +#define bM4_CAN_RTIE_TPIE (*((volatile unsigned int*)(0x42E0948CUL))) +#define bM4_CAN_RTIE_RAFIE (*((volatile unsigned int*)(0x42E09490UL))) +#define bM4_CAN_RTIE_RFIE (*((volatile unsigned int*)(0x42E09494UL))) +#define bM4_CAN_RTIE_ROIE (*((volatile unsigned int*)(0x42E09498UL))) +#define bM4_CAN_RTIE_RIE (*((volatile unsigned int*)(0x42E0949CUL))) +#define bM4_CAN_RTIF_AIF (*((volatile unsigned int*)(0x42E094A0UL))) +#define bM4_CAN_RTIF_EIF (*((volatile unsigned int*)(0x42E094A4UL))) +#define bM4_CAN_RTIF_TSIF (*((volatile unsigned int*)(0x42E094A8UL))) +#define bM4_CAN_RTIF_TPIF (*((volatile unsigned int*)(0x42E094ACUL))) +#define bM4_CAN_RTIF_RAFIF (*((volatile unsigned int*)(0x42E094B0UL))) +#define bM4_CAN_RTIF_RFIF (*((volatile unsigned int*)(0x42E094B4UL))) +#define bM4_CAN_RTIF_ROIF (*((volatile unsigned int*)(0x42E094B8UL))) +#define bM4_CAN_RTIF_RIF (*((volatile unsigned int*)(0x42E094BCUL))) +#define bM4_CAN_ERRINT_BEIF (*((volatile unsigned int*)(0x42E094C0UL))) +#define bM4_CAN_ERRINT_BEIE (*((volatile unsigned int*)(0x42E094C4UL))) +#define bM4_CAN_ERRINT_ALIF (*((volatile unsigned int*)(0x42E094C8UL))) +#define bM4_CAN_ERRINT_ALIE (*((volatile unsigned int*)(0x42E094CCUL))) +#define bM4_CAN_ERRINT_EPIF (*((volatile unsigned int*)(0x42E094D0UL))) +#define bM4_CAN_ERRINT_EPIE (*((volatile unsigned int*)(0x42E094D4UL))) +#define bM4_CAN_ERRINT_EPASS (*((volatile unsigned int*)(0x42E094D8UL))) +#define bM4_CAN_ERRINT_EWARN (*((volatile unsigned int*)(0x42E094DCUL))) +#define bM4_CAN_LIMIT_EWL0 (*((volatile unsigned int*)(0x42E094E0UL))) +#define bM4_CAN_LIMIT_EWL1 (*((volatile unsigned int*)(0x42E094E4UL))) +#define bM4_CAN_LIMIT_EWL2 (*((volatile unsigned int*)(0x42E094E8UL))) +#define bM4_CAN_LIMIT_EWL3 (*((volatile unsigned int*)(0x42E094ECUL))) +#define bM4_CAN_LIMIT_AFWL0 (*((volatile unsigned int*)(0x42E094F0UL))) +#define bM4_CAN_LIMIT_AFWL1 (*((volatile unsigned int*)(0x42E094F4UL))) +#define bM4_CAN_LIMIT_AFWL2 (*((volatile unsigned int*)(0x42E094F8UL))) +#define bM4_CAN_LIMIT_AFWL3 (*((volatile unsigned int*)(0x42E094FCUL))) +#define bM4_CAN_BT_SEG_10 (*((volatile unsigned int*)(0x42E09500UL))) +#define bM4_CAN_BT_SEG_11 (*((volatile unsigned int*)(0x42E09504UL))) +#define bM4_CAN_BT_SEG_12 (*((volatile unsigned int*)(0x42E09508UL))) +#define bM4_CAN_BT_SEG_13 (*((volatile unsigned int*)(0x42E0950CUL))) +#define bM4_CAN_BT_SEG_14 (*((volatile unsigned int*)(0x42E09510UL))) +#define bM4_CAN_BT_SEG_15 (*((volatile unsigned int*)(0x42E09514UL))) +#define bM4_CAN_BT_SEG_16 (*((volatile unsigned int*)(0x42E09518UL))) +#define bM4_CAN_BT_SEG_17 (*((volatile unsigned int*)(0x42E0951CUL))) +#define bM4_CAN_BT_SEG_20 (*((volatile unsigned int*)(0x42E09520UL))) +#define bM4_CAN_BT_SEG_21 (*((volatile unsigned int*)(0x42E09524UL))) +#define bM4_CAN_BT_SEG_22 (*((volatile unsigned int*)(0x42E09528UL))) +#define bM4_CAN_BT_SEG_23 (*((volatile unsigned int*)(0x42E0952CUL))) +#define bM4_CAN_BT_SEG_24 (*((volatile unsigned int*)(0x42E09530UL))) +#define bM4_CAN_BT_SEG_25 (*((volatile unsigned int*)(0x42E09534UL))) +#define bM4_CAN_BT_SEG_26 (*((volatile unsigned int*)(0x42E09538UL))) +#define bM4_CAN_BT_SJW0 (*((volatile unsigned int*)(0x42E09540UL))) +#define bM4_CAN_BT_SJW1 (*((volatile unsigned int*)(0x42E09544UL))) +#define bM4_CAN_BT_SJW2 (*((volatile unsigned int*)(0x42E09548UL))) +#define bM4_CAN_BT_SJW3 (*((volatile unsigned int*)(0x42E0954CUL))) +#define bM4_CAN_BT_SJW4 (*((volatile unsigned int*)(0x42E09550UL))) +#define bM4_CAN_BT_SJW5 (*((volatile unsigned int*)(0x42E09554UL))) +#define bM4_CAN_BT_SJW6 (*((volatile unsigned int*)(0x42E09558UL))) +#define bM4_CAN_BT_PRESC0 (*((volatile unsigned int*)(0x42E09560UL))) +#define bM4_CAN_BT_PRESC1 (*((volatile unsigned int*)(0x42E09564UL))) +#define bM4_CAN_BT_PRESC2 (*((volatile unsigned int*)(0x42E09568UL))) +#define bM4_CAN_BT_PRESC3 (*((volatile unsigned int*)(0x42E0956CUL))) +#define bM4_CAN_BT_PRESC4 (*((volatile unsigned int*)(0x42E09570UL))) +#define bM4_CAN_BT_PRESC5 (*((volatile unsigned int*)(0x42E09574UL))) +#define bM4_CAN_BT_PRESC6 (*((volatile unsigned int*)(0x42E09578UL))) +#define bM4_CAN_BT_PRESC7 (*((volatile unsigned int*)(0x42E0957CUL))) +#define bM4_CAN_EALCAP_ALC0 (*((volatile unsigned int*)(0x42E09600UL))) +#define bM4_CAN_EALCAP_ALC1 (*((volatile unsigned int*)(0x42E09604UL))) +#define bM4_CAN_EALCAP_ALC2 (*((volatile unsigned int*)(0x42E09608UL))) +#define bM4_CAN_EALCAP_ALC3 (*((volatile unsigned int*)(0x42E0960CUL))) +#define bM4_CAN_EALCAP_ALC4 (*((volatile unsigned int*)(0x42E09610UL))) +#define bM4_CAN_EALCAP_KOER0 (*((volatile unsigned int*)(0x42E09614UL))) +#define bM4_CAN_EALCAP_KOER1 (*((volatile unsigned int*)(0x42E09618UL))) +#define bM4_CAN_EALCAP_KOER2 (*((volatile unsigned int*)(0x42E0961CUL))) +#define bM4_CAN_ACFCTRL_ACFADR0 (*((volatile unsigned int*)(0x42E09680UL))) +#define bM4_CAN_ACFCTRL_ACFADR1 (*((volatile unsigned int*)(0x42E09684UL))) +#define bM4_CAN_ACFCTRL_ACFADR2 (*((volatile unsigned int*)(0x42E09688UL))) +#define bM4_CAN_ACFCTRL_ACFADR3 (*((volatile unsigned int*)(0x42E0968CUL))) +#define bM4_CAN_ACFCTRL_SELMASK (*((volatile unsigned int*)(0x42E09694UL))) +#define bM4_CAN_ACFEN_AE_1 (*((volatile unsigned int*)(0x42E096C0UL))) +#define bM4_CAN_ACFEN_AE_2 (*((volatile unsigned int*)(0x42E096C4UL))) +#define bM4_CAN_ACFEN_AE_3 (*((volatile unsigned int*)(0x42E096C8UL))) +#define bM4_CAN_ACFEN_AE_4 (*((volatile unsigned int*)(0x42E096CCUL))) +#define bM4_CAN_ACFEN_AE_5 (*((volatile unsigned int*)(0x42E096D0UL))) +#define bM4_CAN_ACFEN_AE_6 (*((volatile unsigned int*)(0x42E096D4UL))) +#define bM4_CAN_ACFEN_AE_7 (*((volatile unsigned int*)(0x42E096D8UL))) +#define bM4_CAN_ACFEN_AE_8 (*((volatile unsigned int*)(0x42E096DCUL))) +#define bM4_CAN_ACF_ACODEORAMASK0 (*((volatile unsigned int*)(0x42E09700UL))) +#define bM4_CAN_ACF_ACODEORAMASK1 (*((volatile unsigned int*)(0x42E09704UL))) +#define bM4_CAN_ACF_ACODEORAMASK2 (*((volatile unsigned int*)(0x42E09708UL))) +#define bM4_CAN_ACF_ACODEORAMASK3 (*((volatile unsigned int*)(0x42E0970CUL))) +#define bM4_CAN_ACF_ACODEORAMASK4 (*((volatile unsigned int*)(0x42E09710UL))) +#define bM4_CAN_ACF_ACODEORAMASK5 (*((volatile unsigned int*)(0x42E09714UL))) +#define bM4_CAN_ACF_ACODEORAMASK6 (*((volatile unsigned int*)(0x42E09718UL))) +#define bM4_CAN_ACF_ACODEORAMASK7 (*((volatile unsigned int*)(0x42E0971CUL))) +#define bM4_CAN_ACF_ACODEORAMASK8 (*((volatile unsigned int*)(0x42E09720UL))) +#define bM4_CAN_ACF_ACODEORAMASK9 (*((volatile unsigned int*)(0x42E09724UL))) +#define bM4_CAN_ACF_ACODEORAMASK10 (*((volatile unsigned int*)(0x42E09728UL))) +#define bM4_CAN_ACF_ACODEORAMASK11 (*((volatile unsigned int*)(0x42E0972CUL))) +#define bM4_CAN_ACF_ACODEORAMASK12 (*((volatile unsigned int*)(0x42E09730UL))) +#define bM4_CAN_ACF_ACODEORAMASK13 (*((volatile unsigned int*)(0x42E09734UL))) +#define bM4_CAN_ACF_ACODEORAMASK14 (*((volatile unsigned int*)(0x42E09738UL))) +#define bM4_CAN_ACF_ACODEORAMASK15 (*((volatile unsigned int*)(0x42E0973CUL))) +#define bM4_CAN_ACF_ACODEORAMASK16 (*((volatile unsigned int*)(0x42E09740UL))) +#define bM4_CAN_ACF_ACODEORAMASK17 (*((volatile unsigned int*)(0x42E09744UL))) +#define bM4_CAN_ACF_ACODEORAMASK18 (*((volatile unsigned int*)(0x42E09748UL))) +#define bM4_CAN_ACF_ACODEORAMASK19 (*((volatile unsigned int*)(0x42E0974CUL))) +#define bM4_CAN_ACF_ACODEORAMASK20 (*((volatile unsigned int*)(0x42E09750UL))) +#define bM4_CAN_ACF_ACODEORAMASK21 (*((volatile unsigned int*)(0x42E09754UL))) +#define bM4_CAN_ACF_ACODEORAMASK22 (*((volatile unsigned int*)(0x42E09758UL))) +#define bM4_CAN_ACF_ACODEORAMASK23 (*((volatile unsigned int*)(0x42E0975CUL))) +#define bM4_CAN_ACF_ACODEORAMASK24 (*((volatile unsigned int*)(0x42E09760UL))) +#define bM4_CAN_ACF_ACODEORAMASK25 (*((volatile unsigned int*)(0x42E09764UL))) +#define bM4_CAN_ACF_ACODEORAMASK26 (*((volatile unsigned int*)(0x42E09768UL))) +#define bM4_CAN_ACF_ACODEORAMASK27 (*((volatile unsigned int*)(0x42E0976CUL))) +#define bM4_CAN_ACF_ACODEORAMASK28 (*((volatile unsigned int*)(0x42E09770UL))) +#define bM4_CAN_ACF_AIDE (*((volatile unsigned int*)(0x42E09774UL))) +#define bM4_CAN_ACF_AIDEE (*((volatile unsigned int*)(0x42E09778UL))) +#define bM4_CAN_TBSLOT_TBPTR0 (*((volatile unsigned int*)(0x42E097C0UL))) +#define bM4_CAN_TBSLOT_TBPTR1 (*((volatile unsigned int*)(0x42E097C4UL))) +#define bM4_CAN_TBSLOT_TBPTR2 (*((volatile unsigned int*)(0x42E097C8UL))) +#define bM4_CAN_TBSLOT_TBPTR3 (*((volatile unsigned int*)(0x42E097CCUL))) +#define bM4_CAN_TBSLOT_TBPTR4 (*((volatile unsigned int*)(0x42E097D0UL))) +#define bM4_CAN_TBSLOT_TBPTR5 (*((volatile unsigned int*)(0x42E097D4UL))) +#define bM4_CAN_TBSLOT_TBF (*((volatile unsigned int*)(0x42E097D8UL))) +#define bM4_CAN_TBSLOT_TBE (*((volatile unsigned int*)(0x42E097DCUL))) +#define bM4_CAN_TTCFG_TTEN (*((volatile unsigned int*)(0x42E097E0UL))) +#define bM4_CAN_TTCFG_T_PRESC0 (*((volatile unsigned int*)(0x42E097E4UL))) +#define bM4_CAN_TTCFG_T_PRESC1 (*((volatile unsigned int*)(0x42E097E8UL))) +#define bM4_CAN_TTCFG_TTIF (*((volatile unsigned int*)(0x42E097ECUL))) +#define bM4_CAN_TTCFG_TTIE (*((volatile unsigned int*)(0x42E097F0UL))) +#define bM4_CAN_TTCFG_TEIF (*((volatile unsigned int*)(0x42E097F4UL))) +#define bM4_CAN_TTCFG_WTIF (*((volatile unsigned int*)(0x42E097F8UL))) +#define bM4_CAN_TTCFG_WTIE (*((volatile unsigned int*)(0x42E097FCUL))) +#define bM4_CAN_REF_MSG_REF_ID0 (*((volatile unsigned int*)(0x42E09800UL))) +#define bM4_CAN_REF_MSG_REF_ID1 (*((volatile unsigned int*)(0x42E09804UL))) +#define bM4_CAN_REF_MSG_REF_ID2 (*((volatile unsigned int*)(0x42E09808UL))) +#define bM4_CAN_REF_MSG_REF_ID3 (*((volatile unsigned int*)(0x42E0980CUL))) +#define bM4_CAN_REF_MSG_REF_ID4 (*((volatile unsigned int*)(0x42E09810UL))) +#define bM4_CAN_REF_MSG_REF_ID5 (*((volatile unsigned int*)(0x42E09814UL))) +#define bM4_CAN_REF_MSG_REF_ID6 (*((volatile unsigned int*)(0x42E09818UL))) +#define bM4_CAN_REF_MSG_REF_ID7 (*((volatile unsigned int*)(0x42E0981CUL))) +#define bM4_CAN_REF_MSG_REF_ID8 (*((volatile unsigned int*)(0x42E09820UL))) +#define bM4_CAN_REF_MSG_REF_ID9 (*((volatile unsigned int*)(0x42E09824UL))) +#define bM4_CAN_REF_MSG_REF_ID10 (*((volatile unsigned int*)(0x42E09828UL))) +#define bM4_CAN_REF_MSG_REF_ID11 (*((volatile unsigned int*)(0x42E0982CUL))) +#define bM4_CAN_REF_MSG_REF_ID12 (*((volatile unsigned int*)(0x42E09830UL))) +#define bM4_CAN_REF_MSG_REF_ID13 (*((volatile unsigned int*)(0x42E09834UL))) +#define bM4_CAN_REF_MSG_REF_ID14 (*((volatile unsigned int*)(0x42E09838UL))) +#define bM4_CAN_REF_MSG_REF_ID15 (*((volatile unsigned int*)(0x42E0983CUL))) +#define bM4_CAN_REF_MSG_REF_ID16 (*((volatile unsigned int*)(0x42E09840UL))) +#define bM4_CAN_REF_MSG_REF_ID17 (*((volatile unsigned int*)(0x42E09844UL))) +#define bM4_CAN_REF_MSG_REF_ID18 (*((volatile unsigned int*)(0x42E09848UL))) +#define bM4_CAN_REF_MSG_REF_ID19 (*((volatile unsigned int*)(0x42E0984CUL))) +#define bM4_CAN_REF_MSG_REF_ID20 (*((volatile unsigned int*)(0x42E09850UL))) +#define bM4_CAN_REF_MSG_REF_ID21 (*((volatile unsigned int*)(0x42E09854UL))) +#define bM4_CAN_REF_MSG_REF_ID22 (*((volatile unsigned int*)(0x42E09858UL))) +#define bM4_CAN_REF_MSG_REF_ID23 (*((volatile unsigned int*)(0x42E0985CUL))) +#define bM4_CAN_REF_MSG_REF_ID24 (*((volatile unsigned int*)(0x42E09860UL))) +#define bM4_CAN_REF_MSG_REF_ID25 (*((volatile unsigned int*)(0x42E09864UL))) +#define bM4_CAN_REF_MSG_REF_ID26 (*((volatile unsigned int*)(0x42E09868UL))) +#define bM4_CAN_REF_MSG_REF_ID27 (*((volatile unsigned int*)(0x42E0986CUL))) +#define bM4_CAN_REF_MSG_REF_ID28 (*((volatile unsigned int*)(0x42E09870UL))) +#define bM4_CAN_REF_MSG_REF_IDE (*((volatile unsigned int*)(0x42E0987CUL))) +#define bM4_CAN_TRG_CFG_TTPTR0 (*((volatile unsigned int*)(0x42E09880UL))) +#define bM4_CAN_TRG_CFG_TTPTR1 (*((volatile unsigned int*)(0x42E09884UL))) +#define bM4_CAN_TRG_CFG_TTPTR2 (*((volatile unsigned int*)(0x42E09888UL))) +#define bM4_CAN_TRG_CFG_TTPTR3 (*((volatile unsigned int*)(0x42E0988CUL))) +#define bM4_CAN_TRG_CFG_TTPTR4 (*((volatile unsigned int*)(0x42E09890UL))) +#define bM4_CAN_TRG_CFG_TTPTR5 (*((volatile unsigned int*)(0x42E09894UL))) +#define bM4_CAN_TRG_CFG_TTYPE0 (*((volatile unsigned int*)(0x42E098A0UL))) +#define bM4_CAN_TRG_CFG_TTYPE1 (*((volatile unsigned int*)(0x42E098A4UL))) +#define bM4_CAN_TRG_CFG_TTYPE2 (*((volatile unsigned int*)(0x42E098A8UL))) +#define bM4_CAN_TRG_CFG_TEW0 (*((volatile unsigned int*)(0x42E098B0UL))) +#define bM4_CAN_TRG_CFG_TEW1 (*((volatile unsigned int*)(0x42E098B4UL))) +#define bM4_CAN_TRG_CFG_TEW2 (*((volatile unsigned int*)(0x42E098B8UL))) +#define bM4_CAN_TRG_CFG_TEW3 (*((volatile unsigned int*)(0x42E098BCUL))) +#define bM4_CMP1_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940000UL))) +#define bM4_CMP1_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940004UL))) +#define bM4_CMP1_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940008UL))) +#define bM4_CMP1_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940014UL))) +#define bM4_CMP1_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940018UL))) +#define bM4_CMP1_CTRL_IEN (*((volatile unsigned int*)(0x4294001CUL))) +#define bM4_CMP1_CTRL_CVSEN (*((volatile unsigned int*)(0x42940020UL))) +#define bM4_CMP1_CTRL_OUTEN (*((volatile unsigned int*)(0x42940030UL))) +#define bM4_CMP1_CTRL_INV (*((volatile unsigned int*)(0x42940034UL))) +#define bM4_CMP1_CTRL_CMPOE (*((volatile unsigned int*)(0x42940038UL))) +#define bM4_CMP1_CTRL_CMPON (*((volatile unsigned int*)(0x4294003CUL))) +#define bM4_CMP1_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940040UL))) +#define bM4_CMP1_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940044UL))) +#define bM4_CMP1_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940048UL))) +#define bM4_CMP1_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294004CUL))) +#define bM4_CMP1_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940060UL))) +#define bM4_CMP1_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940064UL))) +#define bM4_CMP1_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940068UL))) +#define bM4_CMP1_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294006CUL))) +#define bM4_CMP1_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940070UL))) +#define bM4_CMP1_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940074UL))) +#define bM4_CMP1_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940078UL))) +#define bM4_CMP1_MON_OMON (*((volatile unsigned int*)(0x42940080UL))) +#define bM4_CMP1_MON_CVST0 (*((volatile unsigned int*)(0x429400A0UL))) +#define bM4_CMP1_MON_CVST1 (*((volatile unsigned int*)(0x429400A4UL))) +#define bM4_CMP1_MON_CVST2 (*((volatile unsigned int*)(0x429400A8UL))) +#define bM4_CMP1_MON_CVST3 (*((volatile unsigned int*)(0x429400ACUL))) +#define bM4_CMP1_CVSSTB_STB0 (*((volatile unsigned int*)(0x429400C0UL))) +#define bM4_CMP1_CVSSTB_STB1 (*((volatile unsigned int*)(0x429400C4UL))) +#define bM4_CMP1_CVSSTB_STB2 (*((volatile unsigned int*)(0x429400C8UL))) +#define bM4_CMP1_CVSSTB_STB3 (*((volatile unsigned int*)(0x429400CCUL))) +#define bM4_CMP1_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940100UL))) +#define bM4_CMP1_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940104UL))) +#define bM4_CMP1_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940108UL))) +#define bM4_CMP1_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294010CUL))) +#define bM4_CMP1_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940110UL))) +#define bM4_CMP1_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940114UL))) +#define bM4_CMP1_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940118UL))) +#define bM4_CMP1_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294011CUL))) +#define bM4_CMP2_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940200UL))) +#define bM4_CMP2_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940204UL))) +#define bM4_CMP2_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940208UL))) +#define bM4_CMP2_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940214UL))) +#define bM4_CMP2_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940218UL))) +#define bM4_CMP2_CTRL_IEN (*((volatile unsigned int*)(0x4294021CUL))) +#define bM4_CMP2_CTRL_CVSEN (*((volatile unsigned int*)(0x42940220UL))) +#define bM4_CMP2_CTRL_OUTEN (*((volatile unsigned int*)(0x42940230UL))) +#define bM4_CMP2_CTRL_INV (*((volatile unsigned int*)(0x42940234UL))) +#define bM4_CMP2_CTRL_CMPOE (*((volatile unsigned int*)(0x42940238UL))) +#define bM4_CMP2_CTRL_CMPON (*((volatile unsigned int*)(0x4294023CUL))) +#define bM4_CMP2_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940240UL))) +#define bM4_CMP2_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940244UL))) +#define bM4_CMP2_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940248UL))) +#define bM4_CMP2_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294024CUL))) +#define bM4_CMP2_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940260UL))) +#define bM4_CMP2_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940264UL))) +#define bM4_CMP2_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940268UL))) +#define bM4_CMP2_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294026CUL))) +#define bM4_CMP2_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940270UL))) +#define bM4_CMP2_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940274UL))) +#define bM4_CMP2_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940278UL))) +#define bM4_CMP2_MON_OMON (*((volatile unsigned int*)(0x42940280UL))) +#define bM4_CMP2_MON_CVST0 (*((volatile unsigned int*)(0x429402A0UL))) +#define bM4_CMP2_MON_CVST1 (*((volatile unsigned int*)(0x429402A4UL))) +#define bM4_CMP2_MON_CVST2 (*((volatile unsigned int*)(0x429402A8UL))) +#define bM4_CMP2_MON_CVST3 (*((volatile unsigned int*)(0x429402ACUL))) +#define bM4_CMP2_CVSSTB_STB0 (*((volatile unsigned int*)(0x429402C0UL))) +#define bM4_CMP2_CVSSTB_STB1 (*((volatile unsigned int*)(0x429402C4UL))) +#define bM4_CMP2_CVSSTB_STB2 (*((volatile unsigned int*)(0x429402C8UL))) +#define bM4_CMP2_CVSSTB_STB3 (*((volatile unsigned int*)(0x429402CCUL))) +#define bM4_CMP2_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940300UL))) +#define bM4_CMP2_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940304UL))) +#define bM4_CMP2_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940308UL))) +#define bM4_CMP2_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294030CUL))) +#define bM4_CMP2_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940310UL))) +#define bM4_CMP2_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940314UL))) +#define bM4_CMP2_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940318UL))) +#define bM4_CMP2_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294031CUL))) +#define bM4_CMP3_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940400UL))) +#define bM4_CMP3_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940404UL))) +#define bM4_CMP3_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940408UL))) +#define bM4_CMP3_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940414UL))) +#define bM4_CMP3_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940418UL))) +#define bM4_CMP3_CTRL_IEN (*((volatile unsigned int*)(0x4294041CUL))) +#define bM4_CMP3_CTRL_CVSEN (*((volatile unsigned int*)(0x42940420UL))) +#define bM4_CMP3_CTRL_OUTEN (*((volatile unsigned int*)(0x42940430UL))) +#define bM4_CMP3_CTRL_INV (*((volatile unsigned int*)(0x42940434UL))) +#define bM4_CMP3_CTRL_CMPOE (*((volatile unsigned int*)(0x42940438UL))) +#define bM4_CMP3_CTRL_CMPON (*((volatile unsigned int*)(0x4294043CUL))) +#define bM4_CMP3_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940440UL))) +#define bM4_CMP3_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940444UL))) +#define bM4_CMP3_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940448UL))) +#define bM4_CMP3_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294044CUL))) +#define bM4_CMP3_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940460UL))) +#define bM4_CMP3_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940464UL))) +#define bM4_CMP3_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940468UL))) +#define bM4_CMP3_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294046CUL))) +#define bM4_CMP3_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940470UL))) +#define bM4_CMP3_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940474UL))) +#define bM4_CMP3_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940478UL))) +#define bM4_CMP3_MON_OMON (*((volatile unsigned int*)(0x42940480UL))) +#define bM4_CMP3_MON_CVST0 (*((volatile unsigned int*)(0x429404A0UL))) +#define bM4_CMP3_MON_CVST1 (*((volatile unsigned int*)(0x429404A4UL))) +#define bM4_CMP3_MON_CVST2 (*((volatile unsigned int*)(0x429404A8UL))) +#define bM4_CMP3_MON_CVST3 (*((volatile unsigned int*)(0x429404ACUL))) +#define bM4_CMP3_CVSSTB_STB0 (*((volatile unsigned int*)(0x429404C0UL))) +#define bM4_CMP3_CVSSTB_STB1 (*((volatile unsigned int*)(0x429404C4UL))) +#define bM4_CMP3_CVSSTB_STB2 (*((volatile unsigned int*)(0x429404C8UL))) +#define bM4_CMP3_CVSSTB_STB3 (*((volatile unsigned int*)(0x429404CCUL))) +#define bM4_CMP3_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940500UL))) +#define bM4_CMP3_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940504UL))) +#define bM4_CMP3_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940508UL))) +#define bM4_CMP3_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294050CUL))) +#define bM4_CMP3_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940510UL))) +#define bM4_CMP3_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940514UL))) +#define bM4_CMP3_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940518UL))) +#define bM4_CMP3_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294051CUL))) +#define bM4_CMP_CR_DADR1_DATA0 (*((volatile unsigned int*)(0x42942000UL))) +#define bM4_CMP_CR_DADR1_DATA1 (*((volatile unsigned int*)(0x42942004UL))) +#define bM4_CMP_CR_DADR1_DATA2 (*((volatile unsigned int*)(0x42942008UL))) +#define bM4_CMP_CR_DADR1_DATA3 (*((volatile unsigned int*)(0x4294200CUL))) +#define bM4_CMP_CR_DADR1_DATA4 (*((volatile unsigned int*)(0x42942010UL))) +#define bM4_CMP_CR_DADR1_DATA5 (*((volatile unsigned int*)(0x42942014UL))) +#define bM4_CMP_CR_DADR1_DATA6 (*((volatile unsigned int*)(0x42942018UL))) +#define bM4_CMP_CR_DADR1_DATA7 (*((volatile unsigned int*)(0x4294201CUL))) +#define bM4_CMP_CR_DADR2_DATA0 (*((volatile unsigned int*)(0x42942040UL))) +#define bM4_CMP_CR_DADR2_DATA1 (*((volatile unsigned int*)(0x42942044UL))) +#define bM4_CMP_CR_DADR2_DATA2 (*((volatile unsigned int*)(0x42942048UL))) +#define bM4_CMP_CR_DADR2_DATA3 (*((volatile unsigned int*)(0x4294204CUL))) +#define bM4_CMP_CR_DADR2_DATA4 (*((volatile unsigned int*)(0x42942050UL))) +#define bM4_CMP_CR_DADR2_DATA5 (*((volatile unsigned int*)(0x42942054UL))) +#define bM4_CMP_CR_DADR2_DATA6 (*((volatile unsigned int*)(0x42942058UL))) +#define bM4_CMP_CR_DADR2_DATA7 (*((volatile unsigned int*)(0x4294205CUL))) +#define bM4_CMP_CR_DACR_DA1EN (*((volatile unsigned int*)(0x42942100UL))) +#define bM4_CMP_CR_DACR_DA2EN (*((volatile unsigned int*)(0x42942104UL))) +#define bM4_CMP_CR_RVADC_DA1SW (*((volatile unsigned int*)(0x42942180UL))) +#define bM4_CMP_CR_RVADC_DA2SW (*((volatile unsigned int*)(0x42942184UL))) +#define bM4_CMP_CR_RVADC_VREFSW (*((volatile unsigned int*)(0x42942190UL))) +#define bM4_CMP_CR_RVADC_WPRT0 (*((volatile unsigned int*)(0x429421A0UL))) +#define bM4_CMP_CR_RVADC_WPRT1 (*((volatile unsigned int*)(0x429421A4UL))) +#define bM4_CMP_CR_RVADC_WPRT2 (*((volatile unsigned int*)(0x429421A8UL))) +#define bM4_CMP_CR_RVADC_WPRT3 (*((volatile unsigned int*)(0x429421ACUL))) +#define bM4_CMP_CR_RVADC_WPRT4 (*((volatile unsigned int*)(0x429421B0UL))) +#define bM4_CMP_CR_RVADC_WPRT5 (*((volatile unsigned int*)(0x429421B4UL))) +#define bM4_CMP_CR_RVADC_WPRT6 (*((volatile unsigned int*)(0x429421B8UL))) +#define bM4_CMP_CR_RVADC_WPRT7 (*((volatile unsigned int*)(0x429421BCUL))) +#define bM4_CRC_CR_CRC_SEL (*((volatile unsigned int*)(0x42118004UL))) +#define bM4_CRC_CR_REFIN (*((volatile unsigned int*)(0x42118008UL))) +#define bM4_CRC_CR_REFOUT (*((volatile unsigned int*)(0x4211800CUL))) +#define bM4_CRC_CR_XOROUT (*((volatile unsigned int*)(0x42118010UL))) +#define bM4_CRC_FLG_FLAG (*((volatile unsigned int*)(0x42118180UL))) +#define bM4_DCU1_CTL_MODE0 (*((volatile unsigned int*)(0x42A40000UL))) +#define bM4_DCU1_CTL_MODE1 (*((volatile unsigned int*)(0x42A40004UL))) +#define bM4_DCU1_CTL_MODE2 (*((volatile unsigned int*)(0x42A40008UL))) +#define bM4_DCU1_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4000CUL))) +#define bM4_DCU1_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A40010UL))) +#define bM4_DCU1_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A40020UL))) +#define bM4_DCU1_CTL_INTEN (*((volatile unsigned int*)(0x42A4007CUL))) +#define bM4_DCU1_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A40080UL))) +#define bM4_DCU1_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A40084UL))) +#define bM4_DCU1_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A40088UL))) +#define bM4_DCU1_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4008CUL))) +#define bM4_DCU1_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A40090UL))) +#define bM4_DCU1_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A40094UL))) +#define bM4_DCU1_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A40098UL))) +#define bM4_DCU1_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A40280UL))) +#define bM4_DCU1_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A40284UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A40288UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4028CUL))) +#define bM4_DCU1_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A40290UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A40294UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A40298UL))) +#define bM4_DCU1_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A40300UL))) +#define bM4_DCU1_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A40304UL))) +#define bM4_DCU1_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A40308UL))) +#define bM4_DCU1_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4030CUL))) +#define bM4_DCU1_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A40310UL))) +#define bM4_DCU1_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A40314UL))) +#define bM4_DCU1_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A40318UL))) +#define bM4_DCU1_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4031CUL))) +#define bM4_DCU1_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A40320UL))) +#define bM4_DCU2_CTL_MODE0 (*((volatile unsigned int*)(0x42A48000UL))) +#define bM4_DCU2_CTL_MODE1 (*((volatile unsigned int*)(0x42A48004UL))) +#define bM4_DCU2_CTL_MODE2 (*((volatile unsigned int*)(0x42A48008UL))) +#define bM4_DCU2_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4800CUL))) +#define bM4_DCU2_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A48010UL))) +#define bM4_DCU2_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A48020UL))) +#define bM4_DCU2_CTL_INTEN (*((volatile unsigned int*)(0x42A4807CUL))) +#define bM4_DCU2_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A48080UL))) +#define bM4_DCU2_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A48084UL))) +#define bM4_DCU2_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A48088UL))) +#define bM4_DCU2_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4808CUL))) +#define bM4_DCU2_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A48090UL))) +#define bM4_DCU2_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A48094UL))) +#define bM4_DCU2_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A48098UL))) +#define bM4_DCU2_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A48280UL))) +#define bM4_DCU2_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A48284UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A48288UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4828CUL))) +#define bM4_DCU2_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A48290UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A48294UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A48298UL))) +#define bM4_DCU2_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A48300UL))) +#define bM4_DCU2_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A48304UL))) +#define bM4_DCU2_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A48308UL))) +#define bM4_DCU2_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4830CUL))) +#define bM4_DCU2_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A48310UL))) +#define bM4_DCU2_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A48314UL))) +#define bM4_DCU2_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A48318UL))) +#define bM4_DCU2_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4831CUL))) +#define bM4_DCU2_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A48320UL))) +#define bM4_DCU3_CTL_MODE0 (*((volatile unsigned int*)(0x42A50000UL))) +#define bM4_DCU3_CTL_MODE1 (*((volatile unsigned int*)(0x42A50004UL))) +#define bM4_DCU3_CTL_MODE2 (*((volatile unsigned int*)(0x42A50008UL))) +#define bM4_DCU3_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5000CUL))) +#define bM4_DCU3_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A50010UL))) +#define bM4_DCU3_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A50020UL))) +#define bM4_DCU3_CTL_INTEN (*((volatile unsigned int*)(0x42A5007CUL))) +#define bM4_DCU3_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A50080UL))) +#define bM4_DCU3_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A50084UL))) +#define bM4_DCU3_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A50088UL))) +#define bM4_DCU3_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5008CUL))) +#define bM4_DCU3_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A50090UL))) +#define bM4_DCU3_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A50094UL))) +#define bM4_DCU3_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A50098UL))) +#define bM4_DCU3_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A50280UL))) +#define bM4_DCU3_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A50284UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A50288UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5028CUL))) +#define bM4_DCU3_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A50290UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A50294UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A50298UL))) +#define bM4_DCU3_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A50300UL))) +#define bM4_DCU3_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A50304UL))) +#define bM4_DCU3_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A50308UL))) +#define bM4_DCU3_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5030CUL))) +#define bM4_DCU3_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A50310UL))) +#define bM4_DCU3_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A50314UL))) +#define bM4_DCU3_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A50318UL))) +#define bM4_DCU3_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5031CUL))) +#define bM4_DCU3_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A50320UL))) +#define bM4_DCU4_CTL_MODE0 (*((volatile unsigned int*)(0x42A58000UL))) +#define bM4_DCU4_CTL_MODE1 (*((volatile unsigned int*)(0x42A58004UL))) +#define bM4_DCU4_CTL_MODE2 (*((volatile unsigned int*)(0x42A58008UL))) +#define bM4_DCU4_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5800CUL))) +#define bM4_DCU4_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A58010UL))) +#define bM4_DCU4_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A58020UL))) +#define bM4_DCU4_CTL_INTEN (*((volatile unsigned int*)(0x42A5807CUL))) +#define bM4_DCU4_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A58080UL))) +#define bM4_DCU4_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A58084UL))) +#define bM4_DCU4_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A58088UL))) +#define bM4_DCU4_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5808CUL))) +#define bM4_DCU4_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A58090UL))) +#define bM4_DCU4_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A58094UL))) +#define bM4_DCU4_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A58098UL))) +#define bM4_DCU4_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A58280UL))) +#define bM4_DCU4_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A58284UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A58288UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5828CUL))) +#define bM4_DCU4_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A58290UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A58294UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A58298UL))) +#define bM4_DCU4_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A58300UL))) +#define bM4_DCU4_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A58304UL))) +#define bM4_DCU4_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A58308UL))) +#define bM4_DCU4_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5830CUL))) +#define bM4_DCU4_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A58310UL))) +#define bM4_DCU4_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A58314UL))) +#define bM4_DCU4_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A58318UL))) +#define bM4_DCU4_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5831CUL))) +#define bM4_DCU4_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A58320UL))) +#define bM4_DMA1_EN_EN (*((volatile unsigned int*)(0x42A60000UL))) +#define bM4_DMA1_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A60080UL))) +#define bM4_DMA1_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A60084UL))) +#define bM4_DMA1_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A60088UL))) +#define bM4_DMA1_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6008CUL))) +#define bM4_DMA1_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A600C0UL))) +#define bM4_DMA1_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A600C4UL))) +#define bM4_DMA1_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A600C8UL))) +#define bM4_DMA1_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A600CCUL))) +#define bM4_DMA1_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A60100UL))) +#define bM4_DMA1_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A60104UL))) +#define bM4_DMA1_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A60108UL))) +#define bM4_DMA1_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6010CUL))) +#define bM4_DMA1_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A60140UL))) +#define bM4_DMA1_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A60144UL))) +#define bM4_DMA1_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A60148UL))) +#define bM4_DMA1_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6014CUL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A60180UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A60184UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A60188UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6018CUL))) +#define bM4_DMA1_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A601C0UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A601C4UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A601C8UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A601CCUL))) +#define bM4_DMA1_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A60200UL))) +#define bM4_DMA1_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A60204UL))) +#define bM4_DMA1_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A60208UL))) +#define bM4_DMA1_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6020CUL))) +#define bM4_DMA1_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A60240UL))) +#define bM4_DMA1_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A60244UL))) +#define bM4_DMA1_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A60248UL))) +#define bM4_DMA1_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6024CUL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A60280UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A60284UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A60288UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6028CUL))) +#define bM4_DMA1_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A602C0UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A602C4UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A602C8UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A602CCUL))) +#define bM4_DMA1_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A60300UL))) +#define bM4_DMA1_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A60304UL))) +#define bM4_DMA1_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A60308UL))) +#define bM4_DMA1_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6030CUL))) +#define bM4_DMA1_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A60340UL))) +#define bM4_DMA1_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A60344UL))) +#define bM4_DMA1_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A60348UL))) +#define bM4_DMA1_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6034CUL))) +#define bM4_DMA1_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A60380UL))) +#define bM4_DMA1_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A60384UL))) +#define bM4_DMA1_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A60388UL))) +#define bM4_DMA1_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6038CUL))) +#define bM4_DMA1_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A60480UL))) +#define bM4_DMA1_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A60484UL))) +#define bM4_DMA1_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A604C0UL))) +#define bM4_DMA1_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A604C4UL))) +#define bM4_DMA1_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A604C8UL))) +#define bM4_DMA1_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A604CCUL))) +#define bM4_DMA1_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A60580UL))) +#define bM4_DMA1_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A60584UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A605A0UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A605A4UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A605A8UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A605ACUL))) +#define bM4_DMA1_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A605C0UL))) +#define bM4_DMA1_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A605C4UL))) +#define bM4_DMA1_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A605C8UL))) +#define bM4_DMA1_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A605CCUL))) +#define bM4_DMA1_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A605D0UL))) +#define bM4_DMA1_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A605D4UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60900UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60904UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60908UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6090CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60910UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60914UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60918UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6091CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60920UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60924UL))) +#define bM4_DMA1_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60940UL))) +#define bM4_DMA1_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60944UL))) +#define bM4_DMA1_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60948UL))) +#define bM4_DMA1_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6094CUL))) +#define bM4_DMA1_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60950UL))) +#define bM4_DMA1_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60954UL))) +#define bM4_DMA1_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60958UL))) +#define bM4_DMA1_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6095CUL))) +#define bM4_DMA1_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60960UL))) +#define bM4_DMA1_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60964UL))) +#define bM4_DMA1_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60968UL))) +#define bM4_DMA1_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6096CUL))) +#define bM4_DMA1_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60970UL))) +#define bM4_DMA1_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60974UL))) +#define bM4_DMA1_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60978UL))) +#define bM4_DMA1_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6097CUL))) +#define bM4_DMA1_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_LLP0_LLP0 (*((volatile unsigned int*)(0x42A60B08UL))) +#define bM4_DMA1_LLP0_LLP1 (*((volatile unsigned int*)(0x42A60B0CUL))) +#define bM4_DMA1_LLP0_LLP2 (*((volatile unsigned int*)(0x42A60B10UL))) +#define bM4_DMA1_LLP0_LLP3 (*((volatile unsigned int*)(0x42A60B14UL))) +#define bM4_DMA1_LLP0_LLP4 (*((volatile unsigned int*)(0x42A60B18UL))) +#define bM4_DMA1_LLP0_LLP5 (*((volatile unsigned int*)(0x42A60B1CUL))) +#define bM4_DMA1_LLP0_LLP6 (*((volatile unsigned int*)(0x42A60B20UL))) +#define bM4_DMA1_LLP0_LLP7 (*((volatile unsigned int*)(0x42A60B24UL))) +#define bM4_DMA1_LLP0_LLP8 (*((volatile unsigned int*)(0x42A60B28UL))) +#define bM4_DMA1_LLP0_LLP9 (*((volatile unsigned int*)(0x42A60B2CUL))) +#define bM4_DMA1_LLP0_LLP10 (*((volatile unsigned int*)(0x42A60B30UL))) +#define bM4_DMA1_LLP0_LLP11 (*((volatile unsigned int*)(0x42A60B34UL))) +#define bM4_DMA1_LLP0_LLP12 (*((volatile unsigned int*)(0x42A60B38UL))) +#define bM4_DMA1_LLP0_LLP13 (*((volatile unsigned int*)(0x42A60B3CUL))) +#define bM4_DMA1_LLP0_LLP14 (*((volatile unsigned int*)(0x42A60B40UL))) +#define bM4_DMA1_LLP0_LLP15 (*((volatile unsigned int*)(0x42A60B44UL))) +#define bM4_DMA1_LLP0_LLP16 (*((volatile unsigned int*)(0x42A60B48UL))) +#define bM4_DMA1_LLP0_LLP17 (*((volatile unsigned int*)(0x42A60B4CUL))) +#define bM4_DMA1_LLP0_LLP18 (*((volatile unsigned int*)(0x42A60B50UL))) +#define bM4_DMA1_LLP0_LLP19 (*((volatile unsigned int*)(0x42A60B54UL))) +#define bM4_DMA1_LLP0_LLP20 (*((volatile unsigned int*)(0x42A60B58UL))) +#define bM4_DMA1_LLP0_LLP21 (*((volatile unsigned int*)(0x42A60B5CUL))) +#define bM4_DMA1_LLP0_LLP22 (*((volatile unsigned int*)(0x42A60B60UL))) +#define bM4_DMA1_LLP0_LLP23 (*((volatile unsigned int*)(0x42A60B64UL))) +#define bM4_DMA1_LLP0_LLP24 (*((volatile unsigned int*)(0x42A60B68UL))) +#define bM4_DMA1_LLP0_LLP25 (*((volatile unsigned int*)(0x42A60B6CUL))) +#define bM4_DMA1_LLP0_LLP26 (*((volatile unsigned int*)(0x42A60B70UL))) +#define bM4_DMA1_LLP0_LLP27 (*((volatile unsigned int*)(0x42A60B74UL))) +#define bM4_DMA1_LLP0_LLP28 (*((volatile unsigned int*)(0x42A60B78UL))) +#define bM4_DMA1_LLP0_LLP29 (*((volatile unsigned int*)(0x42A60B7CUL))) +#define bM4_DMA1_CH0CTL_SINC0 (*((volatile unsigned int*)(0x42A60B80UL))) +#define bM4_DMA1_CH0CTL_SINC1 (*((volatile unsigned int*)(0x42A60B84UL))) +#define bM4_DMA1_CH0CTL_DINC0 (*((volatile unsigned int*)(0x42A60B88UL))) +#define bM4_DMA1_CH0CTL_DINC1 (*((volatile unsigned int*)(0x42A60B8CUL))) +#define bM4_DMA1_CH0CTL_SRPTEN (*((volatile unsigned int*)(0x42A60B90UL))) +#define bM4_DMA1_CH0CTL_DRPTEN (*((volatile unsigned int*)(0x42A60B94UL))) +#define bM4_DMA1_CH0CTL_SNSEQEN (*((volatile unsigned int*)(0x42A60B98UL))) +#define bM4_DMA1_CH0CTL_DNSEQEN (*((volatile unsigned int*)(0x42A60B9CUL))) +#define bM4_DMA1_CH0CTL_HSIZE0 (*((volatile unsigned int*)(0x42A60BA0UL))) +#define bM4_DMA1_CH0CTL_HSIZE1 (*((volatile unsigned int*)(0x42A60BA4UL))) +#define bM4_DMA1_CH0CTL_LLPEN (*((volatile unsigned int*)(0x42A60BA8UL))) +#define bM4_DMA1_CH0CTL_LLPRUN (*((volatile unsigned int*)(0x42A60BACUL))) +#define bM4_DMA1_CH0CTL_IE (*((volatile unsigned int*)(0x42A60BB0UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60D00UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60D04UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60D08UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A60D0CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60D10UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60D14UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60D18UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A60D1CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60D20UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60D24UL))) +#define bM4_DMA1_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60D40UL))) +#define bM4_DMA1_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60D44UL))) +#define bM4_DMA1_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60D48UL))) +#define bM4_DMA1_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A60D4CUL))) +#define bM4_DMA1_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60D50UL))) +#define bM4_DMA1_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60D54UL))) +#define bM4_DMA1_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60D58UL))) +#define bM4_DMA1_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A60D5CUL))) +#define bM4_DMA1_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60D60UL))) +#define bM4_DMA1_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60D64UL))) +#define bM4_DMA1_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60D68UL))) +#define bM4_DMA1_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A60D6CUL))) +#define bM4_DMA1_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60D70UL))) +#define bM4_DMA1_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60D74UL))) +#define bM4_DMA1_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60D78UL))) +#define bM4_DMA1_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A60D7CUL))) +#define bM4_DMA1_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A60D80UL))) +#define bM4_DMA1_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A60D84UL))) +#define bM4_DMA1_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A60D88UL))) +#define bM4_DMA1_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A60D8CUL))) +#define bM4_DMA1_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A60D90UL))) +#define bM4_DMA1_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A60D94UL))) +#define bM4_DMA1_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A60D98UL))) +#define bM4_DMA1_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A60D9CUL))) +#define bM4_DMA1_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A60DA0UL))) +#define bM4_DMA1_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A60DA4UL))) +#define bM4_DMA1_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A60DC0UL))) +#define bM4_DMA1_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A60DC4UL))) +#define bM4_DMA1_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A60DC8UL))) +#define bM4_DMA1_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A60DCCUL))) +#define bM4_DMA1_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A60DD0UL))) +#define bM4_DMA1_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A60DD4UL))) +#define bM4_DMA1_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A60DD8UL))) +#define bM4_DMA1_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A60DDCUL))) +#define bM4_DMA1_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A60DE0UL))) +#define bM4_DMA1_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A60DE4UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60E00UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60E04UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60E08UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60E0CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60E10UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60E14UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60E18UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60E1CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60E20UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60E24UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60E28UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60E2CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60E30UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60E34UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60E38UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60E3CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60E40UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60E44UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60E48UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60E4CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60E50UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60E54UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60E58UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60E5CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60E60UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60E64UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60E68UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60E6CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60E70UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60E74UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60E78UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60E7CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60E80UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60E84UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60E88UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60E8CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60E90UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60E94UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60E98UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60E9CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60EA0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60EA4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60EA8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60EACUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60EB0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60EB4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60EB8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60EBCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60EC0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60EC4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60EC8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ECCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60ED0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60ED4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60ED8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60EDCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60EE0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60EE4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60EE8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60EECUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60EF0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60EF4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60EF8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60EFCUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61100UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61104UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61108UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6110CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61110UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61114UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61118UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6111CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61120UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61124UL))) +#define bM4_DMA1_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61140UL))) +#define bM4_DMA1_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61144UL))) +#define bM4_DMA1_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61148UL))) +#define bM4_DMA1_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6114CUL))) +#define bM4_DMA1_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61150UL))) +#define bM4_DMA1_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61154UL))) +#define bM4_DMA1_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61158UL))) +#define bM4_DMA1_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6115CUL))) +#define bM4_DMA1_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61160UL))) +#define bM4_DMA1_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61164UL))) +#define bM4_DMA1_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61168UL))) +#define bM4_DMA1_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6116CUL))) +#define bM4_DMA1_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61170UL))) +#define bM4_DMA1_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61174UL))) +#define bM4_DMA1_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61178UL))) +#define bM4_DMA1_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6117CUL))) +#define bM4_DMA1_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_LLP1_LLP0 (*((volatile unsigned int*)(0x42A61308UL))) +#define bM4_DMA1_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6130CUL))) +#define bM4_DMA1_LLP1_LLP2 (*((volatile unsigned int*)(0x42A61310UL))) +#define bM4_DMA1_LLP1_LLP3 (*((volatile unsigned int*)(0x42A61314UL))) +#define bM4_DMA1_LLP1_LLP4 (*((volatile unsigned int*)(0x42A61318UL))) +#define bM4_DMA1_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6131CUL))) +#define bM4_DMA1_LLP1_LLP6 (*((volatile unsigned int*)(0x42A61320UL))) +#define bM4_DMA1_LLP1_LLP7 (*((volatile unsigned int*)(0x42A61324UL))) +#define bM4_DMA1_LLP1_LLP8 (*((volatile unsigned int*)(0x42A61328UL))) +#define bM4_DMA1_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6132CUL))) +#define bM4_DMA1_LLP1_LLP10 (*((volatile unsigned int*)(0x42A61330UL))) +#define bM4_DMA1_LLP1_LLP11 (*((volatile unsigned int*)(0x42A61334UL))) +#define bM4_DMA1_LLP1_LLP12 (*((volatile unsigned int*)(0x42A61338UL))) +#define bM4_DMA1_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6133CUL))) +#define bM4_DMA1_LLP1_LLP14 (*((volatile unsigned int*)(0x42A61340UL))) +#define bM4_DMA1_LLP1_LLP15 (*((volatile unsigned int*)(0x42A61344UL))) +#define bM4_DMA1_LLP1_LLP16 (*((volatile unsigned int*)(0x42A61348UL))) +#define bM4_DMA1_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6134CUL))) +#define bM4_DMA1_LLP1_LLP18 (*((volatile unsigned int*)(0x42A61350UL))) +#define bM4_DMA1_LLP1_LLP19 (*((volatile unsigned int*)(0x42A61354UL))) +#define bM4_DMA1_LLP1_LLP20 (*((volatile unsigned int*)(0x42A61358UL))) +#define bM4_DMA1_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6135CUL))) +#define bM4_DMA1_LLP1_LLP22 (*((volatile unsigned int*)(0x42A61360UL))) +#define bM4_DMA1_LLP1_LLP23 (*((volatile unsigned int*)(0x42A61364UL))) +#define bM4_DMA1_LLP1_LLP24 (*((volatile unsigned int*)(0x42A61368UL))) +#define bM4_DMA1_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6136CUL))) +#define bM4_DMA1_LLP1_LLP26 (*((volatile unsigned int*)(0x42A61370UL))) +#define bM4_DMA1_LLP1_LLP27 (*((volatile unsigned int*)(0x42A61374UL))) +#define bM4_DMA1_LLP1_LLP28 (*((volatile unsigned int*)(0x42A61378UL))) +#define bM4_DMA1_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6137CUL))) +#define bM4_DMA1_CH1CTL_SINC0 (*((volatile unsigned int*)(0x42A61380UL))) +#define bM4_DMA1_CH1CTL_SINC1 (*((volatile unsigned int*)(0x42A61384UL))) +#define bM4_DMA1_CH1CTL_DINC0 (*((volatile unsigned int*)(0x42A61388UL))) +#define bM4_DMA1_CH1CTL_DINC1 (*((volatile unsigned int*)(0x42A6138CUL))) +#define bM4_DMA1_CH1CTL_SRPTEN (*((volatile unsigned int*)(0x42A61390UL))) +#define bM4_DMA1_CH1CTL_DRPTEN (*((volatile unsigned int*)(0x42A61394UL))) +#define bM4_DMA1_CH1CTL_SNSEQEN (*((volatile unsigned int*)(0x42A61398UL))) +#define bM4_DMA1_CH1CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6139CUL))) +#define bM4_DMA1_CH1CTL_HSIZE0 (*((volatile unsigned int*)(0x42A613A0UL))) +#define bM4_DMA1_CH1CTL_HSIZE1 (*((volatile unsigned int*)(0x42A613A4UL))) +#define bM4_DMA1_CH1CTL_LLPEN (*((volatile unsigned int*)(0x42A613A8UL))) +#define bM4_DMA1_CH1CTL_LLPRUN (*((volatile unsigned int*)(0x42A613ACUL))) +#define bM4_DMA1_CH1CTL_IE (*((volatile unsigned int*)(0x42A613B0UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61500UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61504UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61508UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6150CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61510UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61514UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61518UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6151CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61520UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61524UL))) +#define bM4_DMA1_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61540UL))) +#define bM4_DMA1_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61544UL))) +#define bM4_DMA1_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61548UL))) +#define bM4_DMA1_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6154CUL))) +#define bM4_DMA1_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61550UL))) +#define bM4_DMA1_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61554UL))) +#define bM4_DMA1_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61558UL))) +#define bM4_DMA1_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6155CUL))) +#define bM4_DMA1_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61560UL))) +#define bM4_DMA1_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61564UL))) +#define bM4_DMA1_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61568UL))) +#define bM4_DMA1_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6156CUL))) +#define bM4_DMA1_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61570UL))) +#define bM4_DMA1_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61574UL))) +#define bM4_DMA1_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61578UL))) +#define bM4_DMA1_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6157CUL))) +#define bM4_DMA1_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A61580UL))) +#define bM4_DMA1_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A61584UL))) +#define bM4_DMA1_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A61588UL))) +#define bM4_DMA1_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6158CUL))) +#define bM4_DMA1_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A61590UL))) +#define bM4_DMA1_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A61594UL))) +#define bM4_DMA1_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A61598UL))) +#define bM4_DMA1_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6159CUL))) +#define bM4_DMA1_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A615A0UL))) +#define bM4_DMA1_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A615A4UL))) +#define bM4_DMA1_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A615C0UL))) +#define bM4_DMA1_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A615C4UL))) +#define bM4_DMA1_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A615C8UL))) +#define bM4_DMA1_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A615CCUL))) +#define bM4_DMA1_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A615D0UL))) +#define bM4_DMA1_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A615D4UL))) +#define bM4_DMA1_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A615D8UL))) +#define bM4_DMA1_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A615DCUL))) +#define bM4_DMA1_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A615E0UL))) +#define bM4_DMA1_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A615E4UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61600UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61604UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61608UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6160CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61610UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61614UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61618UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6161CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61620UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61624UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61628UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6162CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61630UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61634UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61638UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6163CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61640UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61644UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61648UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6164CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61650UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61654UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61658UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6165CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61660UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61664UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61668UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6166CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61670UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61674UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61678UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6167CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61680UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61684UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61688UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6168CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61690UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61694UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61698UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6169CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A616A0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A616A4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A616A8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A616ACUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A616B0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A616B4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A616B8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A616BCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A616C0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A616C4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A616C8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A616CCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A616D0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A616D4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A616D8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A616DCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A616E0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A616E4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A616E8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A616ECUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A616F0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A616F4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A616F8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A616FCUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61900UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61904UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61908UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6190CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61910UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61914UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61918UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6191CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61920UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61924UL))) +#define bM4_DMA1_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61940UL))) +#define bM4_DMA1_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61944UL))) +#define bM4_DMA1_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61948UL))) +#define bM4_DMA1_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6194CUL))) +#define bM4_DMA1_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61950UL))) +#define bM4_DMA1_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61954UL))) +#define bM4_DMA1_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61958UL))) +#define bM4_DMA1_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6195CUL))) +#define bM4_DMA1_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61960UL))) +#define bM4_DMA1_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61964UL))) +#define bM4_DMA1_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61968UL))) +#define bM4_DMA1_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6196CUL))) +#define bM4_DMA1_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61970UL))) +#define bM4_DMA1_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61974UL))) +#define bM4_DMA1_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61978UL))) +#define bM4_DMA1_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6197CUL))) +#define bM4_DMA1_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_LLP2_LLP0 (*((volatile unsigned int*)(0x42A61B08UL))) +#define bM4_DMA1_LLP2_LLP1 (*((volatile unsigned int*)(0x42A61B0CUL))) +#define bM4_DMA1_LLP2_LLP2 (*((volatile unsigned int*)(0x42A61B10UL))) +#define bM4_DMA1_LLP2_LLP3 (*((volatile unsigned int*)(0x42A61B14UL))) +#define bM4_DMA1_LLP2_LLP4 (*((volatile unsigned int*)(0x42A61B18UL))) +#define bM4_DMA1_LLP2_LLP5 (*((volatile unsigned int*)(0x42A61B1CUL))) +#define bM4_DMA1_LLP2_LLP6 (*((volatile unsigned int*)(0x42A61B20UL))) +#define bM4_DMA1_LLP2_LLP7 (*((volatile unsigned int*)(0x42A61B24UL))) +#define bM4_DMA1_LLP2_LLP8 (*((volatile unsigned int*)(0x42A61B28UL))) +#define bM4_DMA1_LLP2_LLP9 (*((volatile unsigned int*)(0x42A61B2CUL))) +#define bM4_DMA1_LLP2_LLP10 (*((volatile unsigned int*)(0x42A61B30UL))) +#define bM4_DMA1_LLP2_LLP11 (*((volatile unsigned int*)(0x42A61B34UL))) +#define bM4_DMA1_LLP2_LLP12 (*((volatile unsigned int*)(0x42A61B38UL))) +#define bM4_DMA1_LLP2_LLP13 (*((volatile unsigned int*)(0x42A61B3CUL))) +#define bM4_DMA1_LLP2_LLP14 (*((volatile unsigned int*)(0x42A61B40UL))) +#define bM4_DMA1_LLP2_LLP15 (*((volatile unsigned int*)(0x42A61B44UL))) +#define bM4_DMA1_LLP2_LLP16 (*((volatile unsigned int*)(0x42A61B48UL))) +#define bM4_DMA1_LLP2_LLP17 (*((volatile unsigned int*)(0x42A61B4CUL))) +#define bM4_DMA1_LLP2_LLP18 (*((volatile unsigned int*)(0x42A61B50UL))) +#define bM4_DMA1_LLP2_LLP19 (*((volatile unsigned int*)(0x42A61B54UL))) +#define bM4_DMA1_LLP2_LLP20 (*((volatile unsigned int*)(0x42A61B58UL))) +#define bM4_DMA1_LLP2_LLP21 (*((volatile unsigned int*)(0x42A61B5CUL))) +#define bM4_DMA1_LLP2_LLP22 (*((volatile unsigned int*)(0x42A61B60UL))) +#define bM4_DMA1_LLP2_LLP23 (*((volatile unsigned int*)(0x42A61B64UL))) +#define bM4_DMA1_LLP2_LLP24 (*((volatile unsigned int*)(0x42A61B68UL))) +#define bM4_DMA1_LLP2_LLP25 (*((volatile unsigned int*)(0x42A61B6CUL))) +#define bM4_DMA1_LLP2_LLP26 (*((volatile unsigned int*)(0x42A61B70UL))) +#define bM4_DMA1_LLP2_LLP27 (*((volatile unsigned int*)(0x42A61B74UL))) +#define bM4_DMA1_LLP2_LLP28 (*((volatile unsigned int*)(0x42A61B78UL))) +#define bM4_DMA1_LLP2_LLP29 (*((volatile unsigned int*)(0x42A61B7CUL))) +#define bM4_DMA1_CH2CTL_SINC0 (*((volatile unsigned int*)(0x42A61B80UL))) +#define bM4_DMA1_CH2CTL_SINC1 (*((volatile unsigned int*)(0x42A61B84UL))) +#define bM4_DMA1_CH2CTL_DINC0 (*((volatile unsigned int*)(0x42A61B88UL))) +#define bM4_DMA1_CH2CTL_DINC1 (*((volatile unsigned int*)(0x42A61B8CUL))) +#define bM4_DMA1_CH2CTL_SRPTEN (*((volatile unsigned int*)(0x42A61B90UL))) +#define bM4_DMA1_CH2CTL_DRPTEN (*((volatile unsigned int*)(0x42A61B94UL))) +#define bM4_DMA1_CH2CTL_SNSEQEN (*((volatile unsigned int*)(0x42A61B98UL))) +#define bM4_DMA1_CH2CTL_DNSEQEN (*((volatile unsigned int*)(0x42A61B9CUL))) +#define bM4_DMA1_CH2CTL_HSIZE0 (*((volatile unsigned int*)(0x42A61BA0UL))) +#define bM4_DMA1_CH2CTL_HSIZE1 (*((volatile unsigned int*)(0x42A61BA4UL))) +#define bM4_DMA1_CH2CTL_LLPEN (*((volatile unsigned int*)(0x42A61BA8UL))) +#define bM4_DMA1_CH2CTL_LLPRUN (*((volatile unsigned int*)(0x42A61BACUL))) +#define bM4_DMA1_CH2CTL_IE (*((volatile unsigned int*)(0x42A61BB0UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61D00UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61D04UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61D08UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A61D0CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61D10UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61D14UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61D18UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A61D1CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61D20UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61D24UL))) +#define bM4_DMA1_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61D40UL))) +#define bM4_DMA1_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61D44UL))) +#define bM4_DMA1_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61D48UL))) +#define bM4_DMA1_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A61D4CUL))) +#define bM4_DMA1_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61D50UL))) +#define bM4_DMA1_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61D54UL))) +#define bM4_DMA1_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61D58UL))) +#define bM4_DMA1_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A61D5CUL))) +#define bM4_DMA1_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61D60UL))) +#define bM4_DMA1_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61D64UL))) +#define bM4_DMA1_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61D68UL))) +#define bM4_DMA1_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A61D6CUL))) +#define bM4_DMA1_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61D70UL))) +#define bM4_DMA1_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61D74UL))) +#define bM4_DMA1_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61D78UL))) +#define bM4_DMA1_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A61D7CUL))) +#define bM4_DMA1_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A61D80UL))) +#define bM4_DMA1_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A61D84UL))) +#define bM4_DMA1_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A61D88UL))) +#define bM4_DMA1_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A61D8CUL))) +#define bM4_DMA1_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A61D90UL))) +#define bM4_DMA1_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A61D94UL))) +#define bM4_DMA1_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A61D98UL))) +#define bM4_DMA1_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A61D9CUL))) +#define bM4_DMA1_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A61DA0UL))) +#define bM4_DMA1_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A61DA4UL))) +#define bM4_DMA1_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A61DC0UL))) +#define bM4_DMA1_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A61DC4UL))) +#define bM4_DMA1_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A61DC8UL))) +#define bM4_DMA1_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A61DCCUL))) +#define bM4_DMA1_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A61DD0UL))) +#define bM4_DMA1_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A61DD4UL))) +#define bM4_DMA1_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A61DD8UL))) +#define bM4_DMA1_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A61DDCUL))) +#define bM4_DMA1_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A61DE0UL))) +#define bM4_DMA1_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A61DE4UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61E00UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61E04UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61E08UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61E0CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61E10UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61E14UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61E18UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61E1CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61E20UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61E24UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61E28UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61E2CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61E30UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61E34UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61E38UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61E3CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61E40UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61E44UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61E48UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61E4CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61E50UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61E54UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61E58UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61E5CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61E60UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61E64UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61E68UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61E6CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61E70UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61E74UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61E78UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61E7CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61E80UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61E84UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61E88UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61E8CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61E90UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61E94UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61E98UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61E9CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61EA0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61EA4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61EA8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61EACUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61EB0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61EB4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61EB8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61EBCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61EC0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61EC4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61EC8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ECCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61ED0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61ED4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61ED8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61EDCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61EE0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61EE4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61EE8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61EECUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61EF0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61EF4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61EF8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61EFCUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62100UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62104UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62108UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6210CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62110UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62114UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62118UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6211CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62120UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62124UL))) +#define bM4_DMA1_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62140UL))) +#define bM4_DMA1_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62144UL))) +#define bM4_DMA1_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62148UL))) +#define bM4_DMA1_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6214CUL))) +#define bM4_DMA1_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62150UL))) +#define bM4_DMA1_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62154UL))) +#define bM4_DMA1_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62158UL))) +#define bM4_DMA1_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6215CUL))) +#define bM4_DMA1_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62160UL))) +#define bM4_DMA1_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62164UL))) +#define bM4_DMA1_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62168UL))) +#define bM4_DMA1_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6216CUL))) +#define bM4_DMA1_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62170UL))) +#define bM4_DMA1_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62174UL))) +#define bM4_DMA1_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62178UL))) +#define bM4_DMA1_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6217CUL))) +#define bM4_DMA1_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_LLP3_LLP0 (*((volatile unsigned int*)(0x42A62308UL))) +#define bM4_DMA1_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6230CUL))) +#define bM4_DMA1_LLP3_LLP2 (*((volatile unsigned int*)(0x42A62310UL))) +#define bM4_DMA1_LLP3_LLP3 (*((volatile unsigned int*)(0x42A62314UL))) +#define bM4_DMA1_LLP3_LLP4 (*((volatile unsigned int*)(0x42A62318UL))) +#define bM4_DMA1_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6231CUL))) +#define bM4_DMA1_LLP3_LLP6 (*((volatile unsigned int*)(0x42A62320UL))) +#define bM4_DMA1_LLP3_LLP7 (*((volatile unsigned int*)(0x42A62324UL))) +#define bM4_DMA1_LLP3_LLP8 (*((volatile unsigned int*)(0x42A62328UL))) +#define bM4_DMA1_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6232CUL))) +#define bM4_DMA1_LLP3_LLP10 (*((volatile unsigned int*)(0x42A62330UL))) +#define bM4_DMA1_LLP3_LLP11 (*((volatile unsigned int*)(0x42A62334UL))) +#define bM4_DMA1_LLP3_LLP12 (*((volatile unsigned int*)(0x42A62338UL))) +#define bM4_DMA1_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6233CUL))) +#define bM4_DMA1_LLP3_LLP14 (*((volatile unsigned int*)(0x42A62340UL))) +#define bM4_DMA1_LLP3_LLP15 (*((volatile unsigned int*)(0x42A62344UL))) +#define bM4_DMA1_LLP3_LLP16 (*((volatile unsigned int*)(0x42A62348UL))) +#define bM4_DMA1_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6234CUL))) +#define bM4_DMA1_LLP3_LLP18 (*((volatile unsigned int*)(0x42A62350UL))) +#define bM4_DMA1_LLP3_LLP19 (*((volatile unsigned int*)(0x42A62354UL))) +#define bM4_DMA1_LLP3_LLP20 (*((volatile unsigned int*)(0x42A62358UL))) +#define bM4_DMA1_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6235CUL))) +#define bM4_DMA1_LLP3_LLP22 (*((volatile unsigned int*)(0x42A62360UL))) +#define bM4_DMA1_LLP3_LLP23 (*((volatile unsigned int*)(0x42A62364UL))) +#define bM4_DMA1_LLP3_LLP24 (*((volatile unsigned int*)(0x42A62368UL))) +#define bM4_DMA1_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6236CUL))) +#define bM4_DMA1_LLP3_LLP26 (*((volatile unsigned int*)(0x42A62370UL))) +#define bM4_DMA1_LLP3_LLP27 (*((volatile unsigned int*)(0x42A62374UL))) +#define bM4_DMA1_LLP3_LLP28 (*((volatile unsigned int*)(0x42A62378UL))) +#define bM4_DMA1_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6237CUL))) +#define bM4_DMA1_CH3CTL_SINC0 (*((volatile unsigned int*)(0x42A62380UL))) +#define bM4_DMA1_CH3CTL_SINC1 (*((volatile unsigned int*)(0x42A62384UL))) +#define bM4_DMA1_CH3CTL_DINC0 (*((volatile unsigned int*)(0x42A62388UL))) +#define bM4_DMA1_CH3CTL_DINC1 (*((volatile unsigned int*)(0x42A6238CUL))) +#define bM4_DMA1_CH3CTL_SRPTEN (*((volatile unsigned int*)(0x42A62390UL))) +#define bM4_DMA1_CH3CTL_DRPTEN (*((volatile unsigned int*)(0x42A62394UL))) +#define bM4_DMA1_CH3CTL_SNSEQEN (*((volatile unsigned int*)(0x42A62398UL))) +#define bM4_DMA1_CH3CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6239CUL))) +#define bM4_DMA1_CH3CTL_HSIZE0 (*((volatile unsigned int*)(0x42A623A0UL))) +#define bM4_DMA1_CH3CTL_HSIZE1 (*((volatile unsigned int*)(0x42A623A4UL))) +#define bM4_DMA1_CH3CTL_LLPEN (*((volatile unsigned int*)(0x42A623A8UL))) +#define bM4_DMA1_CH3CTL_LLPRUN (*((volatile unsigned int*)(0x42A623ACUL))) +#define bM4_DMA1_CH3CTL_IE (*((volatile unsigned int*)(0x42A623B0UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62500UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62504UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62508UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6250CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62510UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62514UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62518UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6251CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62520UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62524UL))) +#define bM4_DMA1_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62540UL))) +#define bM4_DMA1_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62544UL))) +#define bM4_DMA1_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62548UL))) +#define bM4_DMA1_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6254CUL))) +#define bM4_DMA1_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62550UL))) +#define bM4_DMA1_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62554UL))) +#define bM4_DMA1_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62558UL))) +#define bM4_DMA1_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6255CUL))) +#define bM4_DMA1_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62560UL))) +#define bM4_DMA1_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62564UL))) +#define bM4_DMA1_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62568UL))) +#define bM4_DMA1_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6256CUL))) +#define bM4_DMA1_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62570UL))) +#define bM4_DMA1_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62574UL))) +#define bM4_DMA1_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62578UL))) +#define bM4_DMA1_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6257CUL))) +#define bM4_DMA1_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A62580UL))) +#define bM4_DMA1_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A62584UL))) +#define bM4_DMA1_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A62588UL))) +#define bM4_DMA1_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6258CUL))) +#define bM4_DMA1_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A62590UL))) +#define bM4_DMA1_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A62594UL))) +#define bM4_DMA1_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A62598UL))) +#define bM4_DMA1_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6259CUL))) +#define bM4_DMA1_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A625A0UL))) +#define bM4_DMA1_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A625A4UL))) +#define bM4_DMA1_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A625C0UL))) +#define bM4_DMA1_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A625C4UL))) +#define bM4_DMA1_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A625C8UL))) +#define bM4_DMA1_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A625CCUL))) +#define bM4_DMA1_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A625D0UL))) +#define bM4_DMA1_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A625D4UL))) +#define bM4_DMA1_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A625D8UL))) +#define bM4_DMA1_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A625DCUL))) +#define bM4_DMA1_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A625E0UL))) +#define bM4_DMA1_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A625E4UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62600UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62604UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62608UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6260CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62610UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62614UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62618UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6261CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62620UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62624UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62628UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6262CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62630UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62634UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62638UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6263CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62640UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62644UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62648UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6264CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62650UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62654UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62658UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6265CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62660UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62664UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62668UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6266CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62670UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62674UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62678UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6267CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62680UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62684UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62688UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6268CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62690UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62694UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62698UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6269CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A626A0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A626A4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A626A8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A626ACUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A626B0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A626B4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A626B8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A626BCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A626C0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A626C4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A626C8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A626CCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A626D0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A626D4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A626D8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A626DCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A626E0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A626E4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A626E8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A626ECUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A626F0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A626F4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A626F8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A626FCUL))) +#define bM4_DMA2_EN_EN (*((volatile unsigned int*)(0x42A68000UL))) +#define bM4_DMA2_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A68080UL))) +#define bM4_DMA2_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A68084UL))) +#define bM4_DMA2_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A68088UL))) +#define bM4_DMA2_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6808CUL))) +#define bM4_DMA2_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A680C0UL))) +#define bM4_DMA2_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A680C4UL))) +#define bM4_DMA2_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A680C8UL))) +#define bM4_DMA2_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A680CCUL))) +#define bM4_DMA2_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A68100UL))) +#define bM4_DMA2_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A68104UL))) +#define bM4_DMA2_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A68108UL))) +#define bM4_DMA2_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6810CUL))) +#define bM4_DMA2_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A68140UL))) +#define bM4_DMA2_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A68144UL))) +#define bM4_DMA2_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A68148UL))) +#define bM4_DMA2_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6814CUL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A68180UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A68184UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A68188UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6818CUL))) +#define bM4_DMA2_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A681C0UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A681C4UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A681C8UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A681CCUL))) +#define bM4_DMA2_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A68200UL))) +#define bM4_DMA2_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A68204UL))) +#define bM4_DMA2_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A68208UL))) +#define bM4_DMA2_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6820CUL))) +#define bM4_DMA2_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A68240UL))) +#define bM4_DMA2_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A68244UL))) +#define bM4_DMA2_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A68248UL))) +#define bM4_DMA2_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6824CUL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A68280UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A68284UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A68288UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6828CUL))) +#define bM4_DMA2_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A682C0UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A682C4UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A682C8UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A682CCUL))) +#define bM4_DMA2_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A68300UL))) +#define bM4_DMA2_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A68304UL))) +#define bM4_DMA2_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A68308UL))) +#define bM4_DMA2_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6830CUL))) +#define bM4_DMA2_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A68340UL))) +#define bM4_DMA2_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A68344UL))) +#define bM4_DMA2_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A68348UL))) +#define bM4_DMA2_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6834CUL))) +#define bM4_DMA2_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A68380UL))) +#define bM4_DMA2_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A68384UL))) +#define bM4_DMA2_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A68388UL))) +#define bM4_DMA2_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6838CUL))) +#define bM4_DMA2_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A68480UL))) +#define bM4_DMA2_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A68484UL))) +#define bM4_DMA2_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A684C0UL))) +#define bM4_DMA2_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A684C4UL))) +#define bM4_DMA2_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A684C8UL))) +#define bM4_DMA2_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A684CCUL))) +#define bM4_DMA2_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A68580UL))) +#define bM4_DMA2_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A68584UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A685A0UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A685A4UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A685A8UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A685ACUL))) +#define bM4_DMA2_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A685C0UL))) +#define bM4_DMA2_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A685C4UL))) +#define bM4_DMA2_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A685C8UL))) +#define bM4_DMA2_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A685CCUL))) +#define bM4_DMA2_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A685D0UL))) +#define bM4_DMA2_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A685D4UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68900UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68904UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68908UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6890CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68910UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68914UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68918UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6891CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68920UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68924UL))) +#define bM4_DMA2_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68940UL))) +#define bM4_DMA2_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68944UL))) +#define bM4_DMA2_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68948UL))) +#define bM4_DMA2_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6894CUL))) +#define bM4_DMA2_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68950UL))) +#define bM4_DMA2_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68954UL))) +#define bM4_DMA2_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68958UL))) +#define bM4_DMA2_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6895CUL))) +#define bM4_DMA2_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68960UL))) +#define bM4_DMA2_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68964UL))) +#define bM4_DMA2_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68968UL))) +#define bM4_DMA2_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6896CUL))) +#define bM4_DMA2_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68970UL))) +#define bM4_DMA2_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68974UL))) +#define bM4_DMA2_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68978UL))) +#define bM4_DMA2_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6897CUL))) +#define bM4_DMA2_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_LLP0_LLP0 (*((volatile unsigned int*)(0x42A68B08UL))) +#define bM4_DMA2_LLP0_LLP1 (*((volatile unsigned int*)(0x42A68B0CUL))) +#define bM4_DMA2_LLP0_LLP2 (*((volatile unsigned int*)(0x42A68B10UL))) +#define bM4_DMA2_LLP0_LLP3 (*((volatile unsigned int*)(0x42A68B14UL))) +#define bM4_DMA2_LLP0_LLP4 (*((volatile unsigned int*)(0x42A68B18UL))) +#define bM4_DMA2_LLP0_LLP5 (*((volatile unsigned int*)(0x42A68B1CUL))) +#define bM4_DMA2_LLP0_LLP6 (*((volatile unsigned int*)(0x42A68B20UL))) +#define bM4_DMA2_LLP0_LLP7 (*((volatile unsigned int*)(0x42A68B24UL))) +#define bM4_DMA2_LLP0_LLP8 (*((volatile unsigned int*)(0x42A68B28UL))) +#define bM4_DMA2_LLP0_LLP9 (*((volatile unsigned int*)(0x42A68B2CUL))) +#define bM4_DMA2_LLP0_LLP10 (*((volatile unsigned int*)(0x42A68B30UL))) +#define bM4_DMA2_LLP0_LLP11 (*((volatile unsigned int*)(0x42A68B34UL))) +#define bM4_DMA2_LLP0_LLP12 (*((volatile unsigned int*)(0x42A68B38UL))) +#define bM4_DMA2_LLP0_LLP13 (*((volatile unsigned int*)(0x42A68B3CUL))) +#define bM4_DMA2_LLP0_LLP14 (*((volatile unsigned int*)(0x42A68B40UL))) +#define bM4_DMA2_LLP0_LLP15 (*((volatile unsigned int*)(0x42A68B44UL))) +#define bM4_DMA2_LLP0_LLP16 (*((volatile unsigned int*)(0x42A68B48UL))) +#define bM4_DMA2_LLP0_LLP17 (*((volatile unsigned int*)(0x42A68B4CUL))) +#define bM4_DMA2_LLP0_LLP18 (*((volatile unsigned int*)(0x42A68B50UL))) +#define bM4_DMA2_LLP0_LLP19 (*((volatile unsigned int*)(0x42A68B54UL))) +#define bM4_DMA2_LLP0_LLP20 (*((volatile unsigned int*)(0x42A68B58UL))) +#define bM4_DMA2_LLP0_LLP21 (*((volatile unsigned int*)(0x42A68B5CUL))) +#define bM4_DMA2_LLP0_LLP22 (*((volatile unsigned int*)(0x42A68B60UL))) +#define bM4_DMA2_LLP0_LLP23 (*((volatile unsigned int*)(0x42A68B64UL))) +#define bM4_DMA2_LLP0_LLP24 (*((volatile unsigned int*)(0x42A68B68UL))) +#define bM4_DMA2_LLP0_LLP25 (*((volatile unsigned int*)(0x42A68B6CUL))) +#define bM4_DMA2_LLP0_LLP26 (*((volatile unsigned int*)(0x42A68B70UL))) +#define bM4_DMA2_LLP0_LLP27 (*((volatile unsigned int*)(0x42A68B74UL))) +#define bM4_DMA2_LLP0_LLP28 (*((volatile unsigned int*)(0x42A68B78UL))) +#define bM4_DMA2_LLP0_LLP29 (*((volatile unsigned int*)(0x42A68B7CUL))) +#define bM4_DMA2_CH0CTL_SINC0 (*((volatile unsigned int*)(0x42A68B80UL))) +#define bM4_DMA2_CH0CTL_SINC1 (*((volatile unsigned int*)(0x42A68B84UL))) +#define bM4_DMA2_CH0CTL_DINC0 (*((volatile unsigned int*)(0x42A68B88UL))) +#define bM4_DMA2_CH0CTL_DINC1 (*((volatile unsigned int*)(0x42A68B8CUL))) +#define bM4_DMA2_CH0CTL_SRPTEN (*((volatile unsigned int*)(0x42A68B90UL))) +#define bM4_DMA2_CH0CTL_DRPTEN (*((volatile unsigned int*)(0x42A68B94UL))) +#define bM4_DMA2_CH0CTL_SNSEQEN (*((volatile unsigned int*)(0x42A68B98UL))) +#define bM4_DMA2_CH0CTL_DNSEQEN (*((volatile unsigned int*)(0x42A68B9CUL))) +#define bM4_DMA2_CH0CTL_HSIZE0 (*((volatile unsigned int*)(0x42A68BA0UL))) +#define bM4_DMA2_CH0CTL_HSIZE1 (*((volatile unsigned int*)(0x42A68BA4UL))) +#define bM4_DMA2_CH0CTL_LLPEN (*((volatile unsigned int*)(0x42A68BA8UL))) +#define bM4_DMA2_CH0CTL_LLPRUN (*((volatile unsigned int*)(0x42A68BACUL))) +#define bM4_DMA2_CH0CTL_IE (*((volatile unsigned int*)(0x42A68BB0UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68D00UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68D04UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68D08UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A68D0CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68D10UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68D14UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68D18UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A68D1CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68D20UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68D24UL))) +#define bM4_DMA2_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68D40UL))) +#define bM4_DMA2_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68D44UL))) +#define bM4_DMA2_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68D48UL))) +#define bM4_DMA2_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A68D4CUL))) +#define bM4_DMA2_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68D50UL))) +#define bM4_DMA2_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68D54UL))) +#define bM4_DMA2_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68D58UL))) +#define bM4_DMA2_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A68D5CUL))) +#define bM4_DMA2_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68D60UL))) +#define bM4_DMA2_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68D64UL))) +#define bM4_DMA2_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68D68UL))) +#define bM4_DMA2_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A68D6CUL))) +#define bM4_DMA2_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68D70UL))) +#define bM4_DMA2_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68D74UL))) +#define bM4_DMA2_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68D78UL))) +#define bM4_DMA2_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A68D7CUL))) +#define bM4_DMA2_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A68D80UL))) +#define bM4_DMA2_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A68D84UL))) +#define bM4_DMA2_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A68D88UL))) +#define bM4_DMA2_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A68D8CUL))) +#define bM4_DMA2_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A68D90UL))) +#define bM4_DMA2_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A68D94UL))) +#define bM4_DMA2_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A68D98UL))) +#define bM4_DMA2_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A68D9CUL))) +#define bM4_DMA2_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A68DA0UL))) +#define bM4_DMA2_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A68DA4UL))) +#define bM4_DMA2_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A68DC0UL))) +#define bM4_DMA2_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A68DC4UL))) +#define bM4_DMA2_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A68DC8UL))) +#define bM4_DMA2_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A68DCCUL))) +#define bM4_DMA2_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A68DD0UL))) +#define bM4_DMA2_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A68DD4UL))) +#define bM4_DMA2_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A68DD8UL))) +#define bM4_DMA2_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A68DDCUL))) +#define bM4_DMA2_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A68DE0UL))) +#define bM4_DMA2_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A68DE4UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68E00UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68E04UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68E08UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68E0CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68E10UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68E14UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68E18UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68E1CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68E20UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68E24UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68E28UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68E2CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68E30UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68E34UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68E38UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68E3CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68E40UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68E44UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68E48UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68E4CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68E50UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68E54UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68E58UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68E5CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68E60UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68E64UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68E68UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68E6CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68E70UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68E74UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68E78UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68E7CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68E80UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68E84UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68E88UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68E8CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68E90UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68E94UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68E98UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68E9CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68EA0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68EA4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68EA8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68EACUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68EB0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68EB4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68EB8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68EBCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68EC0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68EC4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68EC8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ECCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68ED0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68ED4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68ED8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68EDCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68EE0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68EE4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68EE8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68EECUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68EF0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68EF4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68EF8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68EFCUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69100UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69104UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69108UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6910CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69110UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69114UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69118UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6911CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69120UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69124UL))) +#define bM4_DMA2_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69140UL))) +#define bM4_DMA2_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69144UL))) +#define bM4_DMA2_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69148UL))) +#define bM4_DMA2_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6914CUL))) +#define bM4_DMA2_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69150UL))) +#define bM4_DMA2_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69154UL))) +#define bM4_DMA2_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69158UL))) +#define bM4_DMA2_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6915CUL))) +#define bM4_DMA2_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69160UL))) +#define bM4_DMA2_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69164UL))) +#define bM4_DMA2_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69168UL))) +#define bM4_DMA2_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6916CUL))) +#define bM4_DMA2_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69170UL))) +#define bM4_DMA2_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69174UL))) +#define bM4_DMA2_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69178UL))) +#define bM4_DMA2_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6917CUL))) +#define bM4_DMA2_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_LLP1_LLP0 (*((volatile unsigned int*)(0x42A69308UL))) +#define bM4_DMA2_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6930CUL))) +#define bM4_DMA2_LLP1_LLP2 (*((volatile unsigned int*)(0x42A69310UL))) +#define bM4_DMA2_LLP1_LLP3 (*((volatile unsigned int*)(0x42A69314UL))) +#define bM4_DMA2_LLP1_LLP4 (*((volatile unsigned int*)(0x42A69318UL))) +#define bM4_DMA2_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6931CUL))) +#define bM4_DMA2_LLP1_LLP6 (*((volatile unsigned int*)(0x42A69320UL))) +#define bM4_DMA2_LLP1_LLP7 (*((volatile unsigned int*)(0x42A69324UL))) +#define bM4_DMA2_LLP1_LLP8 (*((volatile unsigned int*)(0x42A69328UL))) +#define bM4_DMA2_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6932CUL))) +#define bM4_DMA2_LLP1_LLP10 (*((volatile unsigned int*)(0x42A69330UL))) +#define bM4_DMA2_LLP1_LLP11 (*((volatile unsigned int*)(0x42A69334UL))) +#define bM4_DMA2_LLP1_LLP12 (*((volatile unsigned int*)(0x42A69338UL))) +#define bM4_DMA2_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6933CUL))) +#define bM4_DMA2_LLP1_LLP14 (*((volatile unsigned int*)(0x42A69340UL))) +#define bM4_DMA2_LLP1_LLP15 (*((volatile unsigned int*)(0x42A69344UL))) +#define bM4_DMA2_LLP1_LLP16 (*((volatile unsigned int*)(0x42A69348UL))) +#define bM4_DMA2_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6934CUL))) +#define bM4_DMA2_LLP1_LLP18 (*((volatile unsigned int*)(0x42A69350UL))) +#define bM4_DMA2_LLP1_LLP19 (*((volatile unsigned int*)(0x42A69354UL))) +#define bM4_DMA2_LLP1_LLP20 (*((volatile unsigned int*)(0x42A69358UL))) +#define bM4_DMA2_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6935CUL))) +#define bM4_DMA2_LLP1_LLP22 (*((volatile unsigned int*)(0x42A69360UL))) +#define bM4_DMA2_LLP1_LLP23 (*((volatile unsigned int*)(0x42A69364UL))) +#define bM4_DMA2_LLP1_LLP24 (*((volatile unsigned int*)(0x42A69368UL))) +#define bM4_DMA2_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6936CUL))) +#define bM4_DMA2_LLP1_LLP26 (*((volatile unsigned int*)(0x42A69370UL))) +#define bM4_DMA2_LLP1_LLP27 (*((volatile unsigned int*)(0x42A69374UL))) +#define bM4_DMA2_LLP1_LLP28 (*((volatile unsigned int*)(0x42A69378UL))) +#define bM4_DMA2_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6937CUL))) +#define bM4_DMA2_CH1CTL_SINC0 (*((volatile unsigned int*)(0x42A69380UL))) +#define bM4_DMA2_CH1CTL_SINC1 (*((volatile unsigned int*)(0x42A69384UL))) +#define bM4_DMA2_CH1CTL_DINC0 (*((volatile unsigned int*)(0x42A69388UL))) +#define bM4_DMA2_CH1CTL_DINC1 (*((volatile unsigned int*)(0x42A6938CUL))) +#define bM4_DMA2_CH1CTL_SRPTEN (*((volatile unsigned int*)(0x42A69390UL))) +#define bM4_DMA2_CH1CTL_DRPTEN (*((volatile unsigned int*)(0x42A69394UL))) +#define bM4_DMA2_CH1CTL_SNSEQEN (*((volatile unsigned int*)(0x42A69398UL))) +#define bM4_DMA2_CH1CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6939CUL))) +#define bM4_DMA2_CH1CTL_HSIZE0 (*((volatile unsigned int*)(0x42A693A0UL))) +#define bM4_DMA2_CH1CTL_HSIZE1 (*((volatile unsigned int*)(0x42A693A4UL))) +#define bM4_DMA2_CH1CTL_LLPEN (*((volatile unsigned int*)(0x42A693A8UL))) +#define bM4_DMA2_CH1CTL_LLPRUN (*((volatile unsigned int*)(0x42A693ACUL))) +#define bM4_DMA2_CH1CTL_IE (*((volatile unsigned int*)(0x42A693B0UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69500UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69504UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69508UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6950CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69510UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69514UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69518UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6951CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69520UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69524UL))) +#define bM4_DMA2_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69540UL))) +#define bM4_DMA2_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69544UL))) +#define bM4_DMA2_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69548UL))) +#define bM4_DMA2_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6954CUL))) +#define bM4_DMA2_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69550UL))) +#define bM4_DMA2_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69554UL))) +#define bM4_DMA2_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69558UL))) +#define bM4_DMA2_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6955CUL))) +#define bM4_DMA2_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69560UL))) +#define bM4_DMA2_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69564UL))) +#define bM4_DMA2_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69568UL))) +#define bM4_DMA2_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6956CUL))) +#define bM4_DMA2_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69570UL))) +#define bM4_DMA2_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69574UL))) +#define bM4_DMA2_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69578UL))) +#define bM4_DMA2_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6957CUL))) +#define bM4_DMA2_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A69580UL))) +#define bM4_DMA2_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A69584UL))) +#define bM4_DMA2_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A69588UL))) +#define bM4_DMA2_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6958CUL))) +#define bM4_DMA2_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A69590UL))) +#define bM4_DMA2_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A69594UL))) +#define bM4_DMA2_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A69598UL))) +#define bM4_DMA2_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6959CUL))) +#define bM4_DMA2_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A695A0UL))) +#define bM4_DMA2_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A695A4UL))) +#define bM4_DMA2_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A695C0UL))) +#define bM4_DMA2_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A695C4UL))) +#define bM4_DMA2_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A695C8UL))) +#define bM4_DMA2_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A695CCUL))) +#define bM4_DMA2_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A695D0UL))) +#define bM4_DMA2_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A695D4UL))) +#define bM4_DMA2_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A695D8UL))) +#define bM4_DMA2_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A695DCUL))) +#define bM4_DMA2_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A695E0UL))) +#define bM4_DMA2_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A695E4UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69600UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69604UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69608UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6960CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69610UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69614UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69618UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6961CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69620UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69624UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69628UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6962CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69630UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69634UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69638UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6963CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69640UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69644UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69648UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6964CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69650UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69654UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69658UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6965CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69660UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69664UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69668UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6966CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69670UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69674UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69678UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6967CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69680UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69684UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69688UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6968CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69690UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69694UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69698UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6969CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A696A0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A696A4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A696A8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A696ACUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A696B0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A696B4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A696B8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A696BCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A696C0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A696C4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A696C8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A696CCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A696D0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A696D4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A696D8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A696DCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A696E0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A696E4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A696E8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A696ECUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A696F0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A696F4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A696F8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A696FCUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69900UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69904UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69908UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6990CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69910UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69914UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69918UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6991CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69920UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69924UL))) +#define bM4_DMA2_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69940UL))) +#define bM4_DMA2_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69944UL))) +#define bM4_DMA2_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69948UL))) +#define bM4_DMA2_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6994CUL))) +#define bM4_DMA2_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69950UL))) +#define bM4_DMA2_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69954UL))) +#define bM4_DMA2_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69958UL))) +#define bM4_DMA2_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6995CUL))) +#define bM4_DMA2_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69960UL))) +#define bM4_DMA2_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69964UL))) +#define bM4_DMA2_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69968UL))) +#define bM4_DMA2_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6996CUL))) +#define bM4_DMA2_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69970UL))) +#define bM4_DMA2_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69974UL))) +#define bM4_DMA2_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69978UL))) +#define bM4_DMA2_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6997CUL))) +#define bM4_DMA2_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_LLP2_LLP0 (*((volatile unsigned int*)(0x42A69B08UL))) +#define bM4_DMA2_LLP2_LLP1 (*((volatile unsigned int*)(0x42A69B0CUL))) +#define bM4_DMA2_LLP2_LLP2 (*((volatile unsigned int*)(0x42A69B10UL))) +#define bM4_DMA2_LLP2_LLP3 (*((volatile unsigned int*)(0x42A69B14UL))) +#define bM4_DMA2_LLP2_LLP4 (*((volatile unsigned int*)(0x42A69B18UL))) +#define bM4_DMA2_LLP2_LLP5 (*((volatile unsigned int*)(0x42A69B1CUL))) +#define bM4_DMA2_LLP2_LLP6 (*((volatile unsigned int*)(0x42A69B20UL))) +#define bM4_DMA2_LLP2_LLP7 (*((volatile unsigned int*)(0x42A69B24UL))) +#define bM4_DMA2_LLP2_LLP8 (*((volatile unsigned int*)(0x42A69B28UL))) +#define bM4_DMA2_LLP2_LLP9 (*((volatile unsigned int*)(0x42A69B2CUL))) +#define bM4_DMA2_LLP2_LLP10 (*((volatile unsigned int*)(0x42A69B30UL))) +#define bM4_DMA2_LLP2_LLP11 (*((volatile unsigned int*)(0x42A69B34UL))) +#define bM4_DMA2_LLP2_LLP12 (*((volatile unsigned int*)(0x42A69B38UL))) +#define bM4_DMA2_LLP2_LLP13 (*((volatile unsigned int*)(0x42A69B3CUL))) +#define bM4_DMA2_LLP2_LLP14 (*((volatile unsigned int*)(0x42A69B40UL))) +#define bM4_DMA2_LLP2_LLP15 (*((volatile unsigned int*)(0x42A69B44UL))) +#define bM4_DMA2_LLP2_LLP16 (*((volatile unsigned int*)(0x42A69B48UL))) +#define bM4_DMA2_LLP2_LLP17 (*((volatile unsigned int*)(0x42A69B4CUL))) +#define bM4_DMA2_LLP2_LLP18 (*((volatile unsigned int*)(0x42A69B50UL))) +#define bM4_DMA2_LLP2_LLP19 (*((volatile unsigned int*)(0x42A69B54UL))) +#define bM4_DMA2_LLP2_LLP20 (*((volatile unsigned int*)(0x42A69B58UL))) +#define bM4_DMA2_LLP2_LLP21 (*((volatile unsigned int*)(0x42A69B5CUL))) +#define bM4_DMA2_LLP2_LLP22 (*((volatile unsigned int*)(0x42A69B60UL))) +#define bM4_DMA2_LLP2_LLP23 (*((volatile unsigned int*)(0x42A69B64UL))) +#define bM4_DMA2_LLP2_LLP24 (*((volatile unsigned int*)(0x42A69B68UL))) +#define bM4_DMA2_LLP2_LLP25 (*((volatile unsigned int*)(0x42A69B6CUL))) +#define bM4_DMA2_LLP2_LLP26 (*((volatile unsigned int*)(0x42A69B70UL))) +#define bM4_DMA2_LLP2_LLP27 (*((volatile unsigned int*)(0x42A69B74UL))) +#define bM4_DMA2_LLP2_LLP28 (*((volatile unsigned int*)(0x42A69B78UL))) +#define bM4_DMA2_LLP2_LLP29 (*((volatile unsigned int*)(0x42A69B7CUL))) +#define bM4_DMA2_CH2CTL_SINC0 (*((volatile unsigned int*)(0x42A69B80UL))) +#define bM4_DMA2_CH2CTL_SINC1 (*((volatile unsigned int*)(0x42A69B84UL))) +#define bM4_DMA2_CH2CTL_DINC0 (*((volatile unsigned int*)(0x42A69B88UL))) +#define bM4_DMA2_CH2CTL_DINC1 (*((volatile unsigned int*)(0x42A69B8CUL))) +#define bM4_DMA2_CH2CTL_SRPTEN (*((volatile unsigned int*)(0x42A69B90UL))) +#define bM4_DMA2_CH2CTL_DRPTEN (*((volatile unsigned int*)(0x42A69B94UL))) +#define bM4_DMA2_CH2CTL_SNSEQEN (*((volatile unsigned int*)(0x42A69B98UL))) +#define bM4_DMA2_CH2CTL_DNSEQEN (*((volatile unsigned int*)(0x42A69B9CUL))) +#define bM4_DMA2_CH2CTL_HSIZE0 (*((volatile unsigned int*)(0x42A69BA0UL))) +#define bM4_DMA2_CH2CTL_HSIZE1 (*((volatile unsigned int*)(0x42A69BA4UL))) +#define bM4_DMA2_CH2CTL_LLPEN (*((volatile unsigned int*)(0x42A69BA8UL))) +#define bM4_DMA2_CH2CTL_LLPRUN (*((volatile unsigned int*)(0x42A69BACUL))) +#define bM4_DMA2_CH2CTL_IE (*((volatile unsigned int*)(0x42A69BB0UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69D00UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69D04UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69D08UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A69D0CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69D10UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69D14UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69D18UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A69D1CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69D20UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69D24UL))) +#define bM4_DMA2_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69D40UL))) +#define bM4_DMA2_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69D44UL))) +#define bM4_DMA2_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69D48UL))) +#define bM4_DMA2_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A69D4CUL))) +#define bM4_DMA2_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69D50UL))) +#define bM4_DMA2_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69D54UL))) +#define bM4_DMA2_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69D58UL))) +#define bM4_DMA2_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A69D5CUL))) +#define bM4_DMA2_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69D60UL))) +#define bM4_DMA2_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69D64UL))) +#define bM4_DMA2_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69D68UL))) +#define bM4_DMA2_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A69D6CUL))) +#define bM4_DMA2_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69D70UL))) +#define bM4_DMA2_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69D74UL))) +#define bM4_DMA2_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69D78UL))) +#define bM4_DMA2_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A69D7CUL))) +#define bM4_DMA2_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A69D80UL))) +#define bM4_DMA2_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A69D84UL))) +#define bM4_DMA2_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A69D88UL))) +#define bM4_DMA2_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A69D8CUL))) +#define bM4_DMA2_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A69D90UL))) +#define bM4_DMA2_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A69D94UL))) +#define bM4_DMA2_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A69D98UL))) +#define bM4_DMA2_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A69D9CUL))) +#define bM4_DMA2_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A69DA0UL))) +#define bM4_DMA2_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A69DA4UL))) +#define bM4_DMA2_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A69DC0UL))) +#define bM4_DMA2_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A69DC4UL))) +#define bM4_DMA2_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A69DC8UL))) +#define bM4_DMA2_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A69DCCUL))) +#define bM4_DMA2_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A69DD0UL))) +#define bM4_DMA2_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A69DD4UL))) +#define bM4_DMA2_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A69DD8UL))) +#define bM4_DMA2_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A69DDCUL))) +#define bM4_DMA2_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A69DE0UL))) +#define bM4_DMA2_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A69DE4UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69E00UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69E04UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69E08UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69E0CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69E10UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69E14UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69E18UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69E1CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69E20UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69E24UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69E28UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69E2CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69E30UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69E34UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69E38UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69E3CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69E40UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69E44UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69E48UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69E4CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69E50UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69E54UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69E58UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69E5CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69E60UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69E64UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69E68UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69E6CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69E70UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69E74UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69E78UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69E7CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69E80UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69E84UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69E88UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69E8CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69E90UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69E94UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69E98UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69E9CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69EA0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69EA4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69EA8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69EACUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69EB0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69EB4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69EB8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69EBCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69EC0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69EC4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69EC8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ECCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69ED0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69ED4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69ED8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69EDCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69EE0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69EE4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69EE8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69EECUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69EF0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69EF4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69EF8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69EFCUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A100UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A104UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A108UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A10CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A110UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A114UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A118UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A11CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A120UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A124UL))) +#define bM4_DMA2_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A140UL))) +#define bM4_DMA2_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A144UL))) +#define bM4_DMA2_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A148UL))) +#define bM4_DMA2_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A14CUL))) +#define bM4_DMA2_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A150UL))) +#define bM4_DMA2_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A154UL))) +#define bM4_DMA2_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A158UL))) +#define bM4_DMA2_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A15CUL))) +#define bM4_DMA2_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A160UL))) +#define bM4_DMA2_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A164UL))) +#define bM4_DMA2_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A168UL))) +#define bM4_DMA2_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A16CUL))) +#define bM4_DMA2_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A170UL))) +#define bM4_DMA2_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A174UL))) +#define bM4_DMA2_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A178UL))) +#define bM4_DMA2_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A17CUL))) +#define bM4_DMA2_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_LLP3_LLP0 (*((volatile unsigned int*)(0x42A6A308UL))) +#define bM4_DMA2_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6A30CUL))) +#define bM4_DMA2_LLP3_LLP2 (*((volatile unsigned int*)(0x42A6A310UL))) +#define bM4_DMA2_LLP3_LLP3 (*((volatile unsigned int*)(0x42A6A314UL))) +#define bM4_DMA2_LLP3_LLP4 (*((volatile unsigned int*)(0x42A6A318UL))) +#define bM4_DMA2_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6A31CUL))) +#define bM4_DMA2_LLP3_LLP6 (*((volatile unsigned int*)(0x42A6A320UL))) +#define bM4_DMA2_LLP3_LLP7 (*((volatile unsigned int*)(0x42A6A324UL))) +#define bM4_DMA2_LLP3_LLP8 (*((volatile unsigned int*)(0x42A6A328UL))) +#define bM4_DMA2_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6A32CUL))) +#define bM4_DMA2_LLP3_LLP10 (*((volatile unsigned int*)(0x42A6A330UL))) +#define bM4_DMA2_LLP3_LLP11 (*((volatile unsigned int*)(0x42A6A334UL))) +#define bM4_DMA2_LLP3_LLP12 (*((volatile unsigned int*)(0x42A6A338UL))) +#define bM4_DMA2_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6A33CUL))) +#define bM4_DMA2_LLP3_LLP14 (*((volatile unsigned int*)(0x42A6A340UL))) +#define bM4_DMA2_LLP3_LLP15 (*((volatile unsigned int*)(0x42A6A344UL))) +#define bM4_DMA2_LLP3_LLP16 (*((volatile unsigned int*)(0x42A6A348UL))) +#define bM4_DMA2_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6A34CUL))) +#define bM4_DMA2_LLP3_LLP18 (*((volatile unsigned int*)(0x42A6A350UL))) +#define bM4_DMA2_LLP3_LLP19 (*((volatile unsigned int*)(0x42A6A354UL))) +#define bM4_DMA2_LLP3_LLP20 (*((volatile unsigned int*)(0x42A6A358UL))) +#define bM4_DMA2_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6A35CUL))) +#define bM4_DMA2_LLP3_LLP22 (*((volatile unsigned int*)(0x42A6A360UL))) +#define bM4_DMA2_LLP3_LLP23 (*((volatile unsigned int*)(0x42A6A364UL))) +#define bM4_DMA2_LLP3_LLP24 (*((volatile unsigned int*)(0x42A6A368UL))) +#define bM4_DMA2_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6A36CUL))) +#define bM4_DMA2_LLP3_LLP26 (*((volatile unsigned int*)(0x42A6A370UL))) +#define bM4_DMA2_LLP3_LLP27 (*((volatile unsigned int*)(0x42A6A374UL))) +#define bM4_DMA2_LLP3_LLP28 (*((volatile unsigned int*)(0x42A6A378UL))) +#define bM4_DMA2_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6A37CUL))) +#define bM4_DMA2_CH3CTL_SINC0 (*((volatile unsigned int*)(0x42A6A380UL))) +#define bM4_DMA2_CH3CTL_SINC1 (*((volatile unsigned int*)(0x42A6A384UL))) +#define bM4_DMA2_CH3CTL_DINC0 (*((volatile unsigned int*)(0x42A6A388UL))) +#define bM4_DMA2_CH3CTL_DINC1 (*((volatile unsigned int*)(0x42A6A38CUL))) +#define bM4_DMA2_CH3CTL_SRPTEN (*((volatile unsigned int*)(0x42A6A390UL))) +#define bM4_DMA2_CH3CTL_DRPTEN (*((volatile unsigned int*)(0x42A6A394UL))) +#define bM4_DMA2_CH3CTL_SNSEQEN (*((volatile unsigned int*)(0x42A6A398UL))) +#define bM4_DMA2_CH3CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6A39CUL))) +#define bM4_DMA2_CH3CTL_HSIZE0 (*((volatile unsigned int*)(0x42A6A3A0UL))) +#define bM4_DMA2_CH3CTL_HSIZE1 (*((volatile unsigned int*)(0x42A6A3A4UL))) +#define bM4_DMA2_CH3CTL_LLPEN (*((volatile unsigned int*)(0x42A6A3A8UL))) +#define bM4_DMA2_CH3CTL_LLPRUN (*((volatile unsigned int*)(0x42A6A3ACUL))) +#define bM4_DMA2_CH3CTL_IE (*((volatile unsigned int*)(0x42A6A3B0UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A500UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A504UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A508UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A50CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A510UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A514UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A518UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A51CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A520UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A524UL))) +#define bM4_DMA2_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A540UL))) +#define bM4_DMA2_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A544UL))) +#define bM4_DMA2_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A548UL))) +#define bM4_DMA2_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A54CUL))) +#define bM4_DMA2_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A550UL))) +#define bM4_DMA2_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A554UL))) +#define bM4_DMA2_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A558UL))) +#define bM4_DMA2_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A55CUL))) +#define bM4_DMA2_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A560UL))) +#define bM4_DMA2_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A564UL))) +#define bM4_DMA2_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A568UL))) +#define bM4_DMA2_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A56CUL))) +#define bM4_DMA2_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A570UL))) +#define bM4_DMA2_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A574UL))) +#define bM4_DMA2_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A578UL))) +#define bM4_DMA2_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A57CUL))) +#define bM4_DMA2_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A580UL))) +#define bM4_DMA2_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A584UL))) +#define bM4_DMA2_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A588UL))) +#define bM4_DMA2_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A58CUL))) +#define bM4_DMA2_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A590UL))) +#define bM4_DMA2_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A594UL))) +#define bM4_DMA2_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A598UL))) +#define bM4_DMA2_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A59CUL))) +#define bM4_DMA2_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A5A0UL))) +#define bM4_DMA2_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A5A4UL))) +#define bM4_DMA2_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A5C0UL))) +#define bM4_DMA2_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A5C4UL))) +#define bM4_DMA2_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A5C8UL))) +#define bM4_DMA2_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A5CCUL))) +#define bM4_DMA2_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A5D0UL))) +#define bM4_DMA2_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A5D4UL))) +#define bM4_DMA2_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A5D8UL))) +#define bM4_DMA2_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A5DCUL))) +#define bM4_DMA2_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A5E0UL))) +#define bM4_DMA2_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A5E4UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A600UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A604UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A608UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A60CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A610UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A614UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A618UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A61CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A620UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A624UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A628UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A62CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A630UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A634UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A638UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A63CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A640UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A644UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A648UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A64CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A650UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A654UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A658UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A65CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A660UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A664UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A668UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A66CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A670UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A674UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A678UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A67CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A680UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A684UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A688UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A68CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A690UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A694UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A698UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A69CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A6A0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A6A4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A6A8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A6ACUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A6B0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A6B4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A6B8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A6BCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A6C0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A6C4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A6C8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A6CCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A6D0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A6D4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A6D8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A6DCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A6E0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A6E4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A6E8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A6ECUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A6F0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A6F4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A6F8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A6FCUL))) +#define bM4_EFM_FAPRT_FAPRT0 (*((volatile unsigned int*)(0x42208000UL))) +#define bM4_EFM_FAPRT_FAPRT1 (*((volatile unsigned int*)(0x42208004UL))) +#define bM4_EFM_FAPRT_FAPRT2 (*((volatile unsigned int*)(0x42208008UL))) +#define bM4_EFM_FAPRT_FAPRT3 (*((volatile unsigned int*)(0x4220800CUL))) +#define bM4_EFM_FAPRT_FAPRT4 (*((volatile unsigned int*)(0x42208010UL))) +#define bM4_EFM_FAPRT_FAPRT5 (*((volatile unsigned int*)(0x42208014UL))) +#define bM4_EFM_FAPRT_FAPRT6 (*((volatile unsigned int*)(0x42208018UL))) +#define bM4_EFM_FAPRT_FAPRT7 (*((volatile unsigned int*)(0x4220801CUL))) +#define bM4_EFM_FAPRT_FAPRT8 (*((volatile unsigned int*)(0x42208020UL))) +#define bM4_EFM_FAPRT_FAPRT9 (*((volatile unsigned int*)(0x42208024UL))) +#define bM4_EFM_FAPRT_FAPRT10 (*((volatile unsigned int*)(0x42208028UL))) +#define bM4_EFM_FAPRT_FAPRT11 (*((volatile unsigned int*)(0x4220802CUL))) +#define bM4_EFM_FAPRT_FAPRT12 (*((volatile unsigned int*)(0x42208030UL))) +#define bM4_EFM_FAPRT_FAPRT13 (*((volatile unsigned int*)(0x42208034UL))) +#define bM4_EFM_FAPRT_FAPRT14 (*((volatile unsigned int*)(0x42208038UL))) +#define bM4_EFM_FAPRT_FAPRT15 (*((volatile unsigned int*)(0x4220803CUL))) +#define bM4_EFM_FSTP_FSTP (*((volatile unsigned int*)(0x42208080UL))) +#define bM4_EFM_FRMC_SLPMD (*((volatile unsigned int*)(0x42208100UL))) +#define bM4_EFM_FRMC_FLWT0 (*((volatile unsigned int*)(0x42208110UL))) +#define bM4_EFM_FRMC_FLWT1 (*((volatile unsigned int*)(0x42208114UL))) +#define bM4_EFM_FRMC_FLWT2 (*((volatile unsigned int*)(0x42208118UL))) +#define bM4_EFM_FRMC_FLWT3 (*((volatile unsigned int*)(0x4220811CUL))) +#define bM4_EFM_FRMC_LVM (*((volatile unsigned int*)(0x42208120UL))) +#define bM4_EFM_FRMC_CACHE (*((volatile unsigned int*)(0x42208140UL))) +#define bM4_EFM_FRMC_CRST (*((volatile unsigned int*)(0x42208160UL))) +#define bM4_EFM_FWMC_PEMODE (*((volatile unsigned int*)(0x42208180UL))) +#define bM4_EFM_FWMC_PEMOD0 (*((volatile unsigned int*)(0x42208190UL))) +#define bM4_EFM_FWMC_PEMOD1 (*((volatile unsigned int*)(0x42208194UL))) +#define bM4_EFM_FWMC_PEMOD2 (*((volatile unsigned int*)(0x42208198UL))) +#define bM4_EFM_FWMC_BUSHLDCTL (*((volatile unsigned int*)(0x422081A0UL))) +#define bM4_EFM_FSR_PEWERR (*((volatile unsigned int*)(0x42208200UL))) +#define bM4_EFM_FSR_PEPRTERR (*((volatile unsigned int*)(0x42208204UL))) +#define bM4_EFM_FSR_PGSZERR (*((volatile unsigned int*)(0x42208208UL))) +#define bM4_EFM_FSR_PGMISMTCH (*((volatile unsigned int*)(0x4220820CUL))) +#define bM4_EFM_FSR_OPTEND (*((volatile unsigned int*)(0x42208210UL))) +#define bM4_EFM_FSR_COLERR (*((volatile unsigned int*)(0x42208214UL))) +#define bM4_EFM_FSR_RDY (*((volatile unsigned int*)(0x42208220UL))) +#define bM4_EFM_FSCLR_PEWERRCLR (*((volatile unsigned int*)(0x42208280UL))) +#define bM4_EFM_FSCLR_PEPRTERRCLR (*((volatile unsigned int*)(0x42208284UL))) +#define bM4_EFM_FSCLR_PGSZERRCLR (*((volatile unsigned int*)(0x42208288UL))) +#define bM4_EFM_FSCLR_PGMISMTCHCLR (*((volatile unsigned int*)(0x4220828CUL))) +#define bM4_EFM_FSCLR_OPTENDCLR (*((volatile unsigned int*)(0x42208290UL))) +#define bM4_EFM_FSCLR_COLERRCLR (*((volatile unsigned int*)(0x42208294UL))) +#define bM4_EFM_FITE_PEERRITE (*((volatile unsigned int*)(0x42208300UL))) +#define bM4_EFM_FITE_OPTENDITE (*((volatile unsigned int*)(0x42208304UL))) +#define bM4_EFM_FITE_COLERRITE (*((volatile unsigned int*)(0x42208308UL))) +#define bM4_EFM_FSWP_FSWP (*((volatile unsigned int*)(0x42208380UL))) +#define bM4_EFM_FPMTSW_FPMTSW0 (*((volatile unsigned int*)(0x42208400UL))) +#define bM4_EFM_FPMTSW_FPMTSW1 (*((volatile unsigned int*)(0x42208404UL))) +#define bM4_EFM_FPMTSW_FPMTSW2 (*((volatile unsigned int*)(0x42208408UL))) +#define bM4_EFM_FPMTSW_FPMTSW3 (*((volatile unsigned int*)(0x4220840CUL))) +#define bM4_EFM_FPMTSW_FPMTSW4 (*((volatile unsigned int*)(0x42208410UL))) +#define bM4_EFM_FPMTSW_FPMTSW5 (*((volatile unsigned int*)(0x42208414UL))) +#define bM4_EFM_FPMTSW_FPMTSW6 (*((volatile unsigned int*)(0x42208418UL))) +#define bM4_EFM_FPMTSW_FPMTSW7 (*((volatile unsigned int*)(0x4220841CUL))) +#define bM4_EFM_FPMTSW_FPMTSW8 (*((volatile unsigned int*)(0x42208420UL))) +#define bM4_EFM_FPMTSW_FPMTSW9 (*((volatile unsigned int*)(0x42208424UL))) +#define bM4_EFM_FPMTSW_FPMTSW10 (*((volatile unsigned int*)(0x42208428UL))) +#define bM4_EFM_FPMTSW_FPMTSW11 (*((volatile unsigned int*)(0x4220842CUL))) +#define bM4_EFM_FPMTSW_FPMTSW12 (*((volatile unsigned int*)(0x42208430UL))) +#define bM4_EFM_FPMTSW_FPMTSW13 (*((volatile unsigned int*)(0x42208434UL))) +#define bM4_EFM_FPMTSW_FPMTSW14 (*((volatile unsigned int*)(0x42208438UL))) +#define bM4_EFM_FPMTSW_FPMTSW15 (*((volatile unsigned int*)(0x4220843CUL))) +#define bM4_EFM_FPMTSW_FPMTSW16 (*((volatile unsigned int*)(0x42208440UL))) +#define bM4_EFM_FPMTSW_FPMTSW17 (*((volatile unsigned int*)(0x42208444UL))) +#define bM4_EFM_FPMTSW_FPMTSW18 (*((volatile unsigned int*)(0x42208448UL))) +#define bM4_EFM_FPMTEW_FPMTEW0 (*((volatile unsigned int*)(0x42208480UL))) +#define bM4_EFM_FPMTEW_FPMTEW1 (*((volatile unsigned int*)(0x42208484UL))) +#define bM4_EFM_FPMTEW_FPMTEW2 (*((volatile unsigned int*)(0x42208488UL))) +#define bM4_EFM_FPMTEW_FPMTEW3 (*((volatile unsigned int*)(0x4220848CUL))) +#define bM4_EFM_FPMTEW_FPMTEW4 (*((volatile unsigned int*)(0x42208490UL))) +#define bM4_EFM_FPMTEW_FPMTEW5 (*((volatile unsigned int*)(0x42208494UL))) +#define bM4_EFM_FPMTEW_FPMTEW6 (*((volatile unsigned int*)(0x42208498UL))) +#define bM4_EFM_FPMTEW_FPMTEW7 (*((volatile unsigned int*)(0x4220849CUL))) +#define bM4_EFM_FPMTEW_FPMTEW8 (*((volatile unsigned int*)(0x422084A0UL))) +#define bM4_EFM_FPMTEW_FPMTEW9 (*((volatile unsigned int*)(0x422084A4UL))) +#define bM4_EFM_FPMTEW_FPMTEW10 (*((volatile unsigned int*)(0x422084A8UL))) +#define bM4_EFM_FPMTEW_FPMTEW11 (*((volatile unsigned int*)(0x422084ACUL))) +#define bM4_EFM_FPMTEW_FPMTEW12 (*((volatile unsigned int*)(0x422084B0UL))) +#define bM4_EFM_FPMTEW_FPMTEW13 (*((volatile unsigned int*)(0x422084B4UL))) +#define bM4_EFM_FPMTEW_FPMTEW14 (*((volatile unsigned int*)(0x422084B8UL))) +#define bM4_EFM_FPMTEW_FPMTEW15 (*((volatile unsigned int*)(0x422084BCUL))) +#define bM4_EFM_FPMTEW_FPMTEW16 (*((volatile unsigned int*)(0x422084C0UL))) +#define bM4_EFM_FPMTEW_FPMTEW17 (*((volatile unsigned int*)(0x422084C4UL))) +#define bM4_EFM_FPMTEW_FPMTEW18 (*((volatile unsigned int*)(0x422084C8UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT0 (*((volatile unsigned int*)(0x4220A000UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT1 (*((volatile unsigned int*)(0x4220A004UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT2 (*((volatile unsigned int*)(0x4220A008UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT3 (*((volatile unsigned int*)(0x4220A00CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT4 (*((volatile unsigned int*)(0x4220A010UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT5 (*((volatile unsigned int*)(0x4220A014UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT6 (*((volatile unsigned int*)(0x4220A018UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT7 (*((volatile unsigned int*)(0x4220A01CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT8 (*((volatile unsigned int*)(0x4220A020UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT9 (*((volatile unsigned int*)(0x4220A024UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT10 (*((volatile unsigned int*)(0x4220A028UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT11 (*((volatile unsigned int*)(0x4220A02CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT12 (*((volatile unsigned int*)(0x4220A030UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT13 (*((volatile unsigned int*)(0x4220A034UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT14 (*((volatile unsigned int*)(0x4220A038UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT15 (*((volatile unsigned int*)(0x4220A03CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE0 (*((volatile unsigned int*)(0x4220A080UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE1 (*((volatile unsigned int*)(0x4220A084UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE2 (*((volatile unsigned int*)(0x4220A088UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE3 (*((volatile unsigned int*)(0x4220A08CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE4 (*((volatile unsigned int*)(0x4220A090UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR0 (*((volatile unsigned int*)(0x4220A0B0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR1 (*((volatile unsigned int*)(0x4220A0B4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR2 (*((volatile unsigned int*)(0x4220A0B8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR3 (*((volatile unsigned int*)(0x4220A0BCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR4 (*((volatile unsigned int*)(0x4220A0C0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR5 (*((volatile unsigned int*)(0x4220A0C4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR6 (*((volatile unsigned int*)(0x4220A0C8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR7 (*((volatile unsigned int*)(0x4220A0CCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR8 (*((volatile unsigned int*)(0x4220A0D0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR9 (*((volatile unsigned int*)(0x4220A0D4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR10 (*((volatile unsigned int*)(0x4220A0D8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR11 (*((volatile unsigned int*)(0x4220A0DCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR12 (*((volatile unsigned int*)(0x4220A0E0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR13 (*((volatile unsigned int*)(0x4220A0E4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR14 (*((volatile unsigned int*)(0x4220A0E8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR15 (*((volatile unsigned int*)(0x4220A0ECUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR16 (*((volatile unsigned int*)(0x4220A0F0UL))) +#define bM4_EFM_MMF_REMCR0_EN0 (*((volatile unsigned int*)(0x4220A0FCUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE0 (*((volatile unsigned int*)(0x4220A100UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE1 (*((volatile unsigned int*)(0x4220A104UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE2 (*((volatile unsigned int*)(0x4220A108UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE3 (*((volatile unsigned int*)(0x4220A10CUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE4 (*((volatile unsigned int*)(0x4220A110UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR0 (*((volatile unsigned int*)(0x4220A130UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR1 (*((volatile unsigned int*)(0x4220A134UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR2 (*((volatile unsigned int*)(0x4220A138UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR3 (*((volatile unsigned int*)(0x4220A13CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR4 (*((volatile unsigned int*)(0x4220A140UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR5 (*((volatile unsigned int*)(0x4220A144UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR6 (*((volatile unsigned int*)(0x4220A148UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR7 (*((volatile unsigned int*)(0x4220A14CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR8 (*((volatile unsigned int*)(0x4220A150UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR9 (*((volatile unsigned int*)(0x4220A154UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR10 (*((volatile unsigned int*)(0x4220A158UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR11 (*((volatile unsigned int*)(0x4220A15CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR12 (*((volatile unsigned int*)(0x4220A160UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR13 (*((volatile unsigned int*)(0x4220A164UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR14 (*((volatile unsigned int*)(0x4220A168UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR15 (*((volatile unsigned int*)(0x4220A16CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR16 (*((volatile unsigned int*)(0x4220A170UL))) +#define bM4_EFM_MMF_REMCR1_EN1 (*((volatile unsigned int*)(0x4220A17CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS0 (*((volatile unsigned int*)(0x4220C084UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS1 (*((volatile unsigned int*)(0x4220C088UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS2 (*((volatile unsigned int*)(0x4220C08CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS3 (*((volatile unsigned int*)(0x4220C090UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS4 (*((volatile unsigned int*)(0x4220C094UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS5 (*((volatile unsigned int*)(0x4220C098UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS6 (*((volatile unsigned int*)(0x4220C09CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS7 (*((volatile unsigned int*)(0x4220C0A0UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS8 (*((volatile unsigned int*)(0x4220C0A4UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS9 (*((volatile unsigned int*)(0x4220C0A8UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS10 (*((volatile unsigned int*)(0x4220C0ACUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS11 (*((volatile unsigned int*)(0x4220C0B0UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS12 (*((volatile unsigned int*)(0x4220C0B4UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS13 (*((volatile unsigned int*)(0x4220C0B8UL))) +#define bM4_EFM_EFM_FRANDS_FRANDFG (*((volatile unsigned int*)(0x4220C0C0UL))) +#define bM4_EMB1_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8000UL))) +#define bM4_EMB1_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8004UL))) +#define bM4_EMB1_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8008UL))) +#define bM4_EMB1_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F800CUL))) +#define bM4_EMB1_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8014UL))) +#define bM4_EMB1_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8018UL))) +#define bM4_EMB1_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F801CUL))) +#define bM4_EMB1_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8020UL))) +#define bM4_EMB1_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8070UL))) +#define bM4_EMB1_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8074UL))) +#define bM4_EMB1_CTL_NFEN (*((volatile unsigned int*)(0x422F8078UL))) +#define bM4_EMB1_CTL_INVSEL (*((volatile unsigned int*)(0x422F807CUL))) +#define bM4_EMB1_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8080UL))) +#define bM4_EMB1_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8084UL))) +#define bM4_EMB1_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8088UL))) +#define bM4_EMB1_SOE_SOE (*((volatile unsigned int*)(0x422F8100UL))) +#define bM4_EMB1_STAT_PORTINF (*((volatile unsigned int*)(0x422F8180UL))) +#define bM4_EMB1_STAT_PWMSF (*((volatile unsigned int*)(0x422F8184UL))) +#define bM4_EMB1_STAT_CMPF (*((volatile unsigned int*)(0x422F8188UL))) +#define bM4_EMB1_STAT_OSF (*((volatile unsigned int*)(0x422F818CUL))) +#define bM4_EMB1_STAT_PORTINST (*((volatile unsigned int*)(0x422F8190UL))) +#define bM4_EMB1_STAT_PWMST (*((volatile unsigned int*)(0x422F8194UL))) +#define bM4_EMB1_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8200UL))) +#define bM4_EMB1_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8204UL))) +#define bM4_EMB1_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8208UL))) +#define bM4_EMB1_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F820CUL))) +#define bM4_EMB1_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8280UL))) +#define bM4_EMB1_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8284UL))) +#define bM4_EMB1_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8288UL))) +#define bM4_EMB1_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F828CUL))) +#define bM4_EMB2_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8400UL))) +#define bM4_EMB2_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8404UL))) +#define bM4_EMB2_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8408UL))) +#define bM4_EMB2_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F840CUL))) +#define bM4_EMB2_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8414UL))) +#define bM4_EMB2_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8418UL))) +#define bM4_EMB2_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F841CUL))) +#define bM4_EMB2_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8420UL))) +#define bM4_EMB2_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8470UL))) +#define bM4_EMB2_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8474UL))) +#define bM4_EMB2_CTL_NFEN (*((volatile unsigned int*)(0x422F8478UL))) +#define bM4_EMB2_CTL_INVSEL (*((volatile unsigned int*)(0x422F847CUL))) +#define bM4_EMB2_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8480UL))) +#define bM4_EMB2_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8484UL))) +#define bM4_EMB2_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8488UL))) +#define bM4_EMB2_SOE_SOE (*((volatile unsigned int*)(0x422F8500UL))) +#define bM4_EMB2_STAT_PORTINF (*((volatile unsigned int*)(0x422F8580UL))) +#define bM4_EMB2_STAT_PWMSF (*((volatile unsigned int*)(0x422F8584UL))) +#define bM4_EMB2_STAT_CMPF (*((volatile unsigned int*)(0x422F8588UL))) +#define bM4_EMB2_STAT_OSF (*((volatile unsigned int*)(0x422F858CUL))) +#define bM4_EMB2_STAT_PORTINST (*((volatile unsigned int*)(0x422F8590UL))) +#define bM4_EMB2_STAT_PWMST (*((volatile unsigned int*)(0x422F8594UL))) +#define bM4_EMB2_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8600UL))) +#define bM4_EMB2_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8604UL))) +#define bM4_EMB2_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8608UL))) +#define bM4_EMB2_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F860CUL))) +#define bM4_EMB2_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8680UL))) +#define bM4_EMB2_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8684UL))) +#define bM4_EMB2_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8688UL))) +#define bM4_EMB2_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F868CUL))) +#define bM4_EMB3_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8800UL))) +#define bM4_EMB3_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8804UL))) +#define bM4_EMB3_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8808UL))) +#define bM4_EMB3_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F880CUL))) +#define bM4_EMB3_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8814UL))) +#define bM4_EMB3_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8818UL))) +#define bM4_EMB3_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F881CUL))) +#define bM4_EMB3_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8820UL))) +#define bM4_EMB3_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8870UL))) +#define bM4_EMB3_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8874UL))) +#define bM4_EMB3_CTL_NFEN (*((volatile unsigned int*)(0x422F8878UL))) +#define bM4_EMB3_CTL_INVSEL (*((volatile unsigned int*)(0x422F887CUL))) +#define bM4_EMB3_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8880UL))) +#define bM4_EMB3_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8884UL))) +#define bM4_EMB3_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8888UL))) +#define bM4_EMB3_SOE_SOE (*((volatile unsigned int*)(0x422F8900UL))) +#define bM4_EMB3_STAT_PORTINF (*((volatile unsigned int*)(0x422F8980UL))) +#define bM4_EMB3_STAT_PWMSF (*((volatile unsigned int*)(0x422F8984UL))) +#define bM4_EMB3_STAT_CMPF (*((volatile unsigned int*)(0x422F8988UL))) +#define bM4_EMB3_STAT_OSF (*((volatile unsigned int*)(0x422F898CUL))) +#define bM4_EMB3_STAT_PORTINST (*((volatile unsigned int*)(0x422F8990UL))) +#define bM4_EMB3_STAT_PWMST (*((volatile unsigned int*)(0x422F8994UL))) +#define bM4_EMB3_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8A00UL))) +#define bM4_EMB3_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8A04UL))) +#define bM4_EMB3_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8A08UL))) +#define bM4_EMB3_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8A0CUL))) +#define bM4_EMB3_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8A80UL))) +#define bM4_EMB3_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8A84UL))) +#define bM4_EMB3_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8A88UL))) +#define bM4_EMB3_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8A8CUL))) +#define bM4_EMB4_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8C00UL))) +#define bM4_EMB4_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8C04UL))) +#define bM4_EMB4_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8C08UL))) +#define bM4_EMB4_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F8C0CUL))) +#define bM4_EMB4_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8C14UL))) +#define bM4_EMB4_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8C18UL))) +#define bM4_EMB4_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F8C1CUL))) +#define bM4_EMB4_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8C20UL))) +#define bM4_EMB4_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8C70UL))) +#define bM4_EMB4_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8C74UL))) +#define bM4_EMB4_CTL_NFEN (*((volatile unsigned int*)(0x422F8C78UL))) +#define bM4_EMB4_CTL_INVSEL (*((volatile unsigned int*)(0x422F8C7CUL))) +#define bM4_EMB4_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8C80UL))) +#define bM4_EMB4_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8C84UL))) +#define bM4_EMB4_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8C88UL))) +#define bM4_EMB4_SOE_SOE (*((volatile unsigned int*)(0x422F8D00UL))) +#define bM4_EMB4_STAT_PORTINF (*((volatile unsigned int*)(0x422F8D80UL))) +#define bM4_EMB4_STAT_PWMSF (*((volatile unsigned int*)(0x422F8D84UL))) +#define bM4_EMB4_STAT_CMPF (*((volatile unsigned int*)(0x422F8D88UL))) +#define bM4_EMB4_STAT_OSF (*((volatile unsigned int*)(0x422F8D8CUL))) +#define bM4_EMB4_STAT_PORTINST (*((volatile unsigned int*)(0x422F8D90UL))) +#define bM4_EMB4_STAT_PWMST (*((volatile unsigned int*)(0x422F8D94UL))) +#define bM4_EMB4_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8E00UL))) +#define bM4_EMB4_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8E04UL))) +#define bM4_EMB4_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8E08UL))) +#define bM4_EMB4_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8E0CUL))) +#define bM4_EMB4_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8E80UL))) +#define bM4_EMB4_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8E84UL))) +#define bM4_EMB4_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8E88UL))) +#define bM4_EMB4_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8E8CUL))) +#define bM4_FCM_LVR_LVR0 (*((volatile unsigned int*)(0x42908000UL))) +#define bM4_FCM_LVR_LVR1 (*((volatile unsigned int*)(0x42908004UL))) +#define bM4_FCM_LVR_LVR2 (*((volatile unsigned int*)(0x42908008UL))) +#define bM4_FCM_LVR_LVR3 (*((volatile unsigned int*)(0x4290800CUL))) +#define bM4_FCM_LVR_LVR4 (*((volatile unsigned int*)(0x42908010UL))) +#define bM4_FCM_LVR_LVR5 (*((volatile unsigned int*)(0x42908014UL))) +#define bM4_FCM_LVR_LVR6 (*((volatile unsigned int*)(0x42908018UL))) +#define bM4_FCM_LVR_LVR7 (*((volatile unsigned int*)(0x4290801CUL))) +#define bM4_FCM_LVR_LVR8 (*((volatile unsigned int*)(0x42908020UL))) +#define bM4_FCM_LVR_LVR9 (*((volatile unsigned int*)(0x42908024UL))) +#define bM4_FCM_LVR_LVR10 (*((volatile unsigned int*)(0x42908028UL))) +#define bM4_FCM_LVR_LVR11 (*((volatile unsigned int*)(0x4290802CUL))) +#define bM4_FCM_LVR_LVR12 (*((volatile unsigned int*)(0x42908030UL))) +#define bM4_FCM_LVR_LVR13 (*((volatile unsigned int*)(0x42908034UL))) +#define bM4_FCM_LVR_LVR14 (*((volatile unsigned int*)(0x42908038UL))) +#define bM4_FCM_LVR_LVR15 (*((volatile unsigned int*)(0x4290803CUL))) +#define bM4_FCM_UVR_UVR0 (*((volatile unsigned int*)(0x42908080UL))) +#define bM4_FCM_UVR_UVR1 (*((volatile unsigned int*)(0x42908084UL))) +#define bM4_FCM_UVR_UVR2 (*((volatile unsigned int*)(0x42908088UL))) +#define bM4_FCM_UVR_UVR3 (*((volatile unsigned int*)(0x4290808CUL))) +#define bM4_FCM_UVR_UVR4 (*((volatile unsigned int*)(0x42908090UL))) +#define bM4_FCM_UVR_UVR5 (*((volatile unsigned int*)(0x42908094UL))) +#define bM4_FCM_UVR_UVR6 (*((volatile unsigned int*)(0x42908098UL))) +#define bM4_FCM_UVR_UVR7 (*((volatile unsigned int*)(0x4290809CUL))) +#define bM4_FCM_UVR_UVR8 (*((volatile unsigned int*)(0x429080A0UL))) +#define bM4_FCM_UVR_UVR9 (*((volatile unsigned int*)(0x429080A4UL))) +#define bM4_FCM_UVR_UVR10 (*((volatile unsigned int*)(0x429080A8UL))) +#define bM4_FCM_UVR_UVR11 (*((volatile unsigned int*)(0x429080ACUL))) +#define bM4_FCM_UVR_UVR12 (*((volatile unsigned int*)(0x429080B0UL))) +#define bM4_FCM_UVR_UVR13 (*((volatile unsigned int*)(0x429080B4UL))) +#define bM4_FCM_UVR_UVR14 (*((volatile unsigned int*)(0x429080B8UL))) +#define bM4_FCM_UVR_UVR15 (*((volatile unsigned int*)(0x429080BCUL))) +#define bM4_FCM_CNTR_CNTR0 (*((volatile unsigned int*)(0x42908100UL))) +#define bM4_FCM_CNTR_CNTR1 (*((volatile unsigned int*)(0x42908104UL))) +#define bM4_FCM_CNTR_CNTR2 (*((volatile unsigned int*)(0x42908108UL))) +#define bM4_FCM_CNTR_CNTR3 (*((volatile unsigned int*)(0x4290810CUL))) +#define bM4_FCM_CNTR_CNTR4 (*((volatile unsigned int*)(0x42908110UL))) +#define bM4_FCM_CNTR_CNTR5 (*((volatile unsigned int*)(0x42908114UL))) +#define bM4_FCM_CNTR_CNTR6 (*((volatile unsigned int*)(0x42908118UL))) +#define bM4_FCM_CNTR_CNTR7 (*((volatile unsigned int*)(0x4290811CUL))) +#define bM4_FCM_CNTR_CNTR8 (*((volatile unsigned int*)(0x42908120UL))) +#define bM4_FCM_CNTR_CNTR9 (*((volatile unsigned int*)(0x42908124UL))) +#define bM4_FCM_CNTR_CNTR10 (*((volatile unsigned int*)(0x42908128UL))) +#define bM4_FCM_CNTR_CNTR11 (*((volatile unsigned int*)(0x4290812CUL))) +#define bM4_FCM_CNTR_CNTR12 (*((volatile unsigned int*)(0x42908130UL))) +#define bM4_FCM_CNTR_CNTR13 (*((volatile unsigned int*)(0x42908134UL))) +#define bM4_FCM_CNTR_CNTR14 (*((volatile unsigned int*)(0x42908138UL))) +#define bM4_FCM_CNTR_CNTR15 (*((volatile unsigned int*)(0x4290813CUL))) +#define bM4_FCM_STR_START (*((volatile unsigned int*)(0x42908180UL))) +#define bM4_FCM_MCCR_MDIVS0 (*((volatile unsigned int*)(0x42908200UL))) +#define bM4_FCM_MCCR_MDIVS1 (*((volatile unsigned int*)(0x42908204UL))) +#define bM4_FCM_MCCR_MCKS0 (*((volatile unsigned int*)(0x42908210UL))) +#define bM4_FCM_MCCR_MCKS1 (*((volatile unsigned int*)(0x42908214UL))) +#define bM4_FCM_MCCR_MCKS2 (*((volatile unsigned int*)(0x42908218UL))) +#define bM4_FCM_MCCR_MCKS3 (*((volatile unsigned int*)(0x4290821CUL))) +#define bM4_FCM_RCCR_RDIVS0 (*((volatile unsigned int*)(0x42908280UL))) +#define bM4_FCM_RCCR_RDIVS1 (*((volatile unsigned int*)(0x42908284UL))) +#define bM4_FCM_RCCR_RCKS0 (*((volatile unsigned int*)(0x4290828CUL))) +#define bM4_FCM_RCCR_RCKS1 (*((volatile unsigned int*)(0x42908290UL))) +#define bM4_FCM_RCCR_RCKS2 (*((volatile unsigned int*)(0x42908294UL))) +#define bM4_FCM_RCCR_RCKS3 (*((volatile unsigned int*)(0x42908298UL))) +#define bM4_FCM_RCCR_INEXS (*((volatile unsigned int*)(0x4290829CUL))) +#define bM4_FCM_RCCR_DNFS0 (*((volatile unsigned int*)(0x429082A0UL))) +#define bM4_FCM_RCCR_DNFS1 (*((volatile unsigned int*)(0x429082A4UL))) +#define bM4_FCM_RCCR_EDGES0 (*((volatile unsigned int*)(0x429082B0UL))) +#define bM4_FCM_RCCR_EDGES1 (*((volatile unsigned int*)(0x429082B4UL))) +#define bM4_FCM_RCCR_EXREFE (*((volatile unsigned int*)(0x429082BCUL))) +#define bM4_FCM_RIER_ERRIE (*((volatile unsigned int*)(0x42908300UL))) +#define bM4_FCM_RIER_MENDIE (*((volatile unsigned int*)(0x42908304UL))) +#define bM4_FCM_RIER_OVFIE (*((volatile unsigned int*)(0x42908308UL))) +#define bM4_FCM_RIER_ERRINTRS (*((volatile unsigned int*)(0x42908310UL))) +#define bM4_FCM_RIER_ERRE (*((volatile unsigned int*)(0x4290831CUL))) +#define bM4_FCM_SR_ERRF (*((volatile unsigned int*)(0x42908380UL))) +#define bM4_FCM_SR_MENDF (*((volatile unsigned int*)(0x42908384UL))) +#define bM4_FCM_SR_OVF (*((volatile unsigned int*)(0x42908388UL))) +#define bM4_FCM_CLR_ERRFCLR (*((volatile unsigned int*)(0x42908400UL))) +#define bM4_FCM_CLR_MENDFCLR (*((volatile unsigned int*)(0x42908404UL))) +#define bM4_FCM_CLR_OVFCLR (*((volatile unsigned int*)(0x42908408UL))) +#define bM4_HASH_CR_START (*((volatile unsigned int*)(0x42108000UL))) +#define bM4_HASH_CR_FST_GRP (*((volatile unsigned int*)(0x42108004UL))) +#define bM4_I2C1_CR1_PE (*((volatile unsigned int*)(0x429C0000UL))) +#define bM4_I2C1_CR1_SMBUS (*((volatile unsigned int*)(0x429C0004UL))) +#define bM4_I2C1_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C0008UL))) +#define bM4_I2C1_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C000CUL))) +#define bM4_I2C1_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C0010UL))) +#define bM4_I2C1_CR1_ENGC (*((volatile unsigned int*)(0x429C0018UL))) +#define bM4_I2C1_CR1_RESTART (*((volatile unsigned int*)(0x429C001CUL))) +#define bM4_I2C1_CR1_START (*((volatile unsigned int*)(0x429C0020UL))) +#define bM4_I2C1_CR1_STOP (*((volatile unsigned int*)(0x429C0024UL))) +#define bM4_I2C1_CR1_ACK (*((volatile unsigned int*)(0x429C0028UL))) +#define bM4_I2C1_CR1_SWRST (*((volatile unsigned int*)(0x429C003CUL))) +#define bM4_I2C1_CR2_STARTIE (*((volatile unsigned int*)(0x429C0080UL))) +#define bM4_I2C1_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C0084UL))) +#define bM4_I2C1_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C0088UL))) +#define bM4_I2C1_CR2_TENDIE (*((volatile unsigned int*)(0x429C008CUL))) +#define bM4_I2C1_CR2_STOPIE (*((volatile unsigned int*)(0x429C0090UL))) +#define bM4_I2C1_CR2_RFULLIE (*((volatile unsigned int*)(0x429C0098UL))) +#define bM4_I2C1_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C009CUL))) +#define bM4_I2C1_CR2_ARLOIE (*((volatile unsigned int*)(0x429C00A4UL))) +#define bM4_I2C1_CR2_NACKIE (*((volatile unsigned int*)(0x429C00B0UL))) +#define bM4_I2C1_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C00B8UL))) +#define bM4_I2C1_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C00D0UL))) +#define bM4_I2C1_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C00D4UL))) +#define bM4_I2C1_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C00D8UL))) +#define bM4_I2C1_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C00DCUL))) +#define bM4_I2C1_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C0100UL))) +#define bM4_I2C1_CR3_LTMOUT (*((volatile unsigned int*)(0x429C0104UL))) +#define bM4_I2C1_CR3_HTMOUT (*((volatile unsigned int*)(0x429C0108UL))) +#define bM4_I2C1_CR3_FACKEN (*((volatile unsigned int*)(0x429C011CUL))) +#define bM4_I2C1_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C0200UL))) +#define bM4_I2C1_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C0204UL))) +#define bM4_I2C1_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C0208UL))) +#define bM4_I2C1_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C020CUL))) +#define bM4_I2C1_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C0210UL))) +#define bM4_I2C1_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C0214UL))) +#define bM4_I2C1_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C0218UL))) +#define bM4_I2C1_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C021CUL))) +#define bM4_I2C1_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C0220UL))) +#define bM4_I2C1_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C0224UL))) +#define bM4_I2C1_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C0230UL))) +#define bM4_I2C1_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C023CUL))) +#define bM4_I2C1_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C0280UL))) +#define bM4_I2C1_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C0284UL))) +#define bM4_I2C1_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C0288UL))) +#define bM4_I2C1_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C028CUL))) +#define bM4_I2C1_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C0290UL))) +#define bM4_I2C1_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C0294UL))) +#define bM4_I2C1_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C0298UL))) +#define bM4_I2C1_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C029CUL))) +#define bM4_I2C1_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C02A0UL))) +#define bM4_I2C1_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C02A4UL))) +#define bM4_I2C1_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C02B0UL))) +#define bM4_I2C1_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C02BCUL))) +#define bM4_I2C1_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C0300UL))) +#define bM4_I2C1_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C0304UL))) +#define bM4_I2C1_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C0308UL))) +#define bM4_I2C1_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C030CUL))) +#define bM4_I2C1_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C0310UL))) +#define bM4_I2C1_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C0314UL))) +#define bM4_I2C1_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C0318UL))) +#define bM4_I2C1_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C031CUL))) +#define bM4_I2C1_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C0320UL))) +#define bM4_I2C1_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C0324UL))) +#define bM4_I2C1_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C0328UL))) +#define bM4_I2C1_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C032CUL))) +#define bM4_I2C1_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C0330UL))) +#define bM4_I2C1_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C0334UL))) +#define bM4_I2C1_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C0338UL))) +#define bM4_I2C1_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C033CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C0340UL))) +#define bM4_I2C1_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C0344UL))) +#define bM4_I2C1_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C0348UL))) +#define bM4_I2C1_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C034CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C0350UL))) +#define bM4_I2C1_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C0354UL))) +#define bM4_I2C1_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C0358UL))) +#define bM4_I2C1_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C035CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C0360UL))) +#define bM4_I2C1_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C0364UL))) +#define bM4_I2C1_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C0368UL))) +#define bM4_I2C1_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C036CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C0370UL))) +#define bM4_I2C1_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C0374UL))) +#define bM4_I2C1_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C0378UL))) +#define bM4_I2C1_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C037CUL))) +#define bM4_I2C1_SR_STARTF (*((volatile unsigned int*)(0x429C0380UL))) +#define bM4_I2C1_SR_SLADDR0F (*((volatile unsigned int*)(0x429C0384UL))) +#define bM4_I2C1_SR_SLADDR1F (*((volatile unsigned int*)(0x429C0388UL))) +#define bM4_I2C1_SR_TENDF (*((volatile unsigned int*)(0x429C038CUL))) +#define bM4_I2C1_SR_STOPF (*((volatile unsigned int*)(0x429C0390UL))) +#define bM4_I2C1_SR_RFULLF (*((volatile unsigned int*)(0x429C0398UL))) +#define bM4_I2C1_SR_TEMPTYF (*((volatile unsigned int*)(0x429C039CUL))) +#define bM4_I2C1_SR_ARLOF (*((volatile unsigned int*)(0x429C03A4UL))) +#define bM4_I2C1_SR_ACKRF (*((volatile unsigned int*)(0x429C03A8UL))) +#define bM4_I2C1_SR_NACKF (*((volatile unsigned int*)(0x429C03B0UL))) +#define bM4_I2C1_SR_TMOUTF (*((volatile unsigned int*)(0x429C03B8UL))) +#define bM4_I2C1_SR_MSL (*((volatile unsigned int*)(0x429C03C0UL))) +#define bM4_I2C1_SR_BUSY (*((volatile unsigned int*)(0x429C03C4UL))) +#define bM4_I2C1_SR_TRA (*((volatile unsigned int*)(0x429C03C8UL))) +#define bM4_I2C1_SR_GENCALLF (*((volatile unsigned int*)(0x429C03D0UL))) +#define bM4_I2C1_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C03D4UL))) +#define bM4_I2C1_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C03D8UL))) +#define bM4_I2C1_SR_SMBALRTF (*((volatile unsigned int*)(0x429C03DCUL))) +#define bM4_I2C1_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C0400UL))) +#define bM4_I2C1_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C0404UL))) +#define bM4_I2C1_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C0408UL))) +#define bM4_I2C1_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C040CUL))) +#define bM4_I2C1_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C0410UL))) +#define bM4_I2C1_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C0418UL))) +#define bM4_I2C1_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C041CUL))) +#define bM4_I2C1_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C0424UL))) +#define bM4_I2C1_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C0430UL))) +#define bM4_I2C1_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C0438UL))) +#define bM4_I2C1_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C0450UL))) +#define bM4_I2C1_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C0454UL))) +#define bM4_I2C1_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C0458UL))) +#define bM4_I2C1_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C045CUL))) +#define bM4_I2C1_DTR_DT0 (*((volatile unsigned int*)(0x429C0480UL))) +#define bM4_I2C1_DTR_DT1 (*((volatile unsigned int*)(0x429C0484UL))) +#define bM4_I2C1_DTR_DT2 (*((volatile unsigned int*)(0x429C0488UL))) +#define bM4_I2C1_DTR_DT3 (*((volatile unsigned int*)(0x429C048CUL))) +#define bM4_I2C1_DTR_DT4 (*((volatile unsigned int*)(0x429C0490UL))) +#define bM4_I2C1_DTR_DT5 (*((volatile unsigned int*)(0x429C0494UL))) +#define bM4_I2C1_DTR_DT6 (*((volatile unsigned int*)(0x429C0498UL))) +#define bM4_I2C1_DTR_DT7 (*((volatile unsigned int*)(0x429C049CUL))) +#define bM4_I2C1_DRR_DR0 (*((volatile unsigned int*)(0x429C0500UL))) +#define bM4_I2C1_DRR_DR1 (*((volatile unsigned int*)(0x429C0504UL))) +#define bM4_I2C1_DRR_DR2 (*((volatile unsigned int*)(0x429C0508UL))) +#define bM4_I2C1_DRR_DR3 (*((volatile unsigned int*)(0x429C050CUL))) +#define bM4_I2C1_DRR_DR4 (*((volatile unsigned int*)(0x429C0510UL))) +#define bM4_I2C1_DRR_DR5 (*((volatile unsigned int*)(0x429C0514UL))) +#define bM4_I2C1_DRR_DR6 (*((volatile unsigned int*)(0x429C0518UL))) +#define bM4_I2C1_DRR_DR7 (*((volatile unsigned int*)(0x429C051CUL))) +#define bM4_I2C1_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C0580UL))) +#define bM4_I2C1_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C0584UL))) +#define bM4_I2C1_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C0588UL))) +#define bM4_I2C1_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C058CUL))) +#define bM4_I2C1_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C0590UL))) +#define bM4_I2C1_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C05A0UL))) +#define bM4_I2C1_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C05A4UL))) +#define bM4_I2C1_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C05A8UL))) +#define bM4_I2C1_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C05ACUL))) +#define bM4_I2C1_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C05B0UL))) +#define bM4_I2C1_CCR_FREQ0 (*((volatile unsigned int*)(0x429C05C0UL))) +#define bM4_I2C1_CCR_FREQ1 (*((volatile unsigned int*)(0x429C05C4UL))) +#define bM4_I2C1_CCR_FREQ2 (*((volatile unsigned int*)(0x429C05C8UL))) +#define bM4_I2C1_FLTR_DNF0 (*((volatile unsigned int*)(0x429C0600UL))) +#define bM4_I2C1_FLTR_DNF1 (*((volatile unsigned int*)(0x429C0604UL))) +#define bM4_I2C1_FLTR_DNFEN (*((volatile unsigned int*)(0x429C0610UL))) +#define bM4_I2C1_FLTR_ANFEN (*((volatile unsigned int*)(0x429C0614UL))) +#define bM4_I2C2_CR1_PE (*((volatile unsigned int*)(0x429C8000UL))) +#define bM4_I2C2_CR1_SMBUS (*((volatile unsigned int*)(0x429C8004UL))) +#define bM4_I2C2_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C8008UL))) +#define bM4_I2C2_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C800CUL))) +#define bM4_I2C2_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C8010UL))) +#define bM4_I2C2_CR1_ENGC (*((volatile unsigned int*)(0x429C8018UL))) +#define bM4_I2C2_CR1_RESTART (*((volatile unsigned int*)(0x429C801CUL))) +#define bM4_I2C2_CR1_START (*((volatile unsigned int*)(0x429C8020UL))) +#define bM4_I2C2_CR1_STOP (*((volatile unsigned int*)(0x429C8024UL))) +#define bM4_I2C2_CR1_ACK (*((volatile unsigned int*)(0x429C8028UL))) +#define bM4_I2C2_CR1_SWRST (*((volatile unsigned int*)(0x429C803CUL))) +#define bM4_I2C2_CR2_STARTIE (*((volatile unsigned int*)(0x429C8080UL))) +#define bM4_I2C2_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C8084UL))) +#define bM4_I2C2_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C8088UL))) +#define bM4_I2C2_CR2_TENDIE (*((volatile unsigned int*)(0x429C808CUL))) +#define bM4_I2C2_CR2_STOPIE (*((volatile unsigned int*)(0x429C8090UL))) +#define bM4_I2C2_CR2_RFULLIE (*((volatile unsigned int*)(0x429C8098UL))) +#define bM4_I2C2_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C809CUL))) +#define bM4_I2C2_CR2_ARLOIE (*((volatile unsigned int*)(0x429C80A4UL))) +#define bM4_I2C2_CR2_NACKIE (*((volatile unsigned int*)(0x429C80B0UL))) +#define bM4_I2C2_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C80B8UL))) +#define bM4_I2C2_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C80D0UL))) +#define bM4_I2C2_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C80D4UL))) +#define bM4_I2C2_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C80D8UL))) +#define bM4_I2C2_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C80DCUL))) +#define bM4_I2C2_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C8100UL))) +#define bM4_I2C2_CR3_LTMOUT (*((volatile unsigned int*)(0x429C8104UL))) +#define bM4_I2C2_CR3_HTMOUT (*((volatile unsigned int*)(0x429C8108UL))) +#define bM4_I2C2_CR3_FACKEN (*((volatile unsigned int*)(0x429C811CUL))) +#define bM4_I2C2_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C8200UL))) +#define bM4_I2C2_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C8204UL))) +#define bM4_I2C2_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C8208UL))) +#define bM4_I2C2_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C820CUL))) +#define bM4_I2C2_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C8210UL))) +#define bM4_I2C2_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C8214UL))) +#define bM4_I2C2_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C8218UL))) +#define bM4_I2C2_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C821CUL))) +#define bM4_I2C2_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C8220UL))) +#define bM4_I2C2_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C8224UL))) +#define bM4_I2C2_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C8230UL))) +#define bM4_I2C2_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C823CUL))) +#define bM4_I2C2_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C8280UL))) +#define bM4_I2C2_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C8284UL))) +#define bM4_I2C2_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C8288UL))) +#define bM4_I2C2_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C828CUL))) +#define bM4_I2C2_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C8290UL))) +#define bM4_I2C2_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C8294UL))) +#define bM4_I2C2_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C8298UL))) +#define bM4_I2C2_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C829CUL))) +#define bM4_I2C2_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C82A0UL))) +#define bM4_I2C2_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C82A4UL))) +#define bM4_I2C2_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C82B0UL))) +#define bM4_I2C2_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C82BCUL))) +#define bM4_I2C2_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C8300UL))) +#define bM4_I2C2_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C8304UL))) +#define bM4_I2C2_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C8308UL))) +#define bM4_I2C2_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C830CUL))) +#define bM4_I2C2_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C8310UL))) +#define bM4_I2C2_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C8314UL))) +#define bM4_I2C2_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C8318UL))) +#define bM4_I2C2_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C831CUL))) +#define bM4_I2C2_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C8320UL))) +#define bM4_I2C2_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C8324UL))) +#define bM4_I2C2_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C8328UL))) +#define bM4_I2C2_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C832CUL))) +#define bM4_I2C2_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C8330UL))) +#define bM4_I2C2_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C8334UL))) +#define bM4_I2C2_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C8338UL))) +#define bM4_I2C2_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C833CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C8340UL))) +#define bM4_I2C2_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C8344UL))) +#define bM4_I2C2_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C8348UL))) +#define bM4_I2C2_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C834CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C8350UL))) +#define bM4_I2C2_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C8354UL))) +#define bM4_I2C2_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C8358UL))) +#define bM4_I2C2_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C835CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C8360UL))) +#define bM4_I2C2_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C8364UL))) +#define bM4_I2C2_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C8368UL))) +#define bM4_I2C2_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C836CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C8370UL))) +#define bM4_I2C2_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C8374UL))) +#define bM4_I2C2_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C8378UL))) +#define bM4_I2C2_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C837CUL))) +#define bM4_I2C2_SR_STARTF (*((volatile unsigned int*)(0x429C8380UL))) +#define bM4_I2C2_SR_SLADDR0F (*((volatile unsigned int*)(0x429C8384UL))) +#define bM4_I2C2_SR_SLADDR1F (*((volatile unsigned int*)(0x429C8388UL))) +#define bM4_I2C2_SR_TENDF (*((volatile unsigned int*)(0x429C838CUL))) +#define bM4_I2C2_SR_STOPF (*((volatile unsigned int*)(0x429C8390UL))) +#define bM4_I2C2_SR_RFULLF (*((volatile unsigned int*)(0x429C8398UL))) +#define bM4_I2C2_SR_TEMPTYF (*((volatile unsigned int*)(0x429C839CUL))) +#define bM4_I2C2_SR_ARLOF (*((volatile unsigned int*)(0x429C83A4UL))) +#define bM4_I2C2_SR_ACKRF (*((volatile unsigned int*)(0x429C83A8UL))) +#define bM4_I2C2_SR_NACKF (*((volatile unsigned int*)(0x429C83B0UL))) +#define bM4_I2C2_SR_TMOUTF (*((volatile unsigned int*)(0x429C83B8UL))) +#define bM4_I2C2_SR_MSL (*((volatile unsigned int*)(0x429C83C0UL))) +#define bM4_I2C2_SR_BUSY (*((volatile unsigned int*)(0x429C83C4UL))) +#define bM4_I2C2_SR_TRA (*((volatile unsigned int*)(0x429C83C8UL))) +#define bM4_I2C2_SR_GENCALLF (*((volatile unsigned int*)(0x429C83D0UL))) +#define bM4_I2C2_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C83D4UL))) +#define bM4_I2C2_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C83D8UL))) +#define bM4_I2C2_SR_SMBALRTF (*((volatile unsigned int*)(0x429C83DCUL))) +#define bM4_I2C2_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C8400UL))) +#define bM4_I2C2_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C8404UL))) +#define bM4_I2C2_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C8408UL))) +#define bM4_I2C2_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C840CUL))) +#define bM4_I2C2_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C8410UL))) +#define bM4_I2C2_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C8418UL))) +#define bM4_I2C2_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C841CUL))) +#define bM4_I2C2_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C8424UL))) +#define bM4_I2C2_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C8430UL))) +#define bM4_I2C2_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C8438UL))) +#define bM4_I2C2_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C8450UL))) +#define bM4_I2C2_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C8454UL))) +#define bM4_I2C2_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C8458UL))) +#define bM4_I2C2_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C845CUL))) +#define bM4_I2C2_DTR_DT0 (*((volatile unsigned int*)(0x429C8480UL))) +#define bM4_I2C2_DTR_DT1 (*((volatile unsigned int*)(0x429C8484UL))) +#define bM4_I2C2_DTR_DT2 (*((volatile unsigned int*)(0x429C8488UL))) +#define bM4_I2C2_DTR_DT3 (*((volatile unsigned int*)(0x429C848CUL))) +#define bM4_I2C2_DTR_DT4 (*((volatile unsigned int*)(0x429C8490UL))) +#define bM4_I2C2_DTR_DT5 (*((volatile unsigned int*)(0x429C8494UL))) +#define bM4_I2C2_DTR_DT6 (*((volatile unsigned int*)(0x429C8498UL))) +#define bM4_I2C2_DTR_DT7 (*((volatile unsigned int*)(0x429C849CUL))) +#define bM4_I2C2_DRR_DR0 (*((volatile unsigned int*)(0x429C8500UL))) +#define bM4_I2C2_DRR_DR1 (*((volatile unsigned int*)(0x429C8504UL))) +#define bM4_I2C2_DRR_DR2 (*((volatile unsigned int*)(0x429C8508UL))) +#define bM4_I2C2_DRR_DR3 (*((volatile unsigned int*)(0x429C850CUL))) +#define bM4_I2C2_DRR_DR4 (*((volatile unsigned int*)(0x429C8510UL))) +#define bM4_I2C2_DRR_DR5 (*((volatile unsigned int*)(0x429C8514UL))) +#define bM4_I2C2_DRR_DR6 (*((volatile unsigned int*)(0x429C8518UL))) +#define bM4_I2C2_DRR_DR7 (*((volatile unsigned int*)(0x429C851CUL))) +#define bM4_I2C2_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C8580UL))) +#define bM4_I2C2_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C8584UL))) +#define bM4_I2C2_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C8588UL))) +#define bM4_I2C2_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C858CUL))) +#define bM4_I2C2_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C8590UL))) +#define bM4_I2C2_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C85A0UL))) +#define bM4_I2C2_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C85A4UL))) +#define bM4_I2C2_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C85A8UL))) +#define bM4_I2C2_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C85ACUL))) +#define bM4_I2C2_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C85B0UL))) +#define bM4_I2C2_CCR_FREQ0 (*((volatile unsigned int*)(0x429C85C0UL))) +#define bM4_I2C2_CCR_FREQ1 (*((volatile unsigned int*)(0x429C85C4UL))) +#define bM4_I2C2_CCR_FREQ2 (*((volatile unsigned int*)(0x429C85C8UL))) +#define bM4_I2C2_FLTR_DNF0 (*((volatile unsigned int*)(0x429C8600UL))) +#define bM4_I2C2_FLTR_DNF1 (*((volatile unsigned int*)(0x429C8604UL))) +#define bM4_I2C2_FLTR_DNFEN (*((volatile unsigned int*)(0x429C8610UL))) +#define bM4_I2C2_FLTR_ANFEN (*((volatile unsigned int*)(0x429C8614UL))) +#define bM4_I2C3_CR1_PE (*((volatile unsigned int*)(0x429D0000UL))) +#define bM4_I2C3_CR1_SMBUS (*((volatile unsigned int*)(0x429D0004UL))) +#define bM4_I2C3_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429D0008UL))) +#define bM4_I2C3_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429D000CUL))) +#define bM4_I2C3_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429D0010UL))) +#define bM4_I2C3_CR1_ENGC (*((volatile unsigned int*)(0x429D0018UL))) +#define bM4_I2C3_CR1_RESTART (*((volatile unsigned int*)(0x429D001CUL))) +#define bM4_I2C3_CR1_START (*((volatile unsigned int*)(0x429D0020UL))) +#define bM4_I2C3_CR1_STOP (*((volatile unsigned int*)(0x429D0024UL))) +#define bM4_I2C3_CR1_ACK (*((volatile unsigned int*)(0x429D0028UL))) +#define bM4_I2C3_CR1_SWRST (*((volatile unsigned int*)(0x429D003CUL))) +#define bM4_I2C3_CR2_STARTIE (*((volatile unsigned int*)(0x429D0080UL))) +#define bM4_I2C3_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429D0084UL))) +#define bM4_I2C3_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429D0088UL))) +#define bM4_I2C3_CR2_TENDIE (*((volatile unsigned int*)(0x429D008CUL))) +#define bM4_I2C3_CR2_STOPIE (*((volatile unsigned int*)(0x429D0090UL))) +#define bM4_I2C3_CR2_RFULLIE (*((volatile unsigned int*)(0x429D0098UL))) +#define bM4_I2C3_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429D009CUL))) +#define bM4_I2C3_CR2_ARLOIE (*((volatile unsigned int*)(0x429D00A4UL))) +#define bM4_I2C3_CR2_NACKIE (*((volatile unsigned int*)(0x429D00B0UL))) +#define bM4_I2C3_CR2_TMOUTIE (*((volatile unsigned int*)(0x429D00B8UL))) +#define bM4_I2C3_CR2_GENCALLIE (*((volatile unsigned int*)(0x429D00D0UL))) +#define bM4_I2C3_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429D00D4UL))) +#define bM4_I2C3_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429D00D8UL))) +#define bM4_I2C3_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429D00DCUL))) +#define bM4_I2C3_CR3_TMOUTEN (*((volatile unsigned int*)(0x429D0100UL))) +#define bM4_I2C3_CR3_LTMOUT (*((volatile unsigned int*)(0x429D0104UL))) +#define bM4_I2C3_CR3_HTMOUT (*((volatile unsigned int*)(0x429D0108UL))) +#define bM4_I2C3_CR3_FACKEN (*((volatile unsigned int*)(0x429D011CUL))) +#define bM4_I2C3_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429D0200UL))) +#define bM4_I2C3_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429D0204UL))) +#define bM4_I2C3_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429D0208UL))) +#define bM4_I2C3_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429D020CUL))) +#define bM4_I2C3_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429D0210UL))) +#define bM4_I2C3_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429D0214UL))) +#define bM4_I2C3_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429D0218UL))) +#define bM4_I2C3_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429D021CUL))) +#define bM4_I2C3_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429D0220UL))) +#define bM4_I2C3_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429D0224UL))) +#define bM4_I2C3_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429D0230UL))) +#define bM4_I2C3_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429D023CUL))) +#define bM4_I2C3_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429D0280UL))) +#define bM4_I2C3_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429D0284UL))) +#define bM4_I2C3_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429D0288UL))) +#define bM4_I2C3_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429D028CUL))) +#define bM4_I2C3_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429D0290UL))) +#define bM4_I2C3_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429D0294UL))) +#define bM4_I2C3_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429D0298UL))) +#define bM4_I2C3_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429D029CUL))) +#define bM4_I2C3_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429D02A0UL))) +#define bM4_I2C3_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429D02A4UL))) +#define bM4_I2C3_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429D02B0UL))) +#define bM4_I2C3_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429D02BCUL))) +#define bM4_I2C3_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429D0300UL))) +#define bM4_I2C3_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429D0304UL))) +#define bM4_I2C3_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429D0308UL))) +#define bM4_I2C3_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429D030CUL))) +#define bM4_I2C3_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429D0310UL))) +#define bM4_I2C3_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429D0314UL))) +#define bM4_I2C3_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429D0318UL))) +#define bM4_I2C3_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429D031CUL))) +#define bM4_I2C3_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429D0320UL))) +#define bM4_I2C3_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429D0324UL))) +#define bM4_I2C3_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429D0328UL))) +#define bM4_I2C3_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429D032CUL))) +#define bM4_I2C3_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429D0330UL))) +#define bM4_I2C3_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429D0334UL))) +#define bM4_I2C3_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429D0338UL))) +#define bM4_I2C3_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429D033CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429D0340UL))) +#define bM4_I2C3_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429D0344UL))) +#define bM4_I2C3_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429D0348UL))) +#define bM4_I2C3_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429D034CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429D0350UL))) +#define bM4_I2C3_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429D0354UL))) +#define bM4_I2C3_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429D0358UL))) +#define bM4_I2C3_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429D035CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429D0360UL))) +#define bM4_I2C3_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429D0364UL))) +#define bM4_I2C3_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429D0368UL))) +#define bM4_I2C3_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429D036CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429D0370UL))) +#define bM4_I2C3_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429D0374UL))) +#define bM4_I2C3_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429D0378UL))) +#define bM4_I2C3_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429D037CUL))) +#define bM4_I2C3_SR_STARTF (*((volatile unsigned int*)(0x429D0380UL))) +#define bM4_I2C3_SR_SLADDR0F (*((volatile unsigned int*)(0x429D0384UL))) +#define bM4_I2C3_SR_SLADDR1F (*((volatile unsigned int*)(0x429D0388UL))) +#define bM4_I2C3_SR_TENDF (*((volatile unsigned int*)(0x429D038CUL))) +#define bM4_I2C3_SR_STOPF (*((volatile unsigned int*)(0x429D0390UL))) +#define bM4_I2C3_SR_RFULLF (*((volatile unsigned int*)(0x429D0398UL))) +#define bM4_I2C3_SR_TEMPTYF (*((volatile unsigned int*)(0x429D039CUL))) +#define bM4_I2C3_SR_ARLOF (*((volatile unsigned int*)(0x429D03A4UL))) +#define bM4_I2C3_SR_ACKRF (*((volatile unsigned int*)(0x429D03A8UL))) +#define bM4_I2C3_SR_NACKF (*((volatile unsigned int*)(0x429D03B0UL))) +#define bM4_I2C3_SR_TMOUTF (*((volatile unsigned int*)(0x429D03B8UL))) +#define bM4_I2C3_SR_MSL (*((volatile unsigned int*)(0x429D03C0UL))) +#define bM4_I2C3_SR_BUSY (*((volatile unsigned int*)(0x429D03C4UL))) +#define bM4_I2C3_SR_TRA (*((volatile unsigned int*)(0x429D03C8UL))) +#define bM4_I2C3_SR_GENCALLF (*((volatile unsigned int*)(0x429D03D0UL))) +#define bM4_I2C3_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429D03D4UL))) +#define bM4_I2C3_SR_SMBHOSTF (*((volatile unsigned int*)(0x429D03D8UL))) +#define bM4_I2C3_SR_SMBALRTF (*((volatile unsigned int*)(0x429D03DCUL))) +#define bM4_I2C3_CLR_STARTFCLR (*((volatile unsigned int*)(0x429D0400UL))) +#define bM4_I2C3_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429D0404UL))) +#define bM4_I2C3_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429D0408UL))) +#define bM4_I2C3_CLR_TENDFCLR (*((volatile unsigned int*)(0x429D040CUL))) +#define bM4_I2C3_CLR_STOPFCLR (*((volatile unsigned int*)(0x429D0410UL))) +#define bM4_I2C3_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429D0418UL))) +#define bM4_I2C3_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429D041CUL))) +#define bM4_I2C3_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429D0424UL))) +#define bM4_I2C3_CLR_NACKFCLR (*((volatile unsigned int*)(0x429D0430UL))) +#define bM4_I2C3_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429D0438UL))) +#define bM4_I2C3_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429D0450UL))) +#define bM4_I2C3_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429D0454UL))) +#define bM4_I2C3_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429D0458UL))) +#define bM4_I2C3_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429D045CUL))) +#define bM4_I2C3_DTR_DT0 (*((volatile unsigned int*)(0x429D0480UL))) +#define bM4_I2C3_DTR_DT1 (*((volatile unsigned int*)(0x429D0484UL))) +#define bM4_I2C3_DTR_DT2 (*((volatile unsigned int*)(0x429D0488UL))) +#define bM4_I2C3_DTR_DT3 (*((volatile unsigned int*)(0x429D048CUL))) +#define bM4_I2C3_DTR_DT4 (*((volatile unsigned int*)(0x429D0490UL))) +#define bM4_I2C3_DTR_DT5 (*((volatile unsigned int*)(0x429D0494UL))) +#define bM4_I2C3_DTR_DT6 (*((volatile unsigned int*)(0x429D0498UL))) +#define bM4_I2C3_DTR_DT7 (*((volatile unsigned int*)(0x429D049CUL))) +#define bM4_I2C3_DRR_DR0 (*((volatile unsigned int*)(0x429D0500UL))) +#define bM4_I2C3_DRR_DR1 (*((volatile unsigned int*)(0x429D0504UL))) +#define bM4_I2C3_DRR_DR2 (*((volatile unsigned int*)(0x429D0508UL))) +#define bM4_I2C3_DRR_DR3 (*((volatile unsigned int*)(0x429D050CUL))) +#define bM4_I2C3_DRR_DR4 (*((volatile unsigned int*)(0x429D0510UL))) +#define bM4_I2C3_DRR_DR5 (*((volatile unsigned int*)(0x429D0514UL))) +#define bM4_I2C3_DRR_DR6 (*((volatile unsigned int*)(0x429D0518UL))) +#define bM4_I2C3_DRR_DR7 (*((volatile unsigned int*)(0x429D051CUL))) +#define bM4_I2C3_CCR_SLOWW0 (*((volatile unsigned int*)(0x429D0580UL))) +#define bM4_I2C3_CCR_SLOWW1 (*((volatile unsigned int*)(0x429D0584UL))) +#define bM4_I2C3_CCR_SLOWW2 (*((volatile unsigned int*)(0x429D0588UL))) +#define bM4_I2C3_CCR_SLOWW3 (*((volatile unsigned int*)(0x429D058CUL))) +#define bM4_I2C3_CCR_SLOWW4 (*((volatile unsigned int*)(0x429D0590UL))) +#define bM4_I2C3_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429D05A0UL))) +#define bM4_I2C3_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429D05A4UL))) +#define bM4_I2C3_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429D05A8UL))) +#define bM4_I2C3_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429D05ACUL))) +#define bM4_I2C3_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429D05B0UL))) +#define bM4_I2C3_CCR_FREQ0 (*((volatile unsigned int*)(0x429D05C0UL))) +#define bM4_I2C3_CCR_FREQ1 (*((volatile unsigned int*)(0x429D05C4UL))) +#define bM4_I2C3_CCR_FREQ2 (*((volatile unsigned int*)(0x429D05C8UL))) +#define bM4_I2C3_FLTR_DNF0 (*((volatile unsigned int*)(0x429D0600UL))) +#define bM4_I2C3_FLTR_DNF1 (*((volatile unsigned int*)(0x429D0604UL))) +#define bM4_I2C3_FLTR_DNFEN (*((volatile unsigned int*)(0x429D0610UL))) +#define bM4_I2C3_FLTR_ANFEN (*((volatile unsigned int*)(0x429D0614UL))) +#define bM4_I2S1_CTRL_TXE (*((volatile unsigned int*)(0x423C0000UL))) +#define bM4_I2S1_CTRL_TXIE (*((volatile unsigned int*)(0x423C0004UL))) +#define bM4_I2S1_CTRL_RXE (*((volatile unsigned int*)(0x423C0008UL))) +#define bM4_I2S1_CTRL_RXIE (*((volatile unsigned int*)(0x423C000CUL))) +#define bM4_I2S1_CTRL_EIE (*((volatile unsigned int*)(0x423C0010UL))) +#define bM4_I2S1_CTRL_WMS (*((volatile unsigned int*)(0x423C0014UL))) +#define bM4_I2S1_CTRL_ODD (*((volatile unsigned int*)(0x423C0018UL))) +#define bM4_I2S1_CTRL_MCKOE (*((volatile unsigned int*)(0x423C001CUL))) +#define bM4_I2S1_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C0020UL))) +#define bM4_I2S1_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C0024UL))) +#define bM4_I2S1_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C0028UL))) +#define bM4_I2S1_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C0030UL))) +#define bM4_I2S1_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C0034UL))) +#define bM4_I2S1_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C0038UL))) +#define bM4_I2S1_CTRL_FIFOR (*((volatile unsigned int*)(0x423C0040UL))) +#define bM4_I2S1_CTRL_CODECRC (*((volatile unsigned int*)(0x423C0044UL))) +#define bM4_I2S1_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C0048UL))) +#define bM4_I2S1_CTRL_SDOE (*((volatile unsigned int*)(0x423C004CUL))) +#define bM4_I2S1_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C0050UL))) +#define bM4_I2S1_CTRL_CKOE (*((volatile unsigned int*)(0x423C0054UL))) +#define bM4_I2S1_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C0058UL))) +#define bM4_I2S1_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C005CUL))) +#define bM4_I2S1_SR_TXBA (*((volatile unsigned int*)(0x423C0080UL))) +#define bM4_I2S1_SR_RXBA (*((volatile unsigned int*)(0x423C0084UL))) +#define bM4_I2S1_SR_TXBE (*((volatile unsigned int*)(0x423C0088UL))) +#define bM4_I2S1_SR_TXBF (*((volatile unsigned int*)(0x423C008CUL))) +#define bM4_I2S1_SR_RXBE (*((volatile unsigned int*)(0x423C0090UL))) +#define bM4_I2S1_SR_RXBF (*((volatile unsigned int*)(0x423C0094UL))) +#define bM4_I2S1_ER_TXERR (*((volatile unsigned int*)(0x423C0100UL))) +#define bM4_I2S1_ER_RXERR (*((volatile unsigned int*)(0x423C0104UL))) +#define bM4_I2S1_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C0180UL))) +#define bM4_I2S1_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C0184UL))) +#define bM4_I2S1_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C0188UL))) +#define bM4_I2S1_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C018CUL))) +#define bM4_I2S1_CFGR_CHLEN (*((volatile unsigned int*)(0x423C0190UL))) +#define bM4_I2S1_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C0194UL))) +#define bM4_I2S1_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C0300UL))) +#define bM4_I2S1_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C0304UL))) +#define bM4_I2S1_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C0308UL))) +#define bM4_I2S1_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C030CUL))) +#define bM4_I2S1_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C0310UL))) +#define bM4_I2S1_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C0314UL))) +#define bM4_I2S1_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C0318UL))) +#define bM4_I2S1_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C031CUL))) +#define bM4_I2S2_CTRL_TXE (*((volatile unsigned int*)(0x423C8000UL))) +#define bM4_I2S2_CTRL_TXIE (*((volatile unsigned int*)(0x423C8004UL))) +#define bM4_I2S2_CTRL_RXE (*((volatile unsigned int*)(0x423C8008UL))) +#define bM4_I2S2_CTRL_RXIE (*((volatile unsigned int*)(0x423C800CUL))) +#define bM4_I2S2_CTRL_EIE (*((volatile unsigned int*)(0x423C8010UL))) +#define bM4_I2S2_CTRL_WMS (*((volatile unsigned int*)(0x423C8014UL))) +#define bM4_I2S2_CTRL_ODD (*((volatile unsigned int*)(0x423C8018UL))) +#define bM4_I2S2_CTRL_MCKOE (*((volatile unsigned int*)(0x423C801CUL))) +#define bM4_I2S2_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C8020UL))) +#define bM4_I2S2_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C8024UL))) +#define bM4_I2S2_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C8028UL))) +#define bM4_I2S2_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C8030UL))) +#define bM4_I2S2_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C8034UL))) +#define bM4_I2S2_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C8038UL))) +#define bM4_I2S2_CTRL_FIFOR (*((volatile unsigned int*)(0x423C8040UL))) +#define bM4_I2S2_CTRL_CODECRC (*((volatile unsigned int*)(0x423C8044UL))) +#define bM4_I2S2_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C8048UL))) +#define bM4_I2S2_CTRL_SDOE (*((volatile unsigned int*)(0x423C804CUL))) +#define bM4_I2S2_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C8050UL))) +#define bM4_I2S2_CTRL_CKOE (*((volatile unsigned int*)(0x423C8054UL))) +#define bM4_I2S2_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C8058UL))) +#define bM4_I2S2_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C805CUL))) +#define bM4_I2S2_SR_TXBA (*((volatile unsigned int*)(0x423C8080UL))) +#define bM4_I2S2_SR_RXBA (*((volatile unsigned int*)(0x423C8084UL))) +#define bM4_I2S2_SR_TXBE (*((volatile unsigned int*)(0x423C8088UL))) +#define bM4_I2S2_SR_TXBF (*((volatile unsigned int*)(0x423C808CUL))) +#define bM4_I2S2_SR_RXBE (*((volatile unsigned int*)(0x423C8090UL))) +#define bM4_I2S2_SR_RXBF (*((volatile unsigned int*)(0x423C8094UL))) +#define bM4_I2S2_ER_TXERR (*((volatile unsigned int*)(0x423C8100UL))) +#define bM4_I2S2_ER_RXERR (*((volatile unsigned int*)(0x423C8104UL))) +#define bM4_I2S2_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C8180UL))) +#define bM4_I2S2_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C8184UL))) +#define bM4_I2S2_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C8188UL))) +#define bM4_I2S2_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C818CUL))) +#define bM4_I2S2_CFGR_CHLEN (*((volatile unsigned int*)(0x423C8190UL))) +#define bM4_I2S2_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C8194UL))) +#define bM4_I2S2_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C8300UL))) +#define bM4_I2S2_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C8304UL))) +#define bM4_I2S2_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C8308UL))) +#define bM4_I2S2_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C830CUL))) +#define bM4_I2S2_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C8310UL))) +#define bM4_I2S2_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C8314UL))) +#define bM4_I2S2_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C8318UL))) +#define bM4_I2S2_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C831CUL))) +#define bM4_I2S3_CTRL_TXE (*((volatile unsigned int*)(0x42440000UL))) +#define bM4_I2S3_CTRL_TXIE (*((volatile unsigned int*)(0x42440004UL))) +#define bM4_I2S3_CTRL_RXE (*((volatile unsigned int*)(0x42440008UL))) +#define bM4_I2S3_CTRL_RXIE (*((volatile unsigned int*)(0x4244000CUL))) +#define bM4_I2S3_CTRL_EIE (*((volatile unsigned int*)(0x42440010UL))) +#define bM4_I2S3_CTRL_WMS (*((volatile unsigned int*)(0x42440014UL))) +#define bM4_I2S3_CTRL_ODD (*((volatile unsigned int*)(0x42440018UL))) +#define bM4_I2S3_CTRL_MCKOE (*((volatile unsigned int*)(0x4244001CUL))) +#define bM4_I2S3_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42440020UL))) +#define bM4_I2S3_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42440024UL))) +#define bM4_I2S3_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42440028UL))) +#define bM4_I2S3_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42440030UL))) +#define bM4_I2S3_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42440034UL))) +#define bM4_I2S3_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42440038UL))) +#define bM4_I2S3_CTRL_FIFOR (*((volatile unsigned int*)(0x42440040UL))) +#define bM4_I2S3_CTRL_CODECRC (*((volatile unsigned int*)(0x42440044UL))) +#define bM4_I2S3_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42440048UL))) +#define bM4_I2S3_CTRL_SDOE (*((volatile unsigned int*)(0x4244004CUL))) +#define bM4_I2S3_CTRL_LRCKOE (*((volatile unsigned int*)(0x42440050UL))) +#define bM4_I2S3_CTRL_CKOE (*((volatile unsigned int*)(0x42440054UL))) +#define bM4_I2S3_CTRL_DUPLEX (*((volatile unsigned int*)(0x42440058UL))) +#define bM4_I2S3_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244005CUL))) +#define bM4_I2S3_SR_TXBA (*((volatile unsigned int*)(0x42440080UL))) +#define bM4_I2S3_SR_RXBA (*((volatile unsigned int*)(0x42440084UL))) +#define bM4_I2S3_SR_TXBE (*((volatile unsigned int*)(0x42440088UL))) +#define bM4_I2S3_SR_TXBF (*((volatile unsigned int*)(0x4244008CUL))) +#define bM4_I2S3_SR_RXBE (*((volatile unsigned int*)(0x42440090UL))) +#define bM4_I2S3_SR_RXBF (*((volatile unsigned int*)(0x42440094UL))) +#define bM4_I2S3_ER_TXERR (*((volatile unsigned int*)(0x42440100UL))) +#define bM4_I2S3_ER_RXERR (*((volatile unsigned int*)(0x42440104UL))) +#define bM4_I2S3_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42440180UL))) +#define bM4_I2S3_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42440184UL))) +#define bM4_I2S3_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42440188UL))) +#define bM4_I2S3_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244018CUL))) +#define bM4_I2S3_CFGR_CHLEN (*((volatile unsigned int*)(0x42440190UL))) +#define bM4_I2S3_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42440194UL))) +#define bM4_I2S3_PR_I2SDIV0 (*((volatile unsigned int*)(0x42440300UL))) +#define bM4_I2S3_PR_I2SDIV1 (*((volatile unsigned int*)(0x42440304UL))) +#define bM4_I2S3_PR_I2SDIV2 (*((volatile unsigned int*)(0x42440308UL))) +#define bM4_I2S3_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244030CUL))) +#define bM4_I2S3_PR_I2SDIV4 (*((volatile unsigned int*)(0x42440310UL))) +#define bM4_I2S3_PR_I2SDIV5 (*((volatile unsigned int*)(0x42440314UL))) +#define bM4_I2S3_PR_I2SDIV6 (*((volatile unsigned int*)(0x42440318UL))) +#define bM4_I2S3_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244031CUL))) +#define bM4_I2S4_CTRL_TXE (*((volatile unsigned int*)(0x42448000UL))) +#define bM4_I2S4_CTRL_TXIE (*((volatile unsigned int*)(0x42448004UL))) +#define bM4_I2S4_CTRL_RXE (*((volatile unsigned int*)(0x42448008UL))) +#define bM4_I2S4_CTRL_RXIE (*((volatile unsigned int*)(0x4244800CUL))) +#define bM4_I2S4_CTRL_EIE (*((volatile unsigned int*)(0x42448010UL))) +#define bM4_I2S4_CTRL_WMS (*((volatile unsigned int*)(0x42448014UL))) +#define bM4_I2S4_CTRL_ODD (*((volatile unsigned int*)(0x42448018UL))) +#define bM4_I2S4_CTRL_MCKOE (*((volatile unsigned int*)(0x4244801CUL))) +#define bM4_I2S4_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42448020UL))) +#define bM4_I2S4_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42448024UL))) +#define bM4_I2S4_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42448028UL))) +#define bM4_I2S4_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42448030UL))) +#define bM4_I2S4_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42448034UL))) +#define bM4_I2S4_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42448038UL))) +#define bM4_I2S4_CTRL_FIFOR (*((volatile unsigned int*)(0x42448040UL))) +#define bM4_I2S4_CTRL_CODECRC (*((volatile unsigned int*)(0x42448044UL))) +#define bM4_I2S4_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42448048UL))) +#define bM4_I2S4_CTRL_SDOE (*((volatile unsigned int*)(0x4244804CUL))) +#define bM4_I2S4_CTRL_LRCKOE (*((volatile unsigned int*)(0x42448050UL))) +#define bM4_I2S4_CTRL_CKOE (*((volatile unsigned int*)(0x42448054UL))) +#define bM4_I2S4_CTRL_DUPLEX (*((volatile unsigned int*)(0x42448058UL))) +#define bM4_I2S4_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244805CUL))) +#define bM4_I2S4_SR_TXBA (*((volatile unsigned int*)(0x42448080UL))) +#define bM4_I2S4_SR_RXBA (*((volatile unsigned int*)(0x42448084UL))) +#define bM4_I2S4_SR_TXBE (*((volatile unsigned int*)(0x42448088UL))) +#define bM4_I2S4_SR_TXBF (*((volatile unsigned int*)(0x4244808CUL))) +#define bM4_I2S4_SR_RXBE (*((volatile unsigned int*)(0x42448090UL))) +#define bM4_I2S4_SR_RXBF (*((volatile unsigned int*)(0x42448094UL))) +#define bM4_I2S4_ER_TXERR (*((volatile unsigned int*)(0x42448100UL))) +#define bM4_I2S4_ER_RXERR (*((volatile unsigned int*)(0x42448104UL))) +#define bM4_I2S4_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42448180UL))) +#define bM4_I2S4_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42448184UL))) +#define bM4_I2S4_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42448188UL))) +#define bM4_I2S4_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244818CUL))) +#define bM4_I2S4_CFGR_CHLEN (*((volatile unsigned int*)(0x42448190UL))) +#define bM4_I2S4_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42448194UL))) +#define bM4_I2S4_PR_I2SDIV0 (*((volatile unsigned int*)(0x42448300UL))) +#define bM4_I2S4_PR_I2SDIV1 (*((volatile unsigned int*)(0x42448304UL))) +#define bM4_I2S4_PR_I2SDIV2 (*((volatile unsigned int*)(0x42448308UL))) +#define bM4_I2S4_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244830CUL))) +#define bM4_I2S4_PR_I2SDIV4 (*((volatile unsigned int*)(0x42448310UL))) +#define bM4_I2S4_PR_I2SDIV5 (*((volatile unsigned int*)(0x42448314UL))) +#define bM4_I2S4_PR_I2SDIV6 (*((volatile unsigned int*)(0x42448318UL))) +#define bM4_I2S4_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244831CUL))) +#define bM4_INTC_NMICR_NMITRG (*((volatile unsigned int*)(0x42A20000UL))) +#define bM4_INTC_NMICR_NSMPCLK0 (*((volatile unsigned int*)(0x42A20010UL))) +#define bM4_INTC_NMICR_NSMPCLK1 (*((volatile unsigned int*)(0x42A20014UL))) +#define bM4_INTC_NMICR_NFEN (*((volatile unsigned int*)(0x42A2001CUL))) +#define bM4_INTC_NMIENR_NMIENR (*((volatile unsigned int*)(0x42A20080UL))) +#define bM4_INTC_NMIENR_SWDTENR (*((volatile unsigned int*)(0x42A20084UL))) +#define bM4_INTC_NMIENR_PVD1ENR (*((volatile unsigned int*)(0x42A20088UL))) +#define bM4_INTC_NMIENR_PVD2ENR (*((volatile unsigned int*)(0x42A2008CUL))) +#define bM4_INTC_NMIENR_XTALSTPENR (*((volatile unsigned int*)(0x42A20094UL))) +#define bM4_INTC_NMIENR_REPENR (*((volatile unsigned int*)(0x42A200A0UL))) +#define bM4_INTC_NMIENR_RECCENR (*((volatile unsigned int*)(0x42A200A4UL))) +#define bM4_INTC_NMIENR_BUSMENR (*((volatile unsigned int*)(0x42A200A8UL))) +#define bM4_INTC_NMIENR_WDTENR (*((volatile unsigned int*)(0x42A200ACUL))) +#define bM4_INTC_NMIFR_NMIFR (*((volatile unsigned int*)(0x42A20100UL))) +#define bM4_INTC_NMIFR_SWDTFR (*((volatile unsigned int*)(0x42A20104UL))) +#define bM4_INTC_NMIFR_PVD1FR (*((volatile unsigned int*)(0x42A20108UL))) +#define bM4_INTC_NMIFR_PVD2FR (*((volatile unsigned int*)(0x42A2010CUL))) +#define bM4_INTC_NMIFR_XTALSTPFR (*((volatile unsigned int*)(0x42A20114UL))) +#define bM4_INTC_NMIFR_REPFR (*((volatile unsigned int*)(0x42A20120UL))) +#define bM4_INTC_NMIFR_RECCFR (*((volatile unsigned int*)(0x42A20124UL))) +#define bM4_INTC_NMIFR_BUSMFR (*((volatile unsigned int*)(0x42A20128UL))) +#define bM4_INTC_NMIFR_WDTFR (*((volatile unsigned int*)(0x42A2012CUL))) +#define bM4_INTC_NMICFR_NMICFR (*((volatile unsigned int*)(0x42A20180UL))) +#define bM4_INTC_NMICFR_SWDTCFR (*((volatile unsigned int*)(0x42A20184UL))) +#define bM4_INTC_NMICFR_PVD1CFR (*((volatile unsigned int*)(0x42A20188UL))) +#define bM4_INTC_NMICFR_PVD2CFR (*((volatile unsigned int*)(0x42A2018CUL))) +#define bM4_INTC_NMICFR_XTALSTPCFR (*((volatile unsigned int*)(0x42A20194UL))) +#define bM4_INTC_NMICFR_REPCFR (*((volatile unsigned int*)(0x42A201A0UL))) +#define bM4_INTC_NMICFR_RECCCFR (*((volatile unsigned int*)(0x42A201A4UL))) +#define bM4_INTC_NMICFR_BUSMCFR (*((volatile unsigned int*)(0x42A201A8UL))) +#define bM4_INTC_NMICFR_WDTCFR (*((volatile unsigned int*)(0x42A201ACUL))) +#define bM4_INTC_EIRQCR0_EIRQTRG0 (*((volatile unsigned int*)(0x42A20200UL))) +#define bM4_INTC_EIRQCR0_EIRQTRG1 (*((volatile unsigned int*)(0x42A20204UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK0 (*((volatile unsigned int*)(0x42A20210UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK1 (*((volatile unsigned int*)(0x42A20214UL))) +#define bM4_INTC_EIRQCR0_EFEN (*((volatile unsigned int*)(0x42A2021CUL))) +#define bM4_INTC_EIRQCR1_EIRQTRG0 (*((volatile unsigned int*)(0x42A20280UL))) +#define bM4_INTC_EIRQCR1_EIRQTRG1 (*((volatile unsigned int*)(0x42A20284UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK0 (*((volatile unsigned int*)(0x42A20290UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK1 (*((volatile unsigned int*)(0x42A20294UL))) +#define bM4_INTC_EIRQCR1_EFEN (*((volatile unsigned int*)(0x42A2029CUL))) +#define bM4_INTC_EIRQCR2_EIRQTRG0 (*((volatile unsigned int*)(0x42A20300UL))) +#define bM4_INTC_EIRQCR2_EIRQTRG1 (*((volatile unsigned int*)(0x42A20304UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK0 (*((volatile unsigned int*)(0x42A20310UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK1 (*((volatile unsigned int*)(0x42A20314UL))) +#define bM4_INTC_EIRQCR2_EFEN (*((volatile unsigned int*)(0x42A2031CUL))) +#define bM4_INTC_EIRQCR3_EIRQTRG0 (*((volatile unsigned int*)(0x42A20380UL))) +#define bM4_INTC_EIRQCR3_EIRQTRG1 (*((volatile unsigned int*)(0x42A20384UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK0 (*((volatile unsigned int*)(0x42A20390UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK1 (*((volatile unsigned int*)(0x42A20394UL))) +#define bM4_INTC_EIRQCR3_EFEN (*((volatile unsigned int*)(0x42A2039CUL))) +#define bM4_INTC_EIRQCR4_EIRQTRG0 (*((volatile unsigned int*)(0x42A20400UL))) +#define bM4_INTC_EIRQCR4_EIRQTRG1 (*((volatile unsigned int*)(0x42A20404UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK0 (*((volatile unsigned int*)(0x42A20410UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK1 (*((volatile unsigned int*)(0x42A20414UL))) +#define bM4_INTC_EIRQCR4_EFEN (*((volatile unsigned int*)(0x42A2041CUL))) +#define bM4_INTC_EIRQCR5_EIRQTRG0 (*((volatile unsigned int*)(0x42A20480UL))) +#define bM4_INTC_EIRQCR5_EIRQTRG1 (*((volatile unsigned int*)(0x42A20484UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK0 (*((volatile unsigned int*)(0x42A20490UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK1 (*((volatile unsigned int*)(0x42A20494UL))) +#define bM4_INTC_EIRQCR5_EFEN (*((volatile unsigned int*)(0x42A2049CUL))) +#define bM4_INTC_EIRQCR6_EIRQTRG0 (*((volatile unsigned int*)(0x42A20500UL))) +#define bM4_INTC_EIRQCR6_EIRQTRG1 (*((volatile unsigned int*)(0x42A20504UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK0 (*((volatile unsigned int*)(0x42A20510UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK1 (*((volatile unsigned int*)(0x42A20514UL))) +#define bM4_INTC_EIRQCR6_EFEN (*((volatile unsigned int*)(0x42A2051CUL))) +#define bM4_INTC_EIRQCR7_EIRQTRG0 (*((volatile unsigned int*)(0x42A20580UL))) +#define bM4_INTC_EIRQCR7_EIRQTRG1 (*((volatile unsigned int*)(0x42A20584UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK0 (*((volatile unsigned int*)(0x42A20590UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK1 (*((volatile unsigned int*)(0x42A20594UL))) +#define bM4_INTC_EIRQCR7_EFEN (*((volatile unsigned int*)(0x42A2059CUL))) +#define bM4_INTC_EIRQCR8_EIRQTRG0 (*((volatile unsigned int*)(0x42A20600UL))) +#define bM4_INTC_EIRQCR8_EIRQTRG1 (*((volatile unsigned int*)(0x42A20604UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK0 (*((volatile unsigned int*)(0x42A20610UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK1 (*((volatile unsigned int*)(0x42A20614UL))) +#define bM4_INTC_EIRQCR8_EFEN (*((volatile unsigned int*)(0x42A2061CUL))) +#define bM4_INTC_EIRQCR9_EIRQTRG0 (*((volatile unsigned int*)(0x42A20680UL))) +#define bM4_INTC_EIRQCR9_EIRQTRG1 (*((volatile unsigned int*)(0x42A20684UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK0 (*((volatile unsigned int*)(0x42A20690UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK1 (*((volatile unsigned int*)(0x42A20694UL))) +#define bM4_INTC_EIRQCR9_EFEN (*((volatile unsigned int*)(0x42A2069CUL))) +#define bM4_INTC_EIRQCR10_EIRQTRG0 (*((volatile unsigned int*)(0x42A20700UL))) +#define bM4_INTC_EIRQCR10_EIRQTRG1 (*((volatile unsigned int*)(0x42A20704UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK0 (*((volatile unsigned int*)(0x42A20710UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK1 (*((volatile unsigned int*)(0x42A20714UL))) +#define bM4_INTC_EIRQCR10_EFEN (*((volatile unsigned int*)(0x42A2071CUL))) +#define bM4_INTC_EIRQCR11_EIRQTRG0 (*((volatile unsigned int*)(0x42A20780UL))) +#define bM4_INTC_EIRQCR11_EIRQTRG1 (*((volatile unsigned int*)(0x42A20784UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK0 (*((volatile unsigned int*)(0x42A20790UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK1 (*((volatile unsigned int*)(0x42A20794UL))) +#define bM4_INTC_EIRQCR11_EFEN (*((volatile unsigned int*)(0x42A2079CUL))) +#define bM4_INTC_EIRQCR12_EIRQTRG0 (*((volatile unsigned int*)(0x42A20800UL))) +#define bM4_INTC_EIRQCR12_EIRQTRG1 (*((volatile unsigned int*)(0x42A20804UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK0 (*((volatile unsigned int*)(0x42A20810UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK1 (*((volatile unsigned int*)(0x42A20814UL))) +#define bM4_INTC_EIRQCR12_EFEN (*((volatile unsigned int*)(0x42A2081CUL))) +#define bM4_INTC_EIRQCR13_EIRQTRG0 (*((volatile unsigned int*)(0x42A20880UL))) +#define bM4_INTC_EIRQCR13_EIRQTRG1 (*((volatile unsigned int*)(0x42A20884UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK0 (*((volatile unsigned int*)(0x42A20890UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK1 (*((volatile unsigned int*)(0x42A20894UL))) +#define bM4_INTC_EIRQCR13_EFEN (*((volatile unsigned int*)(0x42A2089CUL))) +#define bM4_INTC_EIRQCR14_EIRQTRG0 (*((volatile unsigned int*)(0x42A20900UL))) +#define bM4_INTC_EIRQCR14_EIRQTRG1 (*((volatile unsigned int*)(0x42A20904UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK0 (*((volatile unsigned int*)(0x42A20910UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK1 (*((volatile unsigned int*)(0x42A20914UL))) +#define bM4_INTC_EIRQCR14_EFEN (*((volatile unsigned int*)(0x42A2091CUL))) +#define bM4_INTC_EIRQCR15_EIRQTRG0 (*((volatile unsigned int*)(0x42A20980UL))) +#define bM4_INTC_EIRQCR15_EIRQTRG1 (*((volatile unsigned int*)(0x42A20984UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK0 (*((volatile unsigned int*)(0x42A20990UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK1 (*((volatile unsigned int*)(0x42A20994UL))) +#define bM4_INTC_EIRQCR15_EFEN (*((volatile unsigned int*)(0x42A2099CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN0 (*((volatile unsigned int*)(0x42A20A00UL))) +#define bM4_INTC_WUPEN_EIRQWUEN1 (*((volatile unsigned int*)(0x42A20A04UL))) +#define bM4_INTC_WUPEN_EIRQWUEN2 (*((volatile unsigned int*)(0x42A20A08UL))) +#define bM4_INTC_WUPEN_EIRQWUEN3 (*((volatile unsigned int*)(0x42A20A0CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN4 (*((volatile unsigned int*)(0x42A20A10UL))) +#define bM4_INTC_WUPEN_EIRQWUEN5 (*((volatile unsigned int*)(0x42A20A14UL))) +#define bM4_INTC_WUPEN_EIRQWUEN6 (*((volatile unsigned int*)(0x42A20A18UL))) +#define bM4_INTC_WUPEN_EIRQWUEN7 (*((volatile unsigned int*)(0x42A20A1CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN8 (*((volatile unsigned int*)(0x42A20A20UL))) +#define bM4_INTC_WUPEN_EIRQWUEN9 (*((volatile unsigned int*)(0x42A20A24UL))) +#define bM4_INTC_WUPEN_EIRQWUEN10 (*((volatile unsigned int*)(0x42A20A28UL))) +#define bM4_INTC_WUPEN_EIRQWUEN11 (*((volatile unsigned int*)(0x42A20A2CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN12 (*((volatile unsigned int*)(0x42A20A30UL))) +#define bM4_INTC_WUPEN_EIRQWUEN13 (*((volatile unsigned int*)(0x42A20A34UL))) +#define bM4_INTC_WUPEN_EIRQWUEN14 (*((volatile unsigned int*)(0x42A20A38UL))) +#define bM4_INTC_WUPEN_EIRQWUEN15 (*((volatile unsigned int*)(0x42A20A3CUL))) +#define bM4_INTC_WUPEN_SWDTWUEN (*((volatile unsigned int*)(0x42A20A40UL))) +#define bM4_INTC_WUPEN_PVD1WUEN (*((volatile unsigned int*)(0x42A20A44UL))) +#define bM4_INTC_WUPEN_PVD2WUEN (*((volatile unsigned int*)(0x42A20A48UL))) +#define bM4_INTC_WUPEN_CMPI0WUEN (*((volatile unsigned int*)(0x42A20A4CUL))) +#define bM4_INTC_WUPEN_WKTMWUEN (*((volatile unsigned int*)(0x42A20A50UL))) +#define bM4_INTC_WUPEN_RTCALMWUEN (*((volatile unsigned int*)(0x42A20A54UL))) +#define bM4_INTC_WUPEN_RTCPRDWUEN (*((volatile unsigned int*)(0x42A20A58UL))) +#define bM4_INTC_WUPEN_TMR0WUEN (*((volatile unsigned int*)(0x42A20A5CUL))) +#define bM4_INTC_WUPEN_RXWUEN (*((volatile unsigned int*)(0x42A20A64UL))) +#define bM4_INTC_EIFR_EIFR0 (*((volatile unsigned int*)(0x42A20A80UL))) +#define bM4_INTC_EIFR_EIFR1 (*((volatile unsigned int*)(0x42A20A84UL))) +#define bM4_INTC_EIFR_EIFR2 (*((volatile unsigned int*)(0x42A20A88UL))) +#define bM4_INTC_EIFR_EIFR3 (*((volatile unsigned int*)(0x42A20A8CUL))) +#define bM4_INTC_EIFR_EIFR4 (*((volatile unsigned int*)(0x42A20A90UL))) +#define bM4_INTC_EIFR_EIFR5 (*((volatile unsigned int*)(0x42A20A94UL))) +#define bM4_INTC_EIFR_EIFR6 (*((volatile unsigned int*)(0x42A20A98UL))) +#define bM4_INTC_EIFR_EIFR7 (*((volatile unsigned int*)(0x42A20A9CUL))) +#define bM4_INTC_EIFR_EIFR8 (*((volatile unsigned int*)(0x42A20AA0UL))) +#define bM4_INTC_EIFR_EIFR9 (*((volatile unsigned int*)(0x42A20AA4UL))) +#define bM4_INTC_EIFR_EIFR10 (*((volatile unsigned int*)(0x42A20AA8UL))) +#define bM4_INTC_EIFR_EIFR11 (*((volatile unsigned int*)(0x42A20AACUL))) +#define bM4_INTC_EIFR_EIFR12 (*((volatile unsigned int*)(0x42A20AB0UL))) +#define bM4_INTC_EIFR_EIFR13 (*((volatile unsigned int*)(0x42A20AB4UL))) +#define bM4_INTC_EIFR_EIFR14 (*((volatile unsigned int*)(0x42A20AB8UL))) +#define bM4_INTC_EIFR_EIFR15 (*((volatile unsigned int*)(0x42A20ABCUL))) +#define bM4_INTC_EICFR_EICFR0 (*((volatile unsigned int*)(0x42A20B00UL))) +#define bM4_INTC_EICFR_EICFR1 (*((volatile unsigned int*)(0x42A20B04UL))) +#define bM4_INTC_EICFR_EICFR2 (*((volatile unsigned int*)(0x42A20B08UL))) +#define bM4_INTC_EICFR_EICFR3 (*((volatile unsigned int*)(0x42A20B0CUL))) +#define bM4_INTC_EICFR_EICFR4 (*((volatile unsigned int*)(0x42A20B10UL))) +#define bM4_INTC_EICFR_EICFR5 (*((volatile unsigned int*)(0x42A20B14UL))) +#define bM4_INTC_EICFR_EICFR6 (*((volatile unsigned int*)(0x42A20B18UL))) +#define bM4_INTC_EICFR_EICFR7 (*((volatile unsigned int*)(0x42A20B1CUL))) +#define bM4_INTC_EICFR_EICFR8 (*((volatile unsigned int*)(0x42A20B20UL))) +#define bM4_INTC_EICFR_EICFR9 (*((volatile unsigned int*)(0x42A20B24UL))) +#define bM4_INTC_EICFR_EICFR10 (*((volatile unsigned int*)(0x42A20B28UL))) +#define bM4_INTC_EICFR_EICFR11 (*((volatile unsigned int*)(0x42A20B2CUL))) +#define bM4_INTC_EICFR_EICFR12 (*((volatile unsigned int*)(0x42A20B30UL))) +#define bM4_INTC_EICFR_EICFR13 (*((volatile unsigned int*)(0x42A20B34UL))) +#define bM4_INTC_EICFR_EICFR14 (*((volatile unsigned int*)(0x42A20B38UL))) +#define bM4_INTC_EICFR_EICFR15 (*((volatile unsigned int*)(0x42A20B3CUL))) +#define bM4_INTC_SEL0_INTSEL0 (*((volatile unsigned int*)(0x42A20B80UL))) +#define bM4_INTC_SEL0_INTSEL1 (*((volatile unsigned int*)(0x42A20B84UL))) +#define bM4_INTC_SEL0_INTSEL2 (*((volatile unsigned int*)(0x42A20B88UL))) +#define bM4_INTC_SEL0_INTSEL3 (*((volatile unsigned int*)(0x42A20B8CUL))) +#define bM4_INTC_SEL0_INTSEL4 (*((volatile unsigned int*)(0x42A20B90UL))) +#define bM4_INTC_SEL0_INTSEL5 (*((volatile unsigned int*)(0x42A20B94UL))) +#define bM4_INTC_SEL0_INTSEL6 (*((volatile unsigned int*)(0x42A20B98UL))) +#define bM4_INTC_SEL0_INTSEL7 (*((volatile unsigned int*)(0x42A20B9CUL))) +#define bM4_INTC_SEL0_INTSEL8 (*((volatile unsigned int*)(0x42A20BA0UL))) +#define bM4_INTC_SEL1_INTSEL0 (*((volatile unsigned int*)(0x42A20C00UL))) +#define bM4_INTC_SEL1_INTSEL1 (*((volatile unsigned int*)(0x42A20C04UL))) +#define bM4_INTC_SEL1_INTSEL2 (*((volatile unsigned int*)(0x42A20C08UL))) +#define bM4_INTC_SEL1_INTSEL3 (*((volatile unsigned int*)(0x42A20C0CUL))) +#define bM4_INTC_SEL1_INTSEL4 (*((volatile unsigned int*)(0x42A20C10UL))) +#define bM4_INTC_SEL1_INTSEL5 (*((volatile unsigned int*)(0x42A20C14UL))) +#define bM4_INTC_SEL1_INTSEL6 (*((volatile unsigned int*)(0x42A20C18UL))) +#define bM4_INTC_SEL1_INTSEL7 (*((volatile unsigned int*)(0x42A20C1CUL))) +#define bM4_INTC_SEL1_INTSEL8 (*((volatile unsigned int*)(0x42A20C20UL))) +#define bM4_INTC_SEL2_INTSEL0 (*((volatile unsigned int*)(0x42A20C80UL))) +#define bM4_INTC_SEL2_INTSEL1 (*((volatile unsigned int*)(0x42A20C84UL))) +#define bM4_INTC_SEL2_INTSEL2 (*((volatile unsigned int*)(0x42A20C88UL))) +#define bM4_INTC_SEL2_INTSEL3 (*((volatile unsigned int*)(0x42A20C8CUL))) +#define bM4_INTC_SEL2_INTSEL4 (*((volatile unsigned int*)(0x42A20C90UL))) +#define bM4_INTC_SEL2_INTSEL5 (*((volatile unsigned int*)(0x42A20C94UL))) +#define bM4_INTC_SEL2_INTSEL6 (*((volatile unsigned int*)(0x42A20C98UL))) +#define bM4_INTC_SEL2_INTSEL7 (*((volatile unsigned int*)(0x42A20C9CUL))) +#define bM4_INTC_SEL2_INTSEL8 (*((volatile unsigned int*)(0x42A20CA0UL))) +#define bM4_INTC_SEL3_INTSEL0 (*((volatile unsigned int*)(0x42A20D00UL))) +#define bM4_INTC_SEL3_INTSEL1 (*((volatile unsigned int*)(0x42A20D04UL))) +#define bM4_INTC_SEL3_INTSEL2 (*((volatile unsigned int*)(0x42A20D08UL))) +#define bM4_INTC_SEL3_INTSEL3 (*((volatile unsigned int*)(0x42A20D0CUL))) +#define bM4_INTC_SEL3_INTSEL4 (*((volatile unsigned int*)(0x42A20D10UL))) +#define bM4_INTC_SEL3_INTSEL5 (*((volatile unsigned int*)(0x42A20D14UL))) +#define bM4_INTC_SEL3_INTSEL6 (*((volatile unsigned int*)(0x42A20D18UL))) +#define bM4_INTC_SEL3_INTSEL7 (*((volatile unsigned int*)(0x42A20D1CUL))) +#define bM4_INTC_SEL3_INTSEL8 (*((volatile unsigned int*)(0x42A20D20UL))) +#define bM4_INTC_SEL4_INTSEL0 (*((volatile unsigned int*)(0x42A20D80UL))) +#define bM4_INTC_SEL4_INTSEL1 (*((volatile unsigned int*)(0x42A20D84UL))) +#define bM4_INTC_SEL4_INTSEL2 (*((volatile unsigned int*)(0x42A20D88UL))) +#define bM4_INTC_SEL4_INTSEL3 (*((volatile unsigned int*)(0x42A20D8CUL))) +#define bM4_INTC_SEL4_INTSEL4 (*((volatile unsigned int*)(0x42A20D90UL))) +#define bM4_INTC_SEL4_INTSEL5 (*((volatile unsigned int*)(0x42A20D94UL))) +#define bM4_INTC_SEL4_INTSEL6 (*((volatile unsigned int*)(0x42A20D98UL))) +#define bM4_INTC_SEL4_INTSEL7 (*((volatile unsigned int*)(0x42A20D9CUL))) +#define bM4_INTC_SEL4_INTSEL8 (*((volatile unsigned int*)(0x42A20DA0UL))) +#define bM4_INTC_SEL5_INTSEL0 (*((volatile unsigned int*)(0x42A20E00UL))) +#define bM4_INTC_SEL5_INTSEL1 (*((volatile unsigned int*)(0x42A20E04UL))) +#define bM4_INTC_SEL5_INTSEL2 (*((volatile unsigned int*)(0x42A20E08UL))) +#define bM4_INTC_SEL5_INTSEL3 (*((volatile unsigned int*)(0x42A20E0CUL))) +#define bM4_INTC_SEL5_INTSEL4 (*((volatile unsigned int*)(0x42A20E10UL))) +#define bM4_INTC_SEL5_INTSEL5 (*((volatile unsigned int*)(0x42A20E14UL))) +#define bM4_INTC_SEL5_INTSEL6 (*((volatile unsigned int*)(0x42A20E18UL))) +#define bM4_INTC_SEL5_INTSEL7 (*((volatile unsigned int*)(0x42A20E1CUL))) +#define bM4_INTC_SEL5_INTSEL8 (*((volatile unsigned int*)(0x42A20E20UL))) +#define bM4_INTC_SEL6_INTSEL0 (*((volatile unsigned int*)(0x42A20E80UL))) +#define bM4_INTC_SEL6_INTSEL1 (*((volatile unsigned int*)(0x42A20E84UL))) +#define bM4_INTC_SEL6_INTSEL2 (*((volatile unsigned int*)(0x42A20E88UL))) +#define bM4_INTC_SEL6_INTSEL3 (*((volatile unsigned int*)(0x42A20E8CUL))) +#define bM4_INTC_SEL6_INTSEL4 (*((volatile unsigned int*)(0x42A20E90UL))) +#define bM4_INTC_SEL6_INTSEL5 (*((volatile unsigned int*)(0x42A20E94UL))) +#define bM4_INTC_SEL6_INTSEL6 (*((volatile unsigned int*)(0x42A20E98UL))) +#define bM4_INTC_SEL6_INTSEL7 (*((volatile unsigned int*)(0x42A20E9CUL))) +#define bM4_INTC_SEL6_INTSEL8 (*((volatile unsigned int*)(0x42A20EA0UL))) +#define bM4_INTC_SEL7_INTSEL0 (*((volatile unsigned int*)(0x42A20F00UL))) +#define bM4_INTC_SEL7_INTSEL1 (*((volatile unsigned int*)(0x42A20F04UL))) +#define bM4_INTC_SEL7_INTSEL2 (*((volatile unsigned int*)(0x42A20F08UL))) +#define bM4_INTC_SEL7_INTSEL3 (*((volatile unsigned int*)(0x42A20F0CUL))) +#define bM4_INTC_SEL7_INTSEL4 (*((volatile unsigned int*)(0x42A20F10UL))) +#define bM4_INTC_SEL7_INTSEL5 (*((volatile unsigned int*)(0x42A20F14UL))) +#define bM4_INTC_SEL7_INTSEL6 (*((volatile unsigned int*)(0x42A20F18UL))) +#define bM4_INTC_SEL7_INTSEL7 (*((volatile unsigned int*)(0x42A20F1CUL))) +#define bM4_INTC_SEL7_INTSEL8 (*((volatile unsigned int*)(0x42A20F20UL))) +#define bM4_INTC_SEL8_INTSEL0 (*((volatile unsigned int*)(0x42A20F80UL))) +#define bM4_INTC_SEL8_INTSEL1 (*((volatile unsigned int*)(0x42A20F84UL))) +#define bM4_INTC_SEL8_INTSEL2 (*((volatile unsigned int*)(0x42A20F88UL))) +#define bM4_INTC_SEL8_INTSEL3 (*((volatile unsigned int*)(0x42A20F8CUL))) +#define bM4_INTC_SEL8_INTSEL4 (*((volatile unsigned int*)(0x42A20F90UL))) +#define bM4_INTC_SEL8_INTSEL5 (*((volatile unsigned int*)(0x42A20F94UL))) +#define bM4_INTC_SEL8_INTSEL6 (*((volatile unsigned int*)(0x42A20F98UL))) +#define bM4_INTC_SEL8_INTSEL7 (*((volatile unsigned int*)(0x42A20F9CUL))) +#define bM4_INTC_SEL8_INTSEL8 (*((volatile unsigned int*)(0x42A20FA0UL))) +#define bM4_INTC_SEL9_INTSEL0 (*((volatile unsigned int*)(0x42A21000UL))) +#define bM4_INTC_SEL9_INTSEL1 (*((volatile unsigned int*)(0x42A21004UL))) +#define bM4_INTC_SEL9_INTSEL2 (*((volatile unsigned int*)(0x42A21008UL))) +#define bM4_INTC_SEL9_INTSEL3 (*((volatile unsigned int*)(0x42A2100CUL))) +#define bM4_INTC_SEL9_INTSEL4 (*((volatile unsigned int*)(0x42A21010UL))) +#define bM4_INTC_SEL9_INTSEL5 (*((volatile unsigned int*)(0x42A21014UL))) +#define bM4_INTC_SEL9_INTSEL6 (*((volatile unsigned int*)(0x42A21018UL))) +#define bM4_INTC_SEL9_INTSEL7 (*((volatile unsigned int*)(0x42A2101CUL))) +#define bM4_INTC_SEL9_INTSEL8 (*((volatile unsigned int*)(0x42A21020UL))) +#define bM4_INTC_SEL10_INTSEL0 (*((volatile unsigned int*)(0x42A21080UL))) +#define bM4_INTC_SEL10_INTSEL1 (*((volatile unsigned int*)(0x42A21084UL))) +#define bM4_INTC_SEL10_INTSEL2 (*((volatile unsigned int*)(0x42A21088UL))) +#define bM4_INTC_SEL10_INTSEL3 (*((volatile unsigned int*)(0x42A2108CUL))) +#define bM4_INTC_SEL10_INTSEL4 (*((volatile unsigned int*)(0x42A21090UL))) +#define bM4_INTC_SEL10_INTSEL5 (*((volatile unsigned int*)(0x42A21094UL))) +#define bM4_INTC_SEL10_INTSEL6 (*((volatile unsigned int*)(0x42A21098UL))) +#define bM4_INTC_SEL10_INTSEL7 (*((volatile unsigned int*)(0x42A2109CUL))) +#define bM4_INTC_SEL10_INTSEL8 (*((volatile unsigned int*)(0x42A210A0UL))) +#define bM4_INTC_SEL11_INTSEL0 (*((volatile unsigned int*)(0x42A21100UL))) +#define bM4_INTC_SEL11_INTSEL1 (*((volatile unsigned int*)(0x42A21104UL))) +#define bM4_INTC_SEL11_INTSEL2 (*((volatile unsigned int*)(0x42A21108UL))) +#define bM4_INTC_SEL11_INTSEL3 (*((volatile unsigned int*)(0x42A2110CUL))) +#define bM4_INTC_SEL11_INTSEL4 (*((volatile unsigned int*)(0x42A21110UL))) +#define bM4_INTC_SEL11_INTSEL5 (*((volatile unsigned int*)(0x42A21114UL))) +#define bM4_INTC_SEL11_INTSEL6 (*((volatile unsigned int*)(0x42A21118UL))) +#define bM4_INTC_SEL11_INTSEL7 (*((volatile unsigned int*)(0x42A2111CUL))) +#define bM4_INTC_SEL11_INTSEL8 (*((volatile unsigned int*)(0x42A21120UL))) +#define bM4_INTC_SEL12_INTSEL0 (*((volatile unsigned int*)(0x42A21180UL))) +#define bM4_INTC_SEL12_INTSEL1 (*((volatile unsigned int*)(0x42A21184UL))) +#define bM4_INTC_SEL12_INTSEL2 (*((volatile unsigned int*)(0x42A21188UL))) +#define bM4_INTC_SEL12_INTSEL3 (*((volatile unsigned int*)(0x42A2118CUL))) +#define bM4_INTC_SEL12_INTSEL4 (*((volatile unsigned int*)(0x42A21190UL))) +#define bM4_INTC_SEL12_INTSEL5 (*((volatile unsigned int*)(0x42A21194UL))) +#define bM4_INTC_SEL12_INTSEL6 (*((volatile unsigned int*)(0x42A21198UL))) +#define bM4_INTC_SEL12_INTSEL7 (*((volatile unsigned int*)(0x42A2119CUL))) +#define bM4_INTC_SEL12_INTSEL8 (*((volatile unsigned int*)(0x42A211A0UL))) +#define bM4_INTC_SEL13_INTSEL0 (*((volatile unsigned int*)(0x42A21200UL))) +#define bM4_INTC_SEL13_INTSEL1 (*((volatile unsigned int*)(0x42A21204UL))) +#define bM4_INTC_SEL13_INTSEL2 (*((volatile unsigned int*)(0x42A21208UL))) +#define bM4_INTC_SEL13_INTSEL3 (*((volatile unsigned int*)(0x42A2120CUL))) +#define bM4_INTC_SEL13_INTSEL4 (*((volatile unsigned int*)(0x42A21210UL))) +#define bM4_INTC_SEL13_INTSEL5 (*((volatile unsigned int*)(0x42A21214UL))) +#define bM4_INTC_SEL13_INTSEL6 (*((volatile unsigned int*)(0x42A21218UL))) +#define bM4_INTC_SEL13_INTSEL7 (*((volatile unsigned int*)(0x42A2121CUL))) +#define bM4_INTC_SEL13_INTSEL8 (*((volatile unsigned int*)(0x42A21220UL))) +#define bM4_INTC_SEL14_INTSEL0 (*((volatile unsigned int*)(0x42A21280UL))) +#define bM4_INTC_SEL14_INTSEL1 (*((volatile unsigned int*)(0x42A21284UL))) +#define bM4_INTC_SEL14_INTSEL2 (*((volatile unsigned int*)(0x42A21288UL))) +#define bM4_INTC_SEL14_INTSEL3 (*((volatile unsigned int*)(0x42A2128CUL))) +#define bM4_INTC_SEL14_INTSEL4 (*((volatile unsigned int*)(0x42A21290UL))) +#define bM4_INTC_SEL14_INTSEL5 (*((volatile unsigned int*)(0x42A21294UL))) +#define bM4_INTC_SEL14_INTSEL6 (*((volatile unsigned int*)(0x42A21298UL))) +#define bM4_INTC_SEL14_INTSEL7 (*((volatile unsigned int*)(0x42A2129CUL))) +#define bM4_INTC_SEL14_INTSEL8 (*((volatile unsigned int*)(0x42A212A0UL))) +#define bM4_INTC_SEL15_INTSEL0 (*((volatile unsigned int*)(0x42A21300UL))) +#define bM4_INTC_SEL15_INTSEL1 (*((volatile unsigned int*)(0x42A21304UL))) +#define bM4_INTC_SEL15_INTSEL2 (*((volatile unsigned int*)(0x42A21308UL))) +#define bM4_INTC_SEL15_INTSEL3 (*((volatile unsigned int*)(0x42A2130CUL))) +#define bM4_INTC_SEL15_INTSEL4 (*((volatile unsigned int*)(0x42A21310UL))) +#define bM4_INTC_SEL15_INTSEL5 (*((volatile unsigned int*)(0x42A21314UL))) +#define bM4_INTC_SEL15_INTSEL6 (*((volatile unsigned int*)(0x42A21318UL))) +#define bM4_INTC_SEL15_INTSEL7 (*((volatile unsigned int*)(0x42A2131CUL))) +#define bM4_INTC_SEL15_INTSEL8 (*((volatile unsigned int*)(0x42A21320UL))) +#define bM4_INTC_SEL16_INTSEL0 (*((volatile unsigned int*)(0x42A21380UL))) +#define bM4_INTC_SEL16_INTSEL1 (*((volatile unsigned int*)(0x42A21384UL))) +#define bM4_INTC_SEL16_INTSEL2 (*((volatile unsigned int*)(0x42A21388UL))) +#define bM4_INTC_SEL16_INTSEL3 (*((volatile unsigned int*)(0x42A2138CUL))) +#define bM4_INTC_SEL16_INTSEL4 (*((volatile unsigned int*)(0x42A21390UL))) +#define bM4_INTC_SEL16_INTSEL5 (*((volatile unsigned int*)(0x42A21394UL))) +#define bM4_INTC_SEL16_INTSEL6 (*((volatile unsigned int*)(0x42A21398UL))) +#define bM4_INTC_SEL16_INTSEL7 (*((volatile unsigned int*)(0x42A2139CUL))) +#define bM4_INTC_SEL16_INTSEL8 (*((volatile unsigned int*)(0x42A213A0UL))) +#define bM4_INTC_SEL17_INTSEL0 (*((volatile unsigned int*)(0x42A21400UL))) +#define bM4_INTC_SEL17_INTSEL1 (*((volatile unsigned int*)(0x42A21404UL))) +#define bM4_INTC_SEL17_INTSEL2 (*((volatile unsigned int*)(0x42A21408UL))) +#define bM4_INTC_SEL17_INTSEL3 (*((volatile unsigned int*)(0x42A2140CUL))) +#define bM4_INTC_SEL17_INTSEL4 (*((volatile unsigned int*)(0x42A21410UL))) +#define bM4_INTC_SEL17_INTSEL5 (*((volatile unsigned int*)(0x42A21414UL))) +#define bM4_INTC_SEL17_INTSEL6 (*((volatile unsigned int*)(0x42A21418UL))) +#define bM4_INTC_SEL17_INTSEL7 (*((volatile unsigned int*)(0x42A2141CUL))) +#define bM4_INTC_SEL17_INTSEL8 (*((volatile unsigned int*)(0x42A21420UL))) +#define bM4_INTC_SEL18_INTSEL0 (*((volatile unsigned int*)(0x42A21480UL))) +#define bM4_INTC_SEL18_INTSEL1 (*((volatile unsigned int*)(0x42A21484UL))) +#define bM4_INTC_SEL18_INTSEL2 (*((volatile unsigned int*)(0x42A21488UL))) +#define bM4_INTC_SEL18_INTSEL3 (*((volatile unsigned int*)(0x42A2148CUL))) +#define bM4_INTC_SEL18_INTSEL4 (*((volatile unsigned int*)(0x42A21490UL))) +#define bM4_INTC_SEL18_INTSEL5 (*((volatile unsigned int*)(0x42A21494UL))) +#define bM4_INTC_SEL18_INTSEL6 (*((volatile unsigned int*)(0x42A21498UL))) +#define bM4_INTC_SEL18_INTSEL7 (*((volatile unsigned int*)(0x42A2149CUL))) +#define bM4_INTC_SEL18_INTSEL8 (*((volatile unsigned int*)(0x42A214A0UL))) +#define bM4_INTC_SEL19_INTSEL0 (*((volatile unsigned int*)(0x42A21500UL))) +#define bM4_INTC_SEL19_INTSEL1 (*((volatile unsigned int*)(0x42A21504UL))) +#define bM4_INTC_SEL19_INTSEL2 (*((volatile unsigned int*)(0x42A21508UL))) +#define bM4_INTC_SEL19_INTSEL3 (*((volatile unsigned int*)(0x42A2150CUL))) +#define bM4_INTC_SEL19_INTSEL4 (*((volatile unsigned int*)(0x42A21510UL))) +#define bM4_INTC_SEL19_INTSEL5 (*((volatile unsigned int*)(0x42A21514UL))) +#define bM4_INTC_SEL19_INTSEL6 (*((volatile unsigned int*)(0x42A21518UL))) +#define bM4_INTC_SEL19_INTSEL7 (*((volatile unsigned int*)(0x42A2151CUL))) +#define bM4_INTC_SEL19_INTSEL8 (*((volatile unsigned int*)(0x42A21520UL))) +#define bM4_INTC_SEL20_INTSEL0 (*((volatile unsigned int*)(0x42A21580UL))) +#define bM4_INTC_SEL20_INTSEL1 (*((volatile unsigned int*)(0x42A21584UL))) +#define bM4_INTC_SEL20_INTSEL2 (*((volatile unsigned int*)(0x42A21588UL))) +#define bM4_INTC_SEL20_INTSEL3 (*((volatile unsigned int*)(0x42A2158CUL))) +#define bM4_INTC_SEL20_INTSEL4 (*((volatile unsigned int*)(0x42A21590UL))) +#define bM4_INTC_SEL20_INTSEL5 (*((volatile unsigned int*)(0x42A21594UL))) +#define bM4_INTC_SEL20_INTSEL6 (*((volatile unsigned int*)(0x42A21598UL))) +#define bM4_INTC_SEL20_INTSEL7 (*((volatile unsigned int*)(0x42A2159CUL))) +#define bM4_INTC_SEL20_INTSEL8 (*((volatile unsigned int*)(0x42A215A0UL))) +#define bM4_INTC_SEL21_INTSEL0 (*((volatile unsigned int*)(0x42A21600UL))) +#define bM4_INTC_SEL21_INTSEL1 (*((volatile unsigned int*)(0x42A21604UL))) +#define bM4_INTC_SEL21_INTSEL2 (*((volatile unsigned int*)(0x42A21608UL))) +#define bM4_INTC_SEL21_INTSEL3 (*((volatile unsigned int*)(0x42A2160CUL))) +#define bM4_INTC_SEL21_INTSEL4 (*((volatile unsigned int*)(0x42A21610UL))) +#define bM4_INTC_SEL21_INTSEL5 (*((volatile unsigned int*)(0x42A21614UL))) +#define bM4_INTC_SEL21_INTSEL6 (*((volatile unsigned int*)(0x42A21618UL))) +#define bM4_INTC_SEL21_INTSEL7 (*((volatile unsigned int*)(0x42A2161CUL))) +#define bM4_INTC_SEL21_INTSEL8 (*((volatile unsigned int*)(0x42A21620UL))) +#define bM4_INTC_SEL22_INTSEL0 (*((volatile unsigned int*)(0x42A21680UL))) +#define bM4_INTC_SEL22_INTSEL1 (*((volatile unsigned int*)(0x42A21684UL))) +#define bM4_INTC_SEL22_INTSEL2 (*((volatile unsigned int*)(0x42A21688UL))) +#define bM4_INTC_SEL22_INTSEL3 (*((volatile unsigned int*)(0x42A2168CUL))) +#define bM4_INTC_SEL22_INTSEL4 (*((volatile unsigned int*)(0x42A21690UL))) +#define bM4_INTC_SEL22_INTSEL5 (*((volatile unsigned int*)(0x42A21694UL))) +#define bM4_INTC_SEL22_INTSEL6 (*((volatile unsigned int*)(0x42A21698UL))) +#define bM4_INTC_SEL22_INTSEL7 (*((volatile unsigned int*)(0x42A2169CUL))) +#define bM4_INTC_SEL22_INTSEL8 (*((volatile unsigned int*)(0x42A216A0UL))) +#define bM4_INTC_SEL23_INTSEL0 (*((volatile unsigned int*)(0x42A21700UL))) +#define bM4_INTC_SEL23_INTSEL1 (*((volatile unsigned int*)(0x42A21704UL))) +#define bM4_INTC_SEL23_INTSEL2 (*((volatile unsigned int*)(0x42A21708UL))) +#define bM4_INTC_SEL23_INTSEL3 (*((volatile unsigned int*)(0x42A2170CUL))) +#define bM4_INTC_SEL23_INTSEL4 (*((volatile unsigned int*)(0x42A21710UL))) +#define bM4_INTC_SEL23_INTSEL5 (*((volatile unsigned int*)(0x42A21714UL))) +#define bM4_INTC_SEL23_INTSEL6 (*((volatile unsigned int*)(0x42A21718UL))) +#define bM4_INTC_SEL23_INTSEL7 (*((volatile unsigned int*)(0x42A2171CUL))) +#define bM4_INTC_SEL23_INTSEL8 (*((volatile unsigned int*)(0x42A21720UL))) +#define bM4_INTC_SEL24_INTSEL0 (*((volatile unsigned int*)(0x42A21780UL))) +#define bM4_INTC_SEL24_INTSEL1 (*((volatile unsigned int*)(0x42A21784UL))) +#define bM4_INTC_SEL24_INTSEL2 (*((volatile unsigned int*)(0x42A21788UL))) +#define bM4_INTC_SEL24_INTSEL3 (*((volatile unsigned int*)(0x42A2178CUL))) +#define bM4_INTC_SEL24_INTSEL4 (*((volatile unsigned int*)(0x42A21790UL))) +#define bM4_INTC_SEL24_INTSEL5 (*((volatile unsigned int*)(0x42A21794UL))) +#define bM4_INTC_SEL24_INTSEL6 (*((volatile unsigned int*)(0x42A21798UL))) +#define bM4_INTC_SEL24_INTSEL7 (*((volatile unsigned int*)(0x42A2179CUL))) +#define bM4_INTC_SEL24_INTSEL8 (*((volatile unsigned int*)(0x42A217A0UL))) +#define bM4_INTC_SEL25_INTSEL0 (*((volatile unsigned int*)(0x42A21800UL))) +#define bM4_INTC_SEL25_INTSEL1 (*((volatile unsigned int*)(0x42A21804UL))) +#define bM4_INTC_SEL25_INTSEL2 (*((volatile unsigned int*)(0x42A21808UL))) +#define bM4_INTC_SEL25_INTSEL3 (*((volatile unsigned int*)(0x42A2180CUL))) +#define bM4_INTC_SEL25_INTSEL4 (*((volatile unsigned int*)(0x42A21810UL))) +#define bM4_INTC_SEL25_INTSEL5 (*((volatile unsigned int*)(0x42A21814UL))) +#define bM4_INTC_SEL25_INTSEL6 (*((volatile unsigned int*)(0x42A21818UL))) +#define bM4_INTC_SEL25_INTSEL7 (*((volatile unsigned int*)(0x42A2181CUL))) +#define bM4_INTC_SEL25_INTSEL8 (*((volatile unsigned int*)(0x42A21820UL))) +#define bM4_INTC_SEL26_INTSEL0 (*((volatile unsigned int*)(0x42A21880UL))) +#define bM4_INTC_SEL26_INTSEL1 (*((volatile unsigned int*)(0x42A21884UL))) +#define bM4_INTC_SEL26_INTSEL2 (*((volatile unsigned int*)(0x42A21888UL))) +#define bM4_INTC_SEL26_INTSEL3 (*((volatile unsigned int*)(0x42A2188CUL))) +#define bM4_INTC_SEL26_INTSEL4 (*((volatile unsigned int*)(0x42A21890UL))) +#define bM4_INTC_SEL26_INTSEL5 (*((volatile unsigned int*)(0x42A21894UL))) +#define bM4_INTC_SEL26_INTSEL6 (*((volatile unsigned int*)(0x42A21898UL))) +#define bM4_INTC_SEL26_INTSEL7 (*((volatile unsigned int*)(0x42A2189CUL))) +#define bM4_INTC_SEL26_INTSEL8 (*((volatile unsigned int*)(0x42A218A0UL))) +#define bM4_INTC_SEL27_INTSEL0 (*((volatile unsigned int*)(0x42A21900UL))) +#define bM4_INTC_SEL27_INTSEL1 (*((volatile unsigned int*)(0x42A21904UL))) +#define bM4_INTC_SEL27_INTSEL2 (*((volatile unsigned int*)(0x42A21908UL))) +#define bM4_INTC_SEL27_INTSEL3 (*((volatile unsigned int*)(0x42A2190CUL))) +#define bM4_INTC_SEL27_INTSEL4 (*((volatile unsigned int*)(0x42A21910UL))) +#define bM4_INTC_SEL27_INTSEL5 (*((volatile unsigned int*)(0x42A21914UL))) +#define bM4_INTC_SEL27_INTSEL6 (*((volatile unsigned int*)(0x42A21918UL))) +#define bM4_INTC_SEL27_INTSEL7 (*((volatile unsigned int*)(0x42A2191CUL))) +#define bM4_INTC_SEL27_INTSEL8 (*((volatile unsigned int*)(0x42A21920UL))) +#define bM4_INTC_SEL28_INTSEL0 (*((volatile unsigned int*)(0x42A21980UL))) +#define bM4_INTC_SEL28_INTSEL1 (*((volatile unsigned int*)(0x42A21984UL))) +#define bM4_INTC_SEL28_INTSEL2 (*((volatile unsigned int*)(0x42A21988UL))) +#define bM4_INTC_SEL28_INTSEL3 (*((volatile unsigned int*)(0x42A2198CUL))) +#define bM4_INTC_SEL28_INTSEL4 (*((volatile unsigned int*)(0x42A21990UL))) +#define bM4_INTC_SEL28_INTSEL5 (*((volatile unsigned int*)(0x42A21994UL))) +#define bM4_INTC_SEL28_INTSEL6 (*((volatile unsigned int*)(0x42A21998UL))) +#define bM4_INTC_SEL28_INTSEL7 (*((volatile unsigned int*)(0x42A2199CUL))) +#define bM4_INTC_SEL28_INTSEL8 (*((volatile unsigned int*)(0x42A219A0UL))) +#define bM4_INTC_SEL29_INTSEL0 (*((volatile unsigned int*)(0x42A21A00UL))) +#define bM4_INTC_SEL29_INTSEL1 (*((volatile unsigned int*)(0x42A21A04UL))) +#define bM4_INTC_SEL29_INTSEL2 (*((volatile unsigned int*)(0x42A21A08UL))) +#define bM4_INTC_SEL29_INTSEL3 (*((volatile unsigned int*)(0x42A21A0CUL))) +#define bM4_INTC_SEL29_INTSEL4 (*((volatile unsigned int*)(0x42A21A10UL))) +#define bM4_INTC_SEL29_INTSEL5 (*((volatile unsigned int*)(0x42A21A14UL))) +#define bM4_INTC_SEL29_INTSEL6 (*((volatile unsigned int*)(0x42A21A18UL))) +#define bM4_INTC_SEL29_INTSEL7 (*((volatile unsigned int*)(0x42A21A1CUL))) +#define bM4_INTC_SEL29_INTSEL8 (*((volatile unsigned int*)(0x42A21A20UL))) +#define bM4_INTC_SEL30_INTSEL0 (*((volatile unsigned int*)(0x42A21A80UL))) +#define bM4_INTC_SEL30_INTSEL1 (*((volatile unsigned int*)(0x42A21A84UL))) +#define bM4_INTC_SEL30_INTSEL2 (*((volatile unsigned int*)(0x42A21A88UL))) +#define bM4_INTC_SEL30_INTSEL3 (*((volatile unsigned int*)(0x42A21A8CUL))) +#define bM4_INTC_SEL30_INTSEL4 (*((volatile unsigned int*)(0x42A21A90UL))) +#define bM4_INTC_SEL30_INTSEL5 (*((volatile unsigned int*)(0x42A21A94UL))) +#define bM4_INTC_SEL30_INTSEL6 (*((volatile unsigned int*)(0x42A21A98UL))) +#define bM4_INTC_SEL30_INTSEL7 (*((volatile unsigned int*)(0x42A21A9CUL))) +#define bM4_INTC_SEL30_INTSEL8 (*((volatile unsigned int*)(0x42A21AA0UL))) +#define bM4_INTC_SEL31_INTSEL0 (*((volatile unsigned int*)(0x42A21B00UL))) +#define bM4_INTC_SEL31_INTSEL1 (*((volatile unsigned int*)(0x42A21B04UL))) +#define bM4_INTC_SEL31_INTSEL2 (*((volatile unsigned int*)(0x42A21B08UL))) +#define bM4_INTC_SEL31_INTSEL3 (*((volatile unsigned int*)(0x42A21B0CUL))) +#define bM4_INTC_SEL31_INTSEL4 (*((volatile unsigned int*)(0x42A21B10UL))) +#define bM4_INTC_SEL31_INTSEL5 (*((volatile unsigned int*)(0x42A21B14UL))) +#define bM4_INTC_SEL31_INTSEL6 (*((volatile unsigned int*)(0x42A21B18UL))) +#define bM4_INTC_SEL31_INTSEL7 (*((volatile unsigned int*)(0x42A21B1CUL))) +#define bM4_INTC_SEL31_INTSEL8 (*((volatile unsigned int*)(0x42A21B20UL))) +#define bM4_INTC_SEL32_INTSEL0 (*((volatile unsigned int*)(0x42A21B80UL))) +#define bM4_INTC_SEL32_INTSEL1 (*((volatile unsigned int*)(0x42A21B84UL))) +#define bM4_INTC_SEL32_INTSEL2 (*((volatile unsigned int*)(0x42A21B88UL))) +#define bM4_INTC_SEL32_INTSEL3 (*((volatile unsigned int*)(0x42A21B8CUL))) +#define bM4_INTC_SEL32_INTSEL4 (*((volatile unsigned int*)(0x42A21B90UL))) +#define bM4_INTC_SEL32_INTSEL5 (*((volatile unsigned int*)(0x42A21B94UL))) +#define bM4_INTC_SEL32_INTSEL6 (*((volatile unsigned int*)(0x42A21B98UL))) +#define bM4_INTC_SEL32_INTSEL7 (*((volatile unsigned int*)(0x42A21B9CUL))) +#define bM4_INTC_SEL32_INTSEL8 (*((volatile unsigned int*)(0x42A21BA0UL))) +#define bM4_INTC_SEL33_INTSEL0 (*((volatile unsigned int*)(0x42A21C00UL))) +#define bM4_INTC_SEL33_INTSEL1 (*((volatile unsigned int*)(0x42A21C04UL))) +#define bM4_INTC_SEL33_INTSEL2 (*((volatile unsigned int*)(0x42A21C08UL))) +#define bM4_INTC_SEL33_INTSEL3 (*((volatile unsigned int*)(0x42A21C0CUL))) +#define bM4_INTC_SEL33_INTSEL4 (*((volatile unsigned int*)(0x42A21C10UL))) +#define bM4_INTC_SEL33_INTSEL5 (*((volatile unsigned int*)(0x42A21C14UL))) +#define bM4_INTC_SEL33_INTSEL6 (*((volatile unsigned int*)(0x42A21C18UL))) +#define bM4_INTC_SEL33_INTSEL7 (*((volatile unsigned int*)(0x42A21C1CUL))) +#define bM4_INTC_SEL33_INTSEL8 (*((volatile unsigned int*)(0x42A21C20UL))) +#define bM4_INTC_SEL34_INTSEL0 (*((volatile unsigned int*)(0x42A21C80UL))) +#define bM4_INTC_SEL34_INTSEL1 (*((volatile unsigned int*)(0x42A21C84UL))) +#define bM4_INTC_SEL34_INTSEL2 (*((volatile unsigned int*)(0x42A21C88UL))) +#define bM4_INTC_SEL34_INTSEL3 (*((volatile unsigned int*)(0x42A21C8CUL))) +#define bM4_INTC_SEL34_INTSEL4 (*((volatile unsigned int*)(0x42A21C90UL))) +#define bM4_INTC_SEL34_INTSEL5 (*((volatile unsigned int*)(0x42A21C94UL))) +#define bM4_INTC_SEL34_INTSEL6 (*((volatile unsigned int*)(0x42A21C98UL))) +#define bM4_INTC_SEL34_INTSEL7 (*((volatile unsigned int*)(0x42A21C9CUL))) +#define bM4_INTC_SEL34_INTSEL8 (*((volatile unsigned int*)(0x42A21CA0UL))) +#define bM4_INTC_SEL35_INTSEL0 (*((volatile unsigned int*)(0x42A21D00UL))) +#define bM4_INTC_SEL35_INTSEL1 (*((volatile unsigned int*)(0x42A21D04UL))) +#define bM4_INTC_SEL35_INTSEL2 (*((volatile unsigned int*)(0x42A21D08UL))) +#define bM4_INTC_SEL35_INTSEL3 (*((volatile unsigned int*)(0x42A21D0CUL))) +#define bM4_INTC_SEL35_INTSEL4 (*((volatile unsigned int*)(0x42A21D10UL))) +#define bM4_INTC_SEL35_INTSEL5 (*((volatile unsigned int*)(0x42A21D14UL))) +#define bM4_INTC_SEL35_INTSEL6 (*((volatile unsigned int*)(0x42A21D18UL))) +#define bM4_INTC_SEL35_INTSEL7 (*((volatile unsigned int*)(0x42A21D1CUL))) +#define bM4_INTC_SEL35_INTSEL8 (*((volatile unsigned int*)(0x42A21D20UL))) +#define bM4_INTC_SEL36_INTSEL0 (*((volatile unsigned int*)(0x42A21D80UL))) +#define bM4_INTC_SEL36_INTSEL1 (*((volatile unsigned int*)(0x42A21D84UL))) +#define bM4_INTC_SEL36_INTSEL2 (*((volatile unsigned int*)(0x42A21D88UL))) +#define bM4_INTC_SEL36_INTSEL3 (*((volatile unsigned int*)(0x42A21D8CUL))) +#define bM4_INTC_SEL36_INTSEL4 (*((volatile unsigned int*)(0x42A21D90UL))) +#define bM4_INTC_SEL36_INTSEL5 (*((volatile unsigned int*)(0x42A21D94UL))) +#define bM4_INTC_SEL36_INTSEL6 (*((volatile unsigned int*)(0x42A21D98UL))) +#define bM4_INTC_SEL36_INTSEL7 (*((volatile unsigned int*)(0x42A21D9CUL))) +#define bM4_INTC_SEL36_INTSEL8 (*((volatile unsigned int*)(0x42A21DA0UL))) +#define bM4_INTC_SEL37_INTSEL0 (*((volatile unsigned int*)(0x42A21E00UL))) +#define bM4_INTC_SEL37_INTSEL1 (*((volatile unsigned int*)(0x42A21E04UL))) +#define bM4_INTC_SEL37_INTSEL2 (*((volatile unsigned int*)(0x42A21E08UL))) +#define bM4_INTC_SEL37_INTSEL3 (*((volatile unsigned int*)(0x42A21E0CUL))) +#define bM4_INTC_SEL37_INTSEL4 (*((volatile unsigned int*)(0x42A21E10UL))) +#define bM4_INTC_SEL37_INTSEL5 (*((volatile unsigned int*)(0x42A21E14UL))) +#define bM4_INTC_SEL37_INTSEL6 (*((volatile unsigned int*)(0x42A21E18UL))) +#define bM4_INTC_SEL37_INTSEL7 (*((volatile unsigned int*)(0x42A21E1CUL))) +#define bM4_INTC_SEL37_INTSEL8 (*((volatile unsigned int*)(0x42A21E20UL))) +#define bM4_INTC_SEL38_INTSEL0 (*((volatile unsigned int*)(0x42A21E80UL))) +#define bM4_INTC_SEL38_INTSEL1 (*((volatile unsigned int*)(0x42A21E84UL))) +#define bM4_INTC_SEL38_INTSEL2 (*((volatile unsigned int*)(0x42A21E88UL))) +#define bM4_INTC_SEL38_INTSEL3 (*((volatile unsigned int*)(0x42A21E8CUL))) +#define bM4_INTC_SEL38_INTSEL4 (*((volatile unsigned int*)(0x42A21E90UL))) +#define bM4_INTC_SEL38_INTSEL5 (*((volatile unsigned int*)(0x42A21E94UL))) +#define bM4_INTC_SEL38_INTSEL6 (*((volatile unsigned int*)(0x42A21E98UL))) +#define bM4_INTC_SEL38_INTSEL7 (*((volatile unsigned int*)(0x42A21E9CUL))) +#define bM4_INTC_SEL38_INTSEL8 (*((volatile unsigned int*)(0x42A21EA0UL))) +#define bM4_INTC_SEL39_INTSEL0 (*((volatile unsigned int*)(0x42A21F00UL))) +#define bM4_INTC_SEL39_INTSEL1 (*((volatile unsigned int*)(0x42A21F04UL))) +#define bM4_INTC_SEL39_INTSEL2 (*((volatile unsigned int*)(0x42A21F08UL))) +#define bM4_INTC_SEL39_INTSEL3 (*((volatile unsigned int*)(0x42A21F0CUL))) +#define bM4_INTC_SEL39_INTSEL4 (*((volatile unsigned int*)(0x42A21F10UL))) +#define bM4_INTC_SEL39_INTSEL5 (*((volatile unsigned int*)(0x42A21F14UL))) +#define bM4_INTC_SEL39_INTSEL6 (*((volatile unsigned int*)(0x42A21F18UL))) +#define bM4_INTC_SEL39_INTSEL7 (*((volatile unsigned int*)(0x42A21F1CUL))) +#define bM4_INTC_SEL39_INTSEL8 (*((volatile unsigned int*)(0x42A21F20UL))) +#define bM4_INTC_SEL40_INTSEL0 (*((volatile unsigned int*)(0x42A21F80UL))) +#define bM4_INTC_SEL40_INTSEL1 (*((volatile unsigned int*)(0x42A21F84UL))) +#define bM4_INTC_SEL40_INTSEL2 (*((volatile unsigned int*)(0x42A21F88UL))) +#define bM4_INTC_SEL40_INTSEL3 (*((volatile unsigned int*)(0x42A21F8CUL))) +#define bM4_INTC_SEL40_INTSEL4 (*((volatile unsigned int*)(0x42A21F90UL))) +#define bM4_INTC_SEL40_INTSEL5 (*((volatile unsigned int*)(0x42A21F94UL))) +#define bM4_INTC_SEL40_INTSEL6 (*((volatile unsigned int*)(0x42A21F98UL))) +#define bM4_INTC_SEL40_INTSEL7 (*((volatile unsigned int*)(0x42A21F9CUL))) +#define bM4_INTC_SEL40_INTSEL8 (*((volatile unsigned int*)(0x42A21FA0UL))) +#define bM4_INTC_SEL41_INTSEL0 (*((volatile unsigned int*)(0x42A22000UL))) +#define bM4_INTC_SEL41_INTSEL1 (*((volatile unsigned int*)(0x42A22004UL))) +#define bM4_INTC_SEL41_INTSEL2 (*((volatile unsigned int*)(0x42A22008UL))) +#define bM4_INTC_SEL41_INTSEL3 (*((volatile unsigned int*)(0x42A2200CUL))) +#define bM4_INTC_SEL41_INTSEL4 (*((volatile unsigned int*)(0x42A22010UL))) +#define bM4_INTC_SEL41_INTSEL5 (*((volatile unsigned int*)(0x42A22014UL))) +#define bM4_INTC_SEL41_INTSEL6 (*((volatile unsigned int*)(0x42A22018UL))) +#define bM4_INTC_SEL41_INTSEL7 (*((volatile unsigned int*)(0x42A2201CUL))) +#define bM4_INTC_SEL41_INTSEL8 (*((volatile unsigned int*)(0x42A22020UL))) +#define bM4_INTC_SEL42_INTSEL0 (*((volatile unsigned int*)(0x42A22080UL))) +#define bM4_INTC_SEL42_INTSEL1 (*((volatile unsigned int*)(0x42A22084UL))) +#define bM4_INTC_SEL42_INTSEL2 (*((volatile unsigned int*)(0x42A22088UL))) +#define bM4_INTC_SEL42_INTSEL3 (*((volatile unsigned int*)(0x42A2208CUL))) +#define bM4_INTC_SEL42_INTSEL4 (*((volatile unsigned int*)(0x42A22090UL))) +#define bM4_INTC_SEL42_INTSEL5 (*((volatile unsigned int*)(0x42A22094UL))) +#define bM4_INTC_SEL42_INTSEL6 (*((volatile unsigned int*)(0x42A22098UL))) +#define bM4_INTC_SEL42_INTSEL7 (*((volatile unsigned int*)(0x42A2209CUL))) +#define bM4_INTC_SEL42_INTSEL8 (*((volatile unsigned int*)(0x42A220A0UL))) +#define bM4_INTC_SEL43_INTSEL0 (*((volatile unsigned int*)(0x42A22100UL))) +#define bM4_INTC_SEL43_INTSEL1 (*((volatile unsigned int*)(0x42A22104UL))) +#define bM4_INTC_SEL43_INTSEL2 (*((volatile unsigned int*)(0x42A22108UL))) +#define bM4_INTC_SEL43_INTSEL3 (*((volatile unsigned int*)(0x42A2210CUL))) +#define bM4_INTC_SEL43_INTSEL4 (*((volatile unsigned int*)(0x42A22110UL))) +#define bM4_INTC_SEL43_INTSEL5 (*((volatile unsigned int*)(0x42A22114UL))) +#define bM4_INTC_SEL43_INTSEL6 (*((volatile unsigned int*)(0x42A22118UL))) +#define bM4_INTC_SEL43_INTSEL7 (*((volatile unsigned int*)(0x42A2211CUL))) +#define bM4_INTC_SEL43_INTSEL8 (*((volatile unsigned int*)(0x42A22120UL))) +#define bM4_INTC_SEL44_INTSEL0 (*((volatile unsigned int*)(0x42A22180UL))) +#define bM4_INTC_SEL44_INTSEL1 (*((volatile unsigned int*)(0x42A22184UL))) +#define bM4_INTC_SEL44_INTSEL2 (*((volatile unsigned int*)(0x42A22188UL))) +#define bM4_INTC_SEL44_INTSEL3 (*((volatile unsigned int*)(0x42A2218CUL))) +#define bM4_INTC_SEL44_INTSEL4 (*((volatile unsigned int*)(0x42A22190UL))) +#define bM4_INTC_SEL44_INTSEL5 (*((volatile unsigned int*)(0x42A22194UL))) +#define bM4_INTC_SEL44_INTSEL6 (*((volatile unsigned int*)(0x42A22198UL))) +#define bM4_INTC_SEL44_INTSEL7 (*((volatile unsigned int*)(0x42A2219CUL))) +#define bM4_INTC_SEL44_INTSEL8 (*((volatile unsigned int*)(0x42A221A0UL))) +#define bM4_INTC_SEL45_INTSEL0 (*((volatile unsigned int*)(0x42A22200UL))) +#define bM4_INTC_SEL45_INTSEL1 (*((volatile unsigned int*)(0x42A22204UL))) +#define bM4_INTC_SEL45_INTSEL2 (*((volatile unsigned int*)(0x42A22208UL))) +#define bM4_INTC_SEL45_INTSEL3 (*((volatile unsigned int*)(0x42A2220CUL))) +#define bM4_INTC_SEL45_INTSEL4 (*((volatile unsigned int*)(0x42A22210UL))) +#define bM4_INTC_SEL45_INTSEL5 (*((volatile unsigned int*)(0x42A22214UL))) +#define bM4_INTC_SEL45_INTSEL6 (*((volatile unsigned int*)(0x42A22218UL))) +#define bM4_INTC_SEL45_INTSEL7 (*((volatile unsigned int*)(0x42A2221CUL))) +#define bM4_INTC_SEL45_INTSEL8 (*((volatile unsigned int*)(0x42A22220UL))) +#define bM4_INTC_SEL46_INTSEL0 (*((volatile unsigned int*)(0x42A22280UL))) +#define bM4_INTC_SEL46_INTSEL1 (*((volatile unsigned int*)(0x42A22284UL))) +#define bM4_INTC_SEL46_INTSEL2 (*((volatile unsigned int*)(0x42A22288UL))) +#define bM4_INTC_SEL46_INTSEL3 (*((volatile unsigned int*)(0x42A2228CUL))) +#define bM4_INTC_SEL46_INTSEL4 (*((volatile unsigned int*)(0x42A22290UL))) +#define bM4_INTC_SEL46_INTSEL5 (*((volatile unsigned int*)(0x42A22294UL))) +#define bM4_INTC_SEL46_INTSEL6 (*((volatile unsigned int*)(0x42A22298UL))) +#define bM4_INTC_SEL46_INTSEL7 (*((volatile unsigned int*)(0x42A2229CUL))) +#define bM4_INTC_SEL46_INTSEL8 (*((volatile unsigned int*)(0x42A222A0UL))) +#define bM4_INTC_SEL47_INTSEL0 (*((volatile unsigned int*)(0x42A22300UL))) +#define bM4_INTC_SEL47_INTSEL1 (*((volatile unsigned int*)(0x42A22304UL))) +#define bM4_INTC_SEL47_INTSEL2 (*((volatile unsigned int*)(0x42A22308UL))) +#define bM4_INTC_SEL47_INTSEL3 (*((volatile unsigned int*)(0x42A2230CUL))) +#define bM4_INTC_SEL47_INTSEL4 (*((volatile unsigned int*)(0x42A22310UL))) +#define bM4_INTC_SEL47_INTSEL5 (*((volatile unsigned int*)(0x42A22314UL))) +#define bM4_INTC_SEL47_INTSEL6 (*((volatile unsigned int*)(0x42A22318UL))) +#define bM4_INTC_SEL47_INTSEL7 (*((volatile unsigned int*)(0x42A2231CUL))) +#define bM4_INTC_SEL47_INTSEL8 (*((volatile unsigned int*)(0x42A22320UL))) +#define bM4_INTC_SEL48_INTSEL0 (*((volatile unsigned int*)(0x42A22380UL))) +#define bM4_INTC_SEL48_INTSEL1 (*((volatile unsigned int*)(0x42A22384UL))) +#define bM4_INTC_SEL48_INTSEL2 (*((volatile unsigned int*)(0x42A22388UL))) +#define bM4_INTC_SEL48_INTSEL3 (*((volatile unsigned int*)(0x42A2238CUL))) +#define bM4_INTC_SEL48_INTSEL4 (*((volatile unsigned int*)(0x42A22390UL))) +#define bM4_INTC_SEL48_INTSEL5 (*((volatile unsigned int*)(0x42A22394UL))) +#define bM4_INTC_SEL48_INTSEL6 (*((volatile unsigned int*)(0x42A22398UL))) +#define bM4_INTC_SEL48_INTSEL7 (*((volatile unsigned int*)(0x42A2239CUL))) +#define bM4_INTC_SEL48_INTSEL8 (*((volatile unsigned int*)(0x42A223A0UL))) +#define bM4_INTC_SEL49_INTSEL0 (*((volatile unsigned int*)(0x42A22400UL))) +#define bM4_INTC_SEL49_INTSEL1 (*((volatile unsigned int*)(0x42A22404UL))) +#define bM4_INTC_SEL49_INTSEL2 (*((volatile unsigned int*)(0x42A22408UL))) +#define bM4_INTC_SEL49_INTSEL3 (*((volatile unsigned int*)(0x42A2240CUL))) +#define bM4_INTC_SEL49_INTSEL4 (*((volatile unsigned int*)(0x42A22410UL))) +#define bM4_INTC_SEL49_INTSEL5 (*((volatile unsigned int*)(0x42A22414UL))) +#define bM4_INTC_SEL49_INTSEL6 (*((volatile unsigned int*)(0x42A22418UL))) +#define bM4_INTC_SEL49_INTSEL7 (*((volatile unsigned int*)(0x42A2241CUL))) +#define bM4_INTC_SEL49_INTSEL8 (*((volatile unsigned int*)(0x42A22420UL))) +#define bM4_INTC_SEL50_INTSEL0 (*((volatile unsigned int*)(0x42A22480UL))) +#define bM4_INTC_SEL50_INTSEL1 (*((volatile unsigned int*)(0x42A22484UL))) +#define bM4_INTC_SEL50_INTSEL2 (*((volatile unsigned int*)(0x42A22488UL))) +#define bM4_INTC_SEL50_INTSEL3 (*((volatile unsigned int*)(0x42A2248CUL))) +#define bM4_INTC_SEL50_INTSEL4 (*((volatile unsigned int*)(0x42A22490UL))) +#define bM4_INTC_SEL50_INTSEL5 (*((volatile unsigned int*)(0x42A22494UL))) +#define bM4_INTC_SEL50_INTSEL6 (*((volatile unsigned int*)(0x42A22498UL))) +#define bM4_INTC_SEL50_INTSEL7 (*((volatile unsigned int*)(0x42A2249CUL))) +#define bM4_INTC_SEL50_INTSEL8 (*((volatile unsigned int*)(0x42A224A0UL))) +#define bM4_INTC_SEL51_INTSEL0 (*((volatile unsigned int*)(0x42A22500UL))) +#define bM4_INTC_SEL51_INTSEL1 (*((volatile unsigned int*)(0x42A22504UL))) +#define bM4_INTC_SEL51_INTSEL2 (*((volatile unsigned int*)(0x42A22508UL))) +#define bM4_INTC_SEL51_INTSEL3 (*((volatile unsigned int*)(0x42A2250CUL))) +#define bM4_INTC_SEL51_INTSEL4 (*((volatile unsigned int*)(0x42A22510UL))) +#define bM4_INTC_SEL51_INTSEL5 (*((volatile unsigned int*)(0x42A22514UL))) +#define bM4_INTC_SEL51_INTSEL6 (*((volatile unsigned int*)(0x42A22518UL))) +#define bM4_INTC_SEL51_INTSEL7 (*((volatile unsigned int*)(0x42A2251CUL))) +#define bM4_INTC_SEL51_INTSEL8 (*((volatile unsigned int*)(0x42A22520UL))) +#define bM4_INTC_SEL52_INTSEL0 (*((volatile unsigned int*)(0x42A22580UL))) +#define bM4_INTC_SEL52_INTSEL1 (*((volatile unsigned int*)(0x42A22584UL))) +#define bM4_INTC_SEL52_INTSEL2 (*((volatile unsigned int*)(0x42A22588UL))) +#define bM4_INTC_SEL52_INTSEL3 (*((volatile unsigned int*)(0x42A2258CUL))) +#define bM4_INTC_SEL52_INTSEL4 (*((volatile unsigned int*)(0x42A22590UL))) +#define bM4_INTC_SEL52_INTSEL5 (*((volatile unsigned int*)(0x42A22594UL))) +#define bM4_INTC_SEL52_INTSEL6 (*((volatile unsigned int*)(0x42A22598UL))) +#define bM4_INTC_SEL52_INTSEL7 (*((volatile unsigned int*)(0x42A2259CUL))) +#define bM4_INTC_SEL52_INTSEL8 (*((volatile unsigned int*)(0x42A225A0UL))) +#define bM4_INTC_SEL53_INTSEL0 (*((volatile unsigned int*)(0x42A22600UL))) +#define bM4_INTC_SEL53_INTSEL1 (*((volatile unsigned int*)(0x42A22604UL))) +#define bM4_INTC_SEL53_INTSEL2 (*((volatile unsigned int*)(0x42A22608UL))) +#define bM4_INTC_SEL53_INTSEL3 (*((volatile unsigned int*)(0x42A2260CUL))) +#define bM4_INTC_SEL53_INTSEL4 (*((volatile unsigned int*)(0x42A22610UL))) +#define bM4_INTC_SEL53_INTSEL5 (*((volatile unsigned int*)(0x42A22614UL))) +#define bM4_INTC_SEL53_INTSEL6 (*((volatile unsigned int*)(0x42A22618UL))) +#define bM4_INTC_SEL53_INTSEL7 (*((volatile unsigned int*)(0x42A2261CUL))) +#define bM4_INTC_SEL53_INTSEL8 (*((volatile unsigned int*)(0x42A22620UL))) +#define bM4_INTC_SEL54_INTSEL0 (*((volatile unsigned int*)(0x42A22680UL))) +#define bM4_INTC_SEL54_INTSEL1 (*((volatile unsigned int*)(0x42A22684UL))) +#define bM4_INTC_SEL54_INTSEL2 (*((volatile unsigned int*)(0x42A22688UL))) +#define bM4_INTC_SEL54_INTSEL3 (*((volatile unsigned int*)(0x42A2268CUL))) +#define bM4_INTC_SEL54_INTSEL4 (*((volatile unsigned int*)(0x42A22690UL))) +#define bM4_INTC_SEL54_INTSEL5 (*((volatile unsigned int*)(0x42A22694UL))) +#define bM4_INTC_SEL54_INTSEL6 (*((volatile unsigned int*)(0x42A22698UL))) +#define bM4_INTC_SEL54_INTSEL7 (*((volatile unsigned int*)(0x42A2269CUL))) +#define bM4_INTC_SEL54_INTSEL8 (*((volatile unsigned int*)(0x42A226A0UL))) +#define bM4_INTC_SEL55_INTSEL0 (*((volatile unsigned int*)(0x42A22700UL))) +#define bM4_INTC_SEL55_INTSEL1 (*((volatile unsigned int*)(0x42A22704UL))) +#define bM4_INTC_SEL55_INTSEL2 (*((volatile unsigned int*)(0x42A22708UL))) +#define bM4_INTC_SEL55_INTSEL3 (*((volatile unsigned int*)(0x42A2270CUL))) +#define bM4_INTC_SEL55_INTSEL4 (*((volatile unsigned int*)(0x42A22710UL))) +#define bM4_INTC_SEL55_INTSEL5 (*((volatile unsigned int*)(0x42A22714UL))) +#define bM4_INTC_SEL55_INTSEL6 (*((volatile unsigned int*)(0x42A22718UL))) +#define bM4_INTC_SEL55_INTSEL7 (*((volatile unsigned int*)(0x42A2271CUL))) +#define bM4_INTC_SEL55_INTSEL8 (*((volatile unsigned int*)(0x42A22720UL))) +#define bM4_INTC_SEL56_INTSEL0 (*((volatile unsigned int*)(0x42A22780UL))) +#define bM4_INTC_SEL56_INTSEL1 (*((volatile unsigned int*)(0x42A22784UL))) +#define bM4_INTC_SEL56_INTSEL2 (*((volatile unsigned int*)(0x42A22788UL))) +#define bM4_INTC_SEL56_INTSEL3 (*((volatile unsigned int*)(0x42A2278CUL))) +#define bM4_INTC_SEL56_INTSEL4 (*((volatile unsigned int*)(0x42A22790UL))) +#define bM4_INTC_SEL56_INTSEL5 (*((volatile unsigned int*)(0x42A22794UL))) +#define bM4_INTC_SEL56_INTSEL6 (*((volatile unsigned int*)(0x42A22798UL))) +#define bM4_INTC_SEL56_INTSEL7 (*((volatile unsigned int*)(0x42A2279CUL))) +#define bM4_INTC_SEL56_INTSEL8 (*((volatile unsigned int*)(0x42A227A0UL))) +#define bM4_INTC_SEL57_INTSEL0 (*((volatile unsigned int*)(0x42A22800UL))) +#define bM4_INTC_SEL57_INTSEL1 (*((volatile unsigned int*)(0x42A22804UL))) +#define bM4_INTC_SEL57_INTSEL2 (*((volatile unsigned int*)(0x42A22808UL))) +#define bM4_INTC_SEL57_INTSEL3 (*((volatile unsigned int*)(0x42A2280CUL))) +#define bM4_INTC_SEL57_INTSEL4 (*((volatile unsigned int*)(0x42A22810UL))) +#define bM4_INTC_SEL57_INTSEL5 (*((volatile unsigned int*)(0x42A22814UL))) +#define bM4_INTC_SEL57_INTSEL6 (*((volatile unsigned int*)(0x42A22818UL))) +#define bM4_INTC_SEL57_INTSEL7 (*((volatile unsigned int*)(0x42A2281CUL))) +#define bM4_INTC_SEL57_INTSEL8 (*((volatile unsigned int*)(0x42A22820UL))) +#define bM4_INTC_SEL58_INTSEL0 (*((volatile unsigned int*)(0x42A22880UL))) +#define bM4_INTC_SEL58_INTSEL1 (*((volatile unsigned int*)(0x42A22884UL))) +#define bM4_INTC_SEL58_INTSEL2 (*((volatile unsigned int*)(0x42A22888UL))) +#define bM4_INTC_SEL58_INTSEL3 (*((volatile unsigned int*)(0x42A2288CUL))) +#define bM4_INTC_SEL58_INTSEL4 (*((volatile unsigned int*)(0x42A22890UL))) +#define bM4_INTC_SEL58_INTSEL5 (*((volatile unsigned int*)(0x42A22894UL))) +#define bM4_INTC_SEL58_INTSEL6 (*((volatile unsigned int*)(0x42A22898UL))) +#define bM4_INTC_SEL58_INTSEL7 (*((volatile unsigned int*)(0x42A2289CUL))) +#define bM4_INTC_SEL58_INTSEL8 (*((volatile unsigned int*)(0x42A228A0UL))) +#define bM4_INTC_SEL59_INTSEL0 (*((volatile unsigned int*)(0x42A22900UL))) +#define bM4_INTC_SEL59_INTSEL1 (*((volatile unsigned int*)(0x42A22904UL))) +#define bM4_INTC_SEL59_INTSEL2 (*((volatile unsigned int*)(0x42A22908UL))) +#define bM4_INTC_SEL59_INTSEL3 (*((volatile unsigned int*)(0x42A2290CUL))) +#define bM4_INTC_SEL59_INTSEL4 (*((volatile unsigned int*)(0x42A22910UL))) +#define bM4_INTC_SEL59_INTSEL5 (*((volatile unsigned int*)(0x42A22914UL))) +#define bM4_INTC_SEL59_INTSEL6 (*((volatile unsigned int*)(0x42A22918UL))) +#define bM4_INTC_SEL59_INTSEL7 (*((volatile unsigned int*)(0x42A2291CUL))) +#define bM4_INTC_SEL59_INTSEL8 (*((volatile unsigned int*)(0x42A22920UL))) +#define bM4_INTC_SEL60_INTSEL0 (*((volatile unsigned int*)(0x42A22980UL))) +#define bM4_INTC_SEL60_INTSEL1 (*((volatile unsigned int*)(0x42A22984UL))) +#define bM4_INTC_SEL60_INTSEL2 (*((volatile unsigned int*)(0x42A22988UL))) +#define bM4_INTC_SEL60_INTSEL3 (*((volatile unsigned int*)(0x42A2298CUL))) +#define bM4_INTC_SEL60_INTSEL4 (*((volatile unsigned int*)(0x42A22990UL))) +#define bM4_INTC_SEL60_INTSEL5 (*((volatile unsigned int*)(0x42A22994UL))) +#define bM4_INTC_SEL60_INTSEL6 (*((volatile unsigned int*)(0x42A22998UL))) +#define bM4_INTC_SEL60_INTSEL7 (*((volatile unsigned int*)(0x42A2299CUL))) +#define bM4_INTC_SEL60_INTSEL8 (*((volatile unsigned int*)(0x42A229A0UL))) +#define bM4_INTC_SEL61_INTSEL0 (*((volatile unsigned int*)(0x42A22A00UL))) +#define bM4_INTC_SEL61_INTSEL1 (*((volatile unsigned int*)(0x42A22A04UL))) +#define bM4_INTC_SEL61_INTSEL2 (*((volatile unsigned int*)(0x42A22A08UL))) +#define bM4_INTC_SEL61_INTSEL3 (*((volatile unsigned int*)(0x42A22A0CUL))) +#define bM4_INTC_SEL61_INTSEL4 (*((volatile unsigned int*)(0x42A22A10UL))) +#define bM4_INTC_SEL61_INTSEL5 (*((volatile unsigned int*)(0x42A22A14UL))) +#define bM4_INTC_SEL61_INTSEL6 (*((volatile unsigned int*)(0x42A22A18UL))) +#define bM4_INTC_SEL61_INTSEL7 (*((volatile unsigned int*)(0x42A22A1CUL))) +#define bM4_INTC_SEL61_INTSEL8 (*((volatile unsigned int*)(0x42A22A20UL))) +#define bM4_INTC_SEL62_INTSEL0 (*((volatile unsigned int*)(0x42A22A80UL))) +#define bM4_INTC_SEL62_INTSEL1 (*((volatile unsigned int*)(0x42A22A84UL))) +#define bM4_INTC_SEL62_INTSEL2 (*((volatile unsigned int*)(0x42A22A88UL))) +#define bM4_INTC_SEL62_INTSEL3 (*((volatile unsigned int*)(0x42A22A8CUL))) +#define bM4_INTC_SEL62_INTSEL4 (*((volatile unsigned int*)(0x42A22A90UL))) +#define bM4_INTC_SEL62_INTSEL5 (*((volatile unsigned int*)(0x42A22A94UL))) +#define bM4_INTC_SEL62_INTSEL6 (*((volatile unsigned int*)(0x42A22A98UL))) +#define bM4_INTC_SEL62_INTSEL7 (*((volatile unsigned int*)(0x42A22A9CUL))) +#define bM4_INTC_SEL62_INTSEL8 (*((volatile unsigned int*)(0x42A22AA0UL))) +#define bM4_INTC_SEL63_INTSEL0 (*((volatile unsigned int*)(0x42A22B00UL))) +#define bM4_INTC_SEL63_INTSEL1 (*((volatile unsigned int*)(0x42A22B04UL))) +#define bM4_INTC_SEL63_INTSEL2 (*((volatile unsigned int*)(0x42A22B08UL))) +#define bM4_INTC_SEL63_INTSEL3 (*((volatile unsigned int*)(0x42A22B0CUL))) +#define bM4_INTC_SEL63_INTSEL4 (*((volatile unsigned int*)(0x42A22B10UL))) +#define bM4_INTC_SEL63_INTSEL5 (*((volatile unsigned int*)(0x42A22B14UL))) +#define bM4_INTC_SEL63_INTSEL6 (*((volatile unsigned int*)(0x42A22B18UL))) +#define bM4_INTC_SEL63_INTSEL7 (*((volatile unsigned int*)(0x42A22B1CUL))) +#define bM4_INTC_SEL63_INTSEL8 (*((volatile unsigned int*)(0x42A22B20UL))) +#define bM4_INTC_SEL64_INTSEL0 (*((volatile unsigned int*)(0x42A22B80UL))) +#define bM4_INTC_SEL64_INTSEL1 (*((volatile unsigned int*)(0x42A22B84UL))) +#define bM4_INTC_SEL64_INTSEL2 (*((volatile unsigned int*)(0x42A22B88UL))) +#define bM4_INTC_SEL64_INTSEL3 (*((volatile unsigned int*)(0x42A22B8CUL))) +#define bM4_INTC_SEL64_INTSEL4 (*((volatile unsigned int*)(0x42A22B90UL))) +#define bM4_INTC_SEL64_INTSEL5 (*((volatile unsigned int*)(0x42A22B94UL))) +#define bM4_INTC_SEL64_INTSEL6 (*((volatile unsigned int*)(0x42A22B98UL))) +#define bM4_INTC_SEL64_INTSEL7 (*((volatile unsigned int*)(0x42A22B9CUL))) +#define bM4_INTC_SEL64_INTSEL8 (*((volatile unsigned int*)(0x42A22BA0UL))) +#define bM4_INTC_SEL65_INTSEL0 (*((volatile unsigned int*)(0x42A22C00UL))) +#define bM4_INTC_SEL65_INTSEL1 (*((volatile unsigned int*)(0x42A22C04UL))) +#define bM4_INTC_SEL65_INTSEL2 (*((volatile unsigned int*)(0x42A22C08UL))) +#define bM4_INTC_SEL65_INTSEL3 (*((volatile unsigned int*)(0x42A22C0CUL))) +#define bM4_INTC_SEL65_INTSEL4 (*((volatile unsigned int*)(0x42A22C10UL))) +#define bM4_INTC_SEL65_INTSEL5 (*((volatile unsigned int*)(0x42A22C14UL))) +#define bM4_INTC_SEL65_INTSEL6 (*((volatile unsigned int*)(0x42A22C18UL))) +#define bM4_INTC_SEL65_INTSEL7 (*((volatile unsigned int*)(0x42A22C1CUL))) +#define bM4_INTC_SEL65_INTSEL8 (*((volatile unsigned int*)(0x42A22C20UL))) +#define bM4_INTC_SEL66_INTSEL0 (*((volatile unsigned int*)(0x42A22C80UL))) +#define bM4_INTC_SEL66_INTSEL1 (*((volatile unsigned int*)(0x42A22C84UL))) +#define bM4_INTC_SEL66_INTSEL2 (*((volatile unsigned int*)(0x42A22C88UL))) +#define bM4_INTC_SEL66_INTSEL3 (*((volatile unsigned int*)(0x42A22C8CUL))) +#define bM4_INTC_SEL66_INTSEL4 (*((volatile unsigned int*)(0x42A22C90UL))) +#define bM4_INTC_SEL66_INTSEL5 (*((volatile unsigned int*)(0x42A22C94UL))) +#define bM4_INTC_SEL66_INTSEL6 (*((volatile unsigned int*)(0x42A22C98UL))) +#define bM4_INTC_SEL66_INTSEL7 (*((volatile unsigned int*)(0x42A22C9CUL))) +#define bM4_INTC_SEL66_INTSEL8 (*((volatile unsigned int*)(0x42A22CA0UL))) +#define bM4_INTC_SEL67_INTSEL0 (*((volatile unsigned int*)(0x42A22D00UL))) +#define bM4_INTC_SEL67_INTSEL1 (*((volatile unsigned int*)(0x42A22D04UL))) +#define bM4_INTC_SEL67_INTSEL2 (*((volatile unsigned int*)(0x42A22D08UL))) +#define bM4_INTC_SEL67_INTSEL3 (*((volatile unsigned int*)(0x42A22D0CUL))) +#define bM4_INTC_SEL67_INTSEL4 (*((volatile unsigned int*)(0x42A22D10UL))) +#define bM4_INTC_SEL67_INTSEL5 (*((volatile unsigned int*)(0x42A22D14UL))) +#define bM4_INTC_SEL67_INTSEL6 (*((volatile unsigned int*)(0x42A22D18UL))) +#define bM4_INTC_SEL67_INTSEL7 (*((volatile unsigned int*)(0x42A22D1CUL))) +#define bM4_INTC_SEL67_INTSEL8 (*((volatile unsigned int*)(0x42A22D20UL))) +#define bM4_INTC_SEL68_INTSEL0 (*((volatile unsigned int*)(0x42A22D80UL))) +#define bM4_INTC_SEL68_INTSEL1 (*((volatile unsigned int*)(0x42A22D84UL))) +#define bM4_INTC_SEL68_INTSEL2 (*((volatile unsigned int*)(0x42A22D88UL))) +#define bM4_INTC_SEL68_INTSEL3 (*((volatile unsigned int*)(0x42A22D8CUL))) +#define bM4_INTC_SEL68_INTSEL4 (*((volatile unsigned int*)(0x42A22D90UL))) +#define bM4_INTC_SEL68_INTSEL5 (*((volatile unsigned int*)(0x42A22D94UL))) +#define bM4_INTC_SEL68_INTSEL6 (*((volatile unsigned int*)(0x42A22D98UL))) +#define bM4_INTC_SEL68_INTSEL7 (*((volatile unsigned int*)(0x42A22D9CUL))) +#define bM4_INTC_SEL68_INTSEL8 (*((volatile unsigned int*)(0x42A22DA0UL))) +#define bM4_INTC_SEL69_INTSEL0 (*((volatile unsigned int*)(0x42A22E00UL))) +#define bM4_INTC_SEL69_INTSEL1 (*((volatile unsigned int*)(0x42A22E04UL))) +#define bM4_INTC_SEL69_INTSEL2 (*((volatile unsigned int*)(0x42A22E08UL))) +#define bM4_INTC_SEL69_INTSEL3 (*((volatile unsigned int*)(0x42A22E0CUL))) +#define bM4_INTC_SEL69_INTSEL4 (*((volatile unsigned int*)(0x42A22E10UL))) +#define bM4_INTC_SEL69_INTSEL5 (*((volatile unsigned int*)(0x42A22E14UL))) +#define bM4_INTC_SEL69_INTSEL6 (*((volatile unsigned int*)(0x42A22E18UL))) +#define bM4_INTC_SEL69_INTSEL7 (*((volatile unsigned int*)(0x42A22E1CUL))) +#define bM4_INTC_SEL69_INTSEL8 (*((volatile unsigned int*)(0x42A22E20UL))) +#define bM4_INTC_SEL70_INTSEL0 (*((volatile unsigned int*)(0x42A22E80UL))) +#define bM4_INTC_SEL70_INTSEL1 (*((volatile unsigned int*)(0x42A22E84UL))) +#define bM4_INTC_SEL70_INTSEL2 (*((volatile unsigned int*)(0x42A22E88UL))) +#define bM4_INTC_SEL70_INTSEL3 (*((volatile unsigned int*)(0x42A22E8CUL))) +#define bM4_INTC_SEL70_INTSEL4 (*((volatile unsigned int*)(0x42A22E90UL))) +#define bM4_INTC_SEL70_INTSEL5 (*((volatile unsigned int*)(0x42A22E94UL))) +#define bM4_INTC_SEL70_INTSEL6 (*((volatile unsigned int*)(0x42A22E98UL))) +#define bM4_INTC_SEL70_INTSEL7 (*((volatile unsigned int*)(0x42A22E9CUL))) +#define bM4_INTC_SEL70_INTSEL8 (*((volatile unsigned int*)(0x42A22EA0UL))) +#define bM4_INTC_SEL71_INTSEL0 (*((volatile unsigned int*)(0x42A22F00UL))) +#define bM4_INTC_SEL71_INTSEL1 (*((volatile unsigned int*)(0x42A22F04UL))) +#define bM4_INTC_SEL71_INTSEL2 (*((volatile unsigned int*)(0x42A22F08UL))) +#define bM4_INTC_SEL71_INTSEL3 (*((volatile unsigned int*)(0x42A22F0CUL))) +#define bM4_INTC_SEL71_INTSEL4 (*((volatile unsigned int*)(0x42A22F10UL))) +#define bM4_INTC_SEL71_INTSEL5 (*((volatile unsigned int*)(0x42A22F14UL))) +#define bM4_INTC_SEL71_INTSEL6 (*((volatile unsigned int*)(0x42A22F18UL))) +#define bM4_INTC_SEL71_INTSEL7 (*((volatile unsigned int*)(0x42A22F1CUL))) +#define bM4_INTC_SEL71_INTSEL8 (*((volatile unsigned int*)(0x42A22F20UL))) +#define bM4_INTC_SEL72_INTSEL0 (*((volatile unsigned int*)(0x42A22F80UL))) +#define bM4_INTC_SEL72_INTSEL1 (*((volatile unsigned int*)(0x42A22F84UL))) +#define bM4_INTC_SEL72_INTSEL2 (*((volatile unsigned int*)(0x42A22F88UL))) +#define bM4_INTC_SEL72_INTSEL3 (*((volatile unsigned int*)(0x42A22F8CUL))) +#define bM4_INTC_SEL72_INTSEL4 (*((volatile unsigned int*)(0x42A22F90UL))) +#define bM4_INTC_SEL72_INTSEL5 (*((volatile unsigned int*)(0x42A22F94UL))) +#define bM4_INTC_SEL72_INTSEL6 (*((volatile unsigned int*)(0x42A22F98UL))) +#define bM4_INTC_SEL72_INTSEL7 (*((volatile unsigned int*)(0x42A22F9CUL))) +#define bM4_INTC_SEL72_INTSEL8 (*((volatile unsigned int*)(0x42A22FA0UL))) +#define bM4_INTC_SEL73_INTSEL0 (*((volatile unsigned int*)(0x42A23000UL))) +#define bM4_INTC_SEL73_INTSEL1 (*((volatile unsigned int*)(0x42A23004UL))) +#define bM4_INTC_SEL73_INTSEL2 (*((volatile unsigned int*)(0x42A23008UL))) +#define bM4_INTC_SEL73_INTSEL3 (*((volatile unsigned int*)(0x42A2300CUL))) +#define bM4_INTC_SEL73_INTSEL4 (*((volatile unsigned int*)(0x42A23010UL))) +#define bM4_INTC_SEL73_INTSEL5 (*((volatile unsigned int*)(0x42A23014UL))) +#define bM4_INTC_SEL73_INTSEL6 (*((volatile unsigned int*)(0x42A23018UL))) +#define bM4_INTC_SEL73_INTSEL7 (*((volatile unsigned int*)(0x42A2301CUL))) +#define bM4_INTC_SEL73_INTSEL8 (*((volatile unsigned int*)(0x42A23020UL))) +#define bM4_INTC_SEL74_INTSEL0 (*((volatile unsigned int*)(0x42A23080UL))) +#define bM4_INTC_SEL74_INTSEL1 (*((volatile unsigned int*)(0x42A23084UL))) +#define bM4_INTC_SEL74_INTSEL2 (*((volatile unsigned int*)(0x42A23088UL))) +#define bM4_INTC_SEL74_INTSEL3 (*((volatile unsigned int*)(0x42A2308CUL))) +#define bM4_INTC_SEL74_INTSEL4 (*((volatile unsigned int*)(0x42A23090UL))) +#define bM4_INTC_SEL74_INTSEL5 (*((volatile unsigned int*)(0x42A23094UL))) +#define bM4_INTC_SEL74_INTSEL6 (*((volatile unsigned int*)(0x42A23098UL))) +#define bM4_INTC_SEL74_INTSEL7 (*((volatile unsigned int*)(0x42A2309CUL))) +#define bM4_INTC_SEL74_INTSEL8 (*((volatile unsigned int*)(0x42A230A0UL))) +#define bM4_INTC_SEL75_INTSEL0 (*((volatile unsigned int*)(0x42A23100UL))) +#define bM4_INTC_SEL75_INTSEL1 (*((volatile unsigned int*)(0x42A23104UL))) +#define bM4_INTC_SEL75_INTSEL2 (*((volatile unsigned int*)(0x42A23108UL))) +#define bM4_INTC_SEL75_INTSEL3 (*((volatile unsigned int*)(0x42A2310CUL))) +#define bM4_INTC_SEL75_INTSEL4 (*((volatile unsigned int*)(0x42A23110UL))) +#define bM4_INTC_SEL75_INTSEL5 (*((volatile unsigned int*)(0x42A23114UL))) +#define bM4_INTC_SEL75_INTSEL6 (*((volatile unsigned int*)(0x42A23118UL))) +#define bM4_INTC_SEL75_INTSEL7 (*((volatile unsigned int*)(0x42A2311CUL))) +#define bM4_INTC_SEL75_INTSEL8 (*((volatile unsigned int*)(0x42A23120UL))) +#define bM4_INTC_SEL76_INTSEL0 (*((volatile unsigned int*)(0x42A23180UL))) +#define bM4_INTC_SEL76_INTSEL1 (*((volatile unsigned int*)(0x42A23184UL))) +#define bM4_INTC_SEL76_INTSEL2 (*((volatile unsigned int*)(0x42A23188UL))) +#define bM4_INTC_SEL76_INTSEL3 (*((volatile unsigned int*)(0x42A2318CUL))) +#define bM4_INTC_SEL76_INTSEL4 (*((volatile unsigned int*)(0x42A23190UL))) +#define bM4_INTC_SEL76_INTSEL5 (*((volatile unsigned int*)(0x42A23194UL))) +#define bM4_INTC_SEL76_INTSEL6 (*((volatile unsigned int*)(0x42A23198UL))) +#define bM4_INTC_SEL76_INTSEL7 (*((volatile unsigned int*)(0x42A2319CUL))) +#define bM4_INTC_SEL76_INTSEL8 (*((volatile unsigned int*)(0x42A231A0UL))) +#define bM4_INTC_SEL77_INTSEL0 (*((volatile unsigned int*)(0x42A23200UL))) +#define bM4_INTC_SEL77_INTSEL1 (*((volatile unsigned int*)(0x42A23204UL))) +#define bM4_INTC_SEL77_INTSEL2 (*((volatile unsigned int*)(0x42A23208UL))) +#define bM4_INTC_SEL77_INTSEL3 (*((volatile unsigned int*)(0x42A2320CUL))) +#define bM4_INTC_SEL77_INTSEL4 (*((volatile unsigned int*)(0x42A23210UL))) +#define bM4_INTC_SEL77_INTSEL5 (*((volatile unsigned int*)(0x42A23214UL))) +#define bM4_INTC_SEL77_INTSEL6 (*((volatile unsigned int*)(0x42A23218UL))) +#define bM4_INTC_SEL77_INTSEL7 (*((volatile unsigned int*)(0x42A2321CUL))) +#define bM4_INTC_SEL77_INTSEL8 (*((volatile unsigned int*)(0x42A23220UL))) +#define bM4_INTC_SEL78_INTSEL0 (*((volatile unsigned int*)(0x42A23280UL))) +#define bM4_INTC_SEL78_INTSEL1 (*((volatile unsigned int*)(0x42A23284UL))) +#define bM4_INTC_SEL78_INTSEL2 (*((volatile unsigned int*)(0x42A23288UL))) +#define bM4_INTC_SEL78_INTSEL3 (*((volatile unsigned int*)(0x42A2328CUL))) +#define bM4_INTC_SEL78_INTSEL4 (*((volatile unsigned int*)(0x42A23290UL))) +#define bM4_INTC_SEL78_INTSEL5 (*((volatile unsigned int*)(0x42A23294UL))) +#define bM4_INTC_SEL78_INTSEL6 (*((volatile unsigned int*)(0x42A23298UL))) +#define bM4_INTC_SEL78_INTSEL7 (*((volatile unsigned int*)(0x42A2329CUL))) +#define bM4_INTC_SEL78_INTSEL8 (*((volatile unsigned int*)(0x42A232A0UL))) +#define bM4_INTC_SEL79_INTSEL0 (*((volatile unsigned int*)(0x42A23300UL))) +#define bM4_INTC_SEL79_INTSEL1 (*((volatile unsigned int*)(0x42A23304UL))) +#define bM4_INTC_SEL79_INTSEL2 (*((volatile unsigned int*)(0x42A23308UL))) +#define bM4_INTC_SEL79_INTSEL3 (*((volatile unsigned int*)(0x42A2330CUL))) +#define bM4_INTC_SEL79_INTSEL4 (*((volatile unsigned int*)(0x42A23310UL))) +#define bM4_INTC_SEL79_INTSEL5 (*((volatile unsigned int*)(0x42A23314UL))) +#define bM4_INTC_SEL79_INTSEL6 (*((volatile unsigned int*)(0x42A23318UL))) +#define bM4_INTC_SEL79_INTSEL7 (*((volatile unsigned int*)(0x42A2331CUL))) +#define bM4_INTC_SEL79_INTSEL8 (*((volatile unsigned int*)(0x42A23320UL))) +#define bM4_INTC_SEL80_INTSEL0 (*((volatile unsigned int*)(0x42A23380UL))) +#define bM4_INTC_SEL80_INTSEL1 (*((volatile unsigned int*)(0x42A23384UL))) +#define bM4_INTC_SEL80_INTSEL2 (*((volatile unsigned int*)(0x42A23388UL))) +#define bM4_INTC_SEL80_INTSEL3 (*((volatile unsigned int*)(0x42A2338CUL))) +#define bM4_INTC_SEL80_INTSEL4 (*((volatile unsigned int*)(0x42A23390UL))) +#define bM4_INTC_SEL80_INTSEL5 (*((volatile unsigned int*)(0x42A23394UL))) +#define bM4_INTC_SEL80_INTSEL6 (*((volatile unsigned int*)(0x42A23398UL))) +#define bM4_INTC_SEL80_INTSEL7 (*((volatile unsigned int*)(0x42A2339CUL))) +#define bM4_INTC_SEL80_INTSEL8 (*((volatile unsigned int*)(0x42A233A0UL))) +#define bM4_INTC_SEL81_INTSEL0 (*((volatile unsigned int*)(0x42A23400UL))) +#define bM4_INTC_SEL81_INTSEL1 (*((volatile unsigned int*)(0x42A23404UL))) +#define bM4_INTC_SEL81_INTSEL2 (*((volatile unsigned int*)(0x42A23408UL))) +#define bM4_INTC_SEL81_INTSEL3 (*((volatile unsigned int*)(0x42A2340CUL))) +#define bM4_INTC_SEL81_INTSEL4 (*((volatile unsigned int*)(0x42A23410UL))) +#define bM4_INTC_SEL81_INTSEL5 (*((volatile unsigned int*)(0x42A23414UL))) +#define bM4_INTC_SEL81_INTSEL6 (*((volatile unsigned int*)(0x42A23418UL))) +#define bM4_INTC_SEL81_INTSEL7 (*((volatile unsigned int*)(0x42A2341CUL))) +#define bM4_INTC_SEL81_INTSEL8 (*((volatile unsigned int*)(0x42A23420UL))) +#define bM4_INTC_SEL82_INTSEL0 (*((volatile unsigned int*)(0x42A23480UL))) +#define bM4_INTC_SEL82_INTSEL1 (*((volatile unsigned int*)(0x42A23484UL))) +#define bM4_INTC_SEL82_INTSEL2 (*((volatile unsigned int*)(0x42A23488UL))) +#define bM4_INTC_SEL82_INTSEL3 (*((volatile unsigned int*)(0x42A2348CUL))) +#define bM4_INTC_SEL82_INTSEL4 (*((volatile unsigned int*)(0x42A23490UL))) +#define bM4_INTC_SEL82_INTSEL5 (*((volatile unsigned int*)(0x42A23494UL))) +#define bM4_INTC_SEL82_INTSEL6 (*((volatile unsigned int*)(0x42A23498UL))) +#define bM4_INTC_SEL82_INTSEL7 (*((volatile unsigned int*)(0x42A2349CUL))) +#define bM4_INTC_SEL82_INTSEL8 (*((volatile unsigned int*)(0x42A234A0UL))) +#define bM4_INTC_SEL83_INTSEL0 (*((volatile unsigned int*)(0x42A23500UL))) +#define bM4_INTC_SEL83_INTSEL1 (*((volatile unsigned int*)(0x42A23504UL))) +#define bM4_INTC_SEL83_INTSEL2 (*((volatile unsigned int*)(0x42A23508UL))) +#define bM4_INTC_SEL83_INTSEL3 (*((volatile unsigned int*)(0x42A2350CUL))) +#define bM4_INTC_SEL83_INTSEL4 (*((volatile unsigned int*)(0x42A23510UL))) +#define bM4_INTC_SEL83_INTSEL5 (*((volatile unsigned int*)(0x42A23514UL))) +#define bM4_INTC_SEL83_INTSEL6 (*((volatile unsigned int*)(0x42A23518UL))) +#define bM4_INTC_SEL83_INTSEL7 (*((volatile unsigned int*)(0x42A2351CUL))) +#define bM4_INTC_SEL83_INTSEL8 (*((volatile unsigned int*)(0x42A23520UL))) +#define bM4_INTC_SEL84_INTSEL0 (*((volatile unsigned int*)(0x42A23580UL))) +#define bM4_INTC_SEL84_INTSEL1 (*((volatile unsigned int*)(0x42A23584UL))) +#define bM4_INTC_SEL84_INTSEL2 (*((volatile unsigned int*)(0x42A23588UL))) +#define bM4_INTC_SEL84_INTSEL3 (*((volatile unsigned int*)(0x42A2358CUL))) +#define bM4_INTC_SEL84_INTSEL4 (*((volatile unsigned int*)(0x42A23590UL))) +#define bM4_INTC_SEL84_INTSEL5 (*((volatile unsigned int*)(0x42A23594UL))) +#define bM4_INTC_SEL84_INTSEL6 (*((volatile unsigned int*)(0x42A23598UL))) +#define bM4_INTC_SEL84_INTSEL7 (*((volatile unsigned int*)(0x42A2359CUL))) +#define bM4_INTC_SEL84_INTSEL8 (*((volatile unsigned int*)(0x42A235A0UL))) +#define bM4_INTC_SEL85_INTSEL0 (*((volatile unsigned int*)(0x42A23600UL))) +#define bM4_INTC_SEL85_INTSEL1 (*((volatile unsigned int*)(0x42A23604UL))) +#define bM4_INTC_SEL85_INTSEL2 (*((volatile unsigned int*)(0x42A23608UL))) +#define bM4_INTC_SEL85_INTSEL3 (*((volatile unsigned int*)(0x42A2360CUL))) +#define bM4_INTC_SEL85_INTSEL4 (*((volatile unsigned int*)(0x42A23610UL))) +#define bM4_INTC_SEL85_INTSEL5 (*((volatile unsigned int*)(0x42A23614UL))) +#define bM4_INTC_SEL85_INTSEL6 (*((volatile unsigned int*)(0x42A23618UL))) +#define bM4_INTC_SEL85_INTSEL7 (*((volatile unsigned int*)(0x42A2361CUL))) +#define bM4_INTC_SEL85_INTSEL8 (*((volatile unsigned int*)(0x42A23620UL))) +#define bM4_INTC_SEL86_INTSEL0 (*((volatile unsigned int*)(0x42A23680UL))) +#define bM4_INTC_SEL86_INTSEL1 (*((volatile unsigned int*)(0x42A23684UL))) +#define bM4_INTC_SEL86_INTSEL2 (*((volatile unsigned int*)(0x42A23688UL))) +#define bM4_INTC_SEL86_INTSEL3 (*((volatile unsigned int*)(0x42A2368CUL))) +#define bM4_INTC_SEL86_INTSEL4 (*((volatile unsigned int*)(0x42A23690UL))) +#define bM4_INTC_SEL86_INTSEL5 (*((volatile unsigned int*)(0x42A23694UL))) +#define bM4_INTC_SEL86_INTSEL6 (*((volatile unsigned int*)(0x42A23698UL))) +#define bM4_INTC_SEL86_INTSEL7 (*((volatile unsigned int*)(0x42A2369CUL))) +#define bM4_INTC_SEL86_INTSEL8 (*((volatile unsigned int*)(0x42A236A0UL))) +#define bM4_INTC_SEL87_INTSEL0 (*((volatile unsigned int*)(0x42A23700UL))) +#define bM4_INTC_SEL87_INTSEL1 (*((volatile unsigned int*)(0x42A23704UL))) +#define bM4_INTC_SEL87_INTSEL2 (*((volatile unsigned int*)(0x42A23708UL))) +#define bM4_INTC_SEL87_INTSEL3 (*((volatile unsigned int*)(0x42A2370CUL))) +#define bM4_INTC_SEL87_INTSEL4 (*((volatile unsigned int*)(0x42A23710UL))) +#define bM4_INTC_SEL87_INTSEL5 (*((volatile unsigned int*)(0x42A23714UL))) +#define bM4_INTC_SEL87_INTSEL6 (*((volatile unsigned int*)(0x42A23718UL))) +#define bM4_INTC_SEL87_INTSEL7 (*((volatile unsigned int*)(0x42A2371CUL))) +#define bM4_INTC_SEL87_INTSEL8 (*((volatile unsigned int*)(0x42A23720UL))) +#define bM4_INTC_SEL88_INTSEL0 (*((volatile unsigned int*)(0x42A23780UL))) +#define bM4_INTC_SEL88_INTSEL1 (*((volatile unsigned int*)(0x42A23784UL))) +#define bM4_INTC_SEL88_INTSEL2 (*((volatile unsigned int*)(0x42A23788UL))) +#define bM4_INTC_SEL88_INTSEL3 (*((volatile unsigned int*)(0x42A2378CUL))) +#define bM4_INTC_SEL88_INTSEL4 (*((volatile unsigned int*)(0x42A23790UL))) +#define bM4_INTC_SEL88_INTSEL5 (*((volatile unsigned int*)(0x42A23794UL))) +#define bM4_INTC_SEL88_INTSEL6 (*((volatile unsigned int*)(0x42A23798UL))) +#define bM4_INTC_SEL88_INTSEL7 (*((volatile unsigned int*)(0x42A2379CUL))) +#define bM4_INTC_SEL88_INTSEL8 (*((volatile unsigned int*)(0x42A237A0UL))) +#define bM4_INTC_SEL89_INTSEL0 (*((volatile unsigned int*)(0x42A23800UL))) +#define bM4_INTC_SEL89_INTSEL1 (*((volatile unsigned int*)(0x42A23804UL))) +#define bM4_INTC_SEL89_INTSEL2 (*((volatile unsigned int*)(0x42A23808UL))) +#define bM4_INTC_SEL89_INTSEL3 (*((volatile unsigned int*)(0x42A2380CUL))) +#define bM4_INTC_SEL89_INTSEL4 (*((volatile unsigned int*)(0x42A23810UL))) +#define bM4_INTC_SEL89_INTSEL5 (*((volatile unsigned int*)(0x42A23814UL))) +#define bM4_INTC_SEL89_INTSEL6 (*((volatile unsigned int*)(0x42A23818UL))) +#define bM4_INTC_SEL89_INTSEL7 (*((volatile unsigned int*)(0x42A2381CUL))) +#define bM4_INTC_SEL89_INTSEL8 (*((volatile unsigned int*)(0x42A23820UL))) +#define bM4_INTC_SEL90_INTSEL0 (*((volatile unsigned int*)(0x42A23880UL))) +#define bM4_INTC_SEL90_INTSEL1 (*((volatile unsigned int*)(0x42A23884UL))) +#define bM4_INTC_SEL90_INTSEL2 (*((volatile unsigned int*)(0x42A23888UL))) +#define bM4_INTC_SEL90_INTSEL3 (*((volatile unsigned int*)(0x42A2388CUL))) +#define bM4_INTC_SEL90_INTSEL4 (*((volatile unsigned int*)(0x42A23890UL))) +#define bM4_INTC_SEL90_INTSEL5 (*((volatile unsigned int*)(0x42A23894UL))) +#define bM4_INTC_SEL90_INTSEL6 (*((volatile unsigned int*)(0x42A23898UL))) +#define bM4_INTC_SEL90_INTSEL7 (*((volatile unsigned int*)(0x42A2389CUL))) +#define bM4_INTC_SEL90_INTSEL8 (*((volatile unsigned int*)(0x42A238A0UL))) +#define bM4_INTC_SEL91_INTSEL0 (*((volatile unsigned int*)(0x42A23900UL))) +#define bM4_INTC_SEL91_INTSEL1 (*((volatile unsigned int*)(0x42A23904UL))) +#define bM4_INTC_SEL91_INTSEL2 (*((volatile unsigned int*)(0x42A23908UL))) +#define bM4_INTC_SEL91_INTSEL3 (*((volatile unsigned int*)(0x42A2390CUL))) +#define bM4_INTC_SEL91_INTSEL4 (*((volatile unsigned int*)(0x42A23910UL))) +#define bM4_INTC_SEL91_INTSEL5 (*((volatile unsigned int*)(0x42A23914UL))) +#define bM4_INTC_SEL91_INTSEL6 (*((volatile unsigned int*)(0x42A23918UL))) +#define bM4_INTC_SEL91_INTSEL7 (*((volatile unsigned int*)(0x42A2391CUL))) +#define bM4_INTC_SEL91_INTSEL8 (*((volatile unsigned int*)(0x42A23920UL))) +#define bM4_INTC_SEL92_INTSEL0 (*((volatile unsigned int*)(0x42A23980UL))) +#define bM4_INTC_SEL92_INTSEL1 (*((volatile unsigned int*)(0x42A23984UL))) +#define bM4_INTC_SEL92_INTSEL2 (*((volatile unsigned int*)(0x42A23988UL))) +#define bM4_INTC_SEL92_INTSEL3 (*((volatile unsigned int*)(0x42A2398CUL))) +#define bM4_INTC_SEL92_INTSEL4 (*((volatile unsigned int*)(0x42A23990UL))) +#define bM4_INTC_SEL92_INTSEL5 (*((volatile unsigned int*)(0x42A23994UL))) +#define bM4_INTC_SEL92_INTSEL6 (*((volatile unsigned int*)(0x42A23998UL))) +#define bM4_INTC_SEL92_INTSEL7 (*((volatile unsigned int*)(0x42A2399CUL))) +#define bM4_INTC_SEL92_INTSEL8 (*((volatile unsigned int*)(0x42A239A0UL))) +#define bM4_INTC_SEL93_INTSEL0 (*((volatile unsigned int*)(0x42A23A00UL))) +#define bM4_INTC_SEL93_INTSEL1 (*((volatile unsigned int*)(0x42A23A04UL))) +#define bM4_INTC_SEL93_INTSEL2 (*((volatile unsigned int*)(0x42A23A08UL))) +#define bM4_INTC_SEL93_INTSEL3 (*((volatile unsigned int*)(0x42A23A0CUL))) +#define bM4_INTC_SEL93_INTSEL4 (*((volatile unsigned int*)(0x42A23A10UL))) +#define bM4_INTC_SEL93_INTSEL5 (*((volatile unsigned int*)(0x42A23A14UL))) +#define bM4_INTC_SEL93_INTSEL6 (*((volatile unsigned int*)(0x42A23A18UL))) +#define bM4_INTC_SEL93_INTSEL7 (*((volatile unsigned int*)(0x42A23A1CUL))) +#define bM4_INTC_SEL93_INTSEL8 (*((volatile unsigned int*)(0x42A23A20UL))) +#define bM4_INTC_SEL94_INTSEL0 (*((volatile unsigned int*)(0x42A23A80UL))) +#define bM4_INTC_SEL94_INTSEL1 (*((volatile unsigned int*)(0x42A23A84UL))) +#define bM4_INTC_SEL94_INTSEL2 (*((volatile unsigned int*)(0x42A23A88UL))) +#define bM4_INTC_SEL94_INTSEL3 (*((volatile unsigned int*)(0x42A23A8CUL))) +#define bM4_INTC_SEL94_INTSEL4 (*((volatile unsigned int*)(0x42A23A90UL))) +#define bM4_INTC_SEL94_INTSEL5 (*((volatile unsigned int*)(0x42A23A94UL))) +#define bM4_INTC_SEL94_INTSEL6 (*((volatile unsigned int*)(0x42A23A98UL))) +#define bM4_INTC_SEL94_INTSEL7 (*((volatile unsigned int*)(0x42A23A9CUL))) +#define bM4_INTC_SEL94_INTSEL8 (*((volatile unsigned int*)(0x42A23AA0UL))) +#define bM4_INTC_SEL95_INTSEL0 (*((volatile unsigned int*)(0x42A23B00UL))) +#define bM4_INTC_SEL95_INTSEL1 (*((volatile unsigned int*)(0x42A23B04UL))) +#define bM4_INTC_SEL95_INTSEL2 (*((volatile unsigned int*)(0x42A23B08UL))) +#define bM4_INTC_SEL95_INTSEL3 (*((volatile unsigned int*)(0x42A23B0CUL))) +#define bM4_INTC_SEL95_INTSEL4 (*((volatile unsigned int*)(0x42A23B10UL))) +#define bM4_INTC_SEL95_INTSEL5 (*((volatile unsigned int*)(0x42A23B14UL))) +#define bM4_INTC_SEL95_INTSEL6 (*((volatile unsigned int*)(0x42A23B18UL))) +#define bM4_INTC_SEL95_INTSEL7 (*((volatile unsigned int*)(0x42A23B1CUL))) +#define bM4_INTC_SEL95_INTSEL8 (*((volatile unsigned int*)(0x42A23B20UL))) +#define bM4_INTC_SEL96_INTSEL0 (*((volatile unsigned int*)(0x42A23B80UL))) +#define bM4_INTC_SEL96_INTSEL1 (*((volatile unsigned int*)(0x42A23B84UL))) +#define bM4_INTC_SEL96_INTSEL2 (*((volatile unsigned int*)(0x42A23B88UL))) +#define bM4_INTC_SEL96_INTSEL3 (*((volatile unsigned int*)(0x42A23B8CUL))) +#define bM4_INTC_SEL96_INTSEL4 (*((volatile unsigned int*)(0x42A23B90UL))) +#define bM4_INTC_SEL96_INTSEL5 (*((volatile unsigned int*)(0x42A23B94UL))) +#define bM4_INTC_SEL96_INTSEL6 (*((volatile unsigned int*)(0x42A23B98UL))) +#define bM4_INTC_SEL96_INTSEL7 (*((volatile unsigned int*)(0x42A23B9CUL))) +#define bM4_INTC_SEL96_INTSEL8 (*((volatile unsigned int*)(0x42A23BA0UL))) +#define bM4_INTC_SEL97_INTSEL0 (*((volatile unsigned int*)(0x42A23C00UL))) +#define bM4_INTC_SEL97_INTSEL1 (*((volatile unsigned int*)(0x42A23C04UL))) +#define bM4_INTC_SEL97_INTSEL2 (*((volatile unsigned int*)(0x42A23C08UL))) +#define bM4_INTC_SEL97_INTSEL3 (*((volatile unsigned int*)(0x42A23C0CUL))) +#define bM4_INTC_SEL97_INTSEL4 (*((volatile unsigned int*)(0x42A23C10UL))) +#define bM4_INTC_SEL97_INTSEL5 (*((volatile unsigned int*)(0x42A23C14UL))) +#define bM4_INTC_SEL97_INTSEL6 (*((volatile unsigned int*)(0x42A23C18UL))) +#define bM4_INTC_SEL97_INTSEL7 (*((volatile unsigned int*)(0x42A23C1CUL))) +#define bM4_INTC_SEL97_INTSEL8 (*((volatile unsigned int*)(0x42A23C20UL))) +#define bM4_INTC_SEL98_INTSEL0 (*((volatile unsigned int*)(0x42A23C80UL))) +#define bM4_INTC_SEL98_INTSEL1 (*((volatile unsigned int*)(0x42A23C84UL))) +#define bM4_INTC_SEL98_INTSEL2 (*((volatile unsigned int*)(0x42A23C88UL))) +#define bM4_INTC_SEL98_INTSEL3 (*((volatile unsigned int*)(0x42A23C8CUL))) +#define bM4_INTC_SEL98_INTSEL4 (*((volatile unsigned int*)(0x42A23C90UL))) +#define bM4_INTC_SEL98_INTSEL5 (*((volatile unsigned int*)(0x42A23C94UL))) +#define bM4_INTC_SEL98_INTSEL6 (*((volatile unsigned int*)(0x42A23C98UL))) +#define bM4_INTC_SEL98_INTSEL7 (*((volatile unsigned int*)(0x42A23C9CUL))) +#define bM4_INTC_SEL98_INTSEL8 (*((volatile unsigned int*)(0x42A23CA0UL))) +#define bM4_INTC_SEL99_INTSEL0 (*((volatile unsigned int*)(0x42A23D00UL))) +#define bM4_INTC_SEL99_INTSEL1 (*((volatile unsigned int*)(0x42A23D04UL))) +#define bM4_INTC_SEL99_INTSEL2 (*((volatile unsigned int*)(0x42A23D08UL))) +#define bM4_INTC_SEL99_INTSEL3 (*((volatile unsigned int*)(0x42A23D0CUL))) +#define bM4_INTC_SEL99_INTSEL4 (*((volatile unsigned int*)(0x42A23D10UL))) +#define bM4_INTC_SEL99_INTSEL5 (*((volatile unsigned int*)(0x42A23D14UL))) +#define bM4_INTC_SEL99_INTSEL6 (*((volatile unsigned int*)(0x42A23D18UL))) +#define bM4_INTC_SEL99_INTSEL7 (*((volatile unsigned int*)(0x42A23D1CUL))) +#define bM4_INTC_SEL99_INTSEL8 (*((volatile unsigned int*)(0x42A23D20UL))) +#define bM4_INTC_SEL100_INTSEL0 (*((volatile unsigned int*)(0x42A23D80UL))) +#define bM4_INTC_SEL100_INTSEL1 (*((volatile unsigned int*)(0x42A23D84UL))) +#define bM4_INTC_SEL100_INTSEL2 (*((volatile unsigned int*)(0x42A23D88UL))) +#define bM4_INTC_SEL100_INTSEL3 (*((volatile unsigned int*)(0x42A23D8CUL))) +#define bM4_INTC_SEL100_INTSEL4 (*((volatile unsigned int*)(0x42A23D90UL))) +#define bM4_INTC_SEL100_INTSEL5 (*((volatile unsigned int*)(0x42A23D94UL))) +#define bM4_INTC_SEL100_INTSEL6 (*((volatile unsigned int*)(0x42A23D98UL))) +#define bM4_INTC_SEL100_INTSEL7 (*((volatile unsigned int*)(0x42A23D9CUL))) +#define bM4_INTC_SEL100_INTSEL8 (*((volatile unsigned int*)(0x42A23DA0UL))) +#define bM4_INTC_SEL101_INTSEL0 (*((volatile unsigned int*)(0x42A23E00UL))) +#define bM4_INTC_SEL101_INTSEL1 (*((volatile unsigned int*)(0x42A23E04UL))) +#define bM4_INTC_SEL101_INTSEL2 (*((volatile unsigned int*)(0x42A23E08UL))) +#define bM4_INTC_SEL101_INTSEL3 (*((volatile unsigned int*)(0x42A23E0CUL))) +#define bM4_INTC_SEL101_INTSEL4 (*((volatile unsigned int*)(0x42A23E10UL))) +#define bM4_INTC_SEL101_INTSEL5 (*((volatile unsigned int*)(0x42A23E14UL))) +#define bM4_INTC_SEL101_INTSEL6 (*((volatile unsigned int*)(0x42A23E18UL))) +#define bM4_INTC_SEL101_INTSEL7 (*((volatile unsigned int*)(0x42A23E1CUL))) +#define bM4_INTC_SEL101_INTSEL8 (*((volatile unsigned int*)(0x42A23E20UL))) +#define bM4_INTC_SEL102_INTSEL0 (*((volatile unsigned int*)(0x42A23E80UL))) +#define bM4_INTC_SEL102_INTSEL1 (*((volatile unsigned int*)(0x42A23E84UL))) +#define bM4_INTC_SEL102_INTSEL2 (*((volatile unsigned int*)(0x42A23E88UL))) +#define bM4_INTC_SEL102_INTSEL3 (*((volatile unsigned int*)(0x42A23E8CUL))) +#define bM4_INTC_SEL102_INTSEL4 (*((volatile unsigned int*)(0x42A23E90UL))) +#define bM4_INTC_SEL102_INTSEL5 (*((volatile unsigned int*)(0x42A23E94UL))) +#define bM4_INTC_SEL102_INTSEL6 (*((volatile unsigned int*)(0x42A23E98UL))) +#define bM4_INTC_SEL102_INTSEL7 (*((volatile unsigned int*)(0x42A23E9CUL))) +#define bM4_INTC_SEL102_INTSEL8 (*((volatile unsigned int*)(0x42A23EA0UL))) +#define bM4_INTC_SEL103_INTSEL0 (*((volatile unsigned int*)(0x42A23F00UL))) +#define bM4_INTC_SEL103_INTSEL1 (*((volatile unsigned int*)(0x42A23F04UL))) +#define bM4_INTC_SEL103_INTSEL2 (*((volatile unsigned int*)(0x42A23F08UL))) +#define bM4_INTC_SEL103_INTSEL3 (*((volatile unsigned int*)(0x42A23F0CUL))) +#define bM4_INTC_SEL103_INTSEL4 (*((volatile unsigned int*)(0x42A23F10UL))) +#define bM4_INTC_SEL103_INTSEL5 (*((volatile unsigned int*)(0x42A23F14UL))) +#define bM4_INTC_SEL103_INTSEL6 (*((volatile unsigned int*)(0x42A23F18UL))) +#define bM4_INTC_SEL103_INTSEL7 (*((volatile unsigned int*)(0x42A23F1CUL))) +#define bM4_INTC_SEL103_INTSEL8 (*((volatile unsigned int*)(0x42A23F20UL))) +#define bM4_INTC_SEL104_INTSEL0 (*((volatile unsigned int*)(0x42A23F80UL))) +#define bM4_INTC_SEL104_INTSEL1 (*((volatile unsigned int*)(0x42A23F84UL))) +#define bM4_INTC_SEL104_INTSEL2 (*((volatile unsigned int*)(0x42A23F88UL))) +#define bM4_INTC_SEL104_INTSEL3 (*((volatile unsigned int*)(0x42A23F8CUL))) +#define bM4_INTC_SEL104_INTSEL4 (*((volatile unsigned int*)(0x42A23F90UL))) +#define bM4_INTC_SEL104_INTSEL5 (*((volatile unsigned int*)(0x42A23F94UL))) +#define bM4_INTC_SEL104_INTSEL6 (*((volatile unsigned int*)(0x42A23F98UL))) +#define bM4_INTC_SEL104_INTSEL7 (*((volatile unsigned int*)(0x42A23F9CUL))) +#define bM4_INTC_SEL104_INTSEL8 (*((volatile unsigned int*)(0x42A23FA0UL))) +#define bM4_INTC_SEL105_INTSEL0 (*((volatile unsigned int*)(0x42A24000UL))) +#define bM4_INTC_SEL105_INTSEL1 (*((volatile unsigned int*)(0x42A24004UL))) +#define bM4_INTC_SEL105_INTSEL2 (*((volatile unsigned int*)(0x42A24008UL))) +#define bM4_INTC_SEL105_INTSEL3 (*((volatile unsigned int*)(0x42A2400CUL))) +#define bM4_INTC_SEL105_INTSEL4 (*((volatile unsigned int*)(0x42A24010UL))) +#define bM4_INTC_SEL105_INTSEL5 (*((volatile unsigned int*)(0x42A24014UL))) +#define bM4_INTC_SEL105_INTSEL6 (*((volatile unsigned int*)(0x42A24018UL))) +#define bM4_INTC_SEL105_INTSEL7 (*((volatile unsigned int*)(0x42A2401CUL))) +#define bM4_INTC_SEL105_INTSEL8 (*((volatile unsigned int*)(0x42A24020UL))) +#define bM4_INTC_SEL106_INTSEL0 (*((volatile unsigned int*)(0x42A24080UL))) +#define bM4_INTC_SEL106_INTSEL1 (*((volatile unsigned int*)(0x42A24084UL))) +#define bM4_INTC_SEL106_INTSEL2 (*((volatile unsigned int*)(0x42A24088UL))) +#define bM4_INTC_SEL106_INTSEL3 (*((volatile unsigned int*)(0x42A2408CUL))) +#define bM4_INTC_SEL106_INTSEL4 (*((volatile unsigned int*)(0x42A24090UL))) +#define bM4_INTC_SEL106_INTSEL5 (*((volatile unsigned int*)(0x42A24094UL))) +#define bM4_INTC_SEL106_INTSEL6 (*((volatile unsigned int*)(0x42A24098UL))) +#define bM4_INTC_SEL106_INTSEL7 (*((volatile unsigned int*)(0x42A2409CUL))) +#define bM4_INTC_SEL106_INTSEL8 (*((volatile unsigned int*)(0x42A240A0UL))) +#define bM4_INTC_SEL107_INTSEL0 (*((volatile unsigned int*)(0x42A24100UL))) +#define bM4_INTC_SEL107_INTSEL1 (*((volatile unsigned int*)(0x42A24104UL))) +#define bM4_INTC_SEL107_INTSEL2 (*((volatile unsigned int*)(0x42A24108UL))) +#define bM4_INTC_SEL107_INTSEL3 (*((volatile unsigned int*)(0x42A2410CUL))) +#define bM4_INTC_SEL107_INTSEL4 (*((volatile unsigned int*)(0x42A24110UL))) +#define bM4_INTC_SEL107_INTSEL5 (*((volatile unsigned int*)(0x42A24114UL))) +#define bM4_INTC_SEL107_INTSEL6 (*((volatile unsigned int*)(0x42A24118UL))) +#define bM4_INTC_SEL107_INTSEL7 (*((volatile unsigned int*)(0x42A2411CUL))) +#define bM4_INTC_SEL107_INTSEL8 (*((volatile unsigned int*)(0x42A24120UL))) +#define bM4_INTC_SEL108_INTSEL0 (*((volatile unsigned int*)(0x42A24180UL))) +#define bM4_INTC_SEL108_INTSEL1 (*((volatile unsigned int*)(0x42A24184UL))) +#define bM4_INTC_SEL108_INTSEL2 (*((volatile unsigned int*)(0x42A24188UL))) +#define bM4_INTC_SEL108_INTSEL3 (*((volatile unsigned int*)(0x42A2418CUL))) +#define bM4_INTC_SEL108_INTSEL4 (*((volatile unsigned int*)(0x42A24190UL))) +#define bM4_INTC_SEL108_INTSEL5 (*((volatile unsigned int*)(0x42A24194UL))) +#define bM4_INTC_SEL108_INTSEL6 (*((volatile unsigned int*)(0x42A24198UL))) +#define bM4_INTC_SEL108_INTSEL7 (*((volatile unsigned int*)(0x42A2419CUL))) +#define bM4_INTC_SEL108_INTSEL8 (*((volatile unsigned int*)(0x42A241A0UL))) +#define bM4_INTC_SEL109_INTSEL0 (*((volatile unsigned int*)(0x42A24200UL))) +#define bM4_INTC_SEL109_INTSEL1 (*((volatile unsigned int*)(0x42A24204UL))) +#define bM4_INTC_SEL109_INTSEL2 (*((volatile unsigned int*)(0x42A24208UL))) +#define bM4_INTC_SEL109_INTSEL3 (*((volatile unsigned int*)(0x42A2420CUL))) +#define bM4_INTC_SEL109_INTSEL4 (*((volatile unsigned int*)(0x42A24210UL))) +#define bM4_INTC_SEL109_INTSEL5 (*((volatile unsigned int*)(0x42A24214UL))) +#define bM4_INTC_SEL109_INTSEL6 (*((volatile unsigned int*)(0x42A24218UL))) +#define bM4_INTC_SEL109_INTSEL7 (*((volatile unsigned int*)(0x42A2421CUL))) +#define bM4_INTC_SEL109_INTSEL8 (*((volatile unsigned int*)(0x42A24220UL))) +#define bM4_INTC_SEL110_INTSEL0 (*((volatile unsigned int*)(0x42A24280UL))) +#define bM4_INTC_SEL110_INTSEL1 (*((volatile unsigned int*)(0x42A24284UL))) +#define bM4_INTC_SEL110_INTSEL2 (*((volatile unsigned int*)(0x42A24288UL))) +#define bM4_INTC_SEL110_INTSEL3 (*((volatile unsigned int*)(0x42A2428CUL))) +#define bM4_INTC_SEL110_INTSEL4 (*((volatile unsigned int*)(0x42A24290UL))) +#define bM4_INTC_SEL110_INTSEL5 (*((volatile unsigned int*)(0x42A24294UL))) +#define bM4_INTC_SEL110_INTSEL6 (*((volatile unsigned int*)(0x42A24298UL))) +#define bM4_INTC_SEL110_INTSEL7 (*((volatile unsigned int*)(0x42A2429CUL))) +#define bM4_INTC_SEL110_INTSEL8 (*((volatile unsigned int*)(0x42A242A0UL))) +#define bM4_INTC_SEL111_INTSEL0 (*((volatile unsigned int*)(0x42A24300UL))) +#define bM4_INTC_SEL111_INTSEL1 (*((volatile unsigned int*)(0x42A24304UL))) +#define bM4_INTC_SEL111_INTSEL2 (*((volatile unsigned int*)(0x42A24308UL))) +#define bM4_INTC_SEL111_INTSEL3 (*((volatile unsigned int*)(0x42A2430CUL))) +#define bM4_INTC_SEL111_INTSEL4 (*((volatile unsigned int*)(0x42A24310UL))) +#define bM4_INTC_SEL111_INTSEL5 (*((volatile unsigned int*)(0x42A24314UL))) +#define bM4_INTC_SEL111_INTSEL6 (*((volatile unsigned int*)(0x42A24318UL))) +#define bM4_INTC_SEL111_INTSEL7 (*((volatile unsigned int*)(0x42A2431CUL))) +#define bM4_INTC_SEL111_INTSEL8 (*((volatile unsigned int*)(0x42A24320UL))) +#define bM4_INTC_SEL112_INTSEL0 (*((volatile unsigned int*)(0x42A24380UL))) +#define bM4_INTC_SEL112_INTSEL1 (*((volatile unsigned int*)(0x42A24384UL))) +#define bM4_INTC_SEL112_INTSEL2 (*((volatile unsigned int*)(0x42A24388UL))) +#define bM4_INTC_SEL112_INTSEL3 (*((volatile unsigned int*)(0x42A2438CUL))) +#define bM4_INTC_SEL112_INTSEL4 (*((volatile unsigned int*)(0x42A24390UL))) +#define bM4_INTC_SEL112_INTSEL5 (*((volatile unsigned int*)(0x42A24394UL))) +#define bM4_INTC_SEL112_INTSEL6 (*((volatile unsigned int*)(0x42A24398UL))) +#define bM4_INTC_SEL112_INTSEL7 (*((volatile unsigned int*)(0x42A2439CUL))) +#define bM4_INTC_SEL112_INTSEL8 (*((volatile unsigned int*)(0x42A243A0UL))) +#define bM4_INTC_SEL113_INTSEL0 (*((volatile unsigned int*)(0x42A24400UL))) +#define bM4_INTC_SEL113_INTSEL1 (*((volatile unsigned int*)(0x42A24404UL))) +#define bM4_INTC_SEL113_INTSEL2 (*((volatile unsigned int*)(0x42A24408UL))) +#define bM4_INTC_SEL113_INTSEL3 (*((volatile unsigned int*)(0x42A2440CUL))) +#define bM4_INTC_SEL113_INTSEL4 (*((volatile unsigned int*)(0x42A24410UL))) +#define bM4_INTC_SEL113_INTSEL5 (*((volatile unsigned int*)(0x42A24414UL))) +#define bM4_INTC_SEL113_INTSEL6 (*((volatile unsigned int*)(0x42A24418UL))) +#define bM4_INTC_SEL113_INTSEL7 (*((volatile unsigned int*)(0x42A2441CUL))) +#define bM4_INTC_SEL113_INTSEL8 (*((volatile unsigned int*)(0x42A24420UL))) +#define bM4_INTC_SEL114_INTSEL0 (*((volatile unsigned int*)(0x42A24480UL))) +#define bM4_INTC_SEL114_INTSEL1 (*((volatile unsigned int*)(0x42A24484UL))) +#define bM4_INTC_SEL114_INTSEL2 (*((volatile unsigned int*)(0x42A24488UL))) +#define bM4_INTC_SEL114_INTSEL3 (*((volatile unsigned int*)(0x42A2448CUL))) +#define bM4_INTC_SEL114_INTSEL4 (*((volatile unsigned int*)(0x42A24490UL))) +#define bM4_INTC_SEL114_INTSEL5 (*((volatile unsigned int*)(0x42A24494UL))) +#define bM4_INTC_SEL114_INTSEL6 (*((volatile unsigned int*)(0x42A24498UL))) +#define bM4_INTC_SEL114_INTSEL7 (*((volatile unsigned int*)(0x42A2449CUL))) +#define bM4_INTC_SEL114_INTSEL8 (*((volatile unsigned int*)(0x42A244A0UL))) +#define bM4_INTC_SEL115_INTSEL0 (*((volatile unsigned int*)(0x42A24500UL))) +#define bM4_INTC_SEL115_INTSEL1 (*((volatile unsigned int*)(0x42A24504UL))) +#define bM4_INTC_SEL115_INTSEL2 (*((volatile unsigned int*)(0x42A24508UL))) +#define bM4_INTC_SEL115_INTSEL3 (*((volatile unsigned int*)(0x42A2450CUL))) +#define bM4_INTC_SEL115_INTSEL4 (*((volatile unsigned int*)(0x42A24510UL))) +#define bM4_INTC_SEL115_INTSEL5 (*((volatile unsigned int*)(0x42A24514UL))) +#define bM4_INTC_SEL115_INTSEL6 (*((volatile unsigned int*)(0x42A24518UL))) +#define bM4_INTC_SEL115_INTSEL7 (*((volatile unsigned int*)(0x42A2451CUL))) +#define bM4_INTC_SEL115_INTSEL8 (*((volatile unsigned int*)(0x42A24520UL))) +#define bM4_INTC_SEL116_INTSEL0 (*((volatile unsigned int*)(0x42A24580UL))) +#define bM4_INTC_SEL116_INTSEL1 (*((volatile unsigned int*)(0x42A24584UL))) +#define bM4_INTC_SEL116_INTSEL2 (*((volatile unsigned int*)(0x42A24588UL))) +#define bM4_INTC_SEL116_INTSEL3 (*((volatile unsigned int*)(0x42A2458CUL))) +#define bM4_INTC_SEL116_INTSEL4 (*((volatile unsigned int*)(0x42A24590UL))) +#define bM4_INTC_SEL116_INTSEL5 (*((volatile unsigned int*)(0x42A24594UL))) +#define bM4_INTC_SEL116_INTSEL6 (*((volatile unsigned int*)(0x42A24598UL))) +#define bM4_INTC_SEL116_INTSEL7 (*((volatile unsigned int*)(0x42A2459CUL))) +#define bM4_INTC_SEL116_INTSEL8 (*((volatile unsigned int*)(0x42A245A0UL))) +#define bM4_INTC_SEL117_INTSEL0 (*((volatile unsigned int*)(0x42A24600UL))) +#define bM4_INTC_SEL117_INTSEL1 (*((volatile unsigned int*)(0x42A24604UL))) +#define bM4_INTC_SEL117_INTSEL2 (*((volatile unsigned int*)(0x42A24608UL))) +#define bM4_INTC_SEL117_INTSEL3 (*((volatile unsigned int*)(0x42A2460CUL))) +#define bM4_INTC_SEL117_INTSEL4 (*((volatile unsigned int*)(0x42A24610UL))) +#define bM4_INTC_SEL117_INTSEL5 (*((volatile unsigned int*)(0x42A24614UL))) +#define bM4_INTC_SEL117_INTSEL6 (*((volatile unsigned int*)(0x42A24618UL))) +#define bM4_INTC_SEL117_INTSEL7 (*((volatile unsigned int*)(0x42A2461CUL))) +#define bM4_INTC_SEL117_INTSEL8 (*((volatile unsigned int*)(0x42A24620UL))) +#define bM4_INTC_SEL118_INTSEL0 (*((volatile unsigned int*)(0x42A24680UL))) +#define bM4_INTC_SEL118_INTSEL1 (*((volatile unsigned int*)(0x42A24684UL))) +#define bM4_INTC_SEL118_INTSEL2 (*((volatile unsigned int*)(0x42A24688UL))) +#define bM4_INTC_SEL118_INTSEL3 (*((volatile unsigned int*)(0x42A2468CUL))) +#define bM4_INTC_SEL118_INTSEL4 (*((volatile unsigned int*)(0x42A24690UL))) +#define bM4_INTC_SEL118_INTSEL5 (*((volatile unsigned int*)(0x42A24694UL))) +#define bM4_INTC_SEL118_INTSEL6 (*((volatile unsigned int*)(0x42A24698UL))) +#define bM4_INTC_SEL118_INTSEL7 (*((volatile unsigned int*)(0x42A2469CUL))) +#define bM4_INTC_SEL118_INTSEL8 (*((volatile unsigned int*)(0x42A246A0UL))) +#define bM4_INTC_SEL119_INTSEL0 (*((volatile unsigned int*)(0x42A24700UL))) +#define bM4_INTC_SEL119_INTSEL1 (*((volatile unsigned int*)(0x42A24704UL))) +#define bM4_INTC_SEL119_INTSEL2 (*((volatile unsigned int*)(0x42A24708UL))) +#define bM4_INTC_SEL119_INTSEL3 (*((volatile unsigned int*)(0x42A2470CUL))) +#define bM4_INTC_SEL119_INTSEL4 (*((volatile unsigned int*)(0x42A24710UL))) +#define bM4_INTC_SEL119_INTSEL5 (*((volatile unsigned int*)(0x42A24714UL))) +#define bM4_INTC_SEL119_INTSEL6 (*((volatile unsigned int*)(0x42A24718UL))) +#define bM4_INTC_SEL119_INTSEL7 (*((volatile unsigned int*)(0x42A2471CUL))) +#define bM4_INTC_SEL119_INTSEL8 (*((volatile unsigned int*)(0x42A24720UL))) +#define bM4_INTC_SEL120_INTSEL0 (*((volatile unsigned int*)(0x42A24780UL))) +#define bM4_INTC_SEL120_INTSEL1 (*((volatile unsigned int*)(0x42A24784UL))) +#define bM4_INTC_SEL120_INTSEL2 (*((volatile unsigned int*)(0x42A24788UL))) +#define bM4_INTC_SEL120_INTSEL3 (*((volatile unsigned int*)(0x42A2478CUL))) +#define bM4_INTC_SEL120_INTSEL4 (*((volatile unsigned int*)(0x42A24790UL))) +#define bM4_INTC_SEL120_INTSEL5 (*((volatile unsigned int*)(0x42A24794UL))) +#define bM4_INTC_SEL120_INTSEL6 (*((volatile unsigned int*)(0x42A24798UL))) +#define bM4_INTC_SEL120_INTSEL7 (*((volatile unsigned int*)(0x42A2479CUL))) +#define bM4_INTC_SEL120_INTSEL8 (*((volatile unsigned int*)(0x42A247A0UL))) +#define bM4_INTC_SEL121_INTSEL0 (*((volatile unsigned int*)(0x42A24800UL))) +#define bM4_INTC_SEL121_INTSEL1 (*((volatile unsigned int*)(0x42A24804UL))) +#define bM4_INTC_SEL121_INTSEL2 (*((volatile unsigned int*)(0x42A24808UL))) +#define bM4_INTC_SEL121_INTSEL3 (*((volatile unsigned int*)(0x42A2480CUL))) +#define bM4_INTC_SEL121_INTSEL4 (*((volatile unsigned int*)(0x42A24810UL))) +#define bM4_INTC_SEL121_INTSEL5 (*((volatile unsigned int*)(0x42A24814UL))) +#define bM4_INTC_SEL121_INTSEL6 (*((volatile unsigned int*)(0x42A24818UL))) +#define bM4_INTC_SEL121_INTSEL7 (*((volatile unsigned int*)(0x42A2481CUL))) +#define bM4_INTC_SEL121_INTSEL8 (*((volatile unsigned int*)(0x42A24820UL))) +#define bM4_INTC_SEL122_INTSEL0 (*((volatile unsigned int*)(0x42A24880UL))) +#define bM4_INTC_SEL122_INTSEL1 (*((volatile unsigned int*)(0x42A24884UL))) +#define bM4_INTC_SEL122_INTSEL2 (*((volatile unsigned int*)(0x42A24888UL))) +#define bM4_INTC_SEL122_INTSEL3 (*((volatile unsigned int*)(0x42A2488CUL))) +#define bM4_INTC_SEL122_INTSEL4 (*((volatile unsigned int*)(0x42A24890UL))) +#define bM4_INTC_SEL122_INTSEL5 (*((volatile unsigned int*)(0x42A24894UL))) +#define bM4_INTC_SEL122_INTSEL6 (*((volatile unsigned int*)(0x42A24898UL))) +#define bM4_INTC_SEL122_INTSEL7 (*((volatile unsigned int*)(0x42A2489CUL))) +#define bM4_INTC_SEL122_INTSEL8 (*((volatile unsigned int*)(0x42A248A0UL))) +#define bM4_INTC_SEL123_INTSEL0 (*((volatile unsigned int*)(0x42A24900UL))) +#define bM4_INTC_SEL123_INTSEL1 (*((volatile unsigned int*)(0x42A24904UL))) +#define bM4_INTC_SEL123_INTSEL2 (*((volatile unsigned int*)(0x42A24908UL))) +#define bM4_INTC_SEL123_INTSEL3 (*((volatile unsigned int*)(0x42A2490CUL))) +#define bM4_INTC_SEL123_INTSEL4 (*((volatile unsigned int*)(0x42A24910UL))) +#define bM4_INTC_SEL123_INTSEL5 (*((volatile unsigned int*)(0x42A24914UL))) +#define bM4_INTC_SEL123_INTSEL6 (*((volatile unsigned int*)(0x42A24918UL))) +#define bM4_INTC_SEL123_INTSEL7 (*((volatile unsigned int*)(0x42A2491CUL))) +#define bM4_INTC_SEL123_INTSEL8 (*((volatile unsigned int*)(0x42A24920UL))) +#define bM4_INTC_SEL124_INTSEL0 (*((volatile unsigned int*)(0x42A24980UL))) +#define bM4_INTC_SEL124_INTSEL1 (*((volatile unsigned int*)(0x42A24984UL))) +#define bM4_INTC_SEL124_INTSEL2 (*((volatile unsigned int*)(0x42A24988UL))) +#define bM4_INTC_SEL124_INTSEL3 (*((volatile unsigned int*)(0x42A2498CUL))) +#define bM4_INTC_SEL124_INTSEL4 (*((volatile unsigned int*)(0x42A24990UL))) +#define bM4_INTC_SEL124_INTSEL5 (*((volatile unsigned int*)(0x42A24994UL))) +#define bM4_INTC_SEL124_INTSEL6 (*((volatile unsigned int*)(0x42A24998UL))) +#define bM4_INTC_SEL124_INTSEL7 (*((volatile unsigned int*)(0x42A2499CUL))) +#define bM4_INTC_SEL124_INTSEL8 (*((volatile unsigned int*)(0x42A249A0UL))) +#define bM4_INTC_SEL125_INTSEL0 (*((volatile unsigned int*)(0x42A24A00UL))) +#define bM4_INTC_SEL125_INTSEL1 (*((volatile unsigned int*)(0x42A24A04UL))) +#define bM4_INTC_SEL125_INTSEL2 (*((volatile unsigned int*)(0x42A24A08UL))) +#define bM4_INTC_SEL125_INTSEL3 (*((volatile unsigned int*)(0x42A24A0CUL))) +#define bM4_INTC_SEL125_INTSEL4 (*((volatile unsigned int*)(0x42A24A10UL))) +#define bM4_INTC_SEL125_INTSEL5 (*((volatile unsigned int*)(0x42A24A14UL))) +#define bM4_INTC_SEL125_INTSEL6 (*((volatile unsigned int*)(0x42A24A18UL))) +#define bM4_INTC_SEL125_INTSEL7 (*((volatile unsigned int*)(0x42A24A1CUL))) +#define bM4_INTC_SEL125_INTSEL8 (*((volatile unsigned int*)(0x42A24A20UL))) +#define bM4_INTC_SEL126_INTSEL0 (*((volatile unsigned int*)(0x42A24A80UL))) +#define bM4_INTC_SEL126_INTSEL1 (*((volatile unsigned int*)(0x42A24A84UL))) +#define bM4_INTC_SEL126_INTSEL2 (*((volatile unsigned int*)(0x42A24A88UL))) +#define bM4_INTC_SEL126_INTSEL3 (*((volatile unsigned int*)(0x42A24A8CUL))) +#define bM4_INTC_SEL126_INTSEL4 (*((volatile unsigned int*)(0x42A24A90UL))) +#define bM4_INTC_SEL126_INTSEL5 (*((volatile unsigned int*)(0x42A24A94UL))) +#define bM4_INTC_SEL126_INTSEL6 (*((volatile unsigned int*)(0x42A24A98UL))) +#define bM4_INTC_SEL126_INTSEL7 (*((volatile unsigned int*)(0x42A24A9CUL))) +#define bM4_INTC_SEL126_INTSEL8 (*((volatile unsigned int*)(0x42A24AA0UL))) +#define bM4_INTC_SEL127_INTSEL0 (*((volatile unsigned int*)(0x42A24B00UL))) +#define bM4_INTC_SEL127_INTSEL1 (*((volatile unsigned int*)(0x42A24B04UL))) +#define bM4_INTC_SEL127_INTSEL2 (*((volatile unsigned int*)(0x42A24B08UL))) +#define bM4_INTC_SEL127_INTSEL3 (*((volatile unsigned int*)(0x42A24B0CUL))) +#define bM4_INTC_SEL127_INTSEL4 (*((volatile unsigned int*)(0x42A24B10UL))) +#define bM4_INTC_SEL127_INTSEL5 (*((volatile unsigned int*)(0x42A24B14UL))) +#define bM4_INTC_SEL127_INTSEL6 (*((volatile unsigned int*)(0x42A24B18UL))) +#define bM4_INTC_SEL127_INTSEL7 (*((volatile unsigned int*)(0x42A24B1CUL))) +#define bM4_INTC_SEL127_INTSEL8 (*((volatile unsigned int*)(0x42A24B20UL))) +#define bM4_INTC_VSSEL128_VSEL0 (*((volatile unsigned int*)(0x42A24B80UL))) +#define bM4_INTC_VSSEL128_VSEL1 (*((volatile unsigned int*)(0x42A24B84UL))) +#define bM4_INTC_VSSEL128_VSEL2 (*((volatile unsigned int*)(0x42A24B88UL))) +#define bM4_INTC_VSSEL128_VSEL3 (*((volatile unsigned int*)(0x42A24B8CUL))) +#define bM4_INTC_VSSEL128_VSEL4 (*((volatile unsigned int*)(0x42A24B90UL))) +#define bM4_INTC_VSSEL128_VSEL5 (*((volatile unsigned int*)(0x42A24B94UL))) +#define bM4_INTC_VSSEL128_VSEL6 (*((volatile unsigned int*)(0x42A24B98UL))) +#define bM4_INTC_VSSEL128_VSEL7 (*((volatile unsigned int*)(0x42A24B9CUL))) +#define bM4_INTC_VSSEL128_VSEL8 (*((volatile unsigned int*)(0x42A24BA0UL))) +#define bM4_INTC_VSSEL128_VSEL9 (*((volatile unsigned int*)(0x42A24BA4UL))) +#define bM4_INTC_VSSEL128_VSEL10 (*((volatile unsigned int*)(0x42A24BA8UL))) +#define bM4_INTC_VSSEL128_VSEL11 (*((volatile unsigned int*)(0x42A24BACUL))) +#define bM4_INTC_VSSEL128_VSEL12 (*((volatile unsigned int*)(0x42A24BB0UL))) +#define bM4_INTC_VSSEL128_VSEL13 (*((volatile unsigned int*)(0x42A24BB4UL))) +#define bM4_INTC_VSSEL128_VSEL14 (*((volatile unsigned int*)(0x42A24BB8UL))) +#define bM4_INTC_VSSEL128_VSEL15 (*((volatile unsigned int*)(0x42A24BBCUL))) +#define bM4_INTC_VSSEL128_VSEL16 (*((volatile unsigned int*)(0x42A24BC0UL))) +#define bM4_INTC_VSSEL128_VSEL17 (*((volatile unsigned int*)(0x42A24BC4UL))) +#define bM4_INTC_VSSEL128_VSEL18 (*((volatile unsigned int*)(0x42A24BC8UL))) +#define bM4_INTC_VSSEL128_VSEL19 (*((volatile unsigned int*)(0x42A24BCCUL))) +#define bM4_INTC_VSSEL128_VSEL20 (*((volatile unsigned int*)(0x42A24BD0UL))) +#define bM4_INTC_VSSEL128_VSEL21 (*((volatile unsigned int*)(0x42A24BD4UL))) +#define bM4_INTC_VSSEL128_VSEL22 (*((volatile unsigned int*)(0x42A24BD8UL))) +#define bM4_INTC_VSSEL128_VSEL23 (*((volatile unsigned int*)(0x42A24BDCUL))) +#define bM4_INTC_VSSEL128_VSEL24 (*((volatile unsigned int*)(0x42A24BE0UL))) +#define bM4_INTC_VSSEL128_VSEL25 (*((volatile unsigned int*)(0x42A24BE4UL))) +#define bM4_INTC_VSSEL128_VSEL26 (*((volatile unsigned int*)(0x42A24BE8UL))) +#define bM4_INTC_VSSEL128_VSEL27 (*((volatile unsigned int*)(0x42A24BECUL))) +#define bM4_INTC_VSSEL128_VSEL28 (*((volatile unsigned int*)(0x42A24BF0UL))) +#define bM4_INTC_VSSEL128_VSEL29 (*((volatile unsigned int*)(0x42A24BF4UL))) +#define bM4_INTC_VSSEL128_VSEL30 (*((volatile unsigned int*)(0x42A24BF8UL))) +#define bM4_INTC_VSSEL128_VSEL31 (*((volatile unsigned int*)(0x42A24BFCUL))) +#define bM4_INTC_VSSEL129_VSEL0 (*((volatile unsigned int*)(0x42A24C00UL))) +#define bM4_INTC_VSSEL129_VSEL1 (*((volatile unsigned int*)(0x42A24C04UL))) +#define bM4_INTC_VSSEL129_VSEL2 (*((volatile unsigned int*)(0x42A24C08UL))) +#define bM4_INTC_VSSEL129_VSEL3 (*((volatile unsigned int*)(0x42A24C0CUL))) +#define bM4_INTC_VSSEL129_VSEL4 (*((volatile unsigned int*)(0x42A24C10UL))) +#define bM4_INTC_VSSEL129_VSEL5 (*((volatile unsigned int*)(0x42A24C14UL))) +#define bM4_INTC_VSSEL129_VSEL6 (*((volatile unsigned int*)(0x42A24C18UL))) +#define bM4_INTC_VSSEL129_VSEL7 (*((volatile unsigned int*)(0x42A24C1CUL))) +#define bM4_INTC_VSSEL129_VSEL8 (*((volatile unsigned int*)(0x42A24C20UL))) +#define bM4_INTC_VSSEL129_VSEL9 (*((volatile unsigned int*)(0x42A24C24UL))) +#define bM4_INTC_VSSEL129_VSEL10 (*((volatile unsigned int*)(0x42A24C28UL))) +#define bM4_INTC_VSSEL129_VSEL11 (*((volatile unsigned int*)(0x42A24C2CUL))) +#define bM4_INTC_VSSEL129_VSEL12 (*((volatile unsigned int*)(0x42A24C30UL))) +#define bM4_INTC_VSSEL129_VSEL13 (*((volatile unsigned int*)(0x42A24C34UL))) +#define bM4_INTC_VSSEL129_VSEL14 (*((volatile unsigned int*)(0x42A24C38UL))) +#define bM4_INTC_VSSEL129_VSEL15 (*((volatile unsigned int*)(0x42A24C3CUL))) +#define bM4_INTC_VSSEL129_VSEL16 (*((volatile unsigned int*)(0x42A24C40UL))) +#define bM4_INTC_VSSEL129_VSEL17 (*((volatile unsigned int*)(0x42A24C44UL))) +#define bM4_INTC_VSSEL129_VSEL18 (*((volatile unsigned int*)(0x42A24C48UL))) +#define bM4_INTC_VSSEL129_VSEL19 (*((volatile unsigned int*)(0x42A24C4CUL))) +#define bM4_INTC_VSSEL129_VSEL20 (*((volatile unsigned int*)(0x42A24C50UL))) +#define bM4_INTC_VSSEL129_VSEL21 (*((volatile unsigned int*)(0x42A24C54UL))) +#define bM4_INTC_VSSEL129_VSEL22 (*((volatile unsigned int*)(0x42A24C58UL))) +#define bM4_INTC_VSSEL129_VSEL23 (*((volatile unsigned int*)(0x42A24C5CUL))) +#define bM4_INTC_VSSEL129_VSEL24 (*((volatile unsigned int*)(0x42A24C60UL))) +#define bM4_INTC_VSSEL129_VSEL25 (*((volatile unsigned int*)(0x42A24C64UL))) +#define bM4_INTC_VSSEL129_VSEL26 (*((volatile unsigned int*)(0x42A24C68UL))) +#define bM4_INTC_VSSEL129_VSEL27 (*((volatile unsigned int*)(0x42A24C6CUL))) +#define bM4_INTC_VSSEL129_VSEL28 (*((volatile unsigned int*)(0x42A24C70UL))) +#define bM4_INTC_VSSEL129_VSEL29 (*((volatile unsigned int*)(0x42A24C74UL))) +#define bM4_INTC_VSSEL129_VSEL30 (*((volatile unsigned int*)(0x42A24C78UL))) +#define bM4_INTC_VSSEL129_VSEL31 (*((volatile unsigned int*)(0x42A24C7CUL))) +#define bM4_INTC_VSSEL130_VSEL0 (*((volatile unsigned int*)(0x42A24C80UL))) +#define bM4_INTC_VSSEL130_VSEL1 (*((volatile unsigned int*)(0x42A24C84UL))) +#define bM4_INTC_VSSEL130_VSEL2 (*((volatile unsigned int*)(0x42A24C88UL))) +#define bM4_INTC_VSSEL130_VSEL3 (*((volatile unsigned int*)(0x42A24C8CUL))) +#define bM4_INTC_VSSEL130_VSEL4 (*((volatile unsigned int*)(0x42A24C90UL))) +#define bM4_INTC_VSSEL130_VSEL5 (*((volatile unsigned int*)(0x42A24C94UL))) +#define bM4_INTC_VSSEL130_VSEL6 (*((volatile unsigned int*)(0x42A24C98UL))) +#define bM4_INTC_VSSEL130_VSEL7 (*((volatile unsigned int*)(0x42A24C9CUL))) +#define bM4_INTC_VSSEL130_VSEL8 (*((volatile unsigned int*)(0x42A24CA0UL))) +#define bM4_INTC_VSSEL130_VSEL9 (*((volatile unsigned int*)(0x42A24CA4UL))) +#define bM4_INTC_VSSEL130_VSEL10 (*((volatile unsigned int*)(0x42A24CA8UL))) +#define bM4_INTC_VSSEL130_VSEL11 (*((volatile unsigned int*)(0x42A24CACUL))) +#define bM4_INTC_VSSEL130_VSEL12 (*((volatile unsigned int*)(0x42A24CB0UL))) +#define bM4_INTC_VSSEL130_VSEL13 (*((volatile unsigned int*)(0x42A24CB4UL))) +#define bM4_INTC_VSSEL130_VSEL14 (*((volatile unsigned int*)(0x42A24CB8UL))) +#define bM4_INTC_VSSEL130_VSEL15 (*((volatile unsigned int*)(0x42A24CBCUL))) +#define bM4_INTC_VSSEL130_VSEL16 (*((volatile unsigned int*)(0x42A24CC0UL))) +#define bM4_INTC_VSSEL130_VSEL17 (*((volatile unsigned int*)(0x42A24CC4UL))) +#define bM4_INTC_VSSEL130_VSEL18 (*((volatile unsigned int*)(0x42A24CC8UL))) +#define bM4_INTC_VSSEL130_VSEL19 (*((volatile unsigned int*)(0x42A24CCCUL))) +#define bM4_INTC_VSSEL130_VSEL20 (*((volatile unsigned int*)(0x42A24CD0UL))) +#define bM4_INTC_VSSEL130_VSEL21 (*((volatile unsigned int*)(0x42A24CD4UL))) +#define bM4_INTC_VSSEL130_VSEL22 (*((volatile unsigned int*)(0x42A24CD8UL))) +#define bM4_INTC_VSSEL130_VSEL23 (*((volatile unsigned int*)(0x42A24CDCUL))) +#define bM4_INTC_VSSEL130_VSEL24 (*((volatile unsigned int*)(0x42A24CE0UL))) +#define bM4_INTC_VSSEL130_VSEL25 (*((volatile unsigned int*)(0x42A24CE4UL))) +#define bM4_INTC_VSSEL130_VSEL26 (*((volatile unsigned int*)(0x42A24CE8UL))) +#define bM4_INTC_VSSEL130_VSEL27 (*((volatile unsigned int*)(0x42A24CECUL))) +#define bM4_INTC_VSSEL130_VSEL28 (*((volatile unsigned int*)(0x42A24CF0UL))) +#define bM4_INTC_VSSEL130_VSEL29 (*((volatile unsigned int*)(0x42A24CF4UL))) +#define bM4_INTC_VSSEL130_VSEL30 (*((volatile unsigned int*)(0x42A24CF8UL))) +#define bM4_INTC_VSSEL130_VSEL31 (*((volatile unsigned int*)(0x42A24CFCUL))) +#define bM4_INTC_VSSEL131_VSEL0 (*((volatile unsigned int*)(0x42A24D00UL))) +#define bM4_INTC_VSSEL131_VSEL1 (*((volatile unsigned int*)(0x42A24D04UL))) +#define bM4_INTC_VSSEL131_VSEL2 (*((volatile unsigned int*)(0x42A24D08UL))) +#define bM4_INTC_VSSEL131_VSEL3 (*((volatile unsigned int*)(0x42A24D0CUL))) +#define bM4_INTC_VSSEL131_VSEL4 (*((volatile unsigned int*)(0x42A24D10UL))) +#define bM4_INTC_VSSEL131_VSEL5 (*((volatile unsigned int*)(0x42A24D14UL))) +#define bM4_INTC_VSSEL131_VSEL6 (*((volatile unsigned int*)(0x42A24D18UL))) +#define bM4_INTC_VSSEL131_VSEL7 (*((volatile unsigned int*)(0x42A24D1CUL))) +#define bM4_INTC_VSSEL131_VSEL8 (*((volatile unsigned int*)(0x42A24D20UL))) +#define bM4_INTC_VSSEL131_VSEL9 (*((volatile unsigned int*)(0x42A24D24UL))) +#define bM4_INTC_VSSEL131_VSEL10 (*((volatile unsigned int*)(0x42A24D28UL))) +#define bM4_INTC_VSSEL131_VSEL11 (*((volatile unsigned int*)(0x42A24D2CUL))) +#define bM4_INTC_VSSEL131_VSEL12 (*((volatile unsigned int*)(0x42A24D30UL))) +#define bM4_INTC_VSSEL131_VSEL13 (*((volatile unsigned int*)(0x42A24D34UL))) +#define bM4_INTC_VSSEL131_VSEL14 (*((volatile unsigned int*)(0x42A24D38UL))) +#define bM4_INTC_VSSEL131_VSEL15 (*((volatile unsigned int*)(0x42A24D3CUL))) +#define bM4_INTC_VSSEL131_VSEL16 (*((volatile unsigned int*)(0x42A24D40UL))) +#define bM4_INTC_VSSEL131_VSEL17 (*((volatile unsigned int*)(0x42A24D44UL))) +#define bM4_INTC_VSSEL131_VSEL18 (*((volatile unsigned int*)(0x42A24D48UL))) +#define bM4_INTC_VSSEL131_VSEL19 (*((volatile unsigned int*)(0x42A24D4CUL))) +#define bM4_INTC_VSSEL131_VSEL20 (*((volatile unsigned int*)(0x42A24D50UL))) +#define bM4_INTC_VSSEL131_VSEL21 (*((volatile unsigned int*)(0x42A24D54UL))) +#define bM4_INTC_VSSEL131_VSEL22 (*((volatile unsigned int*)(0x42A24D58UL))) +#define bM4_INTC_VSSEL131_VSEL23 (*((volatile unsigned int*)(0x42A24D5CUL))) +#define bM4_INTC_VSSEL131_VSEL24 (*((volatile unsigned int*)(0x42A24D60UL))) +#define bM4_INTC_VSSEL131_VSEL25 (*((volatile unsigned int*)(0x42A24D64UL))) +#define bM4_INTC_VSSEL131_VSEL26 (*((volatile unsigned int*)(0x42A24D68UL))) +#define bM4_INTC_VSSEL131_VSEL27 (*((volatile unsigned int*)(0x42A24D6CUL))) +#define bM4_INTC_VSSEL131_VSEL28 (*((volatile unsigned int*)(0x42A24D70UL))) +#define bM4_INTC_VSSEL131_VSEL29 (*((volatile unsigned int*)(0x42A24D74UL))) +#define bM4_INTC_VSSEL131_VSEL30 (*((volatile unsigned int*)(0x42A24D78UL))) +#define bM4_INTC_VSSEL131_VSEL31 (*((volatile unsigned int*)(0x42A24D7CUL))) +#define bM4_INTC_VSSEL132_VSEL0 (*((volatile unsigned int*)(0x42A24D80UL))) +#define bM4_INTC_VSSEL132_VSEL1 (*((volatile unsigned int*)(0x42A24D84UL))) +#define bM4_INTC_VSSEL132_VSEL2 (*((volatile unsigned int*)(0x42A24D88UL))) +#define bM4_INTC_VSSEL132_VSEL3 (*((volatile unsigned int*)(0x42A24D8CUL))) +#define bM4_INTC_VSSEL132_VSEL4 (*((volatile unsigned int*)(0x42A24D90UL))) +#define bM4_INTC_VSSEL132_VSEL5 (*((volatile unsigned int*)(0x42A24D94UL))) +#define bM4_INTC_VSSEL132_VSEL6 (*((volatile unsigned int*)(0x42A24D98UL))) +#define bM4_INTC_VSSEL132_VSEL7 (*((volatile unsigned int*)(0x42A24D9CUL))) +#define bM4_INTC_VSSEL132_VSEL8 (*((volatile unsigned int*)(0x42A24DA0UL))) +#define bM4_INTC_VSSEL132_VSEL9 (*((volatile unsigned int*)(0x42A24DA4UL))) +#define bM4_INTC_VSSEL132_VSEL10 (*((volatile unsigned int*)(0x42A24DA8UL))) +#define bM4_INTC_VSSEL132_VSEL11 (*((volatile unsigned int*)(0x42A24DACUL))) +#define bM4_INTC_VSSEL132_VSEL12 (*((volatile unsigned int*)(0x42A24DB0UL))) +#define bM4_INTC_VSSEL132_VSEL13 (*((volatile unsigned int*)(0x42A24DB4UL))) +#define bM4_INTC_VSSEL132_VSEL14 (*((volatile unsigned int*)(0x42A24DB8UL))) +#define bM4_INTC_VSSEL132_VSEL15 (*((volatile unsigned int*)(0x42A24DBCUL))) +#define bM4_INTC_VSSEL132_VSEL16 (*((volatile unsigned int*)(0x42A24DC0UL))) +#define bM4_INTC_VSSEL132_VSEL17 (*((volatile unsigned int*)(0x42A24DC4UL))) +#define bM4_INTC_VSSEL132_VSEL18 (*((volatile unsigned int*)(0x42A24DC8UL))) +#define bM4_INTC_VSSEL132_VSEL19 (*((volatile unsigned int*)(0x42A24DCCUL))) +#define bM4_INTC_VSSEL132_VSEL20 (*((volatile unsigned int*)(0x42A24DD0UL))) +#define bM4_INTC_VSSEL132_VSEL21 (*((volatile unsigned int*)(0x42A24DD4UL))) +#define bM4_INTC_VSSEL132_VSEL22 (*((volatile unsigned int*)(0x42A24DD8UL))) +#define bM4_INTC_VSSEL132_VSEL23 (*((volatile unsigned int*)(0x42A24DDCUL))) +#define bM4_INTC_VSSEL132_VSEL24 (*((volatile unsigned int*)(0x42A24DE0UL))) +#define bM4_INTC_VSSEL132_VSEL25 (*((volatile unsigned int*)(0x42A24DE4UL))) +#define bM4_INTC_VSSEL132_VSEL26 (*((volatile unsigned int*)(0x42A24DE8UL))) +#define bM4_INTC_VSSEL132_VSEL27 (*((volatile unsigned int*)(0x42A24DECUL))) +#define bM4_INTC_VSSEL132_VSEL28 (*((volatile unsigned int*)(0x42A24DF0UL))) +#define bM4_INTC_VSSEL132_VSEL29 (*((volatile unsigned int*)(0x42A24DF4UL))) +#define bM4_INTC_VSSEL132_VSEL30 (*((volatile unsigned int*)(0x42A24DF8UL))) +#define bM4_INTC_VSSEL132_VSEL31 (*((volatile unsigned int*)(0x42A24DFCUL))) +#define bM4_INTC_VSSEL133_VSEL0 (*((volatile unsigned int*)(0x42A24E00UL))) +#define bM4_INTC_VSSEL133_VSEL1 (*((volatile unsigned int*)(0x42A24E04UL))) +#define bM4_INTC_VSSEL133_VSEL2 (*((volatile unsigned int*)(0x42A24E08UL))) +#define bM4_INTC_VSSEL133_VSEL3 (*((volatile unsigned int*)(0x42A24E0CUL))) +#define bM4_INTC_VSSEL133_VSEL4 (*((volatile unsigned int*)(0x42A24E10UL))) +#define bM4_INTC_VSSEL133_VSEL5 (*((volatile unsigned int*)(0x42A24E14UL))) +#define bM4_INTC_VSSEL133_VSEL6 (*((volatile unsigned int*)(0x42A24E18UL))) +#define bM4_INTC_VSSEL133_VSEL7 (*((volatile unsigned int*)(0x42A24E1CUL))) +#define bM4_INTC_VSSEL133_VSEL8 (*((volatile unsigned int*)(0x42A24E20UL))) +#define bM4_INTC_VSSEL133_VSEL9 (*((volatile unsigned int*)(0x42A24E24UL))) +#define bM4_INTC_VSSEL133_VSEL10 (*((volatile unsigned int*)(0x42A24E28UL))) +#define bM4_INTC_VSSEL133_VSEL11 (*((volatile unsigned int*)(0x42A24E2CUL))) +#define bM4_INTC_VSSEL133_VSEL12 (*((volatile unsigned int*)(0x42A24E30UL))) +#define bM4_INTC_VSSEL133_VSEL13 (*((volatile unsigned int*)(0x42A24E34UL))) +#define bM4_INTC_VSSEL133_VSEL14 (*((volatile unsigned int*)(0x42A24E38UL))) +#define bM4_INTC_VSSEL133_VSEL15 (*((volatile unsigned int*)(0x42A24E3CUL))) +#define bM4_INTC_VSSEL133_VSEL16 (*((volatile unsigned int*)(0x42A24E40UL))) +#define bM4_INTC_VSSEL133_VSEL17 (*((volatile unsigned int*)(0x42A24E44UL))) +#define bM4_INTC_VSSEL133_VSEL18 (*((volatile unsigned int*)(0x42A24E48UL))) +#define bM4_INTC_VSSEL133_VSEL19 (*((volatile unsigned int*)(0x42A24E4CUL))) +#define bM4_INTC_VSSEL133_VSEL20 (*((volatile unsigned int*)(0x42A24E50UL))) +#define bM4_INTC_VSSEL133_VSEL21 (*((volatile unsigned int*)(0x42A24E54UL))) +#define bM4_INTC_VSSEL133_VSEL22 (*((volatile unsigned int*)(0x42A24E58UL))) +#define bM4_INTC_VSSEL133_VSEL23 (*((volatile unsigned int*)(0x42A24E5CUL))) +#define bM4_INTC_VSSEL133_VSEL24 (*((volatile unsigned int*)(0x42A24E60UL))) +#define bM4_INTC_VSSEL133_VSEL25 (*((volatile unsigned int*)(0x42A24E64UL))) +#define bM4_INTC_VSSEL133_VSEL26 (*((volatile unsigned int*)(0x42A24E68UL))) +#define bM4_INTC_VSSEL133_VSEL27 (*((volatile unsigned int*)(0x42A24E6CUL))) +#define bM4_INTC_VSSEL133_VSEL28 (*((volatile unsigned int*)(0x42A24E70UL))) +#define bM4_INTC_VSSEL133_VSEL29 (*((volatile unsigned int*)(0x42A24E74UL))) +#define bM4_INTC_VSSEL133_VSEL30 (*((volatile unsigned int*)(0x42A24E78UL))) +#define bM4_INTC_VSSEL133_VSEL31 (*((volatile unsigned int*)(0x42A24E7CUL))) +#define bM4_INTC_VSSEL134_VSEL0 (*((volatile unsigned int*)(0x42A24E80UL))) +#define bM4_INTC_VSSEL134_VSEL1 (*((volatile unsigned int*)(0x42A24E84UL))) +#define bM4_INTC_VSSEL134_VSEL2 (*((volatile unsigned int*)(0x42A24E88UL))) +#define bM4_INTC_VSSEL134_VSEL3 (*((volatile unsigned int*)(0x42A24E8CUL))) +#define bM4_INTC_VSSEL134_VSEL4 (*((volatile unsigned int*)(0x42A24E90UL))) +#define bM4_INTC_VSSEL134_VSEL5 (*((volatile unsigned int*)(0x42A24E94UL))) +#define bM4_INTC_VSSEL134_VSEL6 (*((volatile unsigned int*)(0x42A24E98UL))) +#define bM4_INTC_VSSEL134_VSEL7 (*((volatile unsigned int*)(0x42A24E9CUL))) +#define bM4_INTC_VSSEL134_VSEL8 (*((volatile unsigned int*)(0x42A24EA0UL))) +#define bM4_INTC_VSSEL134_VSEL9 (*((volatile unsigned int*)(0x42A24EA4UL))) +#define bM4_INTC_VSSEL134_VSEL10 (*((volatile unsigned int*)(0x42A24EA8UL))) +#define bM4_INTC_VSSEL134_VSEL11 (*((volatile unsigned int*)(0x42A24EACUL))) +#define bM4_INTC_VSSEL134_VSEL12 (*((volatile unsigned int*)(0x42A24EB0UL))) +#define bM4_INTC_VSSEL134_VSEL13 (*((volatile unsigned int*)(0x42A24EB4UL))) +#define bM4_INTC_VSSEL134_VSEL14 (*((volatile unsigned int*)(0x42A24EB8UL))) +#define bM4_INTC_VSSEL134_VSEL15 (*((volatile unsigned int*)(0x42A24EBCUL))) +#define bM4_INTC_VSSEL134_VSEL16 (*((volatile unsigned int*)(0x42A24EC0UL))) +#define bM4_INTC_VSSEL134_VSEL17 (*((volatile unsigned int*)(0x42A24EC4UL))) +#define bM4_INTC_VSSEL134_VSEL18 (*((volatile unsigned int*)(0x42A24EC8UL))) +#define bM4_INTC_VSSEL134_VSEL19 (*((volatile unsigned int*)(0x42A24ECCUL))) +#define bM4_INTC_VSSEL134_VSEL20 (*((volatile unsigned int*)(0x42A24ED0UL))) +#define bM4_INTC_VSSEL134_VSEL21 (*((volatile unsigned int*)(0x42A24ED4UL))) +#define bM4_INTC_VSSEL134_VSEL22 (*((volatile unsigned int*)(0x42A24ED8UL))) +#define bM4_INTC_VSSEL134_VSEL23 (*((volatile unsigned int*)(0x42A24EDCUL))) +#define bM4_INTC_VSSEL134_VSEL24 (*((volatile unsigned int*)(0x42A24EE0UL))) +#define bM4_INTC_VSSEL134_VSEL25 (*((volatile unsigned int*)(0x42A24EE4UL))) +#define bM4_INTC_VSSEL134_VSEL26 (*((volatile unsigned int*)(0x42A24EE8UL))) +#define bM4_INTC_VSSEL134_VSEL27 (*((volatile unsigned int*)(0x42A24EECUL))) +#define bM4_INTC_VSSEL134_VSEL28 (*((volatile unsigned int*)(0x42A24EF0UL))) +#define bM4_INTC_VSSEL134_VSEL29 (*((volatile unsigned int*)(0x42A24EF4UL))) +#define bM4_INTC_VSSEL134_VSEL30 (*((volatile unsigned int*)(0x42A24EF8UL))) +#define bM4_INTC_VSSEL134_VSEL31 (*((volatile unsigned int*)(0x42A24EFCUL))) +#define bM4_INTC_VSSEL135_VSEL0 (*((volatile unsigned int*)(0x42A24F00UL))) +#define bM4_INTC_VSSEL135_VSEL1 (*((volatile unsigned int*)(0x42A24F04UL))) +#define bM4_INTC_VSSEL135_VSEL2 (*((volatile unsigned int*)(0x42A24F08UL))) +#define bM4_INTC_VSSEL135_VSEL3 (*((volatile unsigned int*)(0x42A24F0CUL))) +#define bM4_INTC_VSSEL135_VSEL4 (*((volatile unsigned int*)(0x42A24F10UL))) +#define bM4_INTC_VSSEL135_VSEL5 (*((volatile unsigned int*)(0x42A24F14UL))) +#define bM4_INTC_VSSEL135_VSEL6 (*((volatile unsigned int*)(0x42A24F18UL))) +#define bM4_INTC_VSSEL135_VSEL7 (*((volatile unsigned int*)(0x42A24F1CUL))) +#define bM4_INTC_VSSEL135_VSEL8 (*((volatile unsigned int*)(0x42A24F20UL))) +#define bM4_INTC_VSSEL135_VSEL9 (*((volatile unsigned int*)(0x42A24F24UL))) +#define bM4_INTC_VSSEL135_VSEL10 (*((volatile unsigned int*)(0x42A24F28UL))) +#define bM4_INTC_VSSEL135_VSEL11 (*((volatile unsigned int*)(0x42A24F2CUL))) +#define bM4_INTC_VSSEL135_VSEL12 (*((volatile unsigned int*)(0x42A24F30UL))) +#define bM4_INTC_VSSEL135_VSEL13 (*((volatile unsigned int*)(0x42A24F34UL))) +#define bM4_INTC_VSSEL135_VSEL14 (*((volatile unsigned int*)(0x42A24F38UL))) +#define bM4_INTC_VSSEL135_VSEL15 (*((volatile unsigned int*)(0x42A24F3CUL))) +#define bM4_INTC_VSSEL135_VSEL16 (*((volatile unsigned int*)(0x42A24F40UL))) +#define bM4_INTC_VSSEL135_VSEL17 (*((volatile unsigned int*)(0x42A24F44UL))) +#define bM4_INTC_VSSEL135_VSEL18 (*((volatile unsigned int*)(0x42A24F48UL))) +#define bM4_INTC_VSSEL135_VSEL19 (*((volatile unsigned int*)(0x42A24F4CUL))) +#define bM4_INTC_VSSEL135_VSEL20 (*((volatile unsigned int*)(0x42A24F50UL))) +#define bM4_INTC_VSSEL135_VSEL21 (*((volatile unsigned int*)(0x42A24F54UL))) +#define bM4_INTC_VSSEL135_VSEL22 (*((volatile unsigned int*)(0x42A24F58UL))) +#define bM4_INTC_VSSEL135_VSEL23 (*((volatile unsigned int*)(0x42A24F5CUL))) +#define bM4_INTC_VSSEL135_VSEL24 (*((volatile unsigned int*)(0x42A24F60UL))) +#define bM4_INTC_VSSEL135_VSEL25 (*((volatile unsigned int*)(0x42A24F64UL))) +#define bM4_INTC_VSSEL135_VSEL26 (*((volatile unsigned int*)(0x42A24F68UL))) +#define bM4_INTC_VSSEL135_VSEL27 (*((volatile unsigned int*)(0x42A24F6CUL))) +#define bM4_INTC_VSSEL135_VSEL28 (*((volatile unsigned int*)(0x42A24F70UL))) +#define bM4_INTC_VSSEL135_VSEL29 (*((volatile unsigned int*)(0x42A24F74UL))) +#define bM4_INTC_VSSEL135_VSEL30 (*((volatile unsigned int*)(0x42A24F78UL))) +#define bM4_INTC_VSSEL135_VSEL31 (*((volatile unsigned int*)(0x42A24F7CUL))) +#define bM4_INTC_VSSEL136_VSEL0 (*((volatile unsigned int*)(0x42A24F80UL))) +#define bM4_INTC_VSSEL136_VSEL1 (*((volatile unsigned int*)(0x42A24F84UL))) +#define bM4_INTC_VSSEL136_VSEL2 (*((volatile unsigned int*)(0x42A24F88UL))) +#define bM4_INTC_VSSEL136_VSEL3 (*((volatile unsigned int*)(0x42A24F8CUL))) +#define bM4_INTC_VSSEL136_VSEL4 (*((volatile unsigned int*)(0x42A24F90UL))) +#define bM4_INTC_VSSEL136_VSEL5 (*((volatile unsigned int*)(0x42A24F94UL))) +#define bM4_INTC_VSSEL136_VSEL6 (*((volatile unsigned int*)(0x42A24F98UL))) +#define bM4_INTC_VSSEL136_VSEL7 (*((volatile unsigned int*)(0x42A24F9CUL))) +#define bM4_INTC_VSSEL136_VSEL8 (*((volatile unsigned int*)(0x42A24FA0UL))) +#define bM4_INTC_VSSEL136_VSEL9 (*((volatile unsigned int*)(0x42A24FA4UL))) +#define bM4_INTC_VSSEL136_VSEL10 (*((volatile unsigned int*)(0x42A24FA8UL))) +#define bM4_INTC_VSSEL136_VSEL11 (*((volatile unsigned int*)(0x42A24FACUL))) +#define bM4_INTC_VSSEL136_VSEL12 (*((volatile unsigned int*)(0x42A24FB0UL))) +#define bM4_INTC_VSSEL136_VSEL13 (*((volatile unsigned int*)(0x42A24FB4UL))) +#define bM4_INTC_VSSEL136_VSEL14 (*((volatile unsigned int*)(0x42A24FB8UL))) +#define bM4_INTC_VSSEL136_VSEL15 (*((volatile unsigned int*)(0x42A24FBCUL))) +#define bM4_INTC_VSSEL136_VSEL16 (*((volatile unsigned int*)(0x42A24FC0UL))) +#define bM4_INTC_VSSEL136_VSEL17 (*((volatile unsigned int*)(0x42A24FC4UL))) +#define bM4_INTC_VSSEL136_VSEL18 (*((volatile unsigned int*)(0x42A24FC8UL))) +#define bM4_INTC_VSSEL136_VSEL19 (*((volatile unsigned int*)(0x42A24FCCUL))) +#define bM4_INTC_VSSEL136_VSEL20 (*((volatile unsigned int*)(0x42A24FD0UL))) +#define bM4_INTC_VSSEL136_VSEL21 (*((volatile unsigned int*)(0x42A24FD4UL))) +#define bM4_INTC_VSSEL136_VSEL22 (*((volatile unsigned int*)(0x42A24FD8UL))) +#define bM4_INTC_VSSEL136_VSEL23 (*((volatile unsigned int*)(0x42A24FDCUL))) +#define bM4_INTC_VSSEL136_VSEL24 (*((volatile unsigned int*)(0x42A24FE0UL))) +#define bM4_INTC_VSSEL136_VSEL25 (*((volatile unsigned int*)(0x42A24FE4UL))) +#define bM4_INTC_VSSEL136_VSEL26 (*((volatile unsigned int*)(0x42A24FE8UL))) +#define bM4_INTC_VSSEL136_VSEL27 (*((volatile unsigned int*)(0x42A24FECUL))) +#define bM4_INTC_VSSEL136_VSEL28 (*((volatile unsigned int*)(0x42A24FF0UL))) +#define bM4_INTC_VSSEL136_VSEL29 (*((volatile unsigned int*)(0x42A24FF4UL))) +#define bM4_INTC_VSSEL136_VSEL30 (*((volatile unsigned int*)(0x42A24FF8UL))) +#define bM4_INTC_VSSEL136_VSEL31 (*((volatile unsigned int*)(0x42A24FFCUL))) +#define bM4_INTC_VSSEL137_VSEL0 (*((volatile unsigned int*)(0x42A25000UL))) +#define bM4_INTC_VSSEL137_VSEL1 (*((volatile unsigned int*)(0x42A25004UL))) +#define bM4_INTC_VSSEL137_VSEL2 (*((volatile unsigned int*)(0x42A25008UL))) +#define bM4_INTC_VSSEL137_VSEL3 (*((volatile unsigned int*)(0x42A2500CUL))) +#define bM4_INTC_VSSEL137_VSEL4 (*((volatile unsigned int*)(0x42A25010UL))) +#define bM4_INTC_VSSEL137_VSEL5 (*((volatile unsigned int*)(0x42A25014UL))) +#define bM4_INTC_VSSEL137_VSEL6 (*((volatile unsigned int*)(0x42A25018UL))) +#define bM4_INTC_VSSEL137_VSEL7 (*((volatile unsigned int*)(0x42A2501CUL))) +#define bM4_INTC_VSSEL137_VSEL8 (*((volatile unsigned int*)(0x42A25020UL))) +#define bM4_INTC_VSSEL137_VSEL9 (*((volatile unsigned int*)(0x42A25024UL))) +#define bM4_INTC_VSSEL137_VSEL10 (*((volatile unsigned int*)(0x42A25028UL))) +#define bM4_INTC_VSSEL137_VSEL11 (*((volatile unsigned int*)(0x42A2502CUL))) +#define bM4_INTC_VSSEL137_VSEL12 (*((volatile unsigned int*)(0x42A25030UL))) +#define bM4_INTC_VSSEL137_VSEL13 (*((volatile unsigned int*)(0x42A25034UL))) +#define bM4_INTC_VSSEL137_VSEL14 (*((volatile unsigned int*)(0x42A25038UL))) +#define bM4_INTC_VSSEL137_VSEL15 (*((volatile unsigned int*)(0x42A2503CUL))) +#define bM4_INTC_VSSEL137_VSEL16 (*((volatile unsigned int*)(0x42A25040UL))) +#define bM4_INTC_VSSEL137_VSEL17 (*((volatile unsigned int*)(0x42A25044UL))) +#define bM4_INTC_VSSEL137_VSEL18 (*((volatile unsigned int*)(0x42A25048UL))) +#define bM4_INTC_VSSEL137_VSEL19 (*((volatile unsigned int*)(0x42A2504CUL))) +#define bM4_INTC_VSSEL137_VSEL20 (*((volatile unsigned int*)(0x42A25050UL))) +#define bM4_INTC_VSSEL137_VSEL21 (*((volatile unsigned int*)(0x42A25054UL))) +#define bM4_INTC_VSSEL137_VSEL22 (*((volatile unsigned int*)(0x42A25058UL))) +#define bM4_INTC_VSSEL137_VSEL23 (*((volatile unsigned int*)(0x42A2505CUL))) +#define bM4_INTC_VSSEL137_VSEL24 (*((volatile unsigned int*)(0x42A25060UL))) +#define bM4_INTC_VSSEL137_VSEL25 (*((volatile unsigned int*)(0x42A25064UL))) +#define bM4_INTC_VSSEL137_VSEL26 (*((volatile unsigned int*)(0x42A25068UL))) +#define bM4_INTC_VSSEL137_VSEL27 (*((volatile unsigned int*)(0x42A2506CUL))) +#define bM4_INTC_VSSEL137_VSEL28 (*((volatile unsigned int*)(0x42A25070UL))) +#define bM4_INTC_VSSEL137_VSEL29 (*((volatile unsigned int*)(0x42A25074UL))) +#define bM4_INTC_VSSEL137_VSEL30 (*((volatile unsigned int*)(0x42A25078UL))) +#define bM4_INTC_VSSEL137_VSEL31 (*((volatile unsigned int*)(0x42A2507CUL))) +#define bM4_INTC_VSSEL138_VSEL0 (*((volatile unsigned int*)(0x42A25080UL))) +#define bM4_INTC_VSSEL138_VSEL1 (*((volatile unsigned int*)(0x42A25084UL))) +#define bM4_INTC_VSSEL138_VSEL2 (*((volatile unsigned int*)(0x42A25088UL))) +#define bM4_INTC_VSSEL138_VSEL3 (*((volatile unsigned int*)(0x42A2508CUL))) +#define bM4_INTC_VSSEL138_VSEL4 (*((volatile unsigned int*)(0x42A25090UL))) +#define bM4_INTC_VSSEL138_VSEL5 (*((volatile unsigned int*)(0x42A25094UL))) +#define bM4_INTC_VSSEL138_VSEL6 (*((volatile unsigned int*)(0x42A25098UL))) +#define bM4_INTC_VSSEL138_VSEL7 (*((volatile unsigned int*)(0x42A2509CUL))) +#define bM4_INTC_VSSEL138_VSEL8 (*((volatile unsigned int*)(0x42A250A0UL))) +#define bM4_INTC_VSSEL138_VSEL9 (*((volatile unsigned int*)(0x42A250A4UL))) +#define bM4_INTC_VSSEL138_VSEL10 (*((volatile unsigned int*)(0x42A250A8UL))) +#define bM4_INTC_VSSEL138_VSEL11 (*((volatile unsigned int*)(0x42A250ACUL))) +#define bM4_INTC_VSSEL138_VSEL12 (*((volatile unsigned int*)(0x42A250B0UL))) +#define bM4_INTC_VSSEL138_VSEL13 (*((volatile unsigned int*)(0x42A250B4UL))) +#define bM4_INTC_VSSEL138_VSEL14 (*((volatile unsigned int*)(0x42A250B8UL))) +#define bM4_INTC_VSSEL138_VSEL15 (*((volatile unsigned int*)(0x42A250BCUL))) +#define bM4_INTC_VSSEL138_VSEL16 (*((volatile unsigned int*)(0x42A250C0UL))) +#define bM4_INTC_VSSEL138_VSEL17 (*((volatile unsigned int*)(0x42A250C4UL))) +#define bM4_INTC_VSSEL138_VSEL18 (*((volatile unsigned int*)(0x42A250C8UL))) +#define bM4_INTC_VSSEL138_VSEL19 (*((volatile unsigned int*)(0x42A250CCUL))) +#define bM4_INTC_VSSEL138_VSEL20 (*((volatile unsigned int*)(0x42A250D0UL))) +#define bM4_INTC_VSSEL138_VSEL21 (*((volatile unsigned int*)(0x42A250D4UL))) +#define bM4_INTC_VSSEL138_VSEL22 (*((volatile unsigned int*)(0x42A250D8UL))) +#define bM4_INTC_VSSEL138_VSEL23 (*((volatile unsigned int*)(0x42A250DCUL))) +#define bM4_INTC_VSSEL138_VSEL24 (*((volatile unsigned int*)(0x42A250E0UL))) +#define bM4_INTC_VSSEL138_VSEL25 (*((volatile unsigned int*)(0x42A250E4UL))) +#define bM4_INTC_VSSEL138_VSEL26 (*((volatile unsigned int*)(0x42A250E8UL))) +#define bM4_INTC_VSSEL138_VSEL27 (*((volatile unsigned int*)(0x42A250ECUL))) +#define bM4_INTC_VSSEL138_VSEL28 (*((volatile unsigned int*)(0x42A250F0UL))) +#define bM4_INTC_VSSEL138_VSEL29 (*((volatile unsigned int*)(0x42A250F4UL))) +#define bM4_INTC_VSSEL138_VSEL30 (*((volatile unsigned int*)(0x42A250F8UL))) +#define bM4_INTC_VSSEL138_VSEL31 (*((volatile unsigned int*)(0x42A250FCUL))) +#define bM4_INTC_VSSEL139_VSEL0 (*((volatile unsigned int*)(0x42A25100UL))) +#define bM4_INTC_VSSEL139_VSEL1 (*((volatile unsigned int*)(0x42A25104UL))) +#define bM4_INTC_VSSEL139_VSEL2 (*((volatile unsigned int*)(0x42A25108UL))) +#define bM4_INTC_VSSEL139_VSEL3 (*((volatile unsigned int*)(0x42A2510CUL))) +#define bM4_INTC_VSSEL139_VSEL4 (*((volatile unsigned int*)(0x42A25110UL))) +#define bM4_INTC_VSSEL139_VSEL5 (*((volatile unsigned int*)(0x42A25114UL))) +#define bM4_INTC_VSSEL139_VSEL6 (*((volatile unsigned int*)(0x42A25118UL))) +#define bM4_INTC_VSSEL139_VSEL7 (*((volatile unsigned int*)(0x42A2511CUL))) +#define bM4_INTC_VSSEL139_VSEL8 (*((volatile unsigned int*)(0x42A25120UL))) +#define bM4_INTC_VSSEL139_VSEL9 (*((volatile unsigned int*)(0x42A25124UL))) +#define bM4_INTC_VSSEL139_VSEL10 (*((volatile unsigned int*)(0x42A25128UL))) +#define bM4_INTC_VSSEL139_VSEL11 (*((volatile unsigned int*)(0x42A2512CUL))) +#define bM4_INTC_VSSEL139_VSEL12 (*((volatile unsigned int*)(0x42A25130UL))) +#define bM4_INTC_VSSEL139_VSEL13 (*((volatile unsigned int*)(0x42A25134UL))) +#define bM4_INTC_VSSEL139_VSEL14 (*((volatile unsigned int*)(0x42A25138UL))) +#define bM4_INTC_VSSEL139_VSEL15 (*((volatile unsigned int*)(0x42A2513CUL))) +#define bM4_INTC_VSSEL139_VSEL16 (*((volatile unsigned int*)(0x42A25140UL))) +#define bM4_INTC_VSSEL139_VSEL17 (*((volatile unsigned int*)(0x42A25144UL))) +#define bM4_INTC_VSSEL139_VSEL18 (*((volatile unsigned int*)(0x42A25148UL))) +#define bM4_INTC_VSSEL139_VSEL19 (*((volatile unsigned int*)(0x42A2514CUL))) +#define bM4_INTC_VSSEL139_VSEL20 (*((volatile unsigned int*)(0x42A25150UL))) +#define bM4_INTC_VSSEL139_VSEL21 (*((volatile unsigned int*)(0x42A25154UL))) +#define bM4_INTC_VSSEL139_VSEL22 (*((volatile unsigned int*)(0x42A25158UL))) +#define bM4_INTC_VSSEL139_VSEL23 (*((volatile unsigned int*)(0x42A2515CUL))) +#define bM4_INTC_VSSEL139_VSEL24 (*((volatile unsigned int*)(0x42A25160UL))) +#define bM4_INTC_VSSEL139_VSEL25 (*((volatile unsigned int*)(0x42A25164UL))) +#define bM4_INTC_VSSEL139_VSEL26 (*((volatile unsigned int*)(0x42A25168UL))) +#define bM4_INTC_VSSEL139_VSEL27 (*((volatile unsigned int*)(0x42A2516CUL))) +#define bM4_INTC_VSSEL139_VSEL28 (*((volatile unsigned int*)(0x42A25170UL))) +#define bM4_INTC_VSSEL139_VSEL29 (*((volatile unsigned int*)(0x42A25174UL))) +#define bM4_INTC_VSSEL139_VSEL30 (*((volatile unsigned int*)(0x42A25178UL))) +#define bM4_INTC_VSSEL139_VSEL31 (*((volatile unsigned int*)(0x42A2517CUL))) +#define bM4_INTC_VSSEL140_VSEL0 (*((volatile unsigned int*)(0x42A25180UL))) +#define bM4_INTC_VSSEL140_VSEL1 (*((volatile unsigned int*)(0x42A25184UL))) +#define bM4_INTC_VSSEL140_VSEL2 (*((volatile unsigned int*)(0x42A25188UL))) +#define bM4_INTC_VSSEL140_VSEL3 (*((volatile unsigned int*)(0x42A2518CUL))) +#define bM4_INTC_VSSEL140_VSEL4 (*((volatile unsigned int*)(0x42A25190UL))) +#define bM4_INTC_VSSEL140_VSEL5 (*((volatile unsigned int*)(0x42A25194UL))) +#define bM4_INTC_VSSEL140_VSEL6 (*((volatile unsigned int*)(0x42A25198UL))) +#define bM4_INTC_VSSEL140_VSEL7 (*((volatile unsigned int*)(0x42A2519CUL))) +#define bM4_INTC_VSSEL140_VSEL8 (*((volatile unsigned int*)(0x42A251A0UL))) +#define bM4_INTC_VSSEL140_VSEL9 (*((volatile unsigned int*)(0x42A251A4UL))) +#define bM4_INTC_VSSEL140_VSEL10 (*((volatile unsigned int*)(0x42A251A8UL))) +#define bM4_INTC_VSSEL140_VSEL11 (*((volatile unsigned int*)(0x42A251ACUL))) +#define bM4_INTC_VSSEL140_VSEL12 (*((volatile unsigned int*)(0x42A251B0UL))) +#define bM4_INTC_VSSEL140_VSEL13 (*((volatile unsigned int*)(0x42A251B4UL))) +#define bM4_INTC_VSSEL140_VSEL14 (*((volatile unsigned int*)(0x42A251B8UL))) +#define bM4_INTC_VSSEL140_VSEL15 (*((volatile unsigned int*)(0x42A251BCUL))) +#define bM4_INTC_VSSEL140_VSEL16 (*((volatile unsigned int*)(0x42A251C0UL))) +#define bM4_INTC_VSSEL140_VSEL17 (*((volatile unsigned int*)(0x42A251C4UL))) +#define bM4_INTC_VSSEL140_VSEL18 (*((volatile unsigned int*)(0x42A251C8UL))) +#define bM4_INTC_VSSEL140_VSEL19 (*((volatile unsigned int*)(0x42A251CCUL))) +#define bM4_INTC_VSSEL140_VSEL20 (*((volatile unsigned int*)(0x42A251D0UL))) +#define bM4_INTC_VSSEL140_VSEL21 (*((volatile unsigned int*)(0x42A251D4UL))) +#define bM4_INTC_VSSEL140_VSEL22 (*((volatile unsigned int*)(0x42A251D8UL))) +#define bM4_INTC_VSSEL140_VSEL23 (*((volatile unsigned int*)(0x42A251DCUL))) +#define bM4_INTC_VSSEL140_VSEL24 (*((volatile unsigned int*)(0x42A251E0UL))) +#define bM4_INTC_VSSEL140_VSEL25 (*((volatile unsigned int*)(0x42A251E4UL))) +#define bM4_INTC_VSSEL140_VSEL26 (*((volatile unsigned int*)(0x42A251E8UL))) +#define bM4_INTC_VSSEL140_VSEL27 (*((volatile unsigned int*)(0x42A251ECUL))) +#define bM4_INTC_VSSEL140_VSEL28 (*((volatile unsigned int*)(0x42A251F0UL))) +#define bM4_INTC_VSSEL140_VSEL29 (*((volatile unsigned int*)(0x42A251F4UL))) +#define bM4_INTC_VSSEL140_VSEL30 (*((volatile unsigned int*)(0x42A251F8UL))) +#define bM4_INTC_VSSEL140_VSEL31 (*((volatile unsigned int*)(0x42A251FCUL))) +#define bM4_INTC_VSSEL141_VSEL0 (*((volatile unsigned int*)(0x42A25200UL))) +#define bM4_INTC_VSSEL141_VSEL1 (*((volatile unsigned int*)(0x42A25204UL))) +#define bM4_INTC_VSSEL141_VSEL2 (*((volatile unsigned int*)(0x42A25208UL))) +#define bM4_INTC_VSSEL141_VSEL3 (*((volatile unsigned int*)(0x42A2520CUL))) +#define bM4_INTC_VSSEL141_VSEL4 (*((volatile unsigned int*)(0x42A25210UL))) +#define bM4_INTC_VSSEL141_VSEL5 (*((volatile unsigned int*)(0x42A25214UL))) +#define bM4_INTC_VSSEL141_VSEL6 (*((volatile unsigned int*)(0x42A25218UL))) +#define bM4_INTC_VSSEL141_VSEL7 (*((volatile unsigned int*)(0x42A2521CUL))) +#define bM4_INTC_VSSEL141_VSEL8 (*((volatile unsigned int*)(0x42A25220UL))) +#define bM4_INTC_VSSEL141_VSEL9 (*((volatile unsigned int*)(0x42A25224UL))) +#define bM4_INTC_VSSEL141_VSEL10 (*((volatile unsigned int*)(0x42A25228UL))) +#define bM4_INTC_VSSEL141_VSEL11 (*((volatile unsigned int*)(0x42A2522CUL))) +#define bM4_INTC_VSSEL141_VSEL12 (*((volatile unsigned int*)(0x42A25230UL))) +#define bM4_INTC_VSSEL141_VSEL13 (*((volatile unsigned int*)(0x42A25234UL))) +#define bM4_INTC_VSSEL141_VSEL14 (*((volatile unsigned int*)(0x42A25238UL))) +#define bM4_INTC_VSSEL141_VSEL15 (*((volatile unsigned int*)(0x42A2523CUL))) +#define bM4_INTC_VSSEL141_VSEL16 (*((volatile unsigned int*)(0x42A25240UL))) +#define bM4_INTC_VSSEL141_VSEL17 (*((volatile unsigned int*)(0x42A25244UL))) +#define bM4_INTC_VSSEL141_VSEL18 (*((volatile unsigned int*)(0x42A25248UL))) +#define bM4_INTC_VSSEL141_VSEL19 (*((volatile unsigned int*)(0x42A2524CUL))) +#define bM4_INTC_VSSEL141_VSEL20 (*((volatile unsigned int*)(0x42A25250UL))) +#define bM4_INTC_VSSEL141_VSEL21 (*((volatile unsigned int*)(0x42A25254UL))) +#define bM4_INTC_VSSEL141_VSEL22 (*((volatile unsigned int*)(0x42A25258UL))) +#define bM4_INTC_VSSEL141_VSEL23 (*((volatile unsigned int*)(0x42A2525CUL))) +#define bM4_INTC_VSSEL141_VSEL24 (*((volatile unsigned int*)(0x42A25260UL))) +#define bM4_INTC_VSSEL141_VSEL25 (*((volatile unsigned int*)(0x42A25264UL))) +#define bM4_INTC_VSSEL141_VSEL26 (*((volatile unsigned int*)(0x42A25268UL))) +#define bM4_INTC_VSSEL141_VSEL27 (*((volatile unsigned int*)(0x42A2526CUL))) +#define bM4_INTC_VSSEL141_VSEL28 (*((volatile unsigned int*)(0x42A25270UL))) +#define bM4_INTC_VSSEL141_VSEL29 (*((volatile unsigned int*)(0x42A25274UL))) +#define bM4_INTC_VSSEL141_VSEL30 (*((volatile unsigned int*)(0x42A25278UL))) +#define bM4_INTC_VSSEL141_VSEL31 (*((volatile unsigned int*)(0x42A2527CUL))) +#define bM4_INTC_VSSEL142_VSEL0 (*((volatile unsigned int*)(0x42A25280UL))) +#define bM4_INTC_VSSEL142_VSEL1 (*((volatile unsigned int*)(0x42A25284UL))) +#define bM4_INTC_VSSEL142_VSEL2 (*((volatile unsigned int*)(0x42A25288UL))) +#define bM4_INTC_VSSEL142_VSEL3 (*((volatile unsigned int*)(0x42A2528CUL))) +#define bM4_INTC_VSSEL142_VSEL4 (*((volatile unsigned int*)(0x42A25290UL))) +#define bM4_INTC_VSSEL142_VSEL5 (*((volatile unsigned int*)(0x42A25294UL))) +#define bM4_INTC_VSSEL142_VSEL6 (*((volatile unsigned int*)(0x42A25298UL))) +#define bM4_INTC_VSSEL142_VSEL7 (*((volatile unsigned int*)(0x42A2529CUL))) +#define bM4_INTC_VSSEL142_VSEL8 (*((volatile unsigned int*)(0x42A252A0UL))) +#define bM4_INTC_VSSEL142_VSEL9 (*((volatile unsigned int*)(0x42A252A4UL))) +#define bM4_INTC_VSSEL142_VSEL10 (*((volatile unsigned int*)(0x42A252A8UL))) +#define bM4_INTC_VSSEL142_VSEL11 (*((volatile unsigned int*)(0x42A252ACUL))) +#define bM4_INTC_VSSEL142_VSEL12 (*((volatile unsigned int*)(0x42A252B0UL))) +#define bM4_INTC_VSSEL142_VSEL13 (*((volatile unsigned int*)(0x42A252B4UL))) +#define bM4_INTC_VSSEL142_VSEL14 (*((volatile unsigned int*)(0x42A252B8UL))) +#define bM4_INTC_VSSEL142_VSEL15 (*((volatile unsigned int*)(0x42A252BCUL))) +#define bM4_INTC_VSSEL142_VSEL16 (*((volatile unsigned int*)(0x42A252C0UL))) +#define bM4_INTC_VSSEL142_VSEL17 (*((volatile unsigned int*)(0x42A252C4UL))) +#define bM4_INTC_VSSEL142_VSEL18 (*((volatile unsigned int*)(0x42A252C8UL))) +#define bM4_INTC_VSSEL142_VSEL19 (*((volatile unsigned int*)(0x42A252CCUL))) +#define bM4_INTC_VSSEL142_VSEL20 (*((volatile unsigned int*)(0x42A252D0UL))) +#define bM4_INTC_VSSEL142_VSEL21 (*((volatile unsigned int*)(0x42A252D4UL))) +#define bM4_INTC_VSSEL142_VSEL22 (*((volatile unsigned int*)(0x42A252D8UL))) +#define bM4_INTC_VSSEL142_VSEL23 (*((volatile unsigned int*)(0x42A252DCUL))) +#define bM4_INTC_VSSEL142_VSEL24 (*((volatile unsigned int*)(0x42A252E0UL))) +#define bM4_INTC_VSSEL142_VSEL25 (*((volatile unsigned int*)(0x42A252E4UL))) +#define bM4_INTC_VSSEL142_VSEL26 (*((volatile unsigned int*)(0x42A252E8UL))) +#define bM4_INTC_VSSEL142_VSEL27 (*((volatile unsigned int*)(0x42A252ECUL))) +#define bM4_INTC_VSSEL142_VSEL28 (*((volatile unsigned int*)(0x42A252F0UL))) +#define bM4_INTC_VSSEL142_VSEL29 (*((volatile unsigned int*)(0x42A252F4UL))) +#define bM4_INTC_VSSEL142_VSEL30 (*((volatile unsigned int*)(0x42A252F8UL))) +#define bM4_INTC_VSSEL142_VSEL31 (*((volatile unsigned int*)(0x42A252FCUL))) +#define bM4_INTC_VSSEL143_VSEL0 (*((volatile unsigned int*)(0x42A25300UL))) +#define bM4_INTC_VSSEL143_VSEL1 (*((volatile unsigned int*)(0x42A25304UL))) +#define bM4_INTC_VSSEL143_VSEL2 (*((volatile unsigned int*)(0x42A25308UL))) +#define bM4_INTC_VSSEL143_VSEL3 (*((volatile unsigned int*)(0x42A2530CUL))) +#define bM4_INTC_VSSEL143_VSEL4 (*((volatile unsigned int*)(0x42A25310UL))) +#define bM4_INTC_VSSEL143_VSEL5 (*((volatile unsigned int*)(0x42A25314UL))) +#define bM4_INTC_VSSEL143_VSEL6 (*((volatile unsigned int*)(0x42A25318UL))) +#define bM4_INTC_VSSEL143_VSEL7 (*((volatile unsigned int*)(0x42A2531CUL))) +#define bM4_INTC_VSSEL143_VSEL8 (*((volatile unsigned int*)(0x42A25320UL))) +#define bM4_INTC_VSSEL143_VSEL9 (*((volatile unsigned int*)(0x42A25324UL))) +#define bM4_INTC_VSSEL143_VSEL10 (*((volatile unsigned int*)(0x42A25328UL))) +#define bM4_INTC_VSSEL143_VSEL11 (*((volatile unsigned int*)(0x42A2532CUL))) +#define bM4_INTC_VSSEL143_VSEL12 (*((volatile unsigned int*)(0x42A25330UL))) +#define bM4_INTC_VSSEL143_VSEL13 (*((volatile unsigned int*)(0x42A25334UL))) +#define bM4_INTC_VSSEL143_VSEL14 (*((volatile unsigned int*)(0x42A25338UL))) +#define bM4_INTC_VSSEL143_VSEL15 (*((volatile unsigned int*)(0x42A2533CUL))) +#define bM4_INTC_VSSEL143_VSEL16 (*((volatile unsigned int*)(0x42A25340UL))) +#define bM4_INTC_VSSEL143_VSEL17 (*((volatile unsigned int*)(0x42A25344UL))) +#define bM4_INTC_VSSEL143_VSEL18 (*((volatile unsigned int*)(0x42A25348UL))) +#define bM4_INTC_VSSEL143_VSEL19 (*((volatile unsigned int*)(0x42A2534CUL))) +#define bM4_INTC_VSSEL143_VSEL20 (*((volatile unsigned int*)(0x42A25350UL))) +#define bM4_INTC_VSSEL143_VSEL21 (*((volatile unsigned int*)(0x42A25354UL))) +#define bM4_INTC_VSSEL143_VSEL22 (*((volatile unsigned int*)(0x42A25358UL))) +#define bM4_INTC_VSSEL143_VSEL23 (*((volatile unsigned int*)(0x42A2535CUL))) +#define bM4_INTC_VSSEL143_VSEL24 (*((volatile unsigned int*)(0x42A25360UL))) +#define bM4_INTC_VSSEL143_VSEL25 (*((volatile unsigned int*)(0x42A25364UL))) +#define bM4_INTC_VSSEL143_VSEL26 (*((volatile unsigned int*)(0x42A25368UL))) +#define bM4_INTC_VSSEL143_VSEL27 (*((volatile unsigned int*)(0x42A2536CUL))) +#define bM4_INTC_VSSEL143_VSEL28 (*((volatile unsigned int*)(0x42A25370UL))) +#define bM4_INTC_VSSEL143_VSEL29 (*((volatile unsigned int*)(0x42A25374UL))) +#define bM4_INTC_VSSEL143_VSEL30 (*((volatile unsigned int*)(0x42A25378UL))) +#define bM4_INTC_VSSEL143_VSEL31 (*((volatile unsigned int*)(0x42A2537CUL))) +#define bM4_INTC_SWIER_SWIE0 (*((volatile unsigned int*)(0x42A25380UL))) +#define bM4_INTC_SWIER_SWIE1 (*((volatile unsigned int*)(0x42A25384UL))) +#define bM4_INTC_SWIER_SWIE2 (*((volatile unsigned int*)(0x42A25388UL))) +#define bM4_INTC_SWIER_SWIE3 (*((volatile unsigned int*)(0x42A2538CUL))) +#define bM4_INTC_SWIER_SWIE4 (*((volatile unsigned int*)(0x42A25390UL))) +#define bM4_INTC_SWIER_SWIE5 (*((volatile unsigned int*)(0x42A25394UL))) +#define bM4_INTC_SWIER_SWIE6 (*((volatile unsigned int*)(0x42A25398UL))) +#define bM4_INTC_SWIER_SWIE7 (*((volatile unsigned int*)(0x42A2539CUL))) +#define bM4_INTC_SWIER_SWIE8 (*((volatile unsigned int*)(0x42A253A0UL))) +#define bM4_INTC_SWIER_SWIE9 (*((volatile unsigned int*)(0x42A253A4UL))) +#define bM4_INTC_SWIER_SWIE10 (*((volatile unsigned int*)(0x42A253A8UL))) +#define bM4_INTC_SWIER_SWIE11 (*((volatile unsigned int*)(0x42A253ACUL))) +#define bM4_INTC_SWIER_SWIE12 (*((volatile unsigned int*)(0x42A253B0UL))) +#define bM4_INTC_SWIER_SWIE13 (*((volatile unsigned int*)(0x42A253B4UL))) +#define bM4_INTC_SWIER_SWIE14 (*((volatile unsigned int*)(0x42A253B8UL))) +#define bM4_INTC_SWIER_SWIE15 (*((volatile unsigned int*)(0x42A253BCUL))) +#define bM4_INTC_SWIER_SWIE16 (*((volatile unsigned int*)(0x42A253C0UL))) +#define bM4_INTC_SWIER_SWIE17 (*((volatile unsigned int*)(0x42A253C4UL))) +#define bM4_INTC_SWIER_SWIE18 (*((volatile unsigned int*)(0x42A253C8UL))) +#define bM4_INTC_SWIER_SWIE19 (*((volatile unsigned int*)(0x42A253CCUL))) +#define bM4_INTC_SWIER_SWIE20 (*((volatile unsigned int*)(0x42A253D0UL))) +#define bM4_INTC_SWIER_SWIE21 (*((volatile unsigned int*)(0x42A253D4UL))) +#define bM4_INTC_SWIER_SWIE22 (*((volatile unsigned int*)(0x42A253D8UL))) +#define bM4_INTC_SWIER_SWIE23 (*((volatile unsigned int*)(0x42A253DCUL))) +#define bM4_INTC_SWIER_SWIE24 (*((volatile unsigned int*)(0x42A253E0UL))) +#define bM4_INTC_SWIER_SWIE25 (*((volatile unsigned int*)(0x42A253E4UL))) +#define bM4_INTC_SWIER_SWIE26 (*((volatile unsigned int*)(0x42A253E8UL))) +#define bM4_INTC_SWIER_SWIE27 (*((volatile unsigned int*)(0x42A253ECUL))) +#define bM4_INTC_SWIER_SWIE28 (*((volatile unsigned int*)(0x42A253F0UL))) +#define bM4_INTC_SWIER_SWIE29 (*((volatile unsigned int*)(0x42A253F4UL))) +#define bM4_INTC_SWIER_SWIE30 (*((volatile unsigned int*)(0x42A253F8UL))) +#define bM4_INTC_SWIER_SWIE31 (*((volatile unsigned int*)(0x42A253FCUL))) +#define bM4_INTC_EVTER_EVTE0 (*((volatile unsigned int*)(0x42A25400UL))) +#define bM4_INTC_EVTER_EVTE1 (*((volatile unsigned int*)(0x42A25404UL))) +#define bM4_INTC_EVTER_EVTE2 (*((volatile unsigned int*)(0x42A25408UL))) +#define bM4_INTC_EVTER_EVTE3 (*((volatile unsigned int*)(0x42A2540CUL))) +#define bM4_INTC_EVTER_EVTE4 (*((volatile unsigned int*)(0x42A25410UL))) +#define bM4_INTC_EVTER_EVTE5 (*((volatile unsigned int*)(0x42A25414UL))) +#define bM4_INTC_EVTER_EVTE6 (*((volatile unsigned int*)(0x42A25418UL))) +#define bM4_INTC_EVTER_EVTE7 (*((volatile unsigned int*)(0x42A2541CUL))) +#define bM4_INTC_EVTER_EVTE8 (*((volatile unsigned int*)(0x42A25420UL))) +#define bM4_INTC_EVTER_EVTE9 (*((volatile unsigned int*)(0x42A25424UL))) +#define bM4_INTC_EVTER_EVTE10 (*((volatile unsigned int*)(0x42A25428UL))) +#define bM4_INTC_EVTER_EVTE11 (*((volatile unsigned int*)(0x42A2542CUL))) +#define bM4_INTC_EVTER_EVTE12 (*((volatile unsigned int*)(0x42A25430UL))) +#define bM4_INTC_EVTER_EVTE13 (*((volatile unsigned int*)(0x42A25434UL))) +#define bM4_INTC_EVTER_EVTE14 (*((volatile unsigned int*)(0x42A25438UL))) +#define bM4_INTC_EVTER_EVTE15 (*((volatile unsigned int*)(0x42A2543CUL))) +#define bM4_INTC_EVTER_EVTE16 (*((volatile unsigned int*)(0x42A25440UL))) +#define bM4_INTC_EVTER_EVTE17 (*((volatile unsigned int*)(0x42A25444UL))) +#define bM4_INTC_EVTER_EVTE18 (*((volatile unsigned int*)(0x42A25448UL))) +#define bM4_INTC_EVTER_EVTE19 (*((volatile unsigned int*)(0x42A2544CUL))) +#define bM4_INTC_EVTER_EVTE20 (*((volatile unsigned int*)(0x42A25450UL))) +#define bM4_INTC_EVTER_EVTE21 (*((volatile unsigned int*)(0x42A25454UL))) +#define bM4_INTC_EVTER_EVTE22 (*((volatile unsigned int*)(0x42A25458UL))) +#define bM4_INTC_EVTER_EVTE23 (*((volatile unsigned int*)(0x42A2545CUL))) +#define bM4_INTC_EVTER_EVTE24 (*((volatile unsigned int*)(0x42A25460UL))) +#define bM4_INTC_EVTER_EVTE25 (*((volatile unsigned int*)(0x42A25464UL))) +#define bM4_INTC_EVTER_EVTE26 (*((volatile unsigned int*)(0x42A25468UL))) +#define bM4_INTC_EVTER_EVTE27 (*((volatile unsigned int*)(0x42A2546CUL))) +#define bM4_INTC_EVTER_EVTE28 (*((volatile unsigned int*)(0x42A25470UL))) +#define bM4_INTC_EVTER_EVTE29 (*((volatile unsigned int*)(0x42A25474UL))) +#define bM4_INTC_EVTER_EVTE30 (*((volatile unsigned int*)(0x42A25478UL))) +#define bM4_INTC_EVTER_EVTE31 (*((volatile unsigned int*)(0x42A2547CUL))) +#define bM4_INTC_IER_IER0 (*((volatile unsigned int*)(0x42A25480UL))) +#define bM4_INTC_IER_IER1 (*((volatile unsigned int*)(0x42A25484UL))) +#define bM4_INTC_IER_IER2 (*((volatile unsigned int*)(0x42A25488UL))) +#define bM4_INTC_IER_IER3 (*((volatile unsigned int*)(0x42A2548CUL))) +#define bM4_INTC_IER_IER4 (*((volatile unsigned int*)(0x42A25490UL))) +#define bM4_INTC_IER_IER5 (*((volatile unsigned int*)(0x42A25494UL))) +#define bM4_INTC_IER_IER6 (*((volatile unsigned int*)(0x42A25498UL))) +#define bM4_INTC_IER_IER7 (*((volatile unsigned int*)(0x42A2549CUL))) +#define bM4_INTC_IER_IER8 (*((volatile unsigned int*)(0x42A254A0UL))) +#define bM4_INTC_IER_IER9 (*((volatile unsigned int*)(0x42A254A4UL))) +#define bM4_INTC_IER_IER10 (*((volatile unsigned int*)(0x42A254A8UL))) +#define bM4_INTC_IER_IER11 (*((volatile unsigned int*)(0x42A254ACUL))) +#define bM4_INTC_IER_IER12 (*((volatile unsigned int*)(0x42A254B0UL))) +#define bM4_INTC_IER_IER13 (*((volatile unsigned int*)(0x42A254B4UL))) +#define bM4_INTC_IER_IER14 (*((volatile unsigned int*)(0x42A254B8UL))) +#define bM4_INTC_IER_IER15 (*((volatile unsigned int*)(0x42A254BCUL))) +#define bM4_INTC_IER_IER16 (*((volatile unsigned int*)(0x42A254C0UL))) +#define bM4_INTC_IER_IER17 (*((volatile unsigned int*)(0x42A254C4UL))) +#define bM4_INTC_IER_IER18 (*((volatile unsigned int*)(0x42A254C8UL))) +#define bM4_INTC_IER_IER19 (*((volatile unsigned int*)(0x42A254CCUL))) +#define bM4_INTC_IER_IER20 (*((volatile unsigned int*)(0x42A254D0UL))) +#define bM4_INTC_IER_IER21 (*((volatile unsigned int*)(0x42A254D4UL))) +#define bM4_INTC_IER_IER22 (*((volatile unsigned int*)(0x42A254D8UL))) +#define bM4_INTC_IER_IER23 (*((volatile unsigned int*)(0x42A254DCUL))) +#define bM4_INTC_IER_IER24 (*((volatile unsigned int*)(0x42A254E0UL))) +#define bM4_INTC_IER_IER25 (*((volatile unsigned int*)(0x42A254E4UL))) +#define bM4_INTC_IER_IER26 (*((volatile unsigned int*)(0x42A254E8UL))) +#define bM4_INTC_IER_IER27 (*((volatile unsigned int*)(0x42A254ECUL))) +#define bM4_INTC_IER_IER28 (*((volatile unsigned int*)(0x42A254F0UL))) +#define bM4_INTC_IER_IER29 (*((volatile unsigned int*)(0x42A254F4UL))) +#define bM4_INTC_IER_IER30 (*((volatile unsigned int*)(0x42A254F8UL))) +#define bM4_INTC_IER_IER31 (*((volatile unsigned int*)(0x42A254FCUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL0 (*((volatile unsigned int*)(0x42A18000UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL1 (*((volatile unsigned int*)(0x42A18004UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL2 (*((volatile unsigned int*)(0x42A18008UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL3 (*((volatile unsigned int*)(0x42A1800CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL4 (*((volatile unsigned int*)(0x42A18010UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL5 (*((volatile unsigned int*)(0x42A18014UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL6 (*((volatile unsigned int*)(0x42A18018UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL7 (*((volatile unsigned int*)(0x42A1801CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL8 (*((volatile unsigned int*)(0x42A18020UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL9 (*((volatile unsigned int*)(0x42A18024UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL10 (*((volatile unsigned int*)(0x42A18028UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL11 (*((volatile unsigned int*)(0x42A1802CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL12 (*((volatile unsigned int*)(0x42A18030UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL13 (*((volatile unsigned int*)(0x42A18034UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL14 (*((volatile unsigned int*)(0x42A18038UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL15 (*((volatile unsigned int*)(0x42A1803CUL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL0 (*((volatile unsigned int*)(0x42A18040UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL1 (*((volatile unsigned int*)(0x42A18044UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL2 (*((volatile unsigned int*)(0x42A18048UL))) +#define bM4_KEYSCAN_SCR_CKSEL0 (*((volatile unsigned int*)(0x42A18050UL))) +#define bM4_KEYSCAN_SCR_CKSEL1 (*((volatile unsigned int*)(0x42A18054UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL0 (*((volatile unsigned int*)(0x42A18060UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL1 (*((volatile unsigned int*)(0x42A18064UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL2 (*((volatile unsigned int*)(0x42A18068UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL3 (*((volatile unsigned int*)(0x42A1806CUL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL4 (*((volatile unsigned int*)(0x42A18070UL))) +#define bM4_KEYSCAN_SCR_T_HIZ0 (*((volatile unsigned int*)(0x42A18074UL))) +#define bM4_KEYSCAN_SCR_T_HIZ1 (*((volatile unsigned int*)(0x42A18078UL))) +#define bM4_KEYSCAN_SCR_T_HIZ2 (*((volatile unsigned int*)(0x42A1807CUL))) +#define bM4_KEYSCAN_SER_SEN (*((volatile unsigned int*)(0x42A18080UL))) +#define bM4_KEYSCAN_SSR_INDEX0 (*((volatile unsigned int*)(0x42A18100UL))) +#define bM4_KEYSCAN_SSR_INDEX1 (*((volatile unsigned int*)(0x42A18104UL))) +#define bM4_KEYSCAN_SSR_INDEX2 (*((volatile unsigned int*)(0x42A18108UL))) +#define bM4_MPU_RGD0_MPURG0SIZE0 (*((volatile unsigned int*)(0x42A00000UL))) +#define bM4_MPU_RGD0_MPURG0SIZE1 (*((volatile unsigned int*)(0x42A00004UL))) +#define bM4_MPU_RGD0_MPURG0SIZE2 (*((volatile unsigned int*)(0x42A00008UL))) +#define bM4_MPU_RGD0_MPURG0SIZE3 (*((volatile unsigned int*)(0x42A0000CUL))) +#define bM4_MPU_RGD0_MPURG0SIZE4 (*((volatile unsigned int*)(0x42A00010UL))) +#define bM4_MPU_RGD0_MPURG0ADDR0 (*((volatile unsigned int*)(0x42A00014UL))) +#define bM4_MPU_RGD0_MPURG0ADDR1 (*((volatile unsigned int*)(0x42A00018UL))) +#define bM4_MPU_RGD0_MPURG0ADDR2 (*((volatile unsigned int*)(0x42A0001CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR3 (*((volatile unsigned int*)(0x42A00020UL))) +#define bM4_MPU_RGD0_MPURG0ADDR4 (*((volatile unsigned int*)(0x42A00024UL))) +#define bM4_MPU_RGD0_MPURG0ADDR5 (*((volatile unsigned int*)(0x42A00028UL))) +#define bM4_MPU_RGD0_MPURG0ADDR6 (*((volatile unsigned int*)(0x42A0002CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR7 (*((volatile unsigned int*)(0x42A00030UL))) +#define bM4_MPU_RGD0_MPURG0ADDR8 (*((volatile unsigned int*)(0x42A00034UL))) +#define bM4_MPU_RGD0_MPURG0ADDR9 (*((volatile unsigned int*)(0x42A00038UL))) +#define bM4_MPU_RGD0_MPURG0ADDR10 (*((volatile unsigned int*)(0x42A0003CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR11 (*((volatile unsigned int*)(0x42A00040UL))) +#define bM4_MPU_RGD0_MPURG0ADDR12 (*((volatile unsigned int*)(0x42A00044UL))) +#define bM4_MPU_RGD0_MPURG0ADDR13 (*((volatile unsigned int*)(0x42A00048UL))) +#define bM4_MPU_RGD0_MPURG0ADDR14 (*((volatile unsigned int*)(0x42A0004CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR15 (*((volatile unsigned int*)(0x42A00050UL))) +#define bM4_MPU_RGD0_MPURG0ADDR16 (*((volatile unsigned int*)(0x42A00054UL))) +#define bM4_MPU_RGD0_MPURG0ADDR17 (*((volatile unsigned int*)(0x42A00058UL))) +#define bM4_MPU_RGD0_MPURG0ADDR18 (*((volatile unsigned int*)(0x42A0005CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR19 (*((volatile unsigned int*)(0x42A00060UL))) +#define bM4_MPU_RGD0_MPURG0ADDR20 (*((volatile unsigned int*)(0x42A00064UL))) +#define bM4_MPU_RGD0_MPURG0ADDR21 (*((volatile unsigned int*)(0x42A00068UL))) +#define bM4_MPU_RGD0_MPURG0ADDR22 (*((volatile unsigned int*)(0x42A0006CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR23 (*((volatile unsigned int*)(0x42A00070UL))) +#define bM4_MPU_RGD0_MPURG0ADDR24 (*((volatile unsigned int*)(0x42A00074UL))) +#define bM4_MPU_RGD0_MPURG0ADDR25 (*((volatile unsigned int*)(0x42A00078UL))) +#define bM4_MPU_RGD0_MPURG0ADDR26 (*((volatile unsigned int*)(0x42A0007CUL))) +#define bM4_MPU_RGD1_MPURG1SIZE0 (*((volatile unsigned int*)(0x42A00080UL))) +#define bM4_MPU_RGD1_MPURG1SIZE1 (*((volatile unsigned int*)(0x42A00084UL))) +#define bM4_MPU_RGD1_MPURG1SIZE2 (*((volatile unsigned int*)(0x42A00088UL))) +#define bM4_MPU_RGD1_MPURG1SIZE3 (*((volatile unsigned int*)(0x42A0008CUL))) +#define bM4_MPU_RGD1_MPURG1SIZE4 (*((volatile unsigned int*)(0x42A00090UL))) +#define bM4_MPU_RGD1_MPURG1ADDR0 (*((volatile unsigned int*)(0x42A00094UL))) +#define bM4_MPU_RGD1_MPURG1ADDR1 (*((volatile unsigned int*)(0x42A00098UL))) +#define bM4_MPU_RGD1_MPURG1ADDR2 (*((volatile unsigned int*)(0x42A0009CUL))) +#define bM4_MPU_RGD1_MPURG1ADDR3 (*((volatile unsigned int*)(0x42A000A0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR4 (*((volatile unsigned int*)(0x42A000A4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR5 (*((volatile unsigned int*)(0x42A000A8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR6 (*((volatile unsigned int*)(0x42A000ACUL))) +#define bM4_MPU_RGD1_MPURG1ADDR7 (*((volatile unsigned int*)(0x42A000B0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR8 (*((volatile unsigned int*)(0x42A000B4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR9 (*((volatile unsigned int*)(0x42A000B8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR10 (*((volatile unsigned int*)(0x42A000BCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR11 (*((volatile unsigned int*)(0x42A000C0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR12 (*((volatile unsigned int*)(0x42A000C4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR13 (*((volatile unsigned int*)(0x42A000C8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR14 (*((volatile unsigned int*)(0x42A000CCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR15 (*((volatile unsigned int*)(0x42A000D0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR16 (*((volatile unsigned int*)(0x42A000D4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR17 (*((volatile unsigned int*)(0x42A000D8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR18 (*((volatile unsigned int*)(0x42A000DCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR19 (*((volatile unsigned int*)(0x42A000E0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR20 (*((volatile unsigned int*)(0x42A000E4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR21 (*((volatile unsigned int*)(0x42A000E8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR22 (*((volatile unsigned int*)(0x42A000ECUL))) +#define bM4_MPU_RGD1_MPURG1ADDR23 (*((volatile unsigned int*)(0x42A000F0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR24 (*((volatile unsigned int*)(0x42A000F4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR25 (*((volatile unsigned int*)(0x42A000F8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR26 (*((volatile unsigned int*)(0x42A000FCUL))) +#define bM4_MPU_RGD2_MPURG2SIZE0 (*((volatile unsigned int*)(0x42A00100UL))) +#define bM4_MPU_RGD2_MPURG2SIZE1 (*((volatile unsigned int*)(0x42A00104UL))) +#define bM4_MPU_RGD2_MPURG2SIZE2 (*((volatile unsigned int*)(0x42A00108UL))) +#define bM4_MPU_RGD2_MPURG2SIZE3 (*((volatile unsigned int*)(0x42A0010CUL))) +#define bM4_MPU_RGD2_MPURG2SIZE4 (*((volatile unsigned int*)(0x42A00110UL))) +#define bM4_MPU_RGD2_MPURG2ADDR0 (*((volatile unsigned int*)(0x42A00114UL))) +#define bM4_MPU_RGD2_MPURG2ADDR1 (*((volatile unsigned int*)(0x42A00118UL))) +#define bM4_MPU_RGD2_MPURG2ADDR2 (*((volatile unsigned int*)(0x42A0011CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR3 (*((volatile unsigned int*)(0x42A00120UL))) +#define bM4_MPU_RGD2_MPURG2ADDR4 (*((volatile unsigned int*)(0x42A00124UL))) +#define bM4_MPU_RGD2_MPURG2ADDR5 (*((volatile unsigned int*)(0x42A00128UL))) +#define bM4_MPU_RGD2_MPURG2ADDR6 (*((volatile unsigned int*)(0x42A0012CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR7 (*((volatile unsigned int*)(0x42A00130UL))) +#define bM4_MPU_RGD2_MPURG2ADDR8 (*((volatile unsigned int*)(0x42A00134UL))) +#define bM4_MPU_RGD2_MPURG2ADDR9 (*((volatile unsigned int*)(0x42A00138UL))) +#define bM4_MPU_RGD2_MPURG2ADDR10 (*((volatile unsigned int*)(0x42A0013CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR11 (*((volatile unsigned int*)(0x42A00140UL))) +#define bM4_MPU_RGD2_MPURG2ADDR12 (*((volatile unsigned int*)(0x42A00144UL))) +#define bM4_MPU_RGD2_MPURG2ADDR13 (*((volatile unsigned int*)(0x42A00148UL))) +#define bM4_MPU_RGD2_MPURG2ADDR14 (*((volatile unsigned int*)(0x42A0014CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR15 (*((volatile unsigned int*)(0x42A00150UL))) +#define bM4_MPU_RGD2_MPURG2ADDR16 (*((volatile unsigned int*)(0x42A00154UL))) +#define bM4_MPU_RGD2_MPURG2ADDR17 (*((volatile unsigned int*)(0x42A00158UL))) +#define bM4_MPU_RGD2_MPURG2ADDR18 (*((volatile unsigned int*)(0x42A0015CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR19 (*((volatile unsigned int*)(0x42A00160UL))) +#define bM4_MPU_RGD2_MPURG2ADDR20 (*((volatile unsigned int*)(0x42A00164UL))) +#define bM4_MPU_RGD2_MPURG2ADDR21 (*((volatile unsigned int*)(0x42A00168UL))) +#define bM4_MPU_RGD2_MPURG2ADDR22 (*((volatile unsigned int*)(0x42A0016CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR23 (*((volatile unsigned int*)(0x42A00170UL))) +#define bM4_MPU_RGD2_MPURG2ADDR24 (*((volatile unsigned int*)(0x42A00174UL))) +#define bM4_MPU_RGD2_MPURG2ADDR25 (*((volatile unsigned int*)(0x42A00178UL))) +#define bM4_MPU_RGD2_MPURG2ADDR26 (*((volatile unsigned int*)(0x42A0017CUL))) +#define bM4_MPU_RGD3_MPURG3SIZE0 (*((volatile unsigned int*)(0x42A00180UL))) +#define bM4_MPU_RGD3_MPURG3SIZE1 (*((volatile unsigned int*)(0x42A00184UL))) +#define bM4_MPU_RGD3_MPURG3SIZE2 (*((volatile unsigned int*)(0x42A00188UL))) +#define bM4_MPU_RGD3_MPURG3SIZE3 (*((volatile unsigned int*)(0x42A0018CUL))) +#define bM4_MPU_RGD3_MPURG3SIZE4 (*((volatile unsigned int*)(0x42A00190UL))) +#define bM4_MPU_RGD3_MPURG3ADDR0 (*((volatile unsigned int*)(0x42A00194UL))) +#define bM4_MPU_RGD3_MPURG3ADDR1 (*((volatile unsigned int*)(0x42A00198UL))) +#define bM4_MPU_RGD3_MPURG3ADDR2 (*((volatile unsigned int*)(0x42A0019CUL))) +#define bM4_MPU_RGD3_MPURG3ADDR3 (*((volatile unsigned int*)(0x42A001A0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR4 (*((volatile unsigned int*)(0x42A001A4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR5 (*((volatile unsigned int*)(0x42A001A8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR6 (*((volatile unsigned int*)(0x42A001ACUL))) +#define bM4_MPU_RGD3_MPURG3ADDR7 (*((volatile unsigned int*)(0x42A001B0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR8 (*((volatile unsigned int*)(0x42A001B4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR9 (*((volatile unsigned int*)(0x42A001B8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR10 (*((volatile unsigned int*)(0x42A001BCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR11 (*((volatile unsigned int*)(0x42A001C0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR12 (*((volatile unsigned int*)(0x42A001C4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR13 (*((volatile unsigned int*)(0x42A001C8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR14 (*((volatile unsigned int*)(0x42A001CCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR15 (*((volatile unsigned int*)(0x42A001D0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR16 (*((volatile unsigned int*)(0x42A001D4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR17 (*((volatile unsigned int*)(0x42A001D8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR18 (*((volatile unsigned int*)(0x42A001DCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR19 (*((volatile unsigned int*)(0x42A001E0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR20 (*((volatile unsigned int*)(0x42A001E4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR21 (*((volatile unsigned int*)(0x42A001E8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR22 (*((volatile unsigned int*)(0x42A001ECUL))) +#define bM4_MPU_RGD3_MPURG3ADDR23 (*((volatile unsigned int*)(0x42A001F0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR24 (*((volatile unsigned int*)(0x42A001F4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR25 (*((volatile unsigned int*)(0x42A001F8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR26 (*((volatile unsigned int*)(0x42A001FCUL))) +#define bM4_MPU_RGD4_MPURG4SIZE0 (*((volatile unsigned int*)(0x42A00200UL))) +#define bM4_MPU_RGD4_MPURG4SIZE1 (*((volatile unsigned int*)(0x42A00204UL))) +#define bM4_MPU_RGD4_MPURG4SIZE2 (*((volatile unsigned int*)(0x42A00208UL))) +#define bM4_MPU_RGD4_MPURG4SIZE3 (*((volatile unsigned int*)(0x42A0020CUL))) +#define bM4_MPU_RGD4_MPURG4SIZE4 (*((volatile unsigned int*)(0x42A00210UL))) +#define bM4_MPU_RGD4_MPURG4ADDR0 (*((volatile unsigned int*)(0x42A00214UL))) +#define bM4_MPU_RGD4_MPURG4ADDR1 (*((volatile unsigned int*)(0x42A00218UL))) +#define bM4_MPU_RGD4_MPURG4ADDR2 (*((volatile unsigned int*)(0x42A0021CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR3 (*((volatile unsigned int*)(0x42A00220UL))) +#define bM4_MPU_RGD4_MPURG4ADDR4 (*((volatile unsigned int*)(0x42A00224UL))) +#define bM4_MPU_RGD4_MPURG4ADDR5 (*((volatile unsigned int*)(0x42A00228UL))) +#define bM4_MPU_RGD4_MPURG4ADDR6 (*((volatile unsigned int*)(0x42A0022CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR7 (*((volatile unsigned int*)(0x42A00230UL))) +#define bM4_MPU_RGD4_MPURG4ADDR8 (*((volatile unsigned int*)(0x42A00234UL))) +#define bM4_MPU_RGD4_MPURG4ADDR9 (*((volatile unsigned int*)(0x42A00238UL))) +#define bM4_MPU_RGD4_MPURG4ADDR10 (*((volatile unsigned int*)(0x42A0023CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR11 (*((volatile unsigned int*)(0x42A00240UL))) +#define bM4_MPU_RGD4_MPURG4ADDR12 (*((volatile unsigned int*)(0x42A00244UL))) +#define bM4_MPU_RGD4_MPURG4ADDR13 (*((volatile unsigned int*)(0x42A00248UL))) +#define bM4_MPU_RGD4_MPURG4ADDR14 (*((volatile unsigned int*)(0x42A0024CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR15 (*((volatile unsigned int*)(0x42A00250UL))) +#define bM4_MPU_RGD4_MPURG4ADDR16 (*((volatile unsigned int*)(0x42A00254UL))) +#define bM4_MPU_RGD4_MPURG4ADDR17 (*((volatile unsigned int*)(0x42A00258UL))) +#define bM4_MPU_RGD4_MPURG4ADDR18 (*((volatile unsigned int*)(0x42A0025CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR19 (*((volatile unsigned int*)(0x42A00260UL))) +#define bM4_MPU_RGD4_MPURG4ADDR20 (*((volatile unsigned int*)(0x42A00264UL))) +#define bM4_MPU_RGD4_MPURG4ADDR21 (*((volatile unsigned int*)(0x42A00268UL))) +#define bM4_MPU_RGD4_MPURG4ADDR22 (*((volatile unsigned int*)(0x42A0026CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR23 (*((volatile unsigned int*)(0x42A00270UL))) +#define bM4_MPU_RGD4_MPURG4ADDR24 (*((volatile unsigned int*)(0x42A00274UL))) +#define bM4_MPU_RGD4_MPURG4ADDR25 (*((volatile unsigned int*)(0x42A00278UL))) +#define bM4_MPU_RGD4_MPURG4ADDR26 (*((volatile unsigned int*)(0x42A0027CUL))) +#define bM4_MPU_RGD5_MPURG5SIZE0 (*((volatile unsigned int*)(0x42A00280UL))) +#define bM4_MPU_RGD5_MPURG5SIZE1 (*((volatile unsigned int*)(0x42A00284UL))) +#define bM4_MPU_RGD5_MPURG5SIZE2 (*((volatile unsigned int*)(0x42A00288UL))) +#define bM4_MPU_RGD5_MPURG5SIZE3 (*((volatile unsigned int*)(0x42A0028CUL))) +#define bM4_MPU_RGD5_MPURG5SIZE4 (*((volatile unsigned int*)(0x42A00290UL))) +#define bM4_MPU_RGD5_MPURG5ADDR0 (*((volatile unsigned int*)(0x42A00294UL))) +#define bM4_MPU_RGD5_MPURG5ADDR1 (*((volatile unsigned int*)(0x42A00298UL))) +#define bM4_MPU_RGD5_MPURG5ADDR2 (*((volatile unsigned int*)(0x42A0029CUL))) +#define bM4_MPU_RGD5_MPURG5ADDR3 (*((volatile unsigned int*)(0x42A002A0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR4 (*((volatile unsigned int*)(0x42A002A4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR5 (*((volatile unsigned int*)(0x42A002A8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR6 (*((volatile unsigned int*)(0x42A002ACUL))) +#define bM4_MPU_RGD5_MPURG5ADDR7 (*((volatile unsigned int*)(0x42A002B0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR8 (*((volatile unsigned int*)(0x42A002B4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR9 (*((volatile unsigned int*)(0x42A002B8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR10 (*((volatile unsigned int*)(0x42A002BCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR11 (*((volatile unsigned int*)(0x42A002C0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR12 (*((volatile unsigned int*)(0x42A002C4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR13 (*((volatile unsigned int*)(0x42A002C8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR14 (*((volatile unsigned int*)(0x42A002CCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR15 (*((volatile unsigned int*)(0x42A002D0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR16 (*((volatile unsigned int*)(0x42A002D4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR17 (*((volatile unsigned int*)(0x42A002D8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR18 (*((volatile unsigned int*)(0x42A002DCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR19 (*((volatile unsigned int*)(0x42A002E0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR20 (*((volatile unsigned int*)(0x42A002E4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR21 (*((volatile unsigned int*)(0x42A002E8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR22 (*((volatile unsigned int*)(0x42A002ECUL))) +#define bM4_MPU_RGD5_MPURG5ADDR23 (*((volatile unsigned int*)(0x42A002F0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR24 (*((volatile unsigned int*)(0x42A002F4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR25 (*((volatile unsigned int*)(0x42A002F8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR26 (*((volatile unsigned int*)(0x42A002FCUL))) +#define bM4_MPU_RGD6_MPURG6SIZE0 (*((volatile unsigned int*)(0x42A00300UL))) +#define bM4_MPU_RGD6_MPURG6SIZE1 (*((volatile unsigned int*)(0x42A00304UL))) +#define bM4_MPU_RGD6_MPURG6SIZE2 (*((volatile unsigned int*)(0x42A00308UL))) +#define bM4_MPU_RGD6_MPURG6SIZE3 (*((volatile unsigned int*)(0x42A0030CUL))) +#define bM4_MPU_RGD6_MPURG6SIZE4 (*((volatile unsigned int*)(0x42A00310UL))) +#define bM4_MPU_RGD6_MPURG6ADDR0 (*((volatile unsigned int*)(0x42A00314UL))) +#define bM4_MPU_RGD6_MPURG6ADDR1 (*((volatile unsigned int*)(0x42A00318UL))) +#define bM4_MPU_RGD6_MPURG6ADDR2 (*((volatile unsigned int*)(0x42A0031CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR3 (*((volatile unsigned int*)(0x42A00320UL))) +#define bM4_MPU_RGD6_MPURG6ADDR4 (*((volatile unsigned int*)(0x42A00324UL))) +#define bM4_MPU_RGD6_MPURG6ADDR5 (*((volatile unsigned int*)(0x42A00328UL))) +#define bM4_MPU_RGD6_MPURG6ADDR6 (*((volatile unsigned int*)(0x42A0032CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR7 (*((volatile unsigned int*)(0x42A00330UL))) +#define bM4_MPU_RGD6_MPURG6ADDR8 (*((volatile unsigned int*)(0x42A00334UL))) +#define bM4_MPU_RGD6_MPURG6ADDR9 (*((volatile unsigned int*)(0x42A00338UL))) +#define bM4_MPU_RGD6_MPURG6ADDR10 (*((volatile unsigned int*)(0x42A0033CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR11 (*((volatile unsigned int*)(0x42A00340UL))) +#define bM4_MPU_RGD6_MPURG6ADDR12 (*((volatile unsigned int*)(0x42A00344UL))) +#define bM4_MPU_RGD6_MPURG6ADDR13 (*((volatile unsigned int*)(0x42A00348UL))) +#define bM4_MPU_RGD6_MPURG6ADDR14 (*((volatile unsigned int*)(0x42A0034CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR15 (*((volatile unsigned int*)(0x42A00350UL))) +#define bM4_MPU_RGD6_MPURG6ADDR16 (*((volatile unsigned int*)(0x42A00354UL))) +#define bM4_MPU_RGD6_MPURG6ADDR17 (*((volatile unsigned int*)(0x42A00358UL))) +#define bM4_MPU_RGD6_MPURG6ADDR18 (*((volatile unsigned int*)(0x42A0035CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR19 (*((volatile unsigned int*)(0x42A00360UL))) +#define bM4_MPU_RGD6_MPURG6ADDR20 (*((volatile unsigned int*)(0x42A00364UL))) +#define bM4_MPU_RGD6_MPURG6ADDR21 (*((volatile unsigned int*)(0x42A00368UL))) +#define bM4_MPU_RGD6_MPURG6ADDR22 (*((volatile unsigned int*)(0x42A0036CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR23 (*((volatile unsigned int*)(0x42A00370UL))) +#define bM4_MPU_RGD6_MPURG6ADDR24 (*((volatile unsigned int*)(0x42A00374UL))) +#define bM4_MPU_RGD6_MPURG6ADDR25 (*((volatile unsigned int*)(0x42A00378UL))) +#define bM4_MPU_RGD6_MPURG6ADDR26 (*((volatile unsigned int*)(0x42A0037CUL))) +#define bM4_MPU_RGD7_MPURG7SIZE0 (*((volatile unsigned int*)(0x42A00380UL))) +#define bM4_MPU_RGD7_MPURG7SIZE1 (*((volatile unsigned int*)(0x42A00384UL))) +#define bM4_MPU_RGD7_MPURG7SIZE2 (*((volatile unsigned int*)(0x42A00388UL))) +#define bM4_MPU_RGD7_MPURG7SIZE3 (*((volatile unsigned int*)(0x42A0038CUL))) +#define bM4_MPU_RGD7_MPURG7SIZE4 (*((volatile unsigned int*)(0x42A00390UL))) +#define bM4_MPU_RGD7_MPURG7ADDR0 (*((volatile unsigned int*)(0x42A00394UL))) +#define bM4_MPU_RGD7_MPURG7ADDR1 (*((volatile unsigned int*)(0x42A00398UL))) +#define bM4_MPU_RGD7_MPURG7ADDR2 (*((volatile unsigned int*)(0x42A0039CUL))) +#define bM4_MPU_RGD7_MPURG7ADDR3 (*((volatile unsigned int*)(0x42A003A0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR4 (*((volatile unsigned int*)(0x42A003A4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR5 (*((volatile unsigned int*)(0x42A003A8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR6 (*((volatile unsigned int*)(0x42A003ACUL))) +#define bM4_MPU_RGD7_MPURG7ADDR7 (*((volatile unsigned int*)(0x42A003B0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR8 (*((volatile unsigned int*)(0x42A003B4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR9 (*((volatile unsigned int*)(0x42A003B8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR10 (*((volatile unsigned int*)(0x42A003BCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR11 (*((volatile unsigned int*)(0x42A003C0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR12 (*((volatile unsigned int*)(0x42A003C4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR13 (*((volatile unsigned int*)(0x42A003C8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR14 (*((volatile unsigned int*)(0x42A003CCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR15 (*((volatile unsigned int*)(0x42A003D0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR16 (*((volatile unsigned int*)(0x42A003D4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR17 (*((volatile unsigned int*)(0x42A003D8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR18 (*((volatile unsigned int*)(0x42A003DCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR19 (*((volatile unsigned int*)(0x42A003E0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR20 (*((volatile unsigned int*)(0x42A003E4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR21 (*((volatile unsigned int*)(0x42A003E8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR22 (*((volatile unsigned int*)(0x42A003ECUL))) +#define bM4_MPU_RGD7_MPURG7ADDR23 (*((volatile unsigned int*)(0x42A003F0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR24 (*((volatile unsigned int*)(0x42A003F4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR25 (*((volatile unsigned int*)(0x42A003F8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR26 (*((volatile unsigned int*)(0x42A003FCUL))) +#define bM4_MPU_RGD8_MPURG8SIZE0 (*((volatile unsigned int*)(0x42A00400UL))) +#define bM4_MPU_RGD8_MPURG8SIZE1 (*((volatile unsigned int*)(0x42A00404UL))) +#define bM4_MPU_RGD8_MPURG8SIZE2 (*((volatile unsigned int*)(0x42A00408UL))) +#define bM4_MPU_RGD8_MPURG8SIZE3 (*((volatile unsigned int*)(0x42A0040CUL))) +#define bM4_MPU_RGD8_MPURG8SIZE4 (*((volatile unsigned int*)(0x42A00410UL))) +#define bM4_MPU_RGD8_MPURG8ADDR0 (*((volatile unsigned int*)(0x42A00414UL))) +#define bM4_MPU_RGD8_MPURG8ADDR1 (*((volatile unsigned int*)(0x42A00418UL))) +#define bM4_MPU_RGD8_MPURG8ADDR2 (*((volatile unsigned int*)(0x42A0041CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR3 (*((volatile unsigned int*)(0x42A00420UL))) +#define bM4_MPU_RGD8_MPURG8ADDR4 (*((volatile unsigned int*)(0x42A00424UL))) +#define bM4_MPU_RGD8_MPURG8ADDR5 (*((volatile unsigned int*)(0x42A00428UL))) +#define bM4_MPU_RGD8_MPURG8ADDR6 (*((volatile unsigned int*)(0x42A0042CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR7 (*((volatile unsigned int*)(0x42A00430UL))) +#define bM4_MPU_RGD8_MPURG8ADDR8 (*((volatile unsigned int*)(0x42A00434UL))) +#define bM4_MPU_RGD8_MPURG8ADDR9 (*((volatile unsigned int*)(0x42A00438UL))) +#define bM4_MPU_RGD8_MPURG8ADDR10 (*((volatile unsigned int*)(0x42A0043CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR11 (*((volatile unsigned int*)(0x42A00440UL))) +#define bM4_MPU_RGD8_MPURG8ADDR12 (*((volatile unsigned int*)(0x42A00444UL))) +#define bM4_MPU_RGD8_MPURG8ADDR13 (*((volatile unsigned int*)(0x42A00448UL))) +#define bM4_MPU_RGD8_MPURG8ADDR14 (*((volatile unsigned int*)(0x42A0044CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR15 (*((volatile unsigned int*)(0x42A00450UL))) +#define bM4_MPU_RGD8_MPURG8ADDR16 (*((volatile unsigned int*)(0x42A00454UL))) +#define bM4_MPU_RGD8_MPURG8ADDR17 (*((volatile unsigned int*)(0x42A00458UL))) +#define bM4_MPU_RGD8_MPURG8ADDR18 (*((volatile unsigned int*)(0x42A0045CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR19 (*((volatile unsigned int*)(0x42A00460UL))) +#define bM4_MPU_RGD8_MPURG8ADDR20 (*((volatile unsigned int*)(0x42A00464UL))) +#define bM4_MPU_RGD8_MPURG8ADDR21 (*((volatile unsigned int*)(0x42A00468UL))) +#define bM4_MPU_RGD8_MPURG8ADDR22 (*((volatile unsigned int*)(0x42A0046CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR23 (*((volatile unsigned int*)(0x42A00470UL))) +#define bM4_MPU_RGD8_MPURG8ADDR24 (*((volatile unsigned int*)(0x42A00474UL))) +#define bM4_MPU_RGD8_MPURG8ADDR25 (*((volatile unsigned int*)(0x42A00478UL))) +#define bM4_MPU_RGD8_MPURG8ADDR26 (*((volatile unsigned int*)(0x42A0047CUL))) +#define bM4_MPU_RGD9_MPURG9SIZE0 (*((volatile unsigned int*)(0x42A00480UL))) +#define bM4_MPU_RGD9_MPURG9SIZE1 (*((volatile unsigned int*)(0x42A00484UL))) +#define bM4_MPU_RGD9_MPURG9SIZE2 (*((volatile unsigned int*)(0x42A00488UL))) +#define bM4_MPU_RGD9_MPURG9SIZE3 (*((volatile unsigned int*)(0x42A0048CUL))) +#define bM4_MPU_RGD9_MPURG9SIZE4 (*((volatile unsigned int*)(0x42A00490UL))) +#define bM4_MPU_RGD9_MPURG9ADDR0 (*((volatile unsigned int*)(0x42A00494UL))) +#define bM4_MPU_RGD9_MPURG9ADDR1 (*((volatile unsigned int*)(0x42A00498UL))) +#define bM4_MPU_RGD9_MPURG9ADDR2 (*((volatile unsigned int*)(0x42A0049CUL))) +#define bM4_MPU_RGD9_MPURG9ADDR3 (*((volatile unsigned int*)(0x42A004A0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR4 (*((volatile unsigned int*)(0x42A004A4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR5 (*((volatile unsigned int*)(0x42A004A8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR6 (*((volatile unsigned int*)(0x42A004ACUL))) +#define bM4_MPU_RGD9_MPURG9ADDR7 (*((volatile unsigned int*)(0x42A004B0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR8 (*((volatile unsigned int*)(0x42A004B4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR9 (*((volatile unsigned int*)(0x42A004B8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR10 (*((volatile unsigned int*)(0x42A004BCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR11 (*((volatile unsigned int*)(0x42A004C0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR12 (*((volatile unsigned int*)(0x42A004C4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR13 (*((volatile unsigned int*)(0x42A004C8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR14 (*((volatile unsigned int*)(0x42A004CCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR15 (*((volatile unsigned int*)(0x42A004D0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR16 (*((volatile unsigned int*)(0x42A004D4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR17 (*((volatile unsigned int*)(0x42A004D8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR18 (*((volatile unsigned int*)(0x42A004DCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR19 (*((volatile unsigned int*)(0x42A004E0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR20 (*((volatile unsigned int*)(0x42A004E4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR21 (*((volatile unsigned int*)(0x42A004E8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR22 (*((volatile unsigned int*)(0x42A004ECUL))) +#define bM4_MPU_RGD9_MPURG9ADDR23 (*((volatile unsigned int*)(0x42A004F0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR24 (*((volatile unsigned int*)(0x42A004F4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR25 (*((volatile unsigned int*)(0x42A004F8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR26 (*((volatile unsigned int*)(0x42A004FCUL))) +#define bM4_MPU_RGD10_MPURG10SIZE0 (*((volatile unsigned int*)(0x42A00500UL))) +#define bM4_MPU_RGD10_MPURG10SIZE1 (*((volatile unsigned int*)(0x42A00504UL))) +#define bM4_MPU_RGD10_MPURG10SIZE2 (*((volatile unsigned int*)(0x42A00508UL))) +#define bM4_MPU_RGD10_MPURG10SIZE3 (*((volatile unsigned int*)(0x42A0050CUL))) +#define bM4_MPU_RGD10_MPURG10SIZE4 (*((volatile unsigned int*)(0x42A00510UL))) +#define bM4_MPU_RGD10_MPURG10ADDR0 (*((volatile unsigned int*)(0x42A00514UL))) +#define bM4_MPU_RGD10_MPURG10ADDR1 (*((volatile unsigned int*)(0x42A00518UL))) +#define bM4_MPU_RGD10_MPURG10ADDR2 (*((volatile unsigned int*)(0x42A0051CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR3 (*((volatile unsigned int*)(0x42A00520UL))) +#define bM4_MPU_RGD10_MPURG10ADDR4 (*((volatile unsigned int*)(0x42A00524UL))) +#define bM4_MPU_RGD10_MPURG10ADDR5 (*((volatile unsigned int*)(0x42A00528UL))) +#define bM4_MPU_RGD10_MPURG10ADDR6 (*((volatile unsigned int*)(0x42A0052CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR7 (*((volatile unsigned int*)(0x42A00530UL))) +#define bM4_MPU_RGD10_MPURG10ADDR8 (*((volatile unsigned int*)(0x42A00534UL))) +#define bM4_MPU_RGD10_MPURG10ADDR9 (*((volatile unsigned int*)(0x42A00538UL))) +#define bM4_MPU_RGD10_MPURG10ADDR10 (*((volatile unsigned int*)(0x42A0053CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR11 (*((volatile unsigned int*)(0x42A00540UL))) +#define bM4_MPU_RGD10_MPURG10ADDR12 (*((volatile unsigned int*)(0x42A00544UL))) +#define bM4_MPU_RGD10_MPURG10ADDR13 (*((volatile unsigned int*)(0x42A00548UL))) +#define bM4_MPU_RGD10_MPURG10ADDR14 (*((volatile unsigned int*)(0x42A0054CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR15 (*((volatile unsigned int*)(0x42A00550UL))) +#define bM4_MPU_RGD10_MPURG10ADDR16 (*((volatile unsigned int*)(0x42A00554UL))) +#define bM4_MPU_RGD10_MPURG10ADDR17 (*((volatile unsigned int*)(0x42A00558UL))) +#define bM4_MPU_RGD10_MPURG10ADDR18 (*((volatile unsigned int*)(0x42A0055CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR19 (*((volatile unsigned int*)(0x42A00560UL))) +#define bM4_MPU_RGD10_MPURG10ADDR20 (*((volatile unsigned int*)(0x42A00564UL))) +#define bM4_MPU_RGD10_MPURG10ADDR21 (*((volatile unsigned int*)(0x42A00568UL))) +#define bM4_MPU_RGD10_MPURG10ADDR22 (*((volatile unsigned int*)(0x42A0056CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR23 (*((volatile unsigned int*)(0x42A00570UL))) +#define bM4_MPU_RGD10_MPURG10ADDR24 (*((volatile unsigned int*)(0x42A00574UL))) +#define bM4_MPU_RGD10_MPURG10ADDR25 (*((volatile unsigned int*)(0x42A00578UL))) +#define bM4_MPU_RGD10_MPURG10ADDR26 (*((volatile unsigned int*)(0x42A0057CUL))) +#define bM4_MPU_RGD11_MPURG11SIZE0 (*((volatile unsigned int*)(0x42A00580UL))) +#define bM4_MPU_RGD11_MPURG11SIZE1 (*((volatile unsigned int*)(0x42A00584UL))) +#define bM4_MPU_RGD11_MPURG11SIZE2 (*((volatile unsigned int*)(0x42A00588UL))) +#define bM4_MPU_RGD11_MPURG11SIZE3 (*((volatile unsigned int*)(0x42A0058CUL))) +#define bM4_MPU_RGD11_MPURG11SIZE4 (*((volatile unsigned int*)(0x42A00590UL))) +#define bM4_MPU_RGD11_MPURG11ADDR0 (*((volatile unsigned int*)(0x42A00594UL))) +#define bM4_MPU_RGD11_MPURG11ADDR1 (*((volatile unsigned int*)(0x42A00598UL))) +#define bM4_MPU_RGD11_MPURG11ADDR2 (*((volatile unsigned int*)(0x42A0059CUL))) +#define bM4_MPU_RGD11_MPURG11ADDR3 (*((volatile unsigned int*)(0x42A005A0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR4 (*((volatile unsigned int*)(0x42A005A4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR5 (*((volatile unsigned int*)(0x42A005A8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR6 (*((volatile unsigned int*)(0x42A005ACUL))) +#define bM4_MPU_RGD11_MPURG11ADDR7 (*((volatile unsigned int*)(0x42A005B0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR8 (*((volatile unsigned int*)(0x42A005B4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR9 (*((volatile unsigned int*)(0x42A005B8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR10 (*((volatile unsigned int*)(0x42A005BCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR11 (*((volatile unsigned int*)(0x42A005C0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR12 (*((volatile unsigned int*)(0x42A005C4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR13 (*((volatile unsigned int*)(0x42A005C8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR14 (*((volatile unsigned int*)(0x42A005CCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR15 (*((volatile unsigned int*)(0x42A005D0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR16 (*((volatile unsigned int*)(0x42A005D4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR17 (*((volatile unsigned int*)(0x42A005D8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR18 (*((volatile unsigned int*)(0x42A005DCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR19 (*((volatile unsigned int*)(0x42A005E0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR20 (*((volatile unsigned int*)(0x42A005E4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR21 (*((volatile unsigned int*)(0x42A005E8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR22 (*((volatile unsigned int*)(0x42A005ECUL))) +#define bM4_MPU_RGD11_MPURG11ADDR23 (*((volatile unsigned int*)(0x42A005F0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR24 (*((volatile unsigned int*)(0x42A005F4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR25 (*((volatile unsigned int*)(0x42A005F8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR26 (*((volatile unsigned int*)(0x42A005FCUL))) +#define bM4_MPU_RGD12_MPURG12SIZE0 (*((volatile unsigned int*)(0x42A00600UL))) +#define bM4_MPU_RGD12_MPURG12SIZE1 (*((volatile unsigned int*)(0x42A00604UL))) +#define bM4_MPU_RGD12_MPURG12SIZE2 (*((volatile unsigned int*)(0x42A00608UL))) +#define bM4_MPU_RGD12_MPURG12SIZE3 (*((volatile unsigned int*)(0x42A0060CUL))) +#define bM4_MPU_RGD12_MPURG12SIZE4 (*((volatile unsigned int*)(0x42A00610UL))) +#define bM4_MPU_RGD12_MPURG12ADDR0 (*((volatile unsigned int*)(0x42A00614UL))) +#define bM4_MPU_RGD12_MPURG12ADDR1 (*((volatile unsigned int*)(0x42A00618UL))) +#define bM4_MPU_RGD12_MPURG12ADDR2 (*((volatile unsigned int*)(0x42A0061CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR3 (*((volatile unsigned int*)(0x42A00620UL))) +#define bM4_MPU_RGD12_MPURG12ADDR4 (*((volatile unsigned int*)(0x42A00624UL))) +#define bM4_MPU_RGD12_MPURG12ADDR5 (*((volatile unsigned int*)(0x42A00628UL))) +#define bM4_MPU_RGD12_MPURG12ADDR6 (*((volatile unsigned int*)(0x42A0062CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR7 (*((volatile unsigned int*)(0x42A00630UL))) +#define bM4_MPU_RGD12_MPURG12ADDR8 (*((volatile unsigned int*)(0x42A00634UL))) +#define bM4_MPU_RGD12_MPURG12ADDR9 (*((volatile unsigned int*)(0x42A00638UL))) +#define bM4_MPU_RGD12_MPURG12ADDR10 (*((volatile unsigned int*)(0x42A0063CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR11 (*((volatile unsigned int*)(0x42A00640UL))) +#define bM4_MPU_RGD12_MPURG12ADDR12 (*((volatile unsigned int*)(0x42A00644UL))) +#define bM4_MPU_RGD12_MPURG12ADDR13 (*((volatile unsigned int*)(0x42A00648UL))) +#define bM4_MPU_RGD12_MPURG12ADDR14 (*((volatile unsigned int*)(0x42A0064CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR15 (*((volatile unsigned int*)(0x42A00650UL))) +#define bM4_MPU_RGD12_MPURG12ADDR16 (*((volatile unsigned int*)(0x42A00654UL))) +#define bM4_MPU_RGD12_MPURG12ADDR17 (*((volatile unsigned int*)(0x42A00658UL))) +#define bM4_MPU_RGD12_MPURG12ADDR18 (*((volatile unsigned int*)(0x42A0065CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR19 (*((volatile unsigned int*)(0x42A00660UL))) +#define bM4_MPU_RGD12_MPURG12ADDR20 (*((volatile unsigned int*)(0x42A00664UL))) +#define bM4_MPU_RGD12_MPURG12ADDR21 (*((volatile unsigned int*)(0x42A00668UL))) +#define bM4_MPU_RGD12_MPURG12ADDR22 (*((volatile unsigned int*)(0x42A0066CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR23 (*((volatile unsigned int*)(0x42A00670UL))) +#define bM4_MPU_RGD12_MPURG12ADDR24 (*((volatile unsigned int*)(0x42A00674UL))) +#define bM4_MPU_RGD12_MPURG12ADDR25 (*((volatile unsigned int*)(0x42A00678UL))) +#define bM4_MPU_RGD12_MPURG12ADDR26 (*((volatile unsigned int*)(0x42A0067CUL))) +#define bM4_MPU_RGD13_MPURG13SIZE0 (*((volatile unsigned int*)(0x42A00680UL))) +#define bM4_MPU_RGD13_MPURG13SIZE1 (*((volatile unsigned int*)(0x42A00684UL))) +#define bM4_MPU_RGD13_MPURG13SIZE2 (*((volatile unsigned int*)(0x42A00688UL))) +#define bM4_MPU_RGD13_MPURG13SIZE3 (*((volatile unsigned int*)(0x42A0068CUL))) +#define bM4_MPU_RGD13_MPURG13SIZE4 (*((volatile unsigned int*)(0x42A00690UL))) +#define bM4_MPU_RGD13_MPURG13ADDR0 (*((volatile unsigned int*)(0x42A00694UL))) +#define bM4_MPU_RGD13_MPURG13ADDR1 (*((volatile unsigned int*)(0x42A00698UL))) +#define bM4_MPU_RGD13_MPURG13ADDR2 (*((volatile unsigned int*)(0x42A0069CUL))) +#define bM4_MPU_RGD13_MPURG13ADDR3 (*((volatile unsigned int*)(0x42A006A0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR4 (*((volatile unsigned int*)(0x42A006A4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR5 (*((volatile unsigned int*)(0x42A006A8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR6 (*((volatile unsigned int*)(0x42A006ACUL))) +#define bM4_MPU_RGD13_MPURG13ADDR7 (*((volatile unsigned int*)(0x42A006B0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR8 (*((volatile unsigned int*)(0x42A006B4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR9 (*((volatile unsigned int*)(0x42A006B8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR10 (*((volatile unsigned int*)(0x42A006BCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR11 (*((volatile unsigned int*)(0x42A006C0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR12 (*((volatile unsigned int*)(0x42A006C4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR13 (*((volatile unsigned int*)(0x42A006C8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR14 (*((volatile unsigned int*)(0x42A006CCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR15 (*((volatile unsigned int*)(0x42A006D0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR16 (*((volatile unsigned int*)(0x42A006D4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR17 (*((volatile unsigned int*)(0x42A006D8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR18 (*((volatile unsigned int*)(0x42A006DCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR19 (*((volatile unsigned int*)(0x42A006E0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR20 (*((volatile unsigned int*)(0x42A006E4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR21 (*((volatile unsigned int*)(0x42A006E8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR22 (*((volatile unsigned int*)(0x42A006ECUL))) +#define bM4_MPU_RGD13_MPURG13ADDR23 (*((volatile unsigned int*)(0x42A006F0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR24 (*((volatile unsigned int*)(0x42A006F4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR25 (*((volatile unsigned int*)(0x42A006F8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR26 (*((volatile unsigned int*)(0x42A006FCUL))) +#define bM4_MPU_RGD14_MPURG14SIZE0 (*((volatile unsigned int*)(0x42A00700UL))) +#define bM4_MPU_RGD14_MPURG14SIZE1 (*((volatile unsigned int*)(0x42A00704UL))) +#define bM4_MPU_RGD14_MPURG14SIZE2 (*((volatile unsigned int*)(0x42A00708UL))) +#define bM4_MPU_RGD14_MPURG14SIZE3 (*((volatile unsigned int*)(0x42A0070CUL))) +#define bM4_MPU_RGD14_MPURG14SIZE4 (*((volatile unsigned int*)(0x42A00710UL))) +#define bM4_MPU_RGD14_MPURG14ADDR0 (*((volatile unsigned int*)(0x42A00714UL))) +#define bM4_MPU_RGD14_MPURG14ADDR1 (*((volatile unsigned int*)(0x42A00718UL))) +#define bM4_MPU_RGD14_MPURG14ADDR2 (*((volatile unsigned int*)(0x42A0071CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR3 (*((volatile unsigned int*)(0x42A00720UL))) +#define bM4_MPU_RGD14_MPURG14ADDR4 (*((volatile unsigned int*)(0x42A00724UL))) +#define bM4_MPU_RGD14_MPURG14ADDR5 (*((volatile unsigned int*)(0x42A00728UL))) +#define bM4_MPU_RGD14_MPURG14ADDR6 (*((volatile unsigned int*)(0x42A0072CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR7 (*((volatile unsigned int*)(0x42A00730UL))) +#define bM4_MPU_RGD14_MPURG14ADDR8 (*((volatile unsigned int*)(0x42A00734UL))) +#define bM4_MPU_RGD14_MPURG14ADDR9 (*((volatile unsigned int*)(0x42A00738UL))) +#define bM4_MPU_RGD14_MPURG14ADDR10 (*((volatile unsigned int*)(0x42A0073CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR11 (*((volatile unsigned int*)(0x42A00740UL))) +#define bM4_MPU_RGD14_MPURG14ADDR12 (*((volatile unsigned int*)(0x42A00744UL))) +#define bM4_MPU_RGD14_MPURG14ADDR13 (*((volatile unsigned int*)(0x42A00748UL))) +#define bM4_MPU_RGD14_MPURG14ADDR14 (*((volatile unsigned int*)(0x42A0074CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR15 (*((volatile unsigned int*)(0x42A00750UL))) +#define bM4_MPU_RGD14_MPURG14ADDR16 (*((volatile unsigned int*)(0x42A00754UL))) +#define bM4_MPU_RGD14_MPURG14ADDR17 (*((volatile unsigned int*)(0x42A00758UL))) +#define bM4_MPU_RGD14_MPURG14ADDR18 (*((volatile unsigned int*)(0x42A0075CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR19 (*((volatile unsigned int*)(0x42A00760UL))) +#define bM4_MPU_RGD14_MPURG14ADDR20 (*((volatile unsigned int*)(0x42A00764UL))) +#define bM4_MPU_RGD14_MPURG14ADDR21 (*((volatile unsigned int*)(0x42A00768UL))) +#define bM4_MPU_RGD14_MPURG14ADDR22 (*((volatile unsigned int*)(0x42A0076CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR23 (*((volatile unsigned int*)(0x42A00770UL))) +#define bM4_MPU_RGD14_MPURG14ADDR24 (*((volatile unsigned int*)(0x42A00774UL))) +#define bM4_MPU_RGD14_MPURG14ADDR25 (*((volatile unsigned int*)(0x42A00778UL))) +#define bM4_MPU_RGD14_MPURG14ADDR26 (*((volatile unsigned int*)(0x42A0077CUL))) +#define bM4_MPU_RGD15_MPURG15SIZE0 (*((volatile unsigned int*)(0x42A00780UL))) +#define bM4_MPU_RGD15_MPURG15SIZE1 (*((volatile unsigned int*)(0x42A00784UL))) +#define bM4_MPU_RGD15_MPURG15SIZE2 (*((volatile unsigned int*)(0x42A00788UL))) +#define bM4_MPU_RGD15_MPURG15SIZE3 (*((volatile unsigned int*)(0x42A0078CUL))) +#define bM4_MPU_RGD15_MPURG15SIZE4 (*((volatile unsigned int*)(0x42A00790UL))) +#define bM4_MPU_RGD15_MPURG15ADDR0 (*((volatile unsigned int*)(0x42A00794UL))) +#define bM4_MPU_RGD15_MPURG15ADDR1 (*((volatile unsigned int*)(0x42A00798UL))) +#define bM4_MPU_RGD15_MPURG15ADDR2 (*((volatile unsigned int*)(0x42A0079CUL))) +#define bM4_MPU_RGD15_MPURG15ADDR3 (*((volatile unsigned int*)(0x42A007A0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR4 (*((volatile unsigned int*)(0x42A007A4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR5 (*((volatile unsigned int*)(0x42A007A8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR6 (*((volatile unsigned int*)(0x42A007ACUL))) +#define bM4_MPU_RGD15_MPURG15ADDR7 (*((volatile unsigned int*)(0x42A007B0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR8 (*((volatile unsigned int*)(0x42A007B4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR9 (*((volatile unsigned int*)(0x42A007B8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR10 (*((volatile unsigned int*)(0x42A007BCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR11 (*((volatile unsigned int*)(0x42A007C0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR12 (*((volatile unsigned int*)(0x42A007C4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR13 (*((volatile unsigned int*)(0x42A007C8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR14 (*((volatile unsigned int*)(0x42A007CCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR15 (*((volatile unsigned int*)(0x42A007D0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR16 (*((volatile unsigned int*)(0x42A007D4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR17 (*((volatile unsigned int*)(0x42A007D8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR18 (*((volatile unsigned int*)(0x42A007DCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR19 (*((volatile unsigned int*)(0x42A007E0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR20 (*((volatile unsigned int*)(0x42A007E4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR21 (*((volatile unsigned int*)(0x42A007E8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR22 (*((volatile unsigned int*)(0x42A007ECUL))) +#define bM4_MPU_RGD15_MPURG15ADDR23 (*((volatile unsigned int*)(0x42A007F0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR24 (*((volatile unsigned int*)(0x42A007F4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR25 (*((volatile unsigned int*)(0x42A007F8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR26 (*((volatile unsigned int*)(0x42A007FCUL))) +#define bM4_MPU_RGCR0_S2RG0RP (*((volatile unsigned int*)(0x42A00800UL))) +#define bM4_MPU_RGCR0_S2RG0WP (*((volatile unsigned int*)(0x42A00804UL))) +#define bM4_MPU_RGCR0_S2RG0E (*((volatile unsigned int*)(0x42A0081CUL))) +#define bM4_MPU_RGCR0_S1RG0RP (*((volatile unsigned int*)(0x42A00820UL))) +#define bM4_MPU_RGCR0_S1RG0WP (*((volatile unsigned int*)(0x42A00824UL))) +#define bM4_MPU_RGCR0_S1RG0E (*((volatile unsigned int*)(0x42A0083CUL))) +#define bM4_MPU_RGCR0_FRG0RP (*((volatile unsigned int*)(0x42A00840UL))) +#define bM4_MPU_RGCR0_FRG0WP (*((volatile unsigned int*)(0x42A00844UL))) +#define bM4_MPU_RGCR0_FRG0E (*((volatile unsigned int*)(0x42A0085CUL))) +#define bM4_MPU_RGCR1_S2RG1RP (*((volatile unsigned int*)(0x42A00880UL))) +#define bM4_MPU_RGCR1_S2RG1WP (*((volatile unsigned int*)(0x42A00884UL))) +#define bM4_MPU_RGCR1_S2RG1E (*((volatile unsigned int*)(0x42A0089CUL))) +#define bM4_MPU_RGCR1_S1RG1RP (*((volatile unsigned int*)(0x42A008A0UL))) +#define bM4_MPU_RGCR1_S1RG1WP (*((volatile unsigned int*)(0x42A008A4UL))) +#define bM4_MPU_RGCR1_S1RG1E (*((volatile unsigned int*)(0x42A008BCUL))) +#define bM4_MPU_RGCR1_FRG1RP (*((volatile unsigned int*)(0x42A008C0UL))) +#define bM4_MPU_RGCR1_FRG1WP (*((volatile unsigned int*)(0x42A008C4UL))) +#define bM4_MPU_RGCR1_FRG1E (*((volatile unsigned int*)(0x42A008DCUL))) +#define bM4_MPU_RGCR2_S2RG2RP (*((volatile unsigned int*)(0x42A00900UL))) +#define bM4_MPU_RGCR2_S2RG2WP (*((volatile unsigned int*)(0x42A00904UL))) +#define bM4_MPU_RGCR2_S2RG2E (*((volatile unsigned int*)(0x42A0091CUL))) +#define bM4_MPU_RGCR2_S1RG2RP (*((volatile unsigned int*)(0x42A00920UL))) +#define bM4_MPU_RGCR2_S1RG2WP (*((volatile unsigned int*)(0x42A00924UL))) +#define bM4_MPU_RGCR2_S1RG2E (*((volatile unsigned int*)(0x42A0093CUL))) +#define bM4_MPU_RGCR2_FRG2RP (*((volatile unsigned int*)(0x42A00940UL))) +#define bM4_MPU_RGCR2_FRG2WP (*((volatile unsigned int*)(0x42A00944UL))) +#define bM4_MPU_RGCR2_FRG2E (*((volatile unsigned int*)(0x42A0095CUL))) +#define bM4_MPU_RGCR3_S2RG3RP (*((volatile unsigned int*)(0x42A00980UL))) +#define bM4_MPU_RGCR3_S2RG3WP (*((volatile unsigned int*)(0x42A00984UL))) +#define bM4_MPU_RGCR3_S2RG3E (*((volatile unsigned int*)(0x42A0099CUL))) +#define bM4_MPU_RGCR3_S1RG3RP (*((volatile unsigned int*)(0x42A009A0UL))) +#define bM4_MPU_RGCR3_S1RG3WP (*((volatile unsigned int*)(0x42A009A4UL))) +#define bM4_MPU_RGCR3_S1RG3E (*((volatile unsigned int*)(0x42A009BCUL))) +#define bM4_MPU_RGCR3_FRG3RP (*((volatile unsigned int*)(0x42A009C0UL))) +#define bM4_MPU_RGCR3_FRG3WP (*((volatile unsigned int*)(0x42A009C4UL))) +#define bM4_MPU_RGCR3_FRG3E (*((volatile unsigned int*)(0x42A009DCUL))) +#define bM4_MPU_RGCR4_S2RG4RP (*((volatile unsigned int*)(0x42A00A00UL))) +#define bM4_MPU_RGCR4_S2RG4WP (*((volatile unsigned int*)(0x42A00A04UL))) +#define bM4_MPU_RGCR4_S2RG4E (*((volatile unsigned int*)(0x42A00A1CUL))) +#define bM4_MPU_RGCR4_S1RG4RP (*((volatile unsigned int*)(0x42A00A20UL))) +#define bM4_MPU_RGCR4_S1RG4WP (*((volatile unsigned int*)(0x42A00A24UL))) +#define bM4_MPU_RGCR4_S1RG4E (*((volatile unsigned int*)(0x42A00A3CUL))) +#define bM4_MPU_RGCR4_FRG4RP (*((volatile unsigned int*)(0x42A00A40UL))) +#define bM4_MPU_RGCR4_FRG4WP (*((volatile unsigned int*)(0x42A00A44UL))) +#define bM4_MPU_RGCR4_FRG4E (*((volatile unsigned int*)(0x42A00A5CUL))) +#define bM4_MPU_RGCR5_S2RG5RP (*((volatile unsigned int*)(0x42A00A80UL))) +#define bM4_MPU_RGCR5_S2RG5WP (*((volatile unsigned int*)(0x42A00A84UL))) +#define bM4_MPU_RGCR5_S2RG5E (*((volatile unsigned int*)(0x42A00A9CUL))) +#define bM4_MPU_RGCR5_S1RG5RP (*((volatile unsigned int*)(0x42A00AA0UL))) +#define bM4_MPU_RGCR5_S1RG5WP (*((volatile unsigned int*)(0x42A00AA4UL))) +#define bM4_MPU_RGCR5_S1RG5E (*((volatile unsigned int*)(0x42A00ABCUL))) +#define bM4_MPU_RGCR5_FRG5RP (*((volatile unsigned int*)(0x42A00AC0UL))) +#define bM4_MPU_RGCR5_FRG5WP (*((volatile unsigned int*)(0x42A00AC4UL))) +#define bM4_MPU_RGCR5_FRG5E (*((volatile unsigned int*)(0x42A00ADCUL))) +#define bM4_MPU_RGCR6_S2RG6RP (*((volatile unsigned int*)(0x42A00B00UL))) +#define bM4_MPU_RGCR6_S2RG6WP (*((volatile unsigned int*)(0x42A00B04UL))) +#define bM4_MPU_RGCR6_S2RG6E (*((volatile unsigned int*)(0x42A00B1CUL))) +#define bM4_MPU_RGCR6_S1RG6RP (*((volatile unsigned int*)(0x42A00B20UL))) +#define bM4_MPU_RGCR6_S1RG6WP (*((volatile unsigned int*)(0x42A00B24UL))) +#define bM4_MPU_RGCR6_S1RG6E (*((volatile unsigned int*)(0x42A00B3CUL))) +#define bM4_MPU_RGCR6_FRG6RP (*((volatile unsigned int*)(0x42A00B40UL))) +#define bM4_MPU_RGCR6_FRG6WP (*((volatile unsigned int*)(0x42A00B44UL))) +#define bM4_MPU_RGCR6_FRG6E (*((volatile unsigned int*)(0x42A00B5CUL))) +#define bM4_MPU_RGCR7_S2RG7RP (*((volatile unsigned int*)(0x42A00B80UL))) +#define bM4_MPU_RGCR7_S2RG7WP (*((volatile unsigned int*)(0x42A00B84UL))) +#define bM4_MPU_RGCR7_S2RG7E (*((volatile unsigned int*)(0x42A00B9CUL))) +#define bM4_MPU_RGCR7_S1RG7RP (*((volatile unsigned int*)(0x42A00BA0UL))) +#define bM4_MPU_RGCR7_S1RG7WP (*((volatile unsigned int*)(0x42A00BA4UL))) +#define bM4_MPU_RGCR7_S1RG7E (*((volatile unsigned int*)(0x42A00BBCUL))) +#define bM4_MPU_RGCR7_FRG7RP (*((volatile unsigned int*)(0x42A00BC0UL))) +#define bM4_MPU_RGCR7_FRG7WP (*((volatile unsigned int*)(0x42A00BC4UL))) +#define bM4_MPU_RGCR7_FRG7E (*((volatile unsigned int*)(0x42A00BDCUL))) +#define bM4_MPU_RGCR8_S2RG8RP (*((volatile unsigned int*)(0x42A00C00UL))) +#define bM4_MPU_RGCR8_S2RG8WP (*((volatile unsigned int*)(0x42A00C04UL))) +#define bM4_MPU_RGCR8_S2RG8E (*((volatile unsigned int*)(0x42A00C1CUL))) +#define bM4_MPU_RGCR8_S1RG8RP (*((volatile unsigned int*)(0x42A00C20UL))) +#define bM4_MPU_RGCR8_S1RG8WP (*((volatile unsigned int*)(0x42A00C24UL))) +#define bM4_MPU_RGCR8_S1RG8E (*((volatile unsigned int*)(0x42A00C3CUL))) +#define bM4_MPU_RGCR9_S2RG9RP (*((volatile unsigned int*)(0x42A00C80UL))) +#define bM4_MPU_RGCR9_S2RG9WP (*((volatile unsigned int*)(0x42A00C84UL))) +#define bM4_MPU_RGCR9_S2RG9E (*((volatile unsigned int*)(0x42A00C9CUL))) +#define bM4_MPU_RGCR9_S1RG9RP (*((volatile unsigned int*)(0x42A00CA0UL))) +#define bM4_MPU_RGCR9_S1RG9WP (*((volatile unsigned int*)(0x42A00CA4UL))) +#define bM4_MPU_RGCR9_S1RG9E (*((volatile unsigned int*)(0x42A00CBCUL))) +#define bM4_MPU_RGCR10_S2RG10RP (*((volatile unsigned int*)(0x42A00D00UL))) +#define bM4_MPU_RGCR10_S2RG10WP (*((volatile unsigned int*)(0x42A00D04UL))) +#define bM4_MPU_RGCR10_S2RG10E (*((volatile unsigned int*)(0x42A00D1CUL))) +#define bM4_MPU_RGCR10_S1RG10RP (*((volatile unsigned int*)(0x42A00D20UL))) +#define bM4_MPU_RGCR10_S1RG10WP (*((volatile unsigned int*)(0x42A00D24UL))) +#define bM4_MPU_RGCR10_S1RG10E (*((volatile unsigned int*)(0x42A00D3CUL))) +#define bM4_MPU_RGCR11_S2RG11RP (*((volatile unsigned int*)(0x42A00D80UL))) +#define bM4_MPU_RGCR11_S2RG11WP (*((volatile unsigned int*)(0x42A00D84UL))) +#define bM4_MPU_RGCR11_S2RG11E (*((volatile unsigned int*)(0x42A00D9CUL))) +#define bM4_MPU_RGCR11_S1RG11RP (*((volatile unsigned int*)(0x42A00DA0UL))) +#define bM4_MPU_RGCR11_S1RG11WP (*((volatile unsigned int*)(0x42A00DA4UL))) +#define bM4_MPU_RGCR11_S1RG11E (*((volatile unsigned int*)(0x42A00DBCUL))) +#define bM4_MPU_RGCR12_S2RG12RP (*((volatile unsigned int*)(0x42A00E00UL))) +#define bM4_MPU_RGCR12_S2RG12WP (*((volatile unsigned int*)(0x42A00E04UL))) +#define bM4_MPU_RGCR12_S2RG12E (*((volatile unsigned int*)(0x42A00E1CUL))) +#define bM4_MPU_RGCR12_S1RG12RP (*((volatile unsigned int*)(0x42A00E20UL))) +#define bM4_MPU_RGCR12_S1RG12WP (*((volatile unsigned int*)(0x42A00E24UL))) +#define bM4_MPU_RGCR12_S1RG12E (*((volatile unsigned int*)(0x42A00E3CUL))) +#define bM4_MPU_RGCR13_S2RG13RP (*((volatile unsigned int*)(0x42A00E80UL))) +#define bM4_MPU_RGCR13_S2RG13WP (*((volatile unsigned int*)(0x42A00E84UL))) +#define bM4_MPU_RGCR13_S2RG13E (*((volatile unsigned int*)(0x42A00E9CUL))) +#define bM4_MPU_RGCR13_S1RG13RP (*((volatile unsigned int*)(0x42A00EA0UL))) +#define bM4_MPU_RGCR13_S1RG13WP (*((volatile unsigned int*)(0x42A00EA4UL))) +#define bM4_MPU_RGCR13_S1RG13E (*((volatile unsigned int*)(0x42A00EBCUL))) +#define bM4_MPU_RGCR14_S2RG14RP (*((volatile unsigned int*)(0x42A00F00UL))) +#define bM4_MPU_RGCR14_S2RG14WP (*((volatile unsigned int*)(0x42A00F04UL))) +#define bM4_MPU_RGCR14_S2RG14E (*((volatile unsigned int*)(0x42A00F1CUL))) +#define bM4_MPU_RGCR14_S1RG14RP (*((volatile unsigned int*)(0x42A00F20UL))) +#define bM4_MPU_RGCR14_S1RG14WP (*((volatile unsigned int*)(0x42A00F24UL))) +#define bM4_MPU_RGCR14_S1RG14E (*((volatile unsigned int*)(0x42A00F3CUL))) +#define bM4_MPU_RGCR15_S2RG15RP (*((volatile unsigned int*)(0x42A00F80UL))) +#define bM4_MPU_RGCR15_S2RG15WP (*((volatile unsigned int*)(0x42A00F84UL))) +#define bM4_MPU_RGCR15_S2RG15E (*((volatile unsigned int*)(0x42A00F9CUL))) +#define bM4_MPU_RGCR15_S1RG15RP (*((volatile unsigned int*)(0x42A00FA0UL))) +#define bM4_MPU_RGCR15_S1RG15WP (*((volatile unsigned int*)(0x42A00FA4UL))) +#define bM4_MPU_RGCR15_S1RG15E (*((volatile unsigned int*)(0x42A00FBCUL))) +#define bM4_MPU_CR_SMPU2BRP (*((volatile unsigned int*)(0x42A01000UL))) +#define bM4_MPU_CR_SMPU2BWP (*((volatile unsigned int*)(0x42A01004UL))) +#define bM4_MPU_CR_SMPU2ACT0 (*((volatile unsigned int*)(0x42A01008UL))) +#define bM4_MPU_CR_SMPU2ACT1 (*((volatile unsigned int*)(0x42A0100CUL))) +#define bM4_MPU_CR_SMPU2E (*((volatile unsigned int*)(0x42A0101CUL))) +#define bM4_MPU_CR_SMPU1BRP (*((volatile unsigned int*)(0x42A01020UL))) +#define bM4_MPU_CR_SMPU1BWP (*((volatile unsigned int*)(0x42A01024UL))) +#define bM4_MPU_CR_SMPU1ACT0 (*((volatile unsigned int*)(0x42A01028UL))) +#define bM4_MPU_CR_SMPU1ACT1 (*((volatile unsigned int*)(0x42A0102CUL))) +#define bM4_MPU_CR_SMPU1E (*((volatile unsigned int*)(0x42A0103CUL))) +#define bM4_MPU_CR_FMPUBRP (*((volatile unsigned int*)(0x42A01040UL))) +#define bM4_MPU_CR_FMPUBWP (*((volatile unsigned int*)(0x42A01044UL))) +#define bM4_MPU_CR_FMPUACT0 (*((volatile unsigned int*)(0x42A01048UL))) +#define bM4_MPU_CR_FMPUACT1 (*((volatile unsigned int*)(0x42A0104CUL))) +#define bM4_MPU_CR_FMPUE (*((volatile unsigned int*)(0x42A0105CUL))) +#define bM4_MPU_SR_SMPU2EAF (*((volatile unsigned int*)(0x42A01080UL))) +#define bM4_MPU_SR_SMPU1EAF (*((volatile unsigned int*)(0x42A010A0UL))) +#define bM4_MPU_SR_FMPUEAF (*((volatile unsigned int*)(0x42A010C0UL))) +#define bM4_MPU_ECLR_SMPU2ECLR (*((volatile unsigned int*)(0x42A01100UL))) +#define bM4_MPU_ECLR_SMPU1ECLR (*((volatile unsigned int*)(0x42A01120UL))) +#define bM4_MPU_ECLR_FMPUECLR (*((volatile unsigned int*)(0x42A01140UL))) +#define bM4_MPU_WP_MPUWE (*((volatile unsigned int*)(0x42A01180UL))) +#define bM4_MPU_WP_WKEY0 (*((volatile unsigned int*)(0x42A01184UL))) +#define bM4_MPU_WP_WKEY1 (*((volatile unsigned int*)(0x42A01188UL))) +#define bM4_MPU_WP_WKEY2 (*((volatile unsigned int*)(0x42A0118CUL))) +#define bM4_MPU_WP_WKEY3 (*((volatile unsigned int*)(0x42A01190UL))) +#define bM4_MPU_WP_WKEY4 (*((volatile unsigned int*)(0x42A01194UL))) +#define bM4_MPU_WP_WKEY5 (*((volatile unsigned int*)(0x42A01198UL))) +#define bM4_MPU_WP_WKEY6 (*((volatile unsigned int*)(0x42A0119CUL))) +#define bM4_MPU_WP_WKEY7 (*((volatile unsigned int*)(0x42A011A0UL))) +#define bM4_MPU_WP_WKEY8 (*((volatile unsigned int*)(0x42A011A4UL))) +#define bM4_MPU_WP_WKEY9 (*((volatile unsigned int*)(0x42A011A8UL))) +#define bM4_MPU_WP_WKEY10 (*((volatile unsigned int*)(0x42A011ACUL))) +#define bM4_MPU_WP_WKEY11 (*((volatile unsigned int*)(0x42A011B0UL))) +#define bM4_MPU_WP_WKEY12 (*((volatile unsigned int*)(0x42A011B4UL))) +#define bM4_MPU_WP_WKEY13 (*((volatile unsigned int*)(0x42A011B8UL))) +#define bM4_MPU_WP_WKEY14 (*((volatile unsigned int*)(0x42A011BCUL))) +#define bM4_MSTP_FCG0_SRAMH (*((volatile unsigned int*)(0x42900000UL))) +#define bM4_MSTP_FCG0_SRAM12 (*((volatile unsigned int*)(0x42900010UL))) +#define bM4_MSTP_FCG0_SRAM3 (*((volatile unsigned int*)(0x42900020UL))) +#define bM4_MSTP_FCG0_SRAMRET (*((volatile unsigned int*)(0x42900028UL))) +#define bM4_MSTP_FCG0_DMA1 (*((volatile unsigned int*)(0x42900038UL))) +#define bM4_MSTP_FCG0_DMA2 (*((volatile unsigned int*)(0x4290003CUL))) +#define bM4_MSTP_FCG0_FCM (*((volatile unsigned int*)(0x42900040UL))) +#define bM4_MSTP_FCG0_AOS (*((volatile unsigned int*)(0x42900044UL))) +#define bM4_MSTP_FCG0_AES (*((volatile unsigned int*)(0x42900050UL))) +#define bM4_MSTP_FCG0_HASH (*((volatile unsigned int*)(0x42900054UL))) +#define bM4_MSTP_FCG0_TRNG (*((volatile unsigned int*)(0x42900058UL))) +#define bM4_MSTP_FCG0_CRC (*((volatile unsigned int*)(0x4290005CUL))) +#define bM4_MSTP_FCG0_DCU1 (*((volatile unsigned int*)(0x42900060UL))) +#define bM4_MSTP_FCG0_DCU2 (*((volatile unsigned int*)(0x42900064UL))) +#define bM4_MSTP_FCG0_DCU3 (*((volatile unsigned int*)(0x42900068UL))) +#define bM4_MSTP_FCG0_DCU4 (*((volatile unsigned int*)(0x4290006CUL))) +#define bM4_MSTP_FCG0_KEY (*((volatile unsigned int*)(0x4290007CUL))) +#define bM4_MSTP_FCG1_CAN (*((volatile unsigned int*)(0x42900080UL))) +#define bM4_MSTP_FCG1_QSPI (*((volatile unsigned int*)(0x4290008CUL))) +#define bM4_MSTP_FCG1_IIC1 (*((volatile unsigned int*)(0x42900090UL))) +#define bM4_MSTP_FCG1_IIC2 (*((volatile unsigned int*)(0x42900094UL))) +#define bM4_MSTP_FCG1_IIC3 (*((volatile unsigned int*)(0x42900098UL))) +#define bM4_MSTP_FCG1_USBFS (*((volatile unsigned int*)(0x429000A0UL))) +#define bM4_MSTP_FCG1_SDIOC1 (*((volatile unsigned int*)(0x429000A8UL))) +#define bM4_MSTP_FCG1_SDIOC2 (*((volatile unsigned int*)(0x429000ACUL))) +#define bM4_MSTP_FCG1_I2S1 (*((volatile unsigned int*)(0x429000B0UL))) +#define bM4_MSTP_FCG1_I2S2 (*((volatile unsigned int*)(0x429000B4UL))) +#define bM4_MSTP_FCG1_I2S3 (*((volatile unsigned int*)(0x429000B8UL))) +#define bM4_MSTP_FCG1_I2S4 (*((volatile unsigned int*)(0x429000BCUL))) +#define bM4_MSTP_FCG1_SPI1 (*((volatile unsigned int*)(0x429000C0UL))) +#define bM4_MSTP_FCG1_SPI2 (*((volatile unsigned int*)(0x429000C4UL))) +#define bM4_MSTP_FCG1_SPI3 (*((volatile unsigned int*)(0x429000C8UL))) +#define bM4_MSTP_FCG1_SPI4 (*((volatile unsigned int*)(0x429000CCUL))) +#define bM4_MSTP_FCG1_USART1 (*((volatile unsigned int*)(0x429000E0UL))) +#define bM4_MSTP_FCG1_USART2 (*((volatile unsigned int*)(0x429000E4UL))) +#define bM4_MSTP_FCG1_USART3 (*((volatile unsigned int*)(0x429000E8UL))) +#define bM4_MSTP_FCG1_USART4 (*((volatile unsigned int*)(0x429000ECUL))) +#define bM4_MSTP_FCG2_TIMER0_1 (*((volatile unsigned int*)(0x42900100UL))) +#define bM4_MSTP_FCG2_TIMER0_2 (*((volatile unsigned int*)(0x42900104UL))) +#define bM4_MSTP_FCG2_TIMERA_1 (*((volatile unsigned int*)(0x42900108UL))) +#define bM4_MSTP_FCG2_TIMERA_2 (*((volatile unsigned int*)(0x4290010CUL))) +#define bM4_MSTP_FCG2_TIMERA_3 (*((volatile unsigned int*)(0x42900110UL))) +#define bM4_MSTP_FCG2_TIMERA_4 (*((volatile unsigned int*)(0x42900114UL))) +#define bM4_MSTP_FCG2_TIMERA_5 (*((volatile unsigned int*)(0x42900118UL))) +#define bM4_MSTP_FCG2_TIMERA_6 (*((volatile unsigned int*)(0x4290011CUL))) +#define bM4_MSTP_FCG2_TIMER4_1 (*((volatile unsigned int*)(0x42900120UL))) +#define bM4_MSTP_FCG2_TIMER4_2 (*((volatile unsigned int*)(0x42900124UL))) +#define bM4_MSTP_FCG2_TIMER4_3 (*((volatile unsigned int*)(0x42900128UL))) +#define bM4_MSTP_FCG2_EMB (*((volatile unsigned int*)(0x4290013CUL))) +#define bM4_MSTP_FCG2_TIMER6_1 (*((volatile unsigned int*)(0x42900140UL))) +#define bM4_MSTP_FCG2_TIMER6_2 (*((volatile unsigned int*)(0x42900144UL))) +#define bM4_MSTP_FCG2_TIMER6_3 (*((volatile unsigned int*)(0x42900148UL))) +#define bM4_MSTP_FCG3_ADC1 (*((volatile unsigned int*)(0x42900180UL))) +#define bM4_MSTP_FCG3_ADC2 (*((volatile unsigned int*)(0x42900184UL))) +#define bM4_MSTP_FCG3_CMP (*((volatile unsigned int*)(0x429001A0UL))) +#define bM4_MSTP_FCG3_OTS (*((volatile unsigned int*)(0x429001B0UL))) +#define bM4_MSTP_FCG0PC_PRT0 (*((volatile unsigned int*)(0x42900200UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE0 (*((volatile unsigned int*)(0x42900240UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE1 (*((volatile unsigned int*)(0x42900244UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE2 (*((volatile unsigned int*)(0x42900248UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE3 (*((volatile unsigned int*)(0x4290024CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE4 (*((volatile unsigned int*)(0x42900250UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE5 (*((volatile unsigned int*)(0x42900254UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE6 (*((volatile unsigned int*)(0x42900258UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE7 (*((volatile unsigned int*)(0x4290025CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE8 (*((volatile unsigned int*)(0x42900260UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE9 (*((volatile unsigned int*)(0x42900264UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE10 (*((volatile unsigned int*)(0x42900268UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE11 (*((volatile unsigned int*)(0x4290026CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE12 (*((volatile unsigned int*)(0x42900270UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE13 (*((volatile unsigned int*)(0x42900274UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE14 (*((volatile unsigned int*)(0x42900278UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE15 (*((volatile unsigned int*)(0x4290027CUL))) +#define bM4_OTS_CTL_OTSST (*((volatile unsigned int*)(0x42948000UL))) +#define bM4_OTS_CTL_OTSCK (*((volatile unsigned int*)(0x42948004UL))) +#define bM4_OTS_CTL_OTSIE (*((volatile unsigned int*)(0x42948008UL))) +#define bM4_OTS_CTL_TSSTP (*((volatile unsigned int*)(0x4294800CUL))) +#define bM4_OTS_LPR_TSOFS0 (*((volatile unsigned int*)(0x42948100UL))) +#define bM4_OTS_LPR_TSOFS1 (*((volatile unsigned int*)(0x42948104UL))) +#define bM4_OTS_LPR_TSOFS2 (*((volatile unsigned int*)(0x42948108UL))) +#define bM4_OTS_LPR_TSOFS3 (*((volatile unsigned int*)(0x4294810CUL))) +#define bM4_OTS_LPR_TSOFS4 (*((volatile unsigned int*)(0x42948110UL))) +#define bM4_OTS_LPR_TSOFS5 (*((volatile unsigned int*)(0x42948114UL))) +#define bM4_OTS_LPR_TSOFS6 (*((volatile unsigned int*)(0x42948118UL))) +#define bM4_OTS_LPR_TSOFS7 (*((volatile unsigned int*)(0x4294811CUL))) +#define bM4_OTS_LPR_TSSLP0 (*((volatile unsigned int*)(0x42948120UL))) +#define bM4_OTS_LPR_TSSLP1 (*((volatile unsigned int*)(0x42948124UL))) +#define bM4_OTS_LPR_TSSLP2 (*((volatile unsigned int*)(0x42948128UL))) +#define bM4_OTS_LPR_TSSLP3 (*((volatile unsigned int*)(0x4294812CUL))) +#define bM4_OTS_LPR_TSSLP4 (*((volatile unsigned int*)(0x42948130UL))) +#define bM4_OTS_LPR_TSSLP5 (*((volatile unsigned int*)(0x42948134UL))) +#define bM4_OTS_LPR_TSSLP6 (*((volatile unsigned int*)(0x42948138UL))) +#define bM4_OTS_LPR_TSSLP7 (*((volatile unsigned int*)(0x4294813CUL))) +#define bM4_OTS_LPR_TSSLP8 (*((volatile unsigned int*)(0x42948140UL))) +#define bM4_OTS_LPR_TSSLP9 (*((volatile unsigned int*)(0x42948144UL))) +#define bM4_OTS_LPR_TSSLP10 (*((volatile unsigned int*)(0x42948148UL))) +#define bM4_OTS_LPR_TSSLP11 (*((volatile unsigned int*)(0x4294814CUL))) +#define bM4_OTS_LPR_TSSLP12 (*((volatile unsigned int*)(0x42948150UL))) +#define bM4_OTS_LPR_TSSLP13 (*((volatile unsigned int*)(0x42948154UL))) +#define bM4_OTS_LPR_TSSLP14 (*((volatile unsigned int*)(0x42948158UL))) +#define bM4_OTS_LPR_TSSLP15 (*((volatile unsigned int*)(0x4294815CUL))) +#define bM4_OTS_LPR_TSSLP16 (*((volatile unsigned int*)(0x42948160UL))) +#define bM4_OTS_LPR_TSSLP17 (*((volatile unsigned int*)(0x42948164UL))) +#define bM4_OTS_LPR_TSSLP18 (*((volatile unsigned int*)(0x42948168UL))) +#define bM4_OTS_LPR_TSSLP19 (*((volatile unsigned int*)(0x4294816CUL))) +#define bM4_OTS_LPR_TSSLP20 (*((volatile unsigned int*)(0x42948170UL))) +#define bM4_OTS_LPR_TSSLP21 (*((volatile unsigned int*)(0x42948174UL))) +#define bM4_OTS_LPR_TSSLP22 (*((volatile unsigned int*)(0x42948178UL))) +#define bM4_OTS_LPR_TSSLP23 (*((volatile unsigned int*)(0x4294817CUL))) +#define bM4_PERIC_USBFS_SYCTLREG_DFB (*((volatile unsigned int*)(0x42AA8000UL))) +#define bM4_PERIC_USBFS_SYCTLREG_SOFEN (*((volatile unsigned int*)(0x42AA8004UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC1 (*((volatile unsigned int*)(0x42AA8084UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC2 (*((volatile unsigned int*)(0x42AA808CUL))) +#define bM4_PORT_PIDRA_PIN00 (*((volatile unsigned int*)(0x42A70000UL))) +#define bM4_PORT_PIDRA_PIN01 (*((volatile unsigned int*)(0x42A70004UL))) +#define bM4_PORT_PIDRA_PIN02 (*((volatile unsigned int*)(0x42A70008UL))) +#define bM4_PORT_PIDRA_PIN03 (*((volatile unsigned int*)(0x42A7000CUL))) +#define bM4_PORT_PIDRA_PIN04 (*((volatile unsigned int*)(0x42A70010UL))) +#define bM4_PORT_PIDRA_PIN05 (*((volatile unsigned int*)(0x42A70014UL))) +#define bM4_PORT_PIDRA_PIN06 (*((volatile unsigned int*)(0x42A70018UL))) +#define bM4_PORT_PIDRA_PIN07 (*((volatile unsigned int*)(0x42A7001CUL))) +#define bM4_PORT_PIDRA_PIN08 (*((volatile unsigned int*)(0x42A70020UL))) +#define bM4_PORT_PIDRA_PIN09 (*((volatile unsigned int*)(0x42A70024UL))) +#define bM4_PORT_PIDRA_PIN10 (*((volatile unsigned int*)(0x42A70028UL))) +#define bM4_PORT_PIDRA_PIN11 (*((volatile unsigned int*)(0x42A7002CUL))) +#define bM4_PORT_PIDRA_PIN12 (*((volatile unsigned int*)(0x42A70030UL))) +#define bM4_PORT_PIDRA_PIN13 (*((volatile unsigned int*)(0x42A70034UL))) +#define bM4_PORT_PIDRA_PIN14 (*((volatile unsigned int*)(0x42A70038UL))) +#define bM4_PORT_PIDRA_PIN15 (*((volatile unsigned int*)(0x42A7003CUL))) +#define bM4_PORT_PODRA_POUT00 (*((volatile unsigned int*)(0x42A70080UL))) +#define bM4_PORT_PODRA_POUT01 (*((volatile unsigned int*)(0x42A70084UL))) +#define bM4_PORT_PODRA_POUT02 (*((volatile unsigned int*)(0x42A70088UL))) +#define bM4_PORT_PODRA_POUT03 (*((volatile unsigned int*)(0x42A7008CUL))) +#define bM4_PORT_PODRA_POUT04 (*((volatile unsigned int*)(0x42A70090UL))) +#define bM4_PORT_PODRA_POUT05 (*((volatile unsigned int*)(0x42A70094UL))) +#define bM4_PORT_PODRA_POUT06 (*((volatile unsigned int*)(0x42A70098UL))) +#define bM4_PORT_PODRA_POUT07 (*((volatile unsigned int*)(0x42A7009CUL))) +#define bM4_PORT_PODRA_POUT08 (*((volatile unsigned int*)(0x42A700A0UL))) +#define bM4_PORT_PODRA_POUT09 (*((volatile unsigned int*)(0x42A700A4UL))) +#define bM4_PORT_PODRA_POUT10 (*((volatile unsigned int*)(0x42A700A8UL))) +#define bM4_PORT_PODRA_POUT11 (*((volatile unsigned int*)(0x42A700ACUL))) +#define bM4_PORT_PODRA_POUT12 (*((volatile unsigned int*)(0x42A700B0UL))) +#define bM4_PORT_PODRA_POUT13 (*((volatile unsigned int*)(0x42A700B4UL))) +#define bM4_PORT_PODRA_POUT14 (*((volatile unsigned int*)(0x42A700B8UL))) +#define bM4_PORT_PODRA_POUT15 (*((volatile unsigned int*)(0x42A700BCUL))) +#define bM4_PORT_POERA_POUTE00 (*((volatile unsigned int*)(0x42A700C0UL))) +#define bM4_PORT_POERA_POUTE01 (*((volatile unsigned int*)(0x42A700C4UL))) +#define bM4_PORT_POERA_POUTE02 (*((volatile unsigned int*)(0x42A700C8UL))) +#define bM4_PORT_POERA_POUTE03 (*((volatile unsigned int*)(0x42A700CCUL))) +#define bM4_PORT_POERA_POUTE04 (*((volatile unsigned int*)(0x42A700D0UL))) +#define bM4_PORT_POERA_POUTE05 (*((volatile unsigned int*)(0x42A700D4UL))) +#define bM4_PORT_POERA_POUTE06 (*((volatile unsigned int*)(0x42A700D8UL))) +#define bM4_PORT_POERA_POUTE07 (*((volatile unsigned int*)(0x42A700DCUL))) +#define bM4_PORT_POERA_POUTE08 (*((volatile unsigned int*)(0x42A700E0UL))) +#define bM4_PORT_POERA_POUTE09 (*((volatile unsigned int*)(0x42A700E4UL))) +#define bM4_PORT_POERA_POUTE10 (*((volatile unsigned int*)(0x42A700E8UL))) +#define bM4_PORT_POERA_POUTE11 (*((volatile unsigned int*)(0x42A700ECUL))) +#define bM4_PORT_POERA_POUTE12 (*((volatile unsigned int*)(0x42A700F0UL))) +#define bM4_PORT_POERA_POUTE13 (*((volatile unsigned int*)(0x42A700F4UL))) +#define bM4_PORT_POERA_POUTE14 (*((volatile unsigned int*)(0x42A700F8UL))) +#define bM4_PORT_POERA_POUTE15 (*((volatile unsigned int*)(0x42A700FCUL))) +#define bM4_PORT_POSRA_POS00 (*((volatile unsigned int*)(0x42A70100UL))) +#define bM4_PORT_POSRA_POS01 (*((volatile unsigned int*)(0x42A70104UL))) +#define bM4_PORT_POSRA_POS02 (*((volatile unsigned int*)(0x42A70108UL))) +#define bM4_PORT_POSRA_POS03 (*((volatile unsigned int*)(0x42A7010CUL))) +#define bM4_PORT_POSRA_POS04 (*((volatile unsigned int*)(0x42A70110UL))) +#define bM4_PORT_POSRA_POS05 (*((volatile unsigned int*)(0x42A70114UL))) +#define bM4_PORT_POSRA_POS06 (*((volatile unsigned int*)(0x42A70118UL))) +#define bM4_PORT_POSRA_POS07 (*((volatile unsigned int*)(0x42A7011CUL))) +#define bM4_PORT_POSRA_POS08 (*((volatile unsigned int*)(0x42A70120UL))) +#define bM4_PORT_POSRA_POS09 (*((volatile unsigned int*)(0x42A70124UL))) +#define bM4_PORT_POSRA_POS10 (*((volatile unsigned int*)(0x42A70128UL))) +#define bM4_PORT_POSRA_POS11 (*((volatile unsigned int*)(0x42A7012CUL))) +#define bM4_PORT_POSRA_POS12 (*((volatile unsigned int*)(0x42A70130UL))) +#define bM4_PORT_POSRA_POS13 (*((volatile unsigned int*)(0x42A70134UL))) +#define bM4_PORT_POSRA_POS14 (*((volatile unsigned int*)(0x42A70138UL))) +#define bM4_PORT_POSRA_POS15 (*((volatile unsigned int*)(0x42A7013CUL))) +#define bM4_PORT_PORRA_POR00 (*((volatile unsigned int*)(0x42A70140UL))) +#define bM4_PORT_PORRA_POR01 (*((volatile unsigned int*)(0x42A70144UL))) +#define bM4_PORT_PORRA_POR02 (*((volatile unsigned int*)(0x42A70148UL))) +#define bM4_PORT_PORRA_POR03 (*((volatile unsigned int*)(0x42A7014CUL))) +#define bM4_PORT_PORRA_POR04 (*((volatile unsigned int*)(0x42A70150UL))) +#define bM4_PORT_PORRA_POR05 (*((volatile unsigned int*)(0x42A70154UL))) +#define bM4_PORT_PORRA_POR06 (*((volatile unsigned int*)(0x42A70158UL))) +#define bM4_PORT_PORRA_POR07 (*((volatile unsigned int*)(0x42A7015CUL))) +#define bM4_PORT_PORRA_POR08 (*((volatile unsigned int*)(0x42A70160UL))) +#define bM4_PORT_PORRA_POR09 (*((volatile unsigned int*)(0x42A70164UL))) +#define bM4_PORT_PORRA_POR10 (*((volatile unsigned int*)(0x42A70168UL))) +#define bM4_PORT_PORRA_POR11 (*((volatile unsigned int*)(0x42A7016CUL))) +#define bM4_PORT_PORRA_POR12 (*((volatile unsigned int*)(0x42A70170UL))) +#define bM4_PORT_PORRA_POR13 (*((volatile unsigned int*)(0x42A70174UL))) +#define bM4_PORT_PORRA_POR14 (*((volatile unsigned int*)(0x42A70178UL))) +#define bM4_PORT_PORRA_POR15 (*((volatile unsigned int*)(0x42A7017CUL))) +#define bM4_PORT_POTRA_POT00 (*((volatile unsigned int*)(0x42A70180UL))) +#define bM4_PORT_POTRA_POT01 (*((volatile unsigned int*)(0x42A70184UL))) +#define bM4_PORT_POTRA_POT02 (*((volatile unsigned int*)(0x42A70188UL))) +#define bM4_PORT_POTRA_POT03 (*((volatile unsigned int*)(0x42A7018CUL))) +#define bM4_PORT_POTRA_POT04 (*((volatile unsigned int*)(0x42A70190UL))) +#define bM4_PORT_POTRA_POT05 (*((volatile unsigned int*)(0x42A70194UL))) +#define bM4_PORT_POTRA_POT06 (*((volatile unsigned int*)(0x42A70198UL))) +#define bM4_PORT_POTRA_POT07 (*((volatile unsigned int*)(0x42A7019CUL))) +#define bM4_PORT_POTRA_POT08 (*((volatile unsigned int*)(0x42A701A0UL))) +#define bM4_PORT_POTRA_POT09 (*((volatile unsigned int*)(0x42A701A4UL))) +#define bM4_PORT_POTRA_POT10 (*((volatile unsigned int*)(0x42A701A8UL))) +#define bM4_PORT_POTRA_POT11 (*((volatile unsigned int*)(0x42A701ACUL))) +#define bM4_PORT_POTRA_POT12 (*((volatile unsigned int*)(0x42A701B0UL))) +#define bM4_PORT_POTRA_POT13 (*((volatile unsigned int*)(0x42A701B4UL))) +#define bM4_PORT_POTRA_POT14 (*((volatile unsigned int*)(0x42A701B8UL))) +#define bM4_PORT_POTRA_POT15 (*((volatile unsigned int*)(0x42A701BCUL))) +#define bM4_PORT_PIDRB_PIN00 (*((volatile unsigned int*)(0x42A70200UL))) +#define bM4_PORT_PIDRB_PIN01 (*((volatile unsigned int*)(0x42A70204UL))) +#define bM4_PORT_PIDRB_PIN02 (*((volatile unsigned int*)(0x42A70208UL))) +#define bM4_PORT_PIDRB_PIN03 (*((volatile unsigned int*)(0x42A7020CUL))) +#define bM4_PORT_PIDRB_PIN04 (*((volatile unsigned int*)(0x42A70210UL))) +#define bM4_PORT_PIDRB_PIN05 (*((volatile unsigned int*)(0x42A70214UL))) +#define bM4_PORT_PIDRB_PIN06 (*((volatile unsigned int*)(0x42A70218UL))) +#define bM4_PORT_PIDRB_PIN07 (*((volatile unsigned int*)(0x42A7021CUL))) +#define bM4_PORT_PIDRB_PIN08 (*((volatile unsigned int*)(0x42A70220UL))) +#define bM4_PORT_PIDRB_PIN09 (*((volatile unsigned int*)(0x42A70224UL))) +#define bM4_PORT_PIDRB_PIN10 (*((volatile unsigned int*)(0x42A70228UL))) +#define bM4_PORT_PIDRB_PIN11 (*((volatile unsigned int*)(0x42A7022CUL))) +#define bM4_PORT_PIDRB_PIN12 (*((volatile unsigned int*)(0x42A70230UL))) +#define bM4_PORT_PIDRB_PIN13 (*((volatile unsigned int*)(0x42A70234UL))) +#define bM4_PORT_PIDRB_PIN14 (*((volatile unsigned int*)(0x42A70238UL))) +#define bM4_PORT_PIDRB_PIN15 (*((volatile unsigned int*)(0x42A7023CUL))) +#define bM4_PORT_PODRB_POUT00 (*((volatile unsigned int*)(0x42A70280UL))) +#define bM4_PORT_PODRB_POUT01 (*((volatile unsigned int*)(0x42A70284UL))) +#define bM4_PORT_PODRB_POUT02 (*((volatile unsigned int*)(0x42A70288UL))) +#define bM4_PORT_PODRB_POUT03 (*((volatile unsigned int*)(0x42A7028CUL))) +#define bM4_PORT_PODRB_POUT04 (*((volatile unsigned int*)(0x42A70290UL))) +#define bM4_PORT_PODRB_POUT05 (*((volatile unsigned int*)(0x42A70294UL))) +#define bM4_PORT_PODRB_POUT06 (*((volatile unsigned int*)(0x42A70298UL))) +#define bM4_PORT_PODRB_POUT07 (*((volatile unsigned int*)(0x42A7029CUL))) +#define bM4_PORT_PODRB_POUT08 (*((volatile unsigned int*)(0x42A702A0UL))) +#define bM4_PORT_PODRB_POUT09 (*((volatile unsigned int*)(0x42A702A4UL))) +#define bM4_PORT_PODRB_POUT10 (*((volatile unsigned int*)(0x42A702A8UL))) +#define bM4_PORT_PODRB_POUT11 (*((volatile unsigned int*)(0x42A702ACUL))) +#define bM4_PORT_PODRB_POUT12 (*((volatile unsigned int*)(0x42A702B0UL))) +#define bM4_PORT_PODRB_POUT13 (*((volatile unsigned int*)(0x42A702B4UL))) +#define bM4_PORT_PODRB_POUT14 (*((volatile unsigned int*)(0x42A702B8UL))) +#define bM4_PORT_PODRB_POUT15 (*((volatile unsigned int*)(0x42A702BCUL))) +#define bM4_PORT_POERB_POUTE00 (*((volatile unsigned int*)(0x42A702C0UL))) +#define bM4_PORT_POERB_POUTE01 (*((volatile unsigned int*)(0x42A702C4UL))) +#define bM4_PORT_POERB_POUTE02 (*((volatile unsigned int*)(0x42A702C8UL))) +#define bM4_PORT_POERB_POUTE03 (*((volatile unsigned int*)(0x42A702CCUL))) +#define bM4_PORT_POERB_POUTE04 (*((volatile unsigned int*)(0x42A702D0UL))) +#define bM4_PORT_POERB_POUTE05 (*((volatile unsigned int*)(0x42A702D4UL))) +#define bM4_PORT_POERB_POUTE06 (*((volatile unsigned int*)(0x42A702D8UL))) +#define bM4_PORT_POERB_POUTE07 (*((volatile unsigned int*)(0x42A702DCUL))) +#define bM4_PORT_POERB_POUTE08 (*((volatile unsigned int*)(0x42A702E0UL))) +#define bM4_PORT_POERB_POUTE09 (*((volatile unsigned int*)(0x42A702E4UL))) +#define bM4_PORT_POERB_POUTE10 (*((volatile unsigned int*)(0x42A702E8UL))) +#define bM4_PORT_POERB_POUTE11 (*((volatile unsigned int*)(0x42A702ECUL))) +#define bM4_PORT_POERB_POUTE12 (*((volatile unsigned int*)(0x42A702F0UL))) +#define bM4_PORT_POERB_POUTE13 (*((volatile unsigned int*)(0x42A702F4UL))) +#define bM4_PORT_POERB_POUTE14 (*((volatile unsigned int*)(0x42A702F8UL))) +#define bM4_PORT_POERB_POUTE15 (*((volatile unsigned int*)(0x42A702FCUL))) +#define bM4_PORT_POSRB_POS00 (*((volatile unsigned int*)(0x42A70300UL))) +#define bM4_PORT_POSRB_POS01 (*((volatile unsigned int*)(0x42A70304UL))) +#define bM4_PORT_POSRB_POS02 (*((volatile unsigned int*)(0x42A70308UL))) +#define bM4_PORT_POSRB_POS03 (*((volatile unsigned int*)(0x42A7030CUL))) +#define bM4_PORT_POSRB_POS04 (*((volatile unsigned int*)(0x42A70310UL))) +#define bM4_PORT_POSRB_POS05 (*((volatile unsigned int*)(0x42A70314UL))) +#define bM4_PORT_POSRB_POS06 (*((volatile unsigned int*)(0x42A70318UL))) +#define bM4_PORT_POSRB_POS07 (*((volatile unsigned int*)(0x42A7031CUL))) +#define bM4_PORT_POSRB_POS08 (*((volatile unsigned int*)(0x42A70320UL))) +#define bM4_PORT_POSRB_POS09 (*((volatile unsigned int*)(0x42A70324UL))) +#define bM4_PORT_POSRB_POS10 (*((volatile unsigned int*)(0x42A70328UL))) +#define bM4_PORT_POSRB_POS11 (*((volatile unsigned int*)(0x42A7032CUL))) +#define bM4_PORT_POSRB_POS12 (*((volatile unsigned int*)(0x42A70330UL))) +#define bM4_PORT_POSRB_POS13 (*((volatile unsigned int*)(0x42A70334UL))) +#define bM4_PORT_POSRB_POS14 (*((volatile unsigned int*)(0x42A70338UL))) +#define bM4_PORT_POSRB_POS15 (*((volatile unsigned int*)(0x42A7033CUL))) +#define bM4_PORT_PORRB_POR00 (*((volatile unsigned int*)(0x42A70340UL))) +#define bM4_PORT_PORRB_POR01 (*((volatile unsigned int*)(0x42A70344UL))) +#define bM4_PORT_PORRB_POR02 (*((volatile unsigned int*)(0x42A70348UL))) +#define bM4_PORT_PORRB_POR03 (*((volatile unsigned int*)(0x42A7034CUL))) +#define bM4_PORT_PORRB_POR04 (*((volatile unsigned int*)(0x42A70350UL))) +#define bM4_PORT_PORRB_POR05 (*((volatile unsigned int*)(0x42A70354UL))) +#define bM4_PORT_PORRB_POR06 (*((volatile unsigned int*)(0x42A70358UL))) +#define bM4_PORT_PORRB_POR07 (*((volatile unsigned int*)(0x42A7035CUL))) +#define bM4_PORT_PORRB_POR08 (*((volatile unsigned int*)(0x42A70360UL))) +#define bM4_PORT_PORRB_POR09 (*((volatile unsigned int*)(0x42A70364UL))) +#define bM4_PORT_PORRB_POR10 (*((volatile unsigned int*)(0x42A70368UL))) +#define bM4_PORT_PORRB_POR11 (*((volatile unsigned int*)(0x42A7036CUL))) +#define bM4_PORT_PORRB_POR12 (*((volatile unsigned int*)(0x42A70370UL))) +#define bM4_PORT_PORRB_POR13 (*((volatile unsigned int*)(0x42A70374UL))) +#define bM4_PORT_PORRB_POR14 (*((volatile unsigned int*)(0x42A70378UL))) +#define bM4_PORT_PORRB_POR15 (*((volatile unsigned int*)(0x42A7037CUL))) +#define bM4_PORT_POTRB_POT00 (*((volatile unsigned int*)(0x42A70380UL))) +#define bM4_PORT_POTRB_POT01 (*((volatile unsigned int*)(0x42A70384UL))) +#define bM4_PORT_POTRB_POT02 (*((volatile unsigned int*)(0x42A70388UL))) +#define bM4_PORT_POTRB_POT03 (*((volatile unsigned int*)(0x42A7038CUL))) +#define bM4_PORT_POTRB_POT04 (*((volatile unsigned int*)(0x42A70390UL))) +#define bM4_PORT_POTRB_POT05 (*((volatile unsigned int*)(0x42A70394UL))) +#define bM4_PORT_POTRB_POT06 (*((volatile unsigned int*)(0x42A70398UL))) +#define bM4_PORT_POTRB_POT07 (*((volatile unsigned int*)(0x42A7039CUL))) +#define bM4_PORT_POTRB_POT08 (*((volatile unsigned int*)(0x42A703A0UL))) +#define bM4_PORT_POTRB_POT09 (*((volatile unsigned int*)(0x42A703A4UL))) +#define bM4_PORT_POTRB_POT10 (*((volatile unsigned int*)(0x42A703A8UL))) +#define bM4_PORT_POTRB_POT11 (*((volatile unsigned int*)(0x42A703ACUL))) +#define bM4_PORT_POTRB_POT12 (*((volatile unsigned int*)(0x42A703B0UL))) +#define bM4_PORT_POTRB_POT13 (*((volatile unsigned int*)(0x42A703B4UL))) +#define bM4_PORT_POTRB_POT14 (*((volatile unsigned int*)(0x42A703B8UL))) +#define bM4_PORT_POTRB_POT15 (*((volatile unsigned int*)(0x42A703BCUL))) +#define bM4_PORT_PIDRC_PIN00 (*((volatile unsigned int*)(0x42A70400UL))) +#define bM4_PORT_PIDRC_PIN01 (*((volatile unsigned int*)(0x42A70404UL))) +#define bM4_PORT_PIDRC_PIN02 (*((volatile unsigned int*)(0x42A70408UL))) +#define bM4_PORT_PIDRC_PIN03 (*((volatile unsigned int*)(0x42A7040CUL))) +#define bM4_PORT_PIDRC_PIN04 (*((volatile unsigned int*)(0x42A70410UL))) +#define bM4_PORT_PIDRC_PIN05 (*((volatile unsigned int*)(0x42A70414UL))) +#define bM4_PORT_PIDRC_PIN06 (*((volatile unsigned int*)(0x42A70418UL))) +#define bM4_PORT_PIDRC_PIN07 (*((volatile unsigned int*)(0x42A7041CUL))) +#define bM4_PORT_PIDRC_PIN08 (*((volatile unsigned int*)(0x42A70420UL))) +#define bM4_PORT_PIDRC_PIN09 (*((volatile unsigned int*)(0x42A70424UL))) +#define bM4_PORT_PIDRC_PIN10 (*((volatile unsigned int*)(0x42A70428UL))) +#define bM4_PORT_PIDRC_PIN11 (*((volatile unsigned int*)(0x42A7042CUL))) +#define bM4_PORT_PIDRC_PIN12 (*((volatile unsigned int*)(0x42A70430UL))) +#define bM4_PORT_PIDRC_PIN13 (*((volatile unsigned int*)(0x42A70434UL))) +#define bM4_PORT_PIDRC_PIN14 (*((volatile unsigned int*)(0x42A70438UL))) +#define bM4_PORT_PIDRC_PIN15 (*((volatile unsigned int*)(0x42A7043CUL))) +#define bM4_PORT_PODRC_POUT00 (*((volatile unsigned int*)(0x42A70480UL))) +#define bM4_PORT_PODRC_POUT01 (*((volatile unsigned int*)(0x42A70484UL))) +#define bM4_PORT_PODRC_POUT02 (*((volatile unsigned int*)(0x42A70488UL))) +#define bM4_PORT_PODRC_POUT03 (*((volatile unsigned int*)(0x42A7048CUL))) +#define bM4_PORT_PODRC_POUT04 (*((volatile unsigned int*)(0x42A70490UL))) +#define bM4_PORT_PODRC_POUT05 (*((volatile unsigned int*)(0x42A70494UL))) +#define bM4_PORT_PODRC_POUT06 (*((volatile unsigned int*)(0x42A70498UL))) +#define bM4_PORT_PODRC_POUT07 (*((volatile unsigned int*)(0x42A7049CUL))) +#define bM4_PORT_PODRC_POUT08 (*((volatile unsigned int*)(0x42A704A0UL))) +#define bM4_PORT_PODRC_POUT09 (*((volatile unsigned int*)(0x42A704A4UL))) +#define bM4_PORT_PODRC_POUT10 (*((volatile unsigned int*)(0x42A704A8UL))) +#define bM4_PORT_PODRC_POUT11 (*((volatile unsigned int*)(0x42A704ACUL))) +#define bM4_PORT_PODRC_POUT12 (*((volatile unsigned int*)(0x42A704B0UL))) +#define bM4_PORT_PODRC_POUT13 (*((volatile unsigned int*)(0x42A704B4UL))) +#define bM4_PORT_PODRC_POUT14 (*((volatile unsigned int*)(0x42A704B8UL))) +#define bM4_PORT_PODRC_POUT15 (*((volatile unsigned int*)(0x42A704BCUL))) +#define bM4_PORT_POERC_POUTE00 (*((volatile unsigned int*)(0x42A704C0UL))) +#define bM4_PORT_POERC_POUTE01 (*((volatile unsigned int*)(0x42A704C4UL))) +#define bM4_PORT_POERC_POUTE02 (*((volatile unsigned int*)(0x42A704C8UL))) +#define bM4_PORT_POERC_POUTE03 (*((volatile unsigned int*)(0x42A704CCUL))) +#define bM4_PORT_POERC_POUTE04 (*((volatile unsigned int*)(0x42A704D0UL))) +#define bM4_PORT_POERC_POUTE05 (*((volatile unsigned int*)(0x42A704D4UL))) +#define bM4_PORT_POERC_POUTE06 (*((volatile unsigned int*)(0x42A704D8UL))) +#define bM4_PORT_POERC_POUTE07 (*((volatile unsigned int*)(0x42A704DCUL))) +#define bM4_PORT_POERC_POUTE08 (*((volatile unsigned int*)(0x42A704E0UL))) +#define bM4_PORT_POERC_POUTE09 (*((volatile unsigned int*)(0x42A704E4UL))) +#define bM4_PORT_POERC_POUTE10 (*((volatile unsigned int*)(0x42A704E8UL))) +#define bM4_PORT_POERC_POUTE11 (*((volatile unsigned int*)(0x42A704ECUL))) +#define bM4_PORT_POERC_POUTE12 (*((volatile unsigned int*)(0x42A704F0UL))) +#define bM4_PORT_POERC_POUTE13 (*((volatile unsigned int*)(0x42A704F4UL))) +#define bM4_PORT_POERC_POUTE14 (*((volatile unsigned int*)(0x42A704F8UL))) +#define bM4_PORT_POERC_POUTE15 (*((volatile unsigned int*)(0x42A704FCUL))) +#define bM4_PORT_POSRC_POS00 (*((volatile unsigned int*)(0x42A70500UL))) +#define bM4_PORT_POSRC_POS01 (*((volatile unsigned int*)(0x42A70504UL))) +#define bM4_PORT_POSRC_POS02 (*((volatile unsigned int*)(0x42A70508UL))) +#define bM4_PORT_POSRC_POS03 (*((volatile unsigned int*)(0x42A7050CUL))) +#define bM4_PORT_POSRC_POS04 (*((volatile unsigned int*)(0x42A70510UL))) +#define bM4_PORT_POSRC_POS05 (*((volatile unsigned int*)(0x42A70514UL))) +#define bM4_PORT_POSRC_POS06 (*((volatile unsigned int*)(0x42A70518UL))) +#define bM4_PORT_POSRC_POS07 (*((volatile unsigned int*)(0x42A7051CUL))) +#define bM4_PORT_POSRC_POS08 (*((volatile unsigned int*)(0x42A70520UL))) +#define bM4_PORT_POSRC_POS09 (*((volatile unsigned int*)(0x42A70524UL))) +#define bM4_PORT_POSRC_POS10 (*((volatile unsigned int*)(0x42A70528UL))) +#define bM4_PORT_POSRC_POS11 (*((volatile unsigned int*)(0x42A7052CUL))) +#define bM4_PORT_POSRC_POS12 (*((volatile unsigned int*)(0x42A70530UL))) +#define bM4_PORT_POSRC_POS13 (*((volatile unsigned int*)(0x42A70534UL))) +#define bM4_PORT_POSRC_POS14 (*((volatile unsigned int*)(0x42A70538UL))) +#define bM4_PORT_POSRC_POS15 (*((volatile unsigned int*)(0x42A7053CUL))) +#define bM4_PORT_PORRC_POR00 (*((volatile unsigned int*)(0x42A70540UL))) +#define bM4_PORT_PORRC_POR01 (*((volatile unsigned int*)(0x42A70544UL))) +#define bM4_PORT_PORRC_POR02 (*((volatile unsigned int*)(0x42A70548UL))) +#define bM4_PORT_PORRC_POR03 (*((volatile unsigned int*)(0x42A7054CUL))) +#define bM4_PORT_PORRC_POR04 (*((volatile unsigned int*)(0x42A70550UL))) +#define bM4_PORT_PORRC_POR05 (*((volatile unsigned int*)(0x42A70554UL))) +#define bM4_PORT_PORRC_POR06 (*((volatile unsigned int*)(0x42A70558UL))) +#define bM4_PORT_PORRC_POR07 (*((volatile unsigned int*)(0x42A7055CUL))) +#define bM4_PORT_PORRC_POR08 (*((volatile unsigned int*)(0x42A70560UL))) +#define bM4_PORT_PORRC_POR09 (*((volatile unsigned int*)(0x42A70564UL))) +#define bM4_PORT_PORRC_POR10 (*((volatile unsigned int*)(0x42A70568UL))) +#define bM4_PORT_PORRC_POR11 (*((volatile unsigned int*)(0x42A7056CUL))) +#define bM4_PORT_PORRC_POR12 (*((volatile unsigned int*)(0x42A70570UL))) +#define bM4_PORT_PORRC_POR13 (*((volatile unsigned int*)(0x42A70574UL))) +#define bM4_PORT_PORRC_POR14 (*((volatile unsigned int*)(0x42A70578UL))) +#define bM4_PORT_PORRC_POR15 (*((volatile unsigned int*)(0x42A7057CUL))) +#define bM4_PORT_POTRC_POT00 (*((volatile unsigned int*)(0x42A70580UL))) +#define bM4_PORT_POTRC_POT01 (*((volatile unsigned int*)(0x42A70584UL))) +#define bM4_PORT_POTRC_POT02 (*((volatile unsigned int*)(0x42A70588UL))) +#define bM4_PORT_POTRC_POT03 (*((volatile unsigned int*)(0x42A7058CUL))) +#define bM4_PORT_POTRC_POT04 (*((volatile unsigned int*)(0x42A70590UL))) +#define bM4_PORT_POTRC_POT05 (*((volatile unsigned int*)(0x42A70594UL))) +#define bM4_PORT_POTRC_POT06 (*((volatile unsigned int*)(0x42A70598UL))) +#define bM4_PORT_POTRC_POT07 (*((volatile unsigned int*)(0x42A7059CUL))) +#define bM4_PORT_POTRC_POT08 (*((volatile unsigned int*)(0x42A705A0UL))) +#define bM4_PORT_POTRC_POT09 (*((volatile unsigned int*)(0x42A705A4UL))) +#define bM4_PORT_POTRC_POT10 (*((volatile unsigned int*)(0x42A705A8UL))) +#define bM4_PORT_POTRC_POT11 (*((volatile unsigned int*)(0x42A705ACUL))) +#define bM4_PORT_POTRC_POT12 (*((volatile unsigned int*)(0x42A705B0UL))) +#define bM4_PORT_POTRC_POT13 (*((volatile unsigned int*)(0x42A705B4UL))) +#define bM4_PORT_POTRC_POT14 (*((volatile unsigned int*)(0x42A705B8UL))) +#define bM4_PORT_POTRC_POT15 (*((volatile unsigned int*)(0x42A705BCUL))) +#define bM4_PORT_PIDRD_PIN00 (*((volatile unsigned int*)(0x42A70600UL))) +#define bM4_PORT_PIDRD_PIN01 (*((volatile unsigned int*)(0x42A70604UL))) +#define bM4_PORT_PIDRD_PIN02 (*((volatile unsigned int*)(0x42A70608UL))) +#define bM4_PORT_PIDRD_PIN03 (*((volatile unsigned int*)(0x42A7060CUL))) +#define bM4_PORT_PIDRD_PIN04 (*((volatile unsigned int*)(0x42A70610UL))) +#define bM4_PORT_PIDRD_PIN05 (*((volatile unsigned int*)(0x42A70614UL))) +#define bM4_PORT_PIDRD_PIN06 (*((volatile unsigned int*)(0x42A70618UL))) +#define bM4_PORT_PIDRD_PIN07 (*((volatile unsigned int*)(0x42A7061CUL))) +#define bM4_PORT_PIDRD_PIN08 (*((volatile unsigned int*)(0x42A70620UL))) +#define bM4_PORT_PIDRD_PIN09 (*((volatile unsigned int*)(0x42A70624UL))) +#define bM4_PORT_PIDRD_PIN10 (*((volatile unsigned int*)(0x42A70628UL))) +#define bM4_PORT_PIDRD_PIN11 (*((volatile unsigned int*)(0x42A7062CUL))) +#define bM4_PORT_PIDRD_PIN12 (*((volatile unsigned int*)(0x42A70630UL))) +#define bM4_PORT_PIDRD_PIN13 (*((volatile unsigned int*)(0x42A70634UL))) +#define bM4_PORT_PIDRD_PIN14 (*((volatile unsigned int*)(0x42A70638UL))) +#define bM4_PORT_PIDRD_PIN15 (*((volatile unsigned int*)(0x42A7063CUL))) +#define bM4_PORT_PODRD_POUT00 (*((volatile unsigned int*)(0x42A70680UL))) +#define bM4_PORT_PODRD_POUT01 (*((volatile unsigned int*)(0x42A70684UL))) +#define bM4_PORT_PODRD_POUT02 (*((volatile unsigned int*)(0x42A70688UL))) +#define bM4_PORT_PODRD_POUT03 (*((volatile unsigned int*)(0x42A7068CUL))) +#define bM4_PORT_PODRD_POUT04 (*((volatile unsigned int*)(0x42A70690UL))) +#define bM4_PORT_PODRD_POUT05 (*((volatile unsigned int*)(0x42A70694UL))) +#define bM4_PORT_PODRD_POUT06 (*((volatile unsigned int*)(0x42A70698UL))) +#define bM4_PORT_PODRD_POUT07 (*((volatile unsigned int*)(0x42A7069CUL))) +#define bM4_PORT_PODRD_POUT08 (*((volatile unsigned int*)(0x42A706A0UL))) +#define bM4_PORT_PODRD_POUT09 (*((volatile unsigned int*)(0x42A706A4UL))) +#define bM4_PORT_PODRD_POUT10 (*((volatile unsigned int*)(0x42A706A8UL))) +#define bM4_PORT_PODRD_POUT11 (*((volatile unsigned int*)(0x42A706ACUL))) +#define bM4_PORT_PODRD_POUT12 (*((volatile unsigned int*)(0x42A706B0UL))) +#define bM4_PORT_PODRD_POUT13 (*((volatile unsigned int*)(0x42A706B4UL))) +#define bM4_PORT_PODRD_POUT14 (*((volatile unsigned int*)(0x42A706B8UL))) +#define bM4_PORT_PODRD_POUT15 (*((volatile unsigned int*)(0x42A706BCUL))) +#define bM4_PORT_POERD_POUTE00 (*((volatile unsigned int*)(0x42A706C0UL))) +#define bM4_PORT_POERD_POUTE01 (*((volatile unsigned int*)(0x42A706C4UL))) +#define bM4_PORT_POERD_POUTE02 (*((volatile unsigned int*)(0x42A706C8UL))) +#define bM4_PORT_POERD_POUTE03 (*((volatile unsigned int*)(0x42A706CCUL))) +#define bM4_PORT_POERD_POUTE04 (*((volatile unsigned int*)(0x42A706D0UL))) +#define bM4_PORT_POERD_POUTE05 (*((volatile unsigned int*)(0x42A706D4UL))) +#define bM4_PORT_POERD_POUTE06 (*((volatile unsigned int*)(0x42A706D8UL))) +#define bM4_PORT_POERD_POUTE07 (*((volatile unsigned int*)(0x42A706DCUL))) +#define bM4_PORT_POERD_POUTE08 (*((volatile unsigned int*)(0x42A706E0UL))) +#define bM4_PORT_POERD_POUTE09 (*((volatile unsigned int*)(0x42A706E4UL))) +#define bM4_PORT_POERD_POUTE10 (*((volatile unsigned int*)(0x42A706E8UL))) +#define bM4_PORT_POERD_POUTE11 (*((volatile unsigned int*)(0x42A706ECUL))) +#define bM4_PORT_POERD_POUTE12 (*((volatile unsigned int*)(0x42A706F0UL))) +#define bM4_PORT_POERD_POUTE13 (*((volatile unsigned int*)(0x42A706F4UL))) +#define bM4_PORT_POERD_POUTE14 (*((volatile unsigned int*)(0x42A706F8UL))) +#define bM4_PORT_POERD_POUTE15 (*((volatile unsigned int*)(0x42A706FCUL))) +#define bM4_PORT_POSRD_POS00 (*((volatile unsigned int*)(0x42A70700UL))) +#define bM4_PORT_POSRD_POS01 (*((volatile unsigned int*)(0x42A70704UL))) +#define bM4_PORT_POSRD_POS02 (*((volatile unsigned int*)(0x42A70708UL))) +#define bM4_PORT_POSRD_POS03 (*((volatile unsigned int*)(0x42A7070CUL))) +#define bM4_PORT_POSRD_POS04 (*((volatile unsigned int*)(0x42A70710UL))) +#define bM4_PORT_POSRD_POS05 (*((volatile unsigned int*)(0x42A70714UL))) +#define bM4_PORT_POSRD_POS06 (*((volatile unsigned int*)(0x42A70718UL))) +#define bM4_PORT_POSRD_POS07 (*((volatile unsigned int*)(0x42A7071CUL))) +#define bM4_PORT_POSRD_POS08 (*((volatile unsigned int*)(0x42A70720UL))) +#define bM4_PORT_POSRD_POS09 (*((volatile unsigned int*)(0x42A70724UL))) +#define bM4_PORT_POSRD_POS10 (*((volatile unsigned int*)(0x42A70728UL))) +#define bM4_PORT_POSRD_POS11 (*((volatile unsigned int*)(0x42A7072CUL))) +#define bM4_PORT_POSRD_POS12 (*((volatile unsigned int*)(0x42A70730UL))) +#define bM4_PORT_POSRD_POS13 (*((volatile unsigned int*)(0x42A70734UL))) +#define bM4_PORT_POSRD_POS14 (*((volatile unsigned int*)(0x42A70738UL))) +#define bM4_PORT_POSRD_POS15 (*((volatile unsigned int*)(0x42A7073CUL))) +#define bM4_PORT_PORRD_POR00 (*((volatile unsigned int*)(0x42A70740UL))) +#define bM4_PORT_PORRD_POR01 (*((volatile unsigned int*)(0x42A70744UL))) +#define bM4_PORT_PORRD_POR02 (*((volatile unsigned int*)(0x42A70748UL))) +#define bM4_PORT_PORRD_POR03 (*((volatile unsigned int*)(0x42A7074CUL))) +#define bM4_PORT_PORRD_POR04 (*((volatile unsigned int*)(0x42A70750UL))) +#define bM4_PORT_PORRD_POR05 (*((volatile unsigned int*)(0x42A70754UL))) +#define bM4_PORT_PORRD_POR06 (*((volatile unsigned int*)(0x42A70758UL))) +#define bM4_PORT_PORRD_POR07 (*((volatile unsigned int*)(0x42A7075CUL))) +#define bM4_PORT_PORRD_POR08 (*((volatile unsigned int*)(0x42A70760UL))) +#define bM4_PORT_PORRD_POR09 (*((volatile unsigned int*)(0x42A70764UL))) +#define bM4_PORT_PORRD_POR10 (*((volatile unsigned int*)(0x42A70768UL))) +#define bM4_PORT_PORRD_POR11 (*((volatile unsigned int*)(0x42A7076CUL))) +#define bM4_PORT_PORRD_POR12 (*((volatile unsigned int*)(0x42A70770UL))) +#define bM4_PORT_PORRD_POR13 (*((volatile unsigned int*)(0x42A70774UL))) +#define bM4_PORT_PORRD_POR14 (*((volatile unsigned int*)(0x42A70778UL))) +#define bM4_PORT_PORRD_POR15 (*((volatile unsigned int*)(0x42A7077CUL))) +#define bM4_PORT_POTRD_POT00 (*((volatile unsigned int*)(0x42A70780UL))) +#define bM4_PORT_POTRD_POT01 (*((volatile unsigned int*)(0x42A70784UL))) +#define bM4_PORT_POTRD_POT02 (*((volatile unsigned int*)(0x42A70788UL))) +#define bM4_PORT_POTRD_POT03 (*((volatile unsigned int*)(0x42A7078CUL))) +#define bM4_PORT_POTRD_POT04 (*((volatile unsigned int*)(0x42A70790UL))) +#define bM4_PORT_POTRD_POT05 (*((volatile unsigned int*)(0x42A70794UL))) +#define bM4_PORT_POTRD_POT06 (*((volatile unsigned int*)(0x42A70798UL))) +#define bM4_PORT_POTRD_POT07 (*((volatile unsigned int*)(0x42A7079CUL))) +#define bM4_PORT_POTRD_POT08 (*((volatile unsigned int*)(0x42A707A0UL))) +#define bM4_PORT_POTRD_POT09 (*((volatile unsigned int*)(0x42A707A4UL))) +#define bM4_PORT_POTRD_POT10 (*((volatile unsigned int*)(0x42A707A8UL))) +#define bM4_PORT_POTRD_POT11 (*((volatile unsigned int*)(0x42A707ACUL))) +#define bM4_PORT_POTRD_POT12 (*((volatile unsigned int*)(0x42A707B0UL))) +#define bM4_PORT_POTRD_POT13 (*((volatile unsigned int*)(0x42A707B4UL))) +#define bM4_PORT_POTRD_POT14 (*((volatile unsigned int*)(0x42A707B8UL))) +#define bM4_PORT_POTRD_POT15 (*((volatile unsigned int*)(0x42A707BCUL))) +#define bM4_PORT_PIDRE_PIN00 (*((volatile unsigned int*)(0x42A70800UL))) +#define bM4_PORT_PIDRE_PIN01 (*((volatile unsigned int*)(0x42A70804UL))) +#define bM4_PORT_PIDRE_PIN02 (*((volatile unsigned int*)(0x42A70808UL))) +#define bM4_PORT_PIDRE_PIN03 (*((volatile unsigned int*)(0x42A7080CUL))) +#define bM4_PORT_PIDRE_PIN04 (*((volatile unsigned int*)(0x42A70810UL))) +#define bM4_PORT_PIDRE_PIN05 (*((volatile unsigned int*)(0x42A70814UL))) +#define bM4_PORT_PIDRE_PIN06 (*((volatile unsigned int*)(0x42A70818UL))) +#define bM4_PORT_PIDRE_PIN07 (*((volatile unsigned int*)(0x42A7081CUL))) +#define bM4_PORT_PIDRE_PIN08 (*((volatile unsigned int*)(0x42A70820UL))) +#define bM4_PORT_PIDRE_PIN09 (*((volatile unsigned int*)(0x42A70824UL))) +#define bM4_PORT_PIDRE_PIN10 (*((volatile unsigned int*)(0x42A70828UL))) +#define bM4_PORT_PIDRE_PIN11 (*((volatile unsigned int*)(0x42A7082CUL))) +#define bM4_PORT_PIDRE_PIN12 (*((volatile unsigned int*)(0x42A70830UL))) +#define bM4_PORT_PIDRE_PIN13 (*((volatile unsigned int*)(0x42A70834UL))) +#define bM4_PORT_PIDRE_PIN14 (*((volatile unsigned int*)(0x42A70838UL))) +#define bM4_PORT_PIDRE_PIN15 (*((volatile unsigned int*)(0x42A7083CUL))) +#define bM4_PORT_PODRE_POUT00 (*((volatile unsigned int*)(0x42A70880UL))) +#define bM4_PORT_PODRE_POUT01 (*((volatile unsigned int*)(0x42A70884UL))) +#define bM4_PORT_PODRE_POUT02 (*((volatile unsigned int*)(0x42A70888UL))) +#define bM4_PORT_PODRE_POUT03 (*((volatile unsigned int*)(0x42A7088CUL))) +#define bM4_PORT_PODRE_POUT04 (*((volatile unsigned int*)(0x42A70890UL))) +#define bM4_PORT_PODRE_POUT05 (*((volatile unsigned int*)(0x42A70894UL))) +#define bM4_PORT_PODRE_POUT06 (*((volatile unsigned int*)(0x42A70898UL))) +#define bM4_PORT_PODRE_POUT07 (*((volatile unsigned int*)(0x42A7089CUL))) +#define bM4_PORT_PODRE_POUT08 (*((volatile unsigned int*)(0x42A708A0UL))) +#define bM4_PORT_PODRE_POUT09 (*((volatile unsigned int*)(0x42A708A4UL))) +#define bM4_PORT_PODRE_POUT10 (*((volatile unsigned int*)(0x42A708A8UL))) +#define bM4_PORT_PODRE_POUT11 (*((volatile unsigned int*)(0x42A708ACUL))) +#define bM4_PORT_PODRE_POUT12 (*((volatile unsigned int*)(0x42A708B0UL))) +#define bM4_PORT_PODRE_POUT13 (*((volatile unsigned int*)(0x42A708B4UL))) +#define bM4_PORT_PODRE_POUT14 (*((volatile unsigned int*)(0x42A708B8UL))) +#define bM4_PORT_PODRE_POUT15 (*((volatile unsigned int*)(0x42A708BCUL))) +#define bM4_PORT_POERE_POUTE00 (*((volatile unsigned int*)(0x42A708C0UL))) +#define bM4_PORT_POERE_POUTE01 (*((volatile unsigned int*)(0x42A708C4UL))) +#define bM4_PORT_POERE_POUTE02 (*((volatile unsigned int*)(0x42A708C8UL))) +#define bM4_PORT_POERE_POUTE03 (*((volatile unsigned int*)(0x42A708CCUL))) +#define bM4_PORT_POERE_POUTE04 (*((volatile unsigned int*)(0x42A708D0UL))) +#define bM4_PORT_POERE_POUTE05 (*((volatile unsigned int*)(0x42A708D4UL))) +#define bM4_PORT_POERE_POUTE06 (*((volatile unsigned int*)(0x42A708D8UL))) +#define bM4_PORT_POERE_POUTE07 (*((volatile unsigned int*)(0x42A708DCUL))) +#define bM4_PORT_POERE_POUTE08 (*((volatile unsigned int*)(0x42A708E0UL))) +#define bM4_PORT_POERE_POUTE09 (*((volatile unsigned int*)(0x42A708E4UL))) +#define bM4_PORT_POERE_POUTE10 (*((volatile unsigned int*)(0x42A708E8UL))) +#define bM4_PORT_POERE_POUTE11 (*((volatile unsigned int*)(0x42A708ECUL))) +#define bM4_PORT_POERE_POUTE12 (*((volatile unsigned int*)(0x42A708F0UL))) +#define bM4_PORT_POERE_POUTE13 (*((volatile unsigned int*)(0x42A708F4UL))) +#define bM4_PORT_POERE_POUTE14 (*((volatile unsigned int*)(0x42A708F8UL))) +#define bM4_PORT_POERE_POUTE15 (*((volatile unsigned int*)(0x42A708FCUL))) +#define bM4_PORT_POSRE_POS00 (*((volatile unsigned int*)(0x42A70900UL))) +#define bM4_PORT_POSRE_POS01 (*((volatile unsigned int*)(0x42A70904UL))) +#define bM4_PORT_POSRE_POS02 (*((volatile unsigned int*)(0x42A70908UL))) +#define bM4_PORT_POSRE_POS03 (*((volatile unsigned int*)(0x42A7090CUL))) +#define bM4_PORT_POSRE_POS04 (*((volatile unsigned int*)(0x42A70910UL))) +#define bM4_PORT_POSRE_POS05 (*((volatile unsigned int*)(0x42A70914UL))) +#define bM4_PORT_POSRE_POS06 (*((volatile unsigned int*)(0x42A70918UL))) +#define bM4_PORT_POSRE_POS07 (*((volatile unsigned int*)(0x42A7091CUL))) +#define bM4_PORT_POSRE_POS08 (*((volatile unsigned int*)(0x42A70920UL))) +#define bM4_PORT_POSRE_POS09 (*((volatile unsigned int*)(0x42A70924UL))) +#define bM4_PORT_POSRE_POS10 (*((volatile unsigned int*)(0x42A70928UL))) +#define bM4_PORT_POSRE_POS11 (*((volatile unsigned int*)(0x42A7092CUL))) +#define bM4_PORT_POSRE_POS12 (*((volatile unsigned int*)(0x42A70930UL))) +#define bM4_PORT_POSRE_POS13 (*((volatile unsigned int*)(0x42A70934UL))) +#define bM4_PORT_POSRE_POS14 (*((volatile unsigned int*)(0x42A70938UL))) +#define bM4_PORT_POSRE_POS15 (*((volatile unsigned int*)(0x42A7093CUL))) +#define bM4_PORT_PORRE_POR00 (*((volatile unsigned int*)(0x42A70940UL))) +#define bM4_PORT_PORRE_POR01 (*((volatile unsigned int*)(0x42A70944UL))) +#define bM4_PORT_PORRE_POR02 (*((volatile unsigned int*)(0x42A70948UL))) +#define bM4_PORT_PORRE_POR03 (*((volatile unsigned int*)(0x42A7094CUL))) +#define bM4_PORT_PORRE_POR04 (*((volatile unsigned int*)(0x42A70950UL))) +#define bM4_PORT_PORRE_POR05 (*((volatile unsigned int*)(0x42A70954UL))) +#define bM4_PORT_PORRE_POR06 (*((volatile unsigned int*)(0x42A70958UL))) +#define bM4_PORT_PORRE_POR07 (*((volatile unsigned int*)(0x42A7095CUL))) +#define bM4_PORT_PORRE_POR08 (*((volatile unsigned int*)(0x42A70960UL))) +#define bM4_PORT_PORRE_POR09 (*((volatile unsigned int*)(0x42A70964UL))) +#define bM4_PORT_PORRE_POR10 (*((volatile unsigned int*)(0x42A70968UL))) +#define bM4_PORT_PORRE_POR11 (*((volatile unsigned int*)(0x42A7096CUL))) +#define bM4_PORT_PORRE_POR12 (*((volatile unsigned int*)(0x42A70970UL))) +#define bM4_PORT_PORRE_POR13 (*((volatile unsigned int*)(0x42A70974UL))) +#define bM4_PORT_PORRE_POR14 (*((volatile unsigned int*)(0x42A70978UL))) +#define bM4_PORT_PORRE_POR15 (*((volatile unsigned int*)(0x42A7097CUL))) +#define bM4_PORT_POTRE_POT00 (*((volatile unsigned int*)(0x42A70980UL))) +#define bM4_PORT_POTRE_POT01 (*((volatile unsigned int*)(0x42A70984UL))) +#define bM4_PORT_POTRE_POT02 (*((volatile unsigned int*)(0x42A70988UL))) +#define bM4_PORT_POTRE_POT03 (*((volatile unsigned int*)(0x42A7098CUL))) +#define bM4_PORT_POTRE_POT04 (*((volatile unsigned int*)(0x42A70990UL))) +#define bM4_PORT_POTRE_POT05 (*((volatile unsigned int*)(0x42A70994UL))) +#define bM4_PORT_POTRE_POT06 (*((volatile unsigned int*)(0x42A70998UL))) +#define bM4_PORT_POTRE_POT07 (*((volatile unsigned int*)(0x42A7099CUL))) +#define bM4_PORT_POTRE_POT08 (*((volatile unsigned int*)(0x42A709A0UL))) +#define bM4_PORT_POTRE_POT09 (*((volatile unsigned int*)(0x42A709A4UL))) +#define bM4_PORT_POTRE_POT10 (*((volatile unsigned int*)(0x42A709A8UL))) +#define bM4_PORT_POTRE_POT11 (*((volatile unsigned int*)(0x42A709ACUL))) +#define bM4_PORT_POTRE_POT12 (*((volatile unsigned int*)(0x42A709B0UL))) +#define bM4_PORT_POTRE_POT13 (*((volatile unsigned int*)(0x42A709B4UL))) +#define bM4_PORT_POTRE_POT14 (*((volatile unsigned int*)(0x42A709B8UL))) +#define bM4_PORT_POTRE_POT15 (*((volatile unsigned int*)(0x42A709BCUL))) +#define bM4_PORT_PIDRH_PIN00 (*((volatile unsigned int*)(0x42A70A00UL))) +#define bM4_PORT_PIDRH_PIN01 (*((volatile unsigned int*)(0x42A70A04UL))) +#define bM4_PORT_PIDRH_PIN02 (*((volatile unsigned int*)(0x42A70A08UL))) +#define bM4_PORT_PODRH_POUT00 (*((volatile unsigned int*)(0x42A70A80UL))) +#define bM4_PORT_PODRH_POUT01 (*((volatile unsigned int*)(0x42A70A84UL))) +#define bM4_PORT_PODRH_POUT02 (*((volatile unsigned int*)(0x42A70A88UL))) +#define bM4_PORT_POERH_POUTE00 (*((volatile unsigned int*)(0x42A70AC0UL))) +#define bM4_PORT_POERH_POUTE01 (*((volatile unsigned int*)(0x42A70AC4UL))) +#define bM4_PORT_POERH_POUTE02 (*((volatile unsigned int*)(0x42A70AC8UL))) +#define bM4_PORT_POSRH_POS00 (*((volatile unsigned int*)(0x42A70B00UL))) +#define bM4_PORT_POSRH_POS01 (*((volatile unsigned int*)(0x42A70B04UL))) +#define bM4_PORT_POSRH_POS02 (*((volatile unsigned int*)(0x42A70B08UL))) +#define bM4_PORT_PORRH_POR00 (*((volatile unsigned int*)(0x42A70B40UL))) +#define bM4_PORT_PORRH_POR01 (*((volatile unsigned int*)(0x42A70B44UL))) +#define bM4_PORT_PORRH_POR02 (*((volatile unsigned int*)(0x42A70B48UL))) +#define bM4_PORT_POTRH_POT00 (*((volatile unsigned int*)(0x42A70B80UL))) +#define bM4_PORT_POTRH_POT01 (*((volatile unsigned int*)(0x42A70B84UL))) +#define bM4_PORT_POTRH_POT02 (*((volatile unsigned int*)(0x42A70B88UL))) +#define bM4_PORT_PSPCR_SPFE0 (*((volatile unsigned int*)(0x42A77E80UL))) +#define bM4_PORT_PSPCR_SPFE1 (*((volatile unsigned int*)(0x42A77E84UL))) +#define bM4_PORT_PSPCR_SPFE2 (*((volatile unsigned int*)(0x42A77E88UL))) +#define bM4_PORT_PSPCR_SPFE3 (*((volatile unsigned int*)(0x42A77E8CUL))) +#define bM4_PORT_PSPCR_SPFE4 (*((volatile unsigned int*)(0x42A77E90UL))) +#define bM4_PORT_PCCR_BFSEL0 (*((volatile unsigned int*)(0x42A77F00UL))) +#define bM4_PORT_PCCR_BFSEL1 (*((volatile unsigned int*)(0x42A77F04UL))) +#define bM4_PORT_PCCR_BFSEL2 (*((volatile unsigned int*)(0x42A77F08UL))) +#define bM4_PORT_PCCR_BFSEL3 (*((volatile unsigned int*)(0x42A77F0CUL))) +#define bM4_PORT_PCCR_RDWT0 (*((volatile unsigned int*)(0x42A77F38UL))) +#define bM4_PORT_PCCR_RDWT1 (*((volatile unsigned int*)(0x42A77F3CUL))) +#define bM4_PORT_PINAER_PINAE0 (*((volatile unsigned int*)(0x42A77F40UL))) +#define bM4_PORT_PINAER_PINAE1 (*((volatile unsigned int*)(0x42A77F44UL))) +#define bM4_PORT_PINAER_PINAE2 (*((volatile unsigned int*)(0x42A77F48UL))) +#define bM4_PORT_PINAER_PINAE3 (*((volatile unsigned int*)(0x42A77F4CUL))) +#define bM4_PORT_PINAER_PINAE4 (*((volatile unsigned int*)(0x42A77F50UL))) +#define bM4_PORT_PINAER_PINAE5 (*((volatile unsigned int*)(0x42A77F54UL))) +#define bM4_PORT_PWPR_WE (*((volatile unsigned int*)(0x42A77F80UL))) +#define bM4_PORT_PWPR_WP0 (*((volatile unsigned int*)(0x42A77FA0UL))) +#define bM4_PORT_PWPR_WP1 (*((volatile unsigned int*)(0x42A77FA4UL))) +#define bM4_PORT_PWPR_WP2 (*((volatile unsigned int*)(0x42A77FA8UL))) +#define bM4_PORT_PWPR_WP3 (*((volatile unsigned int*)(0x42A77FACUL))) +#define bM4_PORT_PWPR_WP4 (*((volatile unsigned int*)(0x42A77FB0UL))) +#define bM4_PORT_PWPR_WP5 (*((volatile unsigned int*)(0x42A77FB4UL))) +#define bM4_PORT_PWPR_WP6 (*((volatile unsigned int*)(0x42A77FB8UL))) +#define bM4_PORT_PWPR_WP7 (*((volatile unsigned int*)(0x42A77FBCUL))) +#define bM4_PORT_PCRA0_POUT (*((volatile unsigned int*)(0x42A78000UL))) +#define bM4_PORT_PCRA0_POUTE (*((volatile unsigned int*)(0x42A78004UL))) +#define bM4_PORT_PCRA0_NOD (*((volatile unsigned int*)(0x42A78008UL))) +#define bM4_PORT_PCRA0_DRV0 (*((volatile unsigned int*)(0x42A78010UL))) +#define bM4_PORT_PCRA0_DRV1 (*((volatile unsigned int*)(0x42A78014UL))) +#define bM4_PORT_PCRA0_PUU (*((volatile unsigned int*)(0x42A78018UL))) +#define bM4_PORT_PCRA0_PIN (*((volatile unsigned int*)(0x42A78020UL))) +#define bM4_PORT_PCRA0_INVE (*((volatile unsigned int*)(0x42A78024UL))) +#define bM4_PORT_PCRA0_INTE (*((volatile unsigned int*)(0x42A78030UL))) +#define bM4_PORT_PCRA0_LTE (*((volatile unsigned int*)(0x42A78038UL))) +#define bM4_PORT_PCRA0_DDIS (*((volatile unsigned int*)(0x42A7803CUL))) +#define bM4_PORT_PFSRA0_FSEL0 (*((volatile unsigned int*)(0x42A78040UL))) +#define bM4_PORT_PFSRA0_FSEL1 (*((volatile unsigned int*)(0x42A78044UL))) +#define bM4_PORT_PFSRA0_FSEL2 (*((volatile unsigned int*)(0x42A78048UL))) +#define bM4_PORT_PFSRA0_FSEL3 (*((volatile unsigned int*)(0x42A7804CUL))) +#define bM4_PORT_PFSRA0_FSEL4 (*((volatile unsigned int*)(0x42A78050UL))) +#define bM4_PORT_PFSRA0_FSEL5 (*((volatile unsigned int*)(0x42A78054UL))) +#define bM4_PORT_PFSRA0_BFE (*((volatile unsigned int*)(0x42A78060UL))) +#define bM4_PORT_PCRA1_POUT (*((volatile unsigned int*)(0x42A78080UL))) +#define bM4_PORT_PCRA1_POUTE (*((volatile unsigned int*)(0x42A78084UL))) +#define bM4_PORT_PCRA1_NOD (*((volatile unsigned int*)(0x42A78088UL))) +#define bM4_PORT_PCRA1_DRV0 (*((volatile unsigned int*)(0x42A78090UL))) +#define bM4_PORT_PCRA1_DRV1 (*((volatile unsigned int*)(0x42A78094UL))) +#define bM4_PORT_PCRA1_PUU (*((volatile unsigned int*)(0x42A78098UL))) +#define bM4_PORT_PCRA1_PIN (*((volatile unsigned int*)(0x42A780A0UL))) +#define bM4_PORT_PCRA1_INVE (*((volatile unsigned int*)(0x42A780A4UL))) +#define bM4_PORT_PCRA1_INTE (*((volatile unsigned int*)(0x42A780B0UL))) +#define bM4_PORT_PCRA1_LTE (*((volatile unsigned int*)(0x42A780B8UL))) +#define bM4_PORT_PCRA1_DDIS (*((volatile unsigned int*)(0x42A780BCUL))) +#define bM4_PORT_PFSRA1_FSEL0 (*((volatile unsigned int*)(0x42A780C0UL))) +#define bM4_PORT_PFSRA1_FSEL1 (*((volatile unsigned int*)(0x42A780C4UL))) +#define bM4_PORT_PFSRA1_FSEL2 (*((volatile unsigned int*)(0x42A780C8UL))) +#define bM4_PORT_PFSRA1_FSEL3 (*((volatile unsigned int*)(0x42A780CCUL))) +#define bM4_PORT_PFSRA1_FSEL4 (*((volatile unsigned int*)(0x42A780D0UL))) +#define bM4_PORT_PFSRA1_FSEL5 (*((volatile unsigned int*)(0x42A780D4UL))) +#define bM4_PORT_PFSRA1_BFE (*((volatile unsigned int*)(0x42A780E0UL))) +#define bM4_PORT_PCRA2_POUT (*((volatile unsigned int*)(0x42A78100UL))) +#define bM4_PORT_PCRA2_POUTE (*((volatile unsigned int*)(0x42A78104UL))) +#define bM4_PORT_PCRA2_NOD (*((volatile unsigned int*)(0x42A78108UL))) +#define bM4_PORT_PCRA2_DRV0 (*((volatile unsigned int*)(0x42A78110UL))) +#define bM4_PORT_PCRA2_DRV1 (*((volatile unsigned int*)(0x42A78114UL))) +#define bM4_PORT_PCRA2_PUU (*((volatile unsigned int*)(0x42A78118UL))) +#define bM4_PORT_PCRA2_PIN (*((volatile unsigned int*)(0x42A78120UL))) +#define bM4_PORT_PCRA2_INVE (*((volatile unsigned int*)(0x42A78124UL))) +#define bM4_PORT_PCRA2_INTE (*((volatile unsigned int*)(0x42A78130UL))) +#define bM4_PORT_PCRA2_LTE (*((volatile unsigned int*)(0x42A78138UL))) +#define bM4_PORT_PCRA2_DDIS (*((volatile unsigned int*)(0x42A7813CUL))) +#define bM4_PORT_PFSRA2_FSEL0 (*((volatile unsigned int*)(0x42A78140UL))) +#define bM4_PORT_PFSRA2_FSEL1 (*((volatile unsigned int*)(0x42A78144UL))) +#define bM4_PORT_PFSRA2_FSEL2 (*((volatile unsigned int*)(0x42A78148UL))) +#define bM4_PORT_PFSRA2_FSEL3 (*((volatile unsigned int*)(0x42A7814CUL))) +#define bM4_PORT_PFSRA2_FSEL4 (*((volatile unsigned int*)(0x42A78150UL))) +#define bM4_PORT_PFSRA2_FSEL5 (*((volatile unsigned int*)(0x42A78154UL))) +#define bM4_PORT_PFSRA2_BFE (*((volatile unsigned int*)(0x42A78160UL))) +#define bM4_PORT_PCRA3_POUT (*((volatile unsigned int*)(0x42A78180UL))) +#define bM4_PORT_PCRA3_POUTE (*((volatile unsigned int*)(0x42A78184UL))) +#define bM4_PORT_PCRA3_NOD (*((volatile unsigned int*)(0x42A78188UL))) +#define bM4_PORT_PCRA3_DRV0 (*((volatile unsigned int*)(0x42A78190UL))) +#define bM4_PORT_PCRA3_DRV1 (*((volatile unsigned int*)(0x42A78194UL))) +#define bM4_PORT_PCRA3_PUU (*((volatile unsigned int*)(0x42A78198UL))) +#define bM4_PORT_PCRA3_PIN (*((volatile unsigned int*)(0x42A781A0UL))) +#define bM4_PORT_PCRA3_INVE (*((volatile unsigned int*)(0x42A781A4UL))) +#define bM4_PORT_PCRA3_INTE (*((volatile unsigned int*)(0x42A781B0UL))) +#define bM4_PORT_PCRA3_LTE (*((volatile unsigned int*)(0x42A781B8UL))) +#define bM4_PORT_PCRA3_DDIS (*((volatile unsigned int*)(0x42A781BCUL))) +#define bM4_PORT_PFSRA3_FSEL0 (*((volatile unsigned int*)(0x42A781C0UL))) +#define bM4_PORT_PFSRA3_FSEL1 (*((volatile unsigned int*)(0x42A781C4UL))) +#define bM4_PORT_PFSRA3_FSEL2 (*((volatile unsigned int*)(0x42A781C8UL))) +#define bM4_PORT_PFSRA3_FSEL3 (*((volatile unsigned int*)(0x42A781CCUL))) +#define bM4_PORT_PFSRA3_FSEL4 (*((volatile unsigned int*)(0x42A781D0UL))) +#define bM4_PORT_PFSRA3_FSEL5 (*((volatile unsigned int*)(0x42A781D4UL))) +#define bM4_PORT_PFSRA3_BFE (*((volatile unsigned int*)(0x42A781E0UL))) +#define bM4_PORT_PCRA4_POUT (*((volatile unsigned int*)(0x42A78200UL))) +#define bM4_PORT_PCRA4_POUTE (*((volatile unsigned int*)(0x42A78204UL))) +#define bM4_PORT_PCRA4_NOD (*((volatile unsigned int*)(0x42A78208UL))) +#define bM4_PORT_PCRA4_DRV0 (*((volatile unsigned int*)(0x42A78210UL))) +#define bM4_PORT_PCRA4_DRV1 (*((volatile unsigned int*)(0x42A78214UL))) +#define bM4_PORT_PCRA4_PUU (*((volatile unsigned int*)(0x42A78218UL))) +#define bM4_PORT_PCRA4_PIN (*((volatile unsigned int*)(0x42A78220UL))) +#define bM4_PORT_PCRA4_INVE (*((volatile unsigned int*)(0x42A78224UL))) +#define bM4_PORT_PCRA4_INTE (*((volatile unsigned int*)(0x42A78230UL))) +#define bM4_PORT_PCRA4_LTE (*((volatile unsigned int*)(0x42A78238UL))) +#define bM4_PORT_PCRA4_DDIS (*((volatile unsigned int*)(0x42A7823CUL))) +#define bM4_PORT_PFSRA4_FSEL0 (*((volatile unsigned int*)(0x42A78240UL))) +#define bM4_PORT_PFSRA4_FSEL1 (*((volatile unsigned int*)(0x42A78244UL))) +#define bM4_PORT_PFSRA4_FSEL2 (*((volatile unsigned int*)(0x42A78248UL))) +#define bM4_PORT_PFSRA4_FSEL3 (*((volatile unsigned int*)(0x42A7824CUL))) +#define bM4_PORT_PFSRA4_FSEL4 (*((volatile unsigned int*)(0x42A78250UL))) +#define bM4_PORT_PFSRA4_FSEL5 (*((volatile unsigned int*)(0x42A78254UL))) +#define bM4_PORT_PFSRA4_BFE (*((volatile unsigned int*)(0x42A78260UL))) +#define bM4_PORT_PCRA5_POUT (*((volatile unsigned int*)(0x42A78280UL))) +#define bM4_PORT_PCRA5_POUTE (*((volatile unsigned int*)(0x42A78284UL))) +#define bM4_PORT_PCRA5_NOD (*((volatile unsigned int*)(0x42A78288UL))) +#define bM4_PORT_PCRA5_DRV0 (*((volatile unsigned int*)(0x42A78290UL))) +#define bM4_PORT_PCRA5_DRV1 (*((volatile unsigned int*)(0x42A78294UL))) +#define bM4_PORT_PCRA5_PUU (*((volatile unsigned int*)(0x42A78298UL))) +#define bM4_PORT_PCRA5_PIN (*((volatile unsigned int*)(0x42A782A0UL))) +#define bM4_PORT_PCRA5_INVE (*((volatile unsigned int*)(0x42A782A4UL))) +#define bM4_PORT_PCRA5_INTE (*((volatile unsigned int*)(0x42A782B0UL))) +#define bM4_PORT_PCRA5_LTE (*((volatile unsigned int*)(0x42A782B8UL))) +#define bM4_PORT_PCRA5_DDIS (*((volatile unsigned int*)(0x42A782BCUL))) +#define bM4_PORT_PFSRA5_FSEL0 (*((volatile unsigned int*)(0x42A782C0UL))) +#define bM4_PORT_PFSRA5_FSEL1 (*((volatile unsigned int*)(0x42A782C4UL))) +#define bM4_PORT_PFSRA5_FSEL2 (*((volatile unsigned int*)(0x42A782C8UL))) +#define bM4_PORT_PFSRA5_FSEL3 (*((volatile unsigned int*)(0x42A782CCUL))) +#define bM4_PORT_PFSRA5_FSEL4 (*((volatile unsigned int*)(0x42A782D0UL))) +#define bM4_PORT_PFSRA5_FSEL5 (*((volatile unsigned int*)(0x42A782D4UL))) +#define bM4_PORT_PFSRA5_BFE (*((volatile unsigned int*)(0x42A782E0UL))) +#define bM4_PORT_PCRA6_POUT (*((volatile unsigned int*)(0x42A78300UL))) +#define bM4_PORT_PCRA6_POUTE (*((volatile unsigned int*)(0x42A78304UL))) +#define bM4_PORT_PCRA6_NOD (*((volatile unsigned int*)(0x42A78308UL))) +#define bM4_PORT_PCRA6_DRV0 (*((volatile unsigned int*)(0x42A78310UL))) +#define bM4_PORT_PCRA6_DRV1 (*((volatile unsigned int*)(0x42A78314UL))) +#define bM4_PORT_PCRA6_PUU (*((volatile unsigned int*)(0x42A78318UL))) +#define bM4_PORT_PCRA6_PIN (*((volatile unsigned int*)(0x42A78320UL))) +#define bM4_PORT_PCRA6_INVE (*((volatile unsigned int*)(0x42A78324UL))) +#define bM4_PORT_PCRA6_INTE (*((volatile unsigned int*)(0x42A78330UL))) +#define bM4_PORT_PCRA6_LTE (*((volatile unsigned int*)(0x42A78338UL))) +#define bM4_PORT_PCRA6_DDIS (*((volatile unsigned int*)(0x42A7833CUL))) +#define bM4_PORT_PFSRA6_FSEL0 (*((volatile unsigned int*)(0x42A78340UL))) +#define bM4_PORT_PFSRA6_FSEL1 (*((volatile unsigned int*)(0x42A78344UL))) +#define bM4_PORT_PFSRA6_FSEL2 (*((volatile unsigned int*)(0x42A78348UL))) +#define bM4_PORT_PFSRA6_FSEL3 (*((volatile unsigned int*)(0x42A7834CUL))) +#define bM4_PORT_PFSRA6_FSEL4 (*((volatile unsigned int*)(0x42A78350UL))) +#define bM4_PORT_PFSRA6_FSEL5 (*((volatile unsigned int*)(0x42A78354UL))) +#define bM4_PORT_PFSRA6_BFE (*((volatile unsigned int*)(0x42A78360UL))) +#define bM4_PORT_PCRA7_POUT (*((volatile unsigned int*)(0x42A78380UL))) +#define bM4_PORT_PCRA7_POUTE (*((volatile unsigned int*)(0x42A78384UL))) +#define bM4_PORT_PCRA7_NOD (*((volatile unsigned int*)(0x42A78388UL))) +#define bM4_PORT_PCRA7_DRV0 (*((volatile unsigned int*)(0x42A78390UL))) +#define bM4_PORT_PCRA7_DRV1 (*((volatile unsigned int*)(0x42A78394UL))) +#define bM4_PORT_PCRA7_PUU (*((volatile unsigned int*)(0x42A78398UL))) +#define bM4_PORT_PCRA7_PIN (*((volatile unsigned int*)(0x42A783A0UL))) +#define bM4_PORT_PCRA7_INVE (*((volatile unsigned int*)(0x42A783A4UL))) +#define bM4_PORT_PCRA7_INTE (*((volatile unsigned int*)(0x42A783B0UL))) +#define bM4_PORT_PCRA7_LTE (*((volatile unsigned int*)(0x42A783B8UL))) +#define bM4_PORT_PCRA7_DDIS (*((volatile unsigned int*)(0x42A783BCUL))) +#define bM4_PORT_PFSRA7_FSEL0 (*((volatile unsigned int*)(0x42A783C0UL))) +#define bM4_PORT_PFSRA7_FSEL1 (*((volatile unsigned int*)(0x42A783C4UL))) +#define bM4_PORT_PFSRA7_FSEL2 (*((volatile unsigned int*)(0x42A783C8UL))) +#define bM4_PORT_PFSRA7_FSEL3 (*((volatile unsigned int*)(0x42A783CCUL))) +#define bM4_PORT_PFSRA7_FSEL4 (*((volatile unsigned int*)(0x42A783D0UL))) +#define bM4_PORT_PFSRA7_FSEL5 (*((volatile unsigned int*)(0x42A783D4UL))) +#define bM4_PORT_PFSRA7_BFE (*((volatile unsigned int*)(0x42A783E0UL))) +#define bM4_PORT_PCRA8_POUT (*((volatile unsigned int*)(0x42A78400UL))) +#define bM4_PORT_PCRA8_POUTE (*((volatile unsigned int*)(0x42A78404UL))) +#define bM4_PORT_PCRA8_NOD (*((volatile unsigned int*)(0x42A78408UL))) +#define bM4_PORT_PCRA8_DRV0 (*((volatile unsigned int*)(0x42A78410UL))) +#define bM4_PORT_PCRA8_DRV1 (*((volatile unsigned int*)(0x42A78414UL))) +#define bM4_PORT_PCRA8_PUU (*((volatile unsigned int*)(0x42A78418UL))) +#define bM4_PORT_PCRA8_PIN (*((volatile unsigned int*)(0x42A78420UL))) +#define bM4_PORT_PCRA8_INVE (*((volatile unsigned int*)(0x42A78424UL))) +#define bM4_PORT_PCRA8_INTE (*((volatile unsigned int*)(0x42A78430UL))) +#define bM4_PORT_PCRA8_LTE (*((volatile unsigned int*)(0x42A78438UL))) +#define bM4_PORT_PCRA8_DDIS (*((volatile unsigned int*)(0x42A7843CUL))) +#define bM4_PORT_PFSRA8_FSEL0 (*((volatile unsigned int*)(0x42A78440UL))) +#define bM4_PORT_PFSRA8_FSEL1 (*((volatile unsigned int*)(0x42A78444UL))) +#define bM4_PORT_PFSRA8_FSEL2 (*((volatile unsigned int*)(0x42A78448UL))) +#define bM4_PORT_PFSRA8_FSEL3 (*((volatile unsigned int*)(0x42A7844CUL))) +#define bM4_PORT_PFSRA8_FSEL4 (*((volatile unsigned int*)(0x42A78450UL))) +#define bM4_PORT_PFSRA8_FSEL5 (*((volatile unsigned int*)(0x42A78454UL))) +#define bM4_PORT_PFSRA8_BFE (*((volatile unsigned int*)(0x42A78460UL))) +#define bM4_PORT_PCRA9_POUT (*((volatile unsigned int*)(0x42A78480UL))) +#define bM4_PORT_PCRA9_POUTE (*((volatile unsigned int*)(0x42A78484UL))) +#define bM4_PORT_PCRA9_NOD (*((volatile unsigned int*)(0x42A78488UL))) +#define bM4_PORT_PCRA9_DRV0 (*((volatile unsigned int*)(0x42A78490UL))) +#define bM4_PORT_PCRA9_DRV1 (*((volatile unsigned int*)(0x42A78494UL))) +#define bM4_PORT_PCRA9_PUU (*((volatile unsigned int*)(0x42A78498UL))) +#define bM4_PORT_PCRA9_PIN (*((volatile unsigned int*)(0x42A784A0UL))) +#define bM4_PORT_PCRA9_INVE (*((volatile unsigned int*)(0x42A784A4UL))) +#define bM4_PORT_PCRA9_INTE (*((volatile unsigned int*)(0x42A784B0UL))) +#define bM4_PORT_PCRA9_LTE (*((volatile unsigned int*)(0x42A784B8UL))) +#define bM4_PORT_PCRA9_DDIS (*((volatile unsigned int*)(0x42A784BCUL))) +#define bM4_PORT_PFSRA9_FSEL0 (*((volatile unsigned int*)(0x42A784C0UL))) +#define bM4_PORT_PFSRA9_FSEL1 (*((volatile unsigned int*)(0x42A784C4UL))) +#define bM4_PORT_PFSRA9_FSEL2 (*((volatile unsigned int*)(0x42A784C8UL))) +#define bM4_PORT_PFSRA9_FSEL3 (*((volatile unsigned int*)(0x42A784CCUL))) +#define bM4_PORT_PFSRA9_FSEL4 (*((volatile unsigned int*)(0x42A784D0UL))) +#define bM4_PORT_PFSRA9_FSEL5 (*((volatile unsigned int*)(0x42A784D4UL))) +#define bM4_PORT_PFSRA9_BFE (*((volatile unsigned int*)(0x42A784E0UL))) +#define bM4_PORT_PCRA10_POUT (*((volatile unsigned int*)(0x42A78500UL))) +#define bM4_PORT_PCRA10_POUTE (*((volatile unsigned int*)(0x42A78504UL))) +#define bM4_PORT_PCRA10_NOD (*((volatile unsigned int*)(0x42A78508UL))) +#define bM4_PORT_PCRA10_DRV0 (*((volatile unsigned int*)(0x42A78510UL))) +#define bM4_PORT_PCRA10_DRV1 (*((volatile unsigned int*)(0x42A78514UL))) +#define bM4_PORT_PCRA10_PUU (*((volatile unsigned int*)(0x42A78518UL))) +#define bM4_PORT_PCRA10_PIN (*((volatile unsigned int*)(0x42A78520UL))) +#define bM4_PORT_PCRA10_INVE (*((volatile unsigned int*)(0x42A78524UL))) +#define bM4_PORT_PCRA10_INTE (*((volatile unsigned int*)(0x42A78530UL))) +#define bM4_PORT_PCRA10_LTE (*((volatile unsigned int*)(0x42A78538UL))) +#define bM4_PORT_PCRA10_DDIS (*((volatile unsigned int*)(0x42A7853CUL))) +#define bM4_PORT_PFSRA10_FSEL0 (*((volatile unsigned int*)(0x42A78540UL))) +#define bM4_PORT_PFSRA10_FSEL1 (*((volatile unsigned int*)(0x42A78544UL))) +#define bM4_PORT_PFSRA10_FSEL2 (*((volatile unsigned int*)(0x42A78548UL))) +#define bM4_PORT_PFSRA10_FSEL3 (*((volatile unsigned int*)(0x42A7854CUL))) +#define bM4_PORT_PFSRA10_FSEL4 (*((volatile unsigned int*)(0x42A78550UL))) +#define bM4_PORT_PFSRA10_FSEL5 (*((volatile unsigned int*)(0x42A78554UL))) +#define bM4_PORT_PFSRA10_BFE (*((volatile unsigned int*)(0x42A78560UL))) +#define bM4_PORT_PCRA11_POUT (*((volatile unsigned int*)(0x42A78580UL))) +#define bM4_PORT_PCRA11_POUTE (*((volatile unsigned int*)(0x42A78584UL))) +#define bM4_PORT_PCRA11_NOD (*((volatile unsigned int*)(0x42A78588UL))) +#define bM4_PORT_PCRA11_DRV0 (*((volatile unsigned int*)(0x42A78590UL))) +#define bM4_PORT_PCRA11_DRV1 (*((volatile unsigned int*)(0x42A78594UL))) +#define bM4_PORT_PCRA11_PUU (*((volatile unsigned int*)(0x42A78598UL))) +#define bM4_PORT_PCRA11_PIN (*((volatile unsigned int*)(0x42A785A0UL))) +#define bM4_PORT_PCRA11_INVE (*((volatile unsigned int*)(0x42A785A4UL))) +#define bM4_PORT_PCRA11_INTE (*((volatile unsigned int*)(0x42A785B0UL))) +#define bM4_PORT_PCRA11_LTE (*((volatile unsigned int*)(0x42A785B8UL))) +#define bM4_PORT_PCRA11_DDIS (*((volatile unsigned int*)(0x42A785BCUL))) +#define bM4_PORT_PFSRA11_FSEL0 (*((volatile unsigned int*)(0x42A785C0UL))) +#define bM4_PORT_PFSRA11_FSEL1 (*((volatile unsigned int*)(0x42A785C4UL))) +#define bM4_PORT_PFSRA11_FSEL2 (*((volatile unsigned int*)(0x42A785C8UL))) +#define bM4_PORT_PFSRA11_FSEL3 (*((volatile unsigned int*)(0x42A785CCUL))) +#define bM4_PORT_PFSRA11_FSEL4 (*((volatile unsigned int*)(0x42A785D0UL))) +#define bM4_PORT_PFSRA11_FSEL5 (*((volatile unsigned int*)(0x42A785D4UL))) +#define bM4_PORT_PFSRA11_BFE (*((volatile unsigned int*)(0x42A785E0UL))) +#define bM4_PORT_PCRA12_POUT (*((volatile unsigned int*)(0x42A78600UL))) +#define bM4_PORT_PCRA12_POUTE (*((volatile unsigned int*)(0x42A78604UL))) +#define bM4_PORT_PCRA12_NOD (*((volatile unsigned int*)(0x42A78608UL))) +#define bM4_PORT_PCRA12_DRV0 (*((volatile unsigned int*)(0x42A78610UL))) +#define bM4_PORT_PCRA12_DRV1 (*((volatile unsigned int*)(0x42A78614UL))) +#define bM4_PORT_PCRA12_PUU (*((volatile unsigned int*)(0x42A78618UL))) +#define bM4_PORT_PCRA12_PIN (*((volatile unsigned int*)(0x42A78620UL))) +#define bM4_PORT_PCRA12_INVE (*((volatile unsigned int*)(0x42A78624UL))) +#define bM4_PORT_PCRA12_INTE (*((volatile unsigned int*)(0x42A78630UL))) +#define bM4_PORT_PCRA12_LTE (*((volatile unsigned int*)(0x42A78638UL))) +#define bM4_PORT_PCRA12_DDIS (*((volatile unsigned int*)(0x42A7863CUL))) +#define bM4_PORT_PFSRA12_FSEL0 (*((volatile unsigned int*)(0x42A78640UL))) +#define bM4_PORT_PFSRA12_FSEL1 (*((volatile unsigned int*)(0x42A78644UL))) +#define bM4_PORT_PFSRA12_FSEL2 (*((volatile unsigned int*)(0x42A78648UL))) +#define bM4_PORT_PFSRA12_FSEL3 (*((volatile unsigned int*)(0x42A7864CUL))) +#define bM4_PORT_PFSRA12_FSEL4 (*((volatile unsigned int*)(0x42A78650UL))) +#define bM4_PORT_PFSRA12_FSEL5 (*((volatile unsigned int*)(0x42A78654UL))) +#define bM4_PORT_PFSRA12_BFE (*((volatile unsigned int*)(0x42A78660UL))) +#define bM4_PORT_PCRA13_POUT (*((volatile unsigned int*)(0x42A78680UL))) +#define bM4_PORT_PCRA13_POUTE (*((volatile unsigned int*)(0x42A78684UL))) +#define bM4_PORT_PCRA13_NOD (*((volatile unsigned int*)(0x42A78688UL))) +#define bM4_PORT_PCRA13_DRV0 (*((volatile unsigned int*)(0x42A78690UL))) +#define bM4_PORT_PCRA13_DRV1 (*((volatile unsigned int*)(0x42A78694UL))) +#define bM4_PORT_PCRA13_PUU (*((volatile unsigned int*)(0x42A78698UL))) +#define bM4_PORT_PCRA13_PIN (*((volatile unsigned int*)(0x42A786A0UL))) +#define bM4_PORT_PCRA13_INVE (*((volatile unsigned int*)(0x42A786A4UL))) +#define bM4_PORT_PCRA13_INTE (*((volatile unsigned int*)(0x42A786B0UL))) +#define bM4_PORT_PCRA13_LTE (*((volatile unsigned int*)(0x42A786B8UL))) +#define bM4_PORT_PCRA13_DDIS (*((volatile unsigned int*)(0x42A786BCUL))) +#define bM4_PORT_PFSRA13_FSEL0 (*((volatile unsigned int*)(0x42A786C0UL))) +#define bM4_PORT_PFSRA13_FSEL1 (*((volatile unsigned int*)(0x42A786C4UL))) +#define bM4_PORT_PFSRA13_FSEL2 (*((volatile unsigned int*)(0x42A786C8UL))) +#define bM4_PORT_PFSRA13_FSEL3 (*((volatile unsigned int*)(0x42A786CCUL))) +#define bM4_PORT_PFSRA13_FSEL4 (*((volatile unsigned int*)(0x42A786D0UL))) +#define bM4_PORT_PFSRA13_FSEL5 (*((volatile unsigned int*)(0x42A786D4UL))) +#define bM4_PORT_PFSRA13_BFE (*((volatile unsigned int*)(0x42A786E0UL))) +#define bM4_PORT_PCRA14_POUT (*((volatile unsigned int*)(0x42A78700UL))) +#define bM4_PORT_PCRA14_POUTE (*((volatile unsigned int*)(0x42A78704UL))) +#define bM4_PORT_PCRA14_NOD (*((volatile unsigned int*)(0x42A78708UL))) +#define bM4_PORT_PCRA14_DRV0 (*((volatile unsigned int*)(0x42A78710UL))) +#define bM4_PORT_PCRA14_DRV1 (*((volatile unsigned int*)(0x42A78714UL))) +#define bM4_PORT_PCRA14_PUU (*((volatile unsigned int*)(0x42A78718UL))) +#define bM4_PORT_PCRA14_PIN (*((volatile unsigned int*)(0x42A78720UL))) +#define bM4_PORT_PCRA14_INVE (*((volatile unsigned int*)(0x42A78724UL))) +#define bM4_PORT_PCRA14_INTE (*((volatile unsigned int*)(0x42A78730UL))) +#define bM4_PORT_PCRA14_LTE (*((volatile unsigned int*)(0x42A78738UL))) +#define bM4_PORT_PCRA14_DDIS (*((volatile unsigned int*)(0x42A7873CUL))) +#define bM4_PORT_PFSRA14_FSEL0 (*((volatile unsigned int*)(0x42A78740UL))) +#define bM4_PORT_PFSRA14_FSEL1 (*((volatile unsigned int*)(0x42A78744UL))) +#define bM4_PORT_PFSRA14_FSEL2 (*((volatile unsigned int*)(0x42A78748UL))) +#define bM4_PORT_PFSRA14_FSEL3 (*((volatile unsigned int*)(0x42A7874CUL))) +#define bM4_PORT_PFSRA14_FSEL4 (*((volatile unsigned int*)(0x42A78750UL))) +#define bM4_PORT_PFSRA14_FSEL5 (*((volatile unsigned int*)(0x42A78754UL))) +#define bM4_PORT_PFSRA14_BFE (*((volatile unsigned int*)(0x42A78760UL))) +#define bM4_PORT_PCRA15_POUT (*((volatile unsigned int*)(0x42A78780UL))) +#define bM4_PORT_PCRA15_POUTE (*((volatile unsigned int*)(0x42A78784UL))) +#define bM4_PORT_PCRA15_NOD (*((volatile unsigned int*)(0x42A78788UL))) +#define bM4_PORT_PCRA15_DRV0 (*((volatile unsigned int*)(0x42A78790UL))) +#define bM4_PORT_PCRA15_DRV1 (*((volatile unsigned int*)(0x42A78794UL))) +#define bM4_PORT_PCRA15_PUU (*((volatile unsigned int*)(0x42A78798UL))) +#define bM4_PORT_PCRA15_PIN (*((volatile unsigned int*)(0x42A787A0UL))) +#define bM4_PORT_PCRA15_INVE (*((volatile unsigned int*)(0x42A787A4UL))) +#define bM4_PORT_PCRA15_INTE (*((volatile unsigned int*)(0x42A787B0UL))) +#define bM4_PORT_PCRA15_LTE (*((volatile unsigned int*)(0x42A787B8UL))) +#define bM4_PORT_PCRA15_DDIS (*((volatile unsigned int*)(0x42A787BCUL))) +#define bM4_PORT_PFSRA15_FSEL0 (*((volatile unsigned int*)(0x42A787C0UL))) +#define bM4_PORT_PFSRA15_FSEL1 (*((volatile unsigned int*)(0x42A787C4UL))) +#define bM4_PORT_PFSRA15_FSEL2 (*((volatile unsigned int*)(0x42A787C8UL))) +#define bM4_PORT_PFSRA15_FSEL3 (*((volatile unsigned int*)(0x42A787CCUL))) +#define bM4_PORT_PFSRA15_FSEL4 (*((volatile unsigned int*)(0x42A787D0UL))) +#define bM4_PORT_PFSRA15_FSEL5 (*((volatile unsigned int*)(0x42A787D4UL))) +#define bM4_PORT_PFSRA15_BFE (*((volatile unsigned int*)(0x42A787E0UL))) +#define bM4_PORT_PCRB0_POUT (*((volatile unsigned int*)(0x42A78800UL))) +#define bM4_PORT_PCRB0_POUTE (*((volatile unsigned int*)(0x42A78804UL))) +#define bM4_PORT_PCRB0_NOD (*((volatile unsigned int*)(0x42A78808UL))) +#define bM4_PORT_PCRB0_DRV0 (*((volatile unsigned int*)(0x42A78810UL))) +#define bM4_PORT_PCRB0_DRV1 (*((volatile unsigned int*)(0x42A78814UL))) +#define bM4_PORT_PCRB0_PUU (*((volatile unsigned int*)(0x42A78818UL))) +#define bM4_PORT_PCRB0_PIN (*((volatile unsigned int*)(0x42A78820UL))) +#define bM4_PORT_PCRB0_INVE (*((volatile unsigned int*)(0x42A78824UL))) +#define bM4_PORT_PCRB0_INTE (*((volatile unsigned int*)(0x42A78830UL))) +#define bM4_PORT_PCRB0_LTE (*((volatile unsigned int*)(0x42A78838UL))) +#define bM4_PORT_PCRB0_DDIS (*((volatile unsigned int*)(0x42A7883CUL))) +#define bM4_PORT_PFSRB0_FSEL0 (*((volatile unsigned int*)(0x42A78840UL))) +#define bM4_PORT_PFSRB0_FSEL1 (*((volatile unsigned int*)(0x42A78844UL))) +#define bM4_PORT_PFSRB0_FSEL2 (*((volatile unsigned int*)(0x42A78848UL))) +#define bM4_PORT_PFSRB0_FSEL3 (*((volatile unsigned int*)(0x42A7884CUL))) +#define bM4_PORT_PFSRB0_FSEL4 (*((volatile unsigned int*)(0x42A78850UL))) +#define bM4_PORT_PFSRB0_FSEL5 (*((volatile unsigned int*)(0x42A78854UL))) +#define bM4_PORT_PFSRB0_BFE (*((volatile unsigned int*)(0x42A78860UL))) +#define bM4_PORT_PCRB1_POUT (*((volatile unsigned int*)(0x42A78880UL))) +#define bM4_PORT_PCRB1_POUTE (*((volatile unsigned int*)(0x42A78884UL))) +#define bM4_PORT_PCRB1_NOD (*((volatile unsigned int*)(0x42A78888UL))) +#define bM4_PORT_PCRB1_DRV0 (*((volatile unsigned int*)(0x42A78890UL))) +#define bM4_PORT_PCRB1_DRV1 (*((volatile unsigned int*)(0x42A78894UL))) +#define bM4_PORT_PCRB1_PUU (*((volatile unsigned int*)(0x42A78898UL))) +#define bM4_PORT_PCRB1_PIN (*((volatile unsigned int*)(0x42A788A0UL))) +#define bM4_PORT_PCRB1_INVE (*((volatile unsigned int*)(0x42A788A4UL))) +#define bM4_PORT_PCRB1_INTE (*((volatile unsigned int*)(0x42A788B0UL))) +#define bM4_PORT_PCRB1_LTE (*((volatile unsigned int*)(0x42A788B8UL))) +#define bM4_PORT_PCRB1_DDIS (*((volatile unsigned int*)(0x42A788BCUL))) +#define bM4_PORT_PFSRB1_FSEL0 (*((volatile unsigned int*)(0x42A788C0UL))) +#define bM4_PORT_PFSRB1_FSEL1 (*((volatile unsigned int*)(0x42A788C4UL))) +#define bM4_PORT_PFSRB1_FSEL2 (*((volatile unsigned int*)(0x42A788C8UL))) +#define bM4_PORT_PFSRB1_FSEL3 (*((volatile unsigned int*)(0x42A788CCUL))) +#define bM4_PORT_PFSRB1_FSEL4 (*((volatile unsigned int*)(0x42A788D0UL))) +#define bM4_PORT_PFSRB1_FSEL5 (*((volatile unsigned int*)(0x42A788D4UL))) +#define bM4_PORT_PFSRB1_BFE (*((volatile unsigned int*)(0x42A788E0UL))) +#define bM4_PORT_PCRB2_POUT (*((volatile unsigned int*)(0x42A78900UL))) +#define bM4_PORT_PCRB2_POUTE (*((volatile unsigned int*)(0x42A78904UL))) +#define bM4_PORT_PCRB2_NOD (*((volatile unsigned int*)(0x42A78908UL))) +#define bM4_PORT_PCRB2_DRV0 (*((volatile unsigned int*)(0x42A78910UL))) +#define bM4_PORT_PCRB2_DRV1 (*((volatile unsigned int*)(0x42A78914UL))) +#define bM4_PORT_PCRB2_PUU (*((volatile unsigned int*)(0x42A78918UL))) +#define bM4_PORT_PCRB2_PIN (*((volatile unsigned int*)(0x42A78920UL))) +#define bM4_PORT_PCRB2_INVE (*((volatile unsigned int*)(0x42A78924UL))) +#define bM4_PORT_PCRB2_INTE (*((volatile unsigned int*)(0x42A78930UL))) +#define bM4_PORT_PCRB2_LTE (*((volatile unsigned int*)(0x42A78938UL))) +#define bM4_PORT_PCRB2_DDIS (*((volatile unsigned int*)(0x42A7893CUL))) +#define bM4_PORT_PFSRB2_FSEL0 (*((volatile unsigned int*)(0x42A78940UL))) +#define bM4_PORT_PFSRB2_FSEL1 (*((volatile unsigned int*)(0x42A78944UL))) +#define bM4_PORT_PFSRB2_FSEL2 (*((volatile unsigned int*)(0x42A78948UL))) +#define bM4_PORT_PFSRB2_FSEL3 (*((volatile unsigned int*)(0x42A7894CUL))) +#define bM4_PORT_PFSRB2_FSEL4 (*((volatile unsigned int*)(0x42A78950UL))) +#define bM4_PORT_PFSRB2_FSEL5 (*((volatile unsigned int*)(0x42A78954UL))) +#define bM4_PORT_PFSRB2_BFE (*((volatile unsigned int*)(0x42A78960UL))) +#define bM4_PORT_PCRB3_POUT (*((volatile unsigned int*)(0x42A78980UL))) +#define bM4_PORT_PCRB3_POUTE (*((volatile unsigned int*)(0x42A78984UL))) +#define bM4_PORT_PCRB3_NOD (*((volatile unsigned int*)(0x42A78988UL))) +#define bM4_PORT_PCRB3_DRV0 (*((volatile unsigned int*)(0x42A78990UL))) +#define bM4_PORT_PCRB3_DRV1 (*((volatile unsigned int*)(0x42A78994UL))) +#define bM4_PORT_PCRB3_PUU (*((volatile unsigned int*)(0x42A78998UL))) +#define bM4_PORT_PCRB3_PIN (*((volatile unsigned int*)(0x42A789A0UL))) +#define bM4_PORT_PCRB3_INVE (*((volatile unsigned int*)(0x42A789A4UL))) +#define bM4_PORT_PCRB3_INTE (*((volatile unsigned int*)(0x42A789B0UL))) +#define bM4_PORT_PCRB3_LTE (*((volatile unsigned int*)(0x42A789B8UL))) +#define bM4_PORT_PCRB3_DDIS (*((volatile unsigned int*)(0x42A789BCUL))) +#define bM4_PORT_PFSRB3_FSEL0 (*((volatile unsigned int*)(0x42A789C0UL))) +#define bM4_PORT_PFSRB3_FSEL1 (*((volatile unsigned int*)(0x42A789C4UL))) +#define bM4_PORT_PFSRB3_FSEL2 (*((volatile unsigned int*)(0x42A789C8UL))) +#define bM4_PORT_PFSRB3_FSEL3 (*((volatile unsigned int*)(0x42A789CCUL))) +#define bM4_PORT_PFSRB3_FSEL4 (*((volatile unsigned int*)(0x42A789D0UL))) +#define bM4_PORT_PFSRB3_FSEL5 (*((volatile unsigned int*)(0x42A789D4UL))) +#define bM4_PORT_PFSRB3_BFE (*((volatile unsigned int*)(0x42A789E0UL))) +#define bM4_PORT_PCRB4_POUT (*((volatile unsigned int*)(0x42A78A00UL))) +#define bM4_PORT_PCRB4_POUTE (*((volatile unsigned int*)(0x42A78A04UL))) +#define bM4_PORT_PCRB4_NOD (*((volatile unsigned int*)(0x42A78A08UL))) +#define bM4_PORT_PCRB4_DRV0 (*((volatile unsigned int*)(0x42A78A10UL))) +#define bM4_PORT_PCRB4_DRV1 (*((volatile unsigned int*)(0x42A78A14UL))) +#define bM4_PORT_PCRB4_PUU (*((volatile unsigned int*)(0x42A78A18UL))) +#define bM4_PORT_PCRB4_PIN (*((volatile unsigned int*)(0x42A78A20UL))) +#define bM4_PORT_PCRB4_INVE (*((volatile unsigned int*)(0x42A78A24UL))) +#define bM4_PORT_PCRB4_INTE (*((volatile unsigned int*)(0x42A78A30UL))) +#define bM4_PORT_PCRB4_LTE (*((volatile unsigned int*)(0x42A78A38UL))) +#define bM4_PORT_PCRB4_DDIS (*((volatile unsigned int*)(0x42A78A3CUL))) +#define bM4_PORT_PFSRB4_FSEL0 (*((volatile unsigned int*)(0x42A78A40UL))) +#define bM4_PORT_PFSRB4_FSEL1 (*((volatile unsigned int*)(0x42A78A44UL))) +#define bM4_PORT_PFSRB4_FSEL2 (*((volatile unsigned int*)(0x42A78A48UL))) +#define bM4_PORT_PFSRB4_FSEL3 (*((volatile unsigned int*)(0x42A78A4CUL))) +#define bM4_PORT_PFSRB4_FSEL4 (*((volatile unsigned int*)(0x42A78A50UL))) +#define bM4_PORT_PFSRB4_FSEL5 (*((volatile unsigned int*)(0x42A78A54UL))) +#define bM4_PORT_PFSRB4_BFE (*((volatile unsigned int*)(0x42A78A60UL))) +#define bM4_PORT_PCRB5_POUT (*((volatile unsigned int*)(0x42A78A80UL))) +#define bM4_PORT_PCRB5_POUTE (*((volatile unsigned int*)(0x42A78A84UL))) +#define bM4_PORT_PCRB5_NOD (*((volatile unsigned int*)(0x42A78A88UL))) +#define bM4_PORT_PCRB5_DRV0 (*((volatile unsigned int*)(0x42A78A90UL))) +#define bM4_PORT_PCRB5_DRV1 (*((volatile unsigned int*)(0x42A78A94UL))) +#define bM4_PORT_PCRB5_PUU (*((volatile unsigned int*)(0x42A78A98UL))) +#define bM4_PORT_PCRB5_PIN (*((volatile unsigned int*)(0x42A78AA0UL))) +#define bM4_PORT_PCRB5_INVE (*((volatile unsigned int*)(0x42A78AA4UL))) +#define bM4_PORT_PCRB5_INTE (*((volatile unsigned int*)(0x42A78AB0UL))) +#define bM4_PORT_PCRB5_LTE (*((volatile unsigned int*)(0x42A78AB8UL))) +#define bM4_PORT_PCRB5_DDIS (*((volatile unsigned int*)(0x42A78ABCUL))) +#define bM4_PORT_PFSRB5_FSEL0 (*((volatile unsigned int*)(0x42A78AC0UL))) +#define bM4_PORT_PFSRB5_FSEL1 (*((volatile unsigned int*)(0x42A78AC4UL))) +#define bM4_PORT_PFSRB5_FSEL2 (*((volatile unsigned int*)(0x42A78AC8UL))) +#define bM4_PORT_PFSRB5_FSEL3 (*((volatile unsigned int*)(0x42A78ACCUL))) +#define bM4_PORT_PFSRB5_FSEL4 (*((volatile unsigned int*)(0x42A78AD0UL))) +#define bM4_PORT_PFSRB5_FSEL5 (*((volatile unsigned int*)(0x42A78AD4UL))) +#define bM4_PORT_PFSRB5_BFE (*((volatile unsigned int*)(0x42A78AE0UL))) +#define bM4_PORT_PCRB6_POUT (*((volatile unsigned int*)(0x42A78B00UL))) +#define bM4_PORT_PCRB6_POUTE (*((volatile unsigned int*)(0x42A78B04UL))) +#define bM4_PORT_PCRB6_NOD (*((volatile unsigned int*)(0x42A78B08UL))) +#define bM4_PORT_PCRB6_DRV0 (*((volatile unsigned int*)(0x42A78B10UL))) +#define bM4_PORT_PCRB6_DRV1 (*((volatile unsigned int*)(0x42A78B14UL))) +#define bM4_PORT_PCRB6_PUU (*((volatile unsigned int*)(0x42A78B18UL))) +#define bM4_PORT_PCRB6_PIN (*((volatile unsigned int*)(0x42A78B20UL))) +#define bM4_PORT_PCRB6_INVE (*((volatile unsigned int*)(0x42A78B24UL))) +#define bM4_PORT_PCRB6_INTE (*((volatile unsigned int*)(0x42A78B30UL))) +#define bM4_PORT_PCRB6_LTE (*((volatile unsigned int*)(0x42A78B38UL))) +#define bM4_PORT_PCRB6_DDIS (*((volatile unsigned int*)(0x42A78B3CUL))) +#define bM4_PORT_PFSRB6_FSEL0 (*((volatile unsigned int*)(0x42A78B40UL))) +#define bM4_PORT_PFSRB6_FSEL1 (*((volatile unsigned int*)(0x42A78B44UL))) +#define bM4_PORT_PFSRB6_FSEL2 (*((volatile unsigned int*)(0x42A78B48UL))) +#define bM4_PORT_PFSRB6_FSEL3 (*((volatile unsigned int*)(0x42A78B4CUL))) +#define bM4_PORT_PFSRB6_FSEL4 (*((volatile unsigned int*)(0x42A78B50UL))) +#define bM4_PORT_PFSRB6_FSEL5 (*((volatile unsigned int*)(0x42A78B54UL))) +#define bM4_PORT_PFSRB6_BFE (*((volatile unsigned int*)(0x42A78B60UL))) +#define bM4_PORT_PCRB7_POUT (*((volatile unsigned int*)(0x42A78B80UL))) +#define bM4_PORT_PCRB7_POUTE (*((volatile unsigned int*)(0x42A78B84UL))) +#define bM4_PORT_PCRB7_NOD (*((volatile unsigned int*)(0x42A78B88UL))) +#define bM4_PORT_PCRB7_DRV0 (*((volatile unsigned int*)(0x42A78B90UL))) +#define bM4_PORT_PCRB7_DRV1 (*((volatile unsigned int*)(0x42A78B94UL))) +#define bM4_PORT_PCRB7_PUU (*((volatile unsigned int*)(0x42A78B98UL))) +#define bM4_PORT_PCRB7_PIN (*((volatile unsigned int*)(0x42A78BA0UL))) +#define bM4_PORT_PCRB7_INVE (*((volatile unsigned int*)(0x42A78BA4UL))) +#define bM4_PORT_PCRB7_INTE (*((volatile unsigned int*)(0x42A78BB0UL))) +#define bM4_PORT_PCRB7_LTE (*((volatile unsigned int*)(0x42A78BB8UL))) +#define bM4_PORT_PCRB7_DDIS (*((volatile unsigned int*)(0x42A78BBCUL))) +#define bM4_PORT_PFSRB7_FSEL0 (*((volatile unsigned int*)(0x42A78BC0UL))) +#define bM4_PORT_PFSRB7_FSEL1 (*((volatile unsigned int*)(0x42A78BC4UL))) +#define bM4_PORT_PFSRB7_FSEL2 (*((volatile unsigned int*)(0x42A78BC8UL))) +#define bM4_PORT_PFSRB7_FSEL3 (*((volatile unsigned int*)(0x42A78BCCUL))) +#define bM4_PORT_PFSRB7_FSEL4 (*((volatile unsigned int*)(0x42A78BD0UL))) +#define bM4_PORT_PFSRB7_FSEL5 (*((volatile unsigned int*)(0x42A78BD4UL))) +#define bM4_PORT_PFSRB7_BFE (*((volatile unsigned int*)(0x42A78BE0UL))) +#define bM4_PORT_PCRB8_POUT (*((volatile unsigned int*)(0x42A78C00UL))) +#define bM4_PORT_PCRB8_POUTE (*((volatile unsigned int*)(0x42A78C04UL))) +#define bM4_PORT_PCRB8_NOD (*((volatile unsigned int*)(0x42A78C08UL))) +#define bM4_PORT_PCRB8_DRV0 (*((volatile unsigned int*)(0x42A78C10UL))) +#define bM4_PORT_PCRB8_DRV1 (*((volatile unsigned int*)(0x42A78C14UL))) +#define bM4_PORT_PCRB8_PUU (*((volatile unsigned int*)(0x42A78C18UL))) +#define bM4_PORT_PCRB8_PIN (*((volatile unsigned int*)(0x42A78C20UL))) +#define bM4_PORT_PCRB8_INVE (*((volatile unsigned int*)(0x42A78C24UL))) +#define bM4_PORT_PCRB8_INTE (*((volatile unsigned int*)(0x42A78C30UL))) +#define bM4_PORT_PCRB8_LTE (*((volatile unsigned int*)(0x42A78C38UL))) +#define bM4_PORT_PCRB8_DDIS (*((volatile unsigned int*)(0x42A78C3CUL))) +#define bM4_PORT_PFSRB8_FSEL0 (*((volatile unsigned int*)(0x42A78C40UL))) +#define bM4_PORT_PFSRB8_FSEL1 (*((volatile unsigned int*)(0x42A78C44UL))) +#define bM4_PORT_PFSRB8_FSEL2 (*((volatile unsigned int*)(0x42A78C48UL))) +#define bM4_PORT_PFSRB8_FSEL3 (*((volatile unsigned int*)(0x42A78C4CUL))) +#define bM4_PORT_PFSRB8_FSEL4 (*((volatile unsigned int*)(0x42A78C50UL))) +#define bM4_PORT_PFSRB8_FSEL5 (*((volatile unsigned int*)(0x42A78C54UL))) +#define bM4_PORT_PFSRB8_BFE (*((volatile unsigned int*)(0x42A78C60UL))) +#define bM4_PORT_PCRB9_POUT (*((volatile unsigned int*)(0x42A78C80UL))) +#define bM4_PORT_PCRB9_POUTE (*((volatile unsigned int*)(0x42A78C84UL))) +#define bM4_PORT_PCRB9_NOD (*((volatile unsigned int*)(0x42A78C88UL))) +#define bM4_PORT_PCRB9_DRV0 (*((volatile unsigned int*)(0x42A78C90UL))) +#define bM4_PORT_PCRB9_DRV1 (*((volatile unsigned int*)(0x42A78C94UL))) +#define bM4_PORT_PCRB9_PUU (*((volatile unsigned int*)(0x42A78C98UL))) +#define bM4_PORT_PCRB9_PIN (*((volatile unsigned int*)(0x42A78CA0UL))) +#define bM4_PORT_PCRB9_INVE (*((volatile unsigned int*)(0x42A78CA4UL))) +#define bM4_PORT_PCRB9_INTE (*((volatile unsigned int*)(0x42A78CB0UL))) +#define bM4_PORT_PCRB9_LTE (*((volatile unsigned int*)(0x42A78CB8UL))) +#define bM4_PORT_PCRB9_DDIS (*((volatile unsigned int*)(0x42A78CBCUL))) +#define bM4_PORT_PFSRB9_FSEL0 (*((volatile unsigned int*)(0x42A78CC0UL))) +#define bM4_PORT_PFSRB9_FSEL1 (*((volatile unsigned int*)(0x42A78CC4UL))) +#define bM4_PORT_PFSRB9_FSEL2 (*((volatile unsigned int*)(0x42A78CC8UL))) +#define bM4_PORT_PFSRB9_FSEL3 (*((volatile unsigned int*)(0x42A78CCCUL))) +#define bM4_PORT_PFSRB9_FSEL4 (*((volatile unsigned int*)(0x42A78CD0UL))) +#define bM4_PORT_PFSRB9_FSEL5 (*((volatile unsigned int*)(0x42A78CD4UL))) +#define bM4_PORT_PFSRB9_BFE (*((volatile unsigned int*)(0x42A78CE0UL))) +#define bM4_PORT_PCRB10_POUT (*((volatile unsigned int*)(0x42A78D00UL))) +#define bM4_PORT_PCRB10_POUTE (*((volatile unsigned int*)(0x42A78D04UL))) +#define bM4_PORT_PCRB10_NOD (*((volatile unsigned int*)(0x42A78D08UL))) +#define bM4_PORT_PCRB10_DRV0 (*((volatile unsigned int*)(0x42A78D10UL))) +#define bM4_PORT_PCRB10_DRV1 (*((volatile unsigned int*)(0x42A78D14UL))) +#define bM4_PORT_PCRB10_PUU (*((volatile unsigned int*)(0x42A78D18UL))) +#define bM4_PORT_PCRB10_PIN (*((volatile unsigned int*)(0x42A78D20UL))) +#define bM4_PORT_PCRB10_INVE (*((volatile unsigned int*)(0x42A78D24UL))) +#define bM4_PORT_PCRB10_INTE (*((volatile unsigned int*)(0x42A78D30UL))) +#define bM4_PORT_PCRB10_LTE (*((volatile unsigned int*)(0x42A78D38UL))) +#define bM4_PORT_PCRB10_DDIS (*((volatile unsigned int*)(0x42A78D3CUL))) +#define bM4_PORT_PFSRB10_FSEL0 (*((volatile unsigned int*)(0x42A78D40UL))) +#define bM4_PORT_PFSRB10_FSEL1 (*((volatile unsigned int*)(0x42A78D44UL))) +#define bM4_PORT_PFSRB10_FSEL2 (*((volatile unsigned int*)(0x42A78D48UL))) +#define bM4_PORT_PFSRB10_FSEL3 (*((volatile unsigned int*)(0x42A78D4CUL))) +#define bM4_PORT_PFSRB10_FSEL4 (*((volatile unsigned int*)(0x42A78D50UL))) +#define bM4_PORT_PFSRB10_FSEL5 (*((volatile unsigned int*)(0x42A78D54UL))) +#define bM4_PORT_PFSRB10_BFE (*((volatile unsigned int*)(0x42A78D60UL))) +#define bM4_PORT_PCRB11_POUT (*((volatile unsigned int*)(0x42A78D80UL))) +#define bM4_PORT_PCRB11_POUTE (*((volatile unsigned int*)(0x42A78D84UL))) +#define bM4_PORT_PCRB11_NOD (*((volatile unsigned int*)(0x42A78D88UL))) +#define bM4_PORT_PCRB11_DRV0 (*((volatile unsigned int*)(0x42A78D90UL))) +#define bM4_PORT_PCRB11_DRV1 (*((volatile unsigned int*)(0x42A78D94UL))) +#define bM4_PORT_PCRB11_PUU (*((volatile unsigned int*)(0x42A78D98UL))) +#define bM4_PORT_PCRB11_PIN (*((volatile unsigned int*)(0x42A78DA0UL))) +#define bM4_PORT_PCRB11_INVE (*((volatile unsigned int*)(0x42A78DA4UL))) +#define bM4_PORT_PCRB11_INTE (*((volatile unsigned int*)(0x42A78DB0UL))) +#define bM4_PORT_PCRB11_LTE (*((volatile unsigned int*)(0x42A78DB8UL))) +#define bM4_PORT_PCRB11_DDIS (*((volatile unsigned int*)(0x42A78DBCUL))) +#define bM4_PORT_PFSRB11_FSEL0 (*((volatile unsigned int*)(0x42A78DC0UL))) +#define bM4_PORT_PFSRB11_FSEL1 (*((volatile unsigned int*)(0x42A78DC4UL))) +#define bM4_PORT_PFSRB11_FSEL2 (*((volatile unsigned int*)(0x42A78DC8UL))) +#define bM4_PORT_PFSRB11_FSEL3 (*((volatile unsigned int*)(0x42A78DCCUL))) +#define bM4_PORT_PFSRB11_FSEL4 (*((volatile unsigned int*)(0x42A78DD0UL))) +#define bM4_PORT_PFSRB11_FSEL5 (*((volatile unsigned int*)(0x42A78DD4UL))) +#define bM4_PORT_PFSRB11_BFE (*((volatile unsigned int*)(0x42A78DE0UL))) +#define bM4_PORT_PCRB12_POUT (*((volatile unsigned int*)(0x42A78E00UL))) +#define bM4_PORT_PCRB12_POUTE (*((volatile unsigned int*)(0x42A78E04UL))) +#define bM4_PORT_PCRB12_NOD (*((volatile unsigned int*)(0x42A78E08UL))) +#define bM4_PORT_PCRB12_DRV0 (*((volatile unsigned int*)(0x42A78E10UL))) +#define bM4_PORT_PCRB12_DRV1 (*((volatile unsigned int*)(0x42A78E14UL))) +#define bM4_PORT_PCRB12_PUU (*((volatile unsigned int*)(0x42A78E18UL))) +#define bM4_PORT_PCRB12_PIN (*((volatile unsigned int*)(0x42A78E20UL))) +#define bM4_PORT_PCRB12_INVE (*((volatile unsigned int*)(0x42A78E24UL))) +#define bM4_PORT_PCRB12_INTE (*((volatile unsigned int*)(0x42A78E30UL))) +#define bM4_PORT_PCRB12_LTE (*((volatile unsigned int*)(0x42A78E38UL))) +#define bM4_PORT_PCRB12_DDIS (*((volatile unsigned int*)(0x42A78E3CUL))) +#define bM4_PORT_PFSRB12_FSEL0 (*((volatile unsigned int*)(0x42A78E40UL))) +#define bM4_PORT_PFSRB12_FSEL1 (*((volatile unsigned int*)(0x42A78E44UL))) +#define bM4_PORT_PFSRB12_FSEL2 (*((volatile unsigned int*)(0x42A78E48UL))) +#define bM4_PORT_PFSRB12_FSEL3 (*((volatile unsigned int*)(0x42A78E4CUL))) +#define bM4_PORT_PFSRB12_FSEL4 (*((volatile unsigned int*)(0x42A78E50UL))) +#define bM4_PORT_PFSRB12_FSEL5 (*((volatile unsigned int*)(0x42A78E54UL))) +#define bM4_PORT_PFSRB12_BFE (*((volatile unsigned int*)(0x42A78E60UL))) +#define bM4_PORT_PCRB13_POUT (*((volatile unsigned int*)(0x42A78E80UL))) +#define bM4_PORT_PCRB13_POUTE (*((volatile unsigned int*)(0x42A78E84UL))) +#define bM4_PORT_PCRB13_NOD (*((volatile unsigned int*)(0x42A78E88UL))) +#define bM4_PORT_PCRB13_DRV0 (*((volatile unsigned int*)(0x42A78E90UL))) +#define bM4_PORT_PCRB13_DRV1 (*((volatile unsigned int*)(0x42A78E94UL))) +#define bM4_PORT_PCRB13_PUU (*((volatile unsigned int*)(0x42A78E98UL))) +#define bM4_PORT_PCRB13_PIN (*((volatile unsigned int*)(0x42A78EA0UL))) +#define bM4_PORT_PCRB13_INVE (*((volatile unsigned int*)(0x42A78EA4UL))) +#define bM4_PORT_PCRB13_INTE (*((volatile unsigned int*)(0x42A78EB0UL))) +#define bM4_PORT_PCRB13_LTE (*((volatile unsigned int*)(0x42A78EB8UL))) +#define bM4_PORT_PCRB13_DDIS (*((volatile unsigned int*)(0x42A78EBCUL))) +#define bM4_PORT_PFSRB13_FSEL0 (*((volatile unsigned int*)(0x42A78EC0UL))) +#define bM4_PORT_PFSRB13_FSEL1 (*((volatile unsigned int*)(0x42A78EC4UL))) +#define bM4_PORT_PFSRB13_FSEL2 (*((volatile unsigned int*)(0x42A78EC8UL))) +#define bM4_PORT_PFSRB13_FSEL3 (*((volatile unsigned int*)(0x42A78ECCUL))) +#define bM4_PORT_PFSRB13_FSEL4 (*((volatile unsigned int*)(0x42A78ED0UL))) +#define bM4_PORT_PFSRB13_FSEL5 (*((volatile unsigned int*)(0x42A78ED4UL))) +#define bM4_PORT_PFSRB13_BFE (*((volatile unsigned int*)(0x42A78EE0UL))) +#define bM4_PORT_PCRB14_POUT (*((volatile unsigned int*)(0x42A78F00UL))) +#define bM4_PORT_PCRB14_POUTE (*((volatile unsigned int*)(0x42A78F04UL))) +#define bM4_PORT_PCRB14_NOD (*((volatile unsigned int*)(0x42A78F08UL))) +#define bM4_PORT_PCRB14_DRV0 (*((volatile unsigned int*)(0x42A78F10UL))) +#define bM4_PORT_PCRB14_DRV1 (*((volatile unsigned int*)(0x42A78F14UL))) +#define bM4_PORT_PCRB14_PUU (*((volatile unsigned int*)(0x42A78F18UL))) +#define bM4_PORT_PCRB14_PIN (*((volatile unsigned int*)(0x42A78F20UL))) +#define bM4_PORT_PCRB14_INVE (*((volatile unsigned int*)(0x42A78F24UL))) +#define bM4_PORT_PCRB14_INTE (*((volatile unsigned int*)(0x42A78F30UL))) +#define bM4_PORT_PCRB14_LTE (*((volatile unsigned int*)(0x42A78F38UL))) +#define bM4_PORT_PCRB14_DDIS (*((volatile unsigned int*)(0x42A78F3CUL))) +#define bM4_PORT_PFSRB14_FSEL0 (*((volatile unsigned int*)(0x42A78F40UL))) +#define bM4_PORT_PFSRB14_FSEL1 (*((volatile unsigned int*)(0x42A78F44UL))) +#define bM4_PORT_PFSRB14_FSEL2 (*((volatile unsigned int*)(0x42A78F48UL))) +#define bM4_PORT_PFSRB14_FSEL3 (*((volatile unsigned int*)(0x42A78F4CUL))) +#define bM4_PORT_PFSRB14_FSEL4 (*((volatile unsigned int*)(0x42A78F50UL))) +#define bM4_PORT_PFSRB14_FSEL5 (*((volatile unsigned int*)(0x42A78F54UL))) +#define bM4_PORT_PFSRB14_BFE (*((volatile unsigned int*)(0x42A78F60UL))) +#define bM4_PORT_PCRB15_POUT (*((volatile unsigned int*)(0x42A78F80UL))) +#define bM4_PORT_PCRB15_POUTE (*((volatile unsigned int*)(0x42A78F84UL))) +#define bM4_PORT_PCRB15_NOD (*((volatile unsigned int*)(0x42A78F88UL))) +#define bM4_PORT_PCRB15_DRV0 (*((volatile unsigned int*)(0x42A78F90UL))) +#define bM4_PORT_PCRB15_DRV1 (*((volatile unsigned int*)(0x42A78F94UL))) +#define bM4_PORT_PCRB15_PUU (*((volatile unsigned int*)(0x42A78F98UL))) +#define bM4_PORT_PCRB15_PIN (*((volatile unsigned int*)(0x42A78FA0UL))) +#define bM4_PORT_PCRB15_INVE (*((volatile unsigned int*)(0x42A78FA4UL))) +#define bM4_PORT_PCRB15_INTE (*((volatile unsigned int*)(0x42A78FB0UL))) +#define bM4_PORT_PCRB15_LTE (*((volatile unsigned int*)(0x42A78FB8UL))) +#define bM4_PORT_PCRB15_DDIS (*((volatile unsigned int*)(0x42A78FBCUL))) +#define bM4_PORT_PFSRB15_FSEL0 (*((volatile unsigned int*)(0x42A78FC0UL))) +#define bM4_PORT_PFSRB15_FSEL1 (*((volatile unsigned int*)(0x42A78FC4UL))) +#define bM4_PORT_PFSRB15_FSEL2 (*((volatile unsigned int*)(0x42A78FC8UL))) +#define bM4_PORT_PFSRB15_FSEL3 (*((volatile unsigned int*)(0x42A78FCCUL))) +#define bM4_PORT_PFSRB15_FSEL4 (*((volatile unsigned int*)(0x42A78FD0UL))) +#define bM4_PORT_PFSRB15_FSEL5 (*((volatile unsigned int*)(0x42A78FD4UL))) +#define bM4_PORT_PFSRB15_BFE (*((volatile unsigned int*)(0x42A78FE0UL))) +#define bM4_PORT_PCRC0_POUT (*((volatile unsigned int*)(0x42A79000UL))) +#define bM4_PORT_PCRC0_POUTE (*((volatile unsigned int*)(0x42A79004UL))) +#define bM4_PORT_PCRC0_NOD (*((volatile unsigned int*)(0x42A79008UL))) +#define bM4_PORT_PCRC0_DRV0 (*((volatile unsigned int*)(0x42A79010UL))) +#define bM4_PORT_PCRC0_DRV1 (*((volatile unsigned int*)(0x42A79014UL))) +#define bM4_PORT_PCRC0_PUU (*((volatile unsigned int*)(0x42A79018UL))) +#define bM4_PORT_PCRC0_PIN (*((volatile unsigned int*)(0x42A79020UL))) +#define bM4_PORT_PCRC0_INVE (*((volatile unsigned int*)(0x42A79024UL))) +#define bM4_PORT_PCRC0_INTE (*((volatile unsigned int*)(0x42A79030UL))) +#define bM4_PORT_PCRC0_LTE (*((volatile unsigned int*)(0x42A79038UL))) +#define bM4_PORT_PCRC0_DDIS (*((volatile unsigned int*)(0x42A7903CUL))) +#define bM4_PORT_PFSRC0_FSEL0 (*((volatile unsigned int*)(0x42A79040UL))) +#define bM4_PORT_PFSRC0_FSEL1 (*((volatile unsigned int*)(0x42A79044UL))) +#define bM4_PORT_PFSRC0_FSEL2 (*((volatile unsigned int*)(0x42A79048UL))) +#define bM4_PORT_PFSRC0_FSEL3 (*((volatile unsigned int*)(0x42A7904CUL))) +#define bM4_PORT_PFSRC0_FSEL4 (*((volatile unsigned int*)(0x42A79050UL))) +#define bM4_PORT_PFSRC0_FSEL5 (*((volatile unsigned int*)(0x42A79054UL))) +#define bM4_PORT_PFSRC0_BFE (*((volatile unsigned int*)(0x42A79060UL))) +#define bM4_PORT_PCRC1_POUT (*((volatile unsigned int*)(0x42A79080UL))) +#define bM4_PORT_PCRC1_POUTE (*((volatile unsigned int*)(0x42A79084UL))) +#define bM4_PORT_PCRC1_NOD (*((volatile unsigned int*)(0x42A79088UL))) +#define bM4_PORT_PCRC1_DRV0 (*((volatile unsigned int*)(0x42A79090UL))) +#define bM4_PORT_PCRC1_DRV1 (*((volatile unsigned int*)(0x42A79094UL))) +#define bM4_PORT_PCRC1_PUU (*((volatile unsigned int*)(0x42A79098UL))) +#define bM4_PORT_PCRC1_PIN (*((volatile unsigned int*)(0x42A790A0UL))) +#define bM4_PORT_PCRC1_INVE (*((volatile unsigned int*)(0x42A790A4UL))) +#define bM4_PORT_PCRC1_INTE (*((volatile unsigned int*)(0x42A790B0UL))) +#define bM4_PORT_PCRC1_LTE (*((volatile unsigned int*)(0x42A790B8UL))) +#define bM4_PORT_PCRC1_DDIS (*((volatile unsigned int*)(0x42A790BCUL))) +#define bM4_PORT_PFSRC1_FSEL0 (*((volatile unsigned int*)(0x42A790C0UL))) +#define bM4_PORT_PFSRC1_FSEL1 (*((volatile unsigned int*)(0x42A790C4UL))) +#define bM4_PORT_PFSRC1_FSEL2 (*((volatile unsigned int*)(0x42A790C8UL))) +#define bM4_PORT_PFSRC1_FSEL3 (*((volatile unsigned int*)(0x42A790CCUL))) +#define bM4_PORT_PFSRC1_FSEL4 (*((volatile unsigned int*)(0x42A790D0UL))) +#define bM4_PORT_PFSRC1_FSEL5 (*((volatile unsigned int*)(0x42A790D4UL))) +#define bM4_PORT_PFSRC1_BFE (*((volatile unsigned int*)(0x42A790E0UL))) +#define bM4_PORT_PCRC2_POUT (*((volatile unsigned int*)(0x42A79100UL))) +#define bM4_PORT_PCRC2_POUTE (*((volatile unsigned int*)(0x42A79104UL))) +#define bM4_PORT_PCRC2_NOD (*((volatile unsigned int*)(0x42A79108UL))) +#define bM4_PORT_PCRC2_DRV0 (*((volatile unsigned int*)(0x42A79110UL))) +#define bM4_PORT_PCRC2_DRV1 (*((volatile unsigned int*)(0x42A79114UL))) +#define bM4_PORT_PCRC2_PUU (*((volatile unsigned int*)(0x42A79118UL))) +#define bM4_PORT_PCRC2_PIN (*((volatile unsigned int*)(0x42A79120UL))) +#define bM4_PORT_PCRC2_INVE (*((volatile unsigned int*)(0x42A79124UL))) +#define bM4_PORT_PCRC2_INTE (*((volatile unsigned int*)(0x42A79130UL))) +#define bM4_PORT_PCRC2_LTE (*((volatile unsigned int*)(0x42A79138UL))) +#define bM4_PORT_PCRC2_DDIS (*((volatile unsigned int*)(0x42A7913CUL))) +#define bM4_PORT_PFSRC2_FSEL0 (*((volatile unsigned int*)(0x42A79140UL))) +#define bM4_PORT_PFSRC2_FSEL1 (*((volatile unsigned int*)(0x42A79144UL))) +#define bM4_PORT_PFSRC2_FSEL2 (*((volatile unsigned int*)(0x42A79148UL))) +#define bM4_PORT_PFSRC2_FSEL3 (*((volatile unsigned int*)(0x42A7914CUL))) +#define bM4_PORT_PFSRC2_FSEL4 (*((volatile unsigned int*)(0x42A79150UL))) +#define bM4_PORT_PFSRC2_FSEL5 (*((volatile unsigned int*)(0x42A79154UL))) +#define bM4_PORT_PFSRC2_BFE (*((volatile unsigned int*)(0x42A79160UL))) +#define bM4_PORT_PCRC3_POUT (*((volatile unsigned int*)(0x42A79180UL))) +#define bM4_PORT_PCRC3_POUTE (*((volatile unsigned int*)(0x42A79184UL))) +#define bM4_PORT_PCRC3_NOD (*((volatile unsigned int*)(0x42A79188UL))) +#define bM4_PORT_PCRC3_DRV0 (*((volatile unsigned int*)(0x42A79190UL))) +#define bM4_PORT_PCRC3_DRV1 (*((volatile unsigned int*)(0x42A79194UL))) +#define bM4_PORT_PCRC3_PUU (*((volatile unsigned int*)(0x42A79198UL))) +#define bM4_PORT_PCRC3_PIN (*((volatile unsigned int*)(0x42A791A0UL))) +#define bM4_PORT_PCRC3_INVE (*((volatile unsigned int*)(0x42A791A4UL))) +#define bM4_PORT_PCRC3_INTE (*((volatile unsigned int*)(0x42A791B0UL))) +#define bM4_PORT_PCRC3_LTE (*((volatile unsigned int*)(0x42A791B8UL))) +#define bM4_PORT_PCRC3_DDIS (*((volatile unsigned int*)(0x42A791BCUL))) +#define bM4_PORT_PFSRC3_FSEL0 (*((volatile unsigned int*)(0x42A791C0UL))) +#define bM4_PORT_PFSRC3_FSEL1 (*((volatile unsigned int*)(0x42A791C4UL))) +#define bM4_PORT_PFSRC3_FSEL2 (*((volatile unsigned int*)(0x42A791C8UL))) +#define bM4_PORT_PFSRC3_FSEL3 (*((volatile unsigned int*)(0x42A791CCUL))) +#define bM4_PORT_PFSRC3_FSEL4 (*((volatile unsigned int*)(0x42A791D0UL))) +#define bM4_PORT_PFSRC3_FSEL5 (*((volatile unsigned int*)(0x42A791D4UL))) +#define bM4_PORT_PFSRC3_BFE (*((volatile unsigned int*)(0x42A791E0UL))) +#define bM4_PORT_PCRC4_POUT (*((volatile unsigned int*)(0x42A79200UL))) +#define bM4_PORT_PCRC4_POUTE (*((volatile unsigned int*)(0x42A79204UL))) +#define bM4_PORT_PCRC4_NOD (*((volatile unsigned int*)(0x42A79208UL))) +#define bM4_PORT_PCRC4_DRV0 (*((volatile unsigned int*)(0x42A79210UL))) +#define bM4_PORT_PCRC4_DRV1 (*((volatile unsigned int*)(0x42A79214UL))) +#define bM4_PORT_PCRC4_PUU (*((volatile unsigned int*)(0x42A79218UL))) +#define bM4_PORT_PCRC4_PIN (*((volatile unsigned int*)(0x42A79220UL))) +#define bM4_PORT_PCRC4_INVE (*((volatile unsigned int*)(0x42A79224UL))) +#define bM4_PORT_PCRC4_INTE (*((volatile unsigned int*)(0x42A79230UL))) +#define bM4_PORT_PCRC4_LTE (*((volatile unsigned int*)(0x42A79238UL))) +#define bM4_PORT_PCRC4_DDIS (*((volatile unsigned int*)(0x42A7923CUL))) +#define bM4_PORT_PFSRC4_FSEL0 (*((volatile unsigned int*)(0x42A79240UL))) +#define bM4_PORT_PFSRC4_FSEL1 (*((volatile unsigned int*)(0x42A79244UL))) +#define bM4_PORT_PFSRC4_FSEL2 (*((volatile unsigned int*)(0x42A79248UL))) +#define bM4_PORT_PFSRC4_FSEL3 (*((volatile unsigned int*)(0x42A7924CUL))) +#define bM4_PORT_PFSRC4_FSEL4 (*((volatile unsigned int*)(0x42A79250UL))) +#define bM4_PORT_PFSRC4_FSEL5 (*((volatile unsigned int*)(0x42A79254UL))) +#define bM4_PORT_PFSRC4_BFE (*((volatile unsigned int*)(0x42A79260UL))) +#define bM4_PORT_PCRC5_POUT (*((volatile unsigned int*)(0x42A79280UL))) +#define bM4_PORT_PCRC5_POUTE (*((volatile unsigned int*)(0x42A79284UL))) +#define bM4_PORT_PCRC5_NOD (*((volatile unsigned int*)(0x42A79288UL))) +#define bM4_PORT_PCRC5_DRV0 (*((volatile unsigned int*)(0x42A79290UL))) +#define bM4_PORT_PCRC5_DRV1 (*((volatile unsigned int*)(0x42A79294UL))) +#define bM4_PORT_PCRC5_PUU (*((volatile unsigned int*)(0x42A79298UL))) +#define bM4_PORT_PCRC5_PIN (*((volatile unsigned int*)(0x42A792A0UL))) +#define bM4_PORT_PCRC5_INVE (*((volatile unsigned int*)(0x42A792A4UL))) +#define bM4_PORT_PCRC5_INTE (*((volatile unsigned int*)(0x42A792B0UL))) +#define bM4_PORT_PCRC5_LTE (*((volatile unsigned int*)(0x42A792B8UL))) +#define bM4_PORT_PCRC5_DDIS (*((volatile unsigned int*)(0x42A792BCUL))) +#define bM4_PORT_PFSRC5_FSEL0 (*((volatile unsigned int*)(0x42A792C0UL))) +#define bM4_PORT_PFSRC5_FSEL1 (*((volatile unsigned int*)(0x42A792C4UL))) +#define bM4_PORT_PFSRC5_FSEL2 (*((volatile unsigned int*)(0x42A792C8UL))) +#define bM4_PORT_PFSRC5_FSEL3 (*((volatile unsigned int*)(0x42A792CCUL))) +#define bM4_PORT_PFSRC5_FSEL4 (*((volatile unsigned int*)(0x42A792D0UL))) +#define bM4_PORT_PFSRC5_FSEL5 (*((volatile unsigned int*)(0x42A792D4UL))) +#define bM4_PORT_PFSRC5_BFE (*((volatile unsigned int*)(0x42A792E0UL))) +#define bM4_PORT_PCRC6_POUT (*((volatile unsigned int*)(0x42A79300UL))) +#define bM4_PORT_PCRC6_POUTE (*((volatile unsigned int*)(0x42A79304UL))) +#define bM4_PORT_PCRC6_NOD (*((volatile unsigned int*)(0x42A79308UL))) +#define bM4_PORT_PCRC6_DRV0 (*((volatile unsigned int*)(0x42A79310UL))) +#define bM4_PORT_PCRC6_DRV1 (*((volatile unsigned int*)(0x42A79314UL))) +#define bM4_PORT_PCRC6_PUU (*((volatile unsigned int*)(0x42A79318UL))) +#define bM4_PORT_PCRC6_PIN (*((volatile unsigned int*)(0x42A79320UL))) +#define bM4_PORT_PCRC6_INVE (*((volatile unsigned int*)(0x42A79324UL))) +#define bM4_PORT_PCRC6_INTE (*((volatile unsigned int*)(0x42A79330UL))) +#define bM4_PORT_PCRC6_LTE (*((volatile unsigned int*)(0x42A79338UL))) +#define bM4_PORT_PCRC6_DDIS (*((volatile unsigned int*)(0x42A7933CUL))) +#define bM4_PORT_PFSRC6_FSEL0 (*((volatile unsigned int*)(0x42A79340UL))) +#define bM4_PORT_PFSRC6_FSEL1 (*((volatile unsigned int*)(0x42A79344UL))) +#define bM4_PORT_PFSRC6_FSEL2 (*((volatile unsigned int*)(0x42A79348UL))) +#define bM4_PORT_PFSRC6_FSEL3 (*((volatile unsigned int*)(0x42A7934CUL))) +#define bM4_PORT_PFSRC6_FSEL4 (*((volatile unsigned int*)(0x42A79350UL))) +#define bM4_PORT_PFSRC6_FSEL5 (*((volatile unsigned int*)(0x42A79354UL))) +#define bM4_PORT_PFSRC6_BFE (*((volatile unsigned int*)(0x42A79360UL))) +#define bM4_PORT_PCRC7_POUT (*((volatile unsigned int*)(0x42A79380UL))) +#define bM4_PORT_PCRC7_POUTE (*((volatile unsigned int*)(0x42A79384UL))) +#define bM4_PORT_PCRC7_NOD (*((volatile unsigned int*)(0x42A79388UL))) +#define bM4_PORT_PCRC7_DRV0 (*((volatile unsigned int*)(0x42A79390UL))) +#define bM4_PORT_PCRC7_DRV1 (*((volatile unsigned int*)(0x42A79394UL))) +#define bM4_PORT_PCRC7_PUU (*((volatile unsigned int*)(0x42A79398UL))) +#define bM4_PORT_PCRC7_PIN (*((volatile unsigned int*)(0x42A793A0UL))) +#define bM4_PORT_PCRC7_INVE (*((volatile unsigned int*)(0x42A793A4UL))) +#define bM4_PORT_PCRC7_INTE (*((volatile unsigned int*)(0x42A793B0UL))) +#define bM4_PORT_PCRC7_LTE (*((volatile unsigned int*)(0x42A793B8UL))) +#define bM4_PORT_PCRC7_DDIS (*((volatile unsigned int*)(0x42A793BCUL))) +#define bM4_PORT_PFSRC7_FSEL0 (*((volatile unsigned int*)(0x42A793C0UL))) +#define bM4_PORT_PFSRC7_FSEL1 (*((volatile unsigned int*)(0x42A793C4UL))) +#define bM4_PORT_PFSRC7_FSEL2 (*((volatile unsigned int*)(0x42A793C8UL))) +#define bM4_PORT_PFSRC7_FSEL3 (*((volatile unsigned int*)(0x42A793CCUL))) +#define bM4_PORT_PFSRC7_FSEL4 (*((volatile unsigned int*)(0x42A793D0UL))) +#define bM4_PORT_PFSRC7_FSEL5 (*((volatile unsigned int*)(0x42A793D4UL))) +#define bM4_PORT_PFSRC7_BFE (*((volatile unsigned int*)(0x42A793E0UL))) +#define bM4_PORT_PCRC8_POUT (*((volatile unsigned int*)(0x42A79400UL))) +#define bM4_PORT_PCRC8_POUTE (*((volatile unsigned int*)(0x42A79404UL))) +#define bM4_PORT_PCRC8_NOD (*((volatile unsigned int*)(0x42A79408UL))) +#define bM4_PORT_PCRC8_DRV0 (*((volatile unsigned int*)(0x42A79410UL))) +#define bM4_PORT_PCRC8_DRV1 (*((volatile unsigned int*)(0x42A79414UL))) +#define bM4_PORT_PCRC8_PUU (*((volatile unsigned int*)(0x42A79418UL))) +#define bM4_PORT_PCRC8_PIN (*((volatile unsigned int*)(0x42A79420UL))) +#define bM4_PORT_PCRC8_INVE (*((volatile unsigned int*)(0x42A79424UL))) +#define bM4_PORT_PCRC8_INTE (*((volatile unsigned int*)(0x42A79430UL))) +#define bM4_PORT_PCRC8_LTE (*((volatile unsigned int*)(0x42A79438UL))) +#define bM4_PORT_PCRC8_DDIS (*((volatile unsigned int*)(0x42A7943CUL))) +#define bM4_PORT_PFSRC8_FSEL0 (*((volatile unsigned int*)(0x42A79440UL))) +#define bM4_PORT_PFSRC8_FSEL1 (*((volatile unsigned int*)(0x42A79444UL))) +#define bM4_PORT_PFSRC8_FSEL2 (*((volatile unsigned int*)(0x42A79448UL))) +#define bM4_PORT_PFSRC8_FSEL3 (*((volatile unsigned int*)(0x42A7944CUL))) +#define bM4_PORT_PFSRC8_FSEL4 (*((volatile unsigned int*)(0x42A79450UL))) +#define bM4_PORT_PFSRC8_FSEL5 (*((volatile unsigned int*)(0x42A79454UL))) +#define bM4_PORT_PFSRC8_BFE (*((volatile unsigned int*)(0x42A79460UL))) +#define bM4_PORT_PCRC9_POUT (*((volatile unsigned int*)(0x42A79480UL))) +#define bM4_PORT_PCRC9_POUTE (*((volatile unsigned int*)(0x42A79484UL))) +#define bM4_PORT_PCRC9_NOD (*((volatile unsigned int*)(0x42A79488UL))) +#define bM4_PORT_PCRC9_DRV0 (*((volatile unsigned int*)(0x42A79490UL))) +#define bM4_PORT_PCRC9_DRV1 (*((volatile unsigned int*)(0x42A79494UL))) +#define bM4_PORT_PCRC9_PUU (*((volatile unsigned int*)(0x42A79498UL))) +#define bM4_PORT_PCRC9_PIN (*((volatile unsigned int*)(0x42A794A0UL))) +#define bM4_PORT_PCRC9_INVE (*((volatile unsigned int*)(0x42A794A4UL))) +#define bM4_PORT_PCRC9_INTE (*((volatile unsigned int*)(0x42A794B0UL))) +#define bM4_PORT_PCRC9_LTE (*((volatile unsigned int*)(0x42A794B8UL))) +#define bM4_PORT_PCRC9_DDIS (*((volatile unsigned int*)(0x42A794BCUL))) +#define bM4_PORT_PFSRC9_FSEL0 (*((volatile unsigned int*)(0x42A794C0UL))) +#define bM4_PORT_PFSRC9_FSEL1 (*((volatile unsigned int*)(0x42A794C4UL))) +#define bM4_PORT_PFSRC9_FSEL2 (*((volatile unsigned int*)(0x42A794C8UL))) +#define bM4_PORT_PFSRC9_FSEL3 (*((volatile unsigned int*)(0x42A794CCUL))) +#define bM4_PORT_PFSRC9_FSEL4 (*((volatile unsigned int*)(0x42A794D0UL))) +#define bM4_PORT_PFSRC9_FSEL5 (*((volatile unsigned int*)(0x42A794D4UL))) +#define bM4_PORT_PFSRC9_BFE (*((volatile unsigned int*)(0x42A794E0UL))) +#define bM4_PORT_PCRC10_POUT (*((volatile unsigned int*)(0x42A79500UL))) +#define bM4_PORT_PCRC10_POUTE (*((volatile unsigned int*)(0x42A79504UL))) +#define bM4_PORT_PCRC10_NOD (*((volatile unsigned int*)(0x42A79508UL))) +#define bM4_PORT_PCRC10_DRV0 (*((volatile unsigned int*)(0x42A79510UL))) +#define bM4_PORT_PCRC10_DRV1 (*((volatile unsigned int*)(0x42A79514UL))) +#define bM4_PORT_PCRC10_PUU (*((volatile unsigned int*)(0x42A79518UL))) +#define bM4_PORT_PCRC10_PIN (*((volatile unsigned int*)(0x42A79520UL))) +#define bM4_PORT_PCRC10_INVE (*((volatile unsigned int*)(0x42A79524UL))) +#define bM4_PORT_PCRC10_INTE (*((volatile unsigned int*)(0x42A79530UL))) +#define bM4_PORT_PCRC10_LTE (*((volatile unsigned int*)(0x42A79538UL))) +#define bM4_PORT_PCRC10_DDIS (*((volatile unsigned int*)(0x42A7953CUL))) +#define bM4_PORT_PFSRC10_FSEL0 (*((volatile unsigned int*)(0x42A79540UL))) +#define bM4_PORT_PFSRC10_FSEL1 (*((volatile unsigned int*)(0x42A79544UL))) +#define bM4_PORT_PFSRC10_FSEL2 (*((volatile unsigned int*)(0x42A79548UL))) +#define bM4_PORT_PFSRC10_FSEL3 (*((volatile unsigned int*)(0x42A7954CUL))) +#define bM4_PORT_PFSRC10_FSEL4 (*((volatile unsigned int*)(0x42A79550UL))) +#define bM4_PORT_PFSRC10_FSEL5 (*((volatile unsigned int*)(0x42A79554UL))) +#define bM4_PORT_PFSRC10_BFE (*((volatile unsigned int*)(0x42A79560UL))) +#define bM4_PORT_PCRC11_POUT (*((volatile unsigned int*)(0x42A79580UL))) +#define bM4_PORT_PCRC11_POUTE (*((volatile unsigned int*)(0x42A79584UL))) +#define bM4_PORT_PCRC11_NOD (*((volatile unsigned int*)(0x42A79588UL))) +#define bM4_PORT_PCRC11_DRV0 (*((volatile unsigned int*)(0x42A79590UL))) +#define bM4_PORT_PCRC11_DRV1 (*((volatile unsigned int*)(0x42A79594UL))) +#define bM4_PORT_PCRC11_PUU (*((volatile unsigned int*)(0x42A79598UL))) +#define bM4_PORT_PCRC11_PIN (*((volatile unsigned int*)(0x42A795A0UL))) +#define bM4_PORT_PCRC11_INVE (*((volatile unsigned int*)(0x42A795A4UL))) +#define bM4_PORT_PCRC11_INTE (*((volatile unsigned int*)(0x42A795B0UL))) +#define bM4_PORT_PCRC11_LTE (*((volatile unsigned int*)(0x42A795B8UL))) +#define bM4_PORT_PCRC11_DDIS (*((volatile unsigned int*)(0x42A795BCUL))) +#define bM4_PORT_PFSRC11_FSEL0 (*((volatile unsigned int*)(0x42A795C0UL))) +#define bM4_PORT_PFSRC11_FSEL1 (*((volatile unsigned int*)(0x42A795C4UL))) +#define bM4_PORT_PFSRC11_FSEL2 (*((volatile unsigned int*)(0x42A795C8UL))) +#define bM4_PORT_PFSRC11_FSEL3 (*((volatile unsigned int*)(0x42A795CCUL))) +#define bM4_PORT_PFSRC11_FSEL4 (*((volatile unsigned int*)(0x42A795D0UL))) +#define bM4_PORT_PFSRC11_FSEL5 (*((volatile unsigned int*)(0x42A795D4UL))) +#define bM4_PORT_PFSRC11_BFE (*((volatile unsigned int*)(0x42A795E0UL))) +#define bM4_PORT_PCRC12_POUT (*((volatile unsigned int*)(0x42A79600UL))) +#define bM4_PORT_PCRC12_POUTE (*((volatile unsigned int*)(0x42A79604UL))) +#define bM4_PORT_PCRC12_NOD (*((volatile unsigned int*)(0x42A79608UL))) +#define bM4_PORT_PCRC12_DRV0 (*((volatile unsigned int*)(0x42A79610UL))) +#define bM4_PORT_PCRC12_DRV1 (*((volatile unsigned int*)(0x42A79614UL))) +#define bM4_PORT_PCRC12_PUU (*((volatile unsigned int*)(0x42A79618UL))) +#define bM4_PORT_PCRC12_PIN (*((volatile unsigned int*)(0x42A79620UL))) +#define bM4_PORT_PCRC12_INVE (*((volatile unsigned int*)(0x42A79624UL))) +#define bM4_PORT_PCRC12_INTE (*((volatile unsigned int*)(0x42A79630UL))) +#define bM4_PORT_PCRC12_LTE (*((volatile unsigned int*)(0x42A79638UL))) +#define bM4_PORT_PCRC12_DDIS (*((volatile unsigned int*)(0x42A7963CUL))) +#define bM4_PORT_PFSRC12_FSEL0 (*((volatile unsigned int*)(0x42A79640UL))) +#define bM4_PORT_PFSRC12_FSEL1 (*((volatile unsigned int*)(0x42A79644UL))) +#define bM4_PORT_PFSRC12_FSEL2 (*((volatile unsigned int*)(0x42A79648UL))) +#define bM4_PORT_PFSRC12_FSEL3 (*((volatile unsigned int*)(0x42A7964CUL))) +#define bM4_PORT_PFSRC12_FSEL4 (*((volatile unsigned int*)(0x42A79650UL))) +#define bM4_PORT_PFSRC12_FSEL5 (*((volatile unsigned int*)(0x42A79654UL))) +#define bM4_PORT_PFSRC12_BFE (*((volatile unsigned int*)(0x42A79660UL))) +#define bM4_PORT_PCRC13_POUT (*((volatile unsigned int*)(0x42A79680UL))) +#define bM4_PORT_PCRC13_POUTE (*((volatile unsigned int*)(0x42A79684UL))) +#define bM4_PORT_PCRC13_NOD (*((volatile unsigned int*)(0x42A79688UL))) +#define bM4_PORT_PCRC13_DRV0 (*((volatile unsigned int*)(0x42A79690UL))) +#define bM4_PORT_PCRC13_DRV1 (*((volatile unsigned int*)(0x42A79694UL))) +#define bM4_PORT_PCRC13_PUU (*((volatile unsigned int*)(0x42A79698UL))) +#define bM4_PORT_PCRC13_PIN (*((volatile unsigned int*)(0x42A796A0UL))) +#define bM4_PORT_PCRC13_INVE (*((volatile unsigned int*)(0x42A796A4UL))) +#define bM4_PORT_PCRC13_INTE (*((volatile unsigned int*)(0x42A796B0UL))) +#define bM4_PORT_PCRC13_LTE (*((volatile unsigned int*)(0x42A796B8UL))) +#define bM4_PORT_PCRC13_DDIS (*((volatile unsigned int*)(0x42A796BCUL))) +#define bM4_PORT_PFSRC13_FSEL0 (*((volatile unsigned int*)(0x42A796C0UL))) +#define bM4_PORT_PFSRC13_FSEL1 (*((volatile unsigned int*)(0x42A796C4UL))) +#define bM4_PORT_PFSRC13_FSEL2 (*((volatile unsigned int*)(0x42A796C8UL))) +#define bM4_PORT_PFSRC13_FSEL3 (*((volatile unsigned int*)(0x42A796CCUL))) +#define bM4_PORT_PFSRC13_FSEL4 (*((volatile unsigned int*)(0x42A796D0UL))) +#define bM4_PORT_PFSRC13_FSEL5 (*((volatile unsigned int*)(0x42A796D4UL))) +#define bM4_PORT_PFSRC13_BFE (*((volatile unsigned int*)(0x42A796E0UL))) +#define bM4_PORT_PCRC14_POUT (*((volatile unsigned int*)(0x42A79700UL))) +#define bM4_PORT_PCRC14_POUTE (*((volatile unsigned int*)(0x42A79704UL))) +#define bM4_PORT_PCRC14_NOD (*((volatile unsigned int*)(0x42A79708UL))) +#define bM4_PORT_PCRC14_DRV0 (*((volatile unsigned int*)(0x42A79710UL))) +#define bM4_PORT_PCRC14_DRV1 (*((volatile unsigned int*)(0x42A79714UL))) +#define bM4_PORT_PCRC14_PUU (*((volatile unsigned int*)(0x42A79718UL))) +#define bM4_PORT_PCRC14_PIN (*((volatile unsigned int*)(0x42A79720UL))) +#define bM4_PORT_PCRC14_INVE (*((volatile unsigned int*)(0x42A79724UL))) +#define bM4_PORT_PCRC14_INTE (*((volatile unsigned int*)(0x42A79730UL))) +#define bM4_PORT_PCRC14_LTE (*((volatile unsigned int*)(0x42A79738UL))) +#define bM4_PORT_PCRC14_DDIS (*((volatile unsigned int*)(0x42A7973CUL))) +#define bM4_PORT_PFSRC14_FSEL0 (*((volatile unsigned int*)(0x42A79740UL))) +#define bM4_PORT_PFSRC14_FSEL1 (*((volatile unsigned int*)(0x42A79744UL))) +#define bM4_PORT_PFSRC14_FSEL2 (*((volatile unsigned int*)(0x42A79748UL))) +#define bM4_PORT_PFSRC14_FSEL3 (*((volatile unsigned int*)(0x42A7974CUL))) +#define bM4_PORT_PFSRC14_FSEL4 (*((volatile unsigned int*)(0x42A79750UL))) +#define bM4_PORT_PFSRC14_FSEL5 (*((volatile unsigned int*)(0x42A79754UL))) +#define bM4_PORT_PFSRC14_BFE (*((volatile unsigned int*)(0x42A79760UL))) +#define bM4_PORT_PCRC15_POUT (*((volatile unsigned int*)(0x42A79780UL))) +#define bM4_PORT_PCRC15_POUTE (*((volatile unsigned int*)(0x42A79784UL))) +#define bM4_PORT_PCRC15_NOD (*((volatile unsigned int*)(0x42A79788UL))) +#define bM4_PORT_PCRC15_DRV0 (*((volatile unsigned int*)(0x42A79790UL))) +#define bM4_PORT_PCRC15_DRV1 (*((volatile unsigned int*)(0x42A79794UL))) +#define bM4_PORT_PCRC15_PUU (*((volatile unsigned int*)(0x42A79798UL))) +#define bM4_PORT_PCRC15_PIN (*((volatile unsigned int*)(0x42A797A0UL))) +#define bM4_PORT_PCRC15_INVE (*((volatile unsigned int*)(0x42A797A4UL))) +#define bM4_PORT_PCRC15_INTE (*((volatile unsigned int*)(0x42A797B0UL))) +#define bM4_PORT_PCRC15_LTE (*((volatile unsigned int*)(0x42A797B8UL))) +#define bM4_PORT_PCRC15_DDIS (*((volatile unsigned int*)(0x42A797BCUL))) +#define bM4_PORT_PFSRC15_FSEL0 (*((volatile unsigned int*)(0x42A797C0UL))) +#define bM4_PORT_PFSRC15_FSEL1 (*((volatile unsigned int*)(0x42A797C4UL))) +#define bM4_PORT_PFSRC15_FSEL2 (*((volatile unsigned int*)(0x42A797C8UL))) +#define bM4_PORT_PFSRC15_FSEL3 (*((volatile unsigned int*)(0x42A797CCUL))) +#define bM4_PORT_PFSRC15_FSEL4 (*((volatile unsigned int*)(0x42A797D0UL))) +#define bM4_PORT_PFSRC15_FSEL5 (*((volatile unsigned int*)(0x42A797D4UL))) +#define bM4_PORT_PFSRC15_BFE (*((volatile unsigned int*)(0x42A797E0UL))) +#define bM4_PORT_PCRD0_POUT (*((volatile unsigned int*)(0x42A79800UL))) +#define bM4_PORT_PCRD0_POUTE (*((volatile unsigned int*)(0x42A79804UL))) +#define bM4_PORT_PCRD0_NOD (*((volatile unsigned int*)(0x42A79808UL))) +#define bM4_PORT_PCRD0_DRV0 (*((volatile unsigned int*)(0x42A79810UL))) +#define bM4_PORT_PCRD0_DRV1 (*((volatile unsigned int*)(0x42A79814UL))) +#define bM4_PORT_PCRD0_PUU (*((volatile unsigned int*)(0x42A79818UL))) +#define bM4_PORT_PCRD0_PIN (*((volatile unsigned int*)(0x42A79820UL))) +#define bM4_PORT_PCRD0_INVE (*((volatile unsigned int*)(0x42A79824UL))) +#define bM4_PORT_PCRD0_INTE (*((volatile unsigned int*)(0x42A79830UL))) +#define bM4_PORT_PCRD0_LTE (*((volatile unsigned int*)(0x42A79838UL))) +#define bM4_PORT_PCRD0_DDIS (*((volatile unsigned int*)(0x42A7983CUL))) +#define bM4_PORT_PFSRD0_FSEL0 (*((volatile unsigned int*)(0x42A79840UL))) +#define bM4_PORT_PFSRD0_FSEL1 (*((volatile unsigned int*)(0x42A79844UL))) +#define bM4_PORT_PFSRD0_FSEL2 (*((volatile unsigned int*)(0x42A79848UL))) +#define bM4_PORT_PFSRD0_FSEL3 (*((volatile unsigned int*)(0x42A7984CUL))) +#define bM4_PORT_PFSRD0_FSEL4 (*((volatile unsigned int*)(0x42A79850UL))) +#define bM4_PORT_PFSRD0_FSEL5 (*((volatile unsigned int*)(0x42A79854UL))) +#define bM4_PORT_PFSRD0_BFE (*((volatile unsigned int*)(0x42A79860UL))) +#define bM4_PORT_PCRD1_POUT (*((volatile unsigned int*)(0x42A79880UL))) +#define bM4_PORT_PCRD1_POUTE (*((volatile unsigned int*)(0x42A79884UL))) +#define bM4_PORT_PCRD1_NOD (*((volatile unsigned int*)(0x42A79888UL))) +#define bM4_PORT_PCRD1_DRV0 (*((volatile unsigned int*)(0x42A79890UL))) +#define bM4_PORT_PCRD1_DRV1 (*((volatile unsigned int*)(0x42A79894UL))) +#define bM4_PORT_PCRD1_PUU (*((volatile unsigned int*)(0x42A79898UL))) +#define bM4_PORT_PCRD1_PIN (*((volatile unsigned int*)(0x42A798A0UL))) +#define bM4_PORT_PCRD1_INVE (*((volatile unsigned int*)(0x42A798A4UL))) +#define bM4_PORT_PCRD1_INTE (*((volatile unsigned int*)(0x42A798B0UL))) +#define bM4_PORT_PCRD1_LTE (*((volatile unsigned int*)(0x42A798B8UL))) +#define bM4_PORT_PCRD1_DDIS (*((volatile unsigned int*)(0x42A798BCUL))) +#define bM4_PORT_PFSRD1_FSEL0 (*((volatile unsigned int*)(0x42A798C0UL))) +#define bM4_PORT_PFSRD1_FSEL1 (*((volatile unsigned int*)(0x42A798C4UL))) +#define bM4_PORT_PFSRD1_FSEL2 (*((volatile unsigned int*)(0x42A798C8UL))) +#define bM4_PORT_PFSRD1_FSEL3 (*((volatile unsigned int*)(0x42A798CCUL))) +#define bM4_PORT_PFSRD1_FSEL4 (*((volatile unsigned int*)(0x42A798D0UL))) +#define bM4_PORT_PFSRD1_FSEL5 (*((volatile unsigned int*)(0x42A798D4UL))) +#define bM4_PORT_PFSRD1_BFE (*((volatile unsigned int*)(0x42A798E0UL))) +#define bM4_PORT_PCRD2_POUT (*((volatile unsigned int*)(0x42A79900UL))) +#define bM4_PORT_PCRD2_POUTE (*((volatile unsigned int*)(0x42A79904UL))) +#define bM4_PORT_PCRD2_NOD (*((volatile unsigned int*)(0x42A79908UL))) +#define bM4_PORT_PCRD2_DRV0 (*((volatile unsigned int*)(0x42A79910UL))) +#define bM4_PORT_PCRD2_DRV1 (*((volatile unsigned int*)(0x42A79914UL))) +#define bM4_PORT_PCRD2_PUU (*((volatile unsigned int*)(0x42A79918UL))) +#define bM4_PORT_PCRD2_PIN (*((volatile unsigned int*)(0x42A79920UL))) +#define bM4_PORT_PCRD2_INVE (*((volatile unsigned int*)(0x42A79924UL))) +#define bM4_PORT_PCRD2_INTE (*((volatile unsigned int*)(0x42A79930UL))) +#define bM4_PORT_PCRD2_LTE (*((volatile unsigned int*)(0x42A79938UL))) +#define bM4_PORT_PCRD2_DDIS (*((volatile unsigned int*)(0x42A7993CUL))) +#define bM4_PORT_PFSRD2_FSEL0 (*((volatile unsigned int*)(0x42A79940UL))) +#define bM4_PORT_PFSRD2_FSEL1 (*((volatile unsigned int*)(0x42A79944UL))) +#define bM4_PORT_PFSRD2_FSEL2 (*((volatile unsigned int*)(0x42A79948UL))) +#define bM4_PORT_PFSRD2_FSEL3 (*((volatile unsigned int*)(0x42A7994CUL))) +#define bM4_PORT_PFSRD2_FSEL4 (*((volatile unsigned int*)(0x42A79950UL))) +#define bM4_PORT_PFSRD2_FSEL5 (*((volatile unsigned int*)(0x42A79954UL))) +#define bM4_PORT_PFSRD2_BFE (*((volatile unsigned int*)(0x42A79960UL))) +#define bM4_PORT_PCRD3_POUT (*((volatile unsigned int*)(0x42A79980UL))) +#define bM4_PORT_PCRD3_POUTE (*((volatile unsigned int*)(0x42A79984UL))) +#define bM4_PORT_PCRD3_NOD (*((volatile unsigned int*)(0x42A79988UL))) +#define bM4_PORT_PCRD3_DRV0 (*((volatile unsigned int*)(0x42A79990UL))) +#define bM4_PORT_PCRD3_DRV1 (*((volatile unsigned int*)(0x42A79994UL))) +#define bM4_PORT_PCRD3_PUU (*((volatile unsigned int*)(0x42A79998UL))) +#define bM4_PORT_PCRD3_PIN (*((volatile unsigned int*)(0x42A799A0UL))) +#define bM4_PORT_PCRD3_INVE (*((volatile unsigned int*)(0x42A799A4UL))) +#define bM4_PORT_PCRD3_INTE (*((volatile unsigned int*)(0x42A799B0UL))) +#define bM4_PORT_PCRD3_LTE (*((volatile unsigned int*)(0x42A799B8UL))) +#define bM4_PORT_PCRD3_DDIS (*((volatile unsigned int*)(0x42A799BCUL))) +#define bM4_PORT_PFSRD3_FSEL0 (*((volatile unsigned int*)(0x42A799C0UL))) +#define bM4_PORT_PFSRD3_FSEL1 (*((volatile unsigned int*)(0x42A799C4UL))) +#define bM4_PORT_PFSRD3_FSEL2 (*((volatile unsigned int*)(0x42A799C8UL))) +#define bM4_PORT_PFSRD3_FSEL3 (*((volatile unsigned int*)(0x42A799CCUL))) +#define bM4_PORT_PFSRD3_FSEL4 (*((volatile unsigned int*)(0x42A799D0UL))) +#define bM4_PORT_PFSRD3_FSEL5 (*((volatile unsigned int*)(0x42A799D4UL))) +#define bM4_PORT_PFSRD3_BFE (*((volatile unsigned int*)(0x42A799E0UL))) +#define bM4_PORT_PCRD4_POUT (*((volatile unsigned int*)(0x42A79A00UL))) +#define bM4_PORT_PCRD4_POUTE (*((volatile unsigned int*)(0x42A79A04UL))) +#define bM4_PORT_PCRD4_NOD (*((volatile unsigned int*)(0x42A79A08UL))) +#define bM4_PORT_PCRD4_DRV0 (*((volatile unsigned int*)(0x42A79A10UL))) +#define bM4_PORT_PCRD4_DRV1 (*((volatile unsigned int*)(0x42A79A14UL))) +#define bM4_PORT_PCRD4_PUU (*((volatile unsigned int*)(0x42A79A18UL))) +#define bM4_PORT_PCRD4_PIN (*((volatile unsigned int*)(0x42A79A20UL))) +#define bM4_PORT_PCRD4_INVE (*((volatile unsigned int*)(0x42A79A24UL))) +#define bM4_PORT_PCRD4_INTE (*((volatile unsigned int*)(0x42A79A30UL))) +#define bM4_PORT_PCRD4_LTE (*((volatile unsigned int*)(0x42A79A38UL))) +#define bM4_PORT_PCRD4_DDIS (*((volatile unsigned int*)(0x42A79A3CUL))) +#define bM4_PORT_PFSRD4_FSEL0 (*((volatile unsigned int*)(0x42A79A40UL))) +#define bM4_PORT_PFSRD4_FSEL1 (*((volatile unsigned int*)(0x42A79A44UL))) +#define bM4_PORT_PFSRD4_FSEL2 (*((volatile unsigned int*)(0x42A79A48UL))) +#define bM4_PORT_PFSRD4_FSEL3 (*((volatile unsigned int*)(0x42A79A4CUL))) +#define bM4_PORT_PFSRD4_FSEL4 (*((volatile unsigned int*)(0x42A79A50UL))) +#define bM4_PORT_PFSRD4_FSEL5 (*((volatile unsigned int*)(0x42A79A54UL))) +#define bM4_PORT_PFSRD4_BFE (*((volatile unsigned int*)(0x42A79A60UL))) +#define bM4_PORT_PCRD5_POUT (*((volatile unsigned int*)(0x42A79A80UL))) +#define bM4_PORT_PCRD5_POUTE (*((volatile unsigned int*)(0x42A79A84UL))) +#define bM4_PORT_PCRD5_NOD (*((volatile unsigned int*)(0x42A79A88UL))) +#define bM4_PORT_PCRD5_DRV0 (*((volatile unsigned int*)(0x42A79A90UL))) +#define bM4_PORT_PCRD5_DRV1 (*((volatile unsigned int*)(0x42A79A94UL))) +#define bM4_PORT_PCRD5_PUU (*((volatile unsigned int*)(0x42A79A98UL))) +#define bM4_PORT_PCRD5_PIN (*((volatile unsigned int*)(0x42A79AA0UL))) +#define bM4_PORT_PCRD5_INVE (*((volatile unsigned int*)(0x42A79AA4UL))) +#define bM4_PORT_PCRD5_INTE (*((volatile unsigned int*)(0x42A79AB0UL))) +#define bM4_PORT_PCRD5_LTE (*((volatile unsigned int*)(0x42A79AB8UL))) +#define bM4_PORT_PCRD5_DDIS (*((volatile unsigned int*)(0x42A79ABCUL))) +#define bM4_PORT_PFSRD5_FSEL0 (*((volatile unsigned int*)(0x42A79AC0UL))) +#define bM4_PORT_PFSRD5_FSEL1 (*((volatile unsigned int*)(0x42A79AC4UL))) +#define bM4_PORT_PFSRD5_FSEL2 (*((volatile unsigned int*)(0x42A79AC8UL))) +#define bM4_PORT_PFSRD5_FSEL3 (*((volatile unsigned int*)(0x42A79ACCUL))) +#define bM4_PORT_PFSRD5_FSEL4 (*((volatile unsigned int*)(0x42A79AD0UL))) +#define bM4_PORT_PFSRD5_FSEL5 (*((volatile unsigned int*)(0x42A79AD4UL))) +#define bM4_PORT_PFSRD5_BFE (*((volatile unsigned int*)(0x42A79AE0UL))) +#define bM4_PORT_PCRD6_POUT (*((volatile unsigned int*)(0x42A79B00UL))) +#define bM4_PORT_PCRD6_POUTE (*((volatile unsigned int*)(0x42A79B04UL))) +#define bM4_PORT_PCRD6_NOD (*((volatile unsigned int*)(0x42A79B08UL))) +#define bM4_PORT_PCRD6_DRV0 (*((volatile unsigned int*)(0x42A79B10UL))) +#define bM4_PORT_PCRD6_DRV1 (*((volatile unsigned int*)(0x42A79B14UL))) +#define bM4_PORT_PCRD6_PUU (*((volatile unsigned int*)(0x42A79B18UL))) +#define bM4_PORT_PCRD6_PIN (*((volatile unsigned int*)(0x42A79B20UL))) +#define bM4_PORT_PCRD6_INVE (*((volatile unsigned int*)(0x42A79B24UL))) +#define bM4_PORT_PCRD6_INTE (*((volatile unsigned int*)(0x42A79B30UL))) +#define bM4_PORT_PCRD6_LTE (*((volatile unsigned int*)(0x42A79B38UL))) +#define bM4_PORT_PCRD6_DDIS (*((volatile unsigned int*)(0x42A79B3CUL))) +#define bM4_PORT_PFSRD6_FSEL0 (*((volatile unsigned int*)(0x42A79B40UL))) +#define bM4_PORT_PFSRD6_FSEL1 (*((volatile unsigned int*)(0x42A79B44UL))) +#define bM4_PORT_PFSRD6_FSEL2 (*((volatile unsigned int*)(0x42A79B48UL))) +#define bM4_PORT_PFSRD6_FSEL3 (*((volatile unsigned int*)(0x42A79B4CUL))) +#define bM4_PORT_PFSRD6_FSEL4 (*((volatile unsigned int*)(0x42A79B50UL))) +#define bM4_PORT_PFSRD6_FSEL5 (*((volatile unsigned int*)(0x42A79B54UL))) +#define bM4_PORT_PFSRD6_BFE (*((volatile unsigned int*)(0x42A79B60UL))) +#define bM4_PORT_PCRD7_POUT (*((volatile unsigned int*)(0x42A79B80UL))) +#define bM4_PORT_PCRD7_POUTE (*((volatile unsigned int*)(0x42A79B84UL))) +#define bM4_PORT_PCRD7_NOD (*((volatile unsigned int*)(0x42A79B88UL))) +#define bM4_PORT_PCRD7_DRV0 (*((volatile unsigned int*)(0x42A79B90UL))) +#define bM4_PORT_PCRD7_DRV1 (*((volatile unsigned int*)(0x42A79B94UL))) +#define bM4_PORT_PCRD7_PUU (*((volatile unsigned int*)(0x42A79B98UL))) +#define bM4_PORT_PCRD7_PIN (*((volatile unsigned int*)(0x42A79BA0UL))) +#define bM4_PORT_PCRD7_INVE (*((volatile unsigned int*)(0x42A79BA4UL))) +#define bM4_PORT_PCRD7_INTE (*((volatile unsigned int*)(0x42A79BB0UL))) +#define bM4_PORT_PCRD7_LTE (*((volatile unsigned int*)(0x42A79BB8UL))) +#define bM4_PORT_PCRD7_DDIS (*((volatile unsigned int*)(0x42A79BBCUL))) +#define bM4_PORT_PFSRD7_FSEL0 (*((volatile unsigned int*)(0x42A79BC0UL))) +#define bM4_PORT_PFSRD7_FSEL1 (*((volatile unsigned int*)(0x42A79BC4UL))) +#define bM4_PORT_PFSRD7_FSEL2 (*((volatile unsigned int*)(0x42A79BC8UL))) +#define bM4_PORT_PFSRD7_FSEL3 (*((volatile unsigned int*)(0x42A79BCCUL))) +#define bM4_PORT_PFSRD7_FSEL4 (*((volatile unsigned int*)(0x42A79BD0UL))) +#define bM4_PORT_PFSRD7_FSEL5 (*((volatile unsigned int*)(0x42A79BD4UL))) +#define bM4_PORT_PFSRD7_BFE (*((volatile unsigned int*)(0x42A79BE0UL))) +#define bM4_PORT_PCRD8_POUT (*((volatile unsigned int*)(0x42A79C00UL))) +#define bM4_PORT_PCRD8_POUTE (*((volatile unsigned int*)(0x42A79C04UL))) +#define bM4_PORT_PCRD8_NOD (*((volatile unsigned int*)(0x42A79C08UL))) +#define bM4_PORT_PCRD8_DRV0 (*((volatile unsigned int*)(0x42A79C10UL))) +#define bM4_PORT_PCRD8_DRV1 (*((volatile unsigned int*)(0x42A79C14UL))) +#define bM4_PORT_PCRD8_PUU (*((volatile unsigned int*)(0x42A79C18UL))) +#define bM4_PORT_PCRD8_PIN (*((volatile unsigned int*)(0x42A79C20UL))) +#define bM4_PORT_PCRD8_INVE (*((volatile unsigned int*)(0x42A79C24UL))) +#define bM4_PORT_PCRD8_INTE (*((volatile unsigned int*)(0x42A79C30UL))) +#define bM4_PORT_PCRD8_LTE (*((volatile unsigned int*)(0x42A79C38UL))) +#define bM4_PORT_PCRD8_DDIS (*((volatile unsigned int*)(0x42A79C3CUL))) +#define bM4_PORT_PFSRD8_FSEL0 (*((volatile unsigned int*)(0x42A79C40UL))) +#define bM4_PORT_PFSRD8_FSEL1 (*((volatile unsigned int*)(0x42A79C44UL))) +#define bM4_PORT_PFSRD8_FSEL2 (*((volatile unsigned int*)(0x42A79C48UL))) +#define bM4_PORT_PFSRD8_FSEL3 (*((volatile unsigned int*)(0x42A79C4CUL))) +#define bM4_PORT_PFSRD8_FSEL4 (*((volatile unsigned int*)(0x42A79C50UL))) +#define bM4_PORT_PFSRD8_FSEL5 (*((volatile unsigned int*)(0x42A79C54UL))) +#define bM4_PORT_PFSRD8_BFE (*((volatile unsigned int*)(0x42A79C60UL))) +#define bM4_PORT_PCRD9_POUT (*((volatile unsigned int*)(0x42A79C80UL))) +#define bM4_PORT_PCRD9_POUTE (*((volatile unsigned int*)(0x42A79C84UL))) +#define bM4_PORT_PCRD9_NOD (*((volatile unsigned int*)(0x42A79C88UL))) +#define bM4_PORT_PCRD9_DRV0 (*((volatile unsigned int*)(0x42A79C90UL))) +#define bM4_PORT_PCRD9_DRV1 (*((volatile unsigned int*)(0x42A79C94UL))) +#define bM4_PORT_PCRD9_PUU (*((volatile unsigned int*)(0x42A79C98UL))) +#define bM4_PORT_PCRD9_PIN (*((volatile unsigned int*)(0x42A79CA0UL))) +#define bM4_PORT_PCRD9_INVE (*((volatile unsigned int*)(0x42A79CA4UL))) +#define bM4_PORT_PCRD9_INTE (*((volatile unsigned int*)(0x42A79CB0UL))) +#define bM4_PORT_PCRD9_LTE (*((volatile unsigned int*)(0x42A79CB8UL))) +#define bM4_PORT_PCRD9_DDIS (*((volatile unsigned int*)(0x42A79CBCUL))) +#define bM4_PORT_PFSRD9_FSEL0 (*((volatile unsigned int*)(0x42A79CC0UL))) +#define bM4_PORT_PFSRD9_FSEL1 (*((volatile unsigned int*)(0x42A79CC4UL))) +#define bM4_PORT_PFSRD9_FSEL2 (*((volatile unsigned int*)(0x42A79CC8UL))) +#define bM4_PORT_PFSRD9_FSEL3 (*((volatile unsigned int*)(0x42A79CCCUL))) +#define bM4_PORT_PFSRD9_FSEL4 (*((volatile unsigned int*)(0x42A79CD0UL))) +#define bM4_PORT_PFSRD9_FSEL5 (*((volatile unsigned int*)(0x42A79CD4UL))) +#define bM4_PORT_PFSRD9_BFE (*((volatile unsigned int*)(0x42A79CE0UL))) +#define bM4_PORT_PCRD10_POUT (*((volatile unsigned int*)(0x42A79D00UL))) +#define bM4_PORT_PCRD10_POUTE (*((volatile unsigned int*)(0x42A79D04UL))) +#define bM4_PORT_PCRD10_NOD (*((volatile unsigned int*)(0x42A79D08UL))) +#define bM4_PORT_PCRD10_DRV0 (*((volatile unsigned int*)(0x42A79D10UL))) +#define bM4_PORT_PCRD10_DRV1 (*((volatile unsigned int*)(0x42A79D14UL))) +#define bM4_PORT_PCRD10_PUU (*((volatile unsigned int*)(0x42A79D18UL))) +#define bM4_PORT_PCRD10_PIN (*((volatile unsigned int*)(0x42A79D20UL))) +#define bM4_PORT_PCRD10_INVE (*((volatile unsigned int*)(0x42A79D24UL))) +#define bM4_PORT_PCRD10_INTE (*((volatile unsigned int*)(0x42A79D30UL))) +#define bM4_PORT_PCRD10_LTE (*((volatile unsigned int*)(0x42A79D38UL))) +#define bM4_PORT_PCRD10_DDIS (*((volatile unsigned int*)(0x42A79D3CUL))) +#define bM4_PORT_PFSRD10_FSEL0 (*((volatile unsigned int*)(0x42A79D40UL))) +#define bM4_PORT_PFSRD10_FSEL1 (*((volatile unsigned int*)(0x42A79D44UL))) +#define bM4_PORT_PFSRD10_FSEL2 (*((volatile unsigned int*)(0x42A79D48UL))) +#define bM4_PORT_PFSRD10_FSEL3 (*((volatile unsigned int*)(0x42A79D4CUL))) +#define bM4_PORT_PFSRD10_FSEL4 (*((volatile unsigned int*)(0x42A79D50UL))) +#define bM4_PORT_PFSRD10_FSEL5 (*((volatile unsigned int*)(0x42A79D54UL))) +#define bM4_PORT_PFSRD10_BFE (*((volatile unsigned int*)(0x42A79D60UL))) +#define bM4_PORT_PCRD11_POUT (*((volatile unsigned int*)(0x42A79D80UL))) +#define bM4_PORT_PCRD11_POUTE (*((volatile unsigned int*)(0x42A79D84UL))) +#define bM4_PORT_PCRD11_NOD (*((volatile unsigned int*)(0x42A79D88UL))) +#define bM4_PORT_PCRD11_DRV0 (*((volatile unsigned int*)(0x42A79D90UL))) +#define bM4_PORT_PCRD11_DRV1 (*((volatile unsigned int*)(0x42A79D94UL))) +#define bM4_PORT_PCRD11_PUU (*((volatile unsigned int*)(0x42A79D98UL))) +#define bM4_PORT_PCRD11_PIN (*((volatile unsigned int*)(0x42A79DA0UL))) +#define bM4_PORT_PCRD11_INVE (*((volatile unsigned int*)(0x42A79DA4UL))) +#define bM4_PORT_PCRD11_INTE (*((volatile unsigned int*)(0x42A79DB0UL))) +#define bM4_PORT_PCRD11_LTE (*((volatile unsigned int*)(0x42A79DB8UL))) +#define bM4_PORT_PCRD11_DDIS (*((volatile unsigned int*)(0x42A79DBCUL))) +#define bM4_PORT_PFSRD11_FSEL0 (*((volatile unsigned int*)(0x42A79DC0UL))) +#define bM4_PORT_PFSRD11_FSEL1 (*((volatile unsigned int*)(0x42A79DC4UL))) +#define bM4_PORT_PFSRD11_FSEL2 (*((volatile unsigned int*)(0x42A79DC8UL))) +#define bM4_PORT_PFSRD11_FSEL3 (*((volatile unsigned int*)(0x42A79DCCUL))) +#define bM4_PORT_PFSRD11_FSEL4 (*((volatile unsigned int*)(0x42A79DD0UL))) +#define bM4_PORT_PFSRD11_FSEL5 (*((volatile unsigned int*)(0x42A79DD4UL))) +#define bM4_PORT_PFSRD11_BFE (*((volatile unsigned int*)(0x42A79DE0UL))) +#define bM4_PORT_PCRD12_POUT (*((volatile unsigned int*)(0x42A79E00UL))) +#define bM4_PORT_PCRD12_POUTE (*((volatile unsigned int*)(0x42A79E04UL))) +#define bM4_PORT_PCRD12_NOD (*((volatile unsigned int*)(0x42A79E08UL))) +#define bM4_PORT_PCRD12_DRV0 (*((volatile unsigned int*)(0x42A79E10UL))) +#define bM4_PORT_PCRD12_DRV1 (*((volatile unsigned int*)(0x42A79E14UL))) +#define bM4_PORT_PCRD12_PUU (*((volatile unsigned int*)(0x42A79E18UL))) +#define bM4_PORT_PCRD12_PIN (*((volatile unsigned int*)(0x42A79E20UL))) +#define bM4_PORT_PCRD12_INVE (*((volatile unsigned int*)(0x42A79E24UL))) +#define bM4_PORT_PCRD12_INTE (*((volatile unsigned int*)(0x42A79E30UL))) +#define bM4_PORT_PCRD12_LTE (*((volatile unsigned int*)(0x42A79E38UL))) +#define bM4_PORT_PCRD12_DDIS (*((volatile unsigned int*)(0x42A79E3CUL))) +#define bM4_PORT_PFSRD12_FSEL0 (*((volatile unsigned int*)(0x42A79E40UL))) +#define bM4_PORT_PFSRD12_FSEL1 (*((volatile unsigned int*)(0x42A79E44UL))) +#define bM4_PORT_PFSRD12_FSEL2 (*((volatile unsigned int*)(0x42A79E48UL))) +#define bM4_PORT_PFSRD12_FSEL3 (*((volatile unsigned int*)(0x42A79E4CUL))) +#define bM4_PORT_PFSRD12_FSEL4 (*((volatile unsigned int*)(0x42A79E50UL))) +#define bM4_PORT_PFSRD12_FSEL5 (*((volatile unsigned int*)(0x42A79E54UL))) +#define bM4_PORT_PFSRD12_BFE (*((volatile unsigned int*)(0x42A79E60UL))) +#define bM4_PORT_PCRD13_POUT (*((volatile unsigned int*)(0x42A79E80UL))) +#define bM4_PORT_PCRD13_POUTE (*((volatile unsigned int*)(0x42A79E84UL))) +#define bM4_PORT_PCRD13_NOD (*((volatile unsigned int*)(0x42A79E88UL))) +#define bM4_PORT_PCRD13_DRV0 (*((volatile unsigned int*)(0x42A79E90UL))) +#define bM4_PORT_PCRD13_DRV1 (*((volatile unsigned int*)(0x42A79E94UL))) +#define bM4_PORT_PCRD13_PUU (*((volatile unsigned int*)(0x42A79E98UL))) +#define bM4_PORT_PCRD13_PIN (*((volatile unsigned int*)(0x42A79EA0UL))) +#define bM4_PORT_PCRD13_INVE (*((volatile unsigned int*)(0x42A79EA4UL))) +#define bM4_PORT_PCRD13_INTE (*((volatile unsigned int*)(0x42A79EB0UL))) +#define bM4_PORT_PCRD13_LTE (*((volatile unsigned int*)(0x42A79EB8UL))) +#define bM4_PORT_PCRD13_DDIS (*((volatile unsigned int*)(0x42A79EBCUL))) +#define bM4_PORT_PFSRD13_FSEL0 (*((volatile unsigned int*)(0x42A79EC0UL))) +#define bM4_PORT_PFSRD13_FSEL1 (*((volatile unsigned int*)(0x42A79EC4UL))) +#define bM4_PORT_PFSRD13_FSEL2 (*((volatile unsigned int*)(0x42A79EC8UL))) +#define bM4_PORT_PFSRD13_FSEL3 (*((volatile unsigned int*)(0x42A79ECCUL))) +#define bM4_PORT_PFSRD13_FSEL4 (*((volatile unsigned int*)(0x42A79ED0UL))) +#define bM4_PORT_PFSRD13_FSEL5 (*((volatile unsigned int*)(0x42A79ED4UL))) +#define bM4_PORT_PFSRD13_BFE (*((volatile unsigned int*)(0x42A79EE0UL))) +#define bM4_PORT_PCRD14_POUT (*((volatile unsigned int*)(0x42A79F00UL))) +#define bM4_PORT_PCRD14_POUTE (*((volatile unsigned int*)(0x42A79F04UL))) +#define bM4_PORT_PCRD14_NOD (*((volatile unsigned int*)(0x42A79F08UL))) +#define bM4_PORT_PCRD14_DRV0 (*((volatile unsigned int*)(0x42A79F10UL))) +#define bM4_PORT_PCRD14_DRV1 (*((volatile unsigned int*)(0x42A79F14UL))) +#define bM4_PORT_PCRD14_PUU (*((volatile unsigned int*)(0x42A79F18UL))) +#define bM4_PORT_PCRD14_PIN (*((volatile unsigned int*)(0x42A79F20UL))) +#define bM4_PORT_PCRD14_INVE (*((volatile unsigned int*)(0x42A79F24UL))) +#define bM4_PORT_PCRD14_INTE (*((volatile unsigned int*)(0x42A79F30UL))) +#define bM4_PORT_PCRD14_LTE (*((volatile unsigned int*)(0x42A79F38UL))) +#define bM4_PORT_PCRD14_DDIS (*((volatile unsigned int*)(0x42A79F3CUL))) +#define bM4_PORT_PFSRD14_FSEL0 (*((volatile unsigned int*)(0x42A79F40UL))) +#define bM4_PORT_PFSRD14_FSEL1 (*((volatile unsigned int*)(0x42A79F44UL))) +#define bM4_PORT_PFSRD14_FSEL2 (*((volatile unsigned int*)(0x42A79F48UL))) +#define bM4_PORT_PFSRD14_FSEL3 (*((volatile unsigned int*)(0x42A79F4CUL))) +#define bM4_PORT_PFSRD14_FSEL4 (*((volatile unsigned int*)(0x42A79F50UL))) +#define bM4_PORT_PFSRD14_FSEL5 (*((volatile unsigned int*)(0x42A79F54UL))) +#define bM4_PORT_PFSRD14_BFE (*((volatile unsigned int*)(0x42A79F60UL))) +#define bM4_PORT_PCRD15_POUT (*((volatile unsigned int*)(0x42A79F80UL))) +#define bM4_PORT_PCRD15_POUTE (*((volatile unsigned int*)(0x42A79F84UL))) +#define bM4_PORT_PCRD15_NOD (*((volatile unsigned int*)(0x42A79F88UL))) +#define bM4_PORT_PCRD15_DRV0 (*((volatile unsigned int*)(0x42A79F90UL))) +#define bM4_PORT_PCRD15_DRV1 (*((volatile unsigned int*)(0x42A79F94UL))) +#define bM4_PORT_PCRD15_PUU (*((volatile unsigned int*)(0x42A79F98UL))) +#define bM4_PORT_PCRD15_PIN (*((volatile unsigned int*)(0x42A79FA0UL))) +#define bM4_PORT_PCRD15_INVE (*((volatile unsigned int*)(0x42A79FA4UL))) +#define bM4_PORT_PCRD15_INTE (*((volatile unsigned int*)(0x42A79FB0UL))) +#define bM4_PORT_PCRD15_LTE (*((volatile unsigned int*)(0x42A79FB8UL))) +#define bM4_PORT_PCRD15_DDIS (*((volatile unsigned int*)(0x42A79FBCUL))) +#define bM4_PORT_PFSRD15_FSEL0 (*((volatile unsigned int*)(0x42A79FC0UL))) +#define bM4_PORT_PFSRD15_FSEL1 (*((volatile unsigned int*)(0x42A79FC4UL))) +#define bM4_PORT_PFSRD15_FSEL2 (*((volatile unsigned int*)(0x42A79FC8UL))) +#define bM4_PORT_PFSRD15_FSEL3 (*((volatile unsigned int*)(0x42A79FCCUL))) +#define bM4_PORT_PFSRD15_FSEL4 (*((volatile unsigned int*)(0x42A79FD0UL))) +#define bM4_PORT_PFSRD15_FSEL5 (*((volatile unsigned int*)(0x42A79FD4UL))) +#define bM4_PORT_PFSRD15_BFE (*((volatile unsigned int*)(0x42A79FE0UL))) +#define bM4_PORT_PCRE0_POUT (*((volatile unsigned int*)(0x42A7A000UL))) +#define bM4_PORT_PCRE0_POUTE (*((volatile unsigned int*)(0x42A7A004UL))) +#define bM4_PORT_PCRE0_NOD (*((volatile unsigned int*)(0x42A7A008UL))) +#define bM4_PORT_PCRE0_DRV0 (*((volatile unsigned int*)(0x42A7A010UL))) +#define bM4_PORT_PCRE0_DRV1 (*((volatile unsigned int*)(0x42A7A014UL))) +#define bM4_PORT_PCRE0_PUU (*((volatile unsigned int*)(0x42A7A018UL))) +#define bM4_PORT_PCRE0_PIN (*((volatile unsigned int*)(0x42A7A020UL))) +#define bM4_PORT_PCRE0_INVE (*((volatile unsigned int*)(0x42A7A024UL))) +#define bM4_PORT_PCRE0_INTE (*((volatile unsigned int*)(0x42A7A030UL))) +#define bM4_PORT_PCRE0_LTE (*((volatile unsigned int*)(0x42A7A038UL))) +#define bM4_PORT_PCRE0_DDIS (*((volatile unsigned int*)(0x42A7A03CUL))) +#define bM4_PORT_PFSRE0_FSEL0 (*((volatile unsigned int*)(0x42A7A040UL))) +#define bM4_PORT_PFSRE0_FSEL1 (*((volatile unsigned int*)(0x42A7A044UL))) +#define bM4_PORT_PFSRE0_FSEL2 (*((volatile unsigned int*)(0x42A7A048UL))) +#define bM4_PORT_PFSRE0_FSEL3 (*((volatile unsigned int*)(0x42A7A04CUL))) +#define bM4_PORT_PFSRE0_FSEL4 (*((volatile unsigned int*)(0x42A7A050UL))) +#define bM4_PORT_PFSRE0_FSEL5 (*((volatile unsigned int*)(0x42A7A054UL))) +#define bM4_PORT_PFSRE0_BFE (*((volatile unsigned int*)(0x42A7A060UL))) +#define bM4_PORT_PCRE1_POUT (*((volatile unsigned int*)(0x42A7A080UL))) +#define bM4_PORT_PCRE1_POUTE (*((volatile unsigned int*)(0x42A7A084UL))) +#define bM4_PORT_PCRE1_NOD (*((volatile unsigned int*)(0x42A7A088UL))) +#define bM4_PORT_PCRE1_DRV0 (*((volatile unsigned int*)(0x42A7A090UL))) +#define bM4_PORT_PCRE1_DRV1 (*((volatile unsigned int*)(0x42A7A094UL))) +#define bM4_PORT_PCRE1_PUU (*((volatile unsigned int*)(0x42A7A098UL))) +#define bM4_PORT_PCRE1_PIN (*((volatile unsigned int*)(0x42A7A0A0UL))) +#define bM4_PORT_PCRE1_INVE (*((volatile unsigned int*)(0x42A7A0A4UL))) +#define bM4_PORT_PCRE1_INTE (*((volatile unsigned int*)(0x42A7A0B0UL))) +#define bM4_PORT_PCRE1_LTE (*((volatile unsigned int*)(0x42A7A0B8UL))) +#define bM4_PORT_PCRE1_DDIS (*((volatile unsigned int*)(0x42A7A0BCUL))) +#define bM4_PORT_PFSRE1_FSEL0 (*((volatile unsigned int*)(0x42A7A0C0UL))) +#define bM4_PORT_PFSRE1_FSEL1 (*((volatile unsigned int*)(0x42A7A0C4UL))) +#define bM4_PORT_PFSRE1_FSEL2 (*((volatile unsigned int*)(0x42A7A0C8UL))) +#define bM4_PORT_PFSRE1_FSEL3 (*((volatile unsigned int*)(0x42A7A0CCUL))) +#define bM4_PORT_PFSRE1_FSEL4 (*((volatile unsigned int*)(0x42A7A0D0UL))) +#define bM4_PORT_PFSRE1_FSEL5 (*((volatile unsigned int*)(0x42A7A0D4UL))) +#define bM4_PORT_PFSRE1_BFE (*((volatile unsigned int*)(0x42A7A0E0UL))) +#define bM4_PORT_PCRE2_POUT (*((volatile unsigned int*)(0x42A7A100UL))) +#define bM4_PORT_PCRE2_POUTE (*((volatile unsigned int*)(0x42A7A104UL))) +#define bM4_PORT_PCRE2_NOD (*((volatile unsigned int*)(0x42A7A108UL))) +#define bM4_PORT_PCRE2_DRV0 (*((volatile unsigned int*)(0x42A7A110UL))) +#define bM4_PORT_PCRE2_DRV1 (*((volatile unsigned int*)(0x42A7A114UL))) +#define bM4_PORT_PCRE2_PUU (*((volatile unsigned int*)(0x42A7A118UL))) +#define bM4_PORT_PCRE2_PIN (*((volatile unsigned int*)(0x42A7A120UL))) +#define bM4_PORT_PCRE2_INVE (*((volatile unsigned int*)(0x42A7A124UL))) +#define bM4_PORT_PCRE2_INTE (*((volatile unsigned int*)(0x42A7A130UL))) +#define bM4_PORT_PCRE2_LTE (*((volatile unsigned int*)(0x42A7A138UL))) +#define bM4_PORT_PCRE2_DDIS (*((volatile unsigned int*)(0x42A7A13CUL))) +#define bM4_PORT_PFSRE2_FSEL0 (*((volatile unsigned int*)(0x42A7A140UL))) +#define bM4_PORT_PFSRE2_FSEL1 (*((volatile unsigned int*)(0x42A7A144UL))) +#define bM4_PORT_PFSRE2_FSEL2 (*((volatile unsigned int*)(0x42A7A148UL))) +#define bM4_PORT_PFSRE2_FSEL3 (*((volatile unsigned int*)(0x42A7A14CUL))) +#define bM4_PORT_PFSRE2_FSEL4 (*((volatile unsigned int*)(0x42A7A150UL))) +#define bM4_PORT_PFSRE2_FSEL5 (*((volatile unsigned int*)(0x42A7A154UL))) +#define bM4_PORT_PFSRE2_BFE (*((volatile unsigned int*)(0x42A7A160UL))) +#define bM4_PORT_PCRE3_POUT (*((volatile unsigned int*)(0x42A7A180UL))) +#define bM4_PORT_PCRE3_POUTE (*((volatile unsigned int*)(0x42A7A184UL))) +#define bM4_PORT_PCRE3_NOD (*((volatile unsigned int*)(0x42A7A188UL))) +#define bM4_PORT_PCRE3_DRV0 (*((volatile unsigned int*)(0x42A7A190UL))) +#define bM4_PORT_PCRE3_DRV1 (*((volatile unsigned int*)(0x42A7A194UL))) +#define bM4_PORT_PCRE3_PUU (*((volatile unsigned int*)(0x42A7A198UL))) +#define bM4_PORT_PCRE3_PIN (*((volatile unsigned int*)(0x42A7A1A0UL))) +#define bM4_PORT_PCRE3_INVE (*((volatile unsigned int*)(0x42A7A1A4UL))) +#define bM4_PORT_PCRE3_INTE (*((volatile unsigned int*)(0x42A7A1B0UL))) +#define bM4_PORT_PCRE3_LTE (*((volatile unsigned int*)(0x42A7A1B8UL))) +#define bM4_PORT_PCRE3_DDIS (*((volatile unsigned int*)(0x42A7A1BCUL))) +#define bM4_PORT_PFSRE3_FSEL0 (*((volatile unsigned int*)(0x42A7A1C0UL))) +#define bM4_PORT_PFSRE3_FSEL1 (*((volatile unsigned int*)(0x42A7A1C4UL))) +#define bM4_PORT_PFSRE3_FSEL2 (*((volatile unsigned int*)(0x42A7A1C8UL))) +#define bM4_PORT_PFSRE3_FSEL3 (*((volatile unsigned int*)(0x42A7A1CCUL))) +#define bM4_PORT_PFSRE3_FSEL4 (*((volatile unsigned int*)(0x42A7A1D0UL))) +#define bM4_PORT_PFSRE3_FSEL5 (*((volatile unsigned int*)(0x42A7A1D4UL))) +#define bM4_PORT_PFSRE3_BFE (*((volatile unsigned int*)(0x42A7A1E0UL))) +#define bM4_PORT_PCRE4_POUT (*((volatile unsigned int*)(0x42A7A200UL))) +#define bM4_PORT_PCRE4_POUTE (*((volatile unsigned int*)(0x42A7A204UL))) +#define bM4_PORT_PCRE4_NOD (*((volatile unsigned int*)(0x42A7A208UL))) +#define bM4_PORT_PCRE4_DRV0 (*((volatile unsigned int*)(0x42A7A210UL))) +#define bM4_PORT_PCRE4_DRV1 (*((volatile unsigned int*)(0x42A7A214UL))) +#define bM4_PORT_PCRE4_PUU (*((volatile unsigned int*)(0x42A7A218UL))) +#define bM4_PORT_PCRE4_PIN (*((volatile unsigned int*)(0x42A7A220UL))) +#define bM4_PORT_PCRE4_INVE (*((volatile unsigned int*)(0x42A7A224UL))) +#define bM4_PORT_PCRE4_INTE (*((volatile unsigned int*)(0x42A7A230UL))) +#define bM4_PORT_PCRE4_LTE (*((volatile unsigned int*)(0x42A7A238UL))) +#define bM4_PORT_PCRE4_DDIS (*((volatile unsigned int*)(0x42A7A23CUL))) +#define bM4_PORT_PFSRE4_FSEL0 (*((volatile unsigned int*)(0x42A7A240UL))) +#define bM4_PORT_PFSRE4_FSEL1 (*((volatile unsigned int*)(0x42A7A244UL))) +#define bM4_PORT_PFSRE4_FSEL2 (*((volatile unsigned int*)(0x42A7A248UL))) +#define bM4_PORT_PFSRE4_FSEL3 (*((volatile unsigned int*)(0x42A7A24CUL))) +#define bM4_PORT_PFSRE4_FSEL4 (*((volatile unsigned int*)(0x42A7A250UL))) +#define bM4_PORT_PFSRE4_FSEL5 (*((volatile unsigned int*)(0x42A7A254UL))) +#define bM4_PORT_PFSRE4_BFE (*((volatile unsigned int*)(0x42A7A260UL))) +#define bM4_PORT_PCRE5_POUT (*((volatile unsigned int*)(0x42A7A280UL))) +#define bM4_PORT_PCRE5_POUTE (*((volatile unsigned int*)(0x42A7A284UL))) +#define bM4_PORT_PCRE5_NOD (*((volatile unsigned int*)(0x42A7A288UL))) +#define bM4_PORT_PCRE5_DRV0 (*((volatile unsigned int*)(0x42A7A290UL))) +#define bM4_PORT_PCRE5_DRV1 (*((volatile unsigned int*)(0x42A7A294UL))) +#define bM4_PORT_PCRE5_PUU (*((volatile unsigned int*)(0x42A7A298UL))) +#define bM4_PORT_PCRE5_PIN (*((volatile unsigned int*)(0x42A7A2A0UL))) +#define bM4_PORT_PCRE5_INVE (*((volatile unsigned int*)(0x42A7A2A4UL))) +#define bM4_PORT_PCRE5_INTE (*((volatile unsigned int*)(0x42A7A2B0UL))) +#define bM4_PORT_PCRE5_LTE (*((volatile unsigned int*)(0x42A7A2B8UL))) +#define bM4_PORT_PCRE5_DDIS (*((volatile unsigned int*)(0x42A7A2BCUL))) +#define bM4_PORT_PFSRE5_FSEL0 (*((volatile unsigned int*)(0x42A7A2C0UL))) +#define bM4_PORT_PFSRE5_FSEL1 (*((volatile unsigned int*)(0x42A7A2C4UL))) +#define bM4_PORT_PFSRE5_FSEL2 (*((volatile unsigned int*)(0x42A7A2C8UL))) +#define bM4_PORT_PFSRE5_FSEL3 (*((volatile unsigned int*)(0x42A7A2CCUL))) +#define bM4_PORT_PFSRE5_FSEL4 (*((volatile unsigned int*)(0x42A7A2D0UL))) +#define bM4_PORT_PFSRE5_FSEL5 (*((volatile unsigned int*)(0x42A7A2D4UL))) +#define bM4_PORT_PFSRE5_BFE (*((volatile unsigned int*)(0x42A7A2E0UL))) +#define bM4_PORT_PCRE6_POUT (*((volatile unsigned int*)(0x42A7A300UL))) +#define bM4_PORT_PCRE6_POUTE (*((volatile unsigned int*)(0x42A7A304UL))) +#define bM4_PORT_PCRE6_NOD (*((volatile unsigned int*)(0x42A7A308UL))) +#define bM4_PORT_PCRE6_DRV0 (*((volatile unsigned int*)(0x42A7A310UL))) +#define bM4_PORT_PCRE6_DRV1 (*((volatile unsigned int*)(0x42A7A314UL))) +#define bM4_PORT_PCRE6_PUU (*((volatile unsigned int*)(0x42A7A318UL))) +#define bM4_PORT_PCRE6_PIN (*((volatile unsigned int*)(0x42A7A320UL))) +#define bM4_PORT_PCRE6_INVE (*((volatile unsigned int*)(0x42A7A324UL))) +#define bM4_PORT_PCRE6_INTE (*((volatile unsigned int*)(0x42A7A330UL))) +#define bM4_PORT_PCRE6_LTE (*((volatile unsigned int*)(0x42A7A338UL))) +#define bM4_PORT_PCRE6_DDIS (*((volatile unsigned int*)(0x42A7A33CUL))) +#define bM4_PORT_PFSRE6_FSEL0 (*((volatile unsigned int*)(0x42A7A340UL))) +#define bM4_PORT_PFSRE6_FSEL1 (*((volatile unsigned int*)(0x42A7A344UL))) +#define bM4_PORT_PFSRE6_FSEL2 (*((volatile unsigned int*)(0x42A7A348UL))) +#define bM4_PORT_PFSRE6_FSEL3 (*((volatile unsigned int*)(0x42A7A34CUL))) +#define bM4_PORT_PFSRE6_FSEL4 (*((volatile unsigned int*)(0x42A7A350UL))) +#define bM4_PORT_PFSRE6_FSEL5 (*((volatile unsigned int*)(0x42A7A354UL))) +#define bM4_PORT_PFSRE6_BFE (*((volatile unsigned int*)(0x42A7A360UL))) +#define bM4_PORT_PCRE7_POUT (*((volatile unsigned int*)(0x42A7A380UL))) +#define bM4_PORT_PCRE7_POUTE (*((volatile unsigned int*)(0x42A7A384UL))) +#define bM4_PORT_PCRE7_NOD (*((volatile unsigned int*)(0x42A7A388UL))) +#define bM4_PORT_PCRE7_DRV0 (*((volatile unsigned int*)(0x42A7A390UL))) +#define bM4_PORT_PCRE7_DRV1 (*((volatile unsigned int*)(0x42A7A394UL))) +#define bM4_PORT_PCRE7_PUU (*((volatile unsigned int*)(0x42A7A398UL))) +#define bM4_PORT_PCRE7_PIN (*((volatile unsigned int*)(0x42A7A3A0UL))) +#define bM4_PORT_PCRE7_INVE (*((volatile unsigned int*)(0x42A7A3A4UL))) +#define bM4_PORT_PCRE7_INTE (*((volatile unsigned int*)(0x42A7A3B0UL))) +#define bM4_PORT_PCRE7_LTE (*((volatile unsigned int*)(0x42A7A3B8UL))) +#define bM4_PORT_PCRE7_DDIS (*((volatile unsigned int*)(0x42A7A3BCUL))) +#define bM4_PORT_PFSRE7_FSEL0 (*((volatile unsigned int*)(0x42A7A3C0UL))) +#define bM4_PORT_PFSRE7_FSEL1 (*((volatile unsigned int*)(0x42A7A3C4UL))) +#define bM4_PORT_PFSRE7_FSEL2 (*((volatile unsigned int*)(0x42A7A3C8UL))) +#define bM4_PORT_PFSRE7_FSEL3 (*((volatile unsigned int*)(0x42A7A3CCUL))) +#define bM4_PORT_PFSRE7_FSEL4 (*((volatile unsigned int*)(0x42A7A3D0UL))) +#define bM4_PORT_PFSRE7_FSEL5 (*((volatile unsigned int*)(0x42A7A3D4UL))) +#define bM4_PORT_PFSRE7_BFE (*((volatile unsigned int*)(0x42A7A3E0UL))) +#define bM4_PORT_PCRE8_POUT (*((volatile unsigned int*)(0x42A7A400UL))) +#define bM4_PORT_PCRE8_POUTE (*((volatile unsigned int*)(0x42A7A404UL))) +#define bM4_PORT_PCRE8_NOD (*((volatile unsigned int*)(0x42A7A408UL))) +#define bM4_PORT_PCRE8_DRV0 (*((volatile unsigned int*)(0x42A7A410UL))) +#define bM4_PORT_PCRE8_DRV1 (*((volatile unsigned int*)(0x42A7A414UL))) +#define bM4_PORT_PCRE8_PUU (*((volatile unsigned int*)(0x42A7A418UL))) +#define bM4_PORT_PCRE8_PIN (*((volatile unsigned int*)(0x42A7A420UL))) +#define bM4_PORT_PCRE8_INVE (*((volatile unsigned int*)(0x42A7A424UL))) +#define bM4_PORT_PCRE8_INTE (*((volatile unsigned int*)(0x42A7A430UL))) +#define bM4_PORT_PCRE8_LTE (*((volatile unsigned int*)(0x42A7A438UL))) +#define bM4_PORT_PCRE8_DDIS (*((volatile unsigned int*)(0x42A7A43CUL))) +#define bM4_PORT_PFSRE8_FSEL0 (*((volatile unsigned int*)(0x42A7A440UL))) +#define bM4_PORT_PFSRE8_FSEL1 (*((volatile unsigned int*)(0x42A7A444UL))) +#define bM4_PORT_PFSRE8_FSEL2 (*((volatile unsigned int*)(0x42A7A448UL))) +#define bM4_PORT_PFSRE8_FSEL3 (*((volatile unsigned int*)(0x42A7A44CUL))) +#define bM4_PORT_PFSRE8_FSEL4 (*((volatile unsigned int*)(0x42A7A450UL))) +#define bM4_PORT_PFSRE8_FSEL5 (*((volatile unsigned int*)(0x42A7A454UL))) +#define bM4_PORT_PFSRE8_BFE (*((volatile unsigned int*)(0x42A7A460UL))) +#define bM4_PORT_PCRE9_POUT (*((volatile unsigned int*)(0x42A7A480UL))) +#define bM4_PORT_PCRE9_POUTE (*((volatile unsigned int*)(0x42A7A484UL))) +#define bM4_PORT_PCRE9_NOD (*((volatile unsigned int*)(0x42A7A488UL))) +#define bM4_PORT_PCRE9_DRV0 (*((volatile unsigned int*)(0x42A7A490UL))) +#define bM4_PORT_PCRE9_DRV1 (*((volatile unsigned int*)(0x42A7A494UL))) +#define bM4_PORT_PCRE9_PUU (*((volatile unsigned int*)(0x42A7A498UL))) +#define bM4_PORT_PCRE9_PIN (*((volatile unsigned int*)(0x42A7A4A0UL))) +#define bM4_PORT_PCRE9_INVE (*((volatile unsigned int*)(0x42A7A4A4UL))) +#define bM4_PORT_PCRE9_INTE (*((volatile unsigned int*)(0x42A7A4B0UL))) +#define bM4_PORT_PCRE9_LTE (*((volatile unsigned int*)(0x42A7A4B8UL))) +#define bM4_PORT_PCRE9_DDIS (*((volatile unsigned int*)(0x42A7A4BCUL))) +#define bM4_PORT_PFSRE9_FSEL0 (*((volatile unsigned int*)(0x42A7A4C0UL))) +#define bM4_PORT_PFSRE9_FSEL1 (*((volatile unsigned int*)(0x42A7A4C4UL))) +#define bM4_PORT_PFSRE9_FSEL2 (*((volatile unsigned int*)(0x42A7A4C8UL))) +#define bM4_PORT_PFSRE9_FSEL3 (*((volatile unsigned int*)(0x42A7A4CCUL))) +#define bM4_PORT_PFSRE9_FSEL4 (*((volatile unsigned int*)(0x42A7A4D0UL))) +#define bM4_PORT_PFSRE9_FSEL5 (*((volatile unsigned int*)(0x42A7A4D4UL))) +#define bM4_PORT_PFSRE9_BFE (*((volatile unsigned int*)(0x42A7A4E0UL))) +#define bM4_PORT_PCRE10_POUT (*((volatile unsigned int*)(0x42A7A500UL))) +#define bM4_PORT_PCRE10_POUTE (*((volatile unsigned int*)(0x42A7A504UL))) +#define bM4_PORT_PCRE10_NOD (*((volatile unsigned int*)(0x42A7A508UL))) +#define bM4_PORT_PCRE10_DRV0 (*((volatile unsigned int*)(0x42A7A510UL))) +#define bM4_PORT_PCRE10_DRV1 (*((volatile unsigned int*)(0x42A7A514UL))) +#define bM4_PORT_PCRE10_PUU (*((volatile unsigned int*)(0x42A7A518UL))) +#define bM4_PORT_PCRE10_PIN (*((volatile unsigned int*)(0x42A7A520UL))) +#define bM4_PORT_PCRE10_INVE (*((volatile unsigned int*)(0x42A7A524UL))) +#define bM4_PORT_PCRE10_INTE (*((volatile unsigned int*)(0x42A7A530UL))) +#define bM4_PORT_PCRE10_LTE (*((volatile unsigned int*)(0x42A7A538UL))) +#define bM4_PORT_PCRE10_DDIS (*((volatile unsigned int*)(0x42A7A53CUL))) +#define bM4_PORT_PFSRE10_FSEL0 (*((volatile unsigned int*)(0x42A7A540UL))) +#define bM4_PORT_PFSRE10_FSEL1 (*((volatile unsigned int*)(0x42A7A544UL))) +#define bM4_PORT_PFSRE10_FSEL2 (*((volatile unsigned int*)(0x42A7A548UL))) +#define bM4_PORT_PFSRE10_FSEL3 (*((volatile unsigned int*)(0x42A7A54CUL))) +#define bM4_PORT_PFSRE10_FSEL4 (*((volatile unsigned int*)(0x42A7A550UL))) +#define bM4_PORT_PFSRE10_FSEL5 (*((volatile unsigned int*)(0x42A7A554UL))) +#define bM4_PORT_PFSRE10_BFE (*((volatile unsigned int*)(0x42A7A560UL))) +#define bM4_PORT_PCRE11_POUT (*((volatile unsigned int*)(0x42A7A580UL))) +#define bM4_PORT_PCRE11_POUTE (*((volatile unsigned int*)(0x42A7A584UL))) +#define bM4_PORT_PCRE11_NOD (*((volatile unsigned int*)(0x42A7A588UL))) +#define bM4_PORT_PCRE11_DRV0 (*((volatile unsigned int*)(0x42A7A590UL))) +#define bM4_PORT_PCRE11_DRV1 (*((volatile unsigned int*)(0x42A7A594UL))) +#define bM4_PORT_PCRE11_PUU (*((volatile unsigned int*)(0x42A7A598UL))) +#define bM4_PORT_PCRE11_PIN (*((volatile unsigned int*)(0x42A7A5A0UL))) +#define bM4_PORT_PCRE11_INVE (*((volatile unsigned int*)(0x42A7A5A4UL))) +#define bM4_PORT_PCRE11_INTE (*((volatile unsigned int*)(0x42A7A5B0UL))) +#define bM4_PORT_PCRE11_LTE (*((volatile unsigned int*)(0x42A7A5B8UL))) +#define bM4_PORT_PCRE11_DDIS (*((volatile unsigned int*)(0x42A7A5BCUL))) +#define bM4_PORT_PFSRE11_FSEL0 (*((volatile unsigned int*)(0x42A7A5C0UL))) +#define bM4_PORT_PFSRE11_FSEL1 (*((volatile unsigned int*)(0x42A7A5C4UL))) +#define bM4_PORT_PFSRE11_FSEL2 (*((volatile unsigned int*)(0x42A7A5C8UL))) +#define bM4_PORT_PFSRE11_FSEL3 (*((volatile unsigned int*)(0x42A7A5CCUL))) +#define bM4_PORT_PFSRE11_FSEL4 (*((volatile unsigned int*)(0x42A7A5D0UL))) +#define bM4_PORT_PFSRE11_FSEL5 (*((volatile unsigned int*)(0x42A7A5D4UL))) +#define bM4_PORT_PFSRE11_BFE (*((volatile unsigned int*)(0x42A7A5E0UL))) +#define bM4_PORT_PCRE12_POUT (*((volatile unsigned int*)(0x42A7A600UL))) +#define bM4_PORT_PCRE12_POUTE (*((volatile unsigned int*)(0x42A7A604UL))) +#define bM4_PORT_PCRE12_NOD (*((volatile unsigned int*)(0x42A7A608UL))) +#define bM4_PORT_PCRE12_DRV0 (*((volatile unsigned int*)(0x42A7A610UL))) +#define bM4_PORT_PCRE12_DRV1 (*((volatile unsigned int*)(0x42A7A614UL))) +#define bM4_PORT_PCRE12_PUU (*((volatile unsigned int*)(0x42A7A618UL))) +#define bM4_PORT_PCRE12_PIN (*((volatile unsigned int*)(0x42A7A620UL))) +#define bM4_PORT_PCRE12_INVE (*((volatile unsigned int*)(0x42A7A624UL))) +#define bM4_PORT_PCRE12_INTE (*((volatile unsigned int*)(0x42A7A630UL))) +#define bM4_PORT_PCRE12_LTE (*((volatile unsigned int*)(0x42A7A638UL))) +#define bM4_PORT_PCRE12_DDIS (*((volatile unsigned int*)(0x42A7A63CUL))) +#define bM4_PORT_PFSRE12_FSEL0 (*((volatile unsigned int*)(0x42A7A640UL))) +#define bM4_PORT_PFSRE12_FSEL1 (*((volatile unsigned int*)(0x42A7A644UL))) +#define bM4_PORT_PFSRE12_FSEL2 (*((volatile unsigned int*)(0x42A7A648UL))) +#define bM4_PORT_PFSRE12_FSEL3 (*((volatile unsigned int*)(0x42A7A64CUL))) +#define bM4_PORT_PFSRE12_FSEL4 (*((volatile unsigned int*)(0x42A7A650UL))) +#define bM4_PORT_PFSRE12_FSEL5 (*((volatile unsigned int*)(0x42A7A654UL))) +#define bM4_PORT_PFSRE12_BFE (*((volatile unsigned int*)(0x42A7A660UL))) +#define bM4_PORT_PCRE13_POUT (*((volatile unsigned int*)(0x42A7A680UL))) +#define bM4_PORT_PCRE13_POUTE (*((volatile unsigned int*)(0x42A7A684UL))) +#define bM4_PORT_PCRE13_NOD (*((volatile unsigned int*)(0x42A7A688UL))) +#define bM4_PORT_PCRE13_DRV0 (*((volatile unsigned int*)(0x42A7A690UL))) +#define bM4_PORT_PCRE13_DRV1 (*((volatile unsigned int*)(0x42A7A694UL))) +#define bM4_PORT_PCRE13_PUU (*((volatile unsigned int*)(0x42A7A698UL))) +#define bM4_PORT_PCRE13_PIN (*((volatile unsigned int*)(0x42A7A6A0UL))) +#define bM4_PORT_PCRE13_INVE (*((volatile unsigned int*)(0x42A7A6A4UL))) +#define bM4_PORT_PCRE13_INTE (*((volatile unsigned int*)(0x42A7A6B0UL))) +#define bM4_PORT_PCRE13_LTE (*((volatile unsigned int*)(0x42A7A6B8UL))) +#define bM4_PORT_PCRE13_DDIS (*((volatile unsigned int*)(0x42A7A6BCUL))) +#define bM4_PORT_PFSRE13_FSEL0 (*((volatile unsigned int*)(0x42A7A6C0UL))) +#define bM4_PORT_PFSRE13_FSEL1 (*((volatile unsigned int*)(0x42A7A6C4UL))) +#define bM4_PORT_PFSRE13_FSEL2 (*((volatile unsigned int*)(0x42A7A6C8UL))) +#define bM4_PORT_PFSRE13_FSEL3 (*((volatile unsigned int*)(0x42A7A6CCUL))) +#define bM4_PORT_PFSRE13_FSEL4 (*((volatile unsigned int*)(0x42A7A6D0UL))) +#define bM4_PORT_PFSRE13_FSEL5 (*((volatile unsigned int*)(0x42A7A6D4UL))) +#define bM4_PORT_PFSRE13_BFE (*((volatile unsigned int*)(0x42A7A6E0UL))) +#define bM4_PORT_PCRE14_POUT (*((volatile unsigned int*)(0x42A7A700UL))) +#define bM4_PORT_PCRE14_POUTE (*((volatile unsigned int*)(0x42A7A704UL))) +#define bM4_PORT_PCRE14_NOD (*((volatile unsigned int*)(0x42A7A708UL))) +#define bM4_PORT_PCRE14_DRV0 (*((volatile unsigned int*)(0x42A7A710UL))) +#define bM4_PORT_PCRE14_DRV1 (*((volatile unsigned int*)(0x42A7A714UL))) +#define bM4_PORT_PCRE14_PUU (*((volatile unsigned int*)(0x42A7A718UL))) +#define bM4_PORT_PCRE14_PIN (*((volatile unsigned int*)(0x42A7A720UL))) +#define bM4_PORT_PCRE14_INVE (*((volatile unsigned int*)(0x42A7A724UL))) +#define bM4_PORT_PCRE14_INTE (*((volatile unsigned int*)(0x42A7A730UL))) +#define bM4_PORT_PCRE14_LTE (*((volatile unsigned int*)(0x42A7A738UL))) +#define bM4_PORT_PCRE14_DDIS (*((volatile unsigned int*)(0x42A7A73CUL))) +#define bM4_PORT_PFSRE14_FSEL0 (*((volatile unsigned int*)(0x42A7A740UL))) +#define bM4_PORT_PFSRE14_FSEL1 (*((volatile unsigned int*)(0x42A7A744UL))) +#define bM4_PORT_PFSRE14_FSEL2 (*((volatile unsigned int*)(0x42A7A748UL))) +#define bM4_PORT_PFSRE14_FSEL3 (*((volatile unsigned int*)(0x42A7A74CUL))) +#define bM4_PORT_PFSRE14_FSEL4 (*((volatile unsigned int*)(0x42A7A750UL))) +#define bM4_PORT_PFSRE14_FSEL5 (*((volatile unsigned int*)(0x42A7A754UL))) +#define bM4_PORT_PFSRE14_BFE (*((volatile unsigned int*)(0x42A7A760UL))) +#define bM4_PORT_PCRE15_POUT (*((volatile unsigned int*)(0x42A7A780UL))) +#define bM4_PORT_PCRE15_POUTE (*((volatile unsigned int*)(0x42A7A784UL))) +#define bM4_PORT_PCRE15_NOD (*((volatile unsigned int*)(0x42A7A788UL))) +#define bM4_PORT_PCRE15_DRV0 (*((volatile unsigned int*)(0x42A7A790UL))) +#define bM4_PORT_PCRE15_DRV1 (*((volatile unsigned int*)(0x42A7A794UL))) +#define bM4_PORT_PCRE15_PUU (*((volatile unsigned int*)(0x42A7A798UL))) +#define bM4_PORT_PCRE15_PIN (*((volatile unsigned int*)(0x42A7A7A0UL))) +#define bM4_PORT_PCRE15_INVE (*((volatile unsigned int*)(0x42A7A7A4UL))) +#define bM4_PORT_PCRE15_INTE (*((volatile unsigned int*)(0x42A7A7B0UL))) +#define bM4_PORT_PCRE15_LTE (*((volatile unsigned int*)(0x42A7A7B8UL))) +#define bM4_PORT_PCRE15_DDIS (*((volatile unsigned int*)(0x42A7A7BCUL))) +#define bM4_PORT_PFSRE15_FSEL0 (*((volatile unsigned int*)(0x42A7A7C0UL))) +#define bM4_PORT_PFSRE15_FSEL1 (*((volatile unsigned int*)(0x42A7A7C4UL))) +#define bM4_PORT_PFSRE15_FSEL2 (*((volatile unsigned int*)(0x42A7A7C8UL))) +#define bM4_PORT_PFSRE15_FSEL3 (*((volatile unsigned int*)(0x42A7A7CCUL))) +#define bM4_PORT_PFSRE15_FSEL4 (*((volatile unsigned int*)(0x42A7A7D0UL))) +#define bM4_PORT_PFSRE15_FSEL5 (*((volatile unsigned int*)(0x42A7A7D4UL))) +#define bM4_PORT_PFSRE15_BFE (*((volatile unsigned int*)(0x42A7A7E0UL))) +#define bM4_PORT_PCRH0_POUT (*((volatile unsigned int*)(0x42A7A800UL))) +#define bM4_PORT_PCRH0_POUTE (*((volatile unsigned int*)(0x42A7A804UL))) +#define bM4_PORT_PCRH0_NOD (*((volatile unsigned int*)(0x42A7A808UL))) +#define bM4_PORT_PCRH0_DRV0 (*((volatile unsigned int*)(0x42A7A810UL))) +#define bM4_PORT_PCRH0_DRV1 (*((volatile unsigned int*)(0x42A7A814UL))) +#define bM4_PORT_PCRH0_PUU (*((volatile unsigned int*)(0x42A7A818UL))) +#define bM4_PORT_PCRH0_PIN (*((volatile unsigned int*)(0x42A7A820UL))) +#define bM4_PORT_PCRH0_INVE (*((volatile unsigned int*)(0x42A7A824UL))) +#define bM4_PORT_PCRH0_INTE (*((volatile unsigned int*)(0x42A7A830UL))) +#define bM4_PORT_PCRH0_LTE (*((volatile unsigned int*)(0x42A7A838UL))) +#define bM4_PORT_PCRH0_DDIS (*((volatile unsigned int*)(0x42A7A83CUL))) +#define bM4_PORT_PFSRH0_FSEL0 (*((volatile unsigned int*)(0x42A7A840UL))) +#define bM4_PORT_PFSRH0_FSEL1 (*((volatile unsigned int*)(0x42A7A844UL))) +#define bM4_PORT_PFSRH0_FSEL2 (*((volatile unsigned int*)(0x42A7A848UL))) +#define bM4_PORT_PFSRH0_FSEL3 (*((volatile unsigned int*)(0x42A7A84CUL))) +#define bM4_PORT_PFSRH0_FSEL4 (*((volatile unsigned int*)(0x42A7A850UL))) +#define bM4_PORT_PFSRH0_FSEL5 (*((volatile unsigned int*)(0x42A7A854UL))) +#define bM4_PORT_PFSRH0_BFE (*((volatile unsigned int*)(0x42A7A860UL))) +#define bM4_PORT_PCRH1_POUT (*((volatile unsigned int*)(0x42A7A880UL))) +#define bM4_PORT_PCRH1_POUTE (*((volatile unsigned int*)(0x42A7A884UL))) +#define bM4_PORT_PCRH1_NOD (*((volatile unsigned int*)(0x42A7A888UL))) +#define bM4_PORT_PCRH1_DRV0 (*((volatile unsigned int*)(0x42A7A890UL))) +#define bM4_PORT_PCRH1_DRV1 (*((volatile unsigned int*)(0x42A7A894UL))) +#define bM4_PORT_PCRH1_PUU (*((volatile unsigned int*)(0x42A7A898UL))) +#define bM4_PORT_PCRH1_PIN (*((volatile unsigned int*)(0x42A7A8A0UL))) +#define bM4_PORT_PCRH1_INVE (*((volatile unsigned int*)(0x42A7A8A4UL))) +#define bM4_PORT_PCRH1_INTE (*((volatile unsigned int*)(0x42A7A8B0UL))) +#define bM4_PORT_PCRH1_LTE (*((volatile unsigned int*)(0x42A7A8B8UL))) +#define bM4_PORT_PCRH1_DDIS (*((volatile unsigned int*)(0x42A7A8BCUL))) +#define bM4_PORT_PFSRH1_FSEL0 (*((volatile unsigned int*)(0x42A7A8C0UL))) +#define bM4_PORT_PFSRH1_FSEL1 (*((volatile unsigned int*)(0x42A7A8C4UL))) +#define bM4_PORT_PFSRH1_FSEL2 (*((volatile unsigned int*)(0x42A7A8C8UL))) +#define bM4_PORT_PFSRH1_FSEL3 (*((volatile unsigned int*)(0x42A7A8CCUL))) +#define bM4_PORT_PFSRH1_FSEL4 (*((volatile unsigned int*)(0x42A7A8D0UL))) +#define bM4_PORT_PFSRH1_FSEL5 (*((volatile unsigned int*)(0x42A7A8D4UL))) +#define bM4_PORT_PFSRH1_BFE (*((volatile unsigned int*)(0x42A7A8E0UL))) +#define bM4_PORT_PCRH2_POUT (*((volatile unsigned int*)(0x42A7A900UL))) +#define bM4_PORT_PCRH2_POUTE (*((volatile unsigned int*)(0x42A7A904UL))) +#define bM4_PORT_PCRH2_NOD (*((volatile unsigned int*)(0x42A7A908UL))) +#define bM4_PORT_PCRH2_DRV0 (*((volatile unsigned int*)(0x42A7A910UL))) +#define bM4_PORT_PCRH2_DRV1 (*((volatile unsigned int*)(0x42A7A914UL))) +#define bM4_PORT_PCRH2_PUU (*((volatile unsigned int*)(0x42A7A918UL))) +#define bM4_PORT_PCRH2_PIN (*((volatile unsigned int*)(0x42A7A920UL))) +#define bM4_PORT_PCRH2_INVE (*((volatile unsigned int*)(0x42A7A924UL))) +#define bM4_PORT_PCRH2_INTE (*((volatile unsigned int*)(0x42A7A930UL))) +#define bM4_PORT_PCRH2_LTE (*((volatile unsigned int*)(0x42A7A938UL))) +#define bM4_PORT_PCRH2_DDIS (*((volatile unsigned int*)(0x42A7A93CUL))) +#define bM4_PORT_PFSRH2_FSEL0 (*((volatile unsigned int*)(0x42A7A940UL))) +#define bM4_PORT_PFSRH2_FSEL1 (*((volatile unsigned int*)(0x42A7A944UL))) +#define bM4_PORT_PFSRH2_FSEL2 (*((volatile unsigned int*)(0x42A7A948UL))) +#define bM4_PORT_PFSRH2_FSEL3 (*((volatile unsigned int*)(0x42A7A94CUL))) +#define bM4_PORT_PFSRH2_FSEL4 (*((volatile unsigned int*)(0x42A7A950UL))) +#define bM4_PORT_PFSRH2_FSEL5 (*((volatile unsigned int*)(0x42A7A954UL))) +#define bM4_PORT_PFSRH2_BFE (*((volatile unsigned int*)(0x42A7A960UL))) +#define bM4_RTC_CR0_RESET (*((volatile unsigned int*)(0x42980000UL))) +#define bM4_RTC_CR1_PRDS0 (*((volatile unsigned int*)(0x42980080UL))) +#define bM4_RTC_CR1_PRDS1 (*((volatile unsigned int*)(0x42980084UL))) +#define bM4_RTC_CR1_PRDS2 (*((volatile unsigned int*)(0x42980088UL))) +#define bM4_RTC_CR1_AMPM (*((volatile unsigned int*)(0x4298008CUL))) +#define bM4_RTC_CR1_ALMFCLR (*((volatile unsigned int*)(0x42980090UL))) +#define bM4_RTC_CR1_ONEHZOE (*((volatile unsigned int*)(0x42980094UL))) +#define bM4_RTC_CR1_ONEHZSEL (*((volatile unsigned int*)(0x42980098UL))) +#define bM4_RTC_CR1_START (*((volatile unsigned int*)(0x4298009CUL))) +#define bM4_RTC_CR2_RWREQ (*((volatile unsigned int*)(0x42980100UL))) +#define bM4_RTC_CR2_RWEN (*((volatile unsigned int*)(0x42980104UL))) +#define bM4_RTC_CR2_ALMF (*((volatile unsigned int*)(0x4298010CUL))) +#define bM4_RTC_CR2_PRDIE (*((volatile unsigned int*)(0x42980114UL))) +#define bM4_RTC_CR2_ALMIE (*((volatile unsigned int*)(0x42980118UL))) +#define bM4_RTC_CR2_ALME (*((volatile unsigned int*)(0x4298011CUL))) +#define bM4_RTC_CR3_LRCEN (*((volatile unsigned int*)(0x42980190UL))) +#define bM4_RTC_CR3_RCKSEL (*((volatile unsigned int*)(0x4298019CUL))) +#define bM4_RTC_SEC_SECU0 (*((volatile unsigned int*)(0x42980200UL))) +#define bM4_RTC_SEC_SECU1 (*((volatile unsigned int*)(0x42980204UL))) +#define bM4_RTC_SEC_SECU2 (*((volatile unsigned int*)(0x42980208UL))) +#define bM4_RTC_SEC_SECU3 (*((volatile unsigned int*)(0x4298020CUL))) +#define bM4_RTC_SEC_SECD0 (*((volatile unsigned int*)(0x42980210UL))) +#define bM4_RTC_SEC_SECD1 (*((volatile unsigned int*)(0x42980214UL))) +#define bM4_RTC_SEC_SECD2 (*((volatile unsigned int*)(0x42980218UL))) +#define bM4_RTC_MIN_MINU0 (*((volatile unsigned int*)(0x42980280UL))) +#define bM4_RTC_MIN_MINU1 (*((volatile unsigned int*)(0x42980284UL))) +#define bM4_RTC_MIN_MINU2 (*((volatile unsigned int*)(0x42980288UL))) +#define bM4_RTC_MIN_MINU3 (*((volatile unsigned int*)(0x4298028CUL))) +#define bM4_RTC_MIN_MIND0 (*((volatile unsigned int*)(0x42980290UL))) +#define bM4_RTC_MIN_MIND1 (*((volatile unsigned int*)(0x42980294UL))) +#define bM4_RTC_MIN_MIND2 (*((volatile unsigned int*)(0x42980298UL))) +#define bM4_RTC_HOUR_HOURU0 (*((volatile unsigned int*)(0x42980300UL))) +#define bM4_RTC_HOUR_HOURU1 (*((volatile unsigned int*)(0x42980304UL))) +#define bM4_RTC_HOUR_HOURU2 (*((volatile unsigned int*)(0x42980308UL))) +#define bM4_RTC_HOUR_HOURU3 (*((volatile unsigned int*)(0x4298030CUL))) +#define bM4_RTC_HOUR_HOURD0 (*((volatile unsigned int*)(0x42980310UL))) +#define bM4_RTC_HOUR_HOURD1 (*((volatile unsigned int*)(0x42980314UL))) +#define bM4_RTC_WEEK_WEEK0 (*((volatile unsigned int*)(0x42980380UL))) +#define bM4_RTC_WEEK_WEEK1 (*((volatile unsigned int*)(0x42980384UL))) +#define bM4_RTC_WEEK_WEEK2 (*((volatile unsigned int*)(0x42980388UL))) +#define bM4_RTC_DAY_DAYU0 (*((volatile unsigned int*)(0x42980400UL))) +#define bM4_RTC_DAY_DAYU1 (*((volatile unsigned int*)(0x42980404UL))) +#define bM4_RTC_DAY_DAYU2 (*((volatile unsigned int*)(0x42980408UL))) +#define bM4_RTC_DAY_DAYU3 (*((volatile unsigned int*)(0x4298040CUL))) +#define bM4_RTC_DAY_DAYD0 (*((volatile unsigned int*)(0x42980410UL))) +#define bM4_RTC_DAY_DAYD1 (*((volatile unsigned int*)(0x42980414UL))) +#define bM4_RTC_MON_MON0 (*((volatile unsigned int*)(0x42980480UL))) +#define bM4_RTC_MON_MON1 (*((volatile unsigned int*)(0x42980484UL))) +#define bM4_RTC_MON_MON2 (*((volatile unsigned int*)(0x42980488UL))) +#define bM4_RTC_MON_MON3 (*((volatile unsigned int*)(0x4298048CUL))) +#define bM4_RTC_MON_MON4 (*((volatile unsigned int*)(0x42980490UL))) +#define bM4_RTC_YEAR_YEARU0 (*((volatile unsigned int*)(0x42980500UL))) +#define bM4_RTC_YEAR_YEARU1 (*((volatile unsigned int*)(0x42980504UL))) +#define bM4_RTC_YEAR_YEARU2 (*((volatile unsigned int*)(0x42980508UL))) +#define bM4_RTC_YEAR_YEARU3 (*((volatile unsigned int*)(0x4298050CUL))) +#define bM4_RTC_YEAR_YEARD0 (*((volatile unsigned int*)(0x42980510UL))) +#define bM4_RTC_YEAR_YEARD1 (*((volatile unsigned int*)(0x42980514UL))) +#define bM4_RTC_YEAR_YEARD2 (*((volatile unsigned int*)(0x42980518UL))) +#define bM4_RTC_YEAR_YEARD3 (*((volatile unsigned int*)(0x4298051CUL))) +#define bM4_RTC_ALMMIN_ALMMINU0 (*((volatile unsigned int*)(0x42980580UL))) +#define bM4_RTC_ALMMIN_ALMMINU1 (*((volatile unsigned int*)(0x42980584UL))) +#define bM4_RTC_ALMMIN_ALMMINU2 (*((volatile unsigned int*)(0x42980588UL))) +#define bM4_RTC_ALMMIN_ALMMINU3 (*((volatile unsigned int*)(0x4298058CUL))) +#define bM4_RTC_ALMMIN_ALMMIND0 (*((volatile unsigned int*)(0x42980590UL))) +#define bM4_RTC_ALMMIN_ALMMIND1 (*((volatile unsigned int*)(0x42980594UL))) +#define bM4_RTC_ALMMIN_ALMMIND2 (*((volatile unsigned int*)(0x42980598UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU0 (*((volatile unsigned int*)(0x42980600UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU1 (*((volatile unsigned int*)(0x42980604UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU2 (*((volatile unsigned int*)(0x42980608UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU3 (*((volatile unsigned int*)(0x4298060CUL))) +#define bM4_RTC_ALMHOUR_ALMHOURD0 (*((volatile unsigned int*)(0x42980610UL))) +#define bM4_RTC_ALMHOUR_ALMHOURD1 (*((volatile unsigned int*)(0x42980614UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK0 (*((volatile unsigned int*)(0x42980680UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK1 (*((volatile unsigned int*)(0x42980684UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK2 (*((volatile unsigned int*)(0x42980688UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK3 (*((volatile unsigned int*)(0x4298068CUL))) +#define bM4_RTC_ALMWEEK_ALMWEEK4 (*((volatile unsigned int*)(0x42980690UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK5 (*((volatile unsigned int*)(0x42980694UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK6 (*((volatile unsigned int*)(0x42980698UL))) +#define bM4_RTC_ERRCRH_COMP8 (*((volatile unsigned int*)(0x42980700UL))) +#define bM4_RTC_ERRCRH_COMPEN (*((volatile unsigned int*)(0x4298071CUL))) +#define bM4_RTC_ERRCRL_COMP0 (*((volatile unsigned int*)(0x42980780UL))) +#define bM4_RTC_ERRCRL_COMP1 (*((volatile unsigned int*)(0x42980784UL))) +#define bM4_RTC_ERRCRL_COMP2 (*((volatile unsigned int*)(0x42980788UL))) +#define bM4_RTC_ERRCRL_COMP3 (*((volatile unsigned int*)(0x4298078CUL))) +#define bM4_RTC_ERRCRL_COMP4 (*((volatile unsigned int*)(0x42980790UL))) +#define bM4_RTC_ERRCRL_COMP5 (*((volatile unsigned int*)(0x42980794UL))) +#define bM4_RTC_ERRCRL_COMP6 (*((volatile unsigned int*)(0x42980798UL))) +#define bM4_RTC_ERRCRL_COMP7 (*((volatile unsigned int*)(0x4298079CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42DF8080UL))) +#define bM4_SDIOC1_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42DF8084UL))) +#define bM4_SDIOC1_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42DF8088UL))) +#define bM4_SDIOC1_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42DF808CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42DF8090UL))) +#define bM4_SDIOC1_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42DF8094UL))) +#define bM4_SDIOC1_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42DF8098UL))) +#define bM4_SDIOC1_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42DF809CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42DF80A0UL))) +#define bM4_SDIOC1_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42DF80A4UL))) +#define bM4_SDIOC1_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42DF80A8UL))) +#define bM4_SDIOC1_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42DF80ACUL))) +#define bM4_SDIOC1_TRANSMODE_BCE (*((volatile unsigned int*)(0x42DF8184UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42DF8188UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42DF818CUL))) +#define bM4_SDIOC1_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42DF8190UL))) +#define bM4_SDIOC1_TRANSMODE_MULB (*((volatile unsigned int*)(0x42DF8194UL))) +#define bM4_SDIOC1_CMD_RESTYP0 (*((volatile unsigned int*)(0x42DF81C0UL))) +#define bM4_SDIOC1_CMD_RESTYP1 (*((volatile unsigned int*)(0x42DF81C4UL))) +#define bM4_SDIOC1_CMD_CCE (*((volatile unsigned int*)(0x42DF81CCUL))) +#define bM4_SDIOC1_CMD_ICE (*((volatile unsigned int*)(0x42DF81D0UL))) +#define bM4_SDIOC1_CMD_DAT (*((volatile unsigned int*)(0x42DF81D4UL))) +#define bM4_SDIOC1_CMD_TYP0 (*((volatile unsigned int*)(0x42DF81D8UL))) +#define bM4_SDIOC1_CMD_TYP1 (*((volatile unsigned int*)(0x42DF81DCUL))) +#define bM4_SDIOC1_CMD_IDX0 (*((volatile unsigned int*)(0x42DF81E0UL))) +#define bM4_SDIOC1_CMD_IDX1 (*((volatile unsigned int*)(0x42DF81E4UL))) +#define bM4_SDIOC1_CMD_IDX2 (*((volatile unsigned int*)(0x42DF81E8UL))) +#define bM4_SDIOC1_CMD_IDX3 (*((volatile unsigned int*)(0x42DF81ECUL))) +#define bM4_SDIOC1_CMD_IDX4 (*((volatile unsigned int*)(0x42DF81F0UL))) +#define bM4_SDIOC1_CMD_IDX5 (*((volatile unsigned int*)(0x42DF81F4UL))) +#define bM4_SDIOC1_PSTAT_CIC (*((volatile unsigned int*)(0x42DF8480UL))) +#define bM4_SDIOC1_PSTAT_CID (*((volatile unsigned int*)(0x42DF8484UL))) +#define bM4_SDIOC1_PSTAT_DA (*((volatile unsigned int*)(0x42DF8488UL))) +#define bM4_SDIOC1_PSTAT_WTA (*((volatile unsigned int*)(0x42DF84A0UL))) +#define bM4_SDIOC1_PSTAT_RTA (*((volatile unsigned int*)(0x42DF84A4UL))) +#define bM4_SDIOC1_PSTAT_BWE (*((volatile unsigned int*)(0x42DF84A8UL))) +#define bM4_SDIOC1_PSTAT_BRE (*((volatile unsigned int*)(0x42DF84ACUL))) +#define bM4_SDIOC1_PSTAT_CIN (*((volatile unsigned int*)(0x42DF84C0UL))) +#define bM4_SDIOC1_PSTAT_CSS (*((volatile unsigned int*)(0x42DF84C4UL))) +#define bM4_SDIOC1_PSTAT_CDL (*((volatile unsigned int*)(0x42DF84C8UL))) +#define bM4_SDIOC1_PSTAT_WPL (*((volatile unsigned int*)(0x42DF84CCUL))) +#define bM4_SDIOC1_PSTAT_DATL0 (*((volatile unsigned int*)(0x42DF84D0UL))) +#define bM4_SDIOC1_PSTAT_DATL1 (*((volatile unsigned int*)(0x42DF84D4UL))) +#define bM4_SDIOC1_PSTAT_DATL2 (*((volatile unsigned int*)(0x42DF84D8UL))) +#define bM4_SDIOC1_PSTAT_DATL3 (*((volatile unsigned int*)(0x42DF84DCUL))) +#define bM4_SDIOC1_PSTAT_CMDL (*((volatile unsigned int*)(0x42DF84E0UL))) +#define bM4_SDIOC1_HOSTCON_DW (*((volatile unsigned int*)(0x42DF8504UL))) +#define bM4_SDIOC1_HOSTCON_HSEN (*((volatile unsigned int*)(0x42DF8508UL))) +#define bM4_SDIOC1_HOSTCON_EXDW (*((volatile unsigned int*)(0x42DF8514UL))) +#define bM4_SDIOC1_HOSTCON_CDTL (*((volatile unsigned int*)(0x42DF8518UL))) +#define bM4_SDIOC1_HOSTCON_CDSS (*((volatile unsigned int*)(0x42DF851CUL))) +#define bM4_SDIOC1_PWRCON_PWON (*((volatile unsigned int*)(0x42DF8520UL))) +#define bM4_SDIOC1_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42DF8540UL))) +#define bM4_SDIOC1_BLKGPCON_CR (*((volatile unsigned int*)(0x42DF8544UL))) +#define bM4_SDIOC1_BLKGPCON_RWC (*((volatile unsigned int*)(0x42DF8548UL))) +#define bM4_SDIOC1_BLKGPCON_IABG (*((volatile unsigned int*)(0x42DF854CUL))) +#define bM4_SDIOC1_CLKCON_ICE (*((volatile unsigned int*)(0x42DF8580UL))) +#define bM4_SDIOC1_CLKCON_CE (*((volatile unsigned int*)(0x42DF8588UL))) +#define bM4_SDIOC1_CLKCON_FS0 (*((volatile unsigned int*)(0x42DF85A0UL))) +#define bM4_SDIOC1_CLKCON_FS1 (*((volatile unsigned int*)(0x42DF85A4UL))) +#define bM4_SDIOC1_CLKCON_FS2 (*((volatile unsigned int*)(0x42DF85A8UL))) +#define bM4_SDIOC1_CLKCON_FS3 (*((volatile unsigned int*)(0x42DF85ACUL))) +#define bM4_SDIOC1_CLKCON_FS4 (*((volatile unsigned int*)(0x42DF85B0UL))) +#define bM4_SDIOC1_CLKCON_FS5 (*((volatile unsigned int*)(0x42DF85B4UL))) +#define bM4_SDIOC1_CLKCON_FS6 (*((volatile unsigned int*)(0x42DF85B8UL))) +#define bM4_SDIOC1_CLKCON_FS7 (*((volatile unsigned int*)(0x42DF85BCUL))) +#define bM4_SDIOC1_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42DF85C0UL))) +#define bM4_SDIOC1_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42DF85C4UL))) +#define bM4_SDIOC1_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42DF85C8UL))) +#define bM4_SDIOC1_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42DF85CCUL))) +#define bM4_SDIOC1_SFTRST_RSTA (*((volatile unsigned int*)(0x42DF85E0UL))) +#define bM4_SDIOC1_SFTRST_RSTC (*((volatile unsigned int*)(0x42DF85E4UL))) +#define bM4_SDIOC1_SFTRST_RSTD (*((volatile unsigned int*)(0x42DF85E8UL))) +#define bM4_SDIOC1_NORINTST_CC (*((volatile unsigned int*)(0x42DF8600UL))) +#define bM4_SDIOC1_NORINTST_TC (*((volatile unsigned int*)(0x42DF8604UL))) +#define bM4_SDIOC1_NORINTST_BGE (*((volatile unsigned int*)(0x42DF8608UL))) +#define bM4_SDIOC1_NORINTST_BWR (*((volatile unsigned int*)(0x42DF8610UL))) +#define bM4_SDIOC1_NORINTST_BRR (*((volatile unsigned int*)(0x42DF8614UL))) +#define bM4_SDIOC1_NORINTST_CIST (*((volatile unsigned int*)(0x42DF8618UL))) +#define bM4_SDIOC1_NORINTST_CRM (*((volatile unsigned int*)(0x42DF861CUL))) +#define bM4_SDIOC1_NORINTST_CINT (*((volatile unsigned int*)(0x42DF8620UL))) +#define bM4_SDIOC1_NORINTST_EI (*((volatile unsigned int*)(0x42DF863CUL))) +#define bM4_SDIOC1_ERRINTST_CTOE (*((volatile unsigned int*)(0x42DF8640UL))) +#define bM4_SDIOC1_ERRINTST_CCE (*((volatile unsigned int*)(0x42DF8644UL))) +#define bM4_SDIOC1_ERRINTST_CEBE (*((volatile unsigned int*)(0x42DF8648UL))) +#define bM4_SDIOC1_ERRINTST_CIE (*((volatile unsigned int*)(0x42DF864CUL))) +#define bM4_SDIOC1_ERRINTST_DTOE (*((volatile unsigned int*)(0x42DF8650UL))) +#define bM4_SDIOC1_ERRINTST_DCE (*((volatile unsigned int*)(0x42DF8654UL))) +#define bM4_SDIOC1_ERRINTST_DEBE (*((volatile unsigned int*)(0x42DF8658UL))) +#define bM4_SDIOC1_ERRINTST_ACE (*((volatile unsigned int*)(0x42DF8660UL))) +#define bM4_SDIOC1_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42DF8680UL))) +#define bM4_SDIOC1_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42DF8684UL))) +#define bM4_SDIOC1_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42DF8688UL))) +#define bM4_SDIOC1_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42DF8690UL))) +#define bM4_SDIOC1_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42DF8694UL))) +#define bM4_SDIOC1_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42DF8698UL))) +#define bM4_SDIOC1_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42DF869CUL))) +#define bM4_SDIOC1_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42DF86A0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42DF86C0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42DF86C4UL))) +#define bM4_SDIOC1_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42DF86C8UL))) +#define bM4_SDIOC1_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42DF86CCUL))) +#define bM4_SDIOC1_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42DF86D0UL))) +#define bM4_SDIOC1_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42DF86D4UL))) +#define bM4_SDIOC1_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42DF86D8UL))) +#define bM4_SDIOC1_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42DF86E0UL))) +#define bM4_SDIOC1_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42DF8700UL))) +#define bM4_SDIOC1_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42DF8704UL))) +#define bM4_SDIOC1_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42DF8708UL))) +#define bM4_SDIOC1_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42DF8710UL))) +#define bM4_SDIOC1_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42DF8714UL))) +#define bM4_SDIOC1_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42DF8718UL))) +#define bM4_SDIOC1_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42DF871CUL))) +#define bM4_SDIOC1_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42DF8720UL))) +#define bM4_SDIOC1_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42DF8740UL))) +#define bM4_SDIOC1_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42DF8744UL))) +#define bM4_SDIOC1_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42DF8748UL))) +#define bM4_SDIOC1_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42DF874CUL))) +#define bM4_SDIOC1_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42DF8750UL))) +#define bM4_SDIOC1_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42DF8754UL))) +#define bM4_SDIOC1_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42DF8758UL))) +#define bM4_SDIOC1_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42DF8760UL))) +#define bM4_SDIOC1_ATCERRST_NE (*((volatile unsigned int*)(0x42DF8780UL))) +#define bM4_SDIOC1_ATCERRST_TOE (*((volatile unsigned int*)(0x42DF8784UL))) +#define bM4_SDIOC1_ATCERRST_CE (*((volatile unsigned int*)(0x42DF8788UL))) +#define bM4_SDIOC1_ATCERRST_EBE (*((volatile unsigned int*)(0x42DF878CUL))) +#define bM4_SDIOC1_ATCERRST_IE (*((volatile unsigned int*)(0x42DF8790UL))) +#define bM4_SDIOC1_ATCERRST_CMDE (*((volatile unsigned int*)(0x42DF879CUL))) +#define bM4_SDIOC1_FEA_FNE (*((volatile unsigned int*)(0x42DF8A00UL))) +#define bM4_SDIOC1_FEA_FTOE (*((volatile unsigned int*)(0x42DF8A04UL))) +#define bM4_SDIOC1_FEA_FCE (*((volatile unsigned int*)(0x42DF8A08UL))) +#define bM4_SDIOC1_FEA_FEBE (*((volatile unsigned int*)(0x42DF8A0CUL))) +#define bM4_SDIOC1_FEA_FIE (*((volatile unsigned int*)(0x42DF8A10UL))) +#define bM4_SDIOC1_FEA_FCMDE (*((volatile unsigned int*)(0x42DF8A1CUL))) +#define bM4_SDIOC1_FEE_FCTOE (*((volatile unsigned int*)(0x42DF8A40UL))) +#define bM4_SDIOC1_FEE_FCCE (*((volatile unsigned int*)(0x42DF8A44UL))) +#define bM4_SDIOC1_FEE_FCEBE (*((volatile unsigned int*)(0x42DF8A48UL))) +#define bM4_SDIOC1_FEE_FCIE (*((volatile unsigned int*)(0x42DF8A4CUL))) +#define bM4_SDIOC1_FEE_FDTOE (*((volatile unsigned int*)(0x42DF8A50UL))) +#define bM4_SDIOC1_FEE_FDCE (*((volatile unsigned int*)(0x42DF8A54UL))) +#define bM4_SDIOC1_FEE_FDEBE (*((volatile unsigned int*)(0x42DF8A58UL))) +#define bM4_SDIOC1_FEE_FACE (*((volatile unsigned int*)(0x42DF8A60UL))) +#define bM4_SDIOC2_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42E00080UL))) +#define bM4_SDIOC2_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42E00084UL))) +#define bM4_SDIOC2_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42E00088UL))) +#define bM4_SDIOC2_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42E0008CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42E00090UL))) +#define bM4_SDIOC2_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42E00094UL))) +#define bM4_SDIOC2_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42E00098UL))) +#define bM4_SDIOC2_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42E0009CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42E000A0UL))) +#define bM4_SDIOC2_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42E000A4UL))) +#define bM4_SDIOC2_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42E000A8UL))) +#define bM4_SDIOC2_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42E000ACUL))) +#define bM4_SDIOC2_TRANSMODE_BCE (*((volatile unsigned int*)(0x42E00184UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42E00188UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42E0018CUL))) +#define bM4_SDIOC2_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42E00190UL))) +#define bM4_SDIOC2_TRANSMODE_MULB (*((volatile unsigned int*)(0x42E00194UL))) +#define bM4_SDIOC2_CMD_RESTYP0 (*((volatile unsigned int*)(0x42E001C0UL))) +#define bM4_SDIOC2_CMD_RESTYP1 (*((volatile unsigned int*)(0x42E001C4UL))) +#define bM4_SDIOC2_CMD_CCE (*((volatile unsigned int*)(0x42E001CCUL))) +#define bM4_SDIOC2_CMD_ICE (*((volatile unsigned int*)(0x42E001D0UL))) +#define bM4_SDIOC2_CMD_DAT (*((volatile unsigned int*)(0x42E001D4UL))) +#define bM4_SDIOC2_CMD_TYP0 (*((volatile unsigned int*)(0x42E001D8UL))) +#define bM4_SDIOC2_CMD_TYP1 (*((volatile unsigned int*)(0x42E001DCUL))) +#define bM4_SDIOC2_CMD_IDX0 (*((volatile unsigned int*)(0x42E001E0UL))) +#define bM4_SDIOC2_CMD_IDX1 (*((volatile unsigned int*)(0x42E001E4UL))) +#define bM4_SDIOC2_CMD_IDX2 (*((volatile unsigned int*)(0x42E001E8UL))) +#define bM4_SDIOC2_CMD_IDX3 (*((volatile unsigned int*)(0x42E001ECUL))) +#define bM4_SDIOC2_CMD_IDX4 (*((volatile unsigned int*)(0x42E001F0UL))) +#define bM4_SDIOC2_CMD_IDX5 (*((volatile unsigned int*)(0x42E001F4UL))) +#define bM4_SDIOC2_PSTAT_CIC (*((volatile unsigned int*)(0x42E00480UL))) +#define bM4_SDIOC2_PSTAT_CID (*((volatile unsigned int*)(0x42E00484UL))) +#define bM4_SDIOC2_PSTAT_DA (*((volatile unsigned int*)(0x42E00488UL))) +#define bM4_SDIOC2_PSTAT_WTA (*((volatile unsigned int*)(0x42E004A0UL))) +#define bM4_SDIOC2_PSTAT_RTA (*((volatile unsigned int*)(0x42E004A4UL))) +#define bM4_SDIOC2_PSTAT_BWE (*((volatile unsigned int*)(0x42E004A8UL))) +#define bM4_SDIOC2_PSTAT_BRE (*((volatile unsigned int*)(0x42E004ACUL))) +#define bM4_SDIOC2_PSTAT_CIN (*((volatile unsigned int*)(0x42E004C0UL))) +#define bM4_SDIOC2_PSTAT_CSS (*((volatile unsigned int*)(0x42E004C4UL))) +#define bM4_SDIOC2_PSTAT_CDL (*((volatile unsigned int*)(0x42E004C8UL))) +#define bM4_SDIOC2_PSTAT_WPL (*((volatile unsigned int*)(0x42E004CCUL))) +#define bM4_SDIOC2_PSTAT_DATL0 (*((volatile unsigned int*)(0x42E004D0UL))) +#define bM4_SDIOC2_PSTAT_DATL1 (*((volatile unsigned int*)(0x42E004D4UL))) +#define bM4_SDIOC2_PSTAT_DATL2 (*((volatile unsigned int*)(0x42E004D8UL))) +#define bM4_SDIOC2_PSTAT_DATL3 (*((volatile unsigned int*)(0x42E004DCUL))) +#define bM4_SDIOC2_PSTAT_CMDL (*((volatile unsigned int*)(0x42E004E0UL))) +#define bM4_SDIOC2_HOSTCON_DW (*((volatile unsigned int*)(0x42E00504UL))) +#define bM4_SDIOC2_HOSTCON_HSEN (*((volatile unsigned int*)(0x42E00508UL))) +#define bM4_SDIOC2_HOSTCON_EXDW (*((volatile unsigned int*)(0x42E00514UL))) +#define bM4_SDIOC2_HOSTCON_CDTL (*((volatile unsigned int*)(0x42E00518UL))) +#define bM4_SDIOC2_HOSTCON_CDSS (*((volatile unsigned int*)(0x42E0051CUL))) +#define bM4_SDIOC2_PWRCON_PWON (*((volatile unsigned int*)(0x42E00520UL))) +#define bM4_SDIOC2_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42E00540UL))) +#define bM4_SDIOC2_BLKGPCON_CR (*((volatile unsigned int*)(0x42E00544UL))) +#define bM4_SDIOC2_BLKGPCON_RWC (*((volatile unsigned int*)(0x42E00548UL))) +#define bM4_SDIOC2_BLKGPCON_IABG (*((volatile unsigned int*)(0x42E0054CUL))) +#define bM4_SDIOC2_CLKCON_ICE (*((volatile unsigned int*)(0x42E00580UL))) +#define bM4_SDIOC2_CLKCON_CE (*((volatile unsigned int*)(0x42E00588UL))) +#define bM4_SDIOC2_CLKCON_FS0 (*((volatile unsigned int*)(0x42E005A0UL))) +#define bM4_SDIOC2_CLKCON_FS1 (*((volatile unsigned int*)(0x42E005A4UL))) +#define bM4_SDIOC2_CLKCON_FS2 (*((volatile unsigned int*)(0x42E005A8UL))) +#define bM4_SDIOC2_CLKCON_FS3 (*((volatile unsigned int*)(0x42E005ACUL))) +#define bM4_SDIOC2_CLKCON_FS4 (*((volatile unsigned int*)(0x42E005B0UL))) +#define bM4_SDIOC2_CLKCON_FS5 (*((volatile unsigned int*)(0x42E005B4UL))) +#define bM4_SDIOC2_CLKCON_FS6 (*((volatile unsigned int*)(0x42E005B8UL))) +#define bM4_SDIOC2_CLKCON_FS7 (*((volatile unsigned int*)(0x42E005BCUL))) +#define bM4_SDIOC2_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42E005C0UL))) +#define bM4_SDIOC2_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42E005C4UL))) +#define bM4_SDIOC2_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42E005C8UL))) +#define bM4_SDIOC2_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42E005CCUL))) +#define bM4_SDIOC2_SFTRST_RSTA (*((volatile unsigned int*)(0x42E005E0UL))) +#define bM4_SDIOC2_SFTRST_RSTC (*((volatile unsigned int*)(0x42E005E4UL))) +#define bM4_SDIOC2_SFTRST_RSTD (*((volatile unsigned int*)(0x42E005E8UL))) +#define bM4_SDIOC2_NORINTST_CC (*((volatile unsigned int*)(0x42E00600UL))) +#define bM4_SDIOC2_NORINTST_TC (*((volatile unsigned int*)(0x42E00604UL))) +#define bM4_SDIOC2_NORINTST_BGE (*((volatile unsigned int*)(0x42E00608UL))) +#define bM4_SDIOC2_NORINTST_BWR (*((volatile unsigned int*)(0x42E00610UL))) +#define bM4_SDIOC2_NORINTST_BRR (*((volatile unsigned int*)(0x42E00614UL))) +#define bM4_SDIOC2_NORINTST_CIST (*((volatile unsigned int*)(0x42E00618UL))) +#define bM4_SDIOC2_NORINTST_CRM (*((volatile unsigned int*)(0x42E0061CUL))) +#define bM4_SDIOC2_NORINTST_CINT (*((volatile unsigned int*)(0x42E00620UL))) +#define bM4_SDIOC2_NORINTST_EI (*((volatile unsigned int*)(0x42E0063CUL))) +#define bM4_SDIOC2_ERRINTST_CTOE (*((volatile unsigned int*)(0x42E00640UL))) +#define bM4_SDIOC2_ERRINTST_CCE (*((volatile unsigned int*)(0x42E00644UL))) +#define bM4_SDIOC2_ERRINTST_CEBE (*((volatile unsigned int*)(0x42E00648UL))) +#define bM4_SDIOC2_ERRINTST_CIE (*((volatile unsigned int*)(0x42E0064CUL))) +#define bM4_SDIOC2_ERRINTST_DTOE (*((volatile unsigned int*)(0x42E00650UL))) +#define bM4_SDIOC2_ERRINTST_DCE (*((volatile unsigned int*)(0x42E00654UL))) +#define bM4_SDIOC2_ERRINTST_DEBE (*((volatile unsigned int*)(0x42E00658UL))) +#define bM4_SDIOC2_ERRINTST_ACE (*((volatile unsigned int*)(0x42E00660UL))) +#define bM4_SDIOC2_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42E00680UL))) +#define bM4_SDIOC2_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42E00684UL))) +#define bM4_SDIOC2_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42E00688UL))) +#define bM4_SDIOC2_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42E00690UL))) +#define bM4_SDIOC2_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42E00694UL))) +#define bM4_SDIOC2_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42E00698UL))) +#define bM4_SDIOC2_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42E0069CUL))) +#define bM4_SDIOC2_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42E006A0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42E006C0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42E006C4UL))) +#define bM4_SDIOC2_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42E006C8UL))) +#define bM4_SDIOC2_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42E006CCUL))) +#define bM4_SDIOC2_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42E006D0UL))) +#define bM4_SDIOC2_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42E006D4UL))) +#define bM4_SDIOC2_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42E006D8UL))) +#define bM4_SDIOC2_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42E006E0UL))) +#define bM4_SDIOC2_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42E00700UL))) +#define bM4_SDIOC2_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42E00704UL))) +#define bM4_SDIOC2_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42E00708UL))) +#define bM4_SDIOC2_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42E00710UL))) +#define bM4_SDIOC2_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42E00714UL))) +#define bM4_SDIOC2_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42E00718UL))) +#define bM4_SDIOC2_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42E0071CUL))) +#define bM4_SDIOC2_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42E00720UL))) +#define bM4_SDIOC2_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42E00740UL))) +#define bM4_SDIOC2_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42E00744UL))) +#define bM4_SDIOC2_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42E00748UL))) +#define bM4_SDIOC2_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42E0074CUL))) +#define bM4_SDIOC2_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42E00750UL))) +#define bM4_SDIOC2_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42E00754UL))) +#define bM4_SDIOC2_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42E00758UL))) +#define bM4_SDIOC2_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42E00760UL))) +#define bM4_SDIOC2_ATCERRST_NE (*((volatile unsigned int*)(0x42E00780UL))) +#define bM4_SDIOC2_ATCERRST_TOE (*((volatile unsigned int*)(0x42E00784UL))) +#define bM4_SDIOC2_ATCERRST_CE (*((volatile unsigned int*)(0x42E00788UL))) +#define bM4_SDIOC2_ATCERRST_EBE (*((volatile unsigned int*)(0x42E0078CUL))) +#define bM4_SDIOC2_ATCERRST_IE (*((volatile unsigned int*)(0x42E00790UL))) +#define bM4_SDIOC2_ATCERRST_CMDE (*((volatile unsigned int*)(0x42E0079CUL))) +#define bM4_SDIOC2_FEA_FNE (*((volatile unsigned int*)(0x42E00A00UL))) +#define bM4_SDIOC2_FEA_FTOE (*((volatile unsigned int*)(0x42E00A04UL))) +#define bM4_SDIOC2_FEA_FCE (*((volatile unsigned int*)(0x42E00A08UL))) +#define bM4_SDIOC2_FEA_FEBE (*((volatile unsigned int*)(0x42E00A0CUL))) +#define bM4_SDIOC2_FEA_FIE (*((volatile unsigned int*)(0x42E00A10UL))) +#define bM4_SDIOC2_FEA_FCMDE (*((volatile unsigned int*)(0x42E00A1CUL))) +#define bM4_SDIOC2_FEE_FCTOE (*((volatile unsigned int*)(0x42E00A40UL))) +#define bM4_SDIOC2_FEE_FCCE (*((volatile unsigned int*)(0x42E00A44UL))) +#define bM4_SDIOC2_FEE_FCEBE (*((volatile unsigned int*)(0x42E00A48UL))) +#define bM4_SDIOC2_FEE_FCIE (*((volatile unsigned int*)(0x42E00A4CUL))) +#define bM4_SDIOC2_FEE_FDTOE (*((volatile unsigned int*)(0x42E00A50UL))) +#define bM4_SDIOC2_FEE_FDCE (*((volatile unsigned int*)(0x42E00A54UL))) +#define bM4_SDIOC2_FEE_FDEBE (*((volatile unsigned int*)(0x42E00A58UL))) +#define bM4_SDIOC2_FEE_FACE (*((volatile unsigned int*)(0x42E00A60UL))) +#define bM4_SPI1_CR1_SPIMDS (*((volatile unsigned int*)(0x42380080UL))) +#define bM4_SPI1_CR1_TXMDS (*((volatile unsigned int*)(0x42380084UL))) +#define bM4_SPI1_CR1_MSTR (*((volatile unsigned int*)(0x4238008CUL))) +#define bM4_SPI1_CR1_SPLPBK (*((volatile unsigned int*)(0x42380090UL))) +#define bM4_SPI1_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42380094UL))) +#define bM4_SPI1_CR1_SPE (*((volatile unsigned int*)(0x42380098UL))) +#define bM4_SPI1_CR1_CSUSPE (*((volatile unsigned int*)(0x4238009CUL))) +#define bM4_SPI1_CR1_EIE (*((volatile unsigned int*)(0x423800A0UL))) +#define bM4_SPI1_CR1_TXIE (*((volatile unsigned int*)(0x423800A4UL))) +#define bM4_SPI1_CR1_RXIE (*((volatile unsigned int*)(0x423800A8UL))) +#define bM4_SPI1_CR1_IDIE (*((volatile unsigned int*)(0x423800ACUL))) +#define bM4_SPI1_CR1_MODFE (*((volatile unsigned int*)(0x423800B0UL))) +#define bM4_SPI1_CR1_PATE (*((volatile unsigned int*)(0x423800B4UL))) +#define bM4_SPI1_CR1_PAOE (*((volatile unsigned int*)(0x423800B8UL))) +#define bM4_SPI1_CR1_PAE (*((volatile unsigned int*)(0x423800BCUL))) +#define bM4_SPI1_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42380180UL))) +#define bM4_SPI1_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42380184UL))) +#define bM4_SPI1_CFG1_SPRDTD (*((volatile unsigned int*)(0x42380198UL))) +#define bM4_SPI1_CFG1_SS0PV (*((volatile unsigned int*)(0x423801A0UL))) +#define bM4_SPI1_CFG1_SS1PV (*((volatile unsigned int*)(0x423801A4UL))) +#define bM4_SPI1_CFG1_SS2PV (*((volatile unsigned int*)(0x423801A8UL))) +#define bM4_SPI1_CFG1_SS3PV (*((volatile unsigned int*)(0x423801ACUL))) +#define bM4_SPI1_CFG1_MSSI0 (*((volatile unsigned int*)(0x423801D0UL))) +#define bM4_SPI1_CFG1_MSSI1 (*((volatile unsigned int*)(0x423801D4UL))) +#define bM4_SPI1_CFG1_MSSI2 (*((volatile unsigned int*)(0x423801D8UL))) +#define bM4_SPI1_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423801E0UL))) +#define bM4_SPI1_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423801E4UL))) +#define bM4_SPI1_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423801E8UL))) +#define bM4_SPI1_CFG1_MIDI0 (*((volatile unsigned int*)(0x423801F0UL))) +#define bM4_SPI1_CFG1_MIDI1 (*((volatile unsigned int*)(0x423801F4UL))) +#define bM4_SPI1_CFG1_MIDI2 (*((volatile unsigned int*)(0x423801F8UL))) +#define bM4_SPI1_SR_OVRERF (*((volatile unsigned int*)(0x42380280UL))) +#define bM4_SPI1_SR_IDLNF (*((volatile unsigned int*)(0x42380284UL))) +#define bM4_SPI1_SR_MODFERF (*((volatile unsigned int*)(0x42380288UL))) +#define bM4_SPI1_SR_PERF (*((volatile unsigned int*)(0x4238028CUL))) +#define bM4_SPI1_SR_UDRERF (*((volatile unsigned int*)(0x42380290UL))) +#define bM4_SPI1_SR_TDEF (*((volatile unsigned int*)(0x42380294UL))) +#define bM4_SPI1_SR_RDFF (*((volatile unsigned int*)(0x4238029CUL))) +#define bM4_SPI1_CFG2_CPHA (*((volatile unsigned int*)(0x42380300UL))) +#define bM4_SPI1_CFG2_CPOL (*((volatile unsigned int*)(0x42380304UL))) +#define bM4_SPI1_CFG2_MBR0 (*((volatile unsigned int*)(0x42380308UL))) +#define bM4_SPI1_CFG2_MBR1 (*((volatile unsigned int*)(0x4238030CUL))) +#define bM4_SPI1_CFG2_MBR2 (*((volatile unsigned int*)(0x42380310UL))) +#define bM4_SPI1_CFG2_SSA0 (*((volatile unsigned int*)(0x42380314UL))) +#define bM4_SPI1_CFG2_SSA1 (*((volatile unsigned int*)(0x42380318UL))) +#define bM4_SPI1_CFG2_SSA2 (*((volatile unsigned int*)(0x4238031CUL))) +#define bM4_SPI1_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42380320UL))) +#define bM4_SPI1_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42380324UL))) +#define bM4_SPI1_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42380328UL))) +#define bM4_SPI1_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238032CUL))) +#define bM4_SPI1_CFG2_LSBF (*((volatile unsigned int*)(0x42380330UL))) +#define bM4_SPI1_CFG2_MIDIE (*((volatile unsigned int*)(0x42380334UL))) +#define bM4_SPI1_CFG2_MSSDLE (*((volatile unsigned int*)(0x42380338UL))) +#define bM4_SPI1_CFG2_MSSIE (*((volatile unsigned int*)(0x4238033CUL))) +#define bM4_SPI2_CR1_SPIMDS (*((volatile unsigned int*)(0x42388080UL))) +#define bM4_SPI2_CR1_TXMDS (*((volatile unsigned int*)(0x42388084UL))) +#define bM4_SPI2_CR1_MSTR (*((volatile unsigned int*)(0x4238808CUL))) +#define bM4_SPI2_CR1_SPLPBK (*((volatile unsigned int*)(0x42388090UL))) +#define bM4_SPI2_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42388094UL))) +#define bM4_SPI2_CR1_SPE (*((volatile unsigned int*)(0x42388098UL))) +#define bM4_SPI2_CR1_CSUSPE (*((volatile unsigned int*)(0x4238809CUL))) +#define bM4_SPI2_CR1_EIE (*((volatile unsigned int*)(0x423880A0UL))) +#define bM4_SPI2_CR1_TXIE (*((volatile unsigned int*)(0x423880A4UL))) +#define bM4_SPI2_CR1_RXIE (*((volatile unsigned int*)(0x423880A8UL))) +#define bM4_SPI2_CR1_IDIE (*((volatile unsigned int*)(0x423880ACUL))) +#define bM4_SPI2_CR1_MODFE (*((volatile unsigned int*)(0x423880B0UL))) +#define bM4_SPI2_CR1_PATE (*((volatile unsigned int*)(0x423880B4UL))) +#define bM4_SPI2_CR1_PAOE (*((volatile unsigned int*)(0x423880B8UL))) +#define bM4_SPI2_CR1_PAE (*((volatile unsigned int*)(0x423880BCUL))) +#define bM4_SPI2_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42388180UL))) +#define bM4_SPI2_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42388184UL))) +#define bM4_SPI2_CFG1_SPRDTD (*((volatile unsigned int*)(0x42388198UL))) +#define bM4_SPI2_CFG1_SS0PV (*((volatile unsigned int*)(0x423881A0UL))) +#define bM4_SPI2_CFG1_SS1PV (*((volatile unsigned int*)(0x423881A4UL))) +#define bM4_SPI2_CFG1_SS2PV (*((volatile unsigned int*)(0x423881A8UL))) +#define bM4_SPI2_CFG1_SS3PV (*((volatile unsigned int*)(0x423881ACUL))) +#define bM4_SPI2_CFG1_MSSI0 (*((volatile unsigned int*)(0x423881D0UL))) +#define bM4_SPI2_CFG1_MSSI1 (*((volatile unsigned int*)(0x423881D4UL))) +#define bM4_SPI2_CFG1_MSSI2 (*((volatile unsigned int*)(0x423881D8UL))) +#define bM4_SPI2_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423881E0UL))) +#define bM4_SPI2_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423881E4UL))) +#define bM4_SPI2_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423881E8UL))) +#define bM4_SPI2_CFG1_MIDI0 (*((volatile unsigned int*)(0x423881F0UL))) +#define bM4_SPI2_CFG1_MIDI1 (*((volatile unsigned int*)(0x423881F4UL))) +#define bM4_SPI2_CFG1_MIDI2 (*((volatile unsigned int*)(0x423881F8UL))) +#define bM4_SPI2_SR_OVRERF (*((volatile unsigned int*)(0x42388280UL))) +#define bM4_SPI2_SR_IDLNF (*((volatile unsigned int*)(0x42388284UL))) +#define bM4_SPI2_SR_MODFERF (*((volatile unsigned int*)(0x42388288UL))) +#define bM4_SPI2_SR_PERF (*((volatile unsigned int*)(0x4238828CUL))) +#define bM4_SPI2_SR_UDRERF (*((volatile unsigned int*)(0x42388290UL))) +#define bM4_SPI2_SR_TDEF (*((volatile unsigned int*)(0x42388294UL))) +#define bM4_SPI2_SR_RDFF (*((volatile unsigned int*)(0x4238829CUL))) +#define bM4_SPI2_CFG2_CPHA (*((volatile unsigned int*)(0x42388300UL))) +#define bM4_SPI2_CFG2_CPOL (*((volatile unsigned int*)(0x42388304UL))) +#define bM4_SPI2_CFG2_MBR0 (*((volatile unsigned int*)(0x42388308UL))) +#define bM4_SPI2_CFG2_MBR1 (*((volatile unsigned int*)(0x4238830CUL))) +#define bM4_SPI2_CFG2_MBR2 (*((volatile unsigned int*)(0x42388310UL))) +#define bM4_SPI2_CFG2_SSA0 (*((volatile unsigned int*)(0x42388314UL))) +#define bM4_SPI2_CFG2_SSA1 (*((volatile unsigned int*)(0x42388318UL))) +#define bM4_SPI2_CFG2_SSA2 (*((volatile unsigned int*)(0x4238831CUL))) +#define bM4_SPI2_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42388320UL))) +#define bM4_SPI2_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42388324UL))) +#define bM4_SPI2_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42388328UL))) +#define bM4_SPI2_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238832CUL))) +#define bM4_SPI2_CFG2_LSBF (*((volatile unsigned int*)(0x42388330UL))) +#define bM4_SPI2_CFG2_MIDIE (*((volatile unsigned int*)(0x42388334UL))) +#define bM4_SPI2_CFG2_MSSDLE (*((volatile unsigned int*)(0x42388338UL))) +#define bM4_SPI2_CFG2_MSSIE (*((volatile unsigned int*)(0x4238833CUL))) +#define bM4_SPI3_CR1_SPIMDS (*((volatile unsigned int*)(0x42400080UL))) +#define bM4_SPI3_CR1_TXMDS (*((volatile unsigned int*)(0x42400084UL))) +#define bM4_SPI3_CR1_MSTR (*((volatile unsigned int*)(0x4240008CUL))) +#define bM4_SPI3_CR1_SPLPBK (*((volatile unsigned int*)(0x42400090UL))) +#define bM4_SPI3_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42400094UL))) +#define bM4_SPI3_CR1_SPE (*((volatile unsigned int*)(0x42400098UL))) +#define bM4_SPI3_CR1_CSUSPE (*((volatile unsigned int*)(0x4240009CUL))) +#define bM4_SPI3_CR1_EIE (*((volatile unsigned int*)(0x424000A0UL))) +#define bM4_SPI3_CR1_TXIE (*((volatile unsigned int*)(0x424000A4UL))) +#define bM4_SPI3_CR1_RXIE (*((volatile unsigned int*)(0x424000A8UL))) +#define bM4_SPI3_CR1_IDIE (*((volatile unsigned int*)(0x424000ACUL))) +#define bM4_SPI3_CR1_MODFE (*((volatile unsigned int*)(0x424000B0UL))) +#define bM4_SPI3_CR1_PATE (*((volatile unsigned int*)(0x424000B4UL))) +#define bM4_SPI3_CR1_PAOE (*((volatile unsigned int*)(0x424000B8UL))) +#define bM4_SPI3_CR1_PAE (*((volatile unsigned int*)(0x424000BCUL))) +#define bM4_SPI3_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42400180UL))) +#define bM4_SPI3_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42400184UL))) +#define bM4_SPI3_CFG1_SPRDTD (*((volatile unsigned int*)(0x42400198UL))) +#define bM4_SPI3_CFG1_SS0PV (*((volatile unsigned int*)(0x424001A0UL))) +#define bM4_SPI3_CFG1_SS1PV (*((volatile unsigned int*)(0x424001A4UL))) +#define bM4_SPI3_CFG1_SS2PV (*((volatile unsigned int*)(0x424001A8UL))) +#define bM4_SPI3_CFG1_SS3PV (*((volatile unsigned int*)(0x424001ACUL))) +#define bM4_SPI3_CFG1_MSSI0 (*((volatile unsigned int*)(0x424001D0UL))) +#define bM4_SPI3_CFG1_MSSI1 (*((volatile unsigned int*)(0x424001D4UL))) +#define bM4_SPI3_CFG1_MSSI2 (*((volatile unsigned int*)(0x424001D8UL))) +#define bM4_SPI3_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424001E0UL))) +#define bM4_SPI3_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424001E4UL))) +#define bM4_SPI3_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424001E8UL))) +#define bM4_SPI3_CFG1_MIDI0 (*((volatile unsigned int*)(0x424001F0UL))) +#define bM4_SPI3_CFG1_MIDI1 (*((volatile unsigned int*)(0x424001F4UL))) +#define bM4_SPI3_CFG1_MIDI2 (*((volatile unsigned int*)(0x424001F8UL))) +#define bM4_SPI3_SR_OVRERF (*((volatile unsigned int*)(0x42400280UL))) +#define bM4_SPI3_SR_IDLNF (*((volatile unsigned int*)(0x42400284UL))) +#define bM4_SPI3_SR_MODFERF (*((volatile unsigned int*)(0x42400288UL))) +#define bM4_SPI3_SR_PERF (*((volatile unsigned int*)(0x4240028CUL))) +#define bM4_SPI3_SR_UDRERF (*((volatile unsigned int*)(0x42400290UL))) +#define bM4_SPI3_SR_TDEF (*((volatile unsigned int*)(0x42400294UL))) +#define bM4_SPI3_SR_RDFF (*((volatile unsigned int*)(0x4240029CUL))) +#define bM4_SPI3_CFG2_CPHA (*((volatile unsigned int*)(0x42400300UL))) +#define bM4_SPI3_CFG2_CPOL (*((volatile unsigned int*)(0x42400304UL))) +#define bM4_SPI3_CFG2_MBR0 (*((volatile unsigned int*)(0x42400308UL))) +#define bM4_SPI3_CFG2_MBR1 (*((volatile unsigned int*)(0x4240030CUL))) +#define bM4_SPI3_CFG2_MBR2 (*((volatile unsigned int*)(0x42400310UL))) +#define bM4_SPI3_CFG2_SSA0 (*((volatile unsigned int*)(0x42400314UL))) +#define bM4_SPI3_CFG2_SSA1 (*((volatile unsigned int*)(0x42400318UL))) +#define bM4_SPI3_CFG2_SSA2 (*((volatile unsigned int*)(0x4240031CUL))) +#define bM4_SPI3_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42400320UL))) +#define bM4_SPI3_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42400324UL))) +#define bM4_SPI3_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42400328UL))) +#define bM4_SPI3_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240032CUL))) +#define bM4_SPI3_CFG2_LSBF (*((volatile unsigned int*)(0x42400330UL))) +#define bM4_SPI3_CFG2_MIDIE (*((volatile unsigned int*)(0x42400334UL))) +#define bM4_SPI3_CFG2_MSSDLE (*((volatile unsigned int*)(0x42400338UL))) +#define bM4_SPI3_CFG2_MSSIE (*((volatile unsigned int*)(0x4240033CUL))) +#define bM4_SPI4_CR1_SPIMDS (*((volatile unsigned int*)(0x42408080UL))) +#define bM4_SPI4_CR1_TXMDS (*((volatile unsigned int*)(0x42408084UL))) +#define bM4_SPI4_CR1_MSTR (*((volatile unsigned int*)(0x4240808CUL))) +#define bM4_SPI4_CR1_SPLPBK (*((volatile unsigned int*)(0x42408090UL))) +#define bM4_SPI4_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42408094UL))) +#define bM4_SPI4_CR1_SPE (*((volatile unsigned int*)(0x42408098UL))) +#define bM4_SPI4_CR1_CSUSPE (*((volatile unsigned int*)(0x4240809CUL))) +#define bM4_SPI4_CR1_EIE (*((volatile unsigned int*)(0x424080A0UL))) +#define bM4_SPI4_CR1_TXIE (*((volatile unsigned int*)(0x424080A4UL))) +#define bM4_SPI4_CR1_RXIE (*((volatile unsigned int*)(0x424080A8UL))) +#define bM4_SPI4_CR1_IDIE (*((volatile unsigned int*)(0x424080ACUL))) +#define bM4_SPI4_CR1_MODFE (*((volatile unsigned int*)(0x424080B0UL))) +#define bM4_SPI4_CR1_PATE (*((volatile unsigned int*)(0x424080B4UL))) +#define bM4_SPI4_CR1_PAOE (*((volatile unsigned int*)(0x424080B8UL))) +#define bM4_SPI4_CR1_PAE (*((volatile unsigned int*)(0x424080BCUL))) +#define bM4_SPI4_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42408180UL))) +#define bM4_SPI4_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42408184UL))) +#define bM4_SPI4_CFG1_SPRDTD (*((volatile unsigned int*)(0x42408198UL))) +#define bM4_SPI4_CFG1_SS0PV (*((volatile unsigned int*)(0x424081A0UL))) +#define bM4_SPI4_CFG1_SS1PV (*((volatile unsigned int*)(0x424081A4UL))) +#define bM4_SPI4_CFG1_SS2PV (*((volatile unsigned int*)(0x424081A8UL))) +#define bM4_SPI4_CFG1_SS3PV (*((volatile unsigned int*)(0x424081ACUL))) +#define bM4_SPI4_CFG1_MSSI0 (*((volatile unsigned int*)(0x424081D0UL))) +#define bM4_SPI4_CFG1_MSSI1 (*((volatile unsigned int*)(0x424081D4UL))) +#define bM4_SPI4_CFG1_MSSI2 (*((volatile unsigned int*)(0x424081D8UL))) +#define bM4_SPI4_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424081E0UL))) +#define bM4_SPI4_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424081E4UL))) +#define bM4_SPI4_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424081E8UL))) +#define bM4_SPI4_CFG1_MIDI0 (*((volatile unsigned int*)(0x424081F0UL))) +#define bM4_SPI4_CFG1_MIDI1 (*((volatile unsigned int*)(0x424081F4UL))) +#define bM4_SPI4_CFG1_MIDI2 (*((volatile unsigned int*)(0x424081F8UL))) +#define bM4_SPI4_SR_OVRERF (*((volatile unsigned int*)(0x42408280UL))) +#define bM4_SPI4_SR_IDLNF (*((volatile unsigned int*)(0x42408284UL))) +#define bM4_SPI4_SR_MODFERF (*((volatile unsigned int*)(0x42408288UL))) +#define bM4_SPI4_SR_PERF (*((volatile unsigned int*)(0x4240828CUL))) +#define bM4_SPI4_SR_UDRERF (*((volatile unsigned int*)(0x42408290UL))) +#define bM4_SPI4_SR_TDEF (*((volatile unsigned int*)(0x42408294UL))) +#define bM4_SPI4_SR_RDFF (*((volatile unsigned int*)(0x4240829CUL))) +#define bM4_SPI4_CFG2_CPHA (*((volatile unsigned int*)(0x42408300UL))) +#define bM4_SPI4_CFG2_CPOL (*((volatile unsigned int*)(0x42408304UL))) +#define bM4_SPI4_CFG2_MBR0 (*((volatile unsigned int*)(0x42408308UL))) +#define bM4_SPI4_CFG2_MBR1 (*((volatile unsigned int*)(0x4240830CUL))) +#define bM4_SPI4_CFG2_MBR2 (*((volatile unsigned int*)(0x42408310UL))) +#define bM4_SPI4_CFG2_SSA0 (*((volatile unsigned int*)(0x42408314UL))) +#define bM4_SPI4_CFG2_SSA1 (*((volatile unsigned int*)(0x42408318UL))) +#define bM4_SPI4_CFG2_SSA2 (*((volatile unsigned int*)(0x4240831CUL))) +#define bM4_SPI4_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42408320UL))) +#define bM4_SPI4_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42408324UL))) +#define bM4_SPI4_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42408328UL))) +#define bM4_SPI4_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240832CUL))) +#define bM4_SPI4_CFG2_LSBF (*((volatile unsigned int*)(0x42408330UL))) +#define bM4_SPI4_CFG2_MIDIE (*((volatile unsigned int*)(0x42408334UL))) +#define bM4_SPI4_CFG2_MSSDLE (*((volatile unsigned int*)(0x42408338UL))) +#define bM4_SPI4_CFG2_MSSIE (*((volatile unsigned int*)(0x4240833CUL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT0 (*((volatile unsigned int*)(0x42A10000UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT1 (*((volatile unsigned int*)(0x42A10004UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT2 (*((volatile unsigned int*)(0x42A10008UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT0 (*((volatile unsigned int*)(0x42A10010UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT1 (*((volatile unsigned int*)(0x42A10014UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT2 (*((volatile unsigned int*)(0x42A10018UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT0 (*((volatile unsigned int*)(0x42A10020UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT1 (*((volatile unsigned int*)(0x42A10024UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT2 (*((volatile unsigned int*)(0x42A10028UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT0 (*((volatile unsigned int*)(0x42A10030UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT1 (*((volatile unsigned int*)(0x42A10034UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT2 (*((volatile unsigned int*)(0x42A10038UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT0 (*((volatile unsigned int*)(0x42A10040UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT1 (*((volatile unsigned int*)(0x42A10044UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT2 (*((volatile unsigned int*)(0x42A10048UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT0 (*((volatile unsigned int*)(0x42A10050UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT1 (*((volatile unsigned int*)(0x42A10054UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT2 (*((volatile unsigned int*)(0x42A10058UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT0 (*((volatile unsigned int*)(0x42A10060UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT1 (*((volatile unsigned int*)(0x42A10064UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT2 (*((volatile unsigned int*)(0x42A10068UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT0 (*((volatile unsigned int*)(0x42A10070UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT1 (*((volatile unsigned int*)(0x42A10074UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT2 (*((volatile unsigned int*)(0x42A10078UL))) +#define bM4_SRAMC_WTPR_WTPRC (*((volatile unsigned int*)(0x42A10080UL))) +#define bM4_SRAMC_WTPR_WTPRKW0 (*((volatile unsigned int*)(0x42A10084UL))) +#define bM4_SRAMC_WTPR_WTPRKW1 (*((volatile unsigned int*)(0x42A10088UL))) +#define bM4_SRAMC_WTPR_WTPRKW2 (*((volatile unsigned int*)(0x42A1008CUL))) +#define bM4_SRAMC_WTPR_WTPRKW3 (*((volatile unsigned int*)(0x42A10090UL))) +#define bM4_SRAMC_WTPR_WTPRKW4 (*((volatile unsigned int*)(0x42A10094UL))) +#define bM4_SRAMC_WTPR_WTPRKW5 (*((volatile unsigned int*)(0x42A10098UL))) +#define bM4_SRAMC_WTPR_WTPRKW6 (*((volatile unsigned int*)(0x42A1009CUL))) +#define bM4_SRAMC_CKCR_PYOAD (*((volatile unsigned int*)(0x42A10100UL))) +#define bM4_SRAMC_CKCR_ECCOAD (*((volatile unsigned int*)(0x42A10140UL))) +#define bM4_SRAMC_CKCR_ECCMOD0 (*((volatile unsigned int*)(0x42A10160UL))) +#define bM4_SRAMC_CKCR_ECCMOD1 (*((volatile unsigned int*)(0x42A10164UL))) +#define bM4_SRAMC_CKPR_CKPRC (*((volatile unsigned int*)(0x42A10180UL))) +#define bM4_SRAMC_CKPR_CKPRKW0 (*((volatile unsigned int*)(0x42A10184UL))) +#define bM4_SRAMC_CKPR_CKPRKW1 (*((volatile unsigned int*)(0x42A10188UL))) +#define bM4_SRAMC_CKPR_CKPRKW2 (*((volatile unsigned int*)(0x42A1018CUL))) +#define bM4_SRAMC_CKPR_CKPRKW3 (*((volatile unsigned int*)(0x42A10190UL))) +#define bM4_SRAMC_CKPR_CKPRKW4 (*((volatile unsigned int*)(0x42A10194UL))) +#define bM4_SRAMC_CKPR_CKPRKW5 (*((volatile unsigned int*)(0x42A10198UL))) +#define bM4_SRAMC_CKPR_CKPRKW6 (*((volatile unsigned int*)(0x42A1019CUL))) +#define bM4_SRAMC_CKSR_SRAM3_1ERR (*((volatile unsigned int*)(0x42A10200UL))) +#define bM4_SRAMC_CKSR_SRAM3_2ERR (*((volatile unsigned int*)(0x42A10204UL))) +#define bM4_SRAMC_CKSR_SRAM12_PYERR (*((volatile unsigned int*)(0x42A10208UL))) +#define bM4_SRAMC_CKSR_SRAMH_PYERR (*((volatile unsigned int*)(0x42A1020CUL))) +#define bM4_SRAMC_CKSR_SRAMR_PYERR (*((volatile unsigned int*)(0x42A10210UL))) +#define bM4_SWDT_SR_CNT0 (*((volatile unsigned int*)(0x42928080UL))) +#define bM4_SWDT_SR_CNT1 (*((volatile unsigned int*)(0x42928084UL))) +#define bM4_SWDT_SR_CNT2 (*((volatile unsigned int*)(0x42928088UL))) +#define bM4_SWDT_SR_CNT3 (*((volatile unsigned int*)(0x4292808CUL))) +#define bM4_SWDT_SR_CNT4 (*((volatile unsigned int*)(0x42928090UL))) +#define bM4_SWDT_SR_CNT5 (*((volatile unsigned int*)(0x42928094UL))) +#define bM4_SWDT_SR_CNT6 (*((volatile unsigned int*)(0x42928098UL))) +#define bM4_SWDT_SR_CNT7 (*((volatile unsigned int*)(0x4292809CUL))) +#define bM4_SWDT_SR_CNT8 (*((volatile unsigned int*)(0x429280A0UL))) +#define bM4_SWDT_SR_CNT9 (*((volatile unsigned int*)(0x429280A4UL))) +#define bM4_SWDT_SR_CNT10 (*((volatile unsigned int*)(0x429280A8UL))) +#define bM4_SWDT_SR_CNT11 (*((volatile unsigned int*)(0x429280ACUL))) +#define bM4_SWDT_SR_CNT12 (*((volatile unsigned int*)(0x429280B0UL))) +#define bM4_SWDT_SR_CNT13 (*((volatile unsigned int*)(0x429280B4UL))) +#define bM4_SWDT_SR_CNT14 (*((volatile unsigned int*)(0x429280B8UL))) +#define bM4_SWDT_SR_CNT15 (*((volatile unsigned int*)(0x429280BCUL))) +#define bM4_SWDT_SR_UDF (*((volatile unsigned int*)(0x429280C0UL))) +#define bM4_SWDT_SR_REF (*((volatile unsigned int*)(0x429280C4UL))) +#define bM4_SWDT_RR_RF0 (*((volatile unsigned int*)(0x42928100UL))) +#define bM4_SWDT_RR_RF1 (*((volatile unsigned int*)(0x42928104UL))) +#define bM4_SWDT_RR_RF2 (*((volatile unsigned int*)(0x42928108UL))) +#define bM4_SWDT_RR_RF3 (*((volatile unsigned int*)(0x4292810CUL))) +#define bM4_SWDT_RR_RF4 (*((volatile unsigned int*)(0x42928110UL))) +#define bM4_SWDT_RR_RF5 (*((volatile unsigned int*)(0x42928114UL))) +#define bM4_SWDT_RR_RF6 (*((volatile unsigned int*)(0x42928118UL))) +#define bM4_SWDT_RR_RF7 (*((volatile unsigned int*)(0x4292811CUL))) +#define bM4_SWDT_RR_RF8 (*((volatile unsigned int*)(0x42928120UL))) +#define bM4_SWDT_RR_RF9 (*((volatile unsigned int*)(0x42928124UL))) +#define bM4_SWDT_RR_RF10 (*((volatile unsigned int*)(0x42928128UL))) +#define bM4_SWDT_RR_RF11 (*((volatile unsigned int*)(0x4292812CUL))) +#define bM4_SWDT_RR_RF12 (*((volatile unsigned int*)(0x42928130UL))) +#define bM4_SWDT_RR_RF13 (*((volatile unsigned int*)(0x42928134UL))) +#define bM4_SWDT_RR_RF14 (*((volatile unsigned int*)(0x42928138UL))) +#define bM4_SWDT_RR_RF15 (*((volatile unsigned int*)(0x4292813CUL))) +#define bM4_SYSREG_PWR_STPMCR_FLNWT (*((volatile unsigned int*)(0x42A80180UL))) +#define bM4_SYSREG_PWR_STPMCR_CKSMRC (*((volatile unsigned int*)(0x42A80184UL))) +#define bM4_SYSREG_PWR_STPMCR_STOP (*((volatile unsigned int*)(0x42A801BCUL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL0 (*((volatile unsigned int*)(0x42A80200UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL1 (*((volatile unsigned int*)(0x42A80204UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL2 (*((volatile unsigned int*)(0x42A80208UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL3 (*((volatile unsigned int*)(0x42A8020CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL0 (*((volatile unsigned int*)(0x42A80240UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL1 (*((volatile unsigned int*)(0x42A80244UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL2 (*((volatile unsigned int*)(0x42A80248UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL3 (*((volatile unsigned int*)(0x42A8024CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL0 (*((volatile unsigned int*)(0x42A80250UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL1 (*((volatile unsigned int*)(0x42A80254UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL2 (*((volatile unsigned int*)(0x42A80258UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL3 (*((volatile unsigned int*)(0x42A8025CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL0 (*((volatile unsigned int*)(0x42A80260UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL1 (*((volatile unsigned int*)(0x42A80264UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL2 (*((volatile unsigned int*)(0x42A80268UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL3 (*((volatile unsigned int*)(0x42A8026CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL0 (*((volatile unsigned int*)(0x42A80270UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL1 (*((volatile unsigned int*)(0x42A80274UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL2 (*((volatile unsigned int*)(0x42A80278UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL3 (*((volatile unsigned int*)(0x42A8027CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC0 (*((volatile unsigned int*)(0x42A80280UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC1 (*((volatile unsigned int*)(0x42A80284UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC2 (*((volatile unsigned int*)(0x42A80288UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC3 (*((volatile unsigned int*)(0x42A8028CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC4 (*((volatile unsigned int*)(0x42A80290UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC5 (*((volatile unsigned int*)(0x42A80294UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC6 (*((volatile unsigned int*)(0x42A80298UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC7 (*((volatile unsigned int*)(0x42A8029CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC8 (*((volatile unsigned int*)(0x42A802A0UL))) +#define bM4_SYSREG_MPU_IPPR_AESRDP (*((volatile unsigned int*)(0x42A80380UL))) +#define bM4_SYSREG_MPU_IPPR_AESWRP (*((volatile unsigned int*)(0x42A80384UL))) +#define bM4_SYSREG_MPU_IPPR_HASHRDP (*((volatile unsigned int*)(0x42A80388UL))) +#define bM4_SYSREG_MPU_IPPR_HASHWRP (*((volatile unsigned int*)(0x42A8038CUL))) +#define bM4_SYSREG_MPU_IPPR_TRNGRDP (*((volatile unsigned int*)(0x42A80390UL))) +#define bM4_SYSREG_MPU_IPPR_TRNGWRP (*((volatile unsigned int*)(0x42A80394UL))) +#define bM4_SYSREG_MPU_IPPR_CRCRDP (*((volatile unsigned int*)(0x42A80398UL))) +#define bM4_SYSREG_MPU_IPPR_CRCWRP (*((volatile unsigned int*)(0x42A8039CUL))) +#define bM4_SYSREG_MPU_IPPR_FMCRDP (*((volatile unsigned int*)(0x42A803A0UL))) +#define bM4_SYSREG_MPU_IPPR_FMCWRP (*((volatile unsigned int*)(0x42A803A4UL))) +#define bM4_SYSREG_MPU_IPPR_WDTRDP (*((volatile unsigned int*)(0x42A803B0UL))) +#define bM4_SYSREG_MPU_IPPR_WDTWRP (*((volatile unsigned int*)(0x42A803B4UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTRDP (*((volatile unsigned int*)(0x42A803B8UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTWRP (*((volatile unsigned int*)(0x42A803BCUL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMRDP (*((volatile unsigned int*)(0x42A803C0UL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMWRP (*((volatile unsigned int*)(0x42A803C4UL))) +#define bM4_SYSREG_MPU_IPPR_RTCRDP (*((volatile unsigned int*)(0x42A803C8UL))) +#define bM4_SYSREG_MPU_IPPR_RTCWRP (*((volatile unsigned int*)(0x42A803CCUL))) +#define bM4_SYSREG_MPU_IPPR_DMPURDP (*((volatile unsigned int*)(0x42A803D0UL))) +#define bM4_SYSREG_MPU_IPPR_DMPUWRP (*((volatile unsigned int*)(0x42A803D4UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCRDP (*((volatile unsigned int*)(0x42A803D8UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCWRP (*((volatile unsigned int*)(0x42A803DCUL))) +#define bM4_SYSREG_MPU_IPPR_INTCRDP (*((volatile unsigned int*)(0x42A803E0UL))) +#define bM4_SYSREG_MPU_IPPR_INTCWRP (*((volatile unsigned int*)(0x42A803E4UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCRDP (*((volatile unsigned int*)(0x42A803E8UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCWRP (*((volatile unsigned int*)(0x42A803ECUL))) +#define bM4_SYSREG_MPU_IPPR_MSTPRDP (*((volatile unsigned int*)(0x42A803F0UL))) +#define bM4_SYSREG_MPU_IPPR_MSTPWRP (*((volatile unsigned int*)(0x42A803F4UL))) +#define bM4_SYSREG_MPU_IPPR_BUSERRE (*((volatile unsigned int*)(0x42A803FCUL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S0 (*((volatile unsigned int*)(0x42A80400UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S1 (*((volatile unsigned int*)(0x42A80404UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S2 (*((volatile unsigned int*)(0x42A80408UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S0 (*((volatile unsigned int*)(0x42A80410UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S1 (*((volatile unsigned int*)(0x42A80414UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S2 (*((volatile unsigned int*)(0x42A80418UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S0 (*((volatile unsigned int*)(0x42A80420UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S1 (*((volatile unsigned int*)(0x42A80424UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S2 (*((volatile unsigned int*)(0x42A80428UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S0 (*((volatile unsigned int*)(0x42A80430UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S1 (*((volatile unsigned int*)(0x42A80434UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S2 (*((volatile unsigned int*)(0x42A80438UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S0 (*((volatile unsigned int*)(0x42A80440UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S1 (*((volatile unsigned int*)(0x42A80444UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S2 (*((volatile unsigned int*)(0x42A80448UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS0 (*((volatile unsigned int*)(0x42A80450UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS1 (*((volatile unsigned int*)(0x42A80454UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS2 (*((volatile unsigned int*)(0x42A80458UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS0 (*((volatile unsigned int*)(0x42A80460UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS1 (*((volatile unsigned int*)(0x42A80464UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS2 (*((volatile unsigned int*)(0x42A80468UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS0 (*((volatile unsigned int*)(0x42A80490UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS1 (*((volatile unsigned int*)(0x42A80494UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS2 (*((volatile unsigned int*)(0x42A80498UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS3 (*((volatile unsigned int*)(0x42A8049CUL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW0 (*((volatile unsigned int*)(0x42A804C0UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW1 (*((volatile unsigned int*)(0x42A804C4UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW2 (*((volatile unsigned int*)(0x42A804C8UL))) +#define bM4_SYSREG_CMU_PLLCR_MPLLOFF (*((volatile unsigned int*)(0x42A80540UL))) +#define bM4_SYSREG_CMU_UPLLCR_UPLLOFF (*((volatile unsigned int*)(0x42A805C0UL))) +#define bM4_SYSREG_CMU_XTALCR_XTALSTP (*((volatile unsigned int*)(0x42A80640UL))) +#define bM4_SYSREG_CMU_HRCCR_HRCSTP (*((volatile unsigned int*)(0x42A806C0UL))) +#define bM4_SYSREG_CMU_MRCCR_MRCSTP (*((volatile unsigned int*)(0x42A80700UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_HRCSTBF (*((volatile unsigned int*)(0x42A80780UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_XTALSTBF (*((volatile unsigned int*)(0x42A8078CUL))) +#define bM4_SYSREG_CMU_OSCSTBSR_MPLLSTBF (*((volatile unsigned int*)(0x42A80794UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_UPLLSTBF (*((volatile unsigned int*)(0x42A80798UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL0 (*((volatile unsigned int*)(0x42A807A0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL1 (*((volatile unsigned int*)(0x42A807A4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL2 (*((volatile unsigned int*)(0x42A807A8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL3 (*((volatile unsigned int*)(0x42A807ACUL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV0 (*((volatile unsigned int*)(0x42A807B0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV1 (*((volatile unsigned int*)(0x42A807B4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV2 (*((volatile unsigned int*)(0x42A807B8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1EN (*((volatile unsigned int*)(0x42A807BCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL0 (*((volatile unsigned int*)(0x42A807C0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL1 (*((volatile unsigned int*)(0x42A807C4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL2 (*((volatile unsigned int*)(0x42A807C8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL3 (*((volatile unsigned int*)(0x42A807CCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV0 (*((volatile unsigned int*)(0x42A807D0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV1 (*((volatile unsigned int*)(0x42A807D4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV2 (*((volatile unsigned int*)(0x42A807D8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2EN (*((volatile unsigned int*)(0x42A807DCUL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS0 (*((volatile unsigned int*)(0x42A807E0UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS1 (*((volatile unsigned int*)(0x42A807E4UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKOE (*((volatile unsigned int*)(0x42A807FCUL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE (*((volatile unsigned int*)(0x42A80800UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRE (*((volatile unsigned int*)(0x42A80804UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRIS (*((volatile unsigned int*)(0x42A80808UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDE (*((volatile unsigned int*)(0x42A8081CUL))) +#define bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF (*((volatile unsigned int*)(0x42A80820UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB0 (*((volatile unsigned int*)(0x42A81440UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB1 (*((volatile unsigned int*)(0x42A81444UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB2 (*((volatile unsigned int*)(0x42A81448UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB3 (*((volatile unsigned int*)(0x42A8144CUL))) +#define bM4_SYSREG_RMU_RSTF0_PORF (*((volatile unsigned int*)(0x42A81800UL))) +#define bM4_SYSREG_RMU_RSTF0_PINRF (*((volatile unsigned int*)(0x42A81804UL))) +#define bM4_SYSREG_RMU_RSTF0_BORF (*((volatile unsigned int*)(0x42A81808UL))) +#define bM4_SYSREG_RMU_RSTF0_PVD1RF (*((volatile unsigned int*)(0x42A8180CUL))) +#define bM4_SYSREG_RMU_RSTF0_PVD2RF (*((volatile unsigned int*)(0x42A81810UL))) +#define bM4_SYSREG_RMU_RSTF0_WDRF (*((volatile unsigned int*)(0x42A81814UL))) +#define bM4_SYSREG_RMU_RSTF0_SWDRF (*((volatile unsigned int*)(0x42A81818UL))) +#define bM4_SYSREG_RMU_RSTF0_PDRF (*((volatile unsigned int*)(0x42A8181CUL))) +#define bM4_SYSREG_RMU_RSTF0_SWRF (*((volatile unsigned int*)(0x42A81820UL))) +#define bM4_SYSREG_RMU_RSTF0_MPUERF (*((volatile unsigned int*)(0x42A81824UL))) +#define bM4_SYSREG_RMU_RSTF0_RAPERF (*((volatile unsigned int*)(0x42A81828UL))) +#define bM4_SYSREG_RMU_RSTF0_RAECRF (*((volatile unsigned int*)(0x42A8182CUL))) +#define bM4_SYSREG_RMU_RSTF0_CKFERF (*((volatile unsigned int*)(0x42A81830UL))) +#define bM4_SYSREG_RMU_RSTF0_XTALERF (*((volatile unsigned int*)(0x42A81834UL))) +#define bM4_SYSREG_RMU_RSTF0_MULTIRF (*((volatile unsigned int*)(0x42A81838UL))) +#define bM4_SYSREG_RMU_RSTF0_CLRF (*((volatile unsigned int*)(0x42A8183CUL))) +#define bM4_SYSREG_PWR_PVDICR_PVD1NMIS (*((volatile unsigned int*)(0x42A81C00UL))) +#define bM4_SYSREG_PWR_PVDICR_PVD2NMIS (*((volatile unsigned int*)(0x42A81C10UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1MON (*((volatile unsigned int*)(0x42A81C20UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG (*((volatile unsigned int*)(0x42A81C24UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2MON (*((volatile unsigned int*)(0x42A81C30UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG (*((volatile unsigned int*)(0x42A81C34UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM0 (*((volatile unsigned int*)(0x42A82000UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM1 (*((volatile unsigned int*)(0x42A82004UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM2 (*((volatile unsigned int*)(0x42A82008UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM3 (*((volatile unsigned int*)(0x42A8200CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM4 (*((volatile unsigned int*)(0x42A82010UL))) +#define bM4_SYSREG_CMU_PLLCFGR_PLLSRC (*((volatile unsigned int*)(0x42A8201CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN0 (*((volatile unsigned int*)(0x42A82020UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN1 (*((volatile unsigned int*)(0x42A82024UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN2 (*((volatile unsigned int*)(0x42A82028UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN3 (*((volatile unsigned int*)(0x42A8202CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN4 (*((volatile unsigned int*)(0x42A82030UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN5 (*((volatile unsigned int*)(0x42A82034UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN6 (*((volatile unsigned int*)(0x42A82038UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN7 (*((volatile unsigned int*)(0x42A8203CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN8 (*((volatile unsigned int*)(0x42A82040UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR0 (*((volatile unsigned int*)(0x42A82050UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR1 (*((volatile unsigned int*)(0x42A82054UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR2 (*((volatile unsigned int*)(0x42A82058UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR3 (*((volatile unsigned int*)(0x42A8205CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ0 (*((volatile unsigned int*)(0x42A82060UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ1 (*((volatile unsigned int*)(0x42A82064UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ2 (*((volatile unsigned int*)(0x42A82068UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ3 (*((volatile unsigned int*)(0x42A8206CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP0 (*((volatile unsigned int*)(0x42A82070UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP1 (*((volatile unsigned int*)(0x42A82074UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP2 (*((volatile unsigned int*)(0x42A82078UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP3 (*((volatile unsigned int*)(0x42A8207CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM0 (*((volatile unsigned int*)(0x42A82080UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM1 (*((volatile unsigned int*)(0x42A82084UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM2 (*((volatile unsigned int*)(0x42A82088UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM3 (*((volatile unsigned int*)(0x42A8208CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM4 (*((volatile unsigned int*)(0x42A82090UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN0 (*((volatile unsigned int*)(0x42A820A0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN1 (*((volatile unsigned int*)(0x42A820A4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN2 (*((volatile unsigned int*)(0x42A820A8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN3 (*((volatile unsigned int*)(0x42A820ACUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN4 (*((volatile unsigned int*)(0x42A820B0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN5 (*((volatile unsigned int*)(0x42A820B4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN6 (*((volatile unsigned int*)(0x42A820B8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN7 (*((volatile unsigned int*)(0x42A820BCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN8 (*((volatile unsigned int*)(0x42A820C0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR0 (*((volatile unsigned int*)(0x42A820D0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR1 (*((volatile unsigned int*)(0x42A820D4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR2 (*((volatile unsigned int*)(0x42A820D8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR3 (*((volatile unsigned int*)(0x42A820DCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ0 (*((volatile unsigned int*)(0x42A820E0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ1 (*((volatile unsigned int*)(0x42A820E4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ2 (*((volatile unsigned int*)(0x42A820E8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ3 (*((volatile unsigned int*)(0x42A820ECUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP0 (*((volatile unsigned int*)(0x42A820F0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP1 (*((volatile unsigned int*)(0x42A820F4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP2 (*((volatile unsigned int*)(0x42A820F8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP3 (*((volatile unsigned int*)(0x42A820FCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB0 (*((volatile unsigned int*)(0x42A87FC0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB1 (*((volatile unsigned int*)(0x42A87FC4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB2 (*((volatile unsigned int*)(0x42A87FC8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB3 (*((volatile unsigned int*)(0x42A87FCCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE0 (*((volatile unsigned int*)(0x42A87FE0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE1 (*((volatile unsigned int*)(0x42A87FE4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE2 (*((volatile unsigned int*)(0x42A87FE8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE3 (*((volatile unsigned int*)(0x42A87FECUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE4 (*((volatile unsigned int*)(0x42A87FF0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE5 (*((volatile unsigned int*)(0x42A87FF4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE6 (*((volatile unsigned int*)(0x42A87FF8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE7 (*((volatile unsigned int*)(0x42A87FFCUL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS0 (*((volatile unsigned int*)(0x42A88000UL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS1 (*((volatile unsigned int*)(0x42A88004UL))) +#define bM4_SYSREG_PWR_PWRC0_VVDRSD (*((volatile unsigned int*)(0x42A88008UL))) +#define bM4_SYSREG_PWR_PWRC0_RETRAMSD (*((volatile unsigned int*)(0x42A8800CUL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN0 (*((volatile unsigned int*)(0x42A88010UL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN1 (*((volatile unsigned int*)(0x42A88014UL))) +#define bM4_SYSREG_PWR_PWRC0_PWDN (*((volatile unsigned int*)(0x42A8801CUL))) +#define bM4_SYSREG_PWR_PWRC1_VPLLSD (*((volatile unsigned int*)(0x42A88020UL))) +#define bM4_SYSREG_PWR_PWRC1_VHRCSD (*((volatile unsigned int*)(0x42A88024UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS0 (*((volatile unsigned int*)(0x42A88038UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS1 (*((volatile unsigned int*)(0x42A8803CUL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS0 (*((volatile unsigned int*)(0x42A88040UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS1 (*((volatile unsigned int*)(0x42A88044UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS2 (*((volatile unsigned int*)(0x42A88048UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS3 (*((volatile unsigned int*)(0x42A8804CUL))) +#define bM4_SYSREG_PWR_PWRC2_DVS0 (*((volatile unsigned int*)(0x42A88050UL))) +#define bM4_SYSREG_PWR_PWRC2_DVS1 (*((volatile unsigned int*)(0x42A88054UL))) +#define bM4_SYSREG_PWR_PWRC3_PDTS (*((volatile unsigned int*)(0x42A88068UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE00 (*((volatile unsigned int*)(0x42A88080UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE01 (*((volatile unsigned int*)(0x42A88084UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE02 (*((volatile unsigned int*)(0x42A88088UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE03 (*((volatile unsigned int*)(0x42A8808CUL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE10 (*((volatile unsigned int*)(0x42A88090UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE11 (*((volatile unsigned int*)(0x42A88094UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE12 (*((volatile unsigned int*)(0x42A88098UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE13 (*((volatile unsigned int*)(0x42A8809CUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE20 (*((volatile unsigned int*)(0x42A880A0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE21 (*((volatile unsigned int*)(0x42A880A4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE22 (*((volatile unsigned int*)(0x42A880A8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE23 (*((volatile unsigned int*)(0x42A880ACUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE30 (*((volatile unsigned int*)(0x42A880B0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE31 (*((volatile unsigned int*)(0x42A880B4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE32 (*((volatile unsigned int*)(0x42A880B8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE33 (*((volatile unsigned int*)(0x42A880BCUL))) +#define bM4_SYSREG_PWR_PDWKE2_VD1WKE (*((volatile unsigned int*)(0x42A880C0UL))) +#define bM4_SYSREG_PWR_PDWKE2_VD2WKE (*((volatile unsigned int*)(0x42A880C4UL))) +#define bM4_SYSREG_PWR_PDWKE2_NMIWKE (*((volatile unsigned int*)(0x42A880C8UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCPRDWKE (*((volatile unsigned int*)(0x42A880D0UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCALMWKE (*((volatile unsigned int*)(0x42A880D4UL))) +#define bM4_SYSREG_PWR_PDWKE2_WKTMWKE (*((volatile unsigned int*)(0x42A880DCUL))) +#define bM4_SYSREG_PWR_PDWKES_WK0EGS (*((volatile unsigned int*)(0x42A880E0UL))) +#define bM4_SYSREG_PWR_PDWKES_WK1EGS (*((volatile unsigned int*)(0x42A880E4UL))) +#define bM4_SYSREG_PWR_PDWKES_WK2EGS (*((volatile unsigned int*)(0x42A880E8UL))) +#define bM4_SYSREG_PWR_PDWKES_WK3EGS (*((volatile unsigned int*)(0x42A880ECUL))) +#define bM4_SYSREG_PWR_PDWKES_VD1EGS (*((volatile unsigned int*)(0x42A880F0UL))) +#define bM4_SYSREG_PWR_PDWKES_VD2EGS (*((volatile unsigned int*)(0x42A880F4UL))) +#define bM4_SYSREG_PWR_PDWKES_NMIEGS (*((volatile unsigned int*)(0x42A880F8UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK0F (*((volatile unsigned int*)(0x42A88100UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK1F (*((volatile unsigned int*)(0x42A88104UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK2F (*((volatile unsigned int*)(0x42A88108UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK3F (*((volatile unsigned int*)(0x42A8810CUL))) +#define bM4_SYSREG_PWR_PDWKF0_VD1WKF (*((volatile unsigned int*)(0x42A88110UL))) +#define bM4_SYSREG_PWR_PDWKF0_VD2WKF (*((volatile unsigned int*)(0x42A88114UL))) +#define bM4_SYSREG_PWR_PDWKF0_NMIWKF (*((volatile unsigned int*)(0x42A88118UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCPRDWKF (*((volatile unsigned int*)(0x42A88130UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCALMWKF (*((volatile unsigned int*)(0x42A88134UL))) +#define bM4_SYSREG_PWR_PDWKF1_WKTMWKF (*((volatile unsigned int*)(0x42A8813CUL))) +#define bM4_SYSREG_PWR_PWCMR_ADBUFE (*((volatile unsigned int*)(0x42A8815CUL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV0 (*((volatile unsigned int*)(0x42A88210UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV1 (*((volatile unsigned int*)(0x42A88214UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALMS (*((volatile unsigned int*)(0x42A88218UL))) +#define bM4_SYSREG_CMU_XTALCFGR_SUPDRV (*((volatile unsigned int*)(0x42A8821CUL))) +#define bM4_SYSREG_PWR_PVDCR0_EXVCCINEN (*((volatile unsigned int*)(0x42A88240UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD1EN (*((volatile unsigned int*)(0x42A88254UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD2EN (*((volatile unsigned int*)(0x42A88258UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRE (*((volatile unsigned int*)(0x42A88260UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRS (*((volatile unsigned int*)(0x42A88264UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1CMPOE (*((volatile unsigned int*)(0x42A88268UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRE (*((volatile unsigned int*)(0x42A88270UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRS (*((volatile unsigned int*)(0x42A88274UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2CMPOE (*((volatile unsigned int*)(0x42A88278UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFDIS (*((volatile unsigned int*)(0x42A88280UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS0 (*((volatile unsigned int*)(0x42A88284UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS1 (*((volatile unsigned int*)(0x42A88288UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFDIS (*((volatile unsigned int*)(0x42A88290UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS0 (*((volatile unsigned int*)(0x42A88294UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS1 (*((volatile unsigned int*)(0x42A88298UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL0 (*((volatile unsigned int*)(0x42A882A0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL1 (*((volatile unsigned int*)(0x42A882A4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL2 (*((volatile unsigned int*)(0x42A882A8UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL0 (*((volatile unsigned int*)(0x42A882B0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL1 (*((volatile unsigned int*)(0x42A882B4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL2 (*((volatile unsigned int*)(0x42A882B8UL))) +#define bM4_SYSREG_CMU_XTAL32CR_XTAL32STP (*((volatile unsigned int*)(0x42A88400UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV0 (*((volatile unsigned int*)(0x42A88420UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV1 (*((volatile unsigned int*)(0x42A88424UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV2 (*((volatile unsigned int*)(0x42A88428UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF0 (*((volatile unsigned int*)(0x42A884A0UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF1 (*((volatile unsigned int*)(0x42A884A4UL))) +#define bM4_SYSREG_CMU_LRCCR_LRCSTP (*((volatile unsigned int*)(0x42A884E0UL))) +#define bM4_SYSREG_PWR_XTAL32CS_CSDIS (*((volatile unsigned int*)(0x42A8857CUL))) +#define bM4_TMR01_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42480000UL))) +#define bM4_TMR01_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42480004UL))) +#define bM4_TMR01_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42480008UL))) +#define bM4_TMR01_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248000CUL))) +#define bM4_TMR01_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42480010UL))) +#define bM4_TMR01_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42480014UL))) +#define bM4_TMR01_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42480018UL))) +#define bM4_TMR01_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248001CUL))) +#define bM4_TMR01_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42480020UL))) +#define bM4_TMR01_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42480024UL))) +#define bM4_TMR01_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42480028UL))) +#define bM4_TMR01_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248002CUL))) +#define bM4_TMR01_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42480030UL))) +#define bM4_TMR01_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42480034UL))) +#define bM4_TMR01_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42480038UL))) +#define bM4_TMR01_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248003CUL))) +#define bM4_TMR01_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42480080UL))) +#define bM4_TMR01_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42480084UL))) +#define bM4_TMR01_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42480088UL))) +#define bM4_TMR01_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248008CUL))) +#define bM4_TMR01_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42480090UL))) +#define bM4_TMR01_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42480094UL))) +#define bM4_TMR01_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42480098UL))) +#define bM4_TMR01_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248009CUL))) +#define bM4_TMR01_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424800A0UL))) +#define bM4_TMR01_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424800A4UL))) +#define bM4_TMR01_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424800A8UL))) +#define bM4_TMR01_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424800ACUL))) +#define bM4_TMR01_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424800B0UL))) +#define bM4_TMR01_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424800B4UL))) +#define bM4_TMR01_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424800B8UL))) +#define bM4_TMR01_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424800BCUL))) +#define bM4_TMR01_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42480100UL))) +#define bM4_TMR01_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42480104UL))) +#define bM4_TMR01_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42480108UL))) +#define bM4_TMR01_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248010CUL))) +#define bM4_TMR01_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42480110UL))) +#define bM4_TMR01_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42480114UL))) +#define bM4_TMR01_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42480118UL))) +#define bM4_TMR01_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248011CUL))) +#define bM4_TMR01_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42480120UL))) +#define bM4_TMR01_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42480124UL))) +#define bM4_TMR01_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42480128UL))) +#define bM4_TMR01_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248012CUL))) +#define bM4_TMR01_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42480130UL))) +#define bM4_TMR01_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42480134UL))) +#define bM4_TMR01_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42480138UL))) +#define bM4_TMR01_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248013CUL))) +#define bM4_TMR01_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42480180UL))) +#define bM4_TMR01_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42480184UL))) +#define bM4_TMR01_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42480188UL))) +#define bM4_TMR01_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248018CUL))) +#define bM4_TMR01_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42480190UL))) +#define bM4_TMR01_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42480194UL))) +#define bM4_TMR01_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42480198UL))) +#define bM4_TMR01_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248019CUL))) +#define bM4_TMR01_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424801A0UL))) +#define bM4_TMR01_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424801A4UL))) +#define bM4_TMR01_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424801A8UL))) +#define bM4_TMR01_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424801ACUL))) +#define bM4_TMR01_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424801B0UL))) +#define bM4_TMR01_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424801B4UL))) +#define bM4_TMR01_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424801B8UL))) +#define bM4_TMR01_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424801BCUL))) +#define bM4_TMR01_BCONR_CSTA (*((volatile unsigned int*)(0x42480200UL))) +#define bM4_TMR01_BCONR_CAPMDA (*((volatile unsigned int*)(0x42480204UL))) +#define bM4_TMR01_BCONR_INTENA (*((volatile unsigned int*)(0x42480208UL))) +#define bM4_TMR01_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42480210UL))) +#define bM4_TMR01_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42480214UL))) +#define bM4_TMR01_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42480218UL))) +#define bM4_TMR01_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248021CUL))) +#define bM4_TMR01_BCONR_SYNSA (*((volatile unsigned int*)(0x42480220UL))) +#define bM4_TMR01_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42480224UL))) +#define bM4_TMR01_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42480228UL))) +#define bM4_TMR01_BCONR_HSTAA (*((volatile unsigned int*)(0x42480230UL))) +#define bM4_TMR01_BCONR_HSTPA (*((volatile unsigned int*)(0x42480234UL))) +#define bM4_TMR01_BCONR_HCLEA (*((volatile unsigned int*)(0x42480238UL))) +#define bM4_TMR01_BCONR_HICPA (*((volatile unsigned int*)(0x4248023CUL))) +#define bM4_TMR01_BCONR_CSTB (*((volatile unsigned int*)(0x42480240UL))) +#define bM4_TMR01_BCONR_CAPMDB (*((volatile unsigned int*)(0x42480244UL))) +#define bM4_TMR01_BCONR_INTENB (*((volatile unsigned int*)(0x42480248UL))) +#define bM4_TMR01_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42480250UL))) +#define bM4_TMR01_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42480254UL))) +#define bM4_TMR01_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42480258UL))) +#define bM4_TMR01_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248025CUL))) +#define bM4_TMR01_BCONR_SYNSB (*((volatile unsigned int*)(0x42480260UL))) +#define bM4_TMR01_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42480264UL))) +#define bM4_TMR01_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42480268UL))) +#define bM4_TMR01_BCONR_HSTAB (*((volatile unsigned int*)(0x42480270UL))) +#define bM4_TMR01_BCONR_HSTPB (*((volatile unsigned int*)(0x42480274UL))) +#define bM4_TMR01_BCONR_HCLEB (*((volatile unsigned int*)(0x42480278UL))) +#define bM4_TMR01_BCONR_HICPB (*((volatile unsigned int*)(0x4248027CUL))) +#define bM4_TMR01_STFLR_CMAF (*((volatile unsigned int*)(0x42480280UL))) +#define bM4_TMR01_STFLR_CMBF (*((volatile unsigned int*)(0x424802C0UL))) +#define bM4_TMR02_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42488000UL))) +#define bM4_TMR02_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42488004UL))) +#define bM4_TMR02_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42488008UL))) +#define bM4_TMR02_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248800CUL))) +#define bM4_TMR02_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42488010UL))) +#define bM4_TMR02_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42488014UL))) +#define bM4_TMR02_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42488018UL))) +#define bM4_TMR02_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248801CUL))) +#define bM4_TMR02_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42488020UL))) +#define bM4_TMR02_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42488024UL))) +#define bM4_TMR02_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42488028UL))) +#define bM4_TMR02_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248802CUL))) +#define bM4_TMR02_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42488030UL))) +#define bM4_TMR02_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42488034UL))) +#define bM4_TMR02_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42488038UL))) +#define bM4_TMR02_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248803CUL))) +#define bM4_TMR02_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42488080UL))) +#define bM4_TMR02_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42488084UL))) +#define bM4_TMR02_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42488088UL))) +#define bM4_TMR02_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248808CUL))) +#define bM4_TMR02_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42488090UL))) +#define bM4_TMR02_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42488094UL))) +#define bM4_TMR02_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42488098UL))) +#define bM4_TMR02_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248809CUL))) +#define bM4_TMR02_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424880A0UL))) +#define bM4_TMR02_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424880A4UL))) +#define bM4_TMR02_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424880A8UL))) +#define bM4_TMR02_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424880ACUL))) +#define bM4_TMR02_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424880B0UL))) +#define bM4_TMR02_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424880B4UL))) +#define bM4_TMR02_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424880B8UL))) +#define bM4_TMR02_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424880BCUL))) +#define bM4_TMR02_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42488100UL))) +#define bM4_TMR02_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42488104UL))) +#define bM4_TMR02_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42488108UL))) +#define bM4_TMR02_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248810CUL))) +#define bM4_TMR02_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42488110UL))) +#define bM4_TMR02_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42488114UL))) +#define bM4_TMR02_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42488118UL))) +#define bM4_TMR02_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248811CUL))) +#define bM4_TMR02_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42488120UL))) +#define bM4_TMR02_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42488124UL))) +#define bM4_TMR02_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42488128UL))) +#define bM4_TMR02_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248812CUL))) +#define bM4_TMR02_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42488130UL))) +#define bM4_TMR02_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42488134UL))) +#define bM4_TMR02_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42488138UL))) +#define bM4_TMR02_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248813CUL))) +#define bM4_TMR02_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42488180UL))) +#define bM4_TMR02_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42488184UL))) +#define bM4_TMR02_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42488188UL))) +#define bM4_TMR02_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248818CUL))) +#define bM4_TMR02_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42488190UL))) +#define bM4_TMR02_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42488194UL))) +#define bM4_TMR02_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42488198UL))) +#define bM4_TMR02_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248819CUL))) +#define bM4_TMR02_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424881A0UL))) +#define bM4_TMR02_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424881A4UL))) +#define bM4_TMR02_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424881A8UL))) +#define bM4_TMR02_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424881ACUL))) +#define bM4_TMR02_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424881B0UL))) +#define bM4_TMR02_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424881B4UL))) +#define bM4_TMR02_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424881B8UL))) +#define bM4_TMR02_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424881BCUL))) +#define bM4_TMR02_BCONR_CSTA (*((volatile unsigned int*)(0x42488200UL))) +#define bM4_TMR02_BCONR_CAPMDA (*((volatile unsigned int*)(0x42488204UL))) +#define bM4_TMR02_BCONR_INTENA (*((volatile unsigned int*)(0x42488208UL))) +#define bM4_TMR02_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42488210UL))) +#define bM4_TMR02_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42488214UL))) +#define bM4_TMR02_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42488218UL))) +#define bM4_TMR02_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248821CUL))) +#define bM4_TMR02_BCONR_SYNSA (*((volatile unsigned int*)(0x42488220UL))) +#define bM4_TMR02_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42488224UL))) +#define bM4_TMR02_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42488228UL))) +#define bM4_TMR02_BCONR_HSTAA (*((volatile unsigned int*)(0x42488230UL))) +#define bM4_TMR02_BCONR_HSTPA (*((volatile unsigned int*)(0x42488234UL))) +#define bM4_TMR02_BCONR_HCLEA (*((volatile unsigned int*)(0x42488238UL))) +#define bM4_TMR02_BCONR_HICPA (*((volatile unsigned int*)(0x4248823CUL))) +#define bM4_TMR02_BCONR_CSTB (*((volatile unsigned int*)(0x42488240UL))) +#define bM4_TMR02_BCONR_CAPMDB (*((volatile unsigned int*)(0x42488244UL))) +#define bM4_TMR02_BCONR_INTENB (*((volatile unsigned int*)(0x42488248UL))) +#define bM4_TMR02_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42488250UL))) +#define bM4_TMR02_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42488254UL))) +#define bM4_TMR02_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42488258UL))) +#define bM4_TMR02_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248825CUL))) +#define bM4_TMR02_BCONR_SYNSB (*((volatile unsigned int*)(0x42488260UL))) +#define bM4_TMR02_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42488264UL))) +#define bM4_TMR02_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42488268UL))) +#define bM4_TMR02_BCONR_HSTAB (*((volatile unsigned int*)(0x42488270UL))) +#define bM4_TMR02_BCONR_HSTPB (*((volatile unsigned int*)(0x42488274UL))) +#define bM4_TMR02_BCONR_HCLEB (*((volatile unsigned int*)(0x42488278UL))) +#define bM4_TMR02_BCONR_HICPB (*((volatile unsigned int*)(0x4248827CUL))) +#define bM4_TMR02_STFLR_CMAF (*((volatile unsigned int*)(0x42488280UL))) +#define bM4_TMR02_STFLR_CMBF (*((volatile unsigned int*)(0x424882C0UL))) +#define bM4_TMR41_OCSRU_OCEH (*((volatile unsigned int*)(0x422E0300UL))) +#define bM4_TMR41_OCSRU_OCEL (*((volatile unsigned int*)(0x422E0304UL))) +#define bM4_TMR41_OCSRU_OCPH (*((volatile unsigned int*)(0x422E0308UL))) +#define bM4_TMR41_OCSRU_OCPL (*((volatile unsigned int*)(0x422E030CUL))) +#define bM4_TMR41_OCSRU_OCIEH (*((volatile unsigned int*)(0x422E0310UL))) +#define bM4_TMR41_OCSRU_OCIEL (*((volatile unsigned int*)(0x422E0314UL))) +#define bM4_TMR41_OCSRU_OCFH (*((volatile unsigned int*)(0x422E0318UL))) +#define bM4_TMR41_OCSRU_OCFL (*((volatile unsigned int*)(0x422E031CUL))) +#define bM4_TMR41_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x422E0340UL))) +#define bM4_TMR41_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x422E0344UL))) +#define bM4_TMR41_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x422E0348UL))) +#define bM4_TMR41_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x422E034CUL))) +#define bM4_TMR41_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x422E0350UL))) +#define bM4_TMR41_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x422E0354UL))) +#define bM4_TMR41_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x422E0358UL))) +#define bM4_TMR41_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x422E035CUL))) +#define bM4_TMR41_OCERU_LMCH (*((volatile unsigned int*)(0x422E0360UL))) +#define bM4_TMR41_OCERU_LMCL (*((volatile unsigned int*)(0x422E0364UL))) +#define bM4_TMR41_OCERU_LMMH (*((volatile unsigned int*)(0x422E0368UL))) +#define bM4_TMR41_OCERU_LMML (*((volatile unsigned int*)(0x422E036CUL))) +#define bM4_TMR41_OCERU_MCECH (*((volatile unsigned int*)(0x422E0370UL))) +#define bM4_TMR41_OCERU_MCECL (*((volatile unsigned int*)(0x422E0374UL))) +#define bM4_TMR41_OCSRV_OCEH (*((volatile unsigned int*)(0x422E0380UL))) +#define bM4_TMR41_OCSRV_OCEL (*((volatile unsigned int*)(0x422E0384UL))) +#define bM4_TMR41_OCSRV_OCPH (*((volatile unsigned int*)(0x422E0388UL))) +#define bM4_TMR41_OCSRV_OCPL (*((volatile unsigned int*)(0x422E038CUL))) +#define bM4_TMR41_OCSRV_OCIEH (*((volatile unsigned int*)(0x422E0390UL))) +#define bM4_TMR41_OCSRV_OCIEL (*((volatile unsigned int*)(0x422E0394UL))) +#define bM4_TMR41_OCSRV_OCFH (*((volatile unsigned int*)(0x422E0398UL))) +#define bM4_TMR41_OCSRV_OCFL (*((volatile unsigned int*)(0x422E039CUL))) +#define bM4_TMR41_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x422E03C0UL))) +#define bM4_TMR41_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x422E03C4UL))) +#define bM4_TMR41_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x422E03C8UL))) +#define bM4_TMR41_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x422E03CCUL))) +#define bM4_TMR41_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x422E03D0UL))) +#define bM4_TMR41_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x422E03D4UL))) +#define bM4_TMR41_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x422E03D8UL))) +#define bM4_TMR41_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x422E03DCUL))) +#define bM4_TMR41_OCERV_LMCH (*((volatile unsigned int*)(0x422E03E0UL))) +#define bM4_TMR41_OCERV_LMCL (*((volatile unsigned int*)(0x422E03E4UL))) +#define bM4_TMR41_OCERV_LMMH (*((volatile unsigned int*)(0x422E03E8UL))) +#define bM4_TMR41_OCERV_LMML (*((volatile unsigned int*)(0x422E03ECUL))) +#define bM4_TMR41_OCERV_MCECH (*((volatile unsigned int*)(0x422E03F0UL))) +#define bM4_TMR41_OCERV_MCECL (*((volatile unsigned int*)(0x422E03F4UL))) +#define bM4_TMR41_OCSRW_OCEH (*((volatile unsigned int*)(0x422E0400UL))) +#define bM4_TMR41_OCSRW_OCEL (*((volatile unsigned int*)(0x422E0404UL))) +#define bM4_TMR41_OCSRW_OCPH (*((volatile unsigned int*)(0x422E0408UL))) +#define bM4_TMR41_OCSRW_OCPL (*((volatile unsigned int*)(0x422E040CUL))) +#define bM4_TMR41_OCSRW_OCIEH (*((volatile unsigned int*)(0x422E0410UL))) +#define bM4_TMR41_OCSRW_OCIEL (*((volatile unsigned int*)(0x422E0414UL))) +#define bM4_TMR41_OCSRW_OCFH (*((volatile unsigned int*)(0x422E0418UL))) +#define bM4_TMR41_OCSRW_OCFL (*((volatile unsigned int*)(0x422E041CUL))) +#define bM4_TMR41_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x422E0440UL))) +#define bM4_TMR41_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x422E0444UL))) +#define bM4_TMR41_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x422E0448UL))) +#define bM4_TMR41_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x422E044CUL))) +#define bM4_TMR41_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x422E0450UL))) +#define bM4_TMR41_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x422E0454UL))) +#define bM4_TMR41_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x422E0458UL))) +#define bM4_TMR41_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x422E045CUL))) +#define bM4_TMR41_OCERW_LMCH (*((volatile unsigned int*)(0x422E0460UL))) +#define bM4_TMR41_OCERW_LMCL (*((volatile unsigned int*)(0x422E0464UL))) +#define bM4_TMR41_OCERW_LMMH (*((volatile unsigned int*)(0x422E0468UL))) +#define bM4_TMR41_OCERW_LMML (*((volatile unsigned int*)(0x422E046CUL))) +#define bM4_TMR41_OCERW_MCECH (*((volatile unsigned int*)(0x422E0470UL))) +#define bM4_TMR41_OCERW_MCECL (*((volatile unsigned int*)(0x422E0474UL))) +#define bM4_TMR41_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x422E0480UL))) +#define bM4_TMR41_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x422E0484UL))) +#define bM4_TMR41_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x422E0488UL))) +#define bM4_TMR41_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x422E048CUL))) +#define bM4_TMR41_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x422E0490UL))) +#define bM4_TMR41_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x422E0494UL))) +#define bM4_TMR41_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x422E0498UL))) +#define bM4_TMR41_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x422E049CUL))) +#define bM4_TMR41_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x422E04A0UL))) +#define bM4_TMR41_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x422E04A4UL))) +#define bM4_TMR41_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x422E04A8UL))) +#define bM4_TMR41_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x422E04ACUL))) +#define bM4_TMR41_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x422E04B0UL))) +#define bM4_TMR41_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x422E04B4UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x422E04B8UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x422E04BCUL))) +#define bM4_TMR41_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x422E0500UL))) +#define bM4_TMR41_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x422E0504UL))) +#define bM4_TMR41_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x422E0508UL))) +#define bM4_TMR41_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x422E050CUL))) +#define bM4_TMR41_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x422E0510UL))) +#define bM4_TMR41_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x422E0514UL))) +#define bM4_TMR41_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x422E0518UL))) +#define bM4_TMR41_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x422E051CUL))) +#define bM4_TMR41_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x422E0520UL))) +#define bM4_TMR41_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x422E0524UL))) +#define bM4_TMR41_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x422E0528UL))) +#define bM4_TMR41_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x422E052CUL))) +#define bM4_TMR41_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x422E0530UL))) +#define bM4_TMR41_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x422E0534UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x422E0538UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x422E053CUL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0540UL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0544UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0548UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x422E054CUL))) +#define bM4_TMR41_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x422E0550UL))) +#define bM4_TMR41_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x422E0554UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x422E0558UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x422E055CUL))) +#define bM4_TMR41_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x422E0560UL))) +#define bM4_TMR41_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x422E0564UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x422E0568UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x422E056CUL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0570UL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0574UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0578UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x422E057CUL))) +#define bM4_TMR41_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x422E0580UL))) +#define bM4_TMR41_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x422E0584UL))) +#define bM4_TMR41_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x422E0588UL))) +#define bM4_TMR41_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x422E058CUL))) +#define bM4_TMR41_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x422E0590UL))) +#define bM4_TMR41_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x422E0594UL))) +#define bM4_TMR41_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x422E0598UL))) +#define bM4_TMR41_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x422E059CUL))) +#define bM4_TMR41_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x422E05A0UL))) +#define bM4_TMR41_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x422E05A4UL))) +#define bM4_TMR41_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x422E05A8UL))) +#define bM4_TMR41_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x422E05ACUL))) +#define bM4_TMR41_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x422E05B0UL))) +#define bM4_TMR41_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x422E05B4UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x422E05B8UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x422E05BCUL))) +#define bM4_TMR41_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x422E0600UL))) +#define bM4_TMR41_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x422E0604UL))) +#define bM4_TMR41_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x422E0608UL))) +#define bM4_TMR41_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x422E060CUL))) +#define bM4_TMR41_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x422E0610UL))) +#define bM4_TMR41_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x422E0614UL))) +#define bM4_TMR41_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x422E0618UL))) +#define bM4_TMR41_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x422E061CUL))) +#define bM4_TMR41_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x422E0620UL))) +#define bM4_TMR41_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x422E0624UL))) +#define bM4_TMR41_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x422E0628UL))) +#define bM4_TMR41_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x422E062CUL))) +#define bM4_TMR41_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x422E0630UL))) +#define bM4_TMR41_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x422E0634UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x422E0638UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x422E063CUL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0640UL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0644UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0648UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x422E064CUL))) +#define bM4_TMR41_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x422E0650UL))) +#define bM4_TMR41_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x422E0654UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x422E0658UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x422E065CUL))) +#define bM4_TMR41_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x422E0660UL))) +#define bM4_TMR41_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x422E0664UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x422E0668UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x422E066CUL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0670UL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0674UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0678UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x422E067CUL))) +#define bM4_TMR41_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x422E0680UL))) +#define bM4_TMR41_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x422E0684UL))) +#define bM4_TMR41_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x422E0688UL))) +#define bM4_TMR41_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x422E068CUL))) +#define bM4_TMR41_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x422E0690UL))) +#define bM4_TMR41_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x422E0694UL))) +#define bM4_TMR41_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x422E0698UL))) +#define bM4_TMR41_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x422E069CUL))) +#define bM4_TMR41_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x422E06A0UL))) +#define bM4_TMR41_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x422E06A4UL))) +#define bM4_TMR41_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x422E06A8UL))) +#define bM4_TMR41_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x422E06ACUL))) +#define bM4_TMR41_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x422E06B0UL))) +#define bM4_TMR41_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x422E06B4UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x422E06B8UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x422E06BCUL))) +#define bM4_TMR41_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x422E0700UL))) +#define bM4_TMR41_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x422E0704UL))) +#define bM4_TMR41_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x422E0708UL))) +#define bM4_TMR41_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x422E070CUL))) +#define bM4_TMR41_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x422E0710UL))) +#define bM4_TMR41_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x422E0714UL))) +#define bM4_TMR41_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x422E0718UL))) +#define bM4_TMR41_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x422E071CUL))) +#define bM4_TMR41_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x422E0720UL))) +#define bM4_TMR41_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x422E0724UL))) +#define bM4_TMR41_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x422E0728UL))) +#define bM4_TMR41_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x422E072CUL))) +#define bM4_TMR41_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x422E0730UL))) +#define bM4_TMR41_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x422E0734UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x422E0738UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x422E073CUL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0740UL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0744UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0748UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x422E074CUL))) +#define bM4_TMR41_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x422E0750UL))) +#define bM4_TMR41_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x422E0754UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x422E0758UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x422E075CUL))) +#define bM4_TMR41_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x422E0760UL))) +#define bM4_TMR41_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x422E0764UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x422E0768UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x422E076CUL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0770UL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0774UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0778UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x422E077CUL))) +#define bM4_TMR41_CCSR_CKDIV0 (*((volatile unsigned int*)(0x422E0900UL))) +#define bM4_TMR41_CCSR_CKDIV1 (*((volatile unsigned int*)(0x422E0904UL))) +#define bM4_TMR41_CCSR_CKDIV2 (*((volatile unsigned int*)(0x422E0908UL))) +#define bM4_TMR41_CCSR_CKDIV3 (*((volatile unsigned int*)(0x422E090CUL))) +#define bM4_TMR41_CCSR_CLEAR (*((volatile unsigned int*)(0x422E0910UL))) +#define bM4_TMR41_CCSR_MODE (*((volatile unsigned int*)(0x422E0914UL))) +#define bM4_TMR41_CCSR_STOP (*((volatile unsigned int*)(0x422E0918UL))) +#define bM4_TMR41_CCSR_BUFEN (*((volatile unsigned int*)(0x422E091CUL))) +#define bM4_TMR41_CCSR_IRQPEN (*((volatile unsigned int*)(0x422E0920UL))) +#define bM4_TMR41_CCSR_IRQPF (*((volatile unsigned int*)(0x422E0924UL))) +#define bM4_TMR41_CCSR_IRQZEN (*((volatile unsigned int*)(0x422E0934UL))) +#define bM4_TMR41_CCSR_IRQZF (*((volatile unsigned int*)(0x422E0938UL))) +#define bM4_TMR41_CCSR_ECKEN (*((volatile unsigned int*)(0x422E093CUL))) +#define bM4_TMR41_CVPR_ZIM0 (*((volatile unsigned int*)(0x422E0940UL))) +#define bM4_TMR41_CVPR_ZIM1 (*((volatile unsigned int*)(0x422E0944UL))) +#define bM4_TMR41_CVPR_ZIM2 (*((volatile unsigned int*)(0x422E0948UL))) +#define bM4_TMR41_CVPR_ZIM3 (*((volatile unsigned int*)(0x422E094CUL))) +#define bM4_TMR41_CVPR_PIM0 (*((volatile unsigned int*)(0x422E0950UL))) +#define bM4_TMR41_CVPR_PIM1 (*((volatile unsigned int*)(0x422E0954UL))) +#define bM4_TMR41_CVPR_PIM2 (*((volatile unsigned int*)(0x422E0958UL))) +#define bM4_TMR41_CVPR_PIM3 (*((volatile unsigned int*)(0x422E095CUL))) +#define bM4_TMR41_CVPR_ZIC0 (*((volatile unsigned int*)(0x422E0960UL))) +#define bM4_TMR41_CVPR_ZIC1 (*((volatile unsigned int*)(0x422E0964UL))) +#define bM4_TMR41_CVPR_ZIC2 (*((volatile unsigned int*)(0x422E0968UL))) +#define bM4_TMR41_CVPR_ZIC3 (*((volatile unsigned int*)(0x422E096CUL))) +#define bM4_TMR41_CVPR_PIC0 (*((volatile unsigned int*)(0x422E0970UL))) +#define bM4_TMR41_CVPR_PIC1 (*((volatile unsigned int*)(0x422E0974UL))) +#define bM4_TMR41_CVPR_PIC2 (*((volatile unsigned int*)(0x422E0978UL))) +#define bM4_TMR41_CVPR_PIC3 (*((volatile unsigned int*)(0x422E097CUL))) +#define bM4_TMR41_POCRU_DIVCK0 (*((volatile unsigned int*)(0x422E1300UL))) +#define bM4_TMR41_POCRU_DIVCK1 (*((volatile unsigned int*)(0x422E1304UL))) +#define bM4_TMR41_POCRU_DIVCK2 (*((volatile unsigned int*)(0x422E1308UL))) +#define bM4_TMR41_POCRU_DIVCK3 (*((volatile unsigned int*)(0x422E130CUL))) +#define bM4_TMR41_POCRU_PWMMD0 (*((volatile unsigned int*)(0x422E1310UL))) +#define bM4_TMR41_POCRU_PWMMD1 (*((volatile unsigned int*)(0x422E1314UL))) +#define bM4_TMR41_POCRU_LVLS0 (*((volatile unsigned int*)(0x422E1318UL))) +#define bM4_TMR41_POCRU_LVLS1 (*((volatile unsigned int*)(0x422E131CUL))) +#define bM4_TMR41_POCRV_DIVCK0 (*((volatile unsigned int*)(0x422E1380UL))) +#define bM4_TMR41_POCRV_DIVCK1 (*((volatile unsigned int*)(0x422E1384UL))) +#define bM4_TMR41_POCRV_DIVCK2 (*((volatile unsigned int*)(0x422E1388UL))) +#define bM4_TMR41_POCRV_DIVCK3 (*((volatile unsigned int*)(0x422E138CUL))) +#define bM4_TMR41_POCRV_PWMMD0 (*((volatile unsigned int*)(0x422E1390UL))) +#define bM4_TMR41_POCRV_PWMMD1 (*((volatile unsigned int*)(0x422E1394UL))) +#define bM4_TMR41_POCRV_LVLS0 (*((volatile unsigned int*)(0x422E1398UL))) +#define bM4_TMR41_POCRV_LVLS1 (*((volatile unsigned int*)(0x422E139CUL))) +#define bM4_TMR41_POCRW_DIVCK0 (*((volatile unsigned int*)(0x422E1400UL))) +#define bM4_TMR41_POCRW_DIVCK1 (*((volatile unsigned int*)(0x422E1404UL))) +#define bM4_TMR41_POCRW_DIVCK2 (*((volatile unsigned int*)(0x422E1408UL))) +#define bM4_TMR41_POCRW_DIVCK3 (*((volatile unsigned int*)(0x422E140CUL))) +#define bM4_TMR41_POCRW_PWMMD0 (*((volatile unsigned int*)(0x422E1410UL))) +#define bM4_TMR41_POCRW_PWMMD1 (*((volatile unsigned int*)(0x422E1414UL))) +#define bM4_TMR41_POCRW_LVLS0 (*((volatile unsigned int*)(0x422E1418UL))) +#define bM4_TMR41_POCRW_LVLS1 (*((volatile unsigned int*)(0x422E141CUL))) +#define bM4_TMR41_RCSR_RTIDU (*((volatile unsigned int*)(0x422E1480UL))) +#define bM4_TMR41_RCSR_RTIDV (*((volatile unsigned int*)(0x422E1484UL))) +#define bM4_TMR41_RCSR_RTIDW (*((volatile unsigned int*)(0x422E1488UL))) +#define bM4_TMR41_RCSR_RTIFU (*((volatile unsigned int*)(0x422E1490UL))) +#define bM4_TMR41_RCSR_RTICU (*((volatile unsigned int*)(0x422E1494UL))) +#define bM4_TMR41_RCSR_RTEU (*((volatile unsigned int*)(0x422E1498UL))) +#define bM4_TMR41_RCSR_RTSU (*((volatile unsigned int*)(0x422E149CUL))) +#define bM4_TMR41_RCSR_RTIFV (*((volatile unsigned int*)(0x422E14A0UL))) +#define bM4_TMR41_RCSR_RTICV (*((volatile unsigned int*)(0x422E14A4UL))) +#define bM4_TMR41_RCSR_RTEV (*((volatile unsigned int*)(0x422E14A8UL))) +#define bM4_TMR41_RCSR_RTSV (*((volatile unsigned int*)(0x422E14ACUL))) +#define bM4_TMR41_RCSR_RTIFW (*((volatile unsigned int*)(0x422E14B0UL))) +#define bM4_TMR41_RCSR_RTICW (*((volatile unsigned int*)(0x422E14B4UL))) +#define bM4_TMR41_RCSR_RTEW (*((volatile unsigned int*)(0x422E14B8UL))) +#define bM4_TMR41_RCSR_RTSW (*((volatile unsigned int*)(0x422E14BCUL))) +#define bM4_TMR41_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x422E1900UL))) +#define bM4_TMR41_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x422E1904UL))) +#define bM4_TMR41_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x422E1908UL))) +#define bM4_TMR41_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x422E190CUL))) +#define bM4_TMR41_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x422E1910UL))) +#define bM4_TMR41_SCSRUH_LMC (*((volatile unsigned int*)(0x422E1914UL))) +#define bM4_TMR41_SCSRUH_EVTMS (*((volatile unsigned int*)(0x422E1920UL))) +#define bM4_TMR41_SCSRUH_EVTDS (*((volatile unsigned int*)(0x422E1924UL))) +#define bM4_TMR41_SCSRUH_DEN (*((volatile unsigned int*)(0x422E1930UL))) +#define bM4_TMR41_SCSRUH_PEN (*((volatile unsigned int*)(0x422E1934UL))) +#define bM4_TMR41_SCSRUH_UEN (*((volatile unsigned int*)(0x422E1938UL))) +#define bM4_TMR41_SCSRUH_ZEN (*((volatile unsigned int*)(0x422E193CUL))) +#define bM4_TMR41_SCMRUH_AMC0 (*((volatile unsigned int*)(0x422E1940UL))) +#define bM4_TMR41_SCMRUH_AMC1 (*((volatile unsigned int*)(0x422E1944UL))) +#define bM4_TMR41_SCMRUH_AMC2 (*((volatile unsigned int*)(0x422E1948UL))) +#define bM4_TMR41_SCMRUH_AMC3 (*((volatile unsigned int*)(0x422E194CUL))) +#define bM4_TMR41_SCMRUH_MZCE (*((volatile unsigned int*)(0x422E1958UL))) +#define bM4_TMR41_SCMRUH_MPCE (*((volatile unsigned int*)(0x422E195CUL))) +#define bM4_TMR41_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x422E1980UL))) +#define bM4_TMR41_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x422E1984UL))) +#define bM4_TMR41_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x422E1988UL))) +#define bM4_TMR41_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x422E198CUL))) +#define bM4_TMR41_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x422E1990UL))) +#define bM4_TMR41_SCSRUL_LMC (*((volatile unsigned int*)(0x422E1994UL))) +#define bM4_TMR41_SCSRUL_EVTMS (*((volatile unsigned int*)(0x422E19A0UL))) +#define bM4_TMR41_SCSRUL_EVTDS (*((volatile unsigned int*)(0x422E19A4UL))) +#define bM4_TMR41_SCSRUL_DEN (*((volatile unsigned int*)(0x422E19B0UL))) +#define bM4_TMR41_SCSRUL_PEN (*((volatile unsigned int*)(0x422E19B4UL))) +#define bM4_TMR41_SCSRUL_UEN (*((volatile unsigned int*)(0x422E19B8UL))) +#define bM4_TMR41_SCSRUL_ZEN (*((volatile unsigned int*)(0x422E19BCUL))) +#define bM4_TMR41_SCMRUL_AMC0 (*((volatile unsigned int*)(0x422E19C0UL))) +#define bM4_TMR41_SCMRUL_AMC1 (*((volatile unsigned int*)(0x422E19C4UL))) +#define bM4_TMR41_SCMRUL_AMC2 (*((volatile unsigned int*)(0x422E19C8UL))) +#define bM4_TMR41_SCMRUL_AMC3 (*((volatile unsigned int*)(0x422E19CCUL))) +#define bM4_TMR41_SCMRUL_MZCE (*((volatile unsigned int*)(0x422E19D8UL))) +#define bM4_TMR41_SCMRUL_MPCE (*((volatile unsigned int*)(0x422E19DCUL))) +#define bM4_TMR41_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x422E1A00UL))) +#define bM4_TMR41_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x422E1A04UL))) +#define bM4_TMR41_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x422E1A08UL))) +#define bM4_TMR41_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x422E1A0CUL))) +#define bM4_TMR41_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x422E1A10UL))) +#define bM4_TMR41_SCSRVH_LMC (*((volatile unsigned int*)(0x422E1A14UL))) +#define bM4_TMR41_SCSRVH_EVTMS (*((volatile unsigned int*)(0x422E1A20UL))) +#define bM4_TMR41_SCSRVH_EVTDS (*((volatile unsigned int*)(0x422E1A24UL))) +#define bM4_TMR41_SCSRVH_DEN (*((volatile unsigned int*)(0x422E1A30UL))) +#define bM4_TMR41_SCSRVH_PEN (*((volatile unsigned int*)(0x422E1A34UL))) +#define bM4_TMR41_SCSRVH_UEN (*((volatile unsigned int*)(0x422E1A38UL))) +#define bM4_TMR41_SCSRVH_ZEN (*((volatile unsigned int*)(0x422E1A3CUL))) +#define bM4_TMR41_SCMRVH_AMC0 (*((volatile unsigned int*)(0x422E1A40UL))) +#define bM4_TMR41_SCMRVH_AMC1 (*((volatile unsigned int*)(0x422E1A44UL))) +#define bM4_TMR41_SCMRVH_AMC2 (*((volatile unsigned int*)(0x422E1A48UL))) +#define bM4_TMR41_SCMRVH_AMC3 (*((volatile unsigned int*)(0x422E1A4CUL))) +#define bM4_TMR41_SCMRVH_MZCE (*((volatile unsigned int*)(0x422E1A58UL))) +#define bM4_TMR41_SCMRVH_MPCE (*((volatile unsigned int*)(0x422E1A5CUL))) +#define bM4_TMR41_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x422E1A80UL))) +#define bM4_TMR41_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x422E1A84UL))) +#define bM4_TMR41_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x422E1A88UL))) +#define bM4_TMR41_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x422E1A8CUL))) +#define bM4_TMR41_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x422E1A90UL))) +#define bM4_TMR41_SCSRVL_LMC (*((volatile unsigned int*)(0x422E1A94UL))) +#define bM4_TMR41_SCSRVL_EVTMS (*((volatile unsigned int*)(0x422E1AA0UL))) +#define bM4_TMR41_SCSRVL_EVTDS (*((volatile unsigned int*)(0x422E1AA4UL))) +#define bM4_TMR41_SCSRVL_DEN (*((volatile unsigned int*)(0x422E1AB0UL))) +#define bM4_TMR41_SCSRVL_PEN (*((volatile unsigned int*)(0x422E1AB4UL))) +#define bM4_TMR41_SCSRVL_UEN (*((volatile unsigned int*)(0x422E1AB8UL))) +#define bM4_TMR41_SCSRVL_ZEN (*((volatile unsigned int*)(0x422E1ABCUL))) +#define bM4_TMR41_SCMRVL_AMC0 (*((volatile unsigned int*)(0x422E1AC0UL))) +#define bM4_TMR41_SCMRVL_AMC1 (*((volatile unsigned int*)(0x422E1AC4UL))) +#define bM4_TMR41_SCMRVL_AMC2 (*((volatile unsigned int*)(0x422E1AC8UL))) +#define bM4_TMR41_SCMRVL_AMC3 (*((volatile unsigned int*)(0x422E1ACCUL))) +#define bM4_TMR41_SCMRVL_MZCE (*((volatile unsigned int*)(0x422E1AD8UL))) +#define bM4_TMR41_SCMRVL_MPCE (*((volatile unsigned int*)(0x422E1ADCUL))) +#define bM4_TMR41_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x422E1B00UL))) +#define bM4_TMR41_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x422E1B04UL))) +#define bM4_TMR41_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x422E1B08UL))) +#define bM4_TMR41_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x422E1B0CUL))) +#define bM4_TMR41_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x422E1B10UL))) +#define bM4_TMR41_SCSRWH_LMC (*((volatile unsigned int*)(0x422E1B14UL))) +#define bM4_TMR41_SCSRWH_EVTMS (*((volatile unsigned int*)(0x422E1B20UL))) +#define bM4_TMR41_SCSRWH_EVTDS (*((volatile unsigned int*)(0x422E1B24UL))) +#define bM4_TMR41_SCSRWH_DEN (*((volatile unsigned int*)(0x422E1B30UL))) +#define bM4_TMR41_SCSRWH_PEN (*((volatile unsigned int*)(0x422E1B34UL))) +#define bM4_TMR41_SCSRWH_UEN (*((volatile unsigned int*)(0x422E1B38UL))) +#define bM4_TMR41_SCSRWH_ZEN (*((volatile unsigned int*)(0x422E1B3CUL))) +#define bM4_TMR41_SCMRWH_AMC0 (*((volatile unsigned int*)(0x422E1B40UL))) +#define bM4_TMR41_SCMRWH_AMC1 (*((volatile unsigned int*)(0x422E1B44UL))) +#define bM4_TMR41_SCMRWH_AMC2 (*((volatile unsigned int*)(0x422E1B48UL))) +#define bM4_TMR41_SCMRWH_AMC3 (*((volatile unsigned int*)(0x422E1B4CUL))) +#define bM4_TMR41_SCMRWH_MZCE (*((volatile unsigned int*)(0x422E1B58UL))) +#define bM4_TMR41_SCMRWH_MPCE (*((volatile unsigned int*)(0x422E1B5CUL))) +#define bM4_TMR41_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x422E1B80UL))) +#define bM4_TMR41_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x422E1B84UL))) +#define bM4_TMR41_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x422E1B88UL))) +#define bM4_TMR41_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x422E1B8CUL))) +#define bM4_TMR41_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x422E1B90UL))) +#define bM4_TMR41_SCSRWL_LMC (*((volatile unsigned int*)(0x422E1B94UL))) +#define bM4_TMR41_SCSRWL_EVTMS (*((volatile unsigned int*)(0x422E1BA0UL))) +#define bM4_TMR41_SCSRWL_EVTDS (*((volatile unsigned int*)(0x422E1BA4UL))) +#define bM4_TMR41_SCSRWL_DEN (*((volatile unsigned int*)(0x422E1BB0UL))) +#define bM4_TMR41_SCSRWL_PEN (*((volatile unsigned int*)(0x422E1BB4UL))) +#define bM4_TMR41_SCSRWL_UEN (*((volatile unsigned int*)(0x422E1BB8UL))) +#define bM4_TMR41_SCSRWL_ZEN (*((volatile unsigned int*)(0x422E1BBCUL))) +#define bM4_TMR41_SCMRWL_AMC0 (*((volatile unsigned int*)(0x422E1BC0UL))) +#define bM4_TMR41_SCMRWL_AMC1 (*((volatile unsigned int*)(0x422E1BC4UL))) +#define bM4_TMR41_SCMRWL_AMC2 (*((volatile unsigned int*)(0x422E1BC8UL))) +#define bM4_TMR41_SCMRWL_AMC3 (*((volatile unsigned int*)(0x422E1BCCUL))) +#define bM4_TMR41_SCMRWL_MZCE (*((volatile unsigned int*)(0x422E1BD8UL))) +#define bM4_TMR41_SCMRWL_MPCE (*((volatile unsigned int*)(0x422E1BDCUL))) +#define bM4_TMR41_ECSR_HOLD (*((volatile unsigned int*)(0x422E1E1CUL))) +#define bM4_TMR42_OCSRU_OCEH (*((volatile unsigned int*)(0x42490300UL))) +#define bM4_TMR42_OCSRU_OCEL (*((volatile unsigned int*)(0x42490304UL))) +#define bM4_TMR42_OCSRU_OCPH (*((volatile unsigned int*)(0x42490308UL))) +#define bM4_TMR42_OCSRU_OCPL (*((volatile unsigned int*)(0x4249030CUL))) +#define bM4_TMR42_OCSRU_OCIEH (*((volatile unsigned int*)(0x42490310UL))) +#define bM4_TMR42_OCSRU_OCIEL (*((volatile unsigned int*)(0x42490314UL))) +#define bM4_TMR42_OCSRU_OCFH (*((volatile unsigned int*)(0x42490318UL))) +#define bM4_TMR42_OCSRU_OCFL (*((volatile unsigned int*)(0x4249031CUL))) +#define bM4_TMR42_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42490340UL))) +#define bM4_TMR42_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42490344UL))) +#define bM4_TMR42_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42490348UL))) +#define bM4_TMR42_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249034CUL))) +#define bM4_TMR42_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42490350UL))) +#define bM4_TMR42_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42490354UL))) +#define bM4_TMR42_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42490358UL))) +#define bM4_TMR42_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249035CUL))) +#define bM4_TMR42_OCERU_LMCH (*((volatile unsigned int*)(0x42490360UL))) +#define bM4_TMR42_OCERU_LMCL (*((volatile unsigned int*)(0x42490364UL))) +#define bM4_TMR42_OCERU_LMMH (*((volatile unsigned int*)(0x42490368UL))) +#define bM4_TMR42_OCERU_LMML (*((volatile unsigned int*)(0x4249036CUL))) +#define bM4_TMR42_OCERU_MCECH (*((volatile unsigned int*)(0x42490370UL))) +#define bM4_TMR42_OCERU_MCECL (*((volatile unsigned int*)(0x42490374UL))) +#define bM4_TMR42_OCSRV_OCEH (*((volatile unsigned int*)(0x42490380UL))) +#define bM4_TMR42_OCSRV_OCEL (*((volatile unsigned int*)(0x42490384UL))) +#define bM4_TMR42_OCSRV_OCPH (*((volatile unsigned int*)(0x42490388UL))) +#define bM4_TMR42_OCSRV_OCPL (*((volatile unsigned int*)(0x4249038CUL))) +#define bM4_TMR42_OCSRV_OCIEH (*((volatile unsigned int*)(0x42490390UL))) +#define bM4_TMR42_OCSRV_OCIEL (*((volatile unsigned int*)(0x42490394UL))) +#define bM4_TMR42_OCSRV_OCFH (*((volatile unsigned int*)(0x42490398UL))) +#define bM4_TMR42_OCSRV_OCFL (*((volatile unsigned int*)(0x4249039CUL))) +#define bM4_TMR42_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424903C0UL))) +#define bM4_TMR42_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424903C4UL))) +#define bM4_TMR42_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424903C8UL))) +#define bM4_TMR42_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424903CCUL))) +#define bM4_TMR42_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424903D0UL))) +#define bM4_TMR42_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424903D4UL))) +#define bM4_TMR42_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424903D8UL))) +#define bM4_TMR42_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424903DCUL))) +#define bM4_TMR42_OCERV_LMCH (*((volatile unsigned int*)(0x424903E0UL))) +#define bM4_TMR42_OCERV_LMCL (*((volatile unsigned int*)(0x424903E4UL))) +#define bM4_TMR42_OCERV_LMMH (*((volatile unsigned int*)(0x424903E8UL))) +#define bM4_TMR42_OCERV_LMML (*((volatile unsigned int*)(0x424903ECUL))) +#define bM4_TMR42_OCERV_MCECH (*((volatile unsigned int*)(0x424903F0UL))) +#define bM4_TMR42_OCERV_MCECL (*((volatile unsigned int*)(0x424903F4UL))) +#define bM4_TMR42_OCSRW_OCEH (*((volatile unsigned int*)(0x42490400UL))) +#define bM4_TMR42_OCSRW_OCEL (*((volatile unsigned int*)(0x42490404UL))) +#define bM4_TMR42_OCSRW_OCPH (*((volatile unsigned int*)(0x42490408UL))) +#define bM4_TMR42_OCSRW_OCPL (*((volatile unsigned int*)(0x4249040CUL))) +#define bM4_TMR42_OCSRW_OCIEH (*((volatile unsigned int*)(0x42490410UL))) +#define bM4_TMR42_OCSRW_OCIEL (*((volatile unsigned int*)(0x42490414UL))) +#define bM4_TMR42_OCSRW_OCFH (*((volatile unsigned int*)(0x42490418UL))) +#define bM4_TMR42_OCSRW_OCFL (*((volatile unsigned int*)(0x4249041CUL))) +#define bM4_TMR42_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42490440UL))) +#define bM4_TMR42_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42490444UL))) +#define bM4_TMR42_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42490448UL))) +#define bM4_TMR42_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249044CUL))) +#define bM4_TMR42_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42490450UL))) +#define bM4_TMR42_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42490454UL))) +#define bM4_TMR42_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42490458UL))) +#define bM4_TMR42_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249045CUL))) +#define bM4_TMR42_OCERW_LMCH (*((volatile unsigned int*)(0x42490460UL))) +#define bM4_TMR42_OCERW_LMCL (*((volatile unsigned int*)(0x42490464UL))) +#define bM4_TMR42_OCERW_LMMH (*((volatile unsigned int*)(0x42490468UL))) +#define bM4_TMR42_OCERW_LMML (*((volatile unsigned int*)(0x4249046CUL))) +#define bM4_TMR42_OCERW_MCECH (*((volatile unsigned int*)(0x42490470UL))) +#define bM4_TMR42_OCERW_MCECL (*((volatile unsigned int*)(0x42490474UL))) +#define bM4_TMR42_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42490480UL))) +#define bM4_TMR42_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42490484UL))) +#define bM4_TMR42_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42490488UL))) +#define bM4_TMR42_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249048CUL))) +#define bM4_TMR42_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42490490UL))) +#define bM4_TMR42_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42490494UL))) +#define bM4_TMR42_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42490498UL))) +#define bM4_TMR42_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249049CUL))) +#define bM4_TMR42_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424904A0UL))) +#define bM4_TMR42_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424904A4UL))) +#define bM4_TMR42_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424904A8UL))) +#define bM4_TMR42_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424904ACUL))) +#define bM4_TMR42_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424904B0UL))) +#define bM4_TMR42_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424904B4UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424904B8UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424904BCUL))) +#define bM4_TMR42_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42490500UL))) +#define bM4_TMR42_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42490504UL))) +#define bM4_TMR42_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42490508UL))) +#define bM4_TMR42_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249050CUL))) +#define bM4_TMR42_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42490510UL))) +#define bM4_TMR42_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42490514UL))) +#define bM4_TMR42_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42490518UL))) +#define bM4_TMR42_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249051CUL))) +#define bM4_TMR42_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42490520UL))) +#define bM4_TMR42_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42490524UL))) +#define bM4_TMR42_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42490528UL))) +#define bM4_TMR42_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249052CUL))) +#define bM4_TMR42_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42490530UL))) +#define bM4_TMR42_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42490534UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42490538UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249053CUL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42490540UL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42490544UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42490548UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249054CUL))) +#define bM4_TMR42_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42490550UL))) +#define bM4_TMR42_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42490554UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42490558UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249055CUL))) +#define bM4_TMR42_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42490560UL))) +#define bM4_TMR42_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42490564UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42490568UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249056CUL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42490570UL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42490574UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42490578UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249057CUL))) +#define bM4_TMR42_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42490580UL))) +#define bM4_TMR42_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42490584UL))) +#define bM4_TMR42_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42490588UL))) +#define bM4_TMR42_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249058CUL))) +#define bM4_TMR42_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42490590UL))) +#define bM4_TMR42_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42490594UL))) +#define bM4_TMR42_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42490598UL))) +#define bM4_TMR42_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249059CUL))) +#define bM4_TMR42_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424905A0UL))) +#define bM4_TMR42_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424905A4UL))) +#define bM4_TMR42_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424905A8UL))) +#define bM4_TMR42_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424905ACUL))) +#define bM4_TMR42_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424905B0UL))) +#define bM4_TMR42_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424905B4UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424905B8UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424905BCUL))) +#define bM4_TMR42_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42490600UL))) +#define bM4_TMR42_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42490604UL))) +#define bM4_TMR42_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42490608UL))) +#define bM4_TMR42_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249060CUL))) +#define bM4_TMR42_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42490610UL))) +#define bM4_TMR42_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42490614UL))) +#define bM4_TMR42_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42490618UL))) +#define bM4_TMR42_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249061CUL))) +#define bM4_TMR42_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42490620UL))) +#define bM4_TMR42_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42490624UL))) +#define bM4_TMR42_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42490628UL))) +#define bM4_TMR42_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249062CUL))) +#define bM4_TMR42_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42490630UL))) +#define bM4_TMR42_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42490634UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42490638UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249063CUL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42490640UL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42490644UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42490648UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249064CUL))) +#define bM4_TMR42_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42490650UL))) +#define bM4_TMR42_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42490654UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42490658UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249065CUL))) +#define bM4_TMR42_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42490660UL))) +#define bM4_TMR42_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42490664UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42490668UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249066CUL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42490670UL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42490674UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42490678UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249067CUL))) +#define bM4_TMR42_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42490680UL))) +#define bM4_TMR42_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42490684UL))) +#define bM4_TMR42_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42490688UL))) +#define bM4_TMR42_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249068CUL))) +#define bM4_TMR42_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42490690UL))) +#define bM4_TMR42_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42490694UL))) +#define bM4_TMR42_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42490698UL))) +#define bM4_TMR42_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249069CUL))) +#define bM4_TMR42_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424906A0UL))) +#define bM4_TMR42_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424906A4UL))) +#define bM4_TMR42_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424906A8UL))) +#define bM4_TMR42_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424906ACUL))) +#define bM4_TMR42_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424906B0UL))) +#define bM4_TMR42_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424906B4UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424906B8UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424906BCUL))) +#define bM4_TMR42_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42490700UL))) +#define bM4_TMR42_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42490704UL))) +#define bM4_TMR42_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42490708UL))) +#define bM4_TMR42_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249070CUL))) +#define bM4_TMR42_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42490710UL))) +#define bM4_TMR42_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42490714UL))) +#define bM4_TMR42_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42490718UL))) +#define bM4_TMR42_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249071CUL))) +#define bM4_TMR42_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42490720UL))) +#define bM4_TMR42_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42490724UL))) +#define bM4_TMR42_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42490728UL))) +#define bM4_TMR42_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249072CUL))) +#define bM4_TMR42_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42490730UL))) +#define bM4_TMR42_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42490734UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42490738UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249073CUL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42490740UL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42490744UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42490748UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249074CUL))) +#define bM4_TMR42_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42490750UL))) +#define bM4_TMR42_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42490754UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42490758UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249075CUL))) +#define bM4_TMR42_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42490760UL))) +#define bM4_TMR42_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42490764UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42490768UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249076CUL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42490770UL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42490774UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42490778UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249077CUL))) +#define bM4_TMR42_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42490900UL))) +#define bM4_TMR42_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42490904UL))) +#define bM4_TMR42_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42490908UL))) +#define bM4_TMR42_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249090CUL))) +#define bM4_TMR42_CCSR_CLEAR (*((volatile unsigned int*)(0x42490910UL))) +#define bM4_TMR42_CCSR_MODE (*((volatile unsigned int*)(0x42490914UL))) +#define bM4_TMR42_CCSR_STOP (*((volatile unsigned int*)(0x42490918UL))) +#define bM4_TMR42_CCSR_BUFEN (*((volatile unsigned int*)(0x4249091CUL))) +#define bM4_TMR42_CCSR_IRQPEN (*((volatile unsigned int*)(0x42490920UL))) +#define bM4_TMR42_CCSR_IRQPF (*((volatile unsigned int*)(0x42490924UL))) +#define bM4_TMR42_CCSR_IRQZEN (*((volatile unsigned int*)(0x42490934UL))) +#define bM4_TMR42_CCSR_IRQZF (*((volatile unsigned int*)(0x42490938UL))) +#define bM4_TMR42_CCSR_ECKEN (*((volatile unsigned int*)(0x4249093CUL))) +#define bM4_TMR42_CVPR_ZIM0 (*((volatile unsigned int*)(0x42490940UL))) +#define bM4_TMR42_CVPR_ZIM1 (*((volatile unsigned int*)(0x42490944UL))) +#define bM4_TMR42_CVPR_ZIM2 (*((volatile unsigned int*)(0x42490948UL))) +#define bM4_TMR42_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249094CUL))) +#define bM4_TMR42_CVPR_PIM0 (*((volatile unsigned int*)(0x42490950UL))) +#define bM4_TMR42_CVPR_PIM1 (*((volatile unsigned int*)(0x42490954UL))) +#define bM4_TMR42_CVPR_PIM2 (*((volatile unsigned int*)(0x42490958UL))) +#define bM4_TMR42_CVPR_PIM3 (*((volatile unsigned int*)(0x4249095CUL))) +#define bM4_TMR42_CVPR_ZIC0 (*((volatile unsigned int*)(0x42490960UL))) +#define bM4_TMR42_CVPR_ZIC1 (*((volatile unsigned int*)(0x42490964UL))) +#define bM4_TMR42_CVPR_ZIC2 (*((volatile unsigned int*)(0x42490968UL))) +#define bM4_TMR42_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249096CUL))) +#define bM4_TMR42_CVPR_PIC0 (*((volatile unsigned int*)(0x42490970UL))) +#define bM4_TMR42_CVPR_PIC1 (*((volatile unsigned int*)(0x42490974UL))) +#define bM4_TMR42_CVPR_PIC2 (*((volatile unsigned int*)(0x42490978UL))) +#define bM4_TMR42_CVPR_PIC3 (*((volatile unsigned int*)(0x4249097CUL))) +#define bM4_TMR42_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42491300UL))) +#define bM4_TMR42_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42491304UL))) +#define bM4_TMR42_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42491308UL))) +#define bM4_TMR42_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249130CUL))) +#define bM4_TMR42_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42491310UL))) +#define bM4_TMR42_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42491314UL))) +#define bM4_TMR42_POCRU_LVLS0 (*((volatile unsigned int*)(0x42491318UL))) +#define bM4_TMR42_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249131CUL))) +#define bM4_TMR42_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42491380UL))) +#define bM4_TMR42_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42491384UL))) +#define bM4_TMR42_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42491388UL))) +#define bM4_TMR42_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249138CUL))) +#define bM4_TMR42_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42491390UL))) +#define bM4_TMR42_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42491394UL))) +#define bM4_TMR42_POCRV_LVLS0 (*((volatile unsigned int*)(0x42491398UL))) +#define bM4_TMR42_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249139CUL))) +#define bM4_TMR42_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42491400UL))) +#define bM4_TMR42_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42491404UL))) +#define bM4_TMR42_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42491408UL))) +#define bM4_TMR42_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249140CUL))) +#define bM4_TMR42_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42491410UL))) +#define bM4_TMR42_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42491414UL))) +#define bM4_TMR42_POCRW_LVLS0 (*((volatile unsigned int*)(0x42491418UL))) +#define bM4_TMR42_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249141CUL))) +#define bM4_TMR42_RCSR_RTIDU (*((volatile unsigned int*)(0x42491480UL))) +#define bM4_TMR42_RCSR_RTIDV (*((volatile unsigned int*)(0x42491484UL))) +#define bM4_TMR42_RCSR_RTIDW (*((volatile unsigned int*)(0x42491488UL))) +#define bM4_TMR42_RCSR_RTIFU (*((volatile unsigned int*)(0x42491490UL))) +#define bM4_TMR42_RCSR_RTICU (*((volatile unsigned int*)(0x42491494UL))) +#define bM4_TMR42_RCSR_RTEU (*((volatile unsigned int*)(0x42491498UL))) +#define bM4_TMR42_RCSR_RTSU (*((volatile unsigned int*)(0x4249149CUL))) +#define bM4_TMR42_RCSR_RTIFV (*((volatile unsigned int*)(0x424914A0UL))) +#define bM4_TMR42_RCSR_RTICV (*((volatile unsigned int*)(0x424914A4UL))) +#define bM4_TMR42_RCSR_RTEV (*((volatile unsigned int*)(0x424914A8UL))) +#define bM4_TMR42_RCSR_RTSV (*((volatile unsigned int*)(0x424914ACUL))) +#define bM4_TMR42_RCSR_RTIFW (*((volatile unsigned int*)(0x424914B0UL))) +#define bM4_TMR42_RCSR_RTICW (*((volatile unsigned int*)(0x424914B4UL))) +#define bM4_TMR42_RCSR_RTEW (*((volatile unsigned int*)(0x424914B8UL))) +#define bM4_TMR42_RCSR_RTSW (*((volatile unsigned int*)(0x424914BCUL))) +#define bM4_TMR42_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42491900UL))) +#define bM4_TMR42_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42491904UL))) +#define bM4_TMR42_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42491908UL))) +#define bM4_TMR42_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249190CUL))) +#define bM4_TMR42_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42491910UL))) +#define bM4_TMR42_SCSRUH_LMC (*((volatile unsigned int*)(0x42491914UL))) +#define bM4_TMR42_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42491920UL))) +#define bM4_TMR42_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42491924UL))) +#define bM4_TMR42_SCSRUH_DEN (*((volatile unsigned int*)(0x42491930UL))) +#define bM4_TMR42_SCSRUH_PEN (*((volatile unsigned int*)(0x42491934UL))) +#define bM4_TMR42_SCSRUH_UEN (*((volatile unsigned int*)(0x42491938UL))) +#define bM4_TMR42_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249193CUL))) +#define bM4_TMR42_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42491940UL))) +#define bM4_TMR42_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42491944UL))) +#define bM4_TMR42_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42491948UL))) +#define bM4_TMR42_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249194CUL))) +#define bM4_TMR42_SCMRUH_MZCE (*((volatile unsigned int*)(0x42491958UL))) +#define bM4_TMR42_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249195CUL))) +#define bM4_TMR42_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42491980UL))) +#define bM4_TMR42_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42491984UL))) +#define bM4_TMR42_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42491988UL))) +#define bM4_TMR42_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249198CUL))) +#define bM4_TMR42_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42491990UL))) +#define bM4_TMR42_SCSRUL_LMC (*((volatile unsigned int*)(0x42491994UL))) +#define bM4_TMR42_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424919A0UL))) +#define bM4_TMR42_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424919A4UL))) +#define bM4_TMR42_SCSRUL_DEN (*((volatile unsigned int*)(0x424919B0UL))) +#define bM4_TMR42_SCSRUL_PEN (*((volatile unsigned int*)(0x424919B4UL))) +#define bM4_TMR42_SCSRUL_UEN (*((volatile unsigned int*)(0x424919B8UL))) +#define bM4_TMR42_SCSRUL_ZEN (*((volatile unsigned int*)(0x424919BCUL))) +#define bM4_TMR42_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424919C0UL))) +#define bM4_TMR42_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424919C4UL))) +#define bM4_TMR42_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424919C8UL))) +#define bM4_TMR42_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424919CCUL))) +#define bM4_TMR42_SCMRUL_MZCE (*((volatile unsigned int*)(0x424919D8UL))) +#define bM4_TMR42_SCMRUL_MPCE (*((volatile unsigned int*)(0x424919DCUL))) +#define bM4_TMR42_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42491A00UL))) +#define bM4_TMR42_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42491A04UL))) +#define bM4_TMR42_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42491A08UL))) +#define bM4_TMR42_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42491A0CUL))) +#define bM4_TMR42_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42491A10UL))) +#define bM4_TMR42_SCSRVH_LMC (*((volatile unsigned int*)(0x42491A14UL))) +#define bM4_TMR42_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42491A20UL))) +#define bM4_TMR42_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42491A24UL))) +#define bM4_TMR42_SCSRVH_DEN (*((volatile unsigned int*)(0x42491A30UL))) +#define bM4_TMR42_SCSRVH_PEN (*((volatile unsigned int*)(0x42491A34UL))) +#define bM4_TMR42_SCSRVH_UEN (*((volatile unsigned int*)(0x42491A38UL))) +#define bM4_TMR42_SCSRVH_ZEN (*((volatile unsigned int*)(0x42491A3CUL))) +#define bM4_TMR42_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42491A40UL))) +#define bM4_TMR42_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42491A44UL))) +#define bM4_TMR42_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42491A48UL))) +#define bM4_TMR42_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42491A4CUL))) +#define bM4_TMR42_SCMRVH_MZCE (*((volatile unsigned int*)(0x42491A58UL))) +#define bM4_TMR42_SCMRVH_MPCE (*((volatile unsigned int*)(0x42491A5CUL))) +#define bM4_TMR42_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42491A80UL))) +#define bM4_TMR42_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42491A84UL))) +#define bM4_TMR42_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42491A88UL))) +#define bM4_TMR42_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42491A8CUL))) +#define bM4_TMR42_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42491A90UL))) +#define bM4_TMR42_SCSRVL_LMC (*((volatile unsigned int*)(0x42491A94UL))) +#define bM4_TMR42_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42491AA0UL))) +#define bM4_TMR42_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42491AA4UL))) +#define bM4_TMR42_SCSRVL_DEN (*((volatile unsigned int*)(0x42491AB0UL))) +#define bM4_TMR42_SCSRVL_PEN (*((volatile unsigned int*)(0x42491AB4UL))) +#define bM4_TMR42_SCSRVL_UEN (*((volatile unsigned int*)(0x42491AB8UL))) +#define bM4_TMR42_SCSRVL_ZEN (*((volatile unsigned int*)(0x42491ABCUL))) +#define bM4_TMR42_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42491AC0UL))) +#define bM4_TMR42_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42491AC4UL))) +#define bM4_TMR42_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42491AC8UL))) +#define bM4_TMR42_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42491ACCUL))) +#define bM4_TMR42_SCMRVL_MZCE (*((volatile unsigned int*)(0x42491AD8UL))) +#define bM4_TMR42_SCMRVL_MPCE (*((volatile unsigned int*)(0x42491ADCUL))) +#define bM4_TMR42_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42491B00UL))) +#define bM4_TMR42_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42491B04UL))) +#define bM4_TMR42_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42491B08UL))) +#define bM4_TMR42_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42491B0CUL))) +#define bM4_TMR42_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42491B10UL))) +#define bM4_TMR42_SCSRWH_LMC (*((volatile unsigned int*)(0x42491B14UL))) +#define bM4_TMR42_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42491B20UL))) +#define bM4_TMR42_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42491B24UL))) +#define bM4_TMR42_SCSRWH_DEN (*((volatile unsigned int*)(0x42491B30UL))) +#define bM4_TMR42_SCSRWH_PEN (*((volatile unsigned int*)(0x42491B34UL))) +#define bM4_TMR42_SCSRWH_UEN (*((volatile unsigned int*)(0x42491B38UL))) +#define bM4_TMR42_SCSRWH_ZEN (*((volatile unsigned int*)(0x42491B3CUL))) +#define bM4_TMR42_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42491B40UL))) +#define bM4_TMR42_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42491B44UL))) +#define bM4_TMR42_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42491B48UL))) +#define bM4_TMR42_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42491B4CUL))) +#define bM4_TMR42_SCMRWH_MZCE (*((volatile unsigned int*)(0x42491B58UL))) +#define bM4_TMR42_SCMRWH_MPCE (*((volatile unsigned int*)(0x42491B5CUL))) +#define bM4_TMR42_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42491B80UL))) +#define bM4_TMR42_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42491B84UL))) +#define bM4_TMR42_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42491B88UL))) +#define bM4_TMR42_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42491B8CUL))) +#define bM4_TMR42_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42491B90UL))) +#define bM4_TMR42_SCSRWL_LMC (*((volatile unsigned int*)(0x42491B94UL))) +#define bM4_TMR42_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42491BA0UL))) +#define bM4_TMR42_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42491BA4UL))) +#define bM4_TMR42_SCSRWL_DEN (*((volatile unsigned int*)(0x42491BB0UL))) +#define bM4_TMR42_SCSRWL_PEN (*((volatile unsigned int*)(0x42491BB4UL))) +#define bM4_TMR42_SCSRWL_UEN (*((volatile unsigned int*)(0x42491BB8UL))) +#define bM4_TMR42_SCSRWL_ZEN (*((volatile unsigned int*)(0x42491BBCUL))) +#define bM4_TMR42_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42491BC0UL))) +#define bM4_TMR42_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42491BC4UL))) +#define bM4_TMR42_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42491BC8UL))) +#define bM4_TMR42_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42491BCCUL))) +#define bM4_TMR42_SCMRWL_MZCE (*((volatile unsigned int*)(0x42491BD8UL))) +#define bM4_TMR42_SCMRWL_MPCE (*((volatile unsigned int*)(0x42491BDCUL))) +#define bM4_TMR42_ECSR_HOLD (*((volatile unsigned int*)(0x42491E1CUL))) +#define bM4_TMR43_OCSRU_OCEH (*((volatile unsigned int*)(0x42498300UL))) +#define bM4_TMR43_OCSRU_OCEL (*((volatile unsigned int*)(0x42498304UL))) +#define bM4_TMR43_OCSRU_OCPH (*((volatile unsigned int*)(0x42498308UL))) +#define bM4_TMR43_OCSRU_OCPL (*((volatile unsigned int*)(0x4249830CUL))) +#define bM4_TMR43_OCSRU_OCIEH (*((volatile unsigned int*)(0x42498310UL))) +#define bM4_TMR43_OCSRU_OCIEL (*((volatile unsigned int*)(0x42498314UL))) +#define bM4_TMR43_OCSRU_OCFH (*((volatile unsigned int*)(0x42498318UL))) +#define bM4_TMR43_OCSRU_OCFL (*((volatile unsigned int*)(0x4249831CUL))) +#define bM4_TMR43_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42498340UL))) +#define bM4_TMR43_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42498344UL))) +#define bM4_TMR43_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42498348UL))) +#define bM4_TMR43_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249834CUL))) +#define bM4_TMR43_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42498350UL))) +#define bM4_TMR43_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42498354UL))) +#define bM4_TMR43_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42498358UL))) +#define bM4_TMR43_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249835CUL))) +#define bM4_TMR43_OCERU_LMCH (*((volatile unsigned int*)(0x42498360UL))) +#define bM4_TMR43_OCERU_LMCL (*((volatile unsigned int*)(0x42498364UL))) +#define bM4_TMR43_OCERU_LMMH (*((volatile unsigned int*)(0x42498368UL))) +#define bM4_TMR43_OCERU_LMML (*((volatile unsigned int*)(0x4249836CUL))) +#define bM4_TMR43_OCERU_MCECH (*((volatile unsigned int*)(0x42498370UL))) +#define bM4_TMR43_OCERU_MCECL (*((volatile unsigned int*)(0x42498374UL))) +#define bM4_TMR43_OCSRV_OCEH (*((volatile unsigned int*)(0x42498380UL))) +#define bM4_TMR43_OCSRV_OCEL (*((volatile unsigned int*)(0x42498384UL))) +#define bM4_TMR43_OCSRV_OCPH (*((volatile unsigned int*)(0x42498388UL))) +#define bM4_TMR43_OCSRV_OCPL (*((volatile unsigned int*)(0x4249838CUL))) +#define bM4_TMR43_OCSRV_OCIEH (*((volatile unsigned int*)(0x42498390UL))) +#define bM4_TMR43_OCSRV_OCIEL (*((volatile unsigned int*)(0x42498394UL))) +#define bM4_TMR43_OCSRV_OCFH (*((volatile unsigned int*)(0x42498398UL))) +#define bM4_TMR43_OCSRV_OCFL (*((volatile unsigned int*)(0x4249839CUL))) +#define bM4_TMR43_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424983C0UL))) +#define bM4_TMR43_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424983C4UL))) +#define bM4_TMR43_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424983C8UL))) +#define bM4_TMR43_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424983CCUL))) +#define bM4_TMR43_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424983D0UL))) +#define bM4_TMR43_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424983D4UL))) +#define bM4_TMR43_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424983D8UL))) +#define bM4_TMR43_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424983DCUL))) +#define bM4_TMR43_OCERV_LMCH (*((volatile unsigned int*)(0x424983E0UL))) +#define bM4_TMR43_OCERV_LMCL (*((volatile unsigned int*)(0x424983E4UL))) +#define bM4_TMR43_OCERV_LMMH (*((volatile unsigned int*)(0x424983E8UL))) +#define bM4_TMR43_OCERV_LMML (*((volatile unsigned int*)(0x424983ECUL))) +#define bM4_TMR43_OCERV_MCECH (*((volatile unsigned int*)(0x424983F0UL))) +#define bM4_TMR43_OCERV_MCECL (*((volatile unsigned int*)(0x424983F4UL))) +#define bM4_TMR43_OCSRW_OCEH (*((volatile unsigned int*)(0x42498400UL))) +#define bM4_TMR43_OCSRW_OCEL (*((volatile unsigned int*)(0x42498404UL))) +#define bM4_TMR43_OCSRW_OCPH (*((volatile unsigned int*)(0x42498408UL))) +#define bM4_TMR43_OCSRW_OCPL (*((volatile unsigned int*)(0x4249840CUL))) +#define bM4_TMR43_OCSRW_OCIEH (*((volatile unsigned int*)(0x42498410UL))) +#define bM4_TMR43_OCSRW_OCIEL (*((volatile unsigned int*)(0x42498414UL))) +#define bM4_TMR43_OCSRW_OCFH (*((volatile unsigned int*)(0x42498418UL))) +#define bM4_TMR43_OCSRW_OCFL (*((volatile unsigned int*)(0x4249841CUL))) +#define bM4_TMR43_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42498440UL))) +#define bM4_TMR43_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42498444UL))) +#define bM4_TMR43_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42498448UL))) +#define bM4_TMR43_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249844CUL))) +#define bM4_TMR43_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42498450UL))) +#define bM4_TMR43_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42498454UL))) +#define bM4_TMR43_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42498458UL))) +#define bM4_TMR43_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249845CUL))) +#define bM4_TMR43_OCERW_LMCH (*((volatile unsigned int*)(0x42498460UL))) +#define bM4_TMR43_OCERW_LMCL (*((volatile unsigned int*)(0x42498464UL))) +#define bM4_TMR43_OCERW_LMMH (*((volatile unsigned int*)(0x42498468UL))) +#define bM4_TMR43_OCERW_LMML (*((volatile unsigned int*)(0x4249846CUL))) +#define bM4_TMR43_OCERW_MCECH (*((volatile unsigned int*)(0x42498470UL))) +#define bM4_TMR43_OCERW_MCECL (*((volatile unsigned int*)(0x42498474UL))) +#define bM4_TMR43_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42498480UL))) +#define bM4_TMR43_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42498484UL))) +#define bM4_TMR43_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42498488UL))) +#define bM4_TMR43_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249848CUL))) +#define bM4_TMR43_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42498490UL))) +#define bM4_TMR43_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42498494UL))) +#define bM4_TMR43_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42498498UL))) +#define bM4_TMR43_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249849CUL))) +#define bM4_TMR43_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424984A0UL))) +#define bM4_TMR43_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424984A4UL))) +#define bM4_TMR43_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424984A8UL))) +#define bM4_TMR43_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424984ACUL))) +#define bM4_TMR43_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424984B0UL))) +#define bM4_TMR43_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424984B4UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424984B8UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424984BCUL))) +#define bM4_TMR43_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42498500UL))) +#define bM4_TMR43_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42498504UL))) +#define bM4_TMR43_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42498508UL))) +#define bM4_TMR43_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249850CUL))) +#define bM4_TMR43_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42498510UL))) +#define bM4_TMR43_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42498514UL))) +#define bM4_TMR43_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42498518UL))) +#define bM4_TMR43_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249851CUL))) +#define bM4_TMR43_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42498520UL))) +#define bM4_TMR43_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42498524UL))) +#define bM4_TMR43_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42498528UL))) +#define bM4_TMR43_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249852CUL))) +#define bM4_TMR43_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42498530UL))) +#define bM4_TMR43_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42498534UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42498538UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249853CUL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42498540UL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42498544UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42498548UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249854CUL))) +#define bM4_TMR43_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42498550UL))) +#define bM4_TMR43_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42498554UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42498558UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249855CUL))) +#define bM4_TMR43_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42498560UL))) +#define bM4_TMR43_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42498564UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42498568UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249856CUL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42498570UL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42498574UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42498578UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249857CUL))) +#define bM4_TMR43_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42498580UL))) +#define bM4_TMR43_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42498584UL))) +#define bM4_TMR43_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42498588UL))) +#define bM4_TMR43_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249858CUL))) +#define bM4_TMR43_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42498590UL))) +#define bM4_TMR43_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42498594UL))) +#define bM4_TMR43_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42498598UL))) +#define bM4_TMR43_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249859CUL))) +#define bM4_TMR43_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424985A0UL))) +#define bM4_TMR43_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424985A4UL))) +#define bM4_TMR43_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424985A8UL))) +#define bM4_TMR43_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424985ACUL))) +#define bM4_TMR43_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424985B0UL))) +#define bM4_TMR43_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424985B4UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424985B8UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424985BCUL))) +#define bM4_TMR43_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42498600UL))) +#define bM4_TMR43_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42498604UL))) +#define bM4_TMR43_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42498608UL))) +#define bM4_TMR43_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249860CUL))) +#define bM4_TMR43_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42498610UL))) +#define bM4_TMR43_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42498614UL))) +#define bM4_TMR43_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42498618UL))) +#define bM4_TMR43_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249861CUL))) +#define bM4_TMR43_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42498620UL))) +#define bM4_TMR43_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42498624UL))) +#define bM4_TMR43_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42498628UL))) +#define bM4_TMR43_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249862CUL))) +#define bM4_TMR43_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42498630UL))) +#define bM4_TMR43_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42498634UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42498638UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249863CUL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42498640UL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42498644UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42498648UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249864CUL))) +#define bM4_TMR43_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42498650UL))) +#define bM4_TMR43_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42498654UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42498658UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249865CUL))) +#define bM4_TMR43_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42498660UL))) +#define bM4_TMR43_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42498664UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42498668UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249866CUL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42498670UL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42498674UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42498678UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249867CUL))) +#define bM4_TMR43_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42498680UL))) +#define bM4_TMR43_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42498684UL))) +#define bM4_TMR43_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42498688UL))) +#define bM4_TMR43_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249868CUL))) +#define bM4_TMR43_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42498690UL))) +#define bM4_TMR43_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42498694UL))) +#define bM4_TMR43_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42498698UL))) +#define bM4_TMR43_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249869CUL))) +#define bM4_TMR43_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424986A0UL))) +#define bM4_TMR43_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424986A4UL))) +#define bM4_TMR43_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424986A8UL))) +#define bM4_TMR43_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424986ACUL))) +#define bM4_TMR43_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424986B0UL))) +#define bM4_TMR43_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424986B4UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424986B8UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424986BCUL))) +#define bM4_TMR43_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42498700UL))) +#define bM4_TMR43_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42498704UL))) +#define bM4_TMR43_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42498708UL))) +#define bM4_TMR43_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249870CUL))) +#define bM4_TMR43_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42498710UL))) +#define bM4_TMR43_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42498714UL))) +#define bM4_TMR43_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42498718UL))) +#define bM4_TMR43_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249871CUL))) +#define bM4_TMR43_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42498720UL))) +#define bM4_TMR43_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42498724UL))) +#define bM4_TMR43_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42498728UL))) +#define bM4_TMR43_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249872CUL))) +#define bM4_TMR43_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42498730UL))) +#define bM4_TMR43_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42498734UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42498738UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249873CUL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42498740UL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42498744UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42498748UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249874CUL))) +#define bM4_TMR43_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42498750UL))) +#define bM4_TMR43_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42498754UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42498758UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249875CUL))) +#define bM4_TMR43_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42498760UL))) +#define bM4_TMR43_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42498764UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42498768UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249876CUL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42498770UL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42498774UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42498778UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249877CUL))) +#define bM4_TMR43_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42498900UL))) +#define bM4_TMR43_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42498904UL))) +#define bM4_TMR43_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42498908UL))) +#define bM4_TMR43_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249890CUL))) +#define bM4_TMR43_CCSR_CLEAR (*((volatile unsigned int*)(0x42498910UL))) +#define bM4_TMR43_CCSR_MODE (*((volatile unsigned int*)(0x42498914UL))) +#define bM4_TMR43_CCSR_STOP (*((volatile unsigned int*)(0x42498918UL))) +#define bM4_TMR43_CCSR_BUFEN (*((volatile unsigned int*)(0x4249891CUL))) +#define bM4_TMR43_CCSR_IRQPEN (*((volatile unsigned int*)(0x42498920UL))) +#define bM4_TMR43_CCSR_IRQPF (*((volatile unsigned int*)(0x42498924UL))) +#define bM4_TMR43_CCSR_IRQZEN (*((volatile unsigned int*)(0x42498934UL))) +#define bM4_TMR43_CCSR_IRQZF (*((volatile unsigned int*)(0x42498938UL))) +#define bM4_TMR43_CCSR_ECKEN (*((volatile unsigned int*)(0x4249893CUL))) +#define bM4_TMR43_CVPR_ZIM0 (*((volatile unsigned int*)(0x42498940UL))) +#define bM4_TMR43_CVPR_ZIM1 (*((volatile unsigned int*)(0x42498944UL))) +#define bM4_TMR43_CVPR_ZIM2 (*((volatile unsigned int*)(0x42498948UL))) +#define bM4_TMR43_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249894CUL))) +#define bM4_TMR43_CVPR_PIM0 (*((volatile unsigned int*)(0x42498950UL))) +#define bM4_TMR43_CVPR_PIM1 (*((volatile unsigned int*)(0x42498954UL))) +#define bM4_TMR43_CVPR_PIM2 (*((volatile unsigned int*)(0x42498958UL))) +#define bM4_TMR43_CVPR_PIM3 (*((volatile unsigned int*)(0x4249895CUL))) +#define bM4_TMR43_CVPR_ZIC0 (*((volatile unsigned int*)(0x42498960UL))) +#define bM4_TMR43_CVPR_ZIC1 (*((volatile unsigned int*)(0x42498964UL))) +#define bM4_TMR43_CVPR_ZIC2 (*((volatile unsigned int*)(0x42498968UL))) +#define bM4_TMR43_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249896CUL))) +#define bM4_TMR43_CVPR_PIC0 (*((volatile unsigned int*)(0x42498970UL))) +#define bM4_TMR43_CVPR_PIC1 (*((volatile unsigned int*)(0x42498974UL))) +#define bM4_TMR43_CVPR_PIC2 (*((volatile unsigned int*)(0x42498978UL))) +#define bM4_TMR43_CVPR_PIC3 (*((volatile unsigned int*)(0x4249897CUL))) +#define bM4_TMR43_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42499300UL))) +#define bM4_TMR43_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42499304UL))) +#define bM4_TMR43_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42499308UL))) +#define bM4_TMR43_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249930CUL))) +#define bM4_TMR43_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42499310UL))) +#define bM4_TMR43_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42499314UL))) +#define bM4_TMR43_POCRU_LVLS0 (*((volatile unsigned int*)(0x42499318UL))) +#define bM4_TMR43_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249931CUL))) +#define bM4_TMR43_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42499380UL))) +#define bM4_TMR43_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42499384UL))) +#define bM4_TMR43_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42499388UL))) +#define bM4_TMR43_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249938CUL))) +#define bM4_TMR43_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42499390UL))) +#define bM4_TMR43_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42499394UL))) +#define bM4_TMR43_POCRV_LVLS0 (*((volatile unsigned int*)(0x42499398UL))) +#define bM4_TMR43_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249939CUL))) +#define bM4_TMR43_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42499400UL))) +#define bM4_TMR43_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42499404UL))) +#define bM4_TMR43_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42499408UL))) +#define bM4_TMR43_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249940CUL))) +#define bM4_TMR43_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42499410UL))) +#define bM4_TMR43_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42499414UL))) +#define bM4_TMR43_POCRW_LVLS0 (*((volatile unsigned int*)(0x42499418UL))) +#define bM4_TMR43_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249941CUL))) +#define bM4_TMR43_RCSR_RTIDU (*((volatile unsigned int*)(0x42499480UL))) +#define bM4_TMR43_RCSR_RTIDV (*((volatile unsigned int*)(0x42499484UL))) +#define bM4_TMR43_RCSR_RTIDW (*((volatile unsigned int*)(0x42499488UL))) +#define bM4_TMR43_RCSR_RTIFU (*((volatile unsigned int*)(0x42499490UL))) +#define bM4_TMR43_RCSR_RTICU (*((volatile unsigned int*)(0x42499494UL))) +#define bM4_TMR43_RCSR_RTEU (*((volatile unsigned int*)(0x42499498UL))) +#define bM4_TMR43_RCSR_RTSU (*((volatile unsigned int*)(0x4249949CUL))) +#define bM4_TMR43_RCSR_RTIFV (*((volatile unsigned int*)(0x424994A0UL))) +#define bM4_TMR43_RCSR_RTICV (*((volatile unsigned int*)(0x424994A4UL))) +#define bM4_TMR43_RCSR_RTEV (*((volatile unsigned int*)(0x424994A8UL))) +#define bM4_TMR43_RCSR_RTSV (*((volatile unsigned int*)(0x424994ACUL))) +#define bM4_TMR43_RCSR_RTIFW (*((volatile unsigned int*)(0x424994B0UL))) +#define bM4_TMR43_RCSR_RTICW (*((volatile unsigned int*)(0x424994B4UL))) +#define bM4_TMR43_RCSR_RTEW (*((volatile unsigned int*)(0x424994B8UL))) +#define bM4_TMR43_RCSR_RTSW (*((volatile unsigned int*)(0x424994BCUL))) +#define bM4_TMR43_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42499900UL))) +#define bM4_TMR43_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42499904UL))) +#define bM4_TMR43_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42499908UL))) +#define bM4_TMR43_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249990CUL))) +#define bM4_TMR43_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42499910UL))) +#define bM4_TMR43_SCSRUH_LMC (*((volatile unsigned int*)(0x42499914UL))) +#define bM4_TMR43_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42499920UL))) +#define bM4_TMR43_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42499924UL))) +#define bM4_TMR43_SCSRUH_DEN (*((volatile unsigned int*)(0x42499930UL))) +#define bM4_TMR43_SCSRUH_PEN (*((volatile unsigned int*)(0x42499934UL))) +#define bM4_TMR43_SCSRUH_UEN (*((volatile unsigned int*)(0x42499938UL))) +#define bM4_TMR43_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249993CUL))) +#define bM4_TMR43_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42499940UL))) +#define bM4_TMR43_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42499944UL))) +#define bM4_TMR43_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42499948UL))) +#define bM4_TMR43_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249994CUL))) +#define bM4_TMR43_SCMRUH_MZCE (*((volatile unsigned int*)(0x42499958UL))) +#define bM4_TMR43_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249995CUL))) +#define bM4_TMR43_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42499980UL))) +#define bM4_TMR43_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42499984UL))) +#define bM4_TMR43_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42499988UL))) +#define bM4_TMR43_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249998CUL))) +#define bM4_TMR43_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42499990UL))) +#define bM4_TMR43_SCSRUL_LMC (*((volatile unsigned int*)(0x42499994UL))) +#define bM4_TMR43_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424999A0UL))) +#define bM4_TMR43_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424999A4UL))) +#define bM4_TMR43_SCSRUL_DEN (*((volatile unsigned int*)(0x424999B0UL))) +#define bM4_TMR43_SCSRUL_PEN (*((volatile unsigned int*)(0x424999B4UL))) +#define bM4_TMR43_SCSRUL_UEN (*((volatile unsigned int*)(0x424999B8UL))) +#define bM4_TMR43_SCSRUL_ZEN (*((volatile unsigned int*)(0x424999BCUL))) +#define bM4_TMR43_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424999C0UL))) +#define bM4_TMR43_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424999C4UL))) +#define bM4_TMR43_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424999C8UL))) +#define bM4_TMR43_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424999CCUL))) +#define bM4_TMR43_SCMRUL_MZCE (*((volatile unsigned int*)(0x424999D8UL))) +#define bM4_TMR43_SCMRUL_MPCE (*((volatile unsigned int*)(0x424999DCUL))) +#define bM4_TMR43_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42499A00UL))) +#define bM4_TMR43_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42499A04UL))) +#define bM4_TMR43_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42499A08UL))) +#define bM4_TMR43_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42499A0CUL))) +#define bM4_TMR43_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42499A10UL))) +#define bM4_TMR43_SCSRVH_LMC (*((volatile unsigned int*)(0x42499A14UL))) +#define bM4_TMR43_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42499A20UL))) +#define bM4_TMR43_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42499A24UL))) +#define bM4_TMR43_SCSRVH_DEN (*((volatile unsigned int*)(0x42499A30UL))) +#define bM4_TMR43_SCSRVH_PEN (*((volatile unsigned int*)(0x42499A34UL))) +#define bM4_TMR43_SCSRVH_UEN (*((volatile unsigned int*)(0x42499A38UL))) +#define bM4_TMR43_SCSRVH_ZEN (*((volatile unsigned int*)(0x42499A3CUL))) +#define bM4_TMR43_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42499A40UL))) +#define bM4_TMR43_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42499A44UL))) +#define bM4_TMR43_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42499A48UL))) +#define bM4_TMR43_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42499A4CUL))) +#define bM4_TMR43_SCMRVH_MZCE (*((volatile unsigned int*)(0x42499A58UL))) +#define bM4_TMR43_SCMRVH_MPCE (*((volatile unsigned int*)(0x42499A5CUL))) +#define bM4_TMR43_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42499A80UL))) +#define bM4_TMR43_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42499A84UL))) +#define bM4_TMR43_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42499A88UL))) +#define bM4_TMR43_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42499A8CUL))) +#define bM4_TMR43_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42499A90UL))) +#define bM4_TMR43_SCSRVL_LMC (*((volatile unsigned int*)(0x42499A94UL))) +#define bM4_TMR43_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42499AA0UL))) +#define bM4_TMR43_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42499AA4UL))) +#define bM4_TMR43_SCSRVL_DEN (*((volatile unsigned int*)(0x42499AB0UL))) +#define bM4_TMR43_SCSRVL_PEN (*((volatile unsigned int*)(0x42499AB4UL))) +#define bM4_TMR43_SCSRVL_UEN (*((volatile unsigned int*)(0x42499AB8UL))) +#define bM4_TMR43_SCSRVL_ZEN (*((volatile unsigned int*)(0x42499ABCUL))) +#define bM4_TMR43_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42499AC0UL))) +#define bM4_TMR43_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42499AC4UL))) +#define bM4_TMR43_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42499AC8UL))) +#define bM4_TMR43_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42499ACCUL))) +#define bM4_TMR43_SCMRVL_MZCE (*((volatile unsigned int*)(0x42499AD8UL))) +#define bM4_TMR43_SCMRVL_MPCE (*((volatile unsigned int*)(0x42499ADCUL))) +#define bM4_TMR43_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42499B00UL))) +#define bM4_TMR43_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42499B04UL))) +#define bM4_TMR43_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42499B08UL))) +#define bM4_TMR43_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42499B0CUL))) +#define bM4_TMR43_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42499B10UL))) +#define bM4_TMR43_SCSRWH_LMC (*((volatile unsigned int*)(0x42499B14UL))) +#define bM4_TMR43_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42499B20UL))) +#define bM4_TMR43_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42499B24UL))) +#define bM4_TMR43_SCSRWH_DEN (*((volatile unsigned int*)(0x42499B30UL))) +#define bM4_TMR43_SCSRWH_PEN (*((volatile unsigned int*)(0x42499B34UL))) +#define bM4_TMR43_SCSRWH_UEN (*((volatile unsigned int*)(0x42499B38UL))) +#define bM4_TMR43_SCSRWH_ZEN (*((volatile unsigned int*)(0x42499B3CUL))) +#define bM4_TMR43_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42499B40UL))) +#define bM4_TMR43_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42499B44UL))) +#define bM4_TMR43_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42499B48UL))) +#define bM4_TMR43_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42499B4CUL))) +#define bM4_TMR43_SCMRWH_MZCE (*((volatile unsigned int*)(0x42499B58UL))) +#define bM4_TMR43_SCMRWH_MPCE (*((volatile unsigned int*)(0x42499B5CUL))) +#define bM4_TMR43_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42499B80UL))) +#define bM4_TMR43_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42499B84UL))) +#define bM4_TMR43_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42499B88UL))) +#define bM4_TMR43_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42499B8CUL))) +#define bM4_TMR43_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42499B90UL))) +#define bM4_TMR43_SCSRWL_LMC (*((volatile unsigned int*)(0x42499B94UL))) +#define bM4_TMR43_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42499BA0UL))) +#define bM4_TMR43_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42499BA4UL))) +#define bM4_TMR43_SCSRWL_DEN (*((volatile unsigned int*)(0x42499BB0UL))) +#define bM4_TMR43_SCSRWL_PEN (*((volatile unsigned int*)(0x42499BB4UL))) +#define bM4_TMR43_SCSRWL_UEN (*((volatile unsigned int*)(0x42499BB8UL))) +#define bM4_TMR43_SCSRWL_ZEN (*((volatile unsigned int*)(0x42499BBCUL))) +#define bM4_TMR43_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42499BC0UL))) +#define bM4_TMR43_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42499BC4UL))) +#define bM4_TMR43_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42499BC8UL))) +#define bM4_TMR43_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42499BCCUL))) +#define bM4_TMR43_SCMRWL_MZCE (*((volatile unsigned int*)(0x42499BD8UL))) +#define bM4_TMR43_SCMRWL_MPCE (*((volatile unsigned int*)(0x42499BDCUL))) +#define bM4_TMR43_ECSR_HOLD (*((volatile unsigned int*)(0x42499E1CUL))) +#define bM4_TMR4_CR_ECER1_EMBVAL0 (*((volatile unsigned int*)(0x42AA8100UL))) +#define bM4_TMR4_CR_ECER1_EMBVAL1 (*((volatile unsigned int*)(0x42AA8104UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL0 (*((volatile unsigned int*)(0x42AA8180UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL1 (*((volatile unsigned int*)(0x42AA8184UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL0 (*((volatile unsigned int*)(0x42AA8200UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL1 (*((volatile unsigned int*)(0x42AA8204UL))) +#define bM4_TMR61_CNTER_CNT0 (*((volatile unsigned int*)(0x42300000UL))) +#define bM4_TMR61_CNTER_CNT1 (*((volatile unsigned int*)(0x42300004UL))) +#define bM4_TMR61_CNTER_CNT2 (*((volatile unsigned int*)(0x42300008UL))) +#define bM4_TMR61_CNTER_CNT3 (*((volatile unsigned int*)(0x4230000CUL))) +#define bM4_TMR61_CNTER_CNT4 (*((volatile unsigned int*)(0x42300010UL))) +#define bM4_TMR61_CNTER_CNT5 (*((volatile unsigned int*)(0x42300014UL))) +#define bM4_TMR61_CNTER_CNT6 (*((volatile unsigned int*)(0x42300018UL))) +#define bM4_TMR61_CNTER_CNT7 (*((volatile unsigned int*)(0x4230001CUL))) +#define bM4_TMR61_CNTER_CNT8 (*((volatile unsigned int*)(0x42300020UL))) +#define bM4_TMR61_CNTER_CNT9 (*((volatile unsigned int*)(0x42300024UL))) +#define bM4_TMR61_CNTER_CNT10 (*((volatile unsigned int*)(0x42300028UL))) +#define bM4_TMR61_CNTER_CNT11 (*((volatile unsigned int*)(0x4230002CUL))) +#define bM4_TMR61_CNTER_CNT12 (*((volatile unsigned int*)(0x42300030UL))) +#define bM4_TMR61_CNTER_CNT13 (*((volatile unsigned int*)(0x42300034UL))) +#define bM4_TMR61_CNTER_CNT14 (*((volatile unsigned int*)(0x42300038UL))) +#define bM4_TMR61_CNTER_CNT15 (*((volatile unsigned int*)(0x4230003CUL))) +#define bM4_TMR61_PERAR_PERA0 (*((volatile unsigned int*)(0x42300080UL))) +#define bM4_TMR61_PERAR_PERA1 (*((volatile unsigned int*)(0x42300084UL))) +#define bM4_TMR61_PERAR_PERA2 (*((volatile unsigned int*)(0x42300088UL))) +#define bM4_TMR61_PERAR_PERA3 (*((volatile unsigned int*)(0x4230008CUL))) +#define bM4_TMR61_PERAR_PERA4 (*((volatile unsigned int*)(0x42300090UL))) +#define bM4_TMR61_PERAR_PERA5 (*((volatile unsigned int*)(0x42300094UL))) +#define bM4_TMR61_PERAR_PERA6 (*((volatile unsigned int*)(0x42300098UL))) +#define bM4_TMR61_PERAR_PERA7 (*((volatile unsigned int*)(0x4230009CUL))) +#define bM4_TMR61_PERAR_PERA8 (*((volatile unsigned int*)(0x423000A0UL))) +#define bM4_TMR61_PERAR_PERA9 (*((volatile unsigned int*)(0x423000A4UL))) +#define bM4_TMR61_PERAR_PERA10 (*((volatile unsigned int*)(0x423000A8UL))) +#define bM4_TMR61_PERAR_PERA11 (*((volatile unsigned int*)(0x423000ACUL))) +#define bM4_TMR61_PERAR_PERA12 (*((volatile unsigned int*)(0x423000B0UL))) +#define bM4_TMR61_PERAR_PERA13 (*((volatile unsigned int*)(0x423000B4UL))) +#define bM4_TMR61_PERAR_PERA14 (*((volatile unsigned int*)(0x423000B8UL))) +#define bM4_TMR61_PERAR_PERA15 (*((volatile unsigned int*)(0x423000BCUL))) +#define bM4_TMR61_PERBR_PERB0 (*((volatile unsigned int*)(0x42300100UL))) +#define bM4_TMR61_PERBR_PERB1 (*((volatile unsigned int*)(0x42300104UL))) +#define bM4_TMR61_PERBR_PERB2 (*((volatile unsigned int*)(0x42300108UL))) +#define bM4_TMR61_PERBR_PERB3 (*((volatile unsigned int*)(0x4230010CUL))) +#define bM4_TMR61_PERBR_PERB4 (*((volatile unsigned int*)(0x42300110UL))) +#define bM4_TMR61_PERBR_PERB5 (*((volatile unsigned int*)(0x42300114UL))) +#define bM4_TMR61_PERBR_PERB6 (*((volatile unsigned int*)(0x42300118UL))) +#define bM4_TMR61_PERBR_PERB7 (*((volatile unsigned int*)(0x4230011CUL))) +#define bM4_TMR61_PERBR_PERB8 (*((volatile unsigned int*)(0x42300120UL))) +#define bM4_TMR61_PERBR_PERB9 (*((volatile unsigned int*)(0x42300124UL))) +#define bM4_TMR61_PERBR_PERB10 (*((volatile unsigned int*)(0x42300128UL))) +#define bM4_TMR61_PERBR_PERB11 (*((volatile unsigned int*)(0x4230012CUL))) +#define bM4_TMR61_PERBR_PERB12 (*((volatile unsigned int*)(0x42300130UL))) +#define bM4_TMR61_PERBR_PERB13 (*((volatile unsigned int*)(0x42300134UL))) +#define bM4_TMR61_PERBR_PERB14 (*((volatile unsigned int*)(0x42300138UL))) +#define bM4_TMR61_PERBR_PERB15 (*((volatile unsigned int*)(0x4230013CUL))) +#define bM4_TMR61_PERCR_PERC0 (*((volatile unsigned int*)(0x42300180UL))) +#define bM4_TMR61_PERCR_PERC1 (*((volatile unsigned int*)(0x42300184UL))) +#define bM4_TMR61_PERCR_PERC2 (*((volatile unsigned int*)(0x42300188UL))) +#define bM4_TMR61_PERCR_PERC3 (*((volatile unsigned int*)(0x4230018CUL))) +#define bM4_TMR61_PERCR_PERC4 (*((volatile unsigned int*)(0x42300190UL))) +#define bM4_TMR61_PERCR_PERC5 (*((volatile unsigned int*)(0x42300194UL))) +#define bM4_TMR61_PERCR_PERC6 (*((volatile unsigned int*)(0x42300198UL))) +#define bM4_TMR61_PERCR_PERC7 (*((volatile unsigned int*)(0x4230019CUL))) +#define bM4_TMR61_PERCR_PERC8 (*((volatile unsigned int*)(0x423001A0UL))) +#define bM4_TMR61_PERCR_PERC9 (*((volatile unsigned int*)(0x423001A4UL))) +#define bM4_TMR61_PERCR_PERC10 (*((volatile unsigned int*)(0x423001A8UL))) +#define bM4_TMR61_PERCR_PERC11 (*((volatile unsigned int*)(0x423001ACUL))) +#define bM4_TMR61_PERCR_PERC12 (*((volatile unsigned int*)(0x423001B0UL))) +#define bM4_TMR61_PERCR_PERC13 (*((volatile unsigned int*)(0x423001B4UL))) +#define bM4_TMR61_PERCR_PERC14 (*((volatile unsigned int*)(0x423001B8UL))) +#define bM4_TMR61_PERCR_PERC15 (*((volatile unsigned int*)(0x423001BCUL))) +#define bM4_TMR61_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42300200UL))) +#define bM4_TMR61_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42300204UL))) +#define bM4_TMR61_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42300208UL))) +#define bM4_TMR61_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230020CUL))) +#define bM4_TMR61_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42300210UL))) +#define bM4_TMR61_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42300214UL))) +#define bM4_TMR61_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42300218UL))) +#define bM4_TMR61_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230021CUL))) +#define bM4_TMR61_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42300220UL))) +#define bM4_TMR61_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42300224UL))) +#define bM4_TMR61_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42300228UL))) +#define bM4_TMR61_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230022CUL))) +#define bM4_TMR61_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42300230UL))) +#define bM4_TMR61_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42300234UL))) +#define bM4_TMR61_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42300238UL))) +#define bM4_TMR61_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230023CUL))) +#define bM4_TMR61_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42300280UL))) +#define bM4_TMR61_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42300284UL))) +#define bM4_TMR61_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42300288UL))) +#define bM4_TMR61_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230028CUL))) +#define bM4_TMR61_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42300290UL))) +#define bM4_TMR61_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42300294UL))) +#define bM4_TMR61_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42300298UL))) +#define bM4_TMR61_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230029CUL))) +#define bM4_TMR61_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423002A0UL))) +#define bM4_TMR61_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423002A4UL))) +#define bM4_TMR61_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423002A8UL))) +#define bM4_TMR61_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423002ACUL))) +#define bM4_TMR61_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423002B0UL))) +#define bM4_TMR61_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423002B4UL))) +#define bM4_TMR61_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423002B8UL))) +#define bM4_TMR61_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423002BCUL))) +#define bM4_TMR61_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42300300UL))) +#define bM4_TMR61_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42300304UL))) +#define bM4_TMR61_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42300308UL))) +#define bM4_TMR61_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230030CUL))) +#define bM4_TMR61_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42300310UL))) +#define bM4_TMR61_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42300314UL))) +#define bM4_TMR61_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42300318UL))) +#define bM4_TMR61_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230031CUL))) +#define bM4_TMR61_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42300320UL))) +#define bM4_TMR61_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42300324UL))) +#define bM4_TMR61_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42300328UL))) +#define bM4_TMR61_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230032CUL))) +#define bM4_TMR61_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42300330UL))) +#define bM4_TMR61_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42300334UL))) +#define bM4_TMR61_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42300338UL))) +#define bM4_TMR61_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230033CUL))) +#define bM4_TMR61_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42300380UL))) +#define bM4_TMR61_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42300384UL))) +#define bM4_TMR61_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42300388UL))) +#define bM4_TMR61_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230038CUL))) +#define bM4_TMR61_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42300390UL))) +#define bM4_TMR61_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42300394UL))) +#define bM4_TMR61_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42300398UL))) +#define bM4_TMR61_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230039CUL))) +#define bM4_TMR61_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423003A0UL))) +#define bM4_TMR61_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423003A4UL))) +#define bM4_TMR61_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423003A8UL))) +#define bM4_TMR61_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423003ACUL))) +#define bM4_TMR61_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423003B0UL))) +#define bM4_TMR61_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423003B4UL))) +#define bM4_TMR61_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423003B8UL))) +#define bM4_TMR61_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423003BCUL))) +#define bM4_TMR61_GCMER_GCME0 (*((volatile unsigned int*)(0x42300400UL))) +#define bM4_TMR61_GCMER_GCME1 (*((volatile unsigned int*)(0x42300404UL))) +#define bM4_TMR61_GCMER_GCME2 (*((volatile unsigned int*)(0x42300408UL))) +#define bM4_TMR61_GCMER_GCME3 (*((volatile unsigned int*)(0x4230040CUL))) +#define bM4_TMR61_GCMER_GCME4 (*((volatile unsigned int*)(0x42300410UL))) +#define bM4_TMR61_GCMER_GCME5 (*((volatile unsigned int*)(0x42300414UL))) +#define bM4_TMR61_GCMER_GCME6 (*((volatile unsigned int*)(0x42300418UL))) +#define bM4_TMR61_GCMER_GCME7 (*((volatile unsigned int*)(0x4230041CUL))) +#define bM4_TMR61_GCMER_GCME8 (*((volatile unsigned int*)(0x42300420UL))) +#define bM4_TMR61_GCMER_GCME9 (*((volatile unsigned int*)(0x42300424UL))) +#define bM4_TMR61_GCMER_GCME10 (*((volatile unsigned int*)(0x42300428UL))) +#define bM4_TMR61_GCMER_GCME11 (*((volatile unsigned int*)(0x4230042CUL))) +#define bM4_TMR61_GCMER_GCME12 (*((volatile unsigned int*)(0x42300430UL))) +#define bM4_TMR61_GCMER_GCME13 (*((volatile unsigned int*)(0x42300434UL))) +#define bM4_TMR61_GCMER_GCME14 (*((volatile unsigned int*)(0x42300438UL))) +#define bM4_TMR61_GCMER_GCME15 (*((volatile unsigned int*)(0x4230043CUL))) +#define bM4_TMR61_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42300480UL))) +#define bM4_TMR61_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42300484UL))) +#define bM4_TMR61_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42300488UL))) +#define bM4_TMR61_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230048CUL))) +#define bM4_TMR61_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42300490UL))) +#define bM4_TMR61_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42300494UL))) +#define bM4_TMR61_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42300498UL))) +#define bM4_TMR61_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230049CUL))) +#define bM4_TMR61_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423004A0UL))) +#define bM4_TMR61_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423004A4UL))) +#define bM4_TMR61_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423004A8UL))) +#define bM4_TMR61_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423004ACUL))) +#define bM4_TMR61_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423004B0UL))) +#define bM4_TMR61_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423004B4UL))) +#define bM4_TMR61_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423004B8UL))) +#define bM4_TMR61_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423004BCUL))) +#define bM4_TMR61_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42300500UL))) +#define bM4_TMR61_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42300504UL))) +#define bM4_TMR61_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42300508UL))) +#define bM4_TMR61_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230050CUL))) +#define bM4_TMR61_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42300510UL))) +#define bM4_TMR61_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42300514UL))) +#define bM4_TMR61_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42300518UL))) +#define bM4_TMR61_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230051CUL))) +#define bM4_TMR61_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42300520UL))) +#define bM4_TMR61_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42300524UL))) +#define bM4_TMR61_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42300528UL))) +#define bM4_TMR61_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230052CUL))) +#define bM4_TMR61_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42300530UL))) +#define bM4_TMR61_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42300534UL))) +#define bM4_TMR61_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42300538UL))) +#define bM4_TMR61_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230053CUL))) +#define bM4_TMR61_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42300580UL))) +#define bM4_TMR61_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42300584UL))) +#define bM4_TMR61_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42300588UL))) +#define bM4_TMR61_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230058CUL))) +#define bM4_TMR61_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42300590UL))) +#define bM4_TMR61_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42300594UL))) +#define bM4_TMR61_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42300598UL))) +#define bM4_TMR61_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230059CUL))) +#define bM4_TMR61_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423005A0UL))) +#define bM4_TMR61_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423005A4UL))) +#define bM4_TMR61_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423005A8UL))) +#define bM4_TMR61_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423005ACUL))) +#define bM4_TMR61_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423005B0UL))) +#define bM4_TMR61_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423005B4UL))) +#define bM4_TMR61_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423005B8UL))) +#define bM4_TMR61_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423005BCUL))) +#define bM4_TMR61_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42300600UL))) +#define bM4_TMR61_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42300604UL))) +#define bM4_TMR61_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42300608UL))) +#define bM4_TMR61_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230060CUL))) +#define bM4_TMR61_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42300610UL))) +#define bM4_TMR61_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42300614UL))) +#define bM4_TMR61_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42300618UL))) +#define bM4_TMR61_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230061CUL))) +#define bM4_TMR61_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42300620UL))) +#define bM4_TMR61_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42300624UL))) +#define bM4_TMR61_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42300628UL))) +#define bM4_TMR61_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230062CUL))) +#define bM4_TMR61_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42300630UL))) +#define bM4_TMR61_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42300634UL))) +#define bM4_TMR61_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42300638UL))) +#define bM4_TMR61_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230063CUL))) +#define bM4_TMR61_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42300680UL))) +#define bM4_TMR61_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42300684UL))) +#define bM4_TMR61_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42300688UL))) +#define bM4_TMR61_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230068CUL))) +#define bM4_TMR61_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42300690UL))) +#define bM4_TMR61_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42300694UL))) +#define bM4_TMR61_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42300698UL))) +#define bM4_TMR61_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230069CUL))) +#define bM4_TMR61_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423006A0UL))) +#define bM4_TMR61_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423006A4UL))) +#define bM4_TMR61_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423006A8UL))) +#define bM4_TMR61_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423006ACUL))) +#define bM4_TMR61_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423006B0UL))) +#define bM4_TMR61_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423006B4UL))) +#define bM4_TMR61_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423006B8UL))) +#define bM4_TMR61_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423006BCUL))) +#define bM4_TMR61_SCMER_SCME0 (*((volatile unsigned int*)(0x42300700UL))) +#define bM4_TMR61_SCMER_SCME1 (*((volatile unsigned int*)(0x42300704UL))) +#define bM4_TMR61_SCMER_SCME2 (*((volatile unsigned int*)(0x42300708UL))) +#define bM4_TMR61_SCMER_SCME3 (*((volatile unsigned int*)(0x4230070CUL))) +#define bM4_TMR61_SCMER_SCME4 (*((volatile unsigned int*)(0x42300710UL))) +#define bM4_TMR61_SCMER_SCME5 (*((volatile unsigned int*)(0x42300714UL))) +#define bM4_TMR61_SCMER_SCME6 (*((volatile unsigned int*)(0x42300718UL))) +#define bM4_TMR61_SCMER_SCME7 (*((volatile unsigned int*)(0x4230071CUL))) +#define bM4_TMR61_SCMER_SCME8 (*((volatile unsigned int*)(0x42300720UL))) +#define bM4_TMR61_SCMER_SCME9 (*((volatile unsigned int*)(0x42300724UL))) +#define bM4_TMR61_SCMER_SCME10 (*((volatile unsigned int*)(0x42300728UL))) +#define bM4_TMR61_SCMER_SCME11 (*((volatile unsigned int*)(0x4230072CUL))) +#define bM4_TMR61_SCMER_SCME12 (*((volatile unsigned int*)(0x42300730UL))) +#define bM4_TMR61_SCMER_SCME13 (*((volatile unsigned int*)(0x42300734UL))) +#define bM4_TMR61_SCMER_SCME14 (*((volatile unsigned int*)(0x42300738UL))) +#define bM4_TMR61_SCMER_SCME15 (*((volatile unsigned int*)(0x4230073CUL))) +#define bM4_TMR61_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42300780UL))) +#define bM4_TMR61_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42300784UL))) +#define bM4_TMR61_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42300788UL))) +#define bM4_TMR61_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230078CUL))) +#define bM4_TMR61_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42300790UL))) +#define bM4_TMR61_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42300794UL))) +#define bM4_TMR61_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42300798UL))) +#define bM4_TMR61_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230079CUL))) +#define bM4_TMR61_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423007A0UL))) +#define bM4_TMR61_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423007A4UL))) +#define bM4_TMR61_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423007A8UL))) +#define bM4_TMR61_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423007ACUL))) +#define bM4_TMR61_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423007B0UL))) +#define bM4_TMR61_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423007B4UL))) +#define bM4_TMR61_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423007B8UL))) +#define bM4_TMR61_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423007BCUL))) +#define bM4_TMR61_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42300800UL))) +#define bM4_TMR61_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42300804UL))) +#define bM4_TMR61_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42300808UL))) +#define bM4_TMR61_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230080CUL))) +#define bM4_TMR61_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42300810UL))) +#define bM4_TMR61_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42300814UL))) +#define bM4_TMR61_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42300818UL))) +#define bM4_TMR61_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230081CUL))) +#define bM4_TMR61_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42300820UL))) +#define bM4_TMR61_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42300824UL))) +#define bM4_TMR61_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42300828UL))) +#define bM4_TMR61_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230082CUL))) +#define bM4_TMR61_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42300830UL))) +#define bM4_TMR61_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42300834UL))) +#define bM4_TMR61_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42300838UL))) +#define bM4_TMR61_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230083CUL))) +#define bM4_TMR61_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42300880UL))) +#define bM4_TMR61_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42300884UL))) +#define bM4_TMR61_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42300888UL))) +#define bM4_TMR61_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230088CUL))) +#define bM4_TMR61_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42300890UL))) +#define bM4_TMR61_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42300894UL))) +#define bM4_TMR61_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42300898UL))) +#define bM4_TMR61_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230089CUL))) +#define bM4_TMR61_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423008A0UL))) +#define bM4_TMR61_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423008A4UL))) +#define bM4_TMR61_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423008A8UL))) +#define bM4_TMR61_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423008ACUL))) +#define bM4_TMR61_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423008B0UL))) +#define bM4_TMR61_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423008B4UL))) +#define bM4_TMR61_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423008B8UL))) +#define bM4_TMR61_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423008BCUL))) +#define bM4_TMR61_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42300900UL))) +#define bM4_TMR61_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42300904UL))) +#define bM4_TMR61_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42300908UL))) +#define bM4_TMR61_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230090CUL))) +#define bM4_TMR61_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42300910UL))) +#define bM4_TMR61_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42300914UL))) +#define bM4_TMR61_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42300918UL))) +#define bM4_TMR61_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230091CUL))) +#define bM4_TMR61_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42300920UL))) +#define bM4_TMR61_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42300924UL))) +#define bM4_TMR61_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42300928UL))) +#define bM4_TMR61_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230092CUL))) +#define bM4_TMR61_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42300930UL))) +#define bM4_TMR61_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42300934UL))) +#define bM4_TMR61_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42300938UL))) +#define bM4_TMR61_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230093CUL))) +#define bM4_TMR61_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42300980UL))) +#define bM4_TMR61_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42300984UL))) +#define bM4_TMR61_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42300988UL))) +#define bM4_TMR61_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230098CUL))) +#define bM4_TMR61_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42300990UL))) +#define bM4_TMR61_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42300994UL))) +#define bM4_TMR61_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42300998UL))) +#define bM4_TMR61_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230099CUL))) +#define bM4_TMR61_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423009A0UL))) +#define bM4_TMR61_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423009A4UL))) +#define bM4_TMR61_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423009A8UL))) +#define bM4_TMR61_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423009ACUL))) +#define bM4_TMR61_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423009B0UL))) +#define bM4_TMR61_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423009B4UL))) +#define bM4_TMR61_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423009B8UL))) +#define bM4_TMR61_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423009BCUL))) +#define bM4_TMR61_GCONR_START (*((volatile unsigned int*)(0x42300A00UL))) +#define bM4_TMR61_GCONR_MODE0 (*((volatile unsigned int*)(0x42300A04UL))) +#define bM4_TMR61_GCONR_MODE1 (*((volatile unsigned int*)(0x42300A08UL))) +#define bM4_TMR61_GCONR_MODE2 (*((volatile unsigned int*)(0x42300A0CUL))) +#define bM4_TMR61_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42300A10UL))) +#define bM4_TMR61_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42300A14UL))) +#define bM4_TMR61_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42300A18UL))) +#define bM4_TMR61_GCONR_DIR (*((volatile unsigned int*)(0x42300A20UL))) +#define bM4_TMR61_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42300A40UL))) +#define bM4_TMR61_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42300A44UL))) +#define bM4_TMR61_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42300A48UL))) +#define bM4_TMR61_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42300A4CUL))) +#define bM4_TMR61_ICONR_INTENA (*((volatile unsigned int*)(0x42300A80UL))) +#define bM4_TMR61_ICONR_INTENB (*((volatile unsigned int*)(0x42300A84UL))) +#define bM4_TMR61_ICONR_INTENC (*((volatile unsigned int*)(0x42300A88UL))) +#define bM4_TMR61_ICONR_INTEND (*((volatile unsigned int*)(0x42300A8CUL))) +#define bM4_TMR61_ICONR_INTENE (*((volatile unsigned int*)(0x42300A90UL))) +#define bM4_TMR61_ICONR_INTENF (*((volatile unsigned int*)(0x42300A94UL))) +#define bM4_TMR61_ICONR_INTENOVF (*((volatile unsigned int*)(0x42300A98UL))) +#define bM4_TMR61_ICONR_INTENUDF (*((volatile unsigned int*)(0x42300A9CUL))) +#define bM4_TMR61_ICONR_INTENDTE (*((volatile unsigned int*)(0x42300AA0UL))) +#define bM4_TMR61_ICONR_INTENSAU (*((volatile unsigned int*)(0x42300AC0UL))) +#define bM4_TMR61_ICONR_INTENSAD (*((volatile unsigned int*)(0x42300AC4UL))) +#define bM4_TMR61_ICONR_INTENSBU (*((volatile unsigned int*)(0x42300AC8UL))) +#define bM4_TMR61_ICONR_INTENSBD (*((volatile unsigned int*)(0x42300ACCUL))) +#define bM4_TMR61_PCONR_CAPMDA (*((volatile unsigned int*)(0x42300B00UL))) +#define bM4_TMR61_PCONR_STACA (*((volatile unsigned int*)(0x42300B04UL))) +#define bM4_TMR61_PCONR_STPCA (*((volatile unsigned int*)(0x42300B08UL))) +#define bM4_TMR61_PCONR_STASTPSA (*((volatile unsigned int*)(0x42300B0CUL))) +#define bM4_TMR61_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42300B10UL))) +#define bM4_TMR61_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42300B14UL))) +#define bM4_TMR61_PCONR_PERCA0 (*((volatile unsigned int*)(0x42300B18UL))) +#define bM4_TMR61_PCONR_PERCA1 (*((volatile unsigned int*)(0x42300B1CUL))) +#define bM4_TMR61_PCONR_OUTENA (*((volatile unsigned int*)(0x42300B20UL))) +#define bM4_TMR61_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42300B2CUL))) +#define bM4_TMR61_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42300B30UL))) +#define bM4_TMR61_PCONR_CAPMDB (*((volatile unsigned int*)(0x42300B40UL))) +#define bM4_TMR61_PCONR_STACB (*((volatile unsigned int*)(0x42300B44UL))) +#define bM4_TMR61_PCONR_STPCB (*((volatile unsigned int*)(0x42300B48UL))) +#define bM4_TMR61_PCONR_STASTPSB (*((volatile unsigned int*)(0x42300B4CUL))) +#define bM4_TMR61_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42300B50UL))) +#define bM4_TMR61_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42300B54UL))) +#define bM4_TMR61_PCONR_PERCB0 (*((volatile unsigned int*)(0x42300B58UL))) +#define bM4_TMR61_PCONR_PERCB1 (*((volatile unsigned int*)(0x42300B5CUL))) +#define bM4_TMR61_PCONR_OUTENB (*((volatile unsigned int*)(0x42300B60UL))) +#define bM4_TMR61_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42300B6CUL))) +#define bM4_TMR61_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42300B70UL))) +#define bM4_TMR61_BCONR_BENA (*((volatile unsigned int*)(0x42300B80UL))) +#define bM4_TMR61_BCONR_BSEA (*((volatile unsigned int*)(0x42300B84UL))) +#define bM4_TMR61_BCONR_BENB (*((volatile unsigned int*)(0x42300B88UL))) +#define bM4_TMR61_BCONR_BSEB (*((volatile unsigned int*)(0x42300B8CUL))) +#define bM4_TMR61_BCONR_BENP (*((volatile unsigned int*)(0x42300BA0UL))) +#define bM4_TMR61_BCONR_BSEP (*((volatile unsigned int*)(0x42300BA4UL))) +#define bM4_TMR61_BCONR_BENSPA (*((volatile unsigned int*)(0x42300BC0UL))) +#define bM4_TMR61_BCONR_BSESPA (*((volatile unsigned int*)(0x42300BC4UL))) +#define bM4_TMR61_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42300BD0UL))) +#define bM4_TMR61_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42300BD4UL))) +#define bM4_TMR61_BCONR_BENSPB (*((volatile unsigned int*)(0x42300BE0UL))) +#define bM4_TMR61_BCONR_BSESPB (*((volatile unsigned int*)(0x42300BE4UL))) +#define bM4_TMR61_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42300BF0UL))) +#define bM4_TMR61_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42300BF4UL))) +#define bM4_TMR61_DCONR_DTCEN (*((volatile unsigned int*)(0x42300C00UL))) +#define bM4_TMR61_DCONR_DTBENU (*((volatile unsigned int*)(0x42300C10UL))) +#define bM4_TMR61_DCONR_DTBEND (*((volatile unsigned int*)(0x42300C14UL))) +#define bM4_TMR61_DCONR_SEPA (*((volatile unsigned int*)(0x42300C20UL))) +#define bM4_TMR61_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42300D00UL))) +#define bM4_TMR61_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42300D04UL))) +#define bM4_TMR61_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42300D08UL))) +#define bM4_TMR61_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42300D10UL))) +#define bM4_TMR61_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42300D14UL))) +#define bM4_TMR61_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42300D18UL))) +#define bM4_TMR61_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42300D40UL))) +#define bM4_TMR61_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42300D44UL))) +#define bM4_TMR61_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42300D48UL))) +#define bM4_TMR61_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42300D50UL))) +#define bM4_TMR61_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42300D54UL))) +#define bM4_TMR61_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42300D58UL))) +#define bM4_TMR61_VPERR_SPPERIA (*((volatile unsigned int*)(0x42300DA0UL))) +#define bM4_TMR61_VPERR_SPPERIB (*((volatile unsigned int*)(0x42300DA4UL))) +#define bM4_TMR61_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42300DC0UL))) +#define bM4_TMR61_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42300DC4UL))) +#define bM4_TMR61_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42300DC8UL))) +#define bM4_TMR61_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42300DCCUL))) +#define bM4_TMR61_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42300DD0UL))) +#define bM4_TMR61_STFLR_CMAF (*((volatile unsigned int*)(0x42300E00UL))) +#define bM4_TMR61_STFLR_CMBF (*((volatile unsigned int*)(0x42300E04UL))) +#define bM4_TMR61_STFLR_CMCF (*((volatile unsigned int*)(0x42300E08UL))) +#define bM4_TMR61_STFLR_CMDF (*((volatile unsigned int*)(0x42300E0CUL))) +#define bM4_TMR61_STFLR_CMEF (*((volatile unsigned int*)(0x42300E10UL))) +#define bM4_TMR61_STFLR_CMFF (*((volatile unsigned int*)(0x42300E14UL))) +#define bM4_TMR61_STFLR_OVFF (*((volatile unsigned int*)(0x42300E18UL))) +#define bM4_TMR61_STFLR_UDFF (*((volatile unsigned int*)(0x42300E1CUL))) +#define bM4_TMR61_STFLR_DTEF (*((volatile unsigned int*)(0x42300E20UL))) +#define bM4_TMR61_STFLR_CMSAUF (*((volatile unsigned int*)(0x42300E24UL))) +#define bM4_TMR61_STFLR_CMSADF (*((volatile unsigned int*)(0x42300E28UL))) +#define bM4_TMR61_STFLR_CMSBUF (*((volatile unsigned int*)(0x42300E2CUL))) +#define bM4_TMR61_STFLR_CMSBDF (*((volatile unsigned int*)(0x42300E30UL))) +#define bM4_TMR61_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42300E54UL))) +#define bM4_TMR61_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42300E58UL))) +#define bM4_TMR61_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42300E5CUL))) +#define bM4_TMR61_STFLR_DIRF (*((volatile unsigned int*)(0x42300E7CUL))) +#define bM4_TMR61_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42300E80UL))) +#define bM4_TMR61_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42300E84UL))) +#define bM4_TMR61_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42300E90UL))) +#define bM4_TMR61_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42300E94UL))) +#define bM4_TMR61_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42300E98UL))) +#define bM4_TMR61_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42300E9CUL))) +#define bM4_TMR61_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42300EA0UL))) +#define bM4_TMR61_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42300EA4UL))) +#define bM4_TMR61_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42300EA8UL))) +#define bM4_TMR61_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42300EACUL))) +#define bM4_TMR61_HSTAR_STARTS (*((volatile unsigned int*)(0x42300EFCUL))) +#define bM4_TMR61_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42300F00UL))) +#define bM4_TMR61_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42300F04UL))) +#define bM4_TMR61_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42300F10UL))) +#define bM4_TMR61_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42300F14UL))) +#define bM4_TMR61_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42300F18UL))) +#define bM4_TMR61_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42300F1CUL))) +#define bM4_TMR61_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42300F20UL))) +#define bM4_TMR61_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42300F24UL))) +#define bM4_TMR61_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42300F28UL))) +#define bM4_TMR61_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42300F2CUL))) +#define bM4_TMR61_HSTPR_STOPS (*((volatile unsigned int*)(0x42300F7CUL))) +#define bM4_TMR61_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42300F80UL))) +#define bM4_TMR61_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42300F84UL))) +#define bM4_TMR61_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42300F90UL))) +#define bM4_TMR61_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42300F94UL))) +#define bM4_TMR61_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42300F98UL))) +#define bM4_TMR61_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42300F9CUL))) +#define bM4_TMR61_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42300FA0UL))) +#define bM4_TMR61_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42300FA4UL))) +#define bM4_TMR61_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42300FA8UL))) +#define bM4_TMR61_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42300FACUL))) +#define bM4_TMR61_HCLRR_CLEARS (*((volatile unsigned int*)(0x42300FFCUL))) +#define bM4_TMR61_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42301000UL))) +#define bM4_TMR61_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42301004UL))) +#define bM4_TMR61_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42301010UL))) +#define bM4_TMR61_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42301014UL))) +#define bM4_TMR61_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42301018UL))) +#define bM4_TMR61_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230101CUL))) +#define bM4_TMR61_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42301020UL))) +#define bM4_TMR61_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42301024UL))) +#define bM4_TMR61_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42301028UL))) +#define bM4_TMR61_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230102CUL))) +#define bM4_TMR61_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42301080UL))) +#define bM4_TMR61_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42301084UL))) +#define bM4_TMR61_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42301090UL))) +#define bM4_TMR61_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42301094UL))) +#define bM4_TMR61_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42301098UL))) +#define bM4_TMR61_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230109CUL))) +#define bM4_TMR61_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423010A0UL))) +#define bM4_TMR61_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423010A4UL))) +#define bM4_TMR61_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423010A8UL))) +#define bM4_TMR61_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423010ACUL))) +#define bM4_TMR61_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42301100UL))) +#define bM4_TMR61_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42301104UL))) +#define bM4_TMR61_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42301108UL))) +#define bM4_TMR61_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230110CUL))) +#define bM4_TMR61_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42301110UL))) +#define bM4_TMR61_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42301114UL))) +#define bM4_TMR61_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42301118UL))) +#define bM4_TMR61_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230111CUL))) +#define bM4_TMR61_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42301120UL))) +#define bM4_TMR61_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42301124UL))) +#define bM4_TMR61_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42301128UL))) +#define bM4_TMR61_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230112CUL))) +#define bM4_TMR61_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42301140UL))) +#define bM4_TMR61_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42301144UL))) +#define bM4_TMR61_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42301180UL))) +#define bM4_TMR61_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42301184UL))) +#define bM4_TMR61_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42301188UL))) +#define bM4_TMR61_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230118CUL))) +#define bM4_TMR61_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42301190UL))) +#define bM4_TMR61_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42301194UL))) +#define bM4_TMR61_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42301198UL))) +#define bM4_TMR61_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230119CUL))) +#define bM4_TMR61_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423011A0UL))) +#define bM4_TMR61_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423011A4UL))) +#define bM4_TMR61_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423011A8UL))) +#define bM4_TMR61_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423011ACUL))) +#define bM4_TMR61_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423011C0UL))) +#define bM4_TMR61_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423011C4UL))) +#define bM4_TMR62_CNTER_CNT0 (*((volatile unsigned int*)(0x42308000UL))) +#define bM4_TMR62_CNTER_CNT1 (*((volatile unsigned int*)(0x42308004UL))) +#define bM4_TMR62_CNTER_CNT2 (*((volatile unsigned int*)(0x42308008UL))) +#define bM4_TMR62_CNTER_CNT3 (*((volatile unsigned int*)(0x4230800CUL))) +#define bM4_TMR62_CNTER_CNT4 (*((volatile unsigned int*)(0x42308010UL))) +#define bM4_TMR62_CNTER_CNT5 (*((volatile unsigned int*)(0x42308014UL))) +#define bM4_TMR62_CNTER_CNT6 (*((volatile unsigned int*)(0x42308018UL))) +#define bM4_TMR62_CNTER_CNT7 (*((volatile unsigned int*)(0x4230801CUL))) +#define bM4_TMR62_CNTER_CNT8 (*((volatile unsigned int*)(0x42308020UL))) +#define bM4_TMR62_CNTER_CNT9 (*((volatile unsigned int*)(0x42308024UL))) +#define bM4_TMR62_CNTER_CNT10 (*((volatile unsigned int*)(0x42308028UL))) +#define bM4_TMR62_CNTER_CNT11 (*((volatile unsigned int*)(0x4230802CUL))) +#define bM4_TMR62_CNTER_CNT12 (*((volatile unsigned int*)(0x42308030UL))) +#define bM4_TMR62_CNTER_CNT13 (*((volatile unsigned int*)(0x42308034UL))) +#define bM4_TMR62_CNTER_CNT14 (*((volatile unsigned int*)(0x42308038UL))) +#define bM4_TMR62_CNTER_CNT15 (*((volatile unsigned int*)(0x4230803CUL))) +#define bM4_TMR62_PERAR_PERA0 (*((volatile unsigned int*)(0x42308080UL))) +#define bM4_TMR62_PERAR_PERA1 (*((volatile unsigned int*)(0x42308084UL))) +#define bM4_TMR62_PERAR_PERA2 (*((volatile unsigned int*)(0x42308088UL))) +#define bM4_TMR62_PERAR_PERA3 (*((volatile unsigned int*)(0x4230808CUL))) +#define bM4_TMR62_PERAR_PERA4 (*((volatile unsigned int*)(0x42308090UL))) +#define bM4_TMR62_PERAR_PERA5 (*((volatile unsigned int*)(0x42308094UL))) +#define bM4_TMR62_PERAR_PERA6 (*((volatile unsigned int*)(0x42308098UL))) +#define bM4_TMR62_PERAR_PERA7 (*((volatile unsigned int*)(0x4230809CUL))) +#define bM4_TMR62_PERAR_PERA8 (*((volatile unsigned int*)(0x423080A0UL))) +#define bM4_TMR62_PERAR_PERA9 (*((volatile unsigned int*)(0x423080A4UL))) +#define bM4_TMR62_PERAR_PERA10 (*((volatile unsigned int*)(0x423080A8UL))) +#define bM4_TMR62_PERAR_PERA11 (*((volatile unsigned int*)(0x423080ACUL))) +#define bM4_TMR62_PERAR_PERA12 (*((volatile unsigned int*)(0x423080B0UL))) +#define bM4_TMR62_PERAR_PERA13 (*((volatile unsigned int*)(0x423080B4UL))) +#define bM4_TMR62_PERAR_PERA14 (*((volatile unsigned int*)(0x423080B8UL))) +#define bM4_TMR62_PERAR_PERA15 (*((volatile unsigned int*)(0x423080BCUL))) +#define bM4_TMR62_PERBR_PERB0 (*((volatile unsigned int*)(0x42308100UL))) +#define bM4_TMR62_PERBR_PERB1 (*((volatile unsigned int*)(0x42308104UL))) +#define bM4_TMR62_PERBR_PERB2 (*((volatile unsigned int*)(0x42308108UL))) +#define bM4_TMR62_PERBR_PERB3 (*((volatile unsigned int*)(0x4230810CUL))) +#define bM4_TMR62_PERBR_PERB4 (*((volatile unsigned int*)(0x42308110UL))) +#define bM4_TMR62_PERBR_PERB5 (*((volatile unsigned int*)(0x42308114UL))) +#define bM4_TMR62_PERBR_PERB6 (*((volatile unsigned int*)(0x42308118UL))) +#define bM4_TMR62_PERBR_PERB7 (*((volatile unsigned int*)(0x4230811CUL))) +#define bM4_TMR62_PERBR_PERB8 (*((volatile unsigned int*)(0x42308120UL))) +#define bM4_TMR62_PERBR_PERB9 (*((volatile unsigned int*)(0x42308124UL))) +#define bM4_TMR62_PERBR_PERB10 (*((volatile unsigned int*)(0x42308128UL))) +#define bM4_TMR62_PERBR_PERB11 (*((volatile unsigned int*)(0x4230812CUL))) +#define bM4_TMR62_PERBR_PERB12 (*((volatile unsigned int*)(0x42308130UL))) +#define bM4_TMR62_PERBR_PERB13 (*((volatile unsigned int*)(0x42308134UL))) +#define bM4_TMR62_PERBR_PERB14 (*((volatile unsigned int*)(0x42308138UL))) +#define bM4_TMR62_PERBR_PERB15 (*((volatile unsigned int*)(0x4230813CUL))) +#define bM4_TMR62_PERCR_PERC0 (*((volatile unsigned int*)(0x42308180UL))) +#define bM4_TMR62_PERCR_PERC1 (*((volatile unsigned int*)(0x42308184UL))) +#define bM4_TMR62_PERCR_PERC2 (*((volatile unsigned int*)(0x42308188UL))) +#define bM4_TMR62_PERCR_PERC3 (*((volatile unsigned int*)(0x4230818CUL))) +#define bM4_TMR62_PERCR_PERC4 (*((volatile unsigned int*)(0x42308190UL))) +#define bM4_TMR62_PERCR_PERC5 (*((volatile unsigned int*)(0x42308194UL))) +#define bM4_TMR62_PERCR_PERC6 (*((volatile unsigned int*)(0x42308198UL))) +#define bM4_TMR62_PERCR_PERC7 (*((volatile unsigned int*)(0x4230819CUL))) +#define bM4_TMR62_PERCR_PERC8 (*((volatile unsigned int*)(0x423081A0UL))) +#define bM4_TMR62_PERCR_PERC9 (*((volatile unsigned int*)(0x423081A4UL))) +#define bM4_TMR62_PERCR_PERC10 (*((volatile unsigned int*)(0x423081A8UL))) +#define bM4_TMR62_PERCR_PERC11 (*((volatile unsigned int*)(0x423081ACUL))) +#define bM4_TMR62_PERCR_PERC12 (*((volatile unsigned int*)(0x423081B0UL))) +#define bM4_TMR62_PERCR_PERC13 (*((volatile unsigned int*)(0x423081B4UL))) +#define bM4_TMR62_PERCR_PERC14 (*((volatile unsigned int*)(0x423081B8UL))) +#define bM4_TMR62_PERCR_PERC15 (*((volatile unsigned int*)(0x423081BCUL))) +#define bM4_TMR62_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42308200UL))) +#define bM4_TMR62_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42308204UL))) +#define bM4_TMR62_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42308208UL))) +#define bM4_TMR62_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230820CUL))) +#define bM4_TMR62_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42308210UL))) +#define bM4_TMR62_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42308214UL))) +#define bM4_TMR62_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42308218UL))) +#define bM4_TMR62_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230821CUL))) +#define bM4_TMR62_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42308220UL))) +#define bM4_TMR62_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42308224UL))) +#define bM4_TMR62_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42308228UL))) +#define bM4_TMR62_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230822CUL))) +#define bM4_TMR62_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42308230UL))) +#define bM4_TMR62_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42308234UL))) +#define bM4_TMR62_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42308238UL))) +#define bM4_TMR62_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230823CUL))) +#define bM4_TMR62_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42308280UL))) +#define bM4_TMR62_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42308284UL))) +#define bM4_TMR62_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42308288UL))) +#define bM4_TMR62_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230828CUL))) +#define bM4_TMR62_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42308290UL))) +#define bM4_TMR62_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42308294UL))) +#define bM4_TMR62_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42308298UL))) +#define bM4_TMR62_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230829CUL))) +#define bM4_TMR62_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423082A0UL))) +#define bM4_TMR62_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423082A4UL))) +#define bM4_TMR62_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423082A8UL))) +#define bM4_TMR62_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423082ACUL))) +#define bM4_TMR62_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423082B0UL))) +#define bM4_TMR62_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423082B4UL))) +#define bM4_TMR62_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423082B8UL))) +#define bM4_TMR62_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423082BCUL))) +#define bM4_TMR62_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42308300UL))) +#define bM4_TMR62_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42308304UL))) +#define bM4_TMR62_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42308308UL))) +#define bM4_TMR62_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230830CUL))) +#define bM4_TMR62_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42308310UL))) +#define bM4_TMR62_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42308314UL))) +#define bM4_TMR62_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42308318UL))) +#define bM4_TMR62_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230831CUL))) +#define bM4_TMR62_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42308320UL))) +#define bM4_TMR62_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42308324UL))) +#define bM4_TMR62_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42308328UL))) +#define bM4_TMR62_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230832CUL))) +#define bM4_TMR62_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42308330UL))) +#define bM4_TMR62_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42308334UL))) +#define bM4_TMR62_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42308338UL))) +#define bM4_TMR62_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230833CUL))) +#define bM4_TMR62_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42308380UL))) +#define bM4_TMR62_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42308384UL))) +#define bM4_TMR62_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42308388UL))) +#define bM4_TMR62_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230838CUL))) +#define bM4_TMR62_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42308390UL))) +#define bM4_TMR62_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42308394UL))) +#define bM4_TMR62_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42308398UL))) +#define bM4_TMR62_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230839CUL))) +#define bM4_TMR62_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423083A0UL))) +#define bM4_TMR62_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423083A4UL))) +#define bM4_TMR62_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423083A8UL))) +#define bM4_TMR62_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423083ACUL))) +#define bM4_TMR62_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423083B0UL))) +#define bM4_TMR62_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423083B4UL))) +#define bM4_TMR62_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423083B8UL))) +#define bM4_TMR62_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423083BCUL))) +#define bM4_TMR62_GCMER_GCME0 (*((volatile unsigned int*)(0x42308400UL))) +#define bM4_TMR62_GCMER_GCME1 (*((volatile unsigned int*)(0x42308404UL))) +#define bM4_TMR62_GCMER_GCME2 (*((volatile unsigned int*)(0x42308408UL))) +#define bM4_TMR62_GCMER_GCME3 (*((volatile unsigned int*)(0x4230840CUL))) +#define bM4_TMR62_GCMER_GCME4 (*((volatile unsigned int*)(0x42308410UL))) +#define bM4_TMR62_GCMER_GCME5 (*((volatile unsigned int*)(0x42308414UL))) +#define bM4_TMR62_GCMER_GCME6 (*((volatile unsigned int*)(0x42308418UL))) +#define bM4_TMR62_GCMER_GCME7 (*((volatile unsigned int*)(0x4230841CUL))) +#define bM4_TMR62_GCMER_GCME8 (*((volatile unsigned int*)(0x42308420UL))) +#define bM4_TMR62_GCMER_GCME9 (*((volatile unsigned int*)(0x42308424UL))) +#define bM4_TMR62_GCMER_GCME10 (*((volatile unsigned int*)(0x42308428UL))) +#define bM4_TMR62_GCMER_GCME11 (*((volatile unsigned int*)(0x4230842CUL))) +#define bM4_TMR62_GCMER_GCME12 (*((volatile unsigned int*)(0x42308430UL))) +#define bM4_TMR62_GCMER_GCME13 (*((volatile unsigned int*)(0x42308434UL))) +#define bM4_TMR62_GCMER_GCME14 (*((volatile unsigned int*)(0x42308438UL))) +#define bM4_TMR62_GCMER_GCME15 (*((volatile unsigned int*)(0x4230843CUL))) +#define bM4_TMR62_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42308480UL))) +#define bM4_TMR62_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42308484UL))) +#define bM4_TMR62_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42308488UL))) +#define bM4_TMR62_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230848CUL))) +#define bM4_TMR62_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42308490UL))) +#define bM4_TMR62_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42308494UL))) +#define bM4_TMR62_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42308498UL))) +#define bM4_TMR62_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230849CUL))) +#define bM4_TMR62_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423084A0UL))) +#define bM4_TMR62_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423084A4UL))) +#define bM4_TMR62_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423084A8UL))) +#define bM4_TMR62_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423084ACUL))) +#define bM4_TMR62_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423084B0UL))) +#define bM4_TMR62_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423084B4UL))) +#define bM4_TMR62_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423084B8UL))) +#define bM4_TMR62_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423084BCUL))) +#define bM4_TMR62_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42308500UL))) +#define bM4_TMR62_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42308504UL))) +#define bM4_TMR62_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42308508UL))) +#define bM4_TMR62_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230850CUL))) +#define bM4_TMR62_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42308510UL))) +#define bM4_TMR62_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42308514UL))) +#define bM4_TMR62_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42308518UL))) +#define bM4_TMR62_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230851CUL))) +#define bM4_TMR62_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42308520UL))) +#define bM4_TMR62_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42308524UL))) +#define bM4_TMR62_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42308528UL))) +#define bM4_TMR62_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230852CUL))) +#define bM4_TMR62_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42308530UL))) +#define bM4_TMR62_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42308534UL))) +#define bM4_TMR62_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42308538UL))) +#define bM4_TMR62_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230853CUL))) +#define bM4_TMR62_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42308580UL))) +#define bM4_TMR62_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42308584UL))) +#define bM4_TMR62_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42308588UL))) +#define bM4_TMR62_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230858CUL))) +#define bM4_TMR62_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42308590UL))) +#define bM4_TMR62_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42308594UL))) +#define bM4_TMR62_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42308598UL))) +#define bM4_TMR62_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230859CUL))) +#define bM4_TMR62_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423085A0UL))) +#define bM4_TMR62_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423085A4UL))) +#define bM4_TMR62_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423085A8UL))) +#define bM4_TMR62_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423085ACUL))) +#define bM4_TMR62_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423085B0UL))) +#define bM4_TMR62_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423085B4UL))) +#define bM4_TMR62_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423085B8UL))) +#define bM4_TMR62_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423085BCUL))) +#define bM4_TMR62_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42308600UL))) +#define bM4_TMR62_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42308604UL))) +#define bM4_TMR62_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42308608UL))) +#define bM4_TMR62_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230860CUL))) +#define bM4_TMR62_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42308610UL))) +#define bM4_TMR62_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42308614UL))) +#define bM4_TMR62_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42308618UL))) +#define bM4_TMR62_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230861CUL))) +#define bM4_TMR62_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42308620UL))) +#define bM4_TMR62_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42308624UL))) +#define bM4_TMR62_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42308628UL))) +#define bM4_TMR62_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230862CUL))) +#define bM4_TMR62_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42308630UL))) +#define bM4_TMR62_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42308634UL))) +#define bM4_TMR62_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42308638UL))) +#define bM4_TMR62_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230863CUL))) +#define bM4_TMR62_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42308680UL))) +#define bM4_TMR62_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42308684UL))) +#define bM4_TMR62_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42308688UL))) +#define bM4_TMR62_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230868CUL))) +#define bM4_TMR62_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42308690UL))) +#define bM4_TMR62_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42308694UL))) +#define bM4_TMR62_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42308698UL))) +#define bM4_TMR62_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230869CUL))) +#define bM4_TMR62_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423086A0UL))) +#define bM4_TMR62_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423086A4UL))) +#define bM4_TMR62_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423086A8UL))) +#define bM4_TMR62_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423086ACUL))) +#define bM4_TMR62_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423086B0UL))) +#define bM4_TMR62_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423086B4UL))) +#define bM4_TMR62_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423086B8UL))) +#define bM4_TMR62_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423086BCUL))) +#define bM4_TMR62_SCMER_SCME0 (*((volatile unsigned int*)(0x42308700UL))) +#define bM4_TMR62_SCMER_SCME1 (*((volatile unsigned int*)(0x42308704UL))) +#define bM4_TMR62_SCMER_SCME2 (*((volatile unsigned int*)(0x42308708UL))) +#define bM4_TMR62_SCMER_SCME3 (*((volatile unsigned int*)(0x4230870CUL))) +#define bM4_TMR62_SCMER_SCME4 (*((volatile unsigned int*)(0x42308710UL))) +#define bM4_TMR62_SCMER_SCME5 (*((volatile unsigned int*)(0x42308714UL))) +#define bM4_TMR62_SCMER_SCME6 (*((volatile unsigned int*)(0x42308718UL))) +#define bM4_TMR62_SCMER_SCME7 (*((volatile unsigned int*)(0x4230871CUL))) +#define bM4_TMR62_SCMER_SCME8 (*((volatile unsigned int*)(0x42308720UL))) +#define bM4_TMR62_SCMER_SCME9 (*((volatile unsigned int*)(0x42308724UL))) +#define bM4_TMR62_SCMER_SCME10 (*((volatile unsigned int*)(0x42308728UL))) +#define bM4_TMR62_SCMER_SCME11 (*((volatile unsigned int*)(0x4230872CUL))) +#define bM4_TMR62_SCMER_SCME12 (*((volatile unsigned int*)(0x42308730UL))) +#define bM4_TMR62_SCMER_SCME13 (*((volatile unsigned int*)(0x42308734UL))) +#define bM4_TMR62_SCMER_SCME14 (*((volatile unsigned int*)(0x42308738UL))) +#define bM4_TMR62_SCMER_SCME15 (*((volatile unsigned int*)(0x4230873CUL))) +#define bM4_TMR62_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42308780UL))) +#define bM4_TMR62_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42308784UL))) +#define bM4_TMR62_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42308788UL))) +#define bM4_TMR62_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230878CUL))) +#define bM4_TMR62_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42308790UL))) +#define bM4_TMR62_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42308794UL))) +#define bM4_TMR62_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42308798UL))) +#define bM4_TMR62_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230879CUL))) +#define bM4_TMR62_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423087A0UL))) +#define bM4_TMR62_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423087A4UL))) +#define bM4_TMR62_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423087A8UL))) +#define bM4_TMR62_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423087ACUL))) +#define bM4_TMR62_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423087B0UL))) +#define bM4_TMR62_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423087B4UL))) +#define bM4_TMR62_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423087B8UL))) +#define bM4_TMR62_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423087BCUL))) +#define bM4_TMR62_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42308800UL))) +#define bM4_TMR62_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42308804UL))) +#define bM4_TMR62_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42308808UL))) +#define bM4_TMR62_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230880CUL))) +#define bM4_TMR62_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42308810UL))) +#define bM4_TMR62_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42308814UL))) +#define bM4_TMR62_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42308818UL))) +#define bM4_TMR62_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230881CUL))) +#define bM4_TMR62_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42308820UL))) +#define bM4_TMR62_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42308824UL))) +#define bM4_TMR62_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42308828UL))) +#define bM4_TMR62_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230882CUL))) +#define bM4_TMR62_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42308830UL))) +#define bM4_TMR62_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42308834UL))) +#define bM4_TMR62_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42308838UL))) +#define bM4_TMR62_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230883CUL))) +#define bM4_TMR62_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42308880UL))) +#define bM4_TMR62_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42308884UL))) +#define bM4_TMR62_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42308888UL))) +#define bM4_TMR62_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230888CUL))) +#define bM4_TMR62_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42308890UL))) +#define bM4_TMR62_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42308894UL))) +#define bM4_TMR62_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42308898UL))) +#define bM4_TMR62_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230889CUL))) +#define bM4_TMR62_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423088A0UL))) +#define bM4_TMR62_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423088A4UL))) +#define bM4_TMR62_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423088A8UL))) +#define bM4_TMR62_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423088ACUL))) +#define bM4_TMR62_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423088B0UL))) +#define bM4_TMR62_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423088B4UL))) +#define bM4_TMR62_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423088B8UL))) +#define bM4_TMR62_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423088BCUL))) +#define bM4_TMR62_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42308900UL))) +#define bM4_TMR62_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42308904UL))) +#define bM4_TMR62_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42308908UL))) +#define bM4_TMR62_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230890CUL))) +#define bM4_TMR62_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42308910UL))) +#define bM4_TMR62_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42308914UL))) +#define bM4_TMR62_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42308918UL))) +#define bM4_TMR62_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230891CUL))) +#define bM4_TMR62_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42308920UL))) +#define bM4_TMR62_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42308924UL))) +#define bM4_TMR62_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42308928UL))) +#define bM4_TMR62_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230892CUL))) +#define bM4_TMR62_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42308930UL))) +#define bM4_TMR62_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42308934UL))) +#define bM4_TMR62_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42308938UL))) +#define bM4_TMR62_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230893CUL))) +#define bM4_TMR62_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42308980UL))) +#define bM4_TMR62_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42308984UL))) +#define bM4_TMR62_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42308988UL))) +#define bM4_TMR62_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230898CUL))) +#define bM4_TMR62_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42308990UL))) +#define bM4_TMR62_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42308994UL))) +#define bM4_TMR62_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42308998UL))) +#define bM4_TMR62_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230899CUL))) +#define bM4_TMR62_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423089A0UL))) +#define bM4_TMR62_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423089A4UL))) +#define bM4_TMR62_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423089A8UL))) +#define bM4_TMR62_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423089ACUL))) +#define bM4_TMR62_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423089B0UL))) +#define bM4_TMR62_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423089B4UL))) +#define bM4_TMR62_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423089B8UL))) +#define bM4_TMR62_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423089BCUL))) +#define bM4_TMR62_GCONR_START (*((volatile unsigned int*)(0x42308A00UL))) +#define bM4_TMR62_GCONR_MODE0 (*((volatile unsigned int*)(0x42308A04UL))) +#define bM4_TMR62_GCONR_MODE1 (*((volatile unsigned int*)(0x42308A08UL))) +#define bM4_TMR62_GCONR_MODE2 (*((volatile unsigned int*)(0x42308A0CUL))) +#define bM4_TMR62_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42308A10UL))) +#define bM4_TMR62_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42308A14UL))) +#define bM4_TMR62_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42308A18UL))) +#define bM4_TMR62_GCONR_DIR (*((volatile unsigned int*)(0x42308A20UL))) +#define bM4_TMR62_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42308A40UL))) +#define bM4_TMR62_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42308A44UL))) +#define bM4_TMR62_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42308A48UL))) +#define bM4_TMR62_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42308A4CUL))) +#define bM4_TMR62_ICONR_INTENA (*((volatile unsigned int*)(0x42308A80UL))) +#define bM4_TMR62_ICONR_INTENB (*((volatile unsigned int*)(0x42308A84UL))) +#define bM4_TMR62_ICONR_INTENC (*((volatile unsigned int*)(0x42308A88UL))) +#define bM4_TMR62_ICONR_INTEND (*((volatile unsigned int*)(0x42308A8CUL))) +#define bM4_TMR62_ICONR_INTENE (*((volatile unsigned int*)(0x42308A90UL))) +#define bM4_TMR62_ICONR_INTENF (*((volatile unsigned int*)(0x42308A94UL))) +#define bM4_TMR62_ICONR_INTENOVF (*((volatile unsigned int*)(0x42308A98UL))) +#define bM4_TMR62_ICONR_INTENUDF (*((volatile unsigned int*)(0x42308A9CUL))) +#define bM4_TMR62_ICONR_INTENDTE (*((volatile unsigned int*)(0x42308AA0UL))) +#define bM4_TMR62_ICONR_INTENSAU (*((volatile unsigned int*)(0x42308AC0UL))) +#define bM4_TMR62_ICONR_INTENSAD (*((volatile unsigned int*)(0x42308AC4UL))) +#define bM4_TMR62_ICONR_INTENSBU (*((volatile unsigned int*)(0x42308AC8UL))) +#define bM4_TMR62_ICONR_INTENSBD (*((volatile unsigned int*)(0x42308ACCUL))) +#define bM4_TMR62_PCONR_CAPMDA (*((volatile unsigned int*)(0x42308B00UL))) +#define bM4_TMR62_PCONR_STACA (*((volatile unsigned int*)(0x42308B04UL))) +#define bM4_TMR62_PCONR_STPCA (*((volatile unsigned int*)(0x42308B08UL))) +#define bM4_TMR62_PCONR_STASTPSA (*((volatile unsigned int*)(0x42308B0CUL))) +#define bM4_TMR62_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42308B10UL))) +#define bM4_TMR62_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42308B14UL))) +#define bM4_TMR62_PCONR_PERCA0 (*((volatile unsigned int*)(0x42308B18UL))) +#define bM4_TMR62_PCONR_PERCA1 (*((volatile unsigned int*)(0x42308B1CUL))) +#define bM4_TMR62_PCONR_OUTENA (*((volatile unsigned int*)(0x42308B20UL))) +#define bM4_TMR62_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42308B2CUL))) +#define bM4_TMR62_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42308B30UL))) +#define bM4_TMR62_PCONR_CAPMDB (*((volatile unsigned int*)(0x42308B40UL))) +#define bM4_TMR62_PCONR_STACB (*((volatile unsigned int*)(0x42308B44UL))) +#define bM4_TMR62_PCONR_STPCB (*((volatile unsigned int*)(0x42308B48UL))) +#define bM4_TMR62_PCONR_STASTPSB (*((volatile unsigned int*)(0x42308B4CUL))) +#define bM4_TMR62_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42308B50UL))) +#define bM4_TMR62_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42308B54UL))) +#define bM4_TMR62_PCONR_PERCB0 (*((volatile unsigned int*)(0x42308B58UL))) +#define bM4_TMR62_PCONR_PERCB1 (*((volatile unsigned int*)(0x42308B5CUL))) +#define bM4_TMR62_PCONR_OUTENB (*((volatile unsigned int*)(0x42308B60UL))) +#define bM4_TMR62_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42308B6CUL))) +#define bM4_TMR62_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42308B70UL))) +#define bM4_TMR62_BCONR_BENA (*((volatile unsigned int*)(0x42308B80UL))) +#define bM4_TMR62_BCONR_BSEA (*((volatile unsigned int*)(0x42308B84UL))) +#define bM4_TMR62_BCONR_BENB (*((volatile unsigned int*)(0x42308B88UL))) +#define bM4_TMR62_BCONR_BSEB (*((volatile unsigned int*)(0x42308B8CUL))) +#define bM4_TMR62_BCONR_BENP (*((volatile unsigned int*)(0x42308BA0UL))) +#define bM4_TMR62_BCONR_BSEP (*((volatile unsigned int*)(0x42308BA4UL))) +#define bM4_TMR62_BCONR_BENSPA (*((volatile unsigned int*)(0x42308BC0UL))) +#define bM4_TMR62_BCONR_BSESPA (*((volatile unsigned int*)(0x42308BC4UL))) +#define bM4_TMR62_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42308BD0UL))) +#define bM4_TMR62_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42308BD4UL))) +#define bM4_TMR62_BCONR_BENSPB (*((volatile unsigned int*)(0x42308BE0UL))) +#define bM4_TMR62_BCONR_BSESPB (*((volatile unsigned int*)(0x42308BE4UL))) +#define bM4_TMR62_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42308BF0UL))) +#define bM4_TMR62_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42308BF4UL))) +#define bM4_TMR62_DCONR_DTCEN (*((volatile unsigned int*)(0x42308C00UL))) +#define bM4_TMR62_DCONR_DTBENU (*((volatile unsigned int*)(0x42308C10UL))) +#define bM4_TMR62_DCONR_DTBEND (*((volatile unsigned int*)(0x42308C14UL))) +#define bM4_TMR62_DCONR_SEPA (*((volatile unsigned int*)(0x42308C20UL))) +#define bM4_TMR62_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42308D00UL))) +#define bM4_TMR62_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42308D04UL))) +#define bM4_TMR62_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42308D08UL))) +#define bM4_TMR62_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42308D10UL))) +#define bM4_TMR62_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42308D14UL))) +#define bM4_TMR62_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42308D18UL))) +#define bM4_TMR62_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42308D40UL))) +#define bM4_TMR62_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42308D44UL))) +#define bM4_TMR62_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42308D48UL))) +#define bM4_TMR62_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42308D50UL))) +#define bM4_TMR62_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42308D54UL))) +#define bM4_TMR62_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42308D58UL))) +#define bM4_TMR62_VPERR_SPPERIA (*((volatile unsigned int*)(0x42308DA0UL))) +#define bM4_TMR62_VPERR_SPPERIB (*((volatile unsigned int*)(0x42308DA4UL))) +#define bM4_TMR62_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42308DC0UL))) +#define bM4_TMR62_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42308DC4UL))) +#define bM4_TMR62_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42308DC8UL))) +#define bM4_TMR62_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42308DCCUL))) +#define bM4_TMR62_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42308DD0UL))) +#define bM4_TMR62_STFLR_CMAF (*((volatile unsigned int*)(0x42308E00UL))) +#define bM4_TMR62_STFLR_CMBF (*((volatile unsigned int*)(0x42308E04UL))) +#define bM4_TMR62_STFLR_CMCF (*((volatile unsigned int*)(0x42308E08UL))) +#define bM4_TMR62_STFLR_CMDF (*((volatile unsigned int*)(0x42308E0CUL))) +#define bM4_TMR62_STFLR_CMEF (*((volatile unsigned int*)(0x42308E10UL))) +#define bM4_TMR62_STFLR_CMFF (*((volatile unsigned int*)(0x42308E14UL))) +#define bM4_TMR62_STFLR_OVFF (*((volatile unsigned int*)(0x42308E18UL))) +#define bM4_TMR62_STFLR_UDFF (*((volatile unsigned int*)(0x42308E1CUL))) +#define bM4_TMR62_STFLR_DTEF (*((volatile unsigned int*)(0x42308E20UL))) +#define bM4_TMR62_STFLR_CMSAUF (*((volatile unsigned int*)(0x42308E24UL))) +#define bM4_TMR62_STFLR_CMSADF (*((volatile unsigned int*)(0x42308E28UL))) +#define bM4_TMR62_STFLR_CMSBUF (*((volatile unsigned int*)(0x42308E2CUL))) +#define bM4_TMR62_STFLR_CMSBDF (*((volatile unsigned int*)(0x42308E30UL))) +#define bM4_TMR62_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42308E54UL))) +#define bM4_TMR62_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42308E58UL))) +#define bM4_TMR62_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42308E5CUL))) +#define bM4_TMR62_STFLR_DIRF (*((volatile unsigned int*)(0x42308E7CUL))) +#define bM4_TMR62_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42308E80UL))) +#define bM4_TMR62_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42308E84UL))) +#define bM4_TMR62_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42308E90UL))) +#define bM4_TMR62_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42308E94UL))) +#define bM4_TMR62_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42308E98UL))) +#define bM4_TMR62_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42308E9CUL))) +#define bM4_TMR62_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42308EA0UL))) +#define bM4_TMR62_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42308EA4UL))) +#define bM4_TMR62_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42308EA8UL))) +#define bM4_TMR62_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42308EACUL))) +#define bM4_TMR62_HSTAR_STARTS (*((volatile unsigned int*)(0x42308EFCUL))) +#define bM4_TMR62_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42308F00UL))) +#define bM4_TMR62_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42308F04UL))) +#define bM4_TMR62_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42308F10UL))) +#define bM4_TMR62_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42308F14UL))) +#define bM4_TMR62_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42308F18UL))) +#define bM4_TMR62_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42308F1CUL))) +#define bM4_TMR62_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42308F20UL))) +#define bM4_TMR62_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42308F24UL))) +#define bM4_TMR62_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42308F28UL))) +#define bM4_TMR62_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42308F2CUL))) +#define bM4_TMR62_HSTPR_STOPS (*((volatile unsigned int*)(0x42308F7CUL))) +#define bM4_TMR62_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42308F80UL))) +#define bM4_TMR62_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42308F84UL))) +#define bM4_TMR62_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42308F90UL))) +#define bM4_TMR62_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42308F94UL))) +#define bM4_TMR62_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42308F98UL))) +#define bM4_TMR62_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42308F9CUL))) +#define bM4_TMR62_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42308FA0UL))) +#define bM4_TMR62_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42308FA4UL))) +#define bM4_TMR62_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42308FA8UL))) +#define bM4_TMR62_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42308FACUL))) +#define bM4_TMR62_HCLRR_CLEARS (*((volatile unsigned int*)(0x42308FFCUL))) +#define bM4_TMR62_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42309000UL))) +#define bM4_TMR62_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42309004UL))) +#define bM4_TMR62_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42309010UL))) +#define bM4_TMR62_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42309014UL))) +#define bM4_TMR62_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42309018UL))) +#define bM4_TMR62_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230901CUL))) +#define bM4_TMR62_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42309020UL))) +#define bM4_TMR62_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42309024UL))) +#define bM4_TMR62_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42309028UL))) +#define bM4_TMR62_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230902CUL))) +#define bM4_TMR62_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42309080UL))) +#define bM4_TMR62_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42309084UL))) +#define bM4_TMR62_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42309090UL))) +#define bM4_TMR62_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42309094UL))) +#define bM4_TMR62_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42309098UL))) +#define bM4_TMR62_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230909CUL))) +#define bM4_TMR62_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423090A0UL))) +#define bM4_TMR62_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423090A4UL))) +#define bM4_TMR62_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423090A8UL))) +#define bM4_TMR62_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423090ACUL))) +#define bM4_TMR62_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42309100UL))) +#define bM4_TMR62_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42309104UL))) +#define bM4_TMR62_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42309108UL))) +#define bM4_TMR62_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230910CUL))) +#define bM4_TMR62_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42309110UL))) +#define bM4_TMR62_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42309114UL))) +#define bM4_TMR62_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42309118UL))) +#define bM4_TMR62_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230911CUL))) +#define bM4_TMR62_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42309120UL))) +#define bM4_TMR62_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42309124UL))) +#define bM4_TMR62_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42309128UL))) +#define bM4_TMR62_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230912CUL))) +#define bM4_TMR62_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42309140UL))) +#define bM4_TMR62_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42309144UL))) +#define bM4_TMR62_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42309180UL))) +#define bM4_TMR62_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42309184UL))) +#define bM4_TMR62_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42309188UL))) +#define bM4_TMR62_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230918CUL))) +#define bM4_TMR62_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42309190UL))) +#define bM4_TMR62_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42309194UL))) +#define bM4_TMR62_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42309198UL))) +#define bM4_TMR62_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230919CUL))) +#define bM4_TMR62_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423091A0UL))) +#define bM4_TMR62_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423091A4UL))) +#define bM4_TMR62_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423091A8UL))) +#define bM4_TMR62_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423091ACUL))) +#define bM4_TMR62_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423091C0UL))) +#define bM4_TMR62_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423091C4UL))) +#define bM4_TMR63_CNTER_CNT0 (*((volatile unsigned int*)(0x42310000UL))) +#define bM4_TMR63_CNTER_CNT1 (*((volatile unsigned int*)(0x42310004UL))) +#define bM4_TMR63_CNTER_CNT2 (*((volatile unsigned int*)(0x42310008UL))) +#define bM4_TMR63_CNTER_CNT3 (*((volatile unsigned int*)(0x4231000CUL))) +#define bM4_TMR63_CNTER_CNT4 (*((volatile unsigned int*)(0x42310010UL))) +#define bM4_TMR63_CNTER_CNT5 (*((volatile unsigned int*)(0x42310014UL))) +#define bM4_TMR63_CNTER_CNT6 (*((volatile unsigned int*)(0x42310018UL))) +#define bM4_TMR63_CNTER_CNT7 (*((volatile unsigned int*)(0x4231001CUL))) +#define bM4_TMR63_CNTER_CNT8 (*((volatile unsigned int*)(0x42310020UL))) +#define bM4_TMR63_CNTER_CNT9 (*((volatile unsigned int*)(0x42310024UL))) +#define bM4_TMR63_CNTER_CNT10 (*((volatile unsigned int*)(0x42310028UL))) +#define bM4_TMR63_CNTER_CNT11 (*((volatile unsigned int*)(0x4231002CUL))) +#define bM4_TMR63_CNTER_CNT12 (*((volatile unsigned int*)(0x42310030UL))) +#define bM4_TMR63_CNTER_CNT13 (*((volatile unsigned int*)(0x42310034UL))) +#define bM4_TMR63_CNTER_CNT14 (*((volatile unsigned int*)(0x42310038UL))) +#define bM4_TMR63_CNTER_CNT15 (*((volatile unsigned int*)(0x4231003CUL))) +#define bM4_TMR63_PERAR_PERA0 (*((volatile unsigned int*)(0x42310080UL))) +#define bM4_TMR63_PERAR_PERA1 (*((volatile unsigned int*)(0x42310084UL))) +#define bM4_TMR63_PERAR_PERA2 (*((volatile unsigned int*)(0x42310088UL))) +#define bM4_TMR63_PERAR_PERA3 (*((volatile unsigned int*)(0x4231008CUL))) +#define bM4_TMR63_PERAR_PERA4 (*((volatile unsigned int*)(0x42310090UL))) +#define bM4_TMR63_PERAR_PERA5 (*((volatile unsigned int*)(0x42310094UL))) +#define bM4_TMR63_PERAR_PERA6 (*((volatile unsigned int*)(0x42310098UL))) +#define bM4_TMR63_PERAR_PERA7 (*((volatile unsigned int*)(0x4231009CUL))) +#define bM4_TMR63_PERAR_PERA8 (*((volatile unsigned int*)(0x423100A0UL))) +#define bM4_TMR63_PERAR_PERA9 (*((volatile unsigned int*)(0x423100A4UL))) +#define bM4_TMR63_PERAR_PERA10 (*((volatile unsigned int*)(0x423100A8UL))) +#define bM4_TMR63_PERAR_PERA11 (*((volatile unsigned int*)(0x423100ACUL))) +#define bM4_TMR63_PERAR_PERA12 (*((volatile unsigned int*)(0x423100B0UL))) +#define bM4_TMR63_PERAR_PERA13 (*((volatile unsigned int*)(0x423100B4UL))) +#define bM4_TMR63_PERAR_PERA14 (*((volatile unsigned int*)(0x423100B8UL))) +#define bM4_TMR63_PERAR_PERA15 (*((volatile unsigned int*)(0x423100BCUL))) +#define bM4_TMR63_PERBR_PERB0 (*((volatile unsigned int*)(0x42310100UL))) +#define bM4_TMR63_PERBR_PERB1 (*((volatile unsigned int*)(0x42310104UL))) +#define bM4_TMR63_PERBR_PERB2 (*((volatile unsigned int*)(0x42310108UL))) +#define bM4_TMR63_PERBR_PERB3 (*((volatile unsigned int*)(0x4231010CUL))) +#define bM4_TMR63_PERBR_PERB4 (*((volatile unsigned int*)(0x42310110UL))) +#define bM4_TMR63_PERBR_PERB5 (*((volatile unsigned int*)(0x42310114UL))) +#define bM4_TMR63_PERBR_PERB6 (*((volatile unsigned int*)(0x42310118UL))) +#define bM4_TMR63_PERBR_PERB7 (*((volatile unsigned int*)(0x4231011CUL))) +#define bM4_TMR63_PERBR_PERB8 (*((volatile unsigned int*)(0x42310120UL))) +#define bM4_TMR63_PERBR_PERB9 (*((volatile unsigned int*)(0x42310124UL))) +#define bM4_TMR63_PERBR_PERB10 (*((volatile unsigned int*)(0x42310128UL))) +#define bM4_TMR63_PERBR_PERB11 (*((volatile unsigned int*)(0x4231012CUL))) +#define bM4_TMR63_PERBR_PERB12 (*((volatile unsigned int*)(0x42310130UL))) +#define bM4_TMR63_PERBR_PERB13 (*((volatile unsigned int*)(0x42310134UL))) +#define bM4_TMR63_PERBR_PERB14 (*((volatile unsigned int*)(0x42310138UL))) +#define bM4_TMR63_PERBR_PERB15 (*((volatile unsigned int*)(0x4231013CUL))) +#define bM4_TMR63_PERCR_PERC0 (*((volatile unsigned int*)(0x42310180UL))) +#define bM4_TMR63_PERCR_PERC1 (*((volatile unsigned int*)(0x42310184UL))) +#define bM4_TMR63_PERCR_PERC2 (*((volatile unsigned int*)(0x42310188UL))) +#define bM4_TMR63_PERCR_PERC3 (*((volatile unsigned int*)(0x4231018CUL))) +#define bM4_TMR63_PERCR_PERC4 (*((volatile unsigned int*)(0x42310190UL))) +#define bM4_TMR63_PERCR_PERC5 (*((volatile unsigned int*)(0x42310194UL))) +#define bM4_TMR63_PERCR_PERC6 (*((volatile unsigned int*)(0x42310198UL))) +#define bM4_TMR63_PERCR_PERC7 (*((volatile unsigned int*)(0x4231019CUL))) +#define bM4_TMR63_PERCR_PERC8 (*((volatile unsigned int*)(0x423101A0UL))) +#define bM4_TMR63_PERCR_PERC9 (*((volatile unsigned int*)(0x423101A4UL))) +#define bM4_TMR63_PERCR_PERC10 (*((volatile unsigned int*)(0x423101A8UL))) +#define bM4_TMR63_PERCR_PERC11 (*((volatile unsigned int*)(0x423101ACUL))) +#define bM4_TMR63_PERCR_PERC12 (*((volatile unsigned int*)(0x423101B0UL))) +#define bM4_TMR63_PERCR_PERC13 (*((volatile unsigned int*)(0x423101B4UL))) +#define bM4_TMR63_PERCR_PERC14 (*((volatile unsigned int*)(0x423101B8UL))) +#define bM4_TMR63_PERCR_PERC15 (*((volatile unsigned int*)(0x423101BCUL))) +#define bM4_TMR63_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42310200UL))) +#define bM4_TMR63_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42310204UL))) +#define bM4_TMR63_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42310208UL))) +#define bM4_TMR63_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4231020CUL))) +#define bM4_TMR63_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42310210UL))) +#define bM4_TMR63_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42310214UL))) +#define bM4_TMR63_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42310218UL))) +#define bM4_TMR63_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4231021CUL))) +#define bM4_TMR63_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42310220UL))) +#define bM4_TMR63_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42310224UL))) +#define bM4_TMR63_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42310228UL))) +#define bM4_TMR63_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4231022CUL))) +#define bM4_TMR63_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42310230UL))) +#define bM4_TMR63_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42310234UL))) +#define bM4_TMR63_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42310238UL))) +#define bM4_TMR63_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4231023CUL))) +#define bM4_TMR63_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42310280UL))) +#define bM4_TMR63_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42310284UL))) +#define bM4_TMR63_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42310288UL))) +#define bM4_TMR63_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4231028CUL))) +#define bM4_TMR63_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42310290UL))) +#define bM4_TMR63_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42310294UL))) +#define bM4_TMR63_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42310298UL))) +#define bM4_TMR63_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4231029CUL))) +#define bM4_TMR63_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423102A0UL))) +#define bM4_TMR63_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423102A4UL))) +#define bM4_TMR63_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423102A8UL))) +#define bM4_TMR63_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423102ACUL))) +#define bM4_TMR63_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423102B0UL))) +#define bM4_TMR63_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423102B4UL))) +#define bM4_TMR63_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423102B8UL))) +#define bM4_TMR63_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423102BCUL))) +#define bM4_TMR63_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42310300UL))) +#define bM4_TMR63_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42310304UL))) +#define bM4_TMR63_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42310308UL))) +#define bM4_TMR63_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4231030CUL))) +#define bM4_TMR63_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42310310UL))) +#define bM4_TMR63_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42310314UL))) +#define bM4_TMR63_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42310318UL))) +#define bM4_TMR63_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4231031CUL))) +#define bM4_TMR63_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42310320UL))) +#define bM4_TMR63_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42310324UL))) +#define bM4_TMR63_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42310328UL))) +#define bM4_TMR63_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4231032CUL))) +#define bM4_TMR63_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42310330UL))) +#define bM4_TMR63_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42310334UL))) +#define bM4_TMR63_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42310338UL))) +#define bM4_TMR63_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4231033CUL))) +#define bM4_TMR63_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42310380UL))) +#define bM4_TMR63_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42310384UL))) +#define bM4_TMR63_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42310388UL))) +#define bM4_TMR63_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4231038CUL))) +#define bM4_TMR63_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42310390UL))) +#define bM4_TMR63_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42310394UL))) +#define bM4_TMR63_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42310398UL))) +#define bM4_TMR63_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4231039CUL))) +#define bM4_TMR63_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423103A0UL))) +#define bM4_TMR63_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423103A4UL))) +#define bM4_TMR63_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423103A8UL))) +#define bM4_TMR63_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423103ACUL))) +#define bM4_TMR63_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423103B0UL))) +#define bM4_TMR63_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423103B4UL))) +#define bM4_TMR63_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423103B8UL))) +#define bM4_TMR63_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423103BCUL))) +#define bM4_TMR63_GCMER_GCME0 (*((volatile unsigned int*)(0x42310400UL))) +#define bM4_TMR63_GCMER_GCME1 (*((volatile unsigned int*)(0x42310404UL))) +#define bM4_TMR63_GCMER_GCME2 (*((volatile unsigned int*)(0x42310408UL))) +#define bM4_TMR63_GCMER_GCME3 (*((volatile unsigned int*)(0x4231040CUL))) +#define bM4_TMR63_GCMER_GCME4 (*((volatile unsigned int*)(0x42310410UL))) +#define bM4_TMR63_GCMER_GCME5 (*((volatile unsigned int*)(0x42310414UL))) +#define bM4_TMR63_GCMER_GCME6 (*((volatile unsigned int*)(0x42310418UL))) +#define bM4_TMR63_GCMER_GCME7 (*((volatile unsigned int*)(0x4231041CUL))) +#define bM4_TMR63_GCMER_GCME8 (*((volatile unsigned int*)(0x42310420UL))) +#define bM4_TMR63_GCMER_GCME9 (*((volatile unsigned int*)(0x42310424UL))) +#define bM4_TMR63_GCMER_GCME10 (*((volatile unsigned int*)(0x42310428UL))) +#define bM4_TMR63_GCMER_GCME11 (*((volatile unsigned int*)(0x4231042CUL))) +#define bM4_TMR63_GCMER_GCME12 (*((volatile unsigned int*)(0x42310430UL))) +#define bM4_TMR63_GCMER_GCME13 (*((volatile unsigned int*)(0x42310434UL))) +#define bM4_TMR63_GCMER_GCME14 (*((volatile unsigned int*)(0x42310438UL))) +#define bM4_TMR63_GCMER_GCME15 (*((volatile unsigned int*)(0x4231043CUL))) +#define bM4_TMR63_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42310480UL))) +#define bM4_TMR63_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42310484UL))) +#define bM4_TMR63_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42310488UL))) +#define bM4_TMR63_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4231048CUL))) +#define bM4_TMR63_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42310490UL))) +#define bM4_TMR63_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42310494UL))) +#define bM4_TMR63_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42310498UL))) +#define bM4_TMR63_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4231049CUL))) +#define bM4_TMR63_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423104A0UL))) +#define bM4_TMR63_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423104A4UL))) +#define bM4_TMR63_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423104A8UL))) +#define bM4_TMR63_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423104ACUL))) +#define bM4_TMR63_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423104B0UL))) +#define bM4_TMR63_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423104B4UL))) +#define bM4_TMR63_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423104B8UL))) +#define bM4_TMR63_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423104BCUL))) +#define bM4_TMR63_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42310500UL))) +#define bM4_TMR63_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42310504UL))) +#define bM4_TMR63_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42310508UL))) +#define bM4_TMR63_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4231050CUL))) +#define bM4_TMR63_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42310510UL))) +#define bM4_TMR63_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42310514UL))) +#define bM4_TMR63_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42310518UL))) +#define bM4_TMR63_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4231051CUL))) +#define bM4_TMR63_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42310520UL))) +#define bM4_TMR63_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42310524UL))) +#define bM4_TMR63_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42310528UL))) +#define bM4_TMR63_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4231052CUL))) +#define bM4_TMR63_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42310530UL))) +#define bM4_TMR63_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42310534UL))) +#define bM4_TMR63_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42310538UL))) +#define bM4_TMR63_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4231053CUL))) +#define bM4_TMR63_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42310580UL))) +#define bM4_TMR63_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42310584UL))) +#define bM4_TMR63_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42310588UL))) +#define bM4_TMR63_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4231058CUL))) +#define bM4_TMR63_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42310590UL))) +#define bM4_TMR63_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42310594UL))) +#define bM4_TMR63_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42310598UL))) +#define bM4_TMR63_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4231059CUL))) +#define bM4_TMR63_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423105A0UL))) +#define bM4_TMR63_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423105A4UL))) +#define bM4_TMR63_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423105A8UL))) +#define bM4_TMR63_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423105ACUL))) +#define bM4_TMR63_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423105B0UL))) +#define bM4_TMR63_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423105B4UL))) +#define bM4_TMR63_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423105B8UL))) +#define bM4_TMR63_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423105BCUL))) +#define bM4_TMR63_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42310600UL))) +#define bM4_TMR63_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42310604UL))) +#define bM4_TMR63_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42310608UL))) +#define bM4_TMR63_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4231060CUL))) +#define bM4_TMR63_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42310610UL))) +#define bM4_TMR63_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42310614UL))) +#define bM4_TMR63_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42310618UL))) +#define bM4_TMR63_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4231061CUL))) +#define bM4_TMR63_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42310620UL))) +#define bM4_TMR63_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42310624UL))) +#define bM4_TMR63_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42310628UL))) +#define bM4_TMR63_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4231062CUL))) +#define bM4_TMR63_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42310630UL))) +#define bM4_TMR63_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42310634UL))) +#define bM4_TMR63_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42310638UL))) +#define bM4_TMR63_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4231063CUL))) +#define bM4_TMR63_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42310680UL))) +#define bM4_TMR63_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42310684UL))) +#define bM4_TMR63_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42310688UL))) +#define bM4_TMR63_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4231068CUL))) +#define bM4_TMR63_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42310690UL))) +#define bM4_TMR63_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42310694UL))) +#define bM4_TMR63_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42310698UL))) +#define bM4_TMR63_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4231069CUL))) +#define bM4_TMR63_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423106A0UL))) +#define bM4_TMR63_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423106A4UL))) +#define bM4_TMR63_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423106A8UL))) +#define bM4_TMR63_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423106ACUL))) +#define bM4_TMR63_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423106B0UL))) +#define bM4_TMR63_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423106B4UL))) +#define bM4_TMR63_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423106B8UL))) +#define bM4_TMR63_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423106BCUL))) +#define bM4_TMR63_SCMER_SCME0 (*((volatile unsigned int*)(0x42310700UL))) +#define bM4_TMR63_SCMER_SCME1 (*((volatile unsigned int*)(0x42310704UL))) +#define bM4_TMR63_SCMER_SCME2 (*((volatile unsigned int*)(0x42310708UL))) +#define bM4_TMR63_SCMER_SCME3 (*((volatile unsigned int*)(0x4231070CUL))) +#define bM4_TMR63_SCMER_SCME4 (*((volatile unsigned int*)(0x42310710UL))) +#define bM4_TMR63_SCMER_SCME5 (*((volatile unsigned int*)(0x42310714UL))) +#define bM4_TMR63_SCMER_SCME6 (*((volatile unsigned int*)(0x42310718UL))) +#define bM4_TMR63_SCMER_SCME7 (*((volatile unsigned int*)(0x4231071CUL))) +#define bM4_TMR63_SCMER_SCME8 (*((volatile unsigned int*)(0x42310720UL))) +#define bM4_TMR63_SCMER_SCME9 (*((volatile unsigned int*)(0x42310724UL))) +#define bM4_TMR63_SCMER_SCME10 (*((volatile unsigned int*)(0x42310728UL))) +#define bM4_TMR63_SCMER_SCME11 (*((volatile unsigned int*)(0x4231072CUL))) +#define bM4_TMR63_SCMER_SCME12 (*((volatile unsigned int*)(0x42310730UL))) +#define bM4_TMR63_SCMER_SCME13 (*((volatile unsigned int*)(0x42310734UL))) +#define bM4_TMR63_SCMER_SCME14 (*((volatile unsigned int*)(0x42310738UL))) +#define bM4_TMR63_SCMER_SCME15 (*((volatile unsigned int*)(0x4231073CUL))) +#define bM4_TMR63_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42310780UL))) +#define bM4_TMR63_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42310784UL))) +#define bM4_TMR63_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42310788UL))) +#define bM4_TMR63_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4231078CUL))) +#define bM4_TMR63_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42310790UL))) +#define bM4_TMR63_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42310794UL))) +#define bM4_TMR63_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42310798UL))) +#define bM4_TMR63_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4231079CUL))) +#define bM4_TMR63_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423107A0UL))) +#define bM4_TMR63_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423107A4UL))) +#define bM4_TMR63_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423107A8UL))) +#define bM4_TMR63_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423107ACUL))) +#define bM4_TMR63_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423107B0UL))) +#define bM4_TMR63_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423107B4UL))) +#define bM4_TMR63_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423107B8UL))) +#define bM4_TMR63_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423107BCUL))) +#define bM4_TMR63_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42310800UL))) +#define bM4_TMR63_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42310804UL))) +#define bM4_TMR63_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42310808UL))) +#define bM4_TMR63_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4231080CUL))) +#define bM4_TMR63_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42310810UL))) +#define bM4_TMR63_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42310814UL))) +#define bM4_TMR63_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42310818UL))) +#define bM4_TMR63_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4231081CUL))) +#define bM4_TMR63_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42310820UL))) +#define bM4_TMR63_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42310824UL))) +#define bM4_TMR63_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42310828UL))) +#define bM4_TMR63_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4231082CUL))) +#define bM4_TMR63_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42310830UL))) +#define bM4_TMR63_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42310834UL))) +#define bM4_TMR63_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42310838UL))) +#define bM4_TMR63_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4231083CUL))) +#define bM4_TMR63_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42310880UL))) +#define bM4_TMR63_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42310884UL))) +#define bM4_TMR63_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42310888UL))) +#define bM4_TMR63_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4231088CUL))) +#define bM4_TMR63_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42310890UL))) +#define bM4_TMR63_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42310894UL))) +#define bM4_TMR63_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42310898UL))) +#define bM4_TMR63_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4231089CUL))) +#define bM4_TMR63_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423108A0UL))) +#define bM4_TMR63_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423108A4UL))) +#define bM4_TMR63_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423108A8UL))) +#define bM4_TMR63_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423108ACUL))) +#define bM4_TMR63_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423108B0UL))) +#define bM4_TMR63_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423108B4UL))) +#define bM4_TMR63_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423108B8UL))) +#define bM4_TMR63_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423108BCUL))) +#define bM4_TMR63_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42310900UL))) +#define bM4_TMR63_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42310904UL))) +#define bM4_TMR63_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42310908UL))) +#define bM4_TMR63_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4231090CUL))) +#define bM4_TMR63_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42310910UL))) +#define bM4_TMR63_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42310914UL))) +#define bM4_TMR63_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42310918UL))) +#define bM4_TMR63_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4231091CUL))) +#define bM4_TMR63_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42310920UL))) +#define bM4_TMR63_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42310924UL))) +#define bM4_TMR63_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42310928UL))) +#define bM4_TMR63_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4231092CUL))) +#define bM4_TMR63_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42310930UL))) +#define bM4_TMR63_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42310934UL))) +#define bM4_TMR63_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42310938UL))) +#define bM4_TMR63_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4231093CUL))) +#define bM4_TMR63_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42310980UL))) +#define bM4_TMR63_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42310984UL))) +#define bM4_TMR63_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42310988UL))) +#define bM4_TMR63_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4231098CUL))) +#define bM4_TMR63_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42310990UL))) +#define bM4_TMR63_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42310994UL))) +#define bM4_TMR63_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42310998UL))) +#define bM4_TMR63_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4231099CUL))) +#define bM4_TMR63_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423109A0UL))) +#define bM4_TMR63_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423109A4UL))) +#define bM4_TMR63_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423109A8UL))) +#define bM4_TMR63_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423109ACUL))) +#define bM4_TMR63_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423109B0UL))) +#define bM4_TMR63_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423109B4UL))) +#define bM4_TMR63_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423109B8UL))) +#define bM4_TMR63_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423109BCUL))) +#define bM4_TMR63_GCONR_START (*((volatile unsigned int*)(0x42310A00UL))) +#define bM4_TMR63_GCONR_MODE0 (*((volatile unsigned int*)(0x42310A04UL))) +#define bM4_TMR63_GCONR_MODE1 (*((volatile unsigned int*)(0x42310A08UL))) +#define bM4_TMR63_GCONR_MODE2 (*((volatile unsigned int*)(0x42310A0CUL))) +#define bM4_TMR63_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42310A10UL))) +#define bM4_TMR63_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42310A14UL))) +#define bM4_TMR63_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42310A18UL))) +#define bM4_TMR63_GCONR_DIR (*((volatile unsigned int*)(0x42310A20UL))) +#define bM4_TMR63_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42310A40UL))) +#define bM4_TMR63_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42310A44UL))) +#define bM4_TMR63_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42310A48UL))) +#define bM4_TMR63_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42310A4CUL))) +#define bM4_TMR63_ICONR_INTENA (*((volatile unsigned int*)(0x42310A80UL))) +#define bM4_TMR63_ICONR_INTENB (*((volatile unsigned int*)(0x42310A84UL))) +#define bM4_TMR63_ICONR_INTENC (*((volatile unsigned int*)(0x42310A88UL))) +#define bM4_TMR63_ICONR_INTEND (*((volatile unsigned int*)(0x42310A8CUL))) +#define bM4_TMR63_ICONR_INTENE (*((volatile unsigned int*)(0x42310A90UL))) +#define bM4_TMR63_ICONR_INTENF (*((volatile unsigned int*)(0x42310A94UL))) +#define bM4_TMR63_ICONR_INTENOVF (*((volatile unsigned int*)(0x42310A98UL))) +#define bM4_TMR63_ICONR_INTENUDF (*((volatile unsigned int*)(0x42310A9CUL))) +#define bM4_TMR63_ICONR_INTENDTE (*((volatile unsigned int*)(0x42310AA0UL))) +#define bM4_TMR63_ICONR_INTENSAU (*((volatile unsigned int*)(0x42310AC0UL))) +#define bM4_TMR63_ICONR_INTENSAD (*((volatile unsigned int*)(0x42310AC4UL))) +#define bM4_TMR63_ICONR_INTENSBU (*((volatile unsigned int*)(0x42310AC8UL))) +#define bM4_TMR63_ICONR_INTENSBD (*((volatile unsigned int*)(0x42310ACCUL))) +#define bM4_TMR63_PCONR_CAPMDA (*((volatile unsigned int*)(0x42310B00UL))) +#define bM4_TMR63_PCONR_STACA (*((volatile unsigned int*)(0x42310B04UL))) +#define bM4_TMR63_PCONR_STPCA (*((volatile unsigned int*)(0x42310B08UL))) +#define bM4_TMR63_PCONR_STASTPSA (*((volatile unsigned int*)(0x42310B0CUL))) +#define bM4_TMR63_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42310B10UL))) +#define bM4_TMR63_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42310B14UL))) +#define bM4_TMR63_PCONR_PERCA0 (*((volatile unsigned int*)(0x42310B18UL))) +#define bM4_TMR63_PCONR_PERCA1 (*((volatile unsigned int*)(0x42310B1CUL))) +#define bM4_TMR63_PCONR_OUTENA (*((volatile unsigned int*)(0x42310B20UL))) +#define bM4_TMR63_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42310B2CUL))) +#define bM4_TMR63_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42310B30UL))) +#define bM4_TMR63_PCONR_CAPMDB (*((volatile unsigned int*)(0x42310B40UL))) +#define bM4_TMR63_PCONR_STACB (*((volatile unsigned int*)(0x42310B44UL))) +#define bM4_TMR63_PCONR_STPCB (*((volatile unsigned int*)(0x42310B48UL))) +#define bM4_TMR63_PCONR_STASTPSB (*((volatile unsigned int*)(0x42310B4CUL))) +#define bM4_TMR63_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42310B50UL))) +#define bM4_TMR63_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42310B54UL))) +#define bM4_TMR63_PCONR_PERCB0 (*((volatile unsigned int*)(0x42310B58UL))) +#define bM4_TMR63_PCONR_PERCB1 (*((volatile unsigned int*)(0x42310B5CUL))) +#define bM4_TMR63_PCONR_OUTENB (*((volatile unsigned int*)(0x42310B60UL))) +#define bM4_TMR63_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42310B6CUL))) +#define bM4_TMR63_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42310B70UL))) +#define bM4_TMR63_BCONR_BENA (*((volatile unsigned int*)(0x42310B80UL))) +#define bM4_TMR63_BCONR_BSEA (*((volatile unsigned int*)(0x42310B84UL))) +#define bM4_TMR63_BCONR_BENB (*((volatile unsigned int*)(0x42310B88UL))) +#define bM4_TMR63_BCONR_BSEB (*((volatile unsigned int*)(0x42310B8CUL))) +#define bM4_TMR63_BCONR_BENP (*((volatile unsigned int*)(0x42310BA0UL))) +#define bM4_TMR63_BCONR_BSEP (*((volatile unsigned int*)(0x42310BA4UL))) +#define bM4_TMR63_BCONR_BENSPA (*((volatile unsigned int*)(0x42310BC0UL))) +#define bM4_TMR63_BCONR_BSESPA (*((volatile unsigned int*)(0x42310BC4UL))) +#define bM4_TMR63_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42310BD0UL))) +#define bM4_TMR63_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42310BD4UL))) +#define bM4_TMR63_BCONR_BENSPB (*((volatile unsigned int*)(0x42310BE0UL))) +#define bM4_TMR63_BCONR_BSESPB (*((volatile unsigned int*)(0x42310BE4UL))) +#define bM4_TMR63_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42310BF0UL))) +#define bM4_TMR63_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42310BF4UL))) +#define bM4_TMR63_DCONR_DTCEN (*((volatile unsigned int*)(0x42310C00UL))) +#define bM4_TMR63_DCONR_DTBENU (*((volatile unsigned int*)(0x42310C10UL))) +#define bM4_TMR63_DCONR_DTBEND (*((volatile unsigned int*)(0x42310C14UL))) +#define bM4_TMR63_DCONR_SEPA (*((volatile unsigned int*)(0x42310C20UL))) +#define bM4_TMR63_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42310D00UL))) +#define bM4_TMR63_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42310D04UL))) +#define bM4_TMR63_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42310D08UL))) +#define bM4_TMR63_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42310D10UL))) +#define bM4_TMR63_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42310D14UL))) +#define bM4_TMR63_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42310D18UL))) +#define bM4_TMR63_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42310D40UL))) +#define bM4_TMR63_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42310D44UL))) +#define bM4_TMR63_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42310D48UL))) +#define bM4_TMR63_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42310D50UL))) +#define bM4_TMR63_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42310D54UL))) +#define bM4_TMR63_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42310D58UL))) +#define bM4_TMR63_VPERR_SPPERIA (*((volatile unsigned int*)(0x42310DA0UL))) +#define bM4_TMR63_VPERR_SPPERIB (*((volatile unsigned int*)(0x42310DA4UL))) +#define bM4_TMR63_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42310DC0UL))) +#define bM4_TMR63_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42310DC4UL))) +#define bM4_TMR63_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42310DC8UL))) +#define bM4_TMR63_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42310DCCUL))) +#define bM4_TMR63_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42310DD0UL))) +#define bM4_TMR63_STFLR_CMAF (*((volatile unsigned int*)(0x42310E00UL))) +#define bM4_TMR63_STFLR_CMBF (*((volatile unsigned int*)(0x42310E04UL))) +#define bM4_TMR63_STFLR_CMCF (*((volatile unsigned int*)(0x42310E08UL))) +#define bM4_TMR63_STFLR_CMDF (*((volatile unsigned int*)(0x42310E0CUL))) +#define bM4_TMR63_STFLR_CMEF (*((volatile unsigned int*)(0x42310E10UL))) +#define bM4_TMR63_STFLR_CMFF (*((volatile unsigned int*)(0x42310E14UL))) +#define bM4_TMR63_STFLR_OVFF (*((volatile unsigned int*)(0x42310E18UL))) +#define bM4_TMR63_STFLR_UDFF (*((volatile unsigned int*)(0x42310E1CUL))) +#define bM4_TMR63_STFLR_DTEF (*((volatile unsigned int*)(0x42310E20UL))) +#define bM4_TMR63_STFLR_CMSAUF (*((volatile unsigned int*)(0x42310E24UL))) +#define bM4_TMR63_STFLR_CMSADF (*((volatile unsigned int*)(0x42310E28UL))) +#define bM4_TMR63_STFLR_CMSBUF (*((volatile unsigned int*)(0x42310E2CUL))) +#define bM4_TMR63_STFLR_CMSBDF (*((volatile unsigned int*)(0x42310E30UL))) +#define bM4_TMR63_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42310E54UL))) +#define bM4_TMR63_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42310E58UL))) +#define bM4_TMR63_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42310E5CUL))) +#define bM4_TMR63_STFLR_DIRF (*((volatile unsigned int*)(0x42310E7CUL))) +#define bM4_TMR63_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42310E80UL))) +#define bM4_TMR63_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42310E84UL))) +#define bM4_TMR63_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42310E90UL))) +#define bM4_TMR63_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42310E94UL))) +#define bM4_TMR63_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42310E98UL))) +#define bM4_TMR63_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42310E9CUL))) +#define bM4_TMR63_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42310EA0UL))) +#define bM4_TMR63_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42310EA4UL))) +#define bM4_TMR63_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42310EA8UL))) +#define bM4_TMR63_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42310EACUL))) +#define bM4_TMR63_HSTAR_STARTS (*((volatile unsigned int*)(0x42310EFCUL))) +#define bM4_TMR63_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42310F00UL))) +#define bM4_TMR63_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42310F04UL))) +#define bM4_TMR63_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42310F10UL))) +#define bM4_TMR63_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42310F14UL))) +#define bM4_TMR63_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42310F18UL))) +#define bM4_TMR63_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42310F1CUL))) +#define bM4_TMR63_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42310F20UL))) +#define bM4_TMR63_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42310F24UL))) +#define bM4_TMR63_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42310F28UL))) +#define bM4_TMR63_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42310F2CUL))) +#define bM4_TMR63_HSTPR_STOPS (*((volatile unsigned int*)(0x42310F7CUL))) +#define bM4_TMR63_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42310F80UL))) +#define bM4_TMR63_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42310F84UL))) +#define bM4_TMR63_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42310F90UL))) +#define bM4_TMR63_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42310F94UL))) +#define bM4_TMR63_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42310F98UL))) +#define bM4_TMR63_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42310F9CUL))) +#define bM4_TMR63_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42310FA0UL))) +#define bM4_TMR63_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42310FA4UL))) +#define bM4_TMR63_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42310FA8UL))) +#define bM4_TMR63_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42310FACUL))) +#define bM4_TMR63_HCLRR_CLEARS (*((volatile unsigned int*)(0x42310FFCUL))) +#define bM4_TMR63_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42311000UL))) +#define bM4_TMR63_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42311004UL))) +#define bM4_TMR63_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42311010UL))) +#define bM4_TMR63_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42311014UL))) +#define bM4_TMR63_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42311018UL))) +#define bM4_TMR63_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4231101CUL))) +#define bM4_TMR63_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42311020UL))) +#define bM4_TMR63_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42311024UL))) +#define bM4_TMR63_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42311028UL))) +#define bM4_TMR63_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4231102CUL))) +#define bM4_TMR63_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42311080UL))) +#define bM4_TMR63_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42311084UL))) +#define bM4_TMR63_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42311090UL))) +#define bM4_TMR63_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42311094UL))) +#define bM4_TMR63_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42311098UL))) +#define bM4_TMR63_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4231109CUL))) +#define bM4_TMR63_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423110A0UL))) +#define bM4_TMR63_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423110A4UL))) +#define bM4_TMR63_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423110A8UL))) +#define bM4_TMR63_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423110ACUL))) +#define bM4_TMR63_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42311100UL))) +#define bM4_TMR63_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42311104UL))) +#define bM4_TMR63_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42311108UL))) +#define bM4_TMR63_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4231110CUL))) +#define bM4_TMR63_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42311110UL))) +#define bM4_TMR63_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42311114UL))) +#define bM4_TMR63_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42311118UL))) +#define bM4_TMR63_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4231111CUL))) +#define bM4_TMR63_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42311120UL))) +#define bM4_TMR63_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42311124UL))) +#define bM4_TMR63_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42311128UL))) +#define bM4_TMR63_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4231112CUL))) +#define bM4_TMR63_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42311140UL))) +#define bM4_TMR63_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42311144UL))) +#define bM4_TMR63_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42311180UL))) +#define bM4_TMR63_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42311184UL))) +#define bM4_TMR63_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42311188UL))) +#define bM4_TMR63_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4231118CUL))) +#define bM4_TMR63_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42311190UL))) +#define bM4_TMR63_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42311194UL))) +#define bM4_TMR63_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42311198UL))) +#define bM4_TMR63_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4231119CUL))) +#define bM4_TMR63_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423111A0UL))) +#define bM4_TMR63_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423111A4UL))) +#define bM4_TMR63_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423111A8UL))) +#define bM4_TMR63_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423111ACUL))) +#define bM4_TMR63_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423111C0UL))) +#define bM4_TMR63_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423111C4UL))) +#define bM4_TMR6_CR_SSTAR_SSTA1 (*((volatile unsigned int*)(0x42307E80UL))) +#define bM4_TMR6_CR_SSTAR_SSTA2 (*((volatile unsigned int*)(0x42307E84UL))) +#define bM4_TMR6_CR_SSTAR_SSTA3 (*((volatile unsigned int*)(0x42307E88UL))) +#define bM4_TMR6_CR_SSTAR_RESV0 (*((volatile unsigned int*)(0x42307EC0UL))) +#define bM4_TMR6_CR_SSTAR_RESV (*((volatile unsigned int*)(0x42307EE0UL))) +#define bM4_TMR6_CR_SSTPR_SSTP1 (*((volatile unsigned int*)(0x42307F00UL))) +#define bM4_TMR6_CR_SSTPR_SSTP2 (*((volatile unsigned int*)(0x42307F04UL))) +#define bM4_TMR6_CR_SSTPR_SSTP3 (*((volatile unsigned int*)(0x42307F08UL))) +#define bM4_TMR6_CR_SCLRR_SCLE1 (*((volatile unsigned int*)(0x42307F80UL))) +#define bM4_TMR6_CR_SCLRR_SCLE2 (*((volatile unsigned int*)(0x42307F84UL))) +#define bM4_TMR6_CR_SCLRR_SCLE3 (*((volatile unsigned int*)(0x42307F88UL))) +#define bM4_TMRA1_CNTER_CNT0 (*((volatile unsigned int*)(0x422A0000UL))) +#define bM4_TMRA1_CNTER_CNT1 (*((volatile unsigned int*)(0x422A0004UL))) +#define bM4_TMRA1_CNTER_CNT2 (*((volatile unsigned int*)(0x422A0008UL))) +#define bM4_TMRA1_CNTER_CNT3 (*((volatile unsigned int*)(0x422A000CUL))) +#define bM4_TMRA1_CNTER_CNT4 (*((volatile unsigned int*)(0x422A0010UL))) +#define bM4_TMRA1_CNTER_CNT5 (*((volatile unsigned int*)(0x422A0014UL))) +#define bM4_TMRA1_CNTER_CNT6 (*((volatile unsigned int*)(0x422A0018UL))) +#define bM4_TMRA1_CNTER_CNT7 (*((volatile unsigned int*)(0x422A001CUL))) +#define bM4_TMRA1_CNTER_CNT8 (*((volatile unsigned int*)(0x422A0020UL))) +#define bM4_TMRA1_CNTER_CNT9 (*((volatile unsigned int*)(0x422A0024UL))) +#define bM4_TMRA1_CNTER_CNT10 (*((volatile unsigned int*)(0x422A0028UL))) +#define bM4_TMRA1_CNTER_CNT11 (*((volatile unsigned int*)(0x422A002CUL))) +#define bM4_TMRA1_CNTER_CNT12 (*((volatile unsigned int*)(0x422A0030UL))) +#define bM4_TMRA1_CNTER_CNT13 (*((volatile unsigned int*)(0x422A0034UL))) +#define bM4_TMRA1_CNTER_CNT14 (*((volatile unsigned int*)(0x422A0038UL))) +#define bM4_TMRA1_CNTER_CNT15 (*((volatile unsigned int*)(0x422A003CUL))) +#define bM4_TMRA1_PERAR_PER0 (*((volatile unsigned int*)(0x422A0080UL))) +#define bM4_TMRA1_PERAR_PER1 (*((volatile unsigned int*)(0x422A0084UL))) +#define bM4_TMRA1_PERAR_PER2 (*((volatile unsigned int*)(0x422A0088UL))) +#define bM4_TMRA1_PERAR_PER3 (*((volatile unsigned int*)(0x422A008CUL))) +#define bM4_TMRA1_PERAR_PER4 (*((volatile unsigned int*)(0x422A0090UL))) +#define bM4_TMRA1_PERAR_PER5 (*((volatile unsigned int*)(0x422A0094UL))) +#define bM4_TMRA1_PERAR_PER6 (*((volatile unsigned int*)(0x422A0098UL))) +#define bM4_TMRA1_PERAR_PER7 (*((volatile unsigned int*)(0x422A009CUL))) +#define bM4_TMRA1_PERAR_PER8 (*((volatile unsigned int*)(0x422A00A0UL))) +#define bM4_TMRA1_PERAR_PER9 (*((volatile unsigned int*)(0x422A00A4UL))) +#define bM4_TMRA1_PERAR_PER10 (*((volatile unsigned int*)(0x422A00A8UL))) +#define bM4_TMRA1_PERAR_PER11 (*((volatile unsigned int*)(0x422A00ACUL))) +#define bM4_TMRA1_PERAR_PER12 (*((volatile unsigned int*)(0x422A00B0UL))) +#define bM4_TMRA1_PERAR_PER13 (*((volatile unsigned int*)(0x422A00B4UL))) +#define bM4_TMRA1_PERAR_PER14 (*((volatile unsigned int*)(0x422A00B8UL))) +#define bM4_TMRA1_PERAR_PER15 (*((volatile unsigned int*)(0x422A00BCUL))) +#define bM4_TMRA1_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A0800UL))) +#define bM4_TMRA1_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A0804UL))) +#define bM4_TMRA1_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A0808UL))) +#define bM4_TMRA1_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A080CUL))) +#define bM4_TMRA1_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A0810UL))) +#define bM4_TMRA1_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A0814UL))) +#define bM4_TMRA1_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A0818UL))) +#define bM4_TMRA1_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A081CUL))) +#define bM4_TMRA1_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A0820UL))) +#define bM4_TMRA1_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A0824UL))) +#define bM4_TMRA1_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A0828UL))) +#define bM4_TMRA1_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A082CUL))) +#define bM4_TMRA1_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A0830UL))) +#define bM4_TMRA1_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A0834UL))) +#define bM4_TMRA1_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A0838UL))) +#define bM4_TMRA1_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A083CUL))) +#define bM4_TMRA1_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A0880UL))) +#define bM4_TMRA1_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A0884UL))) +#define bM4_TMRA1_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A0888UL))) +#define bM4_TMRA1_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A088CUL))) +#define bM4_TMRA1_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A0890UL))) +#define bM4_TMRA1_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A0894UL))) +#define bM4_TMRA1_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A0898UL))) +#define bM4_TMRA1_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A089CUL))) +#define bM4_TMRA1_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A08A0UL))) +#define bM4_TMRA1_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A08A4UL))) +#define bM4_TMRA1_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A08A8UL))) +#define bM4_TMRA1_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A08ACUL))) +#define bM4_TMRA1_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A08B0UL))) +#define bM4_TMRA1_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A08B4UL))) +#define bM4_TMRA1_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A08B8UL))) +#define bM4_TMRA1_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A08BCUL))) +#define bM4_TMRA1_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A0900UL))) +#define bM4_TMRA1_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A0904UL))) +#define bM4_TMRA1_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A0908UL))) +#define bM4_TMRA1_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A090CUL))) +#define bM4_TMRA1_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A0910UL))) +#define bM4_TMRA1_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A0914UL))) +#define bM4_TMRA1_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A0918UL))) +#define bM4_TMRA1_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A091CUL))) +#define bM4_TMRA1_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A0920UL))) +#define bM4_TMRA1_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A0924UL))) +#define bM4_TMRA1_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A0928UL))) +#define bM4_TMRA1_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A092CUL))) +#define bM4_TMRA1_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A0930UL))) +#define bM4_TMRA1_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A0934UL))) +#define bM4_TMRA1_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A0938UL))) +#define bM4_TMRA1_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A093CUL))) +#define bM4_TMRA1_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A0980UL))) +#define bM4_TMRA1_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A0984UL))) +#define bM4_TMRA1_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A0988UL))) +#define bM4_TMRA1_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A098CUL))) +#define bM4_TMRA1_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A0990UL))) +#define bM4_TMRA1_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A0994UL))) +#define bM4_TMRA1_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A0998UL))) +#define bM4_TMRA1_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A099CUL))) +#define bM4_TMRA1_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A09A0UL))) +#define bM4_TMRA1_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A09A4UL))) +#define bM4_TMRA1_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A09A8UL))) +#define bM4_TMRA1_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A09ACUL))) +#define bM4_TMRA1_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A09B0UL))) +#define bM4_TMRA1_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A09B4UL))) +#define bM4_TMRA1_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A09B8UL))) +#define bM4_TMRA1_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A09BCUL))) +#define bM4_TMRA1_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A0A00UL))) +#define bM4_TMRA1_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A0A04UL))) +#define bM4_TMRA1_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A0A08UL))) +#define bM4_TMRA1_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A0A0CUL))) +#define bM4_TMRA1_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A0A10UL))) +#define bM4_TMRA1_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A0A14UL))) +#define bM4_TMRA1_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A0A18UL))) +#define bM4_TMRA1_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A0A1CUL))) +#define bM4_TMRA1_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A0A20UL))) +#define bM4_TMRA1_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A0A24UL))) +#define bM4_TMRA1_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A0A28UL))) +#define bM4_TMRA1_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A0A2CUL))) +#define bM4_TMRA1_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A0A30UL))) +#define bM4_TMRA1_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A0A34UL))) +#define bM4_TMRA1_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A0A38UL))) +#define bM4_TMRA1_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A0A3CUL))) +#define bM4_TMRA1_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A0A80UL))) +#define bM4_TMRA1_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A0A84UL))) +#define bM4_TMRA1_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A0A88UL))) +#define bM4_TMRA1_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A0A8CUL))) +#define bM4_TMRA1_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A0A90UL))) +#define bM4_TMRA1_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A0A94UL))) +#define bM4_TMRA1_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A0A98UL))) +#define bM4_TMRA1_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A0A9CUL))) +#define bM4_TMRA1_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A0AA0UL))) +#define bM4_TMRA1_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A0AA4UL))) +#define bM4_TMRA1_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A0AA8UL))) +#define bM4_TMRA1_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A0AACUL))) +#define bM4_TMRA1_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A0AB0UL))) +#define bM4_TMRA1_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A0AB4UL))) +#define bM4_TMRA1_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A0AB8UL))) +#define bM4_TMRA1_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A0ABCUL))) +#define bM4_TMRA1_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A0B00UL))) +#define bM4_TMRA1_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A0B04UL))) +#define bM4_TMRA1_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A0B08UL))) +#define bM4_TMRA1_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A0B0CUL))) +#define bM4_TMRA1_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A0B10UL))) +#define bM4_TMRA1_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A0B14UL))) +#define bM4_TMRA1_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A0B18UL))) +#define bM4_TMRA1_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A0B1CUL))) +#define bM4_TMRA1_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A0B20UL))) +#define bM4_TMRA1_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A0B24UL))) +#define bM4_TMRA1_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A0B28UL))) +#define bM4_TMRA1_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A0B2CUL))) +#define bM4_TMRA1_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A0B30UL))) +#define bM4_TMRA1_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A0B34UL))) +#define bM4_TMRA1_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A0B38UL))) +#define bM4_TMRA1_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A0B3CUL))) +#define bM4_TMRA1_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A0B80UL))) +#define bM4_TMRA1_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A0B84UL))) +#define bM4_TMRA1_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A0B88UL))) +#define bM4_TMRA1_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A0B8CUL))) +#define bM4_TMRA1_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A0B90UL))) +#define bM4_TMRA1_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A0B94UL))) +#define bM4_TMRA1_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A0B98UL))) +#define bM4_TMRA1_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A0B9CUL))) +#define bM4_TMRA1_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A0BA0UL))) +#define bM4_TMRA1_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A0BA4UL))) +#define bM4_TMRA1_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A0BA8UL))) +#define bM4_TMRA1_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A0BACUL))) +#define bM4_TMRA1_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A0BB0UL))) +#define bM4_TMRA1_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A0BB4UL))) +#define bM4_TMRA1_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A0BB8UL))) +#define bM4_TMRA1_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A0BBCUL))) +#define bM4_TMRA1_BCSTR_START (*((volatile unsigned int*)(0x422A1000UL))) +#define bM4_TMRA1_BCSTR_DIR (*((volatile unsigned int*)(0x422A1004UL))) +#define bM4_TMRA1_BCSTR_MODE (*((volatile unsigned int*)(0x422A1008UL))) +#define bM4_TMRA1_BCSTR_SYNST (*((volatile unsigned int*)(0x422A100CUL))) +#define bM4_TMRA1_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A1010UL))) +#define bM4_TMRA1_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A1014UL))) +#define bM4_TMRA1_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A1018UL))) +#define bM4_TMRA1_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A101CUL))) +#define bM4_TMRA1_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A1030UL))) +#define bM4_TMRA1_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A1034UL))) +#define bM4_TMRA1_BCSTR_OVFF (*((volatile unsigned int*)(0x422A1038UL))) +#define bM4_TMRA1_BCSTR_UDFF (*((volatile unsigned int*)(0x422A103CUL))) +#define bM4_TMRA1_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A1080UL))) +#define bM4_TMRA1_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A1084UL))) +#define bM4_TMRA1_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A1088UL))) +#define bM4_TMRA1_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A1090UL))) +#define bM4_TMRA1_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A1094UL))) +#define bM4_TMRA1_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A1098UL))) +#define bM4_TMRA1_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A10A0UL))) +#define bM4_TMRA1_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A10A4UL))) +#define bM4_TMRA1_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A10A8UL))) +#define bM4_TMRA1_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A10B0UL))) +#define bM4_TMRA1_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A10B4UL))) +#define bM4_TMRA1_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A10B8UL))) +#define bM4_TMRA1_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A10BCUL))) +#define bM4_TMRA1_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A1100UL))) +#define bM4_TMRA1_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A1104UL))) +#define bM4_TMRA1_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A1108UL))) +#define bM4_TMRA1_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A110CUL))) +#define bM4_TMRA1_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A1110UL))) +#define bM4_TMRA1_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A1114UL))) +#define bM4_TMRA1_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A1118UL))) +#define bM4_TMRA1_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A111CUL))) +#define bM4_TMRA1_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A1120UL))) +#define bM4_TMRA1_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A1124UL))) +#define bM4_TMRA1_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A1128UL))) +#define bM4_TMRA1_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A112CUL))) +#define bM4_TMRA1_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A1130UL))) +#define bM4_TMRA1_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A1180UL))) +#define bM4_TMRA1_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A1184UL))) +#define bM4_TMRA1_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A1188UL))) +#define bM4_TMRA1_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A118CUL))) +#define bM4_TMRA1_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A1190UL))) +#define bM4_TMRA1_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A1194UL))) +#define bM4_TMRA1_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A1198UL))) +#define bM4_TMRA1_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A119CUL))) +#define bM4_TMRA1_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A11A0UL))) +#define bM4_TMRA1_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A11A4UL))) +#define bM4_TMRA1_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A11A8UL))) +#define bM4_TMRA1_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A11ACUL))) +#define bM4_TMRA1_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A11B0UL))) +#define bM4_TMRA1_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A1200UL))) +#define bM4_TMRA1_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A1204UL))) +#define bM4_TMRA1_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A1208UL))) +#define bM4_TMRA1_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A120CUL))) +#define bM4_TMRA1_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A1210UL))) +#define bM4_TMRA1_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A1214UL))) +#define bM4_TMRA1_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A1218UL))) +#define bM4_TMRA1_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A121CUL))) +#define bM4_TMRA1_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A1280UL))) +#define bM4_TMRA1_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A1284UL))) +#define bM4_TMRA1_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A1288UL))) +#define bM4_TMRA1_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A128CUL))) +#define bM4_TMRA1_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A1290UL))) +#define bM4_TMRA1_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A1294UL))) +#define bM4_TMRA1_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A1298UL))) +#define bM4_TMRA1_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A129CUL))) +#define bM4_TMRA1_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A1300UL))) +#define bM4_TMRA1_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A1304UL))) +#define bM4_TMRA1_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A1308UL))) +#define bM4_TMRA1_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A1320UL))) +#define bM4_TMRA1_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A1324UL))) +#define bM4_TMRA1_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A1328UL))) +#define bM4_TMRA1_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A1330UL))) +#define bM4_TMRA1_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A1334UL))) +#define bM4_TMRA1_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A1338UL))) +#define bM4_TMRA1_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A1380UL))) +#define bM4_TMRA1_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A1384UL))) +#define bM4_TMRA1_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A1388UL))) +#define bM4_TMRA1_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A138CUL))) +#define bM4_TMRA1_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A1390UL))) +#define bM4_TMRA1_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A1394UL))) +#define bM4_TMRA1_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A1398UL))) +#define bM4_TMRA1_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A139CUL))) +#define bM4_TMRA1_BCONR1_BEN (*((volatile unsigned int*)(0x422A1800UL))) +#define bM4_TMRA1_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A1804UL))) +#define bM4_TMRA1_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A1808UL))) +#define bM4_TMRA1_BCONR2_BEN (*((volatile unsigned int*)(0x422A1900UL))) +#define bM4_TMRA1_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A1904UL))) +#define bM4_TMRA1_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A1908UL))) +#define bM4_TMRA1_BCONR3_BEN (*((volatile unsigned int*)(0x422A1A00UL))) +#define bM4_TMRA1_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A1A04UL))) +#define bM4_TMRA1_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A1A08UL))) +#define bM4_TMRA1_BCONR4_BEN (*((volatile unsigned int*)(0x422A1B00UL))) +#define bM4_TMRA1_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A1B04UL))) +#define bM4_TMRA1_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A1B08UL))) +#define bM4_TMRA1_CCONR1_CAPMD (*((volatile unsigned int*)(0x422A2000UL))) +#define bM4_TMRA1_CCONR1_HICP0 (*((volatile unsigned int*)(0x422A2010UL))) +#define bM4_TMRA1_CCONR1_HICP1 (*((volatile unsigned int*)(0x422A2014UL))) +#define bM4_TMRA1_CCONR1_HICP2 (*((volatile unsigned int*)(0x422A2018UL))) +#define bM4_TMRA1_CCONR1_HICP3 (*((volatile unsigned int*)(0x422A2020UL))) +#define bM4_TMRA1_CCONR1_HICP4 (*((volatile unsigned int*)(0x422A2024UL))) +#define bM4_TMRA1_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422A2030UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422A2034UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422A2038UL))) +#define bM4_TMRA1_CCONR2_CAPMD (*((volatile unsigned int*)(0x422A2080UL))) +#define bM4_TMRA1_CCONR2_HICP0 (*((volatile unsigned int*)(0x422A2090UL))) +#define bM4_TMRA1_CCONR2_HICP1 (*((volatile unsigned int*)(0x422A2094UL))) +#define bM4_TMRA1_CCONR2_HICP2 (*((volatile unsigned int*)(0x422A2098UL))) +#define bM4_TMRA1_CCONR2_HICP3 (*((volatile unsigned int*)(0x422A20A0UL))) +#define bM4_TMRA1_CCONR2_HICP4 (*((volatile unsigned int*)(0x422A20A4UL))) +#define bM4_TMRA1_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422A20B0UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422A20B4UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422A20B8UL))) +#define bM4_TMRA1_CCONR3_CAPMD (*((volatile unsigned int*)(0x422A2100UL))) +#define bM4_TMRA1_CCONR3_HICP0 (*((volatile unsigned int*)(0x422A2110UL))) +#define bM4_TMRA1_CCONR3_HICP1 (*((volatile unsigned int*)(0x422A2114UL))) +#define bM4_TMRA1_CCONR3_HICP2 (*((volatile unsigned int*)(0x422A2118UL))) +#define bM4_TMRA1_CCONR3_HICP3 (*((volatile unsigned int*)(0x422A2120UL))) +#define bM4_TMRA1_CCONR3_HICP4 (*((volatile unsigned int*)(0x422A2124UL))) +#define bM4_TMRA1_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422A2130UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422A2134UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422A2138UL))) +#define bM4_TMRA1_CCONR4_CAPMD (*((volatile unsigned int*)(0x422A2180UL))) +#define bM4_TMRA1_CCONR4_HICP0 (*((volatile unsigned int*)(0x422A2190UL))) +#define bM4_TMRA1_CCONR4_HICP1 (*((volatile unsigned int*)(0x422A2194UL))) +#define bM4_TMRA1_CCONR4_HICP2 (*((volatile unsigned int*)(0x422A2198UL))) +#define bM4_TMRA1_CCONR4_HICP3 (*((volatile unsigned int*)(0x422A21A0UL))) +#define bM4_TMRA1_CCONR4_HICP4 (*((volatile unsigned int*)(0x422A21A4UL))) +#define bM4_TMRA1_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422A21B0UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422A21B4UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422A21B8UL))) +#define bM4_TMRA1_CCONR5_CAPMD (*((volatile unsigned int*)(0x422A2200UL))) +#define bM4_TMRA1_CCONR5_HICP0 (*((volatile unsigned int*)(0x422A2210UL))) +#define bM4_TMRA1_CCONR5_HICP1 (*((volatile unsigned int*)(0x422A2214UL))) +#define bM4_TMRA1_CCONR5_HICP2 (*((volatile unsigned int*)(0x422A2218UL))) +#define bM4_TMRA1_CCONR5_HICP3 (*((volatile unsigned int*)(0x422A2220UL))) +#define bM4_TMRA1_CCONR5_HICP4 (*((volatile unsigned int*)(0x422A2224UL))) +#define bM4_TMRA1_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422A2230UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422A2234UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422A2238UL))) +#define bM4_TMRA1_CCONR6_CAPMD (*((volatile unsigned int*)(0x422A2280UL))) +#define bM4_TMRA1_CCONR6_HICP0 (*((volatile unsigned int*)(0x422A2290UL))) +#define bM4_TMRA1_CCONR6_HICP1 (*((volatile unsigned int*)(0x422A2294UL))) +#define bM4_TMRA1_CCONR6_HICP2 (*((volatile unsigned int*)(0x422A2298UL))) +#define bM4_TMRA1_CCONR6_HICP3 (*((volatile unsigned int*)(0x422A22A0UL))) +#define bM4_TMRA1_CCONR6_HICP4 (*((volatile unsigned int*)(0x422A22A4UL))) +#define bM4_TMRA1_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422A22B0UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422A22B4UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422A22B8UL))) +#define bM4_TMRA1_CCONR7_CAPMD (*((volatile unsigned int*)(0x422A2300UL))) +#define bM4_TMRA1_CCONR7_HICP0 (*((volatile unsigned int*)(0x422A2310UL))) +#define bM4_TMRA1_CCONR7_HICP1 (*((volatile unsigned int*)(0x422A2314UL))) +#define bM4_TMRA1_CCONR7_HICP2 (*((volatile unsigned int*)(0x422A2318UL))) +#define bM4_TMRA1_CCONR7_HICP3 (*((volatile unsigned int*)(0x422A2320UL))) +#define bM4_TMRA1_CCONR7_HICP4 (*((volatile unsigned int*)(0x422A2324UL))) +#define bM4_TMRA1_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422A2330UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422A2334UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422A2338UL))) +#define bM4_TMRA1_CCONR8_CAPMD (*((volatile unsigned int*)(0x422A2380UL))) +#define bM4_TMRA1_CCONR8_HICP0 (*((volatile unsigned int*)(0x422A2390UL))) +#define bM4_TMRA1_CCONR8_HICP1 (*((volatile unsigned int*)(0x422A2394UL))) +#define bM4_TMRA1_CCONR8_HICP2 (*((volatile unsigned int*)(0x422A2398UL))) +#define bM4_TMRA1_CCONR8_HICP3 (*((volatile unsigned int*)(0x422A23A0UL))) +#define bM4_TMRA1_CCONR8_HICP4 (*((volatile unsigned int*)(0x422A23A4UL))) +#define bM4_TMRA1_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422A23B0UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422A23B4UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422A23B8UL))) +#define bM4_TMRA1_PCONR1_STAC0 (*((volatile unsigned int*)(0x422A2800UL))) +#define bM4_TMRA1_PCONR1_STAC1 (*((volatile unsigned int*)(0x422A2804UL))) +#define bM4_TMRA1_PCONR1_STPC0 (*((volatile unsigned int*)(0x422A2808UL))) +#define bM4_TMRA1_PCONR1_STPC1 (*((volatile unsigned int*)(0x422A280CUL))) +#define bM4_TMRA1_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422A2810UL))) +#define bM4_TMRA1_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422A2814UL))) +#define bM4_TMRA1_PCONR1_PERC0 (*((volatile unsigned int*)(0x422A2818UL))) +#define bM4_TMRA1_PCONR1_PERC1 (*((volatile unsigned int*)(0x422A281CUL))) +#define bM4_TMRA1_PCONR1_FORC0 (*((volatile unsigned int*)(0x422A2820UL))) +#define bM4_TMRA1_PCONR1_FORC1 (*((volatile unsigned int*)(0x422A2824UL))) +#define bM4_TMRA1_PCONR1_OUTEN (*((volatile unsigned int*)(0x422A2830UL))) +#define bM4_TMRA1_PCONR2_STAC0 (*((volatile unsigned int*)(0x422A2880UL))) +#define bM4_TMRA1_PCONR2_STAC1 (*((volatile unsigned int*)(0x422A2884UL))) +#define bM4_TMRA1_PCONR2_STPC0 (*((volatile unsigned int*)(0x422A2888UL))) +#define bM4_TMRA1_PCONR2_STPC1 (*((volatile unsigned int*)(0x422A288CUL))) +#define bM4_TMRA1_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422A2890UL))) +#define bM4_TMRA1_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422A2894UL))) +#define bM4_TMRA1_PCONR2_PERC0 (*((volatile unsigned int*)(0x422A2898UL))) +#define bM4_TMRA1_PCONR2_PERC1 (*((volatile unsigned int*)(0x422A289CUL))) +#define bM4_TMRA1_PCONR2_FORC0 (*((volatile unsigned int*)(0x422A28A0UL))) +#define bM4_TMRA1_PCONR2_FORC1 (*((volatile unsigned int*)(0x422A28A4UL))) +#define bM4_TMRA1_PCONR2_OUTEN (*((volatile unsigned int*)(0x422A28B0UL))) +#define bM4_TMRA1_PCONR3_STAC0 (*((volatile unsigned int*)(0x422A2900UL))) +#define bM4_TMRA1_PCONR3_STAC1 (*((volatile unsigned int*)(0x422A2904UL))) +#define bM4_TMRA1_PCONR3_STPC0 (*((volatile unsigned int*)(0x422A2908UL))) +#define bM4_TMRA1_PCONR3_STPC1 (*((volatile unsigned int*)(0x422A290CUL))) +#define bM4_TMRA1_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422A2910UL))) +#define bM4_TMRA1_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422A2914UL))) +#define bM4_TMRA1_PCONR3_PERC0 (*((volatile unsigned int*)(0x422A2918UL))) +#define bM4_TMRA1_PCONR3_PERC1 (*((volatile unsigned int*)(0x422A291CUL))) +#define bM4_TMRA1_PCONR3_FORC0 (*((volatile unsigned int*)(0x422A2920UL))) +#define bM4_TMRA1_PCONR3_FORC1 (*((volatile unsigned int*)(0x422A2924UL))) +#define bM4_TMRA1_PCONR3_OUTEN (*((volatile unsigned int*)(0x422A2930UL))) +#define bM4_TMRA1_PCONR4_STAC0 (*((volatile unsigned int*)(0x422A2980UL))) +#define bM4_TMRA1_PCONR4_STAC1 (*((volatile unsigned int*)(0x422A2984UL))) +#define bM4_TMRA1_PCONR4_STPC0 (*((volatile unsigned int*)(0x422A2988UL))) +#define bM4_TMRA1_PCONR4_STPC1 (*((volatile unsigned int*)(0x422A298CUL))) +#define bM4_TMRA1_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422A2990UL))) +#define bM4_TMRA1_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422A2994UL))) +#define bM4_TMRA1_PCONR4_PERC0 (*((volatile unsigned int*)(0x422A2998UL))) +#define bM4_TMRA1_PCONR4_PERC1 (*((volatile unsigned int*)(0x422A299CUL))) +#define bM4_TMRA1_PCONR4_FORC0 (*((volatile unsigned int*)(0x422A29A0UL))) +#define bM4_TMRA1_PCONR4_FORC1 (*((volatile unsigned int*)(0x422A29A4UL))) +#define bM4_TMRA1_PCONR4_OUTEN (*((volatile unsigned int*)(0x422A29B0UL))) +#define bM4_TMRA1_PCONR5_STAC0 (*((volatile unsigned int*)(0x422A2A00UL))) +#define bM4_TMRA1_PCONR5_STAC1 (*((volatile unsigned int*)(0x422A2A04UL))) +#define bM4_TMRA1_PCONR5_STPC0 (*((volatile unsigned int*)(0x422A2A08UL))) +#define bM4_TMRA1_PCONR5_STPC1 (*((volatile unsigned int*)(0x422A2A0CUL))) +#define bM4_TMRA1_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422A2A10UL))) +#define bM4_TMRA1_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422A2A14UL))) +#define bM4_TMRA1_PCONR5_PERC0 (*((volatile unsigned int*)(0x422A2A18UL))) +#define bM4_TMRA1_PCONR5_PERC1 (*((volatile unsigned int*)(0x422A2A1CUL))) +#define bM4_TMRA1_PCONR5_FORC0 (*((volatile unsigned int*)(0x422A2A20UL))) +#define bM4_TMRA1_PCONR5_FORC1 (*((volatile unsigned int*)(0x422A2A24UL))) +#define bM4_TMRA1_PCONR5_OUTEN (*((volatile unsigned int*)(0x422A2A30UL))) +#define bM4_TMRA1_PCONR6_STAC0 (*((volatile unsigned int*)(0x422A2A80UL))) +#define bM4_TMRA1_PCONR6_STAC1 (*((volatile unsigned int*)(0x422A2A84UL))) +#define bM4_TMRA1_PCONR6_STPC0 (*((volatile unsigned int*)(0x422A2A88UL))) +#define bM4_TMRA1_PCONR6_STPC1 (*((volatile unsigned int*)(0x422A2A8CUL))) +#define bM4_TMRA1_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422A2A90UL))) +#define bM4_TMRA1_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422A2A94UL))) +#define bM4_TMRA1_PCONR6_PERC0 (*((volatile unsigned int*)(0x422A2A98UL))) +#define bM4_TMRA1_PCONR6_PERC1 (*((volatile unsigned int*)(0x422A2A9CUL))) +#define bM4_TMRA1_PCONR6_FORC0 (*((volatile unsigned int*)(0x422A2AA0UL))) +#define bM4_TMRA1_PCONR6_FORC1 (*((volatile unsigned int*)(0x422A2AA4UL))) +#define bM4_TMRA1_PCONR6_OUTEN (*((volatile unsigned int*)(0x422A2AB0UL))) +#define bM4_TMRA1_PCONR7_STAC0 (*((volatile unsigned int*)(0x422A2B00UL))) +#define bM4_TMRA1_PCONR7_STAC1 (*((volatile unsigned int*)(0x422A2B04UL))) +#define bM4_TMRA1_PCONR7_STPC0 (*((volatile unsigned int*)(0x422A2B08UL))) +#define bM4_TMRA1_PCONR7_STPC1 (*((volatile unsigned int*)(0x422A2B0CUL))) +#define bM4_TMRA1_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422A2B10UL))) +#define bM4_TMRA1_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422A2B14UL))) +#define bM4_TMRA1_PCONR7_PERC0 (*((volatile unsigned int*)(0x422A2B18UL))) +#define bM4_TMRA1_PCONR7_PERC1 (*((volatile unsigned int*)(0x422A2B1CUL))) +#define bM4_TMRA1_PCONR7_FORC0 (*((volatile unsigned int*)(0x422A2B20UL))) +#define bM4_TMRA1_PCONR7_FORC1 (*((volatile unsigned int*)(0x422A2B24UL))) +#define bM4_TMRA1_PCONR7_OUTEN (*((volatile unsigned int*)(0x422A2B30UL))) +#define bM4_TMRA1_PCONR8_STAC0 (*((volatile unsigned int*)(0x422A2B80UL))) +#define bM4_TMRA1_PCONR8_STAC1 (*((volatile unsigned int*)(0x422A2B84UL))) +#define bM4_TMRA1_PCONR8_STPC0 (*((volatile unsigned int*)(0x422A2B88UL))) +#define bM4_TMRA1_PCONR8_STPC1 (*((volatile unsigned int*)(0x422A2B8CUL))) +#define bM4_TMRA1_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422A2B90UL))) +#define bM4_TMRA1_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422A2B94UL))) +#define bM4_TMRA1_PCONR8_PERC0 (*((volatile unsigned int*)(0x422A2B98UL))) +#define bM4_TMRA1_PCONR8_PERC1 (*((volatile unsigned int*)(0x422A2B9CUL))) +#define bM4_TMRA1_PCONR8_FORC0 (*((volatile unsigned int*)(0x422A2BA0UL))) +#define bM4_TMRA1_PCONR8_FORC1 (*((volatile unsigned int*)(0x422A2BA4UL))) +#define bM4_TMRA1_PCONR8_OUTEN (*((volatile unsigned int*)(0x422A2BB0UL))) +#define bM4_TMRA2_CNTER_CNT0 (*((volatile unsigned int*)(0x422A8000UL))) +#define bM4_TMRA2_CNTER_CNT1 (*((volatile unsigned int*)(0x422A8004UL))) +#define bM4_TMRA2_CNTER_CNT2 (*((volatile unsigned int*)(0x422A8008UL))) +#define bM4_TMRA2_CNTER_CNT3 (*((volatile unsigned int*)(0x422A800CUL))) +#define bM4_TMRA2_CNTER_CNT4 (*((volatile unsigned int*)(0x422A8010UL))) +#define bM4_TMRA2_CNTER_CNT5 (*((volatile unsigned int*)(0x422A8014UL))) +#define bM4_TMRA2_CNTER_CNT6 (*((volatile unsigned int*)(0x422A8018UL))) +#define bM4_TMRA2_CNTER_CNT7 (*((volatile unsigned int*)(0x422A801CUL))) +#define bM4_TMRA2_CNTER_CNT8 (*((volatile unsigned int*)(0x422A8020UL))) +#define bM4_TMRA2_CNTER_CNT9 (*((volatile unsigned int*)(0x422A8024UL))) +#define bM4_TMRA2_CNTER_CNT10 (*((volatile unsigned int*)(0x422A8028UL))) +#define bM4_TMRA2_CNTER_CNT11 (*((volatile unsigned int*)(0x422A802CUL))) +#define bM4_TMRA2_CNTER_CNT12 (*((volatile unsigned int*)(0x422A8030UL))) +#define bM4_TMRA2_CNTER_CNT13 (*((volatile unsigned int*)(0x422A8034UL))) +#define bM4_TMRA2_CNTER_CNT14 (*((volatile unsigned int*)(0x422A8038UL))) +#define bM4_TMRA2_CNTER_CNT15 (*((volatile unsigned int*)(0x422A803CUL))) +#define bM4_TMRA2_PERAR_PER0 (*((volatile unsigned int*)(0x422A8080UL))) +#define bM4_TMRA2_PERAR_PER1 (*((volatile unsigned int*)(0x422A8084UL))) +#define bM4_TMRA2_PERAR_PER2 (*((volatile unsigned int*)(0x422A8088UL))) +#define bM4_TMRA2_PERAR_PER3 (*((volatile unsigned int*)(0x422A808CUL))) +#define bM4_TMRA2_PERAR_PER4 (*((volatile unsigned int*)(0x422A8090UL))) +#define bM4_TMRA2_PERAR_PER5 (*((volatile unsigned int*)(0x422A8094UL))) +#define bM4_TMRA2_PERAR_PER6 (*((volatile unsigned int*)(0x422A8098UL))) +#define bM4_TMRA2_PERAR_PER7 (*((volatile unsigned int*)(0x422A809CUL))) +#define bM4_TMRA2_PERAR_PER8 (*((volatile unsigned int*)(0x422A80A0UL))) +#define bM4_TMRA2_PERAR_PER9 (*((volatile unsigned int*)(0x422A80A4UL))) +#define bM4_TMRA2_PERAR_PER10 (*((volatile unsigned int*)(0x422A80A8UL))) +#define bM4_TMRA2_PERAR_PER11 (*((volatile unsigned int*)(0x422A80ACUL))) +#define bM4_TMRA2_PERAR_PER12 (*((volatile unsigned int*)(0x422A80B0UL))) +#define bM4_TMRA2_PERAR_PER13 (*((volatile unsigned int*)(0x422A80B4UL))) +#define bM4_TMRA2_PERAR_PER14 (*((volatile unsigned int*)(0x422A80B8UL))) +#define bM4_TMRA2_PERAR_PER15 (*((volatile unsigned int*)(0x422A80BCUL))) +#define bM4_TMRA2_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A8800UL))) +#define bM4_TMRA2_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A8804UL))) +#define bM4_TMRA2_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A8808UL))) +#define bM4_TMRA2_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A880CUL))) +#define bM4_TMRA2_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A8810UL))) +#define bM4_TMRA2_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A8814UL))) +#define bM4_TMRA2_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A8818UL))) +#define bM4_TMRA2_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A881CUL))) +#define bM4_TMRA2_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A8820UL))) +#define bM4_TMRA2_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A8824UL))) +#define bM4_TMRA2_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A8828UL))) +#define bM4_TMRA2_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A882CUL))) +#define bM4_TMRA2_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A8830UL))) +#define bM4_TMRA2_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A8834UL))) +#define bM4_TMRA2_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A8838UL))) +#define bM4_TMRA2_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A883CUL))) +#define bM4_TMRA2_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A8880UL))) +#define bM4_TMRA2_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A8884UL))) +#define bM4_TMRA2_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A8888UL))) +#define bM4_TMRA2_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A888CUL))) +#define bM4_TMRA2_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A8890UL))) +#define bM4_TMRA2_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A8894UL))) +#define bM4_TMRA2_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A8898UL))) +#define bM4_TMRA2_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A889CUL))) +#define bM4_TMRA2_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A88A0UL))) +#define bM4_TMRA2_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A88A4UL))) +#define bM4_TMRA2_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A88A8UL))) +#define bM4_TMRA2_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A88ACUL))) +#define bM4_TMRA2_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A88B0UL))) +#define bM4_TMRA2_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A88B4UL))) +#define bM4_TMRA2_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A88B8UL))) +#define bM4_TMRA2_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A88BCUL))) +#define bM4_TMRA2_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A8900UL))) +#define bM4_TMRA2_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A8904UL))) +#define bM4_TMRA2_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A8908UL))) +#define bM4_TMRA2_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A890CUL))) +#define bM4_TMRA2_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A8910UL))) +#define bM4_TMRA2_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A8914UL))) +#define bM4_TMRA2_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A8918UL))) +#define bM4_TMRA2_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A891CUL))) +#define bM4_TMRA2_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A8920UL))) +#define bM4_TMRA2_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A8924UL))) +#define bM4_TMRA2_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A8928UL))) +#define bM4_TMRA2_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A892CUL))) +#define bM4_TMRA2_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A8930UL))) +#define bM4_TMRA2_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A8934UL))) +#define bM4_TMRA2_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A8938UL))) +#define bM4_TMRA2_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A893CUL))) +#define bM4_TMRA2_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A8980UL))) +#define bM4_TMRA2_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A8984UL))) +#define bM4_TMRA2_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A8988UL))) +#define bM4_TMRA2_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A898CUL))) +#define bM4_TMRA2_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A8990UL))) +#define bM4_TMRA2_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A8994UL))) +#define bM4_TMRA2_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A8998UL))) +#define bM4_TMRA2_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A899CUL))) +#define bM4_TMRA2_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A89A0UL))) +#define bM4_TMRA2_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A89A4UL))) +#define bM4_TMRA2_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A89A8UL))) +#define bM4_TMRA2_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A89ACUL))) +#define bM4_TMRA2_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A89B0UL))) +#define bM4_TMRA2_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A89B4UL))) +#define bM4_TMRA2_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A89B8UL))) +#define bM4_TMRA2_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A89BCUL))) +#define bM4_TMRA2_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A8A00UL))) +#define bM4_TMRA2_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A8A04UL))) +#define bM4_TMRA2_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A8A08UL))) +#define bM4_TMRA2_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A8A0CUL))) +#define bM4_TMRA2_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A8A10UL))) +#define bM4_TMRA2_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A8A14UL))) +#define bM4_TMRA2_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A8A18UL))) +#define bM4_TMRA2_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A8A1CUL))) +#define bM4_TMRA2_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A8A20UL))) +#define bM4_TMRA2_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A8A24UL))) +#define bM4_TMRA2_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A8A28UL))) +#define bM4_TMRA2_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A8A2CUL))) +#define bM4_TMRA2_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A8A30UL))) +#define bM4_TMRA2_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A8A34UL))) +#define bM4_TMRA2_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A8A38UL))) +#define bM4_TMRA2_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A8A3CUL))) +#define bM4_TMRA2_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A8A80UL))) +#define bM4_TMRA2_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A8A84UL))) +#define bM4_TMRA2_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A8A88UL))) +#define bM4_TMRA2_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A8A8CUL))) +#define bM4_TMRA2_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A8A90UL))) +#define bM4_TMRA2_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A8A94UL))) +#define bM4_TMRA2_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A8A98UL))) +#define bM4_TMRA2_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A8A9CUL))) +#define bM4_TMRA2_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A8AA0UL))) +#define bM4_TMRA2_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A8AA4UL))) +#define bM4_TMRA2_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A8AA8UL))) +#define bM4_TMRA2_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A8AACUL))) +#define bM4_TMRA2_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A8AB0UL))) +#define bM4_TMRA2_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A8AB4UL))) +#define bM4_TMRA2_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A8AB8UL))) +#define bM4_TMRA2_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A8ABCUL))) +#define bM4_TMRA2_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A8B00UL))) +#define bM4_TMRA2_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A8B04UL))) +#define bM4_TMRA2_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A8B08UL))) +#define bM4_TMRA2_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A8B0CUL))) +#define bM4_TMRA2_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A8B10UL))) +#define bM4_TMRA2_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A8B14UL))) +#define bM4_TMRA2_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A8B18UL))) +#define bM4_TMRA2_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A8B1CUL))) +#define bM4_TMRA2_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A8B20UL))) +#define bM4_TMRA2_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A8B24UL))) +#define bM4_TMRA2_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A8B28UL))) +#define bM4_TMRA2_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A8B2CUL))) +#define bM4_TMRA2_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A8B30UL))) +#define bM4_TMRA2_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A8B34UL))) +#define bM4_TMRA2_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A8B38UL))) +#define bM4_TMRA2_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A8B3CUL))) +#define bM4_TMRA2_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A8B80UL))) +#define bM4_TMRA2_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A8B84UL))) +#define bM4_TMRA2_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A8B88UL))) +#define bM4_TMRA2_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A8B8CUL))) +#define bM4_TMRA2_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A8B90UL))) +#define bM4_TMRA2_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A8B94UL))) +#define bM4_TMRA2_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A8B98UL))) +#define bM4_TMRA2_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A8B9CUL))) +#define bM4_TMRA2_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A8BA0UL))) +#define bM4_TMRA2_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A8BA4UL))) +#define bM4_TMRA2_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A8BA8UL))) +#define bM4_TMRA2_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A8BACUL))) +#define bM4_TMRA2_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A8BB0UL))) +#define bM4_TMRA2_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A8BB4UL))) +#define bM4_TMRA2_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A8BB8UL))) +#define bM4_TMRA2_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A8BBCUL))) +#define bM4_TMRA2_BCSTR_START (*((volatile unsigned int*)(0x422A9000UL))) +#define bM4_TMRA2_BCSTR_DIR (*((volatile unsigned int*)(0x422A9004UL))) +#define bM4_TMRA2_BCSTR_MODE (*((volatile unsigned int*)(0x422A9008UL))) +#define bM4_TMRA2_BCSTR_SYNST (*((volatile unsigned int*)(0x422A900CUL))) +#define bM4_TMRA2_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A9010UL))) +#define bM4_TMRA2_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A9014UL))) +#define bM4_TMRA2_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A9018UL))) +#define bM4_TMRA2_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A901CUL))) +#define bM4_TMRA2_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A9030UL))) +#define bM4_TMRA2_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A9034UL))) +#define bM4_TMRA2_BCSTR_OVFF (*((volatile unsigned int*)(0x422A9038UL))) +#define bM4_TMRA2_BCSTR_UDFF (*((volatile unsigned int*)(0x422A903CUL))) +#define bM4_TMRA2_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A9080UL))) +#define bM4_TMRA2_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A9084UL))) +#define bM4_TMRA2_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A9088UL))) +#define bM4_TMRA2_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A9090UL))) +#define bM4_TMRA2_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A9094UL))) +#define bM4_TMRA2_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A9098UL))) +#define bM4_TMRA2_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A90A0UL))) +#define bM4_TMRA2_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A90A4UL))) +#define bM4_TMRA2_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A90A8UL))) +#define bM4_TMRA2_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A90B0UL))) +#define bM4_TMRA2_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A90B4UL))) +#define bM4_TMRA2_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A90B8UL))) +#define bM4_TMRA2_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A90BCUL))) +#define bM4_TMRA2_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A9100UL))) +#define bM4_TMRA2_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A9104UL))) +#define bM4_TMRA2_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A9108UL))) +#define bM4_TMRA2_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A910CUL))) +#define bM4_TMRA2_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A9110UL))) +#define bM4_TMRA2_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A9114UL))) +#define bM4_TMRA2_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A9118UL))) +#define bM4_TMRA2_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A911CUL))) +#define bM4_TMRA2_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A9120UL))) +#define bM4_TMRA2_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A9124UL))) +#define bM4_TMRA2_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A9128UL))) +#define bM4_TMRA2_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A912CUL))) +#define bM4_TMRA2_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A9130UL))) +#define bM4_TMRA2_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A9180UL))) +#define bM4_TMRA2_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A9184UL))) +#define bM4_TMRA2_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A9188UL))) +#define bM4_TMRA2_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A918CUL))) +#define bM4_TMRA2_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A9190UL))) +#define bM4_TMRA2_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A9194UL))) +#define bM4_TMRA2_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A9198UL))) +#define bM4_TMRA2_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A919CUL))) +#define bM4_TMRA2_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A91A0UL))) +#define bM4_TMRA2_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A91A4UL))) +#define bM4_TMRA2_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A91A8UL))) +#define bM4_TMRA2_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A91ACUL))) +#define bM4_TMRA2_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A91B0UL))) +#define bM4_TMRA2_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A9200UL))) +#define bM4_TMRA2_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A9204UL))) +#define bM4_TMRA2_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A9208UL))) +#define bM4_TMRA2_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A920CUL))) +#define bM4_TMRA2_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A9210UL))) +#define bM4_TMRA2_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A9214UL))) +#define bM4_TMRA2_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A9218UL))) +#define bM4_TMRA2_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A921CUL))) +#define bM4_TMRA2_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A9280UL))) +#define bM4_TMRA2_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A9284UL))) +#define bM4_TMRA2_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A9288UL))) +#define bM4_TMRA2_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A928CUL))) +#define bM4_TMRA2_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A9290UL))) +#define bM4_TMRA2_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A9294UL))) +#define bM4_TMRA2_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A9298UL))) +#define bM4_TMRA2_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A929CUL))) +#define bM4_TMRA2_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A9300UL))) +#define bM4_TMRA2_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A9304UL))) +#define bM4_TMRA2_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A9308UL))) +#define bM4_TMRA2_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A9320UL))) +#define bM4_TMRA2_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A9324UL))) +#define bM4_TMRA2_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A9328UL))) +#define bM4_TMRA2_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A9330UL))) +#define bM4_TMRA2_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A9334UL))) +#define bM4_TMRA2_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A9338UL))) +#define bM4_TMRA2_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A9380UL))) +#define bM4_TMRA2_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A9384UL))) +#define bM4_TMRA2_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A9388UL))) +#define bM4_TMRA2_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A938CUL))) +#define bM4_TMRA2_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A9390UL))) +#define bM4_TMRA2_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A9394UL))) +#define bM4_TMRA2_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A9398UL))) +#define bM4_TMRA2_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A939CUL))) +#define bM4_TMRA2_BCONR1_BEN (*((volatile unsigned int*)(0x422A9800UL))) +#define bM4_TMRA2_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A9804UL))) +#define bM4_TMRA2_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A9808UL))) +#define bM4_TMRA2_BCONR2_BEN (*((volatile unsigned int*)(0x422A9900UL))) +#define bM4_TMRA2_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A9904UL))) +#define bM4_TMRA2_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A9908UL))) +#define bM4_TMRA2_BCONR3_BEN (*((volatile unsigned int*)(0x422A9A00UL))) +#define bM4_TMRA2_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A9A04UL))) +#define bM4_TMRA2_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A9A08UL))) +#define bM4_TMRA2_BCONR4_BEN (*((volatile unsigned int*)(0x422A9B00UL))) +#define bM4_TMRA2_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A9B04UL))) +#define bM4_TMRA2_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A9B08UL))) +#define bM4_TMRA2_CCONR1_CAPMD (*((volatile unsigned int*)(0x422AA000UL))) +#define bM4_TMRA2_CCONR1_HICP0 (*((volatile unsigned int*)(0x422AA010UL))) +#define bM4_TMRA2_CCONR1_HICP1 (*((volatile unsigned int*)(0x422AA014UL))) +#define bM4_TMRA2_CCONR1_HICP2 (*((volatile unsigned int*)(0x422AA018UL))) +#define bM4_TMRA2_CCONR1_HICP3 (*((volatile unsigned int*)(0x422AA020UL))) +#define bM4_TMRA2_CCONR1_HICP4 (*((volatile unsigned int*)(0x422AA024UL))) +#define bM4_TMRA2_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422AA030UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422AA034UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422AA038UL))) +#define bM4_TMRA2_CCONR2_CAPMD (*((volatile unsigned int*)(0x422AA080UL))) +#define bM4_TMRA2_CCONR2_HICP0 (*((volatile unsigned int*)(0x422AA090UL))) +#define bM4_TMRA2_CCONR2_HICP1 (*((volatile unsigned int*)(0x422AA094UL))) +#define bM4_TMRA2_CCONR2_HICP2 (*((volatile unsigned int*)(0x422AA098UL))) +#define bM4_TMRA2_CCONR2_HICP3 (*((volatile unsigned int*)(0x422AA0A0UL))) +#define bM4_TMRA2_CCONR2_HICP4 (*((volatile unsigned int*)(0x422AA0A4UL))) +#define bM4_TMRA2_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422AA0B0UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422AA0B4UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422AA0B8UL))) +#define bM4_TMRA2_CCONR3_CAPMD (*((volatile unsigned int*)(0x422AA100UL))) +#define bM4_TMRA2_CCONR3_HICP0 (*((volatile unsigned int*)(0x422AA110UL))) +#define bM4_TMRA2_CCONR3_HICP1 (*((volatile unsigned int*)(0x422AA114UL))) +#define bM4_TMRA2_CCONR3_HICP2 (*((volatile unsigned int*)(0x422AA118UL))) +#define bM4_TMRA2_CCONR3_HICP3 (*((volatile unsigned int*)(0x422AA120UL))) +#define bM4_TMRA2_CCONR3_HICP4 (*((volatile unsigned int*)(0x422AA124UL))) +#define bM4_TMRA2_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422AA130UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422AA134UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422AA138UL))) +#define bM4_TMRA2_CCONR4_CAPMD (*((volatile unsigned int*)(0x422AA180UL))) +#define bM4_TMRA2_CCONR4_HICP0 (*((volatile unsigned int*)(0x422AA190UL))) +#define bM4_TMRA2_CCONR4_HICP1 (*((volatile unsigned int*)(0x422AA194UL))) +#define bM4_TMRA2_CCONR4_HICP2 (*((volatile unsigned int*)(0x422AA198UL))) +#define bM4_TMRA2_CCONR4_HICP3 (*((volatile unsigned int*)(0x422AA1A0UL))) +#define bM4_TMRA2_CCONR4_HICP4 (*((volatile unsigned int*)(0x422AA1A4UL))) +#define bM4_TMRA2_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422AA1B0UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422AA1B4UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422AA1B8UL))) +#define bM4_TMRA2_CCONR5_CAPMD (*((volatile unsigned int*)(0x422AA200UL))) +#define bM4_TMRA2_CCONR5_HICP0 (*((volatile unsigned int*)(0x422AA210UL))) +#define bM4_TMRA2_CCONR5_HICP1 (*((volatile unsigned int*)(0x422AA214UL))) +#define bM4_TMRA2_CCONR5_HICP2 (*((volatile unsigned int*)(0x422AA218UL))) +#define bM4_TMRA2_CCONR5_HICP3 (*((volatile unsigned int*)(0x422AA220UL))) +#define bM4_TMRA2_CCONR5_HICP4 (*((volatile unsigned int*)(0x422AA224UL))) +#define bM4_TMRA2_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422AA230UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422AA234UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422AA238UL))) +#define bM4_TMRA2_CCONR6_CAPMD (*((volatile unsigned int*)(0x422AA280UL))) +#define bM4_TMRA2_CCONR6_HICP0 (*((volatile unsigned int*)(0x422AA290UL))) +#define bM4_TMRA2_CCONR6_HICP1 (*((volatile unsigned int*)(0x422AA294UL))) +#define bM4_TMRA2_CCONR6_HICP2 (*((volatile unsigned int*)(0x422AA298UL))) +#define bM4_TMRA2_CCONR6_HICP3 (*((volatile unsigned int*)(0x422AA2A0UL))) +#define bM4_TMRA2_CCONR6_HICP4 (*((volatile unsigned int*)(0x422AA2A4UL))) +#define bM4_TMRA2_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422AA2B0UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422AA2B4UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422AA2B8UL))) +#define bM4_TMRA2_CCONR7_CAPMD (*((volatile unsigned int*)(0x422AA300UL))) +#define bM4_TMRA2_CCONR7_HICP0 (*((volatile unsigned int*)(0x422AA310UL))) +#define bM4_TMRA2_CCONR7_HICP1 (*((volatile unsigned int*)(0x422AA314UL))) +#define bM4_TMRA2_CCONR7_HICP2 (*((volatile unsigned int*)(0x422AA318UL))) +#define bM4_TMRA2_CCONR7_HICP3 (*((volatile unsigned int*)(0x422AA320UL))) +#define bM4_TMRA2_CCONR7_HICP4 (*((volatile unsigned int*)(0x422AA324UL))) +#define bM4_TMRA2_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422AA330UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422AA334UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422AA338UL))) +#define bM4_TMRA2_CCONR8_CAPMD (*((volatile unsigned int*)(0x422AA380UL))) +#define bM4_TMRA2_CCONR8_HICP0 (*((volatile unsigned int*)(0x422AA390UL))) +#define bM4_TMRA2_CCONR8_HICP1 (*((volatile unsigned int*)(0x422AA394UL))) +#define bM4_TMRA2_CCONR8_HICP2 (*((volatile unsigned int*)(0x422AA398UL))) +#define bM4_TMRA2_CCONR8_HICP3 (*((volatile unsigned int*)(0x422AA3A0UL))) +#define bM4_TMRA2_CCONR8_HICP4 (*((volatile unsigned int*)(0x422AA3A4UL))) +#define bM4_TMRA2_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422AA3B0UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422AA3B4UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422AA3B8UL))) +#define bM4_TMRA2_PCONR1_STAC0 (*((volatile unsigned int*)(0x422AA800UL))) +#define bM4_TMRA2_PCONR1_STAC1 (*((volatile unsigned int*)(0x422AA804UL))) +#define bM4_TMRA2_PCONR1_STPC0 (*((volatile unsigned int*)(0x422AA808UL))) +#define bM4_TMRA2_PCONR1_STPC1 (*((volatile unsigned int*)(0x422AA80CUL))) +#define bM4_TMRA2_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422AA810UL))) +#define bM4_TMRA2_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422AA814UL))) +#define bM4_TMRA2_PCONR1_PERC0 (*((volatile unsigned int*)(0x422AA818UL))) +#define bM4_TMRA2_PCONR1_PERC1 (*((volatile unsigned int*)(0x422AA81CUL))) +#define bM4_TMRA2_PCONR1_FORC0 (*((volatile unsigned int*)(0x422AA820UL))) +#define bM4_TMRA2_PCONR1_FORC1 (*((volatile unsigned int*)(0x422AA824UL))) +#define bM4_TMRA2_PCONR1_OUTEN (*((volatile unsigned int*)(0x422AA830UL))) +#define bM4_TMRA2_PCONR2_STAC0 (*((volatile unsigned int*)(0x422AA880UL))) +#define bM4_TMRA2_PCONR2_STAC1 (*((volatile unsigned int*)(0x422AA884UL))) +#define bM4_TMRA2_PCONR2_STPC0 (*((volatile unsigned int*)(0x422AA888UL))) +#define bM4_TMRA2_PCONR2_STPC1 (*((volatile unsigned int*)(0x422AA88CUL))) +#define bM4_TMRA2_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422AA890UL))) +#define bM4_TMRA2_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422AA894UL))) +#define bM4_TMRA2_PCONR2_PERC0 (*((volatile unsigned int*)(0x422AA898UL))) +#define bM4_TMRA2_PCONR2_PERC1 (*((volatile unsigned int*)(0x422AA89CUL))) +#define bM4_TMRA2_PCONR2_FORC0 (*((volatile unsigned int*)(0x422AA8A0UL))) +#define bM4_TMRA2_PCONR2_FORC1 (*((volatile unsigned int*)(0x422AA8A4UL))) +#define bM4_TMRA2_PCONR2_OUTEN (*((volatile unsigned int*)(0x422AA8B0UL))) +#define bM4_TMRA2_PCONR3_STAC0 (*((volatile unsigned int*)(0x422AA900UL))) +#define bM4_TMRA2_PCONR3_STAC1 (*((volatile unsigned int*)(0x422AA904UL))) +#define bM4_TMRA2_PCONR3_STPC0 (*((volatile unsigned int*)(0x422AA908UL))) +#define bM4_TMRA2_PCONR3_STPC1 (*((volatile unsigned int*)(0x422AA90CUL))) +#define bM4_TMRA2_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422AA910UL))) +#define bM4_TMRA2_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422AA914UL))) +#define bM4_TMRA2_PCONR3_PERC0 (*((volatile unsigned int*)(0x422AA918UL))) +#define bM4_TMRA2_PCONR3_PERC1 (*((volatile unsigned int*)(0x422AA91CUL))) +#define bM4_TMRA2_PCONR3_FORC0 (*((volatile unsigned int*)(0x422AA920UL))) +#define bM4_TMRA2_PCONR3_FORC1 (*((volatile unsigned int*)(0x422AA924UL))) +#define bM4_TMRA2_PCONR3_OUTEN (*((volatile unsigned int*)(0x422AA930UL))) +#define bM4_TMRA2_PCONR4_STAC0 (*((volatile unsigned int*)(0x422AA980UL))) +#define bM4_TMRA2_PCONR4_STAC1 (*((volatile unsigned int*)(0x422AA984UL))) +#define bM4_TMRA2_PCONR4_STPC0 (*((volatile unsigned int*)(0x422AA988UL))) +#define bM4_TMRA2_PCONR4_STPC1 (*((volatile unsigned int*)(0x422AA98CUL))) +#define bM4_TMRA2_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422AA990UL))) +#define bM4_TMRA2_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422AA994UL))) +#define bM4_TMRA2_PCONR4_PERC0 (*((volatile unsigned int*)(0x422AA998UL))) +#define bM4_TMRA2_PCONR4_PERC1 (*((volatile unsigned int*)(0x422AA99CUL))) +#define bM4_TMRA2_PCONR4_FORC0 (*((volatile unsigned int*)(0x422AA9A0UL))) +#define bM4_TMRA2_PCONR4_FORC1 (*((volatile unsigned int*)(0x422AA9A4UL))) +#define bM4_TMRA2_PCONR4_OUTEN (*((volatile unsigned int*)(0x422AA9B0UL))) +#define bM4_TMRA2_PCONR5_STAC0 (*((volatile unsigned int*)(0x422AAA00UL))) +#define bM4_TMRA2_PCONR5_STAC1 (*((volatile unsigned int*)(0x422AAA04UL))) +#define bM4_TMRA2_PCONR5_STPC0 (*((volatile unsigned int*)(0x422AAA08UL))) +#define bM4_TMRA2_PCONR5_STPC1 (*((volatile unsigned int*)(0x422AAA0CUL))) +#define bM4_TMRA2_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422AAA10UL))) +#define bM4_TMRA2_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422AAA14UL))) +#define bM4_TMRA2_PCONR5_PERC0 (*((volatile unsigned int*)(0x422AAA18UL))) +#define bM4_TMRA2_PCONR5_PERC1 (*((volatile unsigned int*)(0x422AAA1CUL))) +#define bM4_TMRA2_PCONR5_FORC0 (*((volatile unsigned int*)(0x422AAA20UL))) +#define bM4_TMRA2_PCONR5_FORC1 (*((volatile unsigned int*)(0x422AAA24UL))) +#define bM4_TMRA2_PCONR5_OUTEN (*((volatile unsigned int*)(0x422AAA30UL))) +#define bM4_TMRA2_PCONR6_STAC0 (*((volatile unsigned int*)(0x422AAA80UL))) +#define bM4_TMRA2_PCONR6_STAC1 (*((volatile unsigned int*)(0x422AAA84UL))) +#define bM4_TMRA2_PCONR6_STPC0 (*((volatile unsigned int*)(0x422AAA88UL))) +#define bM4_TMRA2_PCONR6_STPC1 (*((volatile unsigned int*)(0x422AAA8CUL))) +#define bM4_TMRA2_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422AAA90UL))) +#define bM4_TMRA2_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422AAA94UL))) +#define bM4_TMRA2_PCONR6_PERC0 (*((volatile unsigned int*)(0x422AAA98UL))) +#define bM4_TMRA2_PCONR6_PERC1 (*((volatile unsigned int*)(0x422AAA9CUL))) +#define bM4_TMRA2_PCONR6_FORC0 (*((volatile unsigned int*)(0x422AAAA0UL))) +#define bM4_TMRA2_PCONR6_FORC1 (*((volatile unsigned int*)(0x422AAAA4UL))) +#define bM4_TMRA2_PCONR6_OUTEN (*((volatile unsigned int*)(0x422AAAB0UL))) +#define bM4_TMRA2_PCONR7_STAC0 (*((volatile unsigned int*)(0x422AAB00UL))) +#define bM4_TMRA2_PCONR7_STAC1 (*((volatile unsigned int*)(0x422AAB04UL))) +#define bM4_TMRA2_PCONR7_STPC0 (*((volatile unsigned int*)(0x422AAB08UL))) +#define bM4_TMRA2_PCONR7_STPC1 (*((volatile unsigned int*)(0x422AAB0CUL))) +#define bM4_TMRA2_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422AAB10UL))) +#define bM4_TMRA2_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422AAB14UL))) +#define bM4_TMRA2_PCONR7_PERC0 (*((volatile unsigned int*)(0x422AAB18UL))) +#define bM4_TMRA2_PCONR7_PERC1 (*((volatile unsigned int*)(0x422AAB1CUL))) +#define bM4_TMRA2_PCONR7_FORC0 (*((volatile unsigned int*)(0x422AAB20UL))) +#define bM4_TMRA2_PCONR7_FORC1 (*((volatile unsigned int*)(0x422AAB24UL))) +#define bM4_TMRA2_PCONR7_OUTEN (*((volatile unsigned int*)(0x422AAB30UL))) +#define bM4_TMRA2_PCONR8_STAC0 (*((volatile unsigned int*)(0x422AAB80UL))) +#define bM4_TMRA2_PCONR8_STAC1 (*((volatile unsigned int*)(0x422AAB84UL))) +#define bM4_TMRA2_PCONR8_STPC0 (*((volatile unsigned int*)(0x422AAB88UL))) +#define bM4_TMRA2_PCONR8_STPC1 (*((volatile unsigned int*)(0x422AAB8CUL))) +#define bM4_TMRA2_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422AAB90UL))) +#define bM4_TMRA2_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422AAB94UL))) +#define bM4_TMRA2_PCONR8_PERC0 (*((volatile unsigned int*)(0x422AAB98UL))) +#define bM4_TMRA2_PCONR8_PERC1 (*((volatile unsigned int*)(0x422AAB9CUL))) +#define bM4_TMRA2_PCONR8_FORC0 (*((volatile unsigned int*)(0x422AABA0UL))) +#define bM4_TMRA2_PCONR8_FORC1 (*((volatile unsigned int*)(0x422AABA4UL))) +#define bM4_TMRA2_PCONR8_OUTEN (*((volatile unsigned int*)(0x422AABB0UL))) +#define bM4_TMRA3_CNTER_CNT0 (*((volatile unsigned int*)(0x422B0000UL))) +#define bM4_TMRA3_CNTER_CNT1 (*((volatile unsigned int*)(0x422B0004UL))) +#define bM4_TMRA3_CNTER_CNT2 (*((volatile unsigned int*)(0x422B0008UL))) +#define bM4_TMRA3_CNTER_CNT3 (*((volatile unsigned int*)(0x422B000CUL))) +#define bM4_TMRA3_CNTER_CNT4 (*((volatile unsigned int*)(0x422B0010UL))) +#define bM4_TMRA3_CNTER_CNT5 (*((volatile unsigned int*)(0x422B0014UL))) +#define bM4_TMRA3_CNTER_CNT6 (*((volatile unsigned int*)(0x422B0018UL))) +#define bM4_TMRA3_CNTER_CNT7 (*((volatile unsigned int*)(0x422B001CUL))) +#define bM4_TMRA3_CNTER_CNT8 (*((volatile unsigned int*)(0x422B0020UL))) +#define bM4_TMRA3_CNTER_CNT9 (*((volatile unsigned int*)(0x422B0024UL))) +#define bM4_TMRA3_CNTER_CNT10 (*((volatile unsigned int*)(0x422B0028UL))) +#define bM4_TMRA3_CNTER_CNT11 (*((volatile unsigned int*)(0x422B002CUL))) +#define bM4_TMRA3_CNTER_CNT12 (*((volatile unsigned int*)(0x422B0030UL))) +#define bM4_TMRA3_CNTER_CNT13 (*((volatile unsigned int*)(0x422B0034UL))) +#define bM4_TMRA3_CNTER_CNT14 (*((volatile unsigned int*)(0x422B0038UL))) +#define bM4_TMRA3_CNTER_CNT15 (*((volatile unsigned int*)(0x422B003CUL))) +#define bM4_TMRA3_PERAR_PER0 (*((volatile unsigned int*)(0x422B0080UL))) +#define bM4_TMRA3_PERAR_PER1 (*((volatile unsigned int*)(0x422B0084UL))) +#define bM4_TMRA3_PERAR_PER2 (*((volatile unsigned int*)(0x422B0088UL))) +#define bM4_TMRA3_PERAR_PER3 (*((volatile unsigned int*)(0x422B008CUL))) +#define bM4_TMRA3_PERAR_PER4 (*((volatile unsigned int*)(0x422B0090UL))) +#define bM4_TMRA3_PERAR_PER5 (*((volatile unsigned int*)(0x422B0094UL))) +#define bM4_TMRA3_PERAR_PER6 (*((volatile unsigned int*)(0x422B0098UL))) +#define bM4_TMRA3_PERAR_PER7 (*((volatile unsigned int*)(0x422B009CUL))) +#define bM4_TMRA3_PERAR_PER8 (*((volatile unsigned int*)(0x422B00A0UL))) +#define bM4_TMRA3_PERAR_PER9 (*((volatile unsigned int*)(0x422B00A4UL))) +#define bM4_TMRA3_PERAR_PER10 (*((volatile unsigned int*)(0x422B00A8UL))) +#define bM4_TMRA3_PERAR_PER11 (*((volatile unsigned int*)(0x422B00ACUL))) +#define bM4_TMRA3_PERAR_PER12 (*((volatile unsigned int*)(0x422B00B0UL))) +#define bM4_TMRA3_PERAR_PER13 (*((volatile unsigned int*)(0x422B00B4UL))) +#define bM4_TMRA3_PERAR_PER14 (*((volatile unsigned int*)(0x422B00B8UL))) +#define bM4_TMRA3_PERAR_PER15 (*((volatile unsigned int*)(0x422B00BCUL))) +#define bM4_TMRA3_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B0800UL))) +#define bM4_TMRA3_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B0804UL))) +#define bM4_TMRA3_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B0808UL))) +#define bM4_TMRA3_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B080CUL))) +#define bM4_TMRA3_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B0810UL))) +#define bM4_TMRA3_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B0814UL))) +#define bM4_TMRA3_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B0818UL))) +#define bM4_TMRA3_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B081CUL))) +#define bM4_TMRA3_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B0820UL))) +#define bM4_TMRA3_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B0824UL))) +#define bM4_TMRA3_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B0828UL))) +#define bM4_TMRA3_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B082CUL))) +#define bM4_TMRA3_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B0830UL))) +#define bM4_TMRA3_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B0834UL))) +#define bM4_TMRA3_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B0838UL))) +#define bM4_TMRA3_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B083CUL))) +#define bM4_TMRA3_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B0880UL))) +#define bM4_TMRA3_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B0884UL))) +#define bM4_TMRA3_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B0888UL))) +#define bM4_TMRA3_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B088CUL))) +#define bM4_TMRA3_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B0890UL))) +#define bM4_TMRA3_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B0894UL))) +#define bM4_TMRA3_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B0898UL))) +#define bM4_TMRA3_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B089CUL))) +#define bM4_TMRA3_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B08A0UL))) +#define bM4_TMRA3_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B08A4UL))) +#define bM4_TMRA3_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B08A8UL))) +#define bM4_TMRA3_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B08ACUL))) +#define bM4_TMRA3_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B08B0UL))) +#define bM4_TMRA3_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B08B4UL))) +#define bM4_TMRA3_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B08B8UL))) +#define bM4_TMRA3_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B08BCUL))) +#define bM4_TMRA3_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B0900UL))) +#define bM4_TMRA3_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B0904UL))) +#define bM4_TMRA3_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B0908UL))) +#define bM4_TMRA3_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B090CUL))) +#define bM4_TMRA3_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B0910UL))) +#define bM4_TMRA3_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B0914UL))) +#define bM4_TMRA3_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B0918UL))) +#define bM4_TMRA3_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B091CUL))) +#define bM4_TMRA3_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B0920UL))) +#define bM4_TMRA3_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B0924UL))) +#define bM4_TMRA3_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B0928UL))) +#define bM4_TMRA3_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B092CUL))) +#define bM4_TMRA3_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B0930UL))) +#define bM4_TMRA3_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B0934UL))) +#define bM4_TMRA3_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B0938UL))) +#define bM4_TMRA3_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B093CUL))) +#define bM4_TMRA3_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B0980UL))) +#define bM4_TMRA3_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B0984UL))) +#define bM4_TMRA3_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B0988UL))) +#define bM4_TMRA3_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B098CUL))) +#define bM4_TMRA3_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B0990UL))) +#define bM4_TMRA3_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B0994UL))) +#define bM4_TMRA3_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B0998UL))) +#define bM4_TMRA3_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B099CUL))) +#define bM4_TMRA3_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B09A0UL))) +#define bM4_TMRA3_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B09A4UL))) +#define bM4_TMRA3_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B09A8UL))) +#define bM4_TMRA3_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B09ACUL))) +#define bM4_TMRA3_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B09B0UL))) +#define bM4_TMRA3_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B09B4UL))) +#define bM4_TMRA3_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B09B8UL))) +#define bM4_TMRA3_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B09BCUL))) +#define bM4_TMRA3_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B0A00UL))) +#define bM4_TMRA3_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B0A04UL))) +#define bM4_TMRA3_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B0A08UL))) +#define bM4_TMRA3_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B0A0CUL))) +#define bM4_TMRA3_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B0A10UL))) +#define bM4_TMRA3_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B0A14UL))) +#define bM4_TMRA3_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B0A18UL))) +#define bM4_TMRA3_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B0A1CUL))) +#define bM4_TMRA3_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B0A20UL))) +#define bM4_TMRA3_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B0A24UL))) +#define bM4_TMRA3_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B0A28UL))) +#define bM4_TMRA3_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B0A2CUL))) +#define bM4_TMRA3_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B0A30UL))) +#define bM4_TMRA3_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B0A34UL))) +#define bM4_TMRA3_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B0A38UL))) +#define bM4_TMRA3_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B0A3CUL))) +#define bM4_TMRA3_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B0A80UL))) +#define bM4_TMRA3_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B0A84UL))) +#define bM4_TMRA3_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B0A88UL))) +#define bM4_TMRA3_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B0A8CUL))) +#define bM4_TMRA3_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B0A90UL))) +#define bM4_TMRA3_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B0A94UL))) +#define bM4_TMRA3_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B0A98UL))) +#define bM4_TMRA3_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B0A9CUL))) +#define bM4_TMRA3_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B0AA0UL))) +#define bM4_TMRA3_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B0AA4UL))) +#define bM4_TMRA3_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B0AA8UL))) +#define bM4_TMRA3_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B0AACUL))) +#define bM4_TMRA3_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B0AB0UL))) +#define bM4_TMRA3_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B0AB4UL))) +#define bM4_TMRA3_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B0AB8UL))) +#define bM4_TMRA3_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B0ABCUL))) +#define bM4_TMRA3_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B0B00UL))) +#define bM4_TMRA3_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B0B04UL))) +#define bM4_TMRA3_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B0B08UL))) +#define bM4_TMRA3_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B0B0CUL))) +#define bM4_TMRA3_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B0B10UL))) +#define bM4_TMRA3_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B0B14UL))) +#define bM4_TMRA3_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B0B18UL))) +#define bM4_TMRA3_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B0B1CUL))) +#define bM4_TMRA3_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B0B20UL))) +#define bM4_TMRA3_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B0B24UL))) +#define bM4_TMRA3_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B0B28UL))) +#define bM4_TMRA3_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B0B2CUL))) +#define bM4_TMRA3_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B0B30UL))) +#define bM4_TMRA3_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B0B34UL))) +#define bM4_TMRA3_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B0B38UL))) +#define bM4_TMRA3_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B0B3CUL))) +#define bM4_TMRA3_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B0B80UL))) +#define bM4_TMRA3_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B0B84UL))) +#define bM4_TMRA3_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B0B88UL))) +#define bM4_TMRA3_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B0B8CUL))) +#define bM4_TMRA3_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B0B90UL))) +#define bM4_TMRA3_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B0B94UL))) +#define bM4_TMRA3_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B0B98UL))) +#define bM4_TMRA3_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B0B9CUL))) +#define bM4_TMRA3_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B0BA0UL))) +#define bM4_TMRA3_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B0BA4UL))) +#define bM4_TMRA3_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B0BA8UL))) +#define bM4_TMRA3_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B0BACUL))) +#define bM4_TMRA3_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B0BB0UL))) +#define bM4_TMRA3_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B0BB4UL))) +#define bM4_TMRA3_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B0BB8UL))) +#define bM4_TMRA3_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B0BBCUL))) +#define bM4_TMRA3_BCSTR_START (*((volatile unsigned int*)(0x422B1000UL))) +#define bM4_TMRA3_BCSTR_DIR (*((volatile unsigned int*)(0x422B1004UL))) +#define bM4_TMRA3_BCSTR_MODE (*((volatile unsigned int*)(0x422B1008UL))) +#define bM4_TMRA3_BCSTR_SYNST (*((volatile unsigned int*)(0x422B100CUL))) +#define bM4_TMRA3_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B1010UL))) +#define bM4_TMRA3_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B1014UL))) +#define bM4_TMRA3_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B1018UL))) +#define bM4_TMRA3_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B101CUL))) +#define bM4_TMRA3_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B1030UL))) +#define bM4_TMRA3_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B1034UL))) +#define bM4_TMRA3_BCSTR_OVFF (*((volatile unsigned int*)(0x422B1038UL))) +#define bM4_TMRA3_BCSTR_UDFF (*((volatile unsigned int*)(0x422B103CUL))) +#define bM4_TMRA3_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B1080UL))) +#define bM4_TMRA3_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B1084UL))) +#define bM4_TMRA3_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B1088UL))) +#define bM4_TMRA3_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B1090UL))) +#define bM4_TMRA3_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B1094UL))) +#define bM4_TMRA3_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B1098UL))) +#define bM4_TMRA3_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B10A0UL))) +#define bM4_TMRA3_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B10A4UL))) +#define bM4_TMRA3_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B10A8UL))) +#define bM4_TMRA3_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B10B0UL))) +#define bM4_TMRA3_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B10B4UL))) +#define bM4_TMRA3_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B10B8UL))) +#define bM4_TMRA3_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B10BCUL))) +#define bM4_TMRA3_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B1100UL))) +#define bM4_TMRA3_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B1104UL))) +#define bM4_TMRA3_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B1108UL))) +#define bM4_TMRA3_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B110CUL))) +#define bM4_TMRA3_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B1110UL))) +#define bM4_TMRA3_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B1114UL))) +#define bM4_TMRA3_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B1118UL))) +#define bM4_TMRA3_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B111CUL))) +#define bM4_TMRA3_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B1120UL))) +#define bM4_TMRA3_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B1124UL))) +#define bM4_TMRA3_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B1128UL))) +#define bM4_TMRA3_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B112CUL))) +#define bM4_TMRA3_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B1130UL))) +#define bM4_TMRA3_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B1180UL))) +#define bM4_TMRA3_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B1184UL))) +#define bM4_TMRA3_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B1188UL))) +#define bM4_TMRA3_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B118CUL))) +#define bM4_TMRA3_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B1190UL))) +#define bM4_TMRA3_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B1194UL))) +#define bM4_TMRA3_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B1198UL))) +#define bM4_TMRA3_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B119CUL))) +#define bM4_TMRA3_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B11A0UL))) +#define bM4_TMRA3_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B11A4UL))) +#define bM4_TMRA3_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B11A8UL))) +#define bM4_TMRA3_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B11ACUL))) +#define bM4_TMRA3_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B11B0UL))) +#define bM4_TMRA3_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B1200UL))) +#define bM4_TMRA3_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B1204UL))) +#define bM4_TMRA3_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B1208UL))) +#define bM4_TMRA3_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B120CUL))) +#define bM4_TMRA3_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B1210UL))) +#define bM4_TMRA3_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B1214UL))) +#define bM4_TMRA3_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B1218UL))) +#define bM4_TMRA3_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B121CUL))) +#define bM4_TMRA3_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B1280UL))) +#define bM4_TMRA3_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B1284UL))) +#define bM4_TMRA3_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B1288UL))) +#define bM4_TMRA3_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B128CUL))) +#define bM4_TMRA3_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B1290UL))) +#define bM4_TMRA3_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B1294UL))) +#define bM4_TMRA3_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B1298UL))) +#define bM4_TMRA3_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B129CUL))) +#define bM4_TMRA3_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B1300UL))) +#define bM4_TMRA3_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B1304UL))) +#define bM4_TMRA3_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B1308UL))) +#define bM4_TMRA3_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B1320UL))) +#define bM4_TMRA3_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B1324UL))) +#define bM4_TMRA3_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B1328UL))) +#define bM4_TMRA3_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B1330UL))) +#define bM4_TMRA3_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B1334UL))) +#define bM4_TMRA3_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B1338UL))) +#define bM4_TMRA3_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B1380UL))) +#define bM4_TMRA3_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B1384UL))) +#define bM4_TMRA3_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B1388UL))) +#define bM4_TMRA3_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B138CUL))) +#define bM4_TMRA3_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B1390UL))) +#define bM4_TMRA3_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B1394UL))) +#define bM4_TMRA3_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B1398UL))) +#define bM4_TMRA3_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B139CUL))) +#define bM4_TMRA3_BCONR1_BEN (*((volatile unsigned int*)(0x422B1800UL))) +#define bM4_TMRA3_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B1804UL))) +#define bM4_TMRA3_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B1808UL))) +#define bM4_TMRA3_BCONR2_BEN (*((volatile unsigned int*)(0x422B1900UL))) +#define bM4_TMRA3_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B1904UL))) +#define bM4_TMRA3_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B1908UL))) +#define bM4_TMRA3_BCONR3_BEN (*((volatile unsigned int*)(0x422B1A00UL))) +#define bM4_TMRA3_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B1A04UL))) +#define bM4_TMRA3_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B1A08UL))) +#define bM4_TMRA3_BCONR4_BEN (*((volatile unsigned int*)(0x422B1B00UL))) +#define bM4_TMRA3_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B1B04UL))) +#define bM4_TMRA3_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B1B08UL))) +#define bM4_TMRA3_CCONR1_CAPMD (*((volatile unsigned int*)(0x422B2000UL))) +#define bM4_TMRA3_CCONR1_HICP0 (*((volatile unsigned int*)(0x422B2010UL))) +#define bM4_TMRA3_CCONR1_HICP1 (*((volatile unsigned int*)(0x422B2014UL))) +#define bM4_TMRA3_CCONR1_HICP2 (*((volatile unsigned int*)(0x422B2018UL))) +#define bM4_TMRA3_CCONR1_HICP3 (*((volatile unsigned int*)(0x422B2020UL))) +#define bM4_TMRA3_CCONR1_HICP4 (*((volatile unsigned int*)(0x422B2024UL))) +#define bM4_TMRA3_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422B2030UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422B2034UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422B2038UL))) +#define bM4_TMRA3_CCONR2_CAPMD (*((volatile unsigned int*)(0x422B2080UL))) +#define bM4_TMRA3_CCONR2_HICP0 (*((volatile unsigned int*)(0x422B2090UL))) +#define bM4_TMRA3_CCONR2_HICP1 (*((volatile unsigned int*)(0x422B2094UL))) +#define bM4_TMRA3_CCONR2_HICP2 (*((volatile unsigned int*)(0x422B2098UL))) +#define bM4_TMRA3_CCONR2_HICP3 (*((volatile unsigned int*)(0x422B20A0UL))) +#define bM4_TMRA3_CCONR2_HICP4 (*((volatile unsigned int*)(0x422B20A4UL))) +#define bM4_TMRA3_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422B20B0UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422B20B4UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422B20B8UL))) +#define bM4_TMRA3_CCONR3_CAPMD (*((volatile unsigned int*)(0x422B2100UL))) +#define bM4_TMRA3_CCONR3_HICP0 (*((volatile unsigned int*)(0x422B2110UL))) +#define bM4_TMRA3_CCONR3_HICP1 (*((volatile unsigned int*)(0x422B2114UL))) +#define bM4_TMRA3_CCONR3_HICP2 (*((volatile unsigned int*)(0x422B2118UL))) +#define bM4_TMRA3_CCONR3_HICP3 (*((volatile unsigned int*)(0x422B2120UL))) +#define bM4_TMRA3_CCONR3_HICP4 (*((volatile unsigned int*)(0x422B2124UL))) +#define bM4_TMRA3_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422B2130UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422B2134UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422B2138UL))) +#define bM4_TMRA3_CCONR4_CAPMD (*((volatile unsigned int*)(0x422B2180UL))) +#define bM4_TMRA3_CCONR4_HICP0 (*((volatile unsigned int*)(0x422B2190UL))) +#define bM4_TMRA3_CCONR4_HICP1 (*((volatile unsigned int*)(0x422B2194UL))) +#define bM4_TMRA3_CCONR4_HICP2 (*((volatile unsigned int*)(0x422B2198UL))) +#define bM4_TMRA3_CCONR4_HICP3 (*((volatile unsigned int*)(0x422B21A0UL))) +#define bM4_TMRA3_CCONR4_HICP4 (*((volatile unsigned int*)(0x422B21A4UL))) +#define bM4_TMRA3_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422B21B0UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422B21B4UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422B21B8UL))) +#define bM4_TMRA3_CCONR5_CAPMD (*((volatile unsigned int*)(0x422B2200UL))) +#define bM4_TMRA3_CCONR5_HICP0 (*((volatile unsigned int*)(0x422B2210UL))) +#define bM4_TMRA3_CCONR5_HICP1 (*((volatile unsigned int*)(0x422B2214UL))) +#define bM4_TMRA3_CCONR5_HICP2 (*((volatile unsigned int*)(0x422B2218UL))) +#define bM4_TMRA3_CCONR5_HICP3 (*((volatile unsigned int*)(0x422B2220UL))) +#define bM4_TMRA3_CCONR5_HICP4 (*((volatile unsigned int*)(0x422B2224UL))) +#define bM4_TMRA3_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422B2230UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422B2234UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422B2238UL))) +#define bM4_TMRA3_CCONR6_CAPMD (*((volatile unsigned int*)(0x422B2280UL))) +#define bM4_TMRA3_CCONR6_HICP0 (*((volatile unsigned int*)(0x422B2290UL))) +#define bM4_TMRA3_CCONR6_HICP1 (*((volatile unsigned int*)(0x422B2294UL))) +#define bM4_TMRA3_CCONR6_HICP2 (*((volatile unsigned int*)(0x422B2298UL))) +#define bM4_TMRA3_CCONR6_HICP3 (*((volatile unsigned int*)(0x422B22A0UL))) +#define bM4_TMRA3_CCONR6_HICP4 (*((volatile unsigned int*)(0x422B22A4UL))) +#define bM4_TMRA3_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422B22B0UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422B22B4UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422B22B8UL))) +#define bM4_TMRA3_CCONR7_CAPMD (*((volatile unsigned int*)(0x422B2300UL))) +#define bM4_TMRA3_CCONR7_HICP0 (*((volatile unsigned int*)(0x422B2310UL))) +#define bM4_TMRA3_CCONR7_HICP1 (*((volatile unsigned int*)(0x422B2314UL))) +#define bM4_TMRA3_CCONR7_HICP2 (*((volatile unsigned int*)(0x422B2318UL))) +#define bM4_TMRA3_CCONR7_HICP3 (*((volatile unsigned int*)(0x422B2320UL))) +#define bM4_TMRA3_CCONR7_HICP4 (*((volatile unsigned int*)(0x422B2324UL))) +#define bM4_TMRA3_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422B2330UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422B2334UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422B2338UL))) +#define bM4_TMRA3_CCONR8_CAPMD (*((volatile unsigned int*)(0x422B2380UL))) +#define bM4_TMRA3_CCONR8_HICP0 (*((volatile unsigned int*)(0x422B2390UL))) +#define bM4_TMRA3_CCONR8_HICP1 (*((volatile unsigned int*)(0x422B2394UL))) +#define bM4_TMRA3_CCONR8_HICP2 (*((volatile unsigned int*)(0x422B2398UL))) +#define bM4_TMRA3_CCONR8_HICP3 (*((volatile unsigned int*)(0x422B23A0UL))) +#define bM4_TMRA3_CCONR8_HICP4 (*((volatile unsigned int*)(0x422B23A4UL))) +#define bM4_TMRA3_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422B23B0UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422B23B4UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422B23B8UL))) +#define bM4_TMRA3_PCONR1_STAC0 (*((volatile unsigned int*)(0x422B2800UL))) +#define bM4_TMRA3_PCONR1_STAC1 (*((volatile unsigned int*)(0x422B2804UL))) +#define bM4_TMRA3_PCONR1_STPC0 (*((volatile unsigned int*)(0x422B2808UL))) +#define bM4_TMRA3_PCONR1_STPC1 (*((volatile unsigned int*)(0x422B280CUL))) +#define bM4_TMRA3_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422B2810UL))) +#define bM4_TMRA3_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422B2814UL))) +#define bM4_TMRA3_PCONR1_PERC0 (*((volatile unsigned int*)(0x422B2818UL))) +#define bM4_TMRA3_PCONR1_PERC1 (*((volatile unsigned int*)(0x422B281CUL))) +#define bM4_TMRA3_PCONR1_FORC0 (*((volatile unsigned int*)(0x422B2820UL))) +#define bM4_TMRA3_PCONR1_FORC1 (*((volatile unsigned int*)(0x422B2824UL))) +#define bM4_TMRA3_PCONR1_OUTEN (*((volatile unsigned int*)(0x422B2830UL))) +#define bM4_TMRA3_PCONR2_STAC0 (*((volatile unsigned int*)(0x422B2880UL))) +#define bM4_TMRA3_PCONR2_STAC1 (*((volatile unsigned int*)(0x422B2884UL))) +#define bM4_TMRA3_PCONR2_STPC0 (*((volatile unsigned int*)(0x422B2888UL))) +#define bM4_TMRA3_PCONR2_STPC1 (*((volatile unsigned int*)(0x422B288CUL))) +#define bM4_TMRA3_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422B2890UL))) +#define bM4_TMRA3_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422B2894UL))) +#define bM4_TMRA3_PCONR2_PERC0 (*((volatile unsigned int*)(0x422B2898UL))) +#define bM4_TMRA3_PCONR2_PERC1 (*((volatile unsigned int*)(0x422B289CUL))) +#define bM4_TMRA3_PCONR2_FORC0 (*((volatile unsigned int*)(0x422B28A0UL))) +#define bM4_TMRA3_PCONR2_FORC1 (*((volatile unsigned int*)(0x422B28A4UL))) +#define bM4_TMRA3_PCONR2_OUTEN (*((volatile unsigned int*)(0x422B28B0UL))) +#define bM4_TMRA3_PCONR3_STAC0 (*((volatile unsigned int*)(0x422B2900UL))) +#define bM4_TMRA3_PCONR3_STAC1 (*((volatile unsigned int*)(0x422B2904UL))) +#define bM4_TMRA3_PCONR3_STPC0 (*((volatile unsigned int*)(0x422B2908UL))) +#define bM4_TMRA3_PCONR3_STPC1 (*((volatile unsigned int*)(0x422B290CUL))) +#define bM4_TMRA3_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422B2910UL))) +#define bM4_TMRA3_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422B2914UL))) +#define bM4_TMRA3_PCONR3_PERC0 (*((volatile unsigned int*)(0x422B2918UL))) +#define bM4_TMRA3_PCONR3_PERC1 (*((volatile unsigned int*)(0x422B291CUL))) +#define bM4_TMRA3_PCONR3_FORC0 (*((volatile unsigned int*)(0x422B2920UL))) +#define bM4_TMRA3_PCONR3_FORC1 (*((volatile unsigned int*)(0x422B2924UL))) +#define bM4_TMRA3_PCONR3_OUTEN (*((volatile unsigned int*)(0x422B2930UL))) +#define bM4_TMRA3_PCONR4_STAC0 (*((volatile unsigned int*)(0x422B2980UL))) +#define bM4_TMRA3_PCONR4_STAC1 (*((volatile unsigned int*)(0x422B2984UL))) +#define bM4_TMRA3_PCONR4_STPC0 (*((volatile unsigned int*)(0x422B2988UL))) +#define bM4_TMRA3_PCONR4_STPC1 (*((volatile unsigned int*)(0x422B298CUL))) +#define bM4_TMRA3_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422B2990UL))) +#define bM4_TMRA3_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422B2994UL))) +#define bM4_TMRA3_PCONR4_PERC0 (*((volatile unsigned int*)(0x422B2998UL))) +#define bM4_TMRA3_PCONR4_PERC1 (*((volatile unsigned int*)(0x422B299CUL))) +#define bM4_TMRA3_PCONR4_FORC0 (*((volatile unsigned int*)(0x422B29A0UL))) +#define bM4_TMRA3_PCONR4_FORC1 (*((volatile unsigned int*)(0x422B29A4UL))) +#define bM4_TMRA3_PCONR4_OUTEN (*((volatile unsigned int*)(0x422B29B0UL))) +#define bM4_TMRA3_PCONR5_STAC0 (*((volatile unsigned int*)(0x422B2A00UL))) +#define bM4_TMRA3_PCONR5_STAC1 (*((volatile unsigned int*)(0x422B2A04UL))) +#define bM4_TMRA3_PCONR5_STPC0 (*((volatile unsigned int*)(0x422B2A08UL))) +#define bM4_TMRA3_PCONR5_STPC1 (*((volatile unsigned int*)(0x422B2A0CUL))) +#define bM4_TMRA3_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422B2A10UL))) +#define bM4_TMRA3_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422B2A14UL))) +#define bM4_TMRA3_PCONR5_PERC0 (*((volatile unsigned int*)(0x422B2A18UL))) +#define bM4_TMRA3_PCONR5_PERC1 (*((volatile unsigned int*)(0x422B2A1CUL))) +#define bM4_TMRA3_PCONR5_FORC0 (*((volatile unsigned int*)(0x422B2A20UL))) +#define bM4_TMRA3_PCONR5_FORC1 (*((volatile unsigned int*)(0x422B2A24UL))) +#define bM4_TMRA3_PCONR5_OUTEN (*((volatile unsigned int*)(0x422B2A30UL))) +#define bM4_TMRA3_PCONR6_STAC0 (*((volatile unsigned int*)(0x422B2A80UL))) +#define bM4_TMRA3_PCONR6_STAC1 (*((volatile unsigned int*)(0x422B2A84UL))) +#define bM4_TMRA3_PCONR6_STPC0 (*((volatile unsigned int*)(0x422B2A88UL))) +#define bM4_TMRA3_PCONR6_STPC1 (*((volatile unsigned int*)(0x422B2A8CUL))) +#define bM4_TMRA3_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422B2A90UL))) +#define bM4_TMRA3_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422B2A94UL))) +#define bM4_TMRA3_PCONR6_PERC0 (*((volatile unsigned int*)(0x422B2A98UL))) +#define bM4_TMRA3_PCONR6_PERC1 (*((volatile unsigned int*)(0x422B2A9CUL))) +#define bM4_TMRA3_PCONR6_FORC0 (*((volatile unsigned int*)(0x422B2AA0UL))) +#define bM4_TMRA3_PCONR6_FORC1 (*((volatile unsigned int*)(0x422B2AA4UL))) +#define bM4_TMRA3_PCONR6_OUTEN (*((volatile unsigned int*)(0x422B2AB0UL))) +#define bM4_TMRA3_PCONR7_STAC0 (*((volatile unsigned int*)(0x422B2B00UL))) +#define bM4_TMRA3_PCONR7_STAC1 (*((volatile unsigned int*)(0x422B2B04UL))) +#define bM4_TMRA3_PCONR7_STPC0 (*((volatile unsigned int*)(0x422B2B08UL))) +#define bM4_TMRA3_PCONR7_STPC1 (*((volatile unsigned int*)(0x422B2B0CUL))) +#define bM4_TMRA3_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422B2B10UL))) +#define bM4_TMRA3_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422B2B14UL))) +#define bM4_TMRA3_PCONR7_PERC0 (*((volatile unsigned int*)(0x422B2B18UL))) +#define bM4_TMRA3_PCONR7_PERC1 (*((volatile unsigned int*)(0x422B2B1CUL))) +#define bM4_TMRA3_PCONR7_FORC0 (*((volatile unsigned int*)(0x422B2B20UL))) +#define bM4_TMRA3_PCONR7_FORC1 (*((volatile unsigned int*)(0x422B2B24UL))) +#define bM4_TMRA3_PCONR7_OUTEN (*((volatile unsigned int*)(0x422B2B30UL))) +#define bM4_TMRA3_PCONR8_STAC0 (*((volatile unsigned int*)(0x422B2B80UL))) +#define bM4_TMRA3_PCONR8_STAC1 (*((volatile unsigned int*)(0x422B2B84UL))) +#define bM4_TMRA3_PCONR8_STPC0 (*((volatile unsigned int*)(0x422B2B88UL))) +#define bM4_TMRA3_PCONR8_STPC1 (*((volatile unsigned int*)(0x422B2B8CUL))) +#define bM4_TMRA3_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422B2B90UL))) +#define bM4_TMRA3_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422B2B94UL))) +#define bM4_TMRA3_PCONR8_PERC0 (*((volatile unsigned int*)(0x422B2B98UL))) +#define bM4_TMRA3_PCONR8_PERC1 (*((volatile unsigned int*)(0x422B2B9CUL))) +#define bM4_TMRA3_PCONR8_FORC0 (*((volatile unsigned int*)(0x422B2BA0UL))) +#define bM4_TMRA3_PCONR8_FORC1 (*((volatile unsigned int*)(0x422B2BA4UL))) +#define bM4_TMRA3_PCONR8_OUTEN (*((volatile unsigned int*)(0x422B2BB0UL))) +#define bM4_TMRA4_CNTER_CNT0 (*((volatile unsigned int*)(0x422B8000UL))) +#define bM4_TMRA4_CNTER_CNT1 (*((volatile unsigned int*)(0x422B8004UL))) +#define bM4_TMRA4_CNTER_CNT2 (*((volatile unsigned int*)(0x422B8008UL))) +#define bM4_TMRA4_CNTER_CNT3 (*((volatile unsigned int*)(0x422B800CUL))) +#define bM4_TMRA4_CNTER_CNT4 (*((volatile unsigned int*)(0x422B8010UL))) +#define bM4_TMRA4_CNTER_CNT5 (*((volatile unsigned int*)(0x422B8014UL))) +#define bM4_TMRA4_CNTER_CNT6 (*((volatile unsigned int*)(0x422B8018UL))) +#define bM4_TMRA4_CNTER_CNT7 (*((volatile unsigned int*)(0x422B801CUL))) +#define bM4_TMRA4_CNTER_CNT8 (*((volatile unsigned int*)(0x422B8020UL))) +#define bM4_TMRA4_CNTER_CNT9 (*((volatile unsigned int*)(0x422B8024UL))) +#define bM4_TMRA4_CNTER_CNT10 (*((volatile unsigned int*)(0x422B8028UL))) +#define bM4_TMRA4_CNTER_CNT11 (*((volatile unsigned int*)(0x422B802CUL))) +#define bM4_TMRA4_CNTER_CNT12 (*((volatile unsigned int*)(0x422B8030UL))) +#define bM4_TMRA4_CNTER_CNT13 (*((volatile unsigned int*)(0x422B8034UL))) +#define bM4_TMRA4_CNTER_CNT14 (*((volatile unsigned int*)(0x422B8038UL))) +#define bM4_TMRA4_CNTER_CNT15 (*((volatile unsigned int*)(0x422B803CUL))) +#define bM4_TMRA4_PERAR_PER0 (*((volatile unsigned int*)(0x422B8080UL))) +#define bM4_TMRA4_PERAR_PER1 (*((volatile unsigned int*)(0x422B8084UL))) +#define bM4_TMRA4_PERAR_PER2 (*((volatile unsigned int*)(0x422B8088UL))) +#define bM4_TMRA4_PERAR_PER3 (*((volatile unsigned int*)(0x422B808CUL))) +#define bM4_TMRA4_PERAR_PER4 (*((volatile unsigned int*)(0x422B8090UL))) +#define bM4_TMRA4_PERAR_PER5 (*((volatile unsigned int*)(0x422B8094UL))) +#define bM4_TMRA4_PERAR_PER6 (*((volatile unsigned int*)(0x422B8098UL))) +#define bM4_TMRA4_PERAR_PER7 (*((volatile unsigned int*)(0x422B809CUL))) +#define bM4_TMRA4_PERAR_PER8 (*((volatile unsigned int*)(0x422B80A0UL))) +#define bM4_TMRA4_PERAR_PER9 (*((volatile unsigned int*)(0x422B80A4UL))) +#define bM4_TMRA4_PERAR_PER10 (*((volatile unsigned int*)(0x422B80A8UL))) +#define bM4_TMRA4_PERAR_PER11 (*((volatile unsigned int*)(0x422B80ACUL))) +#define bM4_TMRA4_PERAR_PER12 (*((volatile unsigned int*)(0x422B80B0UL))) +#define bM4_TMRA4_PERAR_PER13 (*((volatile unsigned int*)(0x422B80B4UL))) +#define bM4_TMRA4_PERAR_PER14 (*((volatile unsigned int*)(0x422B80B8UL))) +#define bM4_TMRA4_PERAR_PER15 (*((volatile unsigned int*)(0x422B80BCUL))) +#define bM4_TMRA4_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B8800UL))) +#define bM4_TMRA4_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B8804UL))) +#define bM4_TMRA4_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B8808UL))) +#define bM4_TMRA4_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B880CUL))) +#define bM4_TMRA4_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B8810UL))) +#define bM4_TMRA4_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B8814UL))) +#define bM4_TMRA4_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B8818UL))) +#define bM4_TMRA4_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B881CUL))) +#define bM4_TMRA4_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B8820UL))) +#define bM4_TMRA4_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B8824UL))) +#define bM4_TMRA4_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B8828UL))) +#define bM4_TMRA4_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B882CUL))) +#define bM4_TMRA4_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B8830UL))) +#define bM4_TMRA4_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B8834UL))) +#define bM4_TMRA4_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B8838UL))) +#define bM4_TMRA4_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B883CUL))) +#define bM4_TMRA4_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B8880UL))) +#define bM4_TMRA4_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B8884UL))) +#define bM4_TMRA4_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B8888UL))) +#define bM4_TMRA4_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B888CUL))) +#define bM4_TMRA4_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B8890UL))) +#define bM4_TMRA4_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B8894UL))) +#define bM4_TMRA4_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B8898UL))) +#define bM4_TMRA4_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B889CUL))) +#define bM4_TMRA4_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B88A0UL))) +#define bM4_TMRA4_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B88A4UL))) +#define bM4_TMRA4_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B88A8UL))) +#define bM4_TMRA4_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B88ACUL))) +#define bM4_TMRA4_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B88B0UL))) +#define bM4_TMRA4_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B88B4UL))) +#define bM4_TMRA4_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B88B8UL))) +#define bM4_TMRA4_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B88BCUL))) +#define bM4_TMRA4_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B8900UL))) +#define bM4_TMRA4_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B8904UL))) +#define bM4_TMRA4_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B8908UL))) +#define bM4_TMRA4_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B890CUL))) +#define bM4_TMRA4_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B8910UL))) +#define bM4_TMRA4_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B8914UL))) +#define bM4_TMRA4_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B8918UL))) +#define bM4_TMRA4_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B891CUL))) +#define bM4_TMRA4_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B8920UL))) +#define bM4_TMRA4_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B8924UL))) +#define bM4_TMRA4_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B8928UL))) +#define bM4_TMRA4_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B892CUL))) +#define bM4_TMRA4_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B8930UL))) +#define bM4_TMRA4_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B8934UL))) +#define bM4_TMRA4_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B8938UL))) +#define bM4_TMRA4_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B893CUL))) +#define bM4_TMRA4_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B8980UL))) +#define bM4_TMRA4_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B8984UL))) +#define bM4_TMRA4_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B8988UL))) +#define bM4_TMRA4_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B898CUL))) +#define bM4_TMRA4_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B8990UL))) +#define bM4_TMRA4_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B8994UL))) +#define bM4_TMRA4_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B8998UL))) +#define bM4_TMRA4_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B899CUL))) +#define bM4_TMRA4_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B89A0UL))) +#define bM4_TMRA4_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B89A4UL))) +#define bM4_TMRA4_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B89A8UL))) +#define bM4_TMRA4_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B89ACUL))) +#define bM4_TMRA4_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B89B0UL))) +#define bM4_TMRA4_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B89B4UL))) +#define bM4_TMRA4_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B89B8UL))) +#define bM4_TMRA4_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B89BCUL))) +#define bM4_TMRA4_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B8A00UL))) +#define bM4_TMRA4_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B8A04UL))) +#define bM4_TMRA4_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B8A08UL))) +#define bM4_TMRA4_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B8A0CUL))) +#define bM4_TMRA4_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B8A10UL))) +#define bM4_TMRA4_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B8A14UL))) +#define bM4_TMRA4_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B8A18UL))) +#define bM4_TMRA4_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B8A1CUL))) +#define bM4_TMRA4_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B8A20UL))) +#define bM4_TMRA4_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B8A24UL))) +#define bM4_TMRA4_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B8A28UL))) +#define bM4_TMRA4_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B8A2CUL))) +#define bM4_TMRA4_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B8A30UL))) +#define bM4_TMRA4_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B8A34UL))) +#define bM4_TMRA4_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B8A38UL))) +#define bM4_TMRA4_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B8A3CUL))) +#define bM4_TMRA4_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B8A80UL))) +#define bM4_TMRA4_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B8A84UL))) +#define bM4_TMRA4_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B8A88UL))) +#define bM4_TMRA4_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B8A8CUL))) +#define bM4_TMRA4_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B8A90UL))) +#define bM4_TMRA4_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B8A94UL))) +#define bM4_TMRA4_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B8A98UL))) +#define bM4_TMRA4_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B8A9CUL))) +#define bM4_TMRA4_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B8AA0UL))) +#define bM4_TMRA4_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B8AA4UL))) +#define bM4_TMRA4_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B8AA8UL))) +#define bM4_TMRA4_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B8AACUL))) +#define bM4_TMRA4_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B8AB0UL))) +#define bM4_TMRA4_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B8AB4UL))) +#define bM4_TMRA4_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B8AB8UL))) +#define bM4_TMRA4_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B8ABCUL))) +#define bM4_TMRA4_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B8B00UL))) +#define bM4_TMRA4_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B8B04UL))) +#define bM4_TMRA4_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B8B08UL))) +#define bM4_TMRA4_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B8B0CUL))) +#define bM4_TMRA4_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B8B10UL))) +#define bM4_TMRA4_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B8B14UL))) +#define bM4_TMRA4_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B8B18UL))) +#define bM4_TMRA4_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B8B1CUL))) +#define bM4_TMRA4_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B8B20UL))) +#define bM4_TMRA4_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B8B24UL))) +#define bM4_TMRA4_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B8B28UL))) +#define bM4_TMRA4_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B8B2CUL))) +#define bM4_TMRA4_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B8B30UL))) +#define bM4_TMRA4_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B8B34UL))) +#define bM4_TMRA4_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B8B38UL))) +#define bM4_TMRA4_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B8B3CUL))) +#define bM4_TMRA4_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B8B80UL))) +#define bM4_TMRA4_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B8B84UL))) +#define bM4_TMRA4_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B8B88UL))) +#define bM4_TMRA4_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B8B8CUL))) +#define bM4_TMRA4_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B8B90UL))) +#define bM4_TMRA4_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B8B94UL))) +#define bM4_TMRA4_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B8B98UL))) +#define bM4_TMRA4_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B8B9CUL))) +#define bM4_TMRA4_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B8BA0UL))) +#define bM4_TMRA4_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B8BA4UL))) +#define bM4_TMRA4_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B8BA8UL))) +#define bM4_TMRA4_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B8BACUL))) +#define bM4_TMRA4_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B8BB0UL))) +#define bM4_TMRA4_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B8BB4UL))) +#define bM4_TMRA4_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B8BB8UL))) +#define bM4_TMRA4_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B8BBCUL))) +#define bM4_TMRA4_BCSTR_START (*((volatile unsigned int*)(0x422B9000UL))) +#define bM4_TMRA4_BCSTR_DIR (*((volatile unsigned int*)(0x422B9004UL))) +#define bM4_TMRA4_BCSTR_MODE (*((volatile unsigned int*)(0x422B9008UL))) +#define bM4_TMRA4_BCSTR_SYNST (*((volatile unsigned int*)(0x422B900CUL))) +#define bM4_TMRA4_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B9010UL))) +#define bM4_TMRA4_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B9014UL))) +#define bM4_TMRA4_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B9018UL))) +#define bM4_TMRA4_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B901CUL))) +#define bM4_TMRA4_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B9030UL))) +#define bM4_TMRA4_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B9034UL))) +#define bM4_TMRA4_BCSTR_OVFF (*((volatile unsigned int*)(0x422B9038UL))) +#define bM4_TMRA4_BCSTR_UDFF (*((volatile unsigned int*)(0x422B903CUL))) +#define bM4_TMRA4_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B9080UL))) +#define bM4_TMRA4_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B9084UL))) +#define bM4_TMRA4_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B9088UL))) +#define bM4_TMRA4_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B9090UL))) +#define bM4_TMRA4_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B9094UL))) +#define bM4_TMRA4_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B9098UL))) +#define bM4_TMRA4_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B90A0UL))) +#define bM4_TMRA4_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B90A4UL))) +#define bM4_TMRA4_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B90A8UL))) +#define bM4_TMRA4_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B90B0UL))) +#define bM4_TMRA4_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B90B4UL))) +#define bM4_TMRA4_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B90B8UL))) +#define bM4_TMRA4_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B90BCUL))) +#define bM4_TMRA4_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B9100UL))) +#define bM4_TMRA4_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B9104UL))) +#define bM4_TMRA4_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B9108UL))) +#define bM4_TMRA4_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B910CUL))) +#define bM4_TMRA4_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B9110UL))) +#define bM4_TMRA4_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B9114UL))) +#define bM4_TMRA4_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B9118UL))) +#define bM4_TMRA4_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B911CUL))) +#define bM4_TMRA4_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B9120UL))) +#define bM4_TMRA4_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B9124UL))) +#define bM4_TMRA4_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B9128UL))) +#define bM4_TMRA4_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B912CUL))) +#define bM4_TMRA4_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B9130UL))) +#define bM4_TMRA4_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B9180UL))) +#define bM4_TMRA4_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B9184UL))) +#define bM4_TMRA4_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B9188UL))) +#define bM4_TMRA4_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B918CUL))) +#define bM4_TMRA4_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B9190UL))) +#define bM4_TMRA4_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B9194UL))) +#define bM4_TMRA4_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B9198UL))) +#define bM4_TMRA4_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B919CUL))) +#define bM4_TMRA4_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B91A0UL))) +#define bM4_TMRA4_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B91A4UL))) +#define bM4_TMRA4_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B91A8UL))) +#define bM4_TMRA4_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B91ACUL))) +#define bM4_TMRA4_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B91B0UL))) +#define bM4_TMRA4_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B9200UL))) +#define bM4_TMRA4_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B9204UL))) +#define bM4_TMRA4_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B9208UL))) +#define bM4_TMRA4_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B920CUL))) +#define bM4_TMRA4_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B9210UL))) +#define bM4_TMRA4_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B9214UL))) +#define bM4_TMRA4_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B9218UL))) +#define bM4_TMRA4_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B921CUL))) +#define bM4_TMRA4_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B9280UL))) +#define bM4_TMRA4_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B9284UL))) +#define bM4_TMRA4_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B9288UL))) +#define bM4_TMRA4_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B928CUL))) +#define bM4_TMRA4_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B9290UL))) +#define bM4_TMRA4_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B9294UL))) +#define bM4_TMRA4_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B9298UL))) +#define bM4_TMRA4_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B929CUL))) +#define bM4_TMRA4_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B9300UL))) +#define bM4_TMRA4_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B9304UL))) +#define bM4_TMRA4_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B9308UL))) +#define bM4_TMRA4_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B9320UL))) +#define bM4_TMRA4_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B9324UL))) +#define bM4_TMRA4_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B9328UL))) +#define bM4_TMRA4_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B9330UL))) +#define bM4_TMRA4_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B9334UL))) +#define bM4_TMRA4_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B9338UL))) +#define bM4_TMRA4_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B9380UL))) +#define bM4_TMRA4_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B9384UL))) +#define bM4_TMRA4_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B9388UL))) +#define bM4_TMRA4_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B938CUL))) +#define bM4_TMRA4_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B9390UL))) +#define bM4_TMRA4_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B9394UL))) +#define bM4_TMRA4_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B9398UL))) +#define bM4_TMRA4_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B939CUL))) +#define bM4_TMRA4_BCONR1_BEN (*((volatile unsigned int*)(0x422B9800UL))) +#define bM4_TMRA4_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B9804UL))) +#define bM4_TMRA4_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B9808UL))) +#define bM4_TMRA4_BCONR2_BEN (*((volatile unsigned int*)(0x422B9900UL))) +#define bM4_TMRA4_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B9904UL))) +#define bM4_TMRA4_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B9908UL))) +#define bM4_TMRA4_BCONR3_BEN (*((volatile unsigned int*)(0x422B9A00UL))) +#define bM4_TMRA4_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B9A04UL))) +#define bM4_TMRA4_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B9A08UL))) +#define bM4_TMRA4_BCONR4_BEN (*((volatile unsigned int*)(0x422B9B00UL))) +#define bM4_TMRA4_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B9B04UL))) +#define bM4_TMRA4_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B9B08UL))) +#define bM4_TMRA4_CCONR1_CAPMD (*((volatile unsigned int*)(0x422BA000UL))) +#define bM4_TMRA4_CCONR1_HICP0 (*((volatile unsigned int*)(0x422BA010UL))) +#define bM4_TMRA4_CCONR1_HICP1 (*((volatile unsigned int*)(0x422BA014UL))) +#define bM4_TMRA4_CCONR1_HICP2 (*((volatile unsigned int*)(0x422BA018UL))) +#define bM4_TMRA4_CCONR1_HICP3 (*((volatile unsigned int*)(0x422BA020UL))) +#define bM4_TMRA4_CCONR1_HICP4 (*((volatile unsigned int*)(0x422BA024UL))) +#define bM4_TMRA4_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422BA030UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422BA034UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422BA038UL))) +#define bM4_TMRA4_CCONR2_CAPMD (*((volatile unsigned int*)(0x422BA080UL))) +#define bM4_TMRA4_CCONR2_HICP0 (*((volatile unsigned int*)(0x422BA090UL))) +#define bM4_TMRA4_CCONR2_HICP1 (*((volatile unsigned int*)(0x422BA094UL))) +#define bM4_TMRA4_CCONR2_HICP2 (*((volatile unsigned int*)(0x422BA098UL))) +#define bM4_TMRA4_CCONR2_HICP3 (*((volatile unsigned int*)(0x422BA0A0UL))) +#define bM4_TMRA4_CCONR2_HICP4 (*((volatile unsigned int*)(0x422BA0A4UL))) +#define bM4_TMRA4_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422BA0B0UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422BA0B4UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422BA0B8UL))) +#define bM4_TMRA4_CCONR3_CAPMD (*((volatile unsigned int*)(0x422BA100UL))) +#define bM4_TMRA4_CCONR3_HICP0 (*((volatile unsigned int*)(0x422BA110UL))) +#define bM4_TMRA4_CCONR3_HICP1 (*((volatile unsigned int*)(0x422BA114UL))) +#define bM4_TMRA4_CCONR3_HICP2 (*((volatile unsigned int*)(0x422BA118UL))) +#define bM4_TMRA4_CCONR3_HICP3 (*((volatile unsigned int*)(0x422BA120UL))) +#define bM4_TMRA4_CCONR3_HICP4 (*((volatile unsigned int*)(0x422BA124UL))) +#define bM4_TMRA4_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422BA130UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422BA134UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422BA138UL))) +#define bM4_TMRA4_CCONR4_CAPMD (*((volatile unsigned int*)(0x422BA180UL))) +#define bM4_TMRA4_CCONR4_HICP0 (*((volatile unsigned int*)(0x422BA190UL))) +#define bM4_TMRA4_CCONR4_HICP1 (*((volatile unsigned int*)(0x422BA194UL))) +#define bM4_TMRA4_CCONR4_HICP2 (*((volatile unsigned int*)(0x422BA198UL))) +#define bM4_TMRA4_CCONR4_HICP3 (*((volatile unsigned int*)(0x422BA1A0UL))) +#define bM4_TMRA4_CCONR4_HICP4 (*((volatile unsigned int*)(0x422BA1A4UL))) +#define bM4_TMRA4_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422BA1B0UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422BA1B4UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422BA1B8UL))) +#define bM4_TMRA4_CCONR5_CAPMD (*((volatile unsigned int*)(0x422BA200UL))) +#define bM4_TMRA4_CCONR5_HICP0 (*((volatile unsigned int*)(0x422BA210UL))) +#define bM4_TMRA4_CCONR5_HICP1 (*((volatile unsigned int*)(0x422BA214UL))) +#define bM4_TMRA4_CCONR5_HICP2 (*((volatile unsigned int*)(0x422BA218UL))) +#define bM4_TMRA4_CCONR5_HICP3 (*((volatile unsigned int*)(0x422BA220UL))) +#define bM4_TMRA4_CCONR5_HICP4 (*((volatile unsigned int*)(0x422BA224UL))) +#define bM4_TMRA4_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422BA230UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422BA234UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422BA238UL))) +#define bM4_TMRA4_CCONR6_CAPMD (*((volatile unsigned int*)(0x422BA280UL))) +#define bM4_TMRA4_CCONR6_HICP0 (*((volatile unsigned int*)(0x422BA290UL))) +#define bM4_TMRA4_CCONR6_HICP1 (*((volatile unsigned int*)(0x422BA294UL))) +#define bM4_TMRA4_CCONR6_HICP2 (*((volatile unsigned int*)(0x422BA298UL))) +#define bM4_TMRA4_CCONR6_HICP3 (*((volatile unsigned int*)(0x422BA2A0UL))) +#define bM4_TMRA4_CCONR6_HICP4 (*((volatile unsigned int*)(0x422BA2A4UL))) +#define bM4_TMRA4_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422BA2B0UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422BA2B4UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422BA2B8UL))) +#define bM4_TMRA4_CCONR7_CAPMD (*((volatile unsigned int*)(0x422BA300UL))) +#define bM4_TMRA4_CCONR7_HICP0 (*((volatile unsigned int*)(0x422BA310UL))) +#define bM4_TMRA4_CCONR7_HICP1 (*((volatile unsigned int*)(0x422BA314UL))) +#define bM4_TMRA4_CCONR7_HICP2 (*((volatile unsigned int*)(0x422BA318UL))) +#define bM4_TMRA4_CCONR7_HICP3 (*((volatile unsigned int*)(0x422BA320UL))) +#define bM4_TMRA4_CCONR7_HICP4 (*((volatile unsigned int*)(0x422BA324UL))) +#define bM4_TMRA4_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422BA330UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422BA334UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422BA338UL))) +#define bM4_TMRA4_CCONR8_CAPMD (*((volatile unsigned int*)(0x422BA380UL))) +#define bM4_TMRA4_CCONR8_HICP0 (*((volatile unsigned int*)(0x422BA390UL))) +#define bM4_TMRA4_CCONR8_HICP1 (*((volatile unsigned int*)(0x422BA394UL))) +#define bM4_TMRA4_CCONR8_HICP2 (*((volatile unsigned int*)(0x422BA398UL))) +#define bM4_TMRA4_CCONR8_HICP3 (*((volatile unsigned int*)(0x422BA3A0UL))) +#define bM4_TMRA4_CCONR8_HICP4 (*((volatile unsigned int*)(0x422BA3A4UL))) +#define bM4_TMRA4_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422BA3B0UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422BA3B4UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422BA3B8UL))) +#define bM4_TMRA4_PCONR1_STAC0 (*((volatile unsigned int*)(0x422BA800UL))) +#define bM4_TMRA4_PCONR1_STAC1 (*((volatile unsigned int*)(0x422BA804UL))) +#define bM4_TMRA4_PCONR1_STPC0 (*((volatile unsigned int*)(0x422BA808UL))) +#define bM4_TMRA4_PCONR1_STPC1 (*((volatile unsigned int*)(0x422BA80CUL))) +#define bM4_TMRA4_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422BA810UL))) +#define bM4_TMRA4_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422BA814UL))) +#define bM4_TMRA4_PCONR1_PERC0 (*((volatile unsigned int*)(0x422BA818UL))) +#define bM4_TMRA4_PCONR1_PERC1 (*((volatile unsigned int*)(0x422BA81CUL))) +#define bM4_TMRA4_PCONR1_FORC0 (*((volatile unsigned int*)(0x422BA820UL))) +#define bM4_TMRA4_PCONR1_FORC1 (*((volatile unsigned int*)(0x422BA824UL))) +#define bM4_TMRA4_PCONR1_OUTEN (*((volatile unsigned int*)(0x422BA830UL))) +#define bM4_TMRA4_PCONR2_STAC0 (*((volatile unsigned int*)(0x422BA880UL))) +#define bM4_TMRA4_PCONR2_STAC1 (*((volatile unsigned int*)(0x422BA884UL))) +#define bM4_TMRA4_PCONR2_STPC0 (*((volatile unsigned int*)(0x422BA888UL))) +#define bM4_TMRA4_PCONR2_STPC1 (*((volatile unsigned int*)(0x422BA88CUL))) +#define bM4_TMRA4_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422BA890UL))) +#define bM4_TMRA4_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422BA894UL))) +#define bM4_TMRA4_PCONR2_PERC0 (*((volatile unsigned int*)(0x422BA898UL))) +#define bM4_TMRA4_PCONR2_PERC1 (*((volatile unsigned int*)(0x422BA89CUL))) +#define bM4_TMRA4_PCONR2_FORC0 (*((volatile unsigned int*)(0x422BA8A0UL))) +#define bM4_TMRA4_PCONR2_FORC1 (*((volatile unsigned int*)(0x422BA8A4UL))) +#define bM4_TMRA4_PCONR2_OUTEN (*((volatile unsigned int*)(0x422BA8B0UL))) +#define bM4_TMRA4_PCONR3_STAC0 (*((volatile unsigned int*)(0x422BA900UL))) +#define bM4_TMRA4_PCONR3_STAC1 (*((volatile unsigned int*)(0x422BA904UL))) +#define bM4_TMRA4_PCONR3_STPC0 (*((volatile unsigned int*)(0x422BA908UL))) +#define bM4_TMRA4_PCONR3_STPC1 (*((volatile unsigned int*)(0x422BA90CUL))) +#define bM4_TMRA4_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422BA910UL))) +#define bM4_TMRA4_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422BA914UL))) +#define bM4_TMRA4_PCONR3_PERC0 (*((volatile unsigned int*)(0x422BA918UL))) +#define bM4_TMRA4_PCONR3_PERC1 (*((volatile unsigned int*)(0x422BA91CUL))) +#define bM4_TMRA4_PCONR3_FORC0 (*((volatile unsigned int*)(0x422BA920UL))) +#define bM4_TMRA4_PCONR3_FORC1 (*((volatile unsigned int*)(0x422BA924UL))) +#define bM4_TMRA4_PCONR3_OUTEN (*((volatile unsigned int*)(0x422BA930UL))) +#define bM4_TMRA4_PCONR4_STAC0 (*((volatile unsigned int*)(0x422BA980UL))) +#define bM4_TMRA4_PCONR4_STAC1 (*((volatile unsigned int*)(0x422BA984UL))) +#define bM4_TMRA4_PCONR4_STPC0 (*((volatile unsigned int*)(0x422BA988UL))) +#define bM4_TMRA4_PCONR4_STPC1 (*((volatile unsigned int*)(0x422BA98CUL))) +#define bM4_TMRA4_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422BA990UL))) +#define bM4_TMRA4_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422BA994UL))) +#define bM4_TMRA4_PCONR4_PERC0 (*((volatile unsigned int*)(0x422BA998UL))) +#define bM4_TMRA4_PCONR4_PERC1 (*((volatile unsigned int*)(0x422BA99CUL))) +#define bM4_TMRA4_PCONR4_FORC0 (*((volatile unsigned int*)(0x422BA9A0UL))) +#define bM4_TMRA4_PCONR4_FORC1 (*((volatile unsigned int*)(0x422BA9A4UL))) +#define bM4_TMRA4_PCONR4_OUTEN (*((volatile unsigned int*)(0x422BA9B0UL))) +#define bM4_TMRA4_PCONR5_STAC0 (*((volatile unsigned int*)(0x422BAA00UL))) +#define bM4_TMRA4_PCONR5_STAC1 (*((volatile unsigned int*)(0x422BAA04UL))) +#define bM4_TMRA4_PCONR5_STPC0 (*((volatile unsigned int*)(0x422BAA08UL))) +#define bM4_TMRA4_PCONR5_STPC1 (*((volatile unsigned int*)(0x422BAA0CUL))) +#define bM4_TMRA4_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422BAA10UL))) +#define bM4_TMRA4_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422BAA14UL))) +#define bM4_TMRA4_PCONR5_PERC0 (*((volatile unsigned int*)(0x422BAA18UL))) +#define bM4_TMRA4_PCONR5_PERC1 (*((volatile unsigned int*)(0x422BAA1CUL))) +#define bM4_TMRA4_PCONR5_FORC0 (*((volatile unsigned int*)(0x422BAA20UL))) +#define bM4_TMRA4_PCONR5_FORC1 (*((volatile unsigned int*)(0x422BAA24UL))) +#define bM4_TMRA4_PCONR5_OUTEN (*((volatile unsigned int*)(0x422BAA30UL))) +#define bM4_TMRA4_PCONR6_STAC0 (*((volatile unsigned int*)(0x422BAA80UL))) +#define bM4_TMRA4_PCONR6_STAC1 (*((volatile unsigned int*)(0x422BAA84UL))) +#define bM4_TMRA4_PCONR6_STPC0 (*((volatile unsigned int*)(0x422BAA88UL))) +#define bM4_TMRA4_PCONR6_STPC1 (*((volatile unsigned int*)(0x422BAA8CUL))) +#define bM4_TMRA4_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422BAA90UL))) +#define bM4_TMRA4_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422BAA94UL))) +#define bM4_TMRA4_PCONR6_PERC0 (*((volatile unsigned int*)(0x422BAA98UL))) +#define bM4_TMRA4_PCONR6_PERC1 (*((volatile unsigned int*)(0x422BAA9CUL))) +#define bM4_TMRA4_PCONR6_FORC0 (*((volatile unsigned int*)(0x422BAAA0UL))) +#define bM4_TMRA4_PCONR6_FORC1 (*((volatile unsigned int*)(0x422BAAA4UL))) +#define bM4_TMRA4_PCONR6_OUTEN (*((volatile unsigned int*)(0x422BAAB0UL))) +#define bM4_TMRA4_PCONR7_STAC0 (*((volatile unsigned int*)(0x422BAB00UL))) +#define bM4_TMRA4_PCONR7_STAC1 (*((volatile unsigned int*)(0x422BAB04UL))) +#define bM4_TMRA4_PCONR7_STPC0 (*((volatile unsigned int*)(0x422BAB08UL))) +#define bM4_TMRA4_PCONR7_STPC1 (*((volatile unsigned int*)(0x422BAB0CUL))) +#define bM4_TMRA4_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422BAB10UL))) +#define bM4_TMRA4_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422BAB14UL))) +#define bM4_TMRA4_PCONR7_PERC0 (*((volatile unsigned int*)(0x422BAB18UL))) +#define bM4_TMRA4_PCONR7_PERC1 (*((volatile unsigned int*)(0x422BAB1CUL))) +#define bM4_TMRA4_PCONR7_FORC0 (*((volatile unsigned int*)(0x422BAB20UL))) +#define bM4_TMRA4_PCONR7_FORC1 (*((volatile unsigned int*)(0x422BAB24UL))) +#define bM4_TMRA4_PCONR7_OUTEN (*((volatile unsigned int*)(0x422BAB30UL))) +#define bM4_TMRA4_PCONR8_STAC0 (*((volatile unsigned int*)(0x422BAB80UL))) +#define bM4_TMRA4_PCONR8_STAC1 (*((volatile unsigned int*)(0x422BAB84UL))) +#define bM4_TMRA4_PCONR8_STPC0 (*((volatile unsigned int*)(0x422BAB88UL))) +#define bM4_TMRA4_PCONR8_STPC1 (*((volatile unsigned int*)(0x422BAB8CUL))) +#define bM4_TMRA4_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422BAB90UL))) +#define bM4_TMRA4_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422BAB94UL))) +#define bM4_TMRA4_PCONR8_PERC0 (*((volatile unsigned int*)(0x422BAB98UL))) +#define bM4_TMRA4_PCONR8_PERC1 (*((volatile unsigned int*)(0x422BAB9CUL))) +#define bM4_TMRA4_PCONR8_FORC0 (*((volatile unsigned int*)(0x422BABA0UL))) +#define bM4_TMRA4_PCONR8_FORC1 (*((volatile unsigned int*)(0x422BABA4UL))) +#define bM4_TMRA4_PCONR8_OUTEN (*((volatile unsigned int*)(0x422BABB0UL))) +#define bM4_TMRA5_CNTER_CNT0 (*((volatile unsigned int*)(0x422C0000UL))) +#define bM4_TMRA5_CNTER_CNT1 (*((volatile unsigned int*)(0x422C0004UL))) +#define bM4_TMRA5_CNTER_CNT2 (*((volatile unsigned int*)(0x422C0008UL))) +#define bM4_TMRA5_CNTER_CNT3 (*((volatile unsigned int*)(0x422C000CUL))) +#define bM4_TMRA5_CNTER_CNT4 (*((volatile unsigned int*)(0x422C0010UL))) +#define bM4_TMRA5_CNTER_CNT5 (*((volatile unsigned int*)(0x422C0014UL))) +#define bM4_TMRA5_CNTER_CNT6 (*((volatile unsigned int*)(0x422C0018UL))) +#define bM4_TMRA5_CNTER_CNT7 (*((volatile unsigned int*)(0x422C001CUL))) +#define bM4_TMRA5_CNTER_CNT8 (*((volatile unsigned int*)(0x422C0020UL))) +#define bM4_TMRA5_CNTER_CNT9 (*((volatile unsigned int*)(0x422C0024UL))) +#define bM4_TMRA5_CNTER_CNT10 (*((volatile unsigned int*)(0x422C0028UL))) +#define bM4_TMRA5_CNTER_CNT11 (*((volatile unsigned int*)(0x422C002CUL))) +#define bM4_TMRA5_CNTER_CNT12 (*((volatile unsigned int*)(0x422C0030UL))) +#define bM4_TMRA5_CNTER_CNT13 (*((volatile unsigned int*)(0x422C0034UL))) +#define bM4_TMRA5_CNTER_CNT14 (*((volatile unsigned int*)(0x422C0038UL))) +#define bM4_TMRA5_CNTER_CNT15 (*((volatile unsigned int*)(0x422C003CUL))) +#define bM4_TMRA5_PERAR_PER0 (*((volatile unsigned int*)(0x422C0080UL))) +#define bM4_TMRA5_PERAR_PER1 (*((volatile unsigned int*)(0x422C0084UL))) +#define bM4_TMRA5_PERAR_PER2 (*((volatile unsigned int*)(0x422C0088UL))) +#define bM4_TMRA5_PERAR_PER3 (*((volatile unsigned int*)(0x422C008CUL))) +#define bM4_TMRA5_PERAR_PER4 (*((volatile unsigned int*)(0x422C0090UL))) +#define bM4_TMRA5_PERAR_PER5 (*((volatile unsigned int*)(0x422C0094UL))) +#define bM4_TMRA5_PERAR_PER6 (*((volatile unsigned int*)(0x422C0098UL))) +#define bM4_TMRA5_PERAR_PER7 (*((volatile unsigned int*)(0x422C009CUL))) +#define bM4_TMRA5_PERAR_PER8 (*((volatile unsigned int*)(0x422C00A0UL))) +#define bM4_TMRA5_PERAR_PER9 (*((volatile unsigned int*)(0x422C00A4UL))) +#define bM4_TMRA5_PERAR_PER10 (*((volatile unsigned int*)(0x422C00A8UL))) +#define bM4_TMRA5_PERAR_PER11 (*((volatile unsigned int*)(0x422C00ACUL))) +#define bM4_TMRA5_PERAR_PER12 (*((volatile unsigned int*)(0x422C00B0UL))) +#define bM4_TMRA5_PERAR_PER13 (*((volatile unsigned int*)(0x422C00B4UL))) +#define bM4_TMRA5_PERAR_PER14 (*((volatile unsigned int*)(0x422C00B8UL))) +#define bM4_TMRA5_PERAR_PER15 (*((volatile unsigned int*)(0x422C00BCUL))) +#define bM4_TMRA5_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C0800UL))) +#define bM4_TMRA5_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C0804UL))) +#define bM4_TMRA5_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C0808UL))) +#define bM4_TMRA5_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C080CUL))) +#define bM4_TMRA5_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C0810UL))) +#define bM4_TMRA5_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C0814UL))) +#define bM4_TMRA5_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C0818UL))) +#define bM4_TMRA5_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C081CUL))) +#define bM4_TMRA5_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C0820UL))) +#define bM4_TMRA5_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C0824UL))) +#define bM4_TMRA5_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C0828UL))) +#define bM4_TMRA5_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C082CUL))) +#define bM4_TMRA5_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C0830UL))) +#define bM4_TMRA5_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C0834UL))) +#define bM4_TMRA5_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C0838UL))) +#define bM4_TMRA5_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C083CUL))) +#define bM4_TMRA5_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C0880UL))) +#define bM4_TMRA5_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C0884UL))) +#define bM4_TMRA5_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C0888UL))) +#define bM4_TMRA5_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C088CUL))) +#define bM4_TMRA5_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C0890UL))) +#define bM4_TMRA5_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C0894UL))) +#define bM4_TMRA5_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C0898UL))) +#define bM4_TMRA5_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C089CUL))) +#define bM4_TMRA5_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C08A0UL))) +#define bM4_TMRA5_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C08A4UL))) +#define bM4_TMRA5_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C08A8UL))) +#define bM4_TMRA5_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C08ACUL))) +#define bM4_TMRA5_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C08B0UL))) +#define bM4_TMRA5_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C08B4UL))) +#define bM4_TMRA5_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C08B8UL))) +#define bM4_TMRA5_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C08BCUL))) +#define bM4_TMRA5_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C0900UL))) +#define bM4_TMRA5_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C0904UL))) +#define bM4_TMRA5_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C0908UL))) +#define bM4_TMRA5_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C090CUL))) +#define bM4_TMRA5_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C0910UL))) +#define bM4_TMRA5_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C0914UL))) +#define bM4_TMRA5_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C0918UL))) +#define bM4_TMRA5_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C091CUL))) +#define bM4_TMRA5_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C0920UL))) +#define bM4_TMRA5_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C0924UL))) +#define bM4_TMRA5_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C0928UL))) +#define bM4_TMRA5_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C092CUL))) +#define bM4_TMRA5_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C0930UL))) +#define bM4_TMRA5_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C0934UL))) +#define bM4_TMRA5_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C0938UL))) +#define bM4_TMRA5_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C093CUL))) +#define bM4_TMRA5_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C0980UL))) +#define bM4_TMRA5_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C0984UL))) +#define bM4_TMRA5_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C0988UL))) +#define bM4_TMRA5_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C098CUL))) +#define bM4_TMRA5_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C0990UL))) +#define bM4_TMRA5_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C0994UL))) +#define bM4_TMRA5_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C0998UL))) +#define bM4_TMRA5_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C099CUL))) +#define bM4_TMRA5_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C09A0UL))) +#define bM4_TMRA5_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C09A4UL))) +#define bM4_TMRA5_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C09A8UL))) +#define bM4_TMRA5_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C09ACUL))) +#define bM4_TMRA5_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C09B0UL))) +#define bM4_TMRA5_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C09B4UL))) +#define bM4_TMRA5_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C09B8UL))) +#define bM4_TMRA5_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C09BCUL))) +#define bM4_TMRA5_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C0A00UL))) +#define bM4_TMRA5_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C0A04UL))) +#define bM4_TMRA5_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C0A08UL))) +#define bM4_TMRA5_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C0A0CUL))) +#define bM4_TMRA5_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C0A10UL))) +#define bM4_TMRA5_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C0A14UL))) +#define bM4_TMRA5_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C0A18UL))) +#define bM4_TMRA5_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C0A1CUL))) +#define bM4_TMRA5_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C0A20UL))) +#define bM4_TMRA5_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C0A24UL))) +#define bM4_TMRA5_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C0A28UL))) +#define bM4_TMRA5_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C0A2CUL))) +#define bM4_TMRA5_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C0A30UL))) +#define bM4_TMRA5_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C0A34UL))) +#define bM4_TMRA5_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C0A38UL))) +#define bM4_TMRA5_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C0A3CUL))) +#define bM4_TMRA5_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C0A80UL))) +#define bM4_TMRA5_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C0A84UL))) +#define bM4_TMRA5_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C0A88UL))) +#define bM4_TMRA5_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C0A8CUL))) +#define bM4_TMRA5_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C0A90UL))) +#define bM4_TMRA5_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C0A94UL))) +#define bM4_TMRA5_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C0A98UL))) +#define bM4_TMRA5_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C0A9CUL))) +#define bM4_TMRA5_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C0AA0UL))) +#define bM4_TMRA5_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C0AA4UL))) +#define bM4_TMRA5_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C0AA8UL))) +#define bM4_TMRA5_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C0AACUL))) +#define bM4_TMRA5_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C0AB0UL))) +#define bM4_TMRA5_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C0AB4UL))) +#define bM4_TMRA5_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C0AB8UL))) +#define bM4_TMRA5_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C0ABCUL))) +#define bM4_TMRA5_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C0B00UL))) +#define bM4_TMRA5_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C0B04UL))) +#define bM4_TMRA5_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C0B08UL))) +#define bM4_TMRA5_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C0B0CUL))) +#define bM4_TMRA5_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C0B10UL))) +#define bM4_TMRA5_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C0B14UL))) +#define bM4_TMRA5_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C0B18UL))) +#define bM4_TMRA5_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C0B1CUL))) +#define bM4_TMRA5_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C0B20UL))) +#define bM4_TMRA5_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C0B24UL))) +#define bM4_TMRA5_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C0B28UL))) +#define bM4_TMRA5_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C0B2CUL))) +#define bM4_TMRA5_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C0B30UL))) +#define bM4_TMRA5_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C0B34UL))) +#define bM4_TMRA5_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C0B38UL))) +#define bM4_TMRA5_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C0B3CUL))) +#define bM4_TMRA5_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C0B80UL))) +#define bM4_TMRA5_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C0B84UL))) +#define bM4_TMRA5_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C0B88UL))) +#define bM4_TMRA5_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C0B8CUL))) +#define bM4_TMRA5_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C0B90UL))) +#define bM4_TMRA5_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C0B94UL))) +#define bM4_TMRA5_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C0B98UL))) +#define bM4_TMRA5_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C0B9CUL))) +#define bM4_TMRA5_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C0BA0UL))) +#define bM4_TMRA5_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C0BA4UL))) +#define bM4_TMRA5_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C0BA8UL))) +#define bM4_TMRA5_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C0BACUL))) +#define bM4_TMRA5_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C0BB0UL))) +#define bM4_TMRA5_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C0BB4UL))) +#define bM4_TMRA5_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C0BB8UL))) +#define bM4_TMRA5_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C0BBCUL))) +#define bM4_TMRA5_BCSTR_START (*((volatile unsigned int*)(0x422C1000UL))) +#define bM4_TMRA5_BCSTR_DIR (*((volatile unsigned int*)(0x422C1004UL))) +#define bM4_TMRA5_BCSTR_MODE (*((volatile unsigned int*)(0x422C1008UL))) +#define bM4_TMRA5_BCSTR_SYNST (*((volatile unsigned int*)(0x422C100CUL))) +#define bM4_TMRA5_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C1010UL))) +#define bM4_TMRA5_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C1014UL))) +#define bM4_TMRA5_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C1018UL))) +#define bM4_TMRA5_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C101CUL))) +#define bM4_TMRA5_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C1030UL))) +#define bM4_TMRA5_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C1034UL))) +#define bM4_TMRA5_BCSTR_OVFF (*((volatile unsigned int*)(0x422C1038UL))) +#define bM4_TMRA5_BCSTR_UDFF (*((volatile unsigned int*)(0x422C103CUL))) +#define bM4_TMRA5_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C1080UL))) +#define bM4_TMRA5_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C1084UL))) +#define bM4_TMRA5_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C1088UL))) +#define bM4_TMRA5_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C1090UL))) +#define bM4_TMRA5_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C1094UL))) +#define bM4_TMRA5_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C1098UL))) +#define bM4_TMRA5_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C10A0UL))) +#define bM4_TMRA5_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C10A4UL))) +#define bM4_TMRA5_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C10A8UL))) +#define bM4_TMRA5_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C10B0UL))) +#define bM4_TMRA5_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C10B4UL))) +#define bM4_TMRA5_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C10B8UL))) +#define bM4_TMRA5_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C10BCUL))) +#define bM4_TMRA5_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C1100UL))) +#define bM4_TMRA5_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C1104UL))) +#define bM4_TMRA5_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C1108UL))) +#define bM4_TMRA5_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C110CUL))) +#define bM4_TMRA5_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C1110UL))) +#define bM4_TMRA5_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C1114UL))) +#define bM4_TMRA5_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C1118UL))) +#define bM4_TMRA5_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C111CUL))) +#define bM4_TMRA5_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C1120UL))) +#define bM4_TMRA5_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C1124UL))) +#define bM4_TMRA5_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C1128UL))) +#define bM4_TMRA5_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C112CUL))) +#define bM4_TMRA5_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C1130UL))) +#define bM4_TMRA5_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C1180UL))) +#define bM4_TMRA5_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C1184UL))) +#define bM4_TMRA5_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C1188UL))) +#define bM4_TMRA5_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C118CUL))) +#define bM4_TMRA5_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C1190UL))) +#define bM4_TMRA5_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C1194UL))) +#define bM4_TMRA5_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C1198UL))) +#define bM4_TMRA5_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C119CUL))) +#define bM4_TMRA5_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C11A0UL))) +#define bM4_TMRA5_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C11A4UL))) +#define bM4_TMRA5_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C11A8UL))) +#define bM4_TMRA5_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C11ACUL))) +#define bM4_TMRA5_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C11B0UL))) +#define bM4_TMRA5_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C1200UL))) +#define bM4_TMRA5_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C1204UL))) +#define bM4_TMRA5_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C1208UL))) +#define bM4_TMRA5_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C120CUL))) +#define bM4_TMRA5_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C1210UL))) +#define bM4_TMRA5_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C1214UL))) +#define bM4_TMRA5_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C1218UL))) +#define bM4_TMRA5_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C121CUL))) +#define bM4_TMRA5_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C1280UL))) +#define bM4_TMRA5_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C1284UL))) +#define bM4_TMRA5_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C1288UL))) +#define bM4_TMRA5_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C128CUL))) +#define bM4_TMRA5_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C1290UL))) +#define bM4_TMRA5_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C1294UL))) +#define bM4_TMRA5_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C1298UL))) +#define bM4_TMRA5_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C129CUL))) +#define bM4_TMRA5_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C1300UL))) +#define bM4_TMRA5_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C1304UL))) +#define bM4_TMRA5_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C1308UL))) +#define bM4_TMRA5_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C1320UL))) +#define bM4_TMRA5_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C1324UL))) +#define bM4_TMRA5_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C1328UL))) +#define bM4_TMRA5_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C1330UL))) +#define bM4_TMRA5_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C1334UL))) +#define bM4_TMRA5_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C1338UL))) +#define bM4_TMRA5_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C1380UL))) +#define bM4_TMRA5_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C1384UL))) +#define bM4_TMRA5_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C1388UL))) +#define bM4_TMRA5_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C138CUL))) +#define bM4_TMRA5_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C1390UL))) +#define bM4_TMRA5_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C1394UL))) +#define bM4_TMRA5_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C1398UL))) +#define bM4_TMRA5_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C139CUL))) +#define bM4_TMRA5_BCONR1_BEN (*((volatile unsigned int*)(0x422C1800UL))) +#define bM4_TMRA5_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C1804UL))) +#define bM4_TMRA5_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C1808UL))) +#define bM4_TMRA5_BCONR2_BEN (*((volatile unsigned int*)(0x422C1900UL))) +#define bM4_TMRA5_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C1904UL))) +#define bM4_TMRA5_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C1908UL))) +#define bM4_TMRA5_BCONR3_BEN (*((volatile unsigned int*)(0x422C1A00UL))) +#define bM4_TMRA5_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C1A04UL))) +#define bM4_TMRA5_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C1A08UL))) +#define bM4_TMRA5_BCONR4_BEN (*((volatile unsigned int*)(0x422C1B00UL))) +#define bM4_TMRA5_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C1B04UL))) +#define bM4_TMRA5_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C1B08UL))) +#define bM4_TMRA5_CCONR1_CAPMD (*((volatile unsigned int*)(0x422C2000UL))) +#define bM4_TMRA5_CCONR1_HICP0 (*((volatile unsigned int*)(0x422C2010UL))) +#define bM4_TMRA5_CCONR1_HICP1 (*((volatile unsigned int*)(0x422C2014UL))) +#define bM4_TMRA5_CCONR1_HICP2 (*((volatile unsigned int*)(0x422C2018UL))) +#define bM4_TMRA5_CCONR1_HICP3 (*((volatile unsigned int*)(0x422C2020UL))) +#define bM4_TMRA5_CCONR1_HICP4 (*((volatile unsigned int*)(0x422C2024UL))) +#define bM4_TMRA5_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422C2030UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422C2034UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422C2038UL))) +#define bM4_TMRA5_CCONR2_CAPMD (*((volatile unsigned int*)(0x422C2080UL))) +#define bM4_TMRA5_CCONR2_HICP0 (*((volatile unsigned int*)(0x422C2090UL))) +#define bM4_TMRA5_CCONR2_HICP1 (*((volatile unsigned int*)(0x422C2094UL))) +#define bM4_TMRA5_CCONR2_HICP2 (*((volatile unsigned int*)(0x422C2098UL))) +#define bM4_TMRA5_CCONR2_HICP3 (*((volatile unsigned int*)(0x422C20A0UL))) +#define bM4_TMRA5_CCONR2_HICP4 (*((volatile unsigned int*)(0x422C20A4UL))) +#define bM4_TMRA5_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422C20B0UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422C20B4UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422C20B8UL))) +#define bM4_TMRA5_CCONR3_CAPMD (*((volatile unsigned int*)(0x422C2100UL))) +#define bM4_TMRA5_CCONR3_HICP0 (*((volatile unsigned int*)(0x422C2110UL))) +#define bM4_TMRA5_CCONR3_HICP1 (*((volatile unsigned int*)(0x422C2114UL))) +#define bM4_TMRA5_CCONR3_HICP2 (*((volatile unsigned int*)(0x422C2118UL))) +#define bM4_TMRA5_CCONR3_HICP3 (*((volatile unsigned int*)(0x422C2120UL))) +#define bM4_TMRA5_CCONR3_HICP4 (*((volatile unsigned int*)(0x422C2124UL))) +#define bM4_TMRA5_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422C2130UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422C2134UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422C2138UL))) +#define bM4_TMRA5_CCONR4_CAPMD (*((volatile unsigned int*)(0x422C2180UL))) +#define bM4_TMRA5_CCONR4_HICP0 (*((volatile unsigned int*)(0x422C2190UL))) +#define bM4_TMRA5_CCONR4_HICP1 (*((volatile unsigned int*)(0x422C2194UL))) +#define bM4_TMRA5_CCONR4_HICP2 (*((volatile unsigned int*)(0x422C2198UL))) +#define bM4_TMRA5_CCONR4_HICP3 (*((volatile unsigned int*)(0x422C21A0UL))) +#define bM4_TMRA5_CCONR4_HICP4 (*((volatile unsigned int*)(0x422C21A4UL))) +#define bM4_TMRA5_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422C21B0UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422C21B4UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422C21B8UL))) +#define bM4_TMRA5_CCONR5_CAPMD (*((volatile unsigned int*)(0x422C2200UL))) +#define bM4_TMRA5_CCONR5_HICP0 (*((volatile unsigned int*)(0x422C2210UL))) +#define bM4_TMRA5_CCONR5_HICP1 (*((volatile unsigned int*)(0x422C2214UL))) +#define bM4_TMRA5_CCONR5_HICP2 (*((volatile unsigned int*)(0x422C2218UL))) +#define bM4_TMRA5_CCONR5_HICP3 (*((volatile unsigned int*)(0x422C2220UL))) +#define bM4_TMRA5_CCONR5_HICP4 (*((volatile unsigned int*)(0x422C2224UL))) +#define bM4_TMRA5_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422C2230UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422C2234UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422C2238UL))) +#define bM4_TMRA5_CCONR6_CAPMD (*((volatile unsigned int*)(0x422C2280UL))) +#define bM4_TMRA5_CCONR6_HICP0 (*((volatile unsigned int*)(0x422C2290UL))) +#define bM4_TMRA5_CCONR6_HICP1 (*((volatile unsigned int*)(0x422C2294UL))) +#define bM4_TMRA5_CCONR6_HICP2 (*((volatile unsigned int*)(0x422C2298UL))) +#define bM4_TMRA5_CCONR6_HICP3 (*((volatile unsigned int*)(0x422C22A0UL))) +#define bM4_TMRA5_CCONR6_HICP4 (*((volatile unsigned int*)(0x422C22A4UL))) +#define bM4_TMRA5_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422C22B0UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422C22B4UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422C22B8UL))) +#define bM4_TMRA5_CCONR7_CAPMD (*((volatile unsigned int*)(0x422C2300UL))) +#define bM4_TMRA5_CCONR7_HICP0 (*((volatile unsigned int*)(0x422C2310UL))) +#define bM4_TMRA5_CCONR7_HICP1 (*((volatile unsigned int*)(0x422C2314UL))) +#define bM4_TMRA5_CCONR7_HICP2 (*((volatile unsigned int*)(0x422C2318UL))) +#define bM4_TMRA5_CCONR7_HICP3 (*((volatile unsigned int*)(0x422C2320UL))) +#define bM4_TMRA5_CCONR7_HICP4 (*((volatile unsigned int*)(0x422C2324UL))) +#define bM4_TMRA5_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422C2330UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422C2334UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422C2338UL))) +#define bM4_TMRA5_CCONR8_CAPMD (*((volatile unsigned int*)(0x422C2380UL))) +#define bM4_TMRA5_CCONR8_HICP0 (*((volatile unsigned int*)(0x422C2390UL))) +#define bM4_TMRA5_CCONR8_HICP1 (*((volatile unsigned int*)(0x422C2394UL))) +#define bM4_TMRA5_CCONR8_HICP2 (*((volatile unsigned int*)(0x422C2398UL))) +#define bM4_TMRA5_CCONR8_HICP3 (*((volatile unsigned int*)(0x422C23A0UL))) +#define bM4_TMRA5_CCONR8_HICP4 (*((volatile unsigned int*)(0x422C23A4UL))) +#define bM4_TMRA5_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422C23B0UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422C23B4UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422C23B8UL))) +#define bM4_TMRA5_PCONR1_STAC0 (*((volatile unsigned int*)(0x422C2800UL))) +#define bM4_TMRA5_PCONR1_STAC1 (*((volatile unsigned int*)(0x422C2804UL))) +#define bM4_TMRA5_PCONR1_STPC0 (*((volatile unsigned int*)(0x422C2808UL))) +#define bM4_TMRA5_PCONR1_STPC1 (*((volatile unsigned int*)(0x422C280CUL))) +#define bM4_TMRA5_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422C2810UL))) +#define bM4_TMRA5_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422C2814UL))) +#define bM4_TMRA5_PCONR1_PERC0 (*((volatile unsigned int*)(0x422C2818UL))) +#define bM4_TMRA5_PCONR1_PERC1 (*((volatile unsigned int*)(0x422C281CUL))) +#define bM4_TMRA5_PCONR1_FORC0 (*((volatile unsigned int*)(0x422C2820UL))) +#define bM4_TMRA5_PCONR1_FORC1 (*((volatile unsigned int*)(0x422C2824UL))) +#define bM4_TMRA5_PCONR1_OUTEN (*((volatile unsigned int*)(0x422C2830UL))) +#define bM4_TMRA5_PCONR2_STAC0 (*((volatile unsigned int*)(0x422C2880UL))) +#define bM4_TMRA5_PCONR2_STAC1 (*((volatile unsigned int*)(0x422C2884UL))) +#define bM4_TMRA5_PCONR2_STPC0 (*((volatile unsigned int*)(0x422C2888UL))) +#define bM4_TMRA5_PCONR2_STPC1 (*((volatile unsigned int*)(0x422C288CUL))) +#define bM4_TMRA5_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422C2890UL))) +#define bM4_TMRA5_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422C2894UL))) +#define bM4_TMRA5_PCONR2_PERC0 (*((volatile unsigned int*)(0x422C2898UL))) +#define bM4_TMRA5_PCONR2_PERC1 (*((volatile unsigned int*)(0x422C289CUL))) +#define bM4_TMRA5_PCONR2_FORC0 (*((volatile unsigned int*)(0x422C28A0UL))) +#define bM4_TMRA5_PCONR2_FORC1 (*((volatile unsigned int*)(0x422C28A4UL))) +#define bM4_TMRA5_PCONR2_OUTEN (*((volatile unsigned int*)(0x422C28B0UL))) +#define bM4_TMRA5_PCONR3_STAC0 (*((volatile unsigned int*)(0x422C2900UL))) +#define bM4_TMRA5_PCONR3_STAC1 (*((volatile unsigned int*)(0x422C2904UL))) +#define bM4_TMRA5_PCONR3_STPC0 (*((volatile unsigned int*)(0x422C2908UL))) +#define bM4_TMRA5_PCONR3_STPC1 (*((volatile unsigned int*)(0x422C290CUL))) +#define bM4_TMRA5_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422C2910UL))) +#define bM4_TMRA5_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422C2914UL))) +#define bM4_TMRA5_PCONR3_PERC0 (*((volatile unsigned int*)(0x422C2918UL))) +#define bM4_TMRA5_PCONR3_PERC1 (*((volatile unsigned int*)(0x422C291CUL))) +#define bM4_TMRA5_PCONR3_FORC0 (*((volatile unsigned int*)(0x422C2920UL))) +#define bM4_TMRA5_PCONR3_FORC1 (*((volatile unsigned int*)(0x422C2924UL))) +#define bM4_TMRA5_PCONR3_OUTEN (*((volatile unsigned int*)(0x422C2930UL))) +#define bM4_TMRA5_PCONR4_STAC0 (*((volatile unsigned int*)(0x422C2980UL))) +#define bM4_TMRA5_PCONR4_STAC1 (*((volatile unsigned int*)(0x422C2984UL))) +#define bM4_TMRA5_PCONR4_STPC0 (*((volatile unsigned int*)(0x422C2988UL))) +#define bM4_TMRA5_PCONR4_STPC1 (*((volatile unsigned int*)(0x422C298CUL))) +#define bM4_TMRA5_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422C2990UL))) +#define bM4_TMRA5_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422C2994UL))) +#define bM4_TMRA5_PCONR4_PERC0 (*((volatile unsigned int*)(0x422C2998UL))) +#define bM4_TMRA5_PCONR4_PERC1 (*((volatile unsigned int*)(0x422C299CUL))) +#define bM4_TMRA5_PCONR4_FORC0 (*((volatile unsigned int*)(0x422C29A0UL))) +#define bM4_TMRA5_PCONR4_FORC1 (*((volatile unsigned int*)(0x422C29A4UL))) +#define bM4_TMRA5_PCONR4_OUTEN (*((volatile unsigned int*)(0x422C29B0UL))) +#define bM4_TMRA5_PCONR5_STAC0 (*((volatile unsigned int*)(0x422C2A00UL))) +#define bM4_TMRA5_PCONR5_STAC1 (*((volatile unsigned int*)(0x422C2A04UL))) +#define bM4_TMRA5_PCONR5_STPC0 (*((volatile unsigned int*)(0x422C2A08UL))) +#define bM4_TMRA5_PCONR5_STPC1 (*((volatile unsigned int*)(0x422C2A0CUL))) +#define bM4_TMRA5_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422C2A10UL))) +#define bM4_TMRA5_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422C2A14UL))) +#define bM4_TMRA5_PCONR5_PERC0 (*((volatile unsigned int*)(0x422C2A18UL))) +#define bM4_TMRA5_PCONR5_PERC1 (*((volatile unsigned int*)(0x422C2A1CUL))) +#define bM4_TMRA5_PCONR5_FORC0 (*((volatile unsigned int*)(0x422C2A20UL))) +#define bM4_TMRA5_PCONR5_FORC1 (*((volatile unsigned int*)(0x422C2A24UL))) +#define bM4_TMRA5_PCONR5_OUTEN (*((volatile unsigned int*)(0x422C2A30UL))) +#define bM4_TMRA5_PCONR6_STAC0 (*((volatile unsigned int*)(0x422C2A80UL))) +#define bM4_TMRA5_PCONR6_STAC1 (*((volatile unsigned int*)(0x422C2A84UL))) +#define bM4_TMRA5_PCONR6_STPC0 (*((volatile unsigned int*)(0x422C2A88UL))) +#define bM4_TMRA5_PCONR6_STPC1 (*((volatile unsigned int*)(0x422C2A8CUL))) +#define bM4_TMRA5_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422C2A90UL))) +#define bM4_TMRA5_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422C2A94UL))) +#define bM4_TMRA5_PCONR6_PERC0 (*((volatile unsigned int*)(0x422C2A98UL))) +#define bM4_TMRA5_PCONR6_PERC1 (*((volatile unsigned int*)(0x422C2A9CUL))) +#define bM4_TMRA5_PCONR6_FORC0 (*((volatile unsigned int*)(0x422C2AA0UL))) +#define bM4_TMRA5_PCONR6_FORC1 (*((volatile unsigned int*)(0x422C2AA4UL))) +#define bM4_TMRA5_PCONR6_OUTEN (*((volatile unsigned int*)(0x422C2AB0UL))) +#define bM4_TMRA5_PCONR7_STAC0 (*((volatile unsigned int*)(0x422C2B00UL))) +#define bM4_TMRA5_PCONR7_STAC1 (*((volatile unsigned int*)(0x422C2B04UL))) +#define bM4_TMRA5_PCONR7_STPC0 (*((volatile unsigned int*)(0x422C2B08UL))) +#define bM4_TMRA5_PCONR7_STPC1 (*((volatile unsigned int*)(0x422C2B0CUL))) +#define bM4_TMRA5_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422C2B10UL))) +#define bM4_TMRA5_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422C2B14UL))) +#define bM4_TMRA5_PCONR7_PERC0 (*((volatile unsigned int*)(0x422C2B18UL))) +#define bM4_TMRA5_PCONR7_PERC1 (*((volatile unsigned int*)(0x422C2B1CUL))) +#define bM4_TMRA5_PCONR7_FORC0 (*((volatile unsigned int*)(0x422C2B20UL))) +#define bM4_TMRA5_PCONR7_FORC1 (*((volatile unsigned int*)(0x422C2B24UL))) +#define bM4_TMRA5_PCONR7_OUTEN (*((volatile unsigned int*)(0x422C2B30UL))) +#define bM4_TMRA5_PCONR8_STAC0 (*((volatile unsigned int*)(0x422C2B80UL))) +#define bM4_TMRA5_PCONR8_STAC1 (*((volatile unsigned int*)(0x422C2B84UL))) +#define bM4_TMRA5_PCONR8_STPC0 (*((volatile unsigned int*)(0x422C2B88UL))) +#define bM4_TMRA5_PCONR8_STPC1 (*((volatile unsigned int*)(0x422C2B8CUL))) +#define bM4_TMRA5_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422C2B90UL))) +#define bM4_TMRA5_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422C2B94UL))) +#define bM4_TMRA5_PCONR8_PERC0 (*((volatile unsigned int*)(0x422C2B98UL))) +#define bM4_TMRA5_PCONR8_PERC1 (*((volatile unsigned int*)(0x422C2B9CUL))) +#define bM4_TMRA5_PCONR8_FORC0 (*((volatile unsigned int*)(0x422C2BA0UL))) +#define bM4_TMRA5_PCONR8_FORC1 (*((volatile unsigned int*)(0x422C2BA4UL))) +#define bM4_TMRA5_PCONR8_OUTEN (*((volatile unsigned int*)(0x422C2BB0UL))) +#define bM4_TMRA6_CNTER_CNT0 (*((volatile unsigned int*)(0x422C8000UL))) +#define bM4_TMRA6_CNTER_CNT1 (*((volatile unsigned int*)(0x422C8004UL))) +#define bM4_TMRA6_CNTER_CNT2 (*((volatile unsigned int*)(0x422C8008UL))) +#define bM4_TMRA6_CNTER_CNT3 (*((volatile unsigned int*)(0x422C800CUL))) +#define bM4_TMRA6_CNTER_CNT4 (*((volatile unsigned int*)(0x422C8010UL))) +#define bM4_TMRA6_CNTER_CNT5 (*((volatile unsigned int*)(0x422C8014UL))) +#define bM4_TMRA6_CNTER_CNT6 (*((volatile unsigned int*)(0x422C8018UL))) +#define bM4_TMRA6_CNTER_CNT7 (*((volatile unsigned int*)(0x422C801CUL))) +#define bM4_TMRA6_CNTER_CNT8 (*((volatile unsigned int*)(0x422C8020UL))) +#define bM4_TMRA6_CNTER_CNT9 (*((volatile unsigned int*)(0x422C8024UL))) +#define bM4_TMRA6_CNTER_CNT10 (*((volatile unsigned int*)(0x422C8028UL))) +#define bM4_TMRA6_CNTER_CNT11 (*((volatile unsigned int*)(0x422C802CUL))) +#define bM4_TMRA6_CNTER_CNT12 (*((volatile unsigned int*)(0x422C8030UL))) +#define bM4_TMRA6_CNTER_CNT13 (*((volatile unsigned int*)(0x422C8034UL))) +#define bM4_TMRA6_CNTER_CNT14 (*((volatile unsigned int*)(0x422C8038UL))) +#define bM4_TMRA6_CNTER_CNT15 (*((volatile unsigned int*)(0x422C803CUL))) +#define bM4_TMRA6_PERAR_PER0 (*((volatile unsigned int*)(0x422C8080UL))) +#define bM4_TMRA6_PERAR_PER1 (*((volatile unsigned int*)(0x422C8084UL))) +#define bM4_TMRA6_PERAR_PER2 (*((volatile unsigned int*)(0x422C8088UL))) +#define bM4_TMRA6_PERAR_PER3 (*((volatile unsigned int*)(0x422C808CUL))) +#define bM4_TMRA6_PERAR_PER4 (*((volatile unsigned int*)(0x422C8090UL))) +#define bM4_TMRA6_PERAR_PER5 (*((volatile unsigned int*)(0x422C8094UL))) +#define bM4_TMRA6_PERAR_PER6 (*((volatile unsigned int*)(0x422C8098UL))) +#define bM4_TMRA6_PERAR_PER7 (*((volatile unsigned int*)(0x422C809CUL))) +#define bM4_TMRA6_PERAR_PER8 (*((volatile unsigned int*)(0x422C80A0UL))) +#define bM4_TMRA6_PERAR_PER9 (*((volatile unsigned int*)(0x422C80A4UL))) +#define bM4_TMRA6_PERAR_PER10 (*((volatile unsigned int*)(0x422C80A8UL))) +#define bM4_TMRA6_PERAR_PER11 (*((volatile unsigned int*)(0x422C80ACUL))) +#define bM4_TMRA6_PERAR_PER12 (*((volatile unsigned int*)(0x422C80B0UL))) +#define bM4_TMRA6_PERAR_PER13 (*((volatile unsigned int*)(0x422C80B4UL))) +#define bM4_TMRA6_PERAR_PER14 (*((volatile unsigned int*)(0x422C80B8UL))) +#define bM4_TMRA6_PERAR_PER15 (*((volatile unsigned int*)(0x422C80BCUL))) +#define bM4_TMRA6_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C8800UL))) +#define bM4_TMRA6_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C8804UL))) +#define bM4_TMRA6_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C8808UL))) +#define bM4_TMRA6_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C880CUL))) +#define bM4_TMRA6_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C8810UL))) +#define bM4_TMRA6_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C8814UL))) +#define bM4_TMRA6_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C8818UL))) +#define bM4_TMRA6_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C881CUL))) +#define bM4_TMRA6_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C8820UL))) +#define bM4_TMRA6_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C8824UL))) +#define bM4_TMRA6_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C8828UL))) +#define bM4_TMRA6_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C882CUL))) +#define bM4_TMRA6_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C8830UL))) +#define bM4_TMRA6_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C8834UL))) +#define bM4_TMRA6_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C8838UL))) +#define bM4_TMRA6_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C883CUL))) +#define bM4_TMRA6_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C8880UL))) +#define bM4_TMRA6_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C8884UL))) +#define bM4_TMRA6_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C8888UL))) +#define bM4_TMRA6_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C888CUL))) +#define bM4_TMRA6_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C8890UL))) +#define bM4_TMRA6_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C8894UL))) +#define bM4_TMRA6_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C8898UL))) +#define bM4_TMRA6_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C889CUL))) +#define bM4_TMRA6_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C88A0UL))) +#define bM4_TMRA6_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C88A4UL))) +#define bM4_TMRA6_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C88A8UL))) +#define bM4_TMRA6_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C88ACUL))) +#define bM4_TMRA6_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C88B0UL))) +#define bM4_TMRA6_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C88B4UL))) +#define bM4_TMRA6_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C88B8UL))) +#define bM4_TMRA6_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C88BCUL))) +#define bM4_TMRA6_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C8900UL))) +#define bM4_TMRA6_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C8904UL))) +#define bM4_TMRA6_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C8908UL))) +#define bM4_TMRA6_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C890CUL))) +#define bM4_TMRA6_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C8910UL))) +#define bM4_TMRA6_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C8914UL))) +#define bM4_TMRA6_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C8918UL))) +#define bM4_TMRA6_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C891CUL))) +#define bM4_TMRA6_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C8920UL))) +#define bM4_TMRA6_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C8924UL))) +#define bM4_TMRA6_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C8928UL))) +#define bM4_TMRA6_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C892CUL))) +#define bM4_TMRA6_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C8930UL))) +#define bM4_TMRA6_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C8934UL))) +#define bM4_TMRA6_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C8938UL))) +#define bM4_TMRA6_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C893CUL))) +#define bM4_TMRA6_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C8980UL))) +#define bM4_TMRA6_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C8984UL))) +#define bM4_TMRA6_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C8988UL))) +#define bM4_TMRA6_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C898CUL))) +#define bM4_TMRA6_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C8990UL))) +#define bM4_TMRA6_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C8994UL))) +#define bM4_TMRA6_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C8998UL))) +#define bM4_TMRA6_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C899CUL))) +#define bM4_TMRA6_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C89A0UL))) +#define bM4_TMRA6_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C89A4UL))) +#define bM4_TMRA6_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C89A8UL))) +#define bM4_TMRA6_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C89ACUL))) +#define bM4_TMRA6_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C89B0UL))) +#define bM4_TMRA6_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C89B4UL))) +#define bM4_TMRA6_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C89B8UL))) +#define bM4_TMRA6_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C89BCUL))) +#define bM4_TMRA6_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C8A00UL))) +#define bM4_TMRA6_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C8A04UL))) +#define bM4_TMRA6_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C8A08UL))) +#define bM4_TMRA6_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C8A0CUL))) +#define bM4_TMRA6_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C8A10UL))) +#define bM4_TMRA6_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C8A14UL))) +#define bM4_TMRA6_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C8A18UL))) +#define bM4_TMRA6_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C8A1CUL))) +#define bM4_TMRA6_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C8A20UL))) +#define bM4_TMRA6_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C8A24UL))) +#define bM4_TMRA6_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C8A28UL))) +#define bM4_TMRA6_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C8A2CUL))) +#define bM4_TMRA6_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C8A30UL))) +#define bM4_TMRA6_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C8A34UL))) +#define bM4_TMRA6_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C8A38UL))) +#define bM4_TMRA6_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C8A3CUL))) +#define bM4_TMRA6_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C8A80UL))) +#define bM4_TMRA6_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C8A84UL))) +#define bM4_TMRA6_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C8A88UL))) +#define bM4_TMRA6_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C8A8CUL))) +#define bM4_TMRA6_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C8A90UL))) +#define bM4_TMRA6_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C8A94UL))) +#define bM4_TMRA6_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C8A98UL))) +#define bM4_TMRA6_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C8A9CUL))) +#define bM4_TMRA6_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C8AA0UL))) +#define bM4_TMRA6_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C8AA4UL))) +#define bM4_TMRA6_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C8AA8UL))) +#define bM4_TMRA6_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C8AACUL))) +#define bM4_TMRA6_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C8AB0UL))) +#define bM4_TMRA6_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C8AB4UL))) +#define bM4_TMRA6_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C8AB8UL))) +#define bM4_TMRA6_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C8ABCUL))) +#define bM4_TMRA6_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C8B00UL))) +#define bM4_TMRA6_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C8B04UL))) +#define bM4_TMRA6_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C8B08UL))) +#define bM4_TMRA6_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C8B0CUL))) +#define bM4_TMRA6_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C8B10UL))) +#define bM4_TMRA6_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C8B14UL))) +#define bM4_TMRA6_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C8B18UL))) +#define bM4_TMRA6_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C8B1CUL))) +#define bM4_TMRA6_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C8B20UL))) +#define bM4_TMRA6_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C8B24UL))) +#define bM4_TMRA6_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C8B28UL))) +#define bM4_TMRA6_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C8B2CUL))) +#define bM4_TMRA6_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C8B30UL))) +#define bM4_TMRA6_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C8B34UL))) +#define bM4_TMRA6_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C8B38UL))) +#define bM4_TMRA6_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C8B3CUL))) +#define bM4_TMRA6_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C8B80UL))) +#define bM4_TMRA6_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C8B84UL))) +#define bM4_TMRA6_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C8B88UL))) +#define bM4_TMRA6_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C8B8CUL))) +#define bM4_TMRA6_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C8B90UL))) +#define bM4_TMRA6_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C8B94UL))) +#define bM4_TMRA6_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C8B98UL))) +#define bM4_TMRA6_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C8B9CUL))) +#define bM4_TMRA6_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C8BA0UL))) +#define bM4_TMRA6_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C8BA4UL))) +#define bM4_TMRA6_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C8BA8UL))) +#define bM4_TMRA6_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C8BACUL))) +#define bM4_TMRA6_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C8BB0UL))) +#define bM4_TMRA6_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C8BB4UL))) +#define bM4_TMRA6_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C8BB8UL))) +#define bM4_TMRA6_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C8BBCUL))) +#define bM4_TMRA6_BCSTR_START (*((volatile unsigned int*)(0x422C9000UL))) +#define bM4_TMRA6_BCSTR_DIR (*((volatile unsigned int*)(0x422C9004UL))) +#define bM4_TMRA6_BCSTR_MODE (*((volatile unsigned int*)(0x422C9008UL))) +#define bM4_TMRA6_BCSTR_SYNST (*((volatile unsigned int*)(0x422C900CUL))) +#define bM4_TMRA6_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C9010UL))) +#define bM4_TMRA6_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C9014UL))) +#define bM4_TMRA6_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C9018UL))) +#define bM4_TMRA6_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C901CUL))) +#define bM4_TMRA6_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C9030UL))) +#define bM4_TMRA6_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C9034UL))) +#define bM4_TMRA6_BCSTR_OVFF (*((volatile unsigned int*)(0x422C9038UL))) +#define bM4_TMRA6_BCSTR_UDFF (*((volatile unsigned int*)(0x422C903CUL))) +#define bM4_TMRA6_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C9080UL))) +#define bM4_TMRA6_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C9084UL))) +#define bM4_TMRA6_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C9088UL))) +#define bM4_TMRA6_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C9090UL))) +#define bM4_TMRA6_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C9094UL))) +#define bM4_TMRA6_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C9098UL))) +#define bM4_TMRA6_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C90A0UL))) +#define bM4_TMRA6_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C90A4UL))) +#define bM4_TMRA6_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C90A8UL))) +#define bM4_TMRA6_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C90B0UL))) +#define bM4_TMRA6_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C90B4UL))) +#define bM4_TMRA6_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C90B8UL))) +#define bM4_TMRA6_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C90BCUL))) +#define bM4_TMRA6_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C9100UL))) +#define bM4_TMRA6_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C9104UL))) +#define bM4_TMRA6_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C9108UL))) +#define bM4_TMRA6_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C910CUL))) +#define bM4_TMRA6_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C9110UL))) +#define bM4_TMRA6_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C9114UL))) +#define bM4_TMRA6_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C9118UL))) +#define bM4_TMRA6_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C911CUL))) +#define bM4_TMRA6_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C9120UL))) +#define bM4_TMRA6_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C9124UL))) +#define bM4_TMRA6_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C9128UL))) +#define bM4_TMRA6_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C912CUL))) +#define bM4_TMRA6_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C9130UL))) +#define bM4_TMRA6_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C9180UL))) +#define bM4_TMRA6_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C9184UL))) +#define bM4_TMRA6_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C9188UL))) +#define bM4_TMRA6_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C918CUL))) +#define bM4_TMRA6_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C9190UL))) +#define bM4_TMRA6_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C9194UL))) +#define bM4_TMRA6_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C9198UL))) +#define bM4_TMRA6_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C919CUL))) +#define bM4_TMRA6_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C91A0UL))) +#define bM4_TMRA6_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C91A4UL))) +#define bM4_TMRA6_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C91A8UL))) +#define bM4_TMRA6_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C91ACUL))) +#define bM4_TMRA6_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C91B0UL))) +#define bM4_TMRA6_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C9200UL))) +#define bM4_TMRA6_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C9204UL))) +#define bM4_TMRA6_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C9208UL))) +#define bM4_TMRA6_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C920CUL))) +#define bM4_TMRA6_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C9210UL))) +#define bM4_TMRA6_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C9214UL))) +#define bM4_TMRA6_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C9218UL))) +#define bM4_TMRA6_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C921CUL))) +#define bM4_TMRA6_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C9280UL))) +#define bM4_TMRA6_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C9284UL))) +#define bM4_TMRA6_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C9288UL))) +#define bM4_TMRA6_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C928CUL))) +#define bM4_TMRA6_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C9290UL))) +#define bM4_TMRA6_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C9294UL))) +#define bM4_TMRA6_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C9298UL))) +#define bM4_TMRA6_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C929CUL))) +#define bM4_TMRA6_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C9300UL))) +#define bM4_TMRA6_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C9304UL))) +#define bM4_TMRA6_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C9308UL))) +#define bM4_TMRA6_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C9320UL))) +#define bM4_TMRA6_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C9324UL))) +#define bM4_TMRA6_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C9328UL))) +#define bM4_TMRA6_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C9330UL))) +#define bM4_TMRA6_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C9334UL))) +#define bM4_TMRA6_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C9338UL))) +#define bM4_TMRA6_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C9380UL))) +#define bM4_TMRA6_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C9384UL))) +#define bM4_TMRA6_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C9388UL))) +#define bM4_TMRA6_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C938CUL))) +#define bM4_TMRA6_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C9390UL))) +#define bM4_TMRA6_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C9394UL))) +#define bM4_TMRA6_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C9398UL))) +#define bM4_TMRA6_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C939CUL))) +#define bM4_TMRA6_BCONR1_BEN (*((volatile unsigned int*)(0x422C9800UL))) +#define bM4_TMRA6_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C9804UL))) +#define bM4_TMRA6_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C9808UL))) +#define bM4_TMRA6_BCONR2_BEN (*((volatile unsigned int*)(0x422C9900UL))) +#define bM4_TMRA6_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C9904UL))) +#define bM4_TMRA6_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C9908UL))) +#define bM4_TMRA6_BCONR3_BEN (*((volatile unsigned int*)(0x422C9A00UL))) +#define bM4_TMRA6_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C9A04UL))) +#define bM4_TMRA6_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C9A08UL))) +#define bM4_TMRA6_BCONR4_BEN (*((volatile unsigned int*)(0x422C9B00UL))) +#define bM4_TMRA6_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C9B04UL))) +#define bM4_TMRA6_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C9B08UL))) +#define bM4_TMRA6_CCONR1_CAPMD (*((volatile unsigned int*)(0x422CA000UL))) +#define bM4_TMRA6_CCONR1_HICP0 (*((volatile unsigned int*)(0x422CA010UL))) +#define bM4_TMRA6_CCONR1_HICP1 (*((volatile unsigned int*)(0x422CA014UL))) +#define bM4_TMRA6_CCONR1_HICP2 (*((volatile unsigned int*)(0x422CA018UL))) +#define bM4_TMRA6_CCONR1_HICP3 (*((volatile unsigned int*)(0x422CA020UL))) +#define bM4_TMRA6_CCONR1_HICP4 (*((volatile unsigned int*)(0x422CA024UL))) +#define bM4_TMRA6_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422CA030UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422CA034UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422CA038UL))) +#define bM4_TMRA6_CCONR2_CAPMD (*((volatile unsigned int*)(0x422CA080UL))) +#define bM4_TMRA6_CCONR2_HICP0 (*((volatile unsigned int*)(0x422CA090UL))) +#define bM4_TMRA6_CCONR2_HICP1 (*((volatile unsigned int*)(0x422CA094UL))) +#define bM4_TMRA6_CCONR2_HICP2 (*((volatile unsigned int*)(0x422CA098UL))) +#define bM4_TMRA6_CCONR2_HICP3 (*((volatile unsigned int*)(0x422CA0A0UL))) +#define bM4_TMRA6_CCONR2_HICP4 (*((volatile unsigned int*)(0x422CA0A4UL))) +#define bM4_TMRA6_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422CA0B0UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422CA0B4UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422CA0B8UL))) +#define bM4_TMRA6_CCONR3_CAPMD (*((volatile unsigned int*)(0x422CA100UL))) +#define bM4_TMRA6_CCONR3_HICP0 (*((volatile unsigned int*)(0x422CA110UL))) +#define bM4_TMRA6_CCONR3_HICP1 (*((volatile unsigned int*)(0x422CA114UL))) +#define bM4_TMRA6_CCONR3_HICP2 (*((volatile unsigned int*)(0x422CA118UL))) +#define bM4_TMRA6_CCONR3_HICP3 (*((volatile unsigned int*)(0x422CA120UL))) +#define bM4_TMRA6_CCONR3_HICP4 (*((volatile unsigned int*)(0x422CA124UL))) +#define bM4_TMRA6_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422CA130UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422CA134UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422CA138UL))) +#define bM4_TMRA6_CCONR4_CAPMD (*((volatile unsigned int*)(0x422CA180UL))) +#define bM4_TMRA6_CCONR4_HICP0 (*((volatile unsigned int*)(0x422CA190UL))) +#define bM4_TMRA6_CCONR4_HICP1 (*((volatile unsigned int*)(0x422CA194UL))) +#define bM4_TMRA6_CCONR4_HICP2 (*((volatile unsigned int*)(0x422CA198UL))) +#define bM4_TMRA6_CCONR4_HICP3 (*((volatile unsigned int*)(0x422CA1A0UL))) +#define bM4_TMRA6_CCONR4_HICP4 (*((volatile unsigned int*)(0x422CA1A4UL))) +#define bM4_TMRA6_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422CA1B0UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422CA1B4UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422CA1B8UL))) +#define bM4_TMRA6_CCONR5_CAPMD (*((volatile unsigned int*)(0x422CA200UL))) +#define bM4_TMRA6_CCONR5_HICP0 (*((volatile unsigned int*)(0x422CA210UL))) +#define bM4_TMRA6_CCONR5_HICP1 (*((volatile unsigned int*)(0x422CA214UL))) +#define bM4_TMRA6_CCONR5_HICP2 (*((volatile unsigned int*)(0x422CA218UL))) +#define bM4_TMRA6_CCONR5_HICP3 (*((volatile unsigned int*)(0x422CA220UL))) +#define bM4_TMRA6_CCONR5_HICP4 (*((volatile unsigned int*)(0x422CA224UL))) +#define bM4_TMRA6_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422CA230UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422CA234UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422CA238UL))) +#define bM4_TMRA6_CCONR6_CAPMD (*((volatile unsigned int*)(0x422CA280UL))) +#define bM4_TMRA6_CCONR6_HICP0 (*((volatile unsigned int*)(0x422CA290UL))) +#define bM4_TMRA6_CCONR6_HICP1 (*((volatile unsigned int*)(0x422CA294UL))) +#define bM4_TMRA6_CCONR6_HICP2 (*((volatile unsigned int*)(0x422CA298UL))) +#define bM4_TMRA6_CCONR6_HICP3 (*((volatile unsigned int*)(0x422CA2A0UL))) +#define bM4_TMRA6_CCONR6_HICP4 (*((volatile unsigned int*)(0x422CA2A4UL))) +#define bM4_TMRA6_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422CA2B0UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422CA2B4UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422CA2B8UL))) +#define bM4_TMRA6_CCONR7_CAPMD (*((volatile unsigned int*)(0x422CA300UL))) +#define bM4_TMRA6_CCONR7_HICP0 (*((volatile unsigned int*)(0x422CA310UL))) +#define bM4_TMRA6_CCONR7_HICP1 (*((volatile unsigned int*)(0x422CA314UL))) +#define bM4_TMRA6_CCONR7_HICP2 (*((volatile unsigned int*)(0x422CA318UL))) +#define bM4_TMRA6_CCONR7_HICP3 (*((volatile unsigned int*)(0x422CA320UL))) +#define bM4_TMRA6_CCONR7_HICP4 (*((volatile unsigned int*)(0x422CA324UL))) +#define bM4_TMRA6_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422CA330UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422CA334UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422CA338UL))) +#define bM4_TMRA6_CCONR8_CAPMD (*((volatile unsigned int*)(0x422CA380UL))) +#define bM4_TMRA6_CCONR8_HICP0 (*((volatile unsigned int*)(0x422CA390UL))) +#define bM4_TMRA6_CCONR8_HICP1 (*((volatile unsigned int*)(0x422CA394UL))) +#define bM4_TMRA6_CCONR8_HICP2 (*((volatile unsigned int*)(0x422CA398UL))) +#define bM4_TMRA6_CCONR8_HICP3 (*((volatile unsigned int*)(0x422CA3A0UL))) +#define bM4_TMRA6_CCONR8_HICP4 (*((volatile unsigned int*)(0x422CA3A4UL))) +#define bM4_TMRA6_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422CA3B0UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422CA3B4UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422CA3B8UL))) +#define bM4_TMRA6_PCONR1_STAC0 (*((volatile unsigned int*)(0x422CA800UL))) +#define bM4_TMRA6_PCONR1_STAC1 (*((volatile unsigned int*)(0x422CA804UL))) +#define bM4_TMRA6_PCONR1_STPC0 (*((volatile unsigned int*)(0x422CA808UL))) +#define bM4_TMRA6_PCONR1_STPC1 (*((volatile unsigned int*)(0x422CA80CUL))) +#define bM4_TMRA6_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422CA810UL))) +#define bM4_TMRA6_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422CA814UL))) +#define bM4_TMRA6_PCONR1_PERC0 (*((volatile unsigned int*)(0x422CA818UL))) +#define bM4_TMRA6_PCONR1_PERC1 (*((volatile unsigned int*)(0x422CA81CUL))) +#define bM4_TMRA6_PCONR1_FORC0 (*((volatile unsigned int*)(0x422CA820UL))) +#define bM4_TMRA6_PCONR1_FORC1 (*((volatile unsigned int*)(0x422CA824UL))) +#define bM4_TMRA6_PCONR1_OUTEN (*((volatile unsigned int*)(0x422CA830UL))) +#define bM4_TMRA6_PCONR2_STAC0 (*((volatile unsigned int*)(0x422CA880UL))) +#define bM4_TMRA6_PCONR2_STAC1 (*((volatile unsigned int*)(0x422CA884UL))) +#define bM4_TMRA6_PCONR2_STPC0 (*((volatile unsigned int*)(0x422CA888UL))) +#define bM4_TMRA6_PCONR2_STPC1 (*((volatile unsigned int*)(0x422CA88CUL))) +#define bM4_TMRA6_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422CA890UL))) +#define bM4_TMRA6_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422CA894UL))) +#define bM4_TMRA6_PCONR2_PERC0 (*((volatile unsigned int*)(0x422CA898UL))) +#define bM4_TMRA6_PCONR2_PERC1 (*((volatile unsigned int*)(0x422CA89CUL))) +#define bM4_TMRA6_PCONR2_FORC0 (*((volatile unsigned int*)(0x422CA8A0UL))) +#define bM4_TMRA6_PCONR2_FORC1 (*((volatile unsigned int*)(0x422CA8A4UL))) +#define bM4_TMRA6_PCONR2_OUTEN (*((volatile unsigned int*)(0x422CA8B0UL))) +#define bM4_TMRA6_PCONR3_STAC0 (*((volatile unsigned int*)(0x422CA900UL))) +#define bM4_TMRA6_PCONR3_STAC1 (*((volatile unsigned int*)(0x422CA904UL))) +#define bM4_TMRA6_PCONR3_STPC0 (*((volatile unsigned int*)(0x422CA908UL))) +#define bM4_TMRA6_PCONR3_STPC1 (*((volatile unsigned int*)(0x422CA90CUL))) +#define bM4_TMRA6_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422CA910UL))) +#define bM4_TMRA6_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422CA914UL))) +#define bM4_TMRA6_PCONR3_PERC0 (*((volatile unsigned int*)(0x422CA918UL))) +#define bM4_TMRA6_PCONR3_PERC1 (*((volatile unsigned int*)(0x422CA91CUL))) +#define bM4_TMRA6_PCONR3_FORC0 (*((volatile unsigned int*)(0x422CA920UL))) +#define bM4_TMRA6_PCONR3_FORC1 (*((volatile unsigned int*)(0x422CA924UL))) +#define bM4_TMRA6_PCONR3_OUTEN (*((volatile unsigned int*)(0x422CA930UL))) +#define bM4_TMRA6_PCONR4_STAC0 (*((volatile unsigned int*)(0x422CA980UL))) +#define bM4_TMRA6_PCONR4_STAC1 (*((volatile unsigned int*)(0x422CA984UL))) +#define bM4_TMRA6_PCONR4_STPC0 (*((volatile unsigned int*)(0x422CA988UL))) +#define bM4_TMRA6_PCONR4_STPC1 (*((volatile unsigned int*)(0x422CA98CUL))) +#define bM4_TMRA6_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422CA990UL))) +#define bM4_TMRA6_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422CA994UL))) +#define bM4_TMRA6_PCONR4_PERC0 (*((volatile unsigned int*)(0x422CA998UL))) +#define bM4_TMRA6_PCONR4_PERC1 (*((volatile unsigned int*)(0x422CA99CUL))) +#define bM4_TMRA6_PCONR4_FORC0 (*((volatile unsigned int*)(0x422CA9A0UL))) +#define bM4_TMRA6_PCONR4_FORC1 (*((volatile unsigned int*)(0x422CA9A4UL))) +#define bM4_TMRA6_PCONR4_OUTEN (*((volatile unsigned int*)(0x422CA9B0UL))) +#define bM4_TMRA6_PCONR5_STAC0 (*((volatile unsigned int*)(0x422CAA00UL))) +#define bM4_TMRA6_PCONR5_STAC1 (*((volatile unsigned int*)(0x422CAA04UL))) +#define bM4_TMRA6_PCONR5_STPC0 (*((volatile unsigned int*)(0x422CAA08UL))) +#define bM4_TMRA6_PCONR5_STPC1 (*((volatile unsigned int*)(0x422CAA0CUL))) +#define bM4_TMRA6_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422CAA10UL))) +#define bM4_TMRA6_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422CAA14UL))) +#define bM4_TMRA6_PCONR5_PERC0 (*((volatile unsigned int*)(0x422CAA18UL))) +#define bM4_TMRA6_PCONR5_PERC1 (*((volatile unsigned int*)(0x422CAA1CUL))) +#define bM4_TMRA6_PCONR5_FORC0 (*((volatile unsigned int*)(0x422CAA20UL))) +#define bM4_TMRA6_PCONR5_FORC1 (*((volatile unsigned int*)(0x422CAA24UL))) +#define bM4_TMRA6_PCONR5_OUTEN (*((volatile unsigned int*)(0x422CAA30UL))) +#define bM4_TMRA6_PCONR6_STAC0 (*((volatile unsigned int*)(0x422CAA80UL))) +#define bM4_TMRA6_PCONR6_STAC1 (*((volatile unsigned int*)(0x422CAA84UL))) +#define bM4_TMRA6_PCONR6_STPC0 (*((volatile unsigned int*)(0x422CAA88UL))) +#define bM4_TMRA6_PCONR6_STPC1 (*((volatile unsigned int*)(0x422CAA8CUL))) +#define bM4_TMRA6_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422CAA90UL))) +#define bM4_TMRA6_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422CAA94UL))) +#define bM4_TMRA6_PCONR6_PERC0 (*((volatile unsigned int*)(0x422CAA98UL))) +#define bM4_TMRA6_PCONR6_PERC1 (*((volatile unsigned int*)(0x422CAA9CUL))) +#define bM4_TMRA6_PCONR6_FORC0 (*((volatile unsigned int*)(0x422CAAA0UL))) +#define bM4_TMRA6_PCONR6_FORC1 (*((volatile unsigned int*)(0x422CAAA4UL))) +#define bM4_TMRA6_PCONR6_OUTEN (*((volatile unsigned int*)(0x422CAAB0UL))) +#define bM4_TMRA6_PCONR7_STAC0 (*((volatile unsigned int*)(0x422CAB00UL))) +#define bM4_TMRA6_PCONR7_STAC1 (*((volatile unsigned int*)(0x422CAB04UL))) +#define bM4_TMRA6_PCONR7_STPC0 (*((volatile unsigned int*)(0x422CAB08UL))) +#define bM4_TMRA6_PCONR7_STPC1 (*((volatile unsigned int*)(0x422CAB0CUL))) +#define bM4_TMRA6_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422CAB10UL))) +#define bM4_TMRA6_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422CAB14UL))) +#define bM4_TMRA6_PCONR7_PERC0 (*((volatile unsigned int*)(0x422CAB18UL))) +#define bM4_TMRA6_PCONR7_PERC1 (*((volatile unsigned int*)(0x422CAB1CUL))) +#define bM4_TMRA6_PCONR7_FORC0 (*((volatile unsigned int*)(0x422CAB20UL))) +#define bM4_TMRA6_PCONR7_FORC1 (*((volatile unsigned int*)(0x422CAB24UL))) +#define bM4_TMRA6_PCONR7_OUTEN (*((volatile unsigned int*)(0x422CAB30UL))) +#define bM4_TMRA6_PCONR8_STAC0 (*((volatile unsigned int*)(0x422CAB80UL))) +#define bM4_TMRA6_PCONR8_STAC1 (*((volatile unsigned int*)(0x422CAB84UL))) +#define bM4_TMRA6_PCONR8_STPC0 (*((volatile unsigned int*)(0x422CAB88UL))) +#define bM4_TMRA6_PCONR8_STPC1 (*((volatile unsigned int*)(0x422CAB8CUL))) +#define bM4_TMRA6_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422CAB90UL))) +#define bM4_TMRA6_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422CAB94UL))) +#define bM4_TMRA6_PCONR8_PERC0 (*((volatile unsigned int*)(0x422CAB98UL))) +#define bM4_TMRA6_PCONR8_PERC1 (*((volatile unsigned int*)(0x422CAB9CUL))) +#define bM4_TMRA6_PCONR8_FORC0 (*((volatile unsigned int*)(0x422CABA0UL))) +#define bM4_TMRA6_PCONR8_FORC1 (*((volatile unsigned int*)(0x422CABA4UL))) +#define bM4_TMRA6_PCONR8_OUTEN (*((volatile unsigned int*)(0x422CABB0UL))) +#define bM4_TRNG_CR_EN (*((volatile unsigned int*)(0x42820000UL))) +#define bM4_TRNG_CR_RUN (*((volatile unsigned int*)(0x42820004UL))) +#define bM4_TRNG_MR_LOAD (*((volatile unsigned int*)(0x42820080UL))) +#define bM4_TRNG_MR_CNT0 (*((volatile unsigned int*)(0x42820088UL))) +#define bM4_TRNG_MR_CNT1 (*((volatile unsigned int*)(0x4282008CUL))) +#define bM4_TRNG_MR_CNT2 (*((volatile unsigned int*)(0x42820090UL))) +#define bM4_USART1_SR_PE (*((volatile unsigned int*)(0x423A0000UL))) +#define bM4_USART1_SR_FE (*((volatile unsigned int*)(0x423A0004UL))) +#define bM4_USART1_SR_ORE (*((volatile unsigned int*)(0x423A000CUL))) +#define bM4_USART1_SR_RXNE (*((volatile unsigned int*)(0x423A0014UL))) +#define bM4_USART1_SR_TC (*((volatile unsigned int*)(0x423A0018UL))) +#define bM4_USART1_SR_TXE (*((volatile unsigned int*)(0x423A001CUL))) +#define bM4_USART1_SR_RTOF (*((volatile unsigned int*)(0x423A0020UL))) +#define bM4_USART1_SR_MPB (*((volatile unsigned int*)(0x423A0040UL))) +#define bM4_USART1_DR_TDR0 (*((volatile unsigned int*)(0x423A0080UL))) +#define bM4_USART1_DR_TDR1 (*((volatile unsigned int*)(0x423A0084UL))) +#define bM4_USART1_DR_TDR2 (*((volatile unsigned int*)(0x423A0088UL))) +#define bM4_USART1_DR_TDR3 (*((volatile unsigned int*)(0x423A008CUL))) +#define bM4_USART1_DR_TDR4 (*((volatile unsigned int*)(0x423A0090UL))) +#define bM4_USART1_DR_TDR5 (*((volatile unsigned int*)(0x423A0094UL))) +#define bM4_USART1_DR_TDR6 (*((volatile unsigned int*)(0x423A0098UL))) +#define bM4_USART1_DR_TDR7 (*((volatile unsigned int*)(0x423A009CUL))) +#define bM4_USART1_DR_TDR8 (*((volatile unsigned int*)(0x423A00A0UL))) +#define bM4_USART1_DR_MPID (*((volatile unsigned int*)(0x423A00A4UL))) +#define bM4_USART1_DR_RDR0 (*((volatile unsigned int*)(0x423A00C0UL))) +#define bM4_USART1_DR_RDR1 (*((volatile unsigned int*)(0x423A00C4UL))) +#define bM4_USART1_DR_RDR2 (*((volatile unsigned int*)(0x423A00C8UL))) +#define bM4_USART1_DR_RDR3 (*((volatile unsigned int*)(0x423A00CCUL))) +#define bM4_USART1_DR_RDR4 (*((volatile unsigned int*)(0x423A00D0UL))) +#define bM4_USART1_DR_RDR5 (*((volatile unsigned int*)(0x423A00D4UL))) +#define bM4_USART1_DR_RDR6 (*((volatile unsigned int*)(0x423A00D8UL))) +#define bM4_USART1_DR_RDR7 (*((volatile unsigned int*)(0x423A00DCUL))) +#define bM4_USART1_DR_RDR8 (*((volatile unsigned int*)(0x423A00E0UL))) +#define bM4_USART1_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A0100UL))) +#define bM4_USART1_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A0104UL))) +#define bM4_USART1_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A0108UL))) +#define bM4_USART1_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A010CUL))) +#define bM4_USART1_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A0110UL))) +#define bM4_USART1_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A0114UL))) +#define bM4_USART1_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A0118UL))) +#define bM4_USART1_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A0120UL))) +#define bM4_USART1_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A0124UL))) +#define bM4_USART1_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A0128UL))) +#define bM4_USART1_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A012CUL))) +#define bM4_USART1_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A0130UL))) +#define bM4_USART1_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A0134UL))) +#define bM4_USART1_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A0138UL))) +#define bM4_USART1_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A013CUL))) +#define bM4_USART1_CR1_RTOE (*((volatile unsigned int*)(0x423A0180UL))) +#define bM4_USART1_CR1_RTOIE (*((volatile unsigned int*)(0x423A0184UL))) +#define bM4_USART1_CR1_RE (*((volatile unsigned int*)(0x423A0188UL))) +#define bM4_USART1_CR1_TE (*((volatile unsigned int*)(0x423A018CUL))) +#define bM4_USART1_CR1_SLME (*((volatile unsigned int*)(0x423A0190UL))) +#define bM4_USART1_CR1_RIE (*((volatile unsigned int*)(0x423A0194UL))) +#define bM4_USART1_CR1_TCIE (*((volatile unsigned int*)(0x423A0198UL))) +#define bM4_USART1_CR1_TXEIE (*((volatile unsigned int*)(0x423A019CUL))) +#define bM4_USART1_CR1_PS (*((volatile unsigned int*)(0x423A01A4UL))) +#define bM4_USART1_CR1_PCE (*((volatile unsigned int*)(0x423A01A8UL))) +#define bM4_USART1_CR1_M (*((volatile unsigned int*)(0x423A01B0UL))) +#define bM4_USART1_CR1_OVER8 (*((volatile unsigned int*)(0x423A01BCUL))) +#define bM4_USART1_CR1_CPE (*((volatile unsigned int*)(0x423A01C0UL))) +#define bM4_USART1_CR1_CFE (*((volatile unsigned int*)(0x423A01C4UL))) +#define bM4_USART1_CR1_CORE (*((volatile unsigned int*)(0x423A01CCUL))) +#define bM4_USART1_CR1_CRTOF (*((volatile unsigned int*)(0x423A01D0UL))) +#define bM4_USART1_CR1_MS (*((volatile unsigned int*)(0x423A01E0UL))) +#define bM4_USART1_CR1_ML (*((volatile unsigned int*)(0x423A01F0UL))) +#define bM4_USART1_CR1_FBME (*((volatile unsigned int*)(0x423A01F4UL))) +#define bM4_USART1_CR1_NFE (*((volatile unsigned int*)(0x423A01F8UL))) +#define bM4_USART1_CR1_SBS (*((volatile unsigned int*)(0x423A01FCUL))) +#define bM4_USART1_CR2_MPE (*((volatile unsigned int*)(0x423A0200UL))) +#define bM4_USART1_CR2_CLKC0 (*((volatile unsigned int*)(0x423A022CUL))) +#define bM4_USART1_CR2_CLKC1 (*((volatile unsigned int*)(0x423A0230UL))) +#define bM4_USART1_CR2_STOP (*((volatile unsigned int*)(0x423A0234UL))) +#define bM4_USART1_CR3_SCEN (*((volatile unsigned int*)(0x423A0294UL))) +#define bM4_USART1_CR3_CTSE (*((volatile unsigned int*)(0x423A02A4UL))) +#define bM4_USART1_CR3_BCN0 (*((volatile unsigned int*)(0x423A02D4UL))) +#define bM4_USART1_CR3_BCN1 (*((volatile unsigned int*)(0x423A02D8UL))) +#define bM4_USART1_CR3_BCN2 (*((volatile unsigned int*)(0x423A02DCUL))) +#define bM4_USART1_PR_PSC0 (*((volatile unsigned int*)(0x423A0300UL))) +#define bM4_USART1_PR_PSC1 (*((volatile unsigned int*)(0x423A0304UL))) +#define bM4_USART2_SR_PE (*((volatile unsigned int*)(0x423A8000UL))) +#define bM4_USART2_SR_FE (*((volatile unsigned int*)(0x423A8004UL))) +#define bM4_USART2_SR_ORE (*((volatile unsigned int*)(0x423A800CUL))) +#define bM4_USART2_SR_RXNE (*((volatile unsigned int*)(0x423A8014UL))) +#define bM4_USART2_SR_TC (*((volatile unsigned int*)(0x423A8018UL))) +#define bM4_USART2_SR_TXE (*((volatile unsigned int*)(0x423A801CUL))) +#define bM4_USART2_SR_RTOF (*((volatile unsigned int*)(0x423A8020UL))) +#define bM4_USART2_SR_MPB (*((volatile unsigned int*)(0x423A8040UL))) +#define bM4_USART2_DR_TDR0 (*((volatile unsigned int*)(0x423A8080UL))) +#define bM4_USART2_DR_TDR1 (*((volatile unsigned int*)(0x423A8084UL))) +#define bM4_USART2_DR_TDR2 (*((volatile unsigned int*)(0x423A8088UL))) +#define bM4_USART2_DR_TDR3 (*((volatile unsigned int*)(0x423A808CUL))) +#define bM4_USART2_DR_TDR4 (*((volatile unsigned int*)(0x423A8090UL))) +#define bM4_USART2_DR_TDR5 (*((volatile unsigned int*)(0x423A8094UL))) +#define bM4_USART2_DR_TDR6 (*((volatile unsigned int*)(0x423A8098UL))) +#define bM4_USART2_DR_TDR7 (*((volatile unsigned int*)(0x423A809CUL))) +#define bM4_USART2_DR_TDR8 (*((volatile unsigned int*)(0x423A80A0UL))) +#define bM4_USART2_DR_MPID (*((volatile unsigned int*)(0x423A80A4UL))) +#define bM4_USART2_DR_RDR0 (*((volatile unsigned int*)(0x423A80C0UL))) +#define bM4_USART2_DR_RDR1 (*((volatile unsigned int*)(0x423A80C4UL))) +#define bM4_USART2_DR_RDR2 (*((volatile unsigned int*)(0x423A80C8UL))) +#define bM4_USART2_DR_RDR3 (*((volatile unsigned int*)(0x423A80CCUL))) +#define bM4_USART2_DR_RDR4 (*((volatile unsigned int*)(0x423A80D0UL))) +#define bM4_USART2_DR_RDR5 (*((volatile unsigned int*)(0x423A80D4UL))) +#define bM4_USART2_DR_RDR6 (*((volatile unsigned int*)(0x423A80D8UL))) +#define bM4_USART2_DR_RDR7 (*((volatile unsigned int*)(0x423A80DCUL))) +#define bM4_USART2_DR_RDR8 (*((volatile unsigned int*)(0x423A80E0UL))) +#define bM4_USART2_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A8100UL))) +#define bM4_USART2_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A8104UL))) +#define bM4_USART2_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A8108UL))) +#define bM4_USART2_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A810CUL))) +#define bM4_USART2_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A8110UL))) +#define bM4_USART2_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A8114UL))) +#define bM4_USART2_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A8118UL))) +#define bM4_USART2_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A8120UL))) +#define bM4_USART2_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A8124UL))) +#define bM4_USART2_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A8128UL))) +#define bM4_USART2_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A812CUL))) +#define bM4_USART2_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A8130UL))) +#define bM4_USART2_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A8134UL))) +#define bM4_USART2_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A8138UL))) +#define bM4_USART2_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A813CUL))) +#define bM4_USART2_CR1_RTOE (*((volatile unsigned int*)(0x423A8180UL))) +#define bM4_USART2_CR1_RTOIE (*((volatile unsigned int*)(0x423A8184UL))) +#define bM4_USART2_CR1_RE (*((volatile unsigned int*)(0x423A8188UL))) +#define bM4_USART2_CR1_TE (*((volatile unsigned int*)(0x423A818CUL))) +#define bM4_USART2_CR1_SLME (*((volatile unsigned int*)(0x423A8190UL))) +#define bM4_USART2_CR1_RIE (*((volatile unsigned int*)(0x423A8194UL))) +#define bM4_USART2_CR1_TCIE (*((volatile unsigned int*)(0x423A8198UL))) +#define bM4_USART2_CR1_TXEIE (*((volatile unsigned int*)(0x423A819CUL))) +#define bM4_USART2_CR1_PS (*((volatile unsigned int*)(0x423A81A4UL))) +#define bM4_USART2_CR1_PCE (*((volatile unsigned int*)(0x423A81A8UL))) +#define bM4_USART2_CR1_M (*((volatile unsigned int*)(0x423A81B0UL))) +#define bM4_USART2_CR1_OVER8 (*((volatile unsigned int*)(0x423A81BCUL))) +#define bM4_USART2_CR1_CPE (*((volatile unsigned int*)(0x423A81C0UL))) +#define bM4_USART2_CR1_CFE (*((volatile unsigned int*)(0x423A81C4UL))) +#define bM4_USART2_CR1_CORE (*((volatile unsigned int*)(0x423A81CCUL))) +#define bM4_USART2_CR1_CRTOF (*((volatile unsigned int*)(0x423A81D0UL))) +#define bM4_USART2_CR1_MS (*((volatile unsigned int*)(0x423A81E0UL))) +#define bM4_USART2_CR1_ML (*((volatile unsigned int*)(0x423A81F0UL))) +#define bM4_USART2_CR1_FBME (*((volatile unsigned int*)(0x423A81F4UL))) +#define bM4_USART2_CR1_NFE (*((volatile unsigned int*)(0x423A81F8UL))) +#define bM4_USART2_CR1_SBS (*((volatile unsigned int*)(0x423A81FCUL))) +#define bM4_USART2_CR2_MPE (*((volatile unsigned int*)(0x423A8200UL))) +#define bM4_USART2_CR2_CLKC0 (*((volatile unsigned int*)(0x423A822CUL))) +#define bM4_USART2_CR2_CLKC1 (*((volatile unsigned int*)(0x423A8230UL))) +#define bM4_USART2_CR2_STOP (*((volatile unsigned int*)(0x423A8234UL))) +#define bM4_USART2_CR3_SCEN (*((volatile unsigned int*)(0x423A8294UL))) +#define bM4_USART2_CR3_CTSE (*((volatile unsigned int*)(0x423A82A4UL))) +#define bM4_USART2_CR3_BCN0 (*((volatile unsigned int*)(0x423A82D4UL))) +#define bM4_USART2_CR3_BCN1 (*((volatile unsigned int*)(0x423A82D8UL))) +#define bM4_USART2_CR3_BCN2 (*((volatile unsigned int*)(0x423A82DCUL))) +#define bM4_USART2_PR_PSC0 (*((volatile unsigned int*)(0x423A8300UL))) +#define bM4_USART2_PR_PSC1 (*((volatile unsigned int*)(0x423A8304UL))) +#define bM4_USART3_SR_PE (*((volatile unsigned int*)(0x42420000UL))) +#define bM4_USART3_SR_FE (*((volatile unsigned int*)(0x42420004UL))) +#define bM4_USART3_SR_ORE (*((volatile unsigned int*)(0x4242000CUL))) +#define bM4_USART3_SR_RXNE (*((volatile unsigned int*)(0x42420014UL))) +#define bM4_USART3_SR_TC (*((volatile unsigned int*)(0x42420018UL))) +#define bM4_USART3_SR_TXE (*((volatile unsigned int*)(0x4242001CUL))) +#define bM4_USART3_SR_RTOF (*((volatile unsigned int*)(0x42420020UL))) +#define bM4_USART3_SR_MPB (*((volatile unsigned int*)(0x42420040UL))) +#define bM4_USART3_DR_TDR0 (*((volatile unsigned int*)(0x42420080UL))) +#define bM4_USART3_DR_TDR1 (*((volatile unsigned int*)(0x42420084UL))) +#define bM4_USART3_DR_TDR2 (*((volatile unsigned int*)(0x42420088UL))) +#define bM4_USART3_DR_TDR3 (*((volatile unsigned int*)(0x4242008CUL))) +#define bM4_USART3_DR_TDR4 (*((volatile unsigned int*)(0x42420090UL))) +#define bM4_USART3_DR_TDR5 (*((volatile unsigned int*)(0x42420094UL))) +#define bM4_USART3_DR_TDR6 (*((volatile unsigned int*)(0x42420098UL))) +#define bM4_USART3_DR_TDR7 (*((volatile unsigned int*)(0x4242009CUL))) +#define bM4_USART3_DR_TDR8 (*((volatile unsigned int*)(0x424200A0UL))) +#define bM4_USART3_DR_MPID (*((volatile unsigned int*)(0x424200A4UL))) +#define bM4_USART3_DR_RDR0 (*((volatile unsigned int*)(0x424200C0UL))) +#define bM4_USART3_DR_RDR1 (*((volatile unsigned int*)(0x424200C4UL))) +#define bM4_USART3_DR_RDR2 (*((volatile unsigned int*)(0x424200C8UL))) +#define bM4_USART3_DR_RDR3 (*((volatile unsigned int*)(0x424200CCUL))) +#define bM4_USART3_DR_RDR4 (*((volatile unsigned int*)(0x424200D0UL))) +#define bM4_USART3_DR_RDR5 (*((volatile unsigned int*)(0x424200D4UL))) +#define bM4_USART3_DR_RDR6 (*((volatile unsigned int*)(0x424200D8UL))) +#define bM4_USART3_DR_RDR7 (*((volatile unsigned int*)(0x424200DCUL))) +#define bM4_USART3_DR_RDR8 (*((volatile unsigned int*)(0x424200E0UL))) +#define bM4_USART3_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42420100UL))) +#define bM4_USART3_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42420104UL))) +#define bM4_USART3_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42420108UL))) +#define bM4_USART3_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242010CUL))) +#define bM4_USART3_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42420110UL))) +#define bM4_USART3_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42420114UL))) +#define bM4_USART3_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42420118UL))) +#define bM4_USART3_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42420120UL))) +#define bM4_USART3_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42420124UL))) +#define bM4_USART3_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42420128UL))) +#define bM4_USART3_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242012CUL))) +#define bM4_USART3_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42420130UL))) +#define bM4_USART3_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42420134UL))) +#define bM4_USART3_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42420138UL))) +#define bM4_USART3_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242013CUL))) +#define bM4_USART3_CR1_RTOE (*((volatile unsigned int*)(0x42420180UL))) +#define bM4_USART3_CR1_RTOIE (*((volatile unsigned int*)(0x42420184UL))) +#define bM4_USART3_CR1_RE (*((volatile unsigned int*)(0x42420188UL))) +#define bM4_USART3_CR1_TE (*((volatile unsigned int*)(0x4242018CUL))) +#define bM4_USART3_CR1_SLME (*((volatile unsigned int*)(0x42420190UL))) +#define bM4_USART3_CR1_RIE (*((volatile unsigned int*)(0x42420194UL))) +#define bM4_USART3_CR1_TCIE (*((volatile unsigned int*)(0x42420198UL))) +#define bM4_USART3_CR1_TXEIE (*((volatile unsigned int*)(0x4242019CUL))) +#define bM4_USART3_CR1_PS (*((volatile unsigned int*)(0x424201A4UL))) +#define bM4_USART3_CR1_PCE (*((volatile unsigned int*)(0x424201A8UL))) +#define bM4_USART3_CR1_M (*((volatile unsigned int*)(0x424201B0UL))) +#define bM4_USART3_CR1_OVER8 (*((volatile unsigned int*)(0x424201BCUL))) +#define bM4_USART3_CR1_CPE (*((volatile unsigned int*)(0x424201C0UL))) +#define bM4_USART3_CR1_CFE (*((volatile unsigned int*)(0x424201C4UL))) +#define bM4_USART3_CR1_CORE (*((volatile unsigned int*)(0x424201CCUL))) +#define bM4_USART3_CR1_CRTOF (*((volatile unsigned int*)(0x424201D0UL))) +#define bM4_USART3_CR1_MS (*((volatile unsigned int*)(0x424201E0UL))) +#define bM4_USART3_CR1_ML (*((volatile unsigned int*)(0x424201F0UL))) +#define bM4_USART3_CR1_FBME (*((volatile unsigned int*)(0x424201F4UL))) +#define bM4_USART3_CR1_NFE (*((volatile unsigned int*)(0x424201F8UL))) +#define bM4_USART3_CR1_SBS (*((volatile unsigned int*)(0x424201FCUL))) +#define bM4_USART3_CR2_MPE (*((volatile unsigned int*)(0x42420200UL))) +#define bM4_USART3_CR2_CLKC0 (*((volatile unsigned int*)(0x4242022CUL))) +#define bM4_USART3_CR2_CLKC1 (*((volatile unsigned int*)(0x42420230UL))) +#define bM4_USART3_CR2_STOP (*((volatile unsigned int*)(0x42420234UL))) +#define bM4_USART3_CR3_SCEN (*((volatile unsigned int*)(0x42420294UL))) +#define bM4_USART3_CR3_CTSE (*((volatile unsigned int*)(0x424202A4UL))) +#define bM4_USART3_CR3_BCN0 (*((volatile unsigned int*)(0x424202D4UL))) +#define bM4_USART3_CR3_BCN1 (*((volatile unsigned int*)(0x424202D8UL))) +#define bM4_USART3_CR3_BCN2 (*((volatile unsigned int*)(0x424202DCUL))) +#define bM4_USART3_PR_PSC0 (*((volatile unsigned int*)(0x42420300UL))) +#define bM4_USART3_PR_PSC1 (*((volatile unsigned int*)(0x42420304UL))) +#define bM4_USART4_SR_PE (*((volatile unsigned int*)(0x42428000UL))) +#define bM4_USART4_SR_FE (*((volatile unsigned int*)(0x42428004UL))) +#define bM4_USART4_SR_ORE (*((volatile unsigned int*)(0x4242800CUL))) +#define bM4_USART4_SR_RXNE (*((volatile unsigned int*)(0x42428014UL))) +#define bM4_USART4_SR_TC (*((volatile unsigned int*)(0x42428018UL))) +#define bM4_USART4_SR_TXE (*((volatile unsigned int*)(0x4242801CUL))) +#define bM4_USART4_SR_RTOF (*((volatile unsigned int*)(0x42428020UL))) +#define bM4_USART4_SR_MPB (*((volatile unsigned int*)(0x42428040UL))) +#define bM4_USART4_DR_TDR0 (*((volatile unsigned int*)(0x42428080UL))) +#define bM4_USART4_DR_TDR1 (*((volatile unsigned int*)(0x42428084UL))) +#define bM4_USART4_DR_TDR2 (*((volatile unsigned int*)(0x42428088UL))) +#define bM4_USART4_DR_TDR3 (*((volatile unsigned int*)(0x4242808CUL))) +#define bM4_USART4_DR_TDR4 (*((volatile unsigned int*)(0x42428090UL))) +#define bM4_USART4_DR_TDR5 (*((volatile unsigned int*)(0x42428094UL))) +#define bM4_USART4_DR_TDR6 (*((volatile unsigned int*)(0x42428098UL))) +#define bM4_USART4_DR_TDR7 (*((volatile unsigned int*)(0x4242809CUL))) +#define bM4_USART4_DR_TDR8 (*((volatile unsigned int*)(0x424280A0UL))) +#define bM4_USART4_DR_MPID (*((volatile unsigned int*)(0x424280A4UL))) +#define bM4_USART4_DR_RDR0 (*((volatile unsigned int*)(0x424280C0UL))) +#define bM4_USART4_DR_RDR1 (*((volatile unsigned int*)(0x424280C4UL))) +#define bM4_USART4_DR_RDR2 (*((volatile unsigned int*)(0x424280C8UL))) +#define bM4_USART4_DR_RDR3 (*((volatile unsigned int*)(0x424280CCUL))) +#define bM4_USART4_DR_RDR4 (*((volatile unsigned int*)(0x424280D0UL))) +#define bM4_USART4_DR_RDR5 (*((volatile unsigned int*)(0x424280D4UL))) +#define bM4_USART4_DR_RDR6 (*((volatile unsigned int*)(0x424280D8UL))) +#define bM4_USART4_DR_RDR7 (*((volatile unsigned int*)(0x424280DCUL))) +#define bM4_USART4_DR_RDR8 (*((volatile unsigned int*)(0x424280E0UL))) +#define bM4_USART4_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42428100UL))) +#define bM4_USART4_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42428104UL))) +#define bM4_USART4_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42428108UL))) +#define bM4_USART4_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242810CUL))) +#define bM4_USART4_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42428110UL))) +#define bM4_USART4_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42428114UL))) +#define bM4_USART4_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42428118UL))) +#define bM4_USART4_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42428120UL))) +#define bM4_USART4_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42428124UL))) +#define bM4_USART4_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42428128UL))) +#define bM4_USART4_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242812CUL))) +#define bM4_USART4_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42428130UL))) +#define bM4_USART4_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42428134UL))) +#define bM4_USART4_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42428138UL))) +#define bM4_USART4_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242813CUL))) +#define bM4_USART4_CR1_RTOE (*((volatile unsigned int*)(0x42428180UL))) +#define bM4_USART4_CR1_RTOIE (*((volatile unsigned int*)(0x42428184UL))) +#define bM4_USART4_CR1_RE (*((volatile unsigned int*)(0x42428188UL))) +#define bM4_USART4_CR1_TE (*((volatile unsigned int*)(0x4242818CUL))) +#define bM4_USART4_CR1_SLME (*((volatile unsigned int*)(0x42428190UL))) +#define bM4_USART4_CR1_RIE (*((volatile unsigned int*)(0x42428194UL))) +#define bM4_USART4_CR1_TCIE (*((volatile unsigned int*)(0x42428198UL))) +#define bM4_USART4_CR1_TXEIE (*((volatile unsigned int*)(0x4242819CUL))) +#define bM4_USART4_CR1_PS (*((volatile unsigned int*)(0x424281A4UL))) +#define bM4_USART4_CR1_PCE (*((volatile unsigned int*)(0x424281A8UL))) +#define bM4_USART4_CR1_M (*((volatile unsigned int*)(0x424281B0UL))) +#define bM4_USART4_CR1_OVER8 (*((volatile unsigned int*)(0x424281BCUL))) +#define bM4_USART4_CR1_CPE (*((volatile unsigned int*)(0x424281C0UL))) +#define bM4_USART4_CR1_CFE (*((volatile unsigned int*)(0x424281C4UL))) +#define bM4_USART4_CR1_CORE (*((volatile unsigned int*)(0x424281CCUL))) +#define bM4_USART4_CR1_CRTOF (*((volatile unsigned int*)(0x424281D0UL))) +#define bM4_USART4_CR1_MS (*((volatile unsigned int*)(0x424281E0UL))) +#define bM4_USART4_CR1_ML (*((volatile unsigned int*)(0x424281F0UL))) +#define bM4_USART4_CR1_FBME (*((volatile unsigned int*)(0x424281F4UL))) +#define bM4_USART4_CR1_NFE (*((volatile unsigned int*)(0x424281F8UL))) +#define bM4_USART4_CR1_SBS (*((volatile unsigned int*)(0x424281FCUL))) +#define bM4_USART4_CR2_MPE (*((volatile unsigned int*)(0x42428200UL))) +#define bM4_USART4_CR2_CLKC0 (*((volatile unsigned int*)(0x4242822CUL))) +#define bM4_USART4_CR2_CLKC1 (*((volatile unsigned int*)(0x42428230UL))) +#define bM4_USART4_CR2_STOP (*((volatile unsigned int*)(0x42428234UL))) +#define bM4_USART4_CR3_SCEN (*((volatile unsigned int*)(0x42428294UL))) +#define bM4_USART4_CR3_CTSE (*((volatile unsigned int*)(0x424282A4UL))) +#define bM4_USART4_CR3_BCN0 (*((volatile unsigned int*)(0x424282D4UL))) +#define bM4_USART4_CR3_BCN1 (*((volatile unsigned int*)(0x424282D8UL))) +#define bM4_USART4_CR3_BCN2 (*((volatile unsigned int*)(0x424282DCUL))) +#define bM4_USART4_PR_PSC0 (*((volatile unsigned int*)(0x42428300UL))) +#define bM4_USART4_PR_PSC1 (*((volatile unsigned int*)(0x42428304UL))) +#define bM4_USBFS_USBFS_GVBUSCFG_VBUSOVEN (*((volatile unsigned int*)(0x43800018UL))) +#define bM4_USBFS_USBFS_GVBUSCFG_VBUSVAL (*((volatile unsigned int*)(0x4380001CUL))) +#define bM4_USBFS_GAHBCFG_GINTMSK (*((volatile unsigned int*)(0x43800100UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN0 (*((volatile unsigned int*)(0x43800104UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN1 (*((volatile unsigned int*)(0x43800108UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN2 (*((volatile unsigned int*)(0x4380010CUL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN3 (*((volatile unsigned int*)(0x43800110UL))) +#define bM4_USBFS_GAHBCFG_DMAEN (*((volatile unsigned int*)(0x43800114UL))) +#define bM4_USBFS_GAHBCFG_TXFELVL (*((volatile unsigned int*)(0x4380011CUL))) +#define bM4_USBFS_GAHBCFG_PTXFELVL (*((volatile unsigned int*)(0x43800120UL))) +#define bM4_USBFS_GUSBCFG_TOCAL0 (*((volatile unsigned int*)(0x43800180UL))) +#define bM4_USBFS_GUSBCFG_TOCAL1 (*((volatile unsigned int*)(0x43800184UL))) +#define bM4_USBFS_GUSBCFG_TOCAL2 (*((volatile unsigned int*)(0x43800188UL))) +#define bM4_USBFS_GUSBCFG_PHYSEL (*((volatile unsigned int*)(0x43800198UL))) +#define bM4_USBFS_GUSBCFG_TRDT0 (*((volatile unsigned int*)(0x438001A8UL))) +#define bM4_USBFS_GUSBCFG_TRDT1 (*((volatile unsigned int*)(0x438001ACUL))) +#define bM4_USBFS_GUSBCFG_TRDT2 (*((volatile unsigned int*)(0x438001B0UL))) +#define bM4_USBFS_GUSBCFG_TRDT3 (*((volatile unsigned int*)(0x438001B4UL))) +#define bM4_USBFS_GUSBCFG_FHMOD (*((volatile unsigned int*)(0x438001F4UL))) +#define bM4_USBFS_GUSBCFG_FDMOD (*((volatile unsigned int*)(0x438001F8UL))) +#define bM4_USBFS_GRSTCTL_CSRST (*((volatile unsigned int*)(0x43800200UL))) +#define bM4_USBFS_GRSTCTL_HSRST (*((volatile unsigned int*)(0x43800204UL))) +#define bM4_USBFS_GRSTCTL_FCRST (*((volatile unsigned int*)(0x43800208UL))) +#define bM4_USBFS_GRSTCTL_RXFFLSH (*((volatile unsigned int*)(0x43800210UL))) +#define bM4_USBFS_GRSTCTL_TXFFLSH (*((volatile unsigned int*)(0x43800214UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM0 (*((volatile unsigned int*)(0x43800218UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM1 (*((volatile unsigned int*)(0x4380021CUL))) +#define bM4_USBFS_GRSTCTL_TXFNUM2 (*((volatile unsigned int*)(0x43800220UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM3 (*((volatile unsigned int*)(0x43800224UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM4 (*((volatile unsigned int*)(0x43800228UL))) +#define bM4_USBFS_GRSTCTL_DMAREQ (*((volatile unsigned int*)(0x43800278UL))) +#define bM4_USBFS_GRSTCTL_AHBIDL (*((volatile unsigned int*)(0x4380027CUL))) +#define bM4_USBFS_GINTSTS_CMOD (*((volatile unsigned int*)(0x43800280UL))) +#define bM4_USBFS_GINTSTS_MMIS (*((volatile unsigned int*)(0x43800284UL))) +#define bM4_USBFS_GINTSTS_SOF (*((volatile unsigned int*)(0x4380028CUL))) +#define bM4_USBFS_GINTSTS_RXFNE (*((volatile unsigned int*)(0x43800290UL))) +#define bM4_USBFS_GINTSTS_NPTXFE (*((volatile unsigned int*)(0x43800294UL))) +#define bM4_USBFS_GINTSTS_GINAKEFF (*((volatile unsigned int*)(0x43800298UL))) +#define bM4_USBFS_GINTSTS_GONAKEFF (*((volatile unsigned int*)(0x4380029CUL))) +#define bM4_USBFS_GINTSTS_ESUSP (*((volatile unsigned int*)(0x438002A8UL))) +#define bM4_USBFS_GINTSTS_USBSUSP (*((volatile unsigned int*)(0x438002ACUL))) +#define bM4_USBFS_GINTSTS_USBRST (*((volatile unsigned int*)(0x438002B0UL))) +#define bM4_USBFS_GINTSTS_ENUMDNE (*((volatile unsigned int*)(0x438002B4UL))) +#define bM4_USBFS_GINTSTS_ISOODRP (*((volatile unsigned int*)(0x438002B8UL))) +#define bM4_USBFS_GINTSTS_EOPF (*((volatile unsigned int*)(0x438002BCUL))) +#define bM4_USBFS_GINTSTS_IEPINT (*((volatile unsigned int*)(0x438002C8UL))) +#define bM4_USBFS_GINTSTS_OEPINT (*((volatile unsigned int*)(0x438002CCUL))) +#define bM4_USBFS_GINTSTS_IISOIXFR (*((volatile unsigned int*)(0x438002D0UL))) +#define bM4_USBFS_GINTSTS_IPXFR_INCOMPISOOUT (*((volatile unsigned int*)(0x438002D4UL))) +#define bM4_USBFS_GINTSTS_DATAFSUSP (*((volatile unsigned int*)(0x438002D8UL))) +#define bM4_USBFS_GINTSTS_HPRTINT (*((volatile unsigned int*)(0x438002E0UL))) +#define bM4_USBFS_GINTSTS_HCINT (*((volatile unsigned int*)(0x438002E4UL))) +#define bM4_USBFS_GINTSTS_PTXFE (*((volatile unsigned int*)(0x438002E8UL))) +#define bM4_USBFS_GINTSTS_CIDSCHG (*((volatile unsigned int*)(0x438002F0UL))) +#define bM4_USBFS_GINTSTS_DISCINT (*((volatile unsigned int*)(0x438002F4UL))) +#define bM4_USBFS_GINTSTS_VBUSVINT (*((volatile unsigned int*)(0x438002F8UL))) +#define bM4_USBFS_GINTSTS_WKUINT (*((volatile unsigned int*)(0x438002FCUL))) +#define bM4_USBFS_GINTMSK_MMISM (*((volatile unsigned int*)(0x43800304UL))) +#define bM4_USBFS_GINTMSK_SOFM (*((volatile unsigned int*)(0x4380030CUL))) +#define bM4_USBFS_GINTMSK_RXFNEM (*((volatile unsigned int*)(0x43800310UL))) +#define bM4_USBFS_GINTMSK_NPTXFEM (*((volatile unsigned int*)(0x43800314UL))) +#define bM4_USBFS_GINTMSK_GINAKEFFM (*((volatile unsigned int*)(0x43800318UL))) +#define bM4_USBFS_GINTMSK_GONAKEFFM (*((volatile unsigned int*)(0x4380031CUL))) +#define bM4_USBFS_GINTMSK_ESUSPM (*((volatile unsigned int*)(0x43800328UL))) +#define bM4_USBFS_GINTMSK_USBSUSPM (*((volatile unsigned int*)(0x4380032CUL))) +#define bM4_USBFS_GINTMSK_USBRSTM (*((volatile unsigned int*)(0x43800330UL))) +#define bM4_USBFS_GINTMSK_ENUMDNEM (*((volatile unsigned int*)(0x43800334UL))) +#define bM4_USBFS_GINTMSK_ISOODRPM (*((volatile unsigned int*)(0x43800338UL))) +#define bM4_USBFS_GINTMSK_EOPFM (*((volatile unsigned int*)(0x4380033CUL))) +#define bM4_USBFS_GINTMSK_IEPIM (*((volatile unsigned int*)(0x43800348UL))) +#define bM4_USBFS_GINTMSK_OEPIM (*((volatile unsigned int*)(0x4380034CUL))) +#define bM4_USBFS_GINTMSK_IISOIXFRM (*((volatile unsigned int*)(0x43800350UL))) +#define bM4_USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (*((volatile unsigned int*)(0x43800354UL))) +#define bM4_USBFS_GINTMSK_DATAFSUSPM (*((volatile unsigned int*)(0x43800358UL))) +#define bM4_USBFS_GINTMSK_HPRTIM (*((volatile unsigned int*)(0x43800360UL))) +#define bM4_USBFS_GINTMSK_HCIM (*((volatile unsigned int*)(0x43800364UL))) +#define bM4_USBFS_GINTMSK_PTXFEM (*((volatile unsigned int*)(0x43800368UL))) +#define bM4_USBFS_GINTMSK_CIDSCHGM (*((volatile unsigned int*)(0x43800370UL))) +#define bM4_USBFS_GINTMSK_DISCIM (*((volatile unsigned int*)(0x43800374UL))) +#define bM4_USBFS_GINTMSK_VBUSVIM (*((volatile unsigned int*)(0x43800378UL))) +#define bM4_USBFS_GINTMSK_WKUIM (*((volatile unsigned int*)(0x4380037CUL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800380UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800384UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800388UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380038CUL))) +#define bM4_USBFS_GRXSTSR_BCNT0 (*((volatile unsigned int*)(0x43800390UL))) +#define bM4_USBFS_GRXSTSR_BCNT1 (*((volatile unsigned int*)(0x43800394UL))) +#define bM4_USBFS_GRXSTSR_BCNT2 (*((volatile unsigned int*)(0x43800398UL))) +#define bM4_USBFS_GRXSTSR_BCNT3 (*((volatile unsigned int*)(0x4380039CUL))) +#define bM4_USBFS_GRXSTSR_BCNT4 (*((volatile unsigned int*)(0x438003A0UL))) +#define bM4_USBFS_GRXSTSR_BCNT5 (*((volatile unsigned int*)(0x438003A4UL))) +#define bM4_USBFS_GRXSTSR_BCNT6 (*((volatile unsigned int*)(0x438003A8UL))) +#define bM4_USBFS_GRXSTSR_BCNT7 (*((volatile unsigned int*)(0x438003ACUL))) +#define bM4_USBFS_GRXSTSR_BCNT8 (*((volatile unsigned int*)(0x438003B0UL))) +#define bM4_USBFS_GRXSTSR_BCNT9 (*((volatile unsigned int*)(0x438003B4UL))) +#define bM4_USBFS_GRXSTSR_BCNT10 (*((volatile unsigned int*)(0x438003B8UL))) +#define bM4_USBFS_GRXSTSR_DPID0 (*((volatile unsigned int*)(0x438003BCUL))) +#define bM4_USBFS_GRXSTSR_DPID1 (*((volatile unsigned int*)(0x438003C0UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS0 (*((volatile unsigned int*)(0x438003C4UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS1 (*((volatile unsigned int*)(0x438003C8UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS2 (*((volatile unsigned int*)(0x438003CCUL))) +#define bM4_USBFS_GRXSTSR_PKTSTS3 (*((volatile unsigned int*)(0x438003D0UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800400UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800404UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800408UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380040CUL))) +#define bM4_USBFS_GRXSTSP_BCNT0 (*((volatile unsigned int*)(0x43800410UL))) +#define bM4_USBFS_GRXSTSP_BCNT1 (*((volatile unsigned int*)(0x43800414UL))) +#define bM4_USBFS_GRXSTSP_BCNT2 (*((volatile unsigned int*)(0x43800418UL))) +#define bM4_USBFS_GRXSTSP_BCNT3 (*((volatile unsigned int*)(0x4380041CUL))) +#define bM4_USBFS_GRXSTSP_BCNT4 (*((volatile unsigned int*)(0x43800420UL))) +#define bM4_USBFS_GRXSTSP_BCNT5 (*((volatile unsigned int*)(0x43800424UL))) +#define bM4_USBFS_GRXSTSP_BCNT6 (*((volatile unsigned int*)(0x43800428UL))) +#define bM4_USBFS_GRXSTSP_BCNT7 (*((volatile unsigned int*)(0x4380042CUL))) +#define bM4_USBFS_GRXSTSP_BCNT8 (*((volatile unsigned int*)(0x43800430UL))) +#define bM4_USBFS_GRXSTSP_BCNT9 (*((volatile unsigned int*)(0x43800434UL))) +#define bM4_USBFS_GRXSTSP_BCNT10 (*((volatile unsigned int*)(0x43800438UL))) +#define bM4_USBFS_GRXSTSP_DPID0 (*((volatile unsigned int*)(0x4380043CUL))) +#define bM4_USBFS_GRXSTSP_DPID1 (*((volatile unsigned int*)(0x43800440UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS0 (*((volatile unsigned int*)(0x43800444UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS1 (*((volatile unsigned int*)(0x43800448UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS2 (*((volatile unsigned int*)(0x4380044CUL))) +#define bM4_USBFS_GRXSTSP_PKTSTS3 (*((volatile unsigned int*)(0x43800450UL))) +#define bM4_USBFS_GRXFSIZ_RXFD0 (*((volatile unsigned int*)(0x43800480UL))) +#define bM4_USBFS_GRXFSIZ_RXFD1 (*((volatile unsigned int*)(0x43800484UL))) +#define bM4_USBFS_GRXFSIZ_RXFD2 (*((volatile unsigned int*)(0x43800488UL))) +#define bM4_USBFS_GRXFSIZ_RXFD3 (*((volatile unsigned int*)(0x4380048CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD4 (*((volatile unsigned int*)(0x43800490UL))) +#define bM4_USBFS_GRXFSIZ_RXFD5 (*((volatile unsigned int*)(0x43800494UL))) +#define bM4_USBFS_GRXFSIZ_RXFD6 (*((volatile unsigned int*)(0x43800498UL))) +#define bM4_USBFS_GRXFSIZ_RXFD7 (*((volatile unsigned int*)(0x4380049CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD8 (*((volatile unsigned int*)(0x438004A0UL))) +#define bM4_USBFS_GRXFSIZ_RXFD9 (*((volatile unsigned int*)(0x438004A4UL))) +#define bM4_USBFS_GRXFSIZ_RXFD10 (*((volatile unsigned int*)(0x438004A8UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA0 (*((volatile unsigned int*)(0x43800500UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA1 (*((volatile unsigned int*)(0x43800504UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA2 (*((volatile unsigned int*)(0x43800508UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA3 (*((volatile unsigned int*)(0x4380050CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA4 (*((volatile unsigned int*)(0x43800510UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA5 (*((volatile unsigned int*)(0x43800514UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA6 (*((volatile unsigned int*)(0x43800518UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA7 (*((volatile unsigned int*)(0x4380051CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA8 (*((volatile unsigned int*)(0x43800520UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA9 (*((volatile unsigned int*)(0x43800524UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA10 (*((volatile unsigned int*)(0x43800528UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA11 (*((volatile unsigned int*)(0x4380052CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA12 (*((volatile unsigned int*)(0x43800530UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA13 (*((volatile unsigned int*)(0x43800534UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA14 (*((volatile unsigned int*)(0x43800538UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA15 (*((volatile unsigned int*)(0x4380053CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD0 (*((volatile unsigned int*)(0x43800540UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD1 (*((volatile unsigned int*)(0x43800544UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD2 (*((volatile unsigned int*)(0x43800548UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD3 (*((volatile unsigned int*)(0x4380054CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD4 (*((volatile unsigned int*)(0x43800550UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD5 (*((volatile unsigned int*)(0x43800554UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD6 (*((volatile unsigned int*)(0x43800558UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD7 (*((volatile unsigned int*)(0x4380055CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD8 (*((volatile unsigned int*)(0x43800560UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD9 (*((volatile unsigned int*)(0x43800564UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD10 (*((volatile unsigned int*)(0x43800568UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD11 (*((volatile unsigned int*)(0x4380056CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD12 (*((volatile unsigned int*)(0x43800570UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD13 (*((volatile unsigned int*)(0x43800574UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD14 (*((volatile unsigned int*)(0x43800578UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD15 (*((volatile unsigned int*)(0x4380057CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV0 (*((volatile unsigned int*)(0x43800580UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV1 (*((volatile unsigned int*)(0x43800584UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV2 (*((volatile unsigned int*)(0x43800588UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV3 (*((volatile unsigned int*)(0x4380058CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV4 (*((volatile unsigned int*)(0x43800590UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV5 (*((volatile unsigned int*)(0x43800594UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV6 (*((volatile unsigned int*)(0x43800598UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV7 (*((volatile unsigned int*)(0x4380059CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV8 (*((volatile unsigned int*)(0x438005A0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV9 (*((volatile unsigned int*)(0x438005A4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV10 (*((volatile unsigned int*)(0x438005A8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV11 (*((volatile unsigned int*)(0x438005ACUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV12 (*((volatile unsigned int*)(0x438005B0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV13 (*((volatile unsigned int*)(0x438005B4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV14 (*((volatile unsigned int*)(0x438005B8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV15 (*((volatile unsigned int*)(0x438005BCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV0 (*((volatile unsigned int*)(0x438005C0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV1 (*((volatile unsigned int*)(0x438005C4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV2 (*((volatile unsigned int*)(0x438005C8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV3 (*((volatile unsigned int*)(0x438005CCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV4 (*((volatile unsigned int*)(0x438005D0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV5 (*((volatile unsigned int*)(0x438005D4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV6 (*((volatile unsigned int*)(0x438005D8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV7 (*((volatile unsigned int*)(0x438005DCUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP0 (*((volatile unsigned int*)(0x438005E0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP1 (*((volatile unsigned int*)(0x438005E4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP2 (*((volatile unsigned int*)(0x438005E8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP3 (*((volatile unsigned int*)(0x438005ECUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP4 (*((volatile unsigned int*)(0x438005F0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP5 (*((volatile unsigned int*)(0x438005F4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP6 (*((volatile unsigned int*)(0x438005F8UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA0 (*((volatile unsigned int*)(0x43802000UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA1 (*((volatile unsigned int*)(0x43802004UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA2 (*((volatile unsigned int*)(0x43802008UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA3 (*((volatile unsigned int*)(0x4380200CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA4 (*((volatile unsigned int*)(0x43802010UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA5 (*((volatile unsigned int*)(0x43802014UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA6 (*((volatile unsigned int*)(0x43802018UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA7 (*((volatile unsigned int*)(0x4380201CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA8 (*((volatile unsigned int*)(0x43802020UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA9 (*((volatile unsigned int*)(0x43802024UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA10 (*((volatile unsigned int*)(0x43802028UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA11 (*((volatile unsigned int*)(0x4380202CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD0 (*((volatile unsigned int*)(0x43802040UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD1 (*((volatile unsigned int*)(0x43802044UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD2 (*((volatile unsigned int*)(0x43802048UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD3 (*((volatile unsigned int*)(0x4380204CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD4 (*((volatile unsigned int*)(0x43802050UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD5 (*((volatile unsigned int*)(0x43802054UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD6 (*((volatile unsigned int*)(0x43802058UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD7 (*((volatile unsigned int*)(0x4380205CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD8 (*((volatile unsigned int*)(0x43802060UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD9 (*((volatile unsigned int*)(0x43802064UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD10 (*((volatile unsigned int*)(0x43802068UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA0 (*((volatile unsigned int*)(0x43802080UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA1 (*((volatile unsigned int*)(0x43802084UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA2 (*((volatile unsigned int*)(0x43802088UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA3 (*((volatile unsigned int*)(0x4380208CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA4 (*((volatile unsigned int*)(0x43802090UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA5 (*((volatile unsigned int*)(0x43802094UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA6 (*((volatile unsigned int*)(0x43802098UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA7 (*((volatile unsigned int*)(0x4380209CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA8 (*((volatile unsigned int*)(0x438020A0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA9 (*((volatile unsigned int*)(0x438020A4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA10 (*((volatile unsigned int*)(0x438020A8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA11 (*((volatile unsigned int*)(0x438020ACUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD0 (*((volatile unsigned int*)(0x438020C0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD1 (*((volatile unsigned int*)(0x438020C4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD2 (*((volatile unsigned int*)(0x438020C8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD3 (*((volatile unsigned int*)(0x438020CCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD4 (*((volatile unsigned int*)(0x438020D0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD5 (*((volatile unsigned int*)(0x438020D4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD6 (*((volatile unsigned int*)(0x438020D8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD7 (*((volatile unsigned int*)(0x438020DCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD8 (*((volatile unsigned int*)(0x438020E0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD9 (*((volatile unsigned int*)(0x438020E4UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA0 (*((volatile unsigned int*)(0x43802100UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA1 (*((volatile unsigned int*)(0x43802104UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA2 (*((volatile unsigned int*)(0x43802108UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA3 (*((volatile unsigned int*)(0x4380210CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA4 (*((volatile unsigned int*)(0x43802110UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA5 (*((volatile unsigned int*)(0x43802114UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA6 (*((volatile unsigned int*)(0x43802118UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA7 (*((volatile unsigned int*)(0x4380211CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA8 (*((volatile unsigned int*)(0x43802120UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA9 (*((volatile unsigned int*)(0x43802124UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA10 (*((volatile unsigned int*)(0x43802128UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA11 (*((volatile unsigned int*)(0x4380212CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD0 (*((volatile unsigned int*)(0x43802140UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD1 (*((volatile unsigned int*)(0x43802144UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD2 (*((volatile unsigned int*)(0x43802148UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD3 (*((volatile unsigned int*)(0x4380214CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD4 (*((volatile unsigned int*)(0x43802150UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD5 (*((volatile unsigned int*)(0x43802154UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD6 (*((volatile unsigned int*)(0x43802158UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD7 (*((volatile unsigned int*)(0x4380215CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD8 (*((volatile unsigned int*)(0x43802160UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD9 (*((volatile unsigned int*)(0x43802164UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA0 (*((volatile unsigned int*)(0x43802180UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA1 (*((volatile unsigned int*)(0x43802184UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA2 (*((volatile unsigned int*)(0x43802188UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA3 (*((volatile unsigned int*)(0x4380218CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA4 (*((volatile unsigned int*)(0x43802190UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA5 (*((volatile unsigned int*)(0x43802194UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA6 (*((volatile unsigned int*)(0x43802198UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA7 (*((volatile unsigned int*)(0x4380219CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA8 (*((volatile unsigned int*)(0x438021A0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA9 (*((volatile unsigned int*)(0x438021A4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA10 (*((volatile unsigned int*)(0x438021A8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA11 (*((volatile unsigned int*)(0x438021ACUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD0 (*((volatile unsigned int*)(0x438021C0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD1 (*((volatile unsigned int*)(0x438021C4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD2 (*((volatile unsigned int*)(0x438021C8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD3 (*((volatile unsigned int*)(0x438021CCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD4 (*((volatile unsigned int*)(0x438021D0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD5 (*((volatile unsigned int*)(0x438021D4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD6 (*((volatile unsigned int*)(0x438021D8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD7 (*((volatile unsigned int*)(0x438021DCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD8 (*((volatile unsigned int*)(0x438021E0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD9 (*((volatile unsigned int*)(0x438021E4UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA0 (*((volatile unsigned int*)(0x43802200UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA1 (*((volatile unsigned int*)(0x43802204UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA2 (*((volatile unsigned int*)(0x43802208UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA3 (*((volatile unsigned int*)(0x4380220CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA4 (*((volatile unsigned int*)(0x43802210UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA5 (*((volatile unsigned int*)(0x43802214UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA6 (*((volatile unsigned int*)(0x43802218UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA7 (*((volatile unsigned int*)(0x4380221CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA8 (*((volatile unsigned int*)(0x43802220UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA9 (*((volatile unsigned int*)(0x43802224UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA10 (*((volatile unsigned int*)(0x43802228UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA11 (*((volatile unsigned int*)(0x4380222CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD0 (*((volatile unsigned int*)(0x43802240UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD1 (*((volatile unsigned int*)(0x43802244UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD2 (*((volatile unsigned int*)(0x43802248UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD3 (*((volatile unsigned int*)(0x4380224CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD4 (*((volatile unsigned int*)(0x43802250UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD5 (*((volatile unsigned int*)(0x43802254UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD6 (*((volatile unsigned int*)(0x43802258UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD7 (*((volatile unsigned int*)(0x4380225CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD8 (*((volatile unsigned int*)(0x43802260UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD9 (*((volatile unsigned int*)(0x43802264UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA0 (*((volatile unsigned int*)(0x43802280UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA1 (*((volatile unsigned int*)(0x43802284UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA2 (*((volatile unsigned int*)(0x43802288UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA3 (*((volatile unsigned int*)(0x4380228CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA4 (*((volatile unsigned int*)(0x43802290UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA5 (*((volatile unsigned int*)(0x43802294UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA6 (*((volatile unsigned int*)(0x43802298UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA7 (*((volatile unsigned int*)(0x4380229CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA8 (*((volatile unsigned int*)(0x438022A0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA9 (*((volatile unsigned int*)(0x438022A4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA10 (*((volatile unsigned int*)(0x438022A8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA11 (*((volatile unsigned int*)(0x438022ACUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD0 (*((volatile unsigned int*)(0x438022C0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD1 (*((volatile unsigned int*)(0x438022C4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD2 (*((volatile unsigned int*)(0x438022C8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD3 (*((volatile unsigned int*)(0x438022CCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD4 (*((volatile unsigned int*)(0x438022D0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD5 (*((volatile unsigned int*)(0x438022D4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD6 (*((volatile unsigned int*)(0x438022D8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD7 (*((volatile unsigned int*)(0x438022DCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD8 (*((volatile unsigned int*)(0x438022E0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD9 (*((volatile unsigned int*)(0x438022E4UL))) +#define bM4_USBFS_HCFG_FSLSPCS0 (*((volatile unsigned int*)(0x43808000UL))) +#define bM4_USBFS_HCFG_FSLSPCS1 (*((volatile unsigned int*)(0x43808004UL))) +#define bM4_USBFS_HCFG_FSLSS (*((volatile unsigned int*)(0x43808008UL))) +#define bM4_USBFS_HFIR_FRIVL0 (*((volatile unsigned int*)(0x43808080UL))) +#define bM4_USBFS_HFIR_FRIVL1 (*((volatile unsigned int*)(0x43808084UL))) +#define bM4_USBFS_HFIR_FRIVL2 (*((volatile unsigned int*)(0x43808088UL))) +#define bM4_USBFS_HFIR_FRIVL3 (*((volatile unsigned int*)(0x4380808CUL))) +#define bM4_USBFS_HFIR_FRIVL4 (*((volatile unsigned int*)(0x43808090UL))) +#define bM4_USBFS_HFIR_FRIVL5 (*((volatile unsigned int*)(0x43808094UL))) +#define bM4_USBFS_HFIR_FRIVL6 (*((volatile unsigned int*)(0x43808098UL))) +#define bM4_USBFS_HFIR_FRIVL7 (*((volatile unsigned int*)(0x4380809CUL))) +#define bM4_USBFS_HFIR_FRIVL8 (*((volatile unsigned int*)(0x438080A0UL))) +#define bM4_USBFS_HFIR_FRIVL9 (*((volatile unsigned int*)(0x438080A4UL))) +#define bM4_USBFS_HFIR_FRIVL10 (*((volatile unsigned int*)(0x438080A8UL))) +#define bM4_USBFS_HFIR_FRIVL11 (*((volatile unsigned int*)(0x438080ACUL))) +#define bM4_USBFS_HFIR_FRIVL12 (*((volatile unsigned int*)(0x438080B0UL))) +#define bM4_USBFS_HFIR_FRIVL13 (*((volatile unsigned int*)(0x438080B4UL))) +#define bM4_USBFS_HFIR_FRIVL14 (*((volatile unsigned int*)(0x438080B8UL))) +#define bM4_USBFS_HFIR_FRIVL15 (*((volatile unsigned int*)(0x438080BCUL))) +#define bM4_USBFS_HFNUM_FRNUM0 (*((volatile unsigned int*)(0x43808100UL))) +#define bM4_USBFS_HFNUM_FRNUM1 (*((volatile unsigned int*)(0x43808104UL))) +#define bM4_USBFS_HFNUM_FRNUM2 (*((volatile unsigned int*)(0x43808108UL))) +#define bM4_USBFS_HFNUM_FRNUM3 (*((volatile unsigned int*)(0x4380810CUL))) +#define bM4_USBFS_HFNUM_FRNUM4 (*((volatile unsigned int*)(0x43808110UL))) +#define bM4_USBFS_HFNUM_FRNUM5 (*((volatile unsigned int*)(0x43808114UL))) +#define bM4_USBFS_HFNUM_FRNUM6 (*((volatile unsigned int*)(0x43808118UL))) +#define bM4_USBFS_HFNUM_FRNUM7 (*((volatile unsigned int*)(0x4380811CUL))) +#define bM4_USBFS_HFNUM_FRNUM8 (*((volatile unsigned int*)(0x43808120UL))) +#define bM4_USBFS_HFNUM_FRNUM9 (*((volatile unsigned int*)(0x43808124UL))) +#define bM4_USBFS_HFNUM_FRNUM10 (*((volatile unsigned int*)(0x43808128UL))) +#define bM4_USBFS_HFNUM_FRNUM11 (*((volatile unsigned int*)(0x4380812CUL))) +#define bM4_USBFS_HFNUM_FRNUM12 (*((volatile unsigned int*)(0x43808130UL))) +#define bM4_USBFS_HFNUM_FRNUM13 (*((volatile unsigned int*)(0x43808134UL))) +#define bM4_USBFS_HFNUM_FRNUM14 (*((volatile unsigned int*)(0x43808138UL))) +#define bM4_USBFS_HFNUM_FRNUM15 (*((volatile unsigned int*)(0x4380813CUL))) +#define bM4_USBFS_HFNUM_FTREM0 (*((volatile unsigned int*)(0x43808140UL))) +#define bM4_USBFS_HFNUM_FTREM1 (*((volatile unsigned int*)(0x43808144UL))) +#define bM4_USBFS_HFNUM_FTREM2 (*((volatile unsigned int*)(0x43808148UL))) +#define bM4_USBFS_HFNUM_FTREM3 (*((volatile unsigned int*)(0x4380814CUL))) +#define bM4_USBFS_HFNUM_FTREM4 (*((volatile unsigned int*)(0x43808150UL))) +#define bM4_USBFS_HFNUM_FTREM5 (*((volatile unsigned int*)(0x43808154UL))) +#define bM4_USBFS_HFNUM_FTREM6 (*((volatile unsigned int*)(0x43808158UL))) +#define bM4_USBFS_HFNUM_FTREM7 (*((volatile unsigned int*)(0x4380815CUL))) +#define bM4_USBFS_HFNUM_FTREM8 (*((volatile unsigned int*)(0x43808160UL))) +#define bM4_USBFS_HFNUM_FTREM9 (*((volatile unsigned int*)(0x43808164UL))) +#define bM4_USBFS_HFNUM_FTREM10 (*((volatile unsigned int*)(0x43808168UL))) +#define bM4_USBFS_HFNUM_FTREM11 (*((volatile unsigned int*)(0x4380816CUL))) +#define bM4_USBFS_HFNUM_FTREM12 (*((volatile unsigned int*)(0x43808170UL))) +#define bM4_USBFS_HFNUM_FTREM13 (*((volatile unsigned int*)(0x43808174UL))) +#define bM4_USBFS_HFNUM_FTREM14 (*((volatile unsigned int*)(0x43808178UL))) +#define bM4_USBFS_HFNUM_FTREM15 (*((volatile unsigned int*)(0x4380817CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL0 (*((volatile unsigned int*)(0x43808200UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL1 (*((volatile unsigned int*)(0x43808204UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL2 (*((volatile unsigned int*)(0x43808208UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL3 (*((volatile unsigned int*)(0x4380820CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL4 (*((volatile unsigned int*)(0x43808210UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL5 (*((volatile unsigned int*)(0x43808214UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL6 (*((volatile unsigned int*)(0x43808218UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL7 (*((volatile unsigned int*)(0x4380821CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL8 (*((volatile unsigned int*)(0x43808220UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL9 (*((volatile unsigned int*)(0x43808224UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL10 (*((volatile unsigned int*)(0x43808228UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL11 (*((volatile unsigned int*)(0x4380822CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL12 (*((volatile unsigned int*)(0x43808230UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL13 (*((volatile unsigned int*)(0x43808234UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL14 (*((volatile unsigned int*)(0x43808238UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL15 (*((volatile unsigned int*)(0x4380823CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV0 (*((volatile unsigned int*)(0x43808240UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV1 (*((volatile unsigned int*)(0x43808244UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV2 (*((volatile unsigned int*)(0x43808248UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV3 (*((volatile unsigned int*)(0x4380824CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV4 (*((volatile unsigned int*)(0x43808250UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV5 (*((volatile unsigned int*)(0x43808254UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV6 (*((volatile unsigned int*)(0x43808258UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV7 (*((volatile unsigned int*)(0x4380825CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP0 (*((volatile unsigned int*)(0x43808260UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP1 (*((volatile unsigned int*)(0x43808264UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP2 (*((volatile unsigned int*)(0x43808268UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP3 (*((volatile unsigned int*)(0x4380826CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP4 (*((volatile unsigned int*)(0x43808270UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP5 (*((volatile unsigned int*)(0x43808274UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP6 (*((volatile unsigned int*)(0x43808278UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP7 (*((volatile unsigned int*)(0x4380827CUL))) +#define bM4_USBFS_HAINT_HAINT0 (*((volatile unsigned int*)(0x43808280UL))) +#define bM4_USBFS_HAINT_HAINT1 (*((volatile unsigned int*)(0x43808284UL))) +#define bM4_USBFS_HAINT_HAINT2 (*((volatile unsigned int*)(0x43808288UL))) +#define bM4_USBFS_HAINT_HAINT3 (*((volatile unsigned int*)(0x4380828CUL))) +#define bM4_USBFS_HAINT_HAINT4 (*((volatile unsigned int*)(0x43808290UL))) +#define bM4_USBFS_HAINT_HAINT5 (*((volatile unsigned int*)(0x43808294UL))) +#define bM4_USBFS_HAINT_HAINT6 (*((volatile unsigned int*)(0x43808298UL))) +#define bM4_USBFS_HAINT_HAINT7 (*((volatile unsigned int*)(0x4380829CUL))) +#define bM4_USBFS_HAINT_HAINT8 (*((volatile unsigned int*)(0x438082A0UL))) +#define bM4_USBFS_HAINT_HAINT9 (*((volatile unsigned int*)(0x438082A4UL))) +#define bM4_USBFS_HAINT_HAINT10 (*((volatile unsigned int*)(0x438082A8UL))) +#define bM4_USBFS_HAINT_HAINT11 (*((volatile unsigned int*)(0x438082ACUL))) +#define bM4_USBFS_HAINTMSK_HAINTM0 (*((volatile unsigned int*)(0x43808300UL))) +#define bM4_USBFS_HAINTMSK_HAINTM1 (*((volatile unsigned int*)(0x43808304UL))) +#define bM4_USBFS_HAINTMSK_HAINTM2 (*((volatile unsigned int*)(0x43808308UL))) +#define bM4_USBFS_HAINTMSK_HAINTM3 (*((volatile unsigned int*)(0x4380830CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM4 (*((volatile unsigned int*)(0x43808310UL))) +#define bM4_USBFS_HAINTMSK_HAINTM5 (*((volatile unsigned int*)(0x43808314UL))) +#define bM4_USBFS_HAINTMSK_HAINTM6 (*((volatile unsigned int*)(0x43808318UL))) +#define bM4_USBFS_HAINTMSK_HAINTM7 (*((volatile unsigned int*)(0x4380831CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM8 (*((volatile unsigned int*)(0x43808320UL))) +#define bM4_USBFS_HAINTMSK_HAINTM9 (*((volatile unsigned int*)(0x43808324UL))) +#define bM4_USBFS_HAINTMSK_HAINTM10 (*((volatile unsigned int*)(0x43808328UL))) +#define bM4_USBFS_HAINTMSK_HAINTM11 (*((volatile unsigned int*)(0x4380832CUL))) +#define bM4_USBFS_HPRT_PCSTS (*((volatile unsigned int*)(0x43808800UL))) +#define bM4_USBFS_HPRT_PCDET (*((volatile unsigned int*)(0x43808804UL))) +#define bM4_USBFS_HPRT_PENA (*((volatile unsigned int*)(0x43808808UL))) +#define bM4_USBFS_HPRT_PENCHNG (*((volatile unsigned int*)(0x4380880CUL))) +#define bM4_USBFS_HPRT_PRES (*((volatile unsigned int*)(0x43808818UL))) +#define bM4_USBFS_HPRT_PSUSP (*((volatile unsigned int*)(0x4380881CUL))) +#define bM4_USBFS_HPRT_PRST (*((volatile unsigned int*)(0x43808820UL))) +#define bM4_USBFS_HPRT_PLSTS0 (*((volatile unsigned int*)(0x43808828UL))) +#define bM4_USBFS_HPRT_PLSTS1 (*((volatile unsigned int*)(0x4380882CUL))) +#define bM4_USBFS_HPRT_PWPR (*((volatile unsigned int*)(0x43808830UL))) +#define bM4_USBFS_HPRT_PSPD0 (*((volatile unsigned int*)(0x43808844UL))) +#define bM4_USBFS_HPRT_PSPD1 (*((volatile unsigned int*)(0x43808848UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ0 (*((volatile unsigned int*)(0x4380A000UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ1 (*((volatile unsigned int*)(0x4380A004UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ2 (*((volatile unsigned int*)(0x4380A008UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ3 (*((volatile unsigned int*)(0x4380A00CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ4 (*((volatile unsigned int*)(0x4380A010UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ5 (*((volatile unsigned int*)(0x4380A014UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ6 (*((volatile unsigned int*)(0x4380A018UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ7 (*((volatile unsigned int*)(0x4380A01CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ8 (*((volatile unsigned int*)(0x4380A020UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ9 (*((volatile unsigned int*)(0x4380A024UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ10 (*((volatile unsigned int*)(0x4380A028UL))) +#define bM4_USBFS_HCCHAR0_EPNUM0 (*((volatile unsigned int*)(0x4380A02CUL))) +#define bM4_USBFS_HCCHAR0_EPNUM1 (*((volatile unsigned int*)(0x4380A030UL))) +#define bM4_USBFS_HCCHAR0_EPNUM2 (*((volatile unsigned int*)(0x4380A034UL))) +#define bM4_USBFS_HCCHAR0_EPNUM3 (*((volatile unsigned int*)(0x4380A038UL))) +#define bM4_USBFS_HCCHAR0_EPDIR (*((volatile unsigned int*)(0x4380A03CUL))) +#define bM4_USBFS_HCCHAR0_LSDEV (*((volatile unsigned int*)(0x4380A044UL))) +#define bM4_USBFS_HCCHAR0_EPTYP0 (*((volatile unsigned int*)(0x4380A048UL))) +#define bM4_USBFS_HCCHAR0_EPTYP1 (*((volatile unsigned int*)(0x4380A04CUL))) +#define bM4_USBFS_HCCHAR0_DAD0 (*((volatile unsigned int*)(0x4380A058UL))) +#define bM4_USBFS_HCCHAR0_DAD1 (*((volatile unsigned int*)(0x4380A05CUL))) +#define bM4_USBFS_HCCHAR0_DAD2 (*((volatile unsigned int*)(0x4380A060UL))) +#define bM4_USBFS_HCCHAR0_DAD3 (*((volatile unsigned int*)(0x4380A064UL))) +#define bM4_USBFS_HCCHAR0_DAD4 (*((volatile unsigned int*)(0x4380A068UL))) +#define bM4_USBFS_HCCHAR0_DAD5 (*((volatile unsigned int*)(0x4380A06CUL))) +#define bM4_USBFS_HCCHAR0_DAD6 (*((volatile unsigned int*)(0x4380A070UL))) +#define bM4_USBFS_HCCHAR0_ODDFRM (*((volatile unsigned int*)(0x4380A074UL))) +#define bM4_USBFS_HCCHAR0_CHDIS (*((volatile unsigned int*)(0x4380A078UL))) +#define bM4_USBFS_HCCHAR0_CHENA (*((volatile unsigned int*)(0x4380A07CUL))) +#define bM4_USBFS_HCINT0_XFRC (*((volatile unsigned int*)(0x4380A100UL))) +#define bM4_USBFS_HCINT0_CHH (*((volatile unsigned int*)(0x4380A104UL))) +#define bM4_USBFS_HCINT0_STALL (*((volatile unsigned int*)(0x4380A10CUL))) +#define bM4_USBFS_HCINT0_NAK (*((volatile unsigned int*)(0x4380A110UL))) +#define bM4_USBFS_HCINT0_ACK (*((volatile unsigned int*)(0x4380A114UL))) +#define bM4_USBFS_HCINT0_TXERR (*((volatile unsigned int*)(0x4380A11CUL))) +#define bM4_USBFS_HCINT0_BBERR (*((volatile unsigned int*)(0x4380A120UL))) +#define bM4_USBFS_HCINT0_FRMOR (*((volatile unsigned int*)(0x4380A124UL))) +#define bM4_USBFS_HCINT0_DTERR (*((volatile unsigned int*)(0x4380A128UL))) +#define bM4_USBFS_HCINTMSK0_XFRCM (*((volatile unsigned int*)(0x4380A180UL))) +#define bM4_USBFS_HCINTMSK0_CHHM (*((volatile unsigned int*)(0x4380A184UL))) +#define bM4_USBFS_HCINTMSK0_STALLM (*((volatile unsigned int*)(0x4380A18CUL))) +#define bM4_USBFS_HCINTMSK0_NAKM (*((volatile unsigned int*)(0x4380A190UL))) +#define bM4_USBFS_HCINTMSK0_ACKM (*((volatile unsigned int*)(0x4380A194UL))) +#define bM4_USBFS_HCINTMSK0_TXERRM (*((volatile unsigned int*)(0x4380A19CUL))) +#define bM4_USBFS_HCINTMSK0_BBERRM (*((volatile unsigned int*)(0x4380A1A0UL))) +#define bM4_USBFS_HCINTMSK0_FRMORM (*((volatile unsigned int*)(0x4380A1A4UL))) +#define bM4_USBFS_HCINTMSK0_DTERRM (*((volatile unsigned int*)(0x4380A1A8UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x4380A200UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x4380A204UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x4380A208UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4380A20CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x4380A210UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x4380A214UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x4380A218UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ7 (*((volatile unsigned int*)(0x4380A21CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ8 (*((volatile unsigned int*)(0x4380A220UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ9 (*((volatile unsigned int*)(0x4380A224UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ10 (*((volatile unsigned int*)(0x4380A228UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ11 (*((volatile unsigned int*)(0x4380A22CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ12 (*((volatile unsigned int*)(0x4380A230UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ13 (*((volatile unsigned int*)(0x4380A234UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ14 (*((volatile unsigned int*)(0x4380A238UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ15 (*((volatile unsigned int*)(0x4380A23CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ16 (*((volatile unsigned int*)(0x4380A240UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ17 (*((volatile unsigned int*)(0x4380A244UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ18 (*((volatile unsigned int*)(0x4380A248UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4380A24CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x4380A250UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT2 (*((volatile unsigned int*)(0x4380A254UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT3 (*((volatile unsigned int*)(0x4380A258UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT4 (*((volatile unsigned int*)(0x4380A25CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT5 (*((volatile unsigned int*)(0x4380A260UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT6 (*((volatile unsigned int*)(0x4380A264UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT7 (*((volatile unsigned int*)(0x4380A268UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT8 (*((volatile unsigned int*)(0x4380A26CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT9 (*((volatile unsigned int*)(0x4380A270UL))) +#define bM4_USBFS_HCTSIZ0_DPID0 (*((volatile unsigned int*)(0x4380A274UL))) +#define bM4_USBFS_HCTSIZ0_DPID1 (*((volatile unsigned int*)(0x4380A278UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ0 (*((volatile unsigned int*)(0x4380A400UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ1 (*((volatile unsigned int*)(0x4380A404UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ2 (*((volatile unsigned int*)(0x4380A408UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ3 (*((volatile unsigned int*)(0x4380A40CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ4 (*((volatile unsigned int*)(0x4380A410UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ5 (*((volatile unsigned int*)(0x4380A414UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ6 (*((volatile unsigned int*)(0x4380A418UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ7 (*((volatile unsigned int*)(0x4380A41CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ8 (*((volatile unsigned int*)(0x4380A420UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ9 (*((volatile unsigned int*)(0x4380A424UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ10 (*((volatile unsigned int*)(0x4380A428UL))) +#define bM4_USBFS_HCCHAR1_EPNUM0 (*((volatile unsigned int*)(0x4380A42CUL))) +#define bM4_USBFS_HCCHAR1_EPNUM1 (*((volatile unsigned int*)(0x4380A430UL))) +#define bM4_USBFS_HCCHAR1_EPNUM2 (*((volatile unsigned int*)(0x4380A434UL))) +#define bM4_USBFS_HCCHAR1_EPNUM3 (*((volatile unsigned int*)(0x4380A438UL))) +#define bM4_USBFS_HCCHAR1_EPDIR (*((volatile unsigned int*)(0x4380A43CUL))) +#define bM4_USBFS_HCCHAR1_LSDEV (*((volatile unsigned int*)(0x4380A444UL))) +#define bM4_USBFS_HCCHAR1_EPTYP0 (*((volatile unsigned int*)(0x4380A448UL))) +#define bM4_USBFS_HCCHAR1_EPTYP1 (*((volatile unsigned int*)(0x4380A44CUL))) +#define bM4_USBFS_HCCHAR1_DAD0 (*((volatile unsigned int*)(0x4380A458UL))) +#define bM4_USBFS_HCCHAR1_DAD1 (*((volatile unsigned int*)(0x4380A45CUL))) +#define bM4_USBFS_HCCHAR1_DAD2 (*((volatile unsigned int*)(0x4380A460UL))) +#define bM4_USBFS_HCCHAR1_DAD3 (*((volatile unsigned int*)(0x4380A464UL))) +#define bM4_USBFS_HCCHAR1_DAD4 (*((volatile unsigned int*)(0x4380A468UL))) +#define bM4_USBFS_HCCHAR1_DAD5 (*((volatile unsigned int*)(0x4380A46CUL))) +#define bM4_USBFS_HCCHAR1_DAD6 (*((volatile unsigned int*)(0x4380A470UL))) +#define bM4_USBFS_HCCHAR1_ODDFRM (*((volatile unsigned int*)(0x4380A474UL))) +#define bM4_USBFS_HCCHAR1_CHDIS (*((volatile unsigned int*)(0x4380A478UL))) +#define bM4_USBFS_HCCHAR1_CHENA (*((volatile unsigned int*)(0x4380A47CUL))) +#define bM4_USBFS_HCINT1_XFRC (*((volatile unsigned int*)(0x4380A500UL))) +#define bM4_USBFS_HCINT1_CHH (*((volatile unsigned int*)(0x4380A504UL))) +#define bM4_USBFS_HCINT1_STALL (*((volatile unsigned int*)(0x4380A50CUL))) +#define bM4_USBFS_HCINT1_NAK (*((volatile unsigned int*)(0x4380A510UL))) +#define bM4_USBFS_HCINT1_ACK (*((volatile unsigned int*)(0x4380A514UL))) +#define bM4_USBFS_HCINT1_TXERR (*((volatile unsigned int*)(0x4380A51CUL))) +#define bM4_USBFS_HCINT1_BBERR (*((volatile unsigned int*)(0x4380A520UL))) +#define bM4_USBFS_HCINT1_FRMOR (*((volatile unsigned int*)(0x4380A524UL))) +#define bM4_USBFS_HCINT1_DTERR (*((volatile unsigned int*)(0x4380A528UL))) +#define bM4_USBFS_HCINTMSK1_XFRCM (*((volatile unsigned int*)(0x4380A580UL))) +#define bM4_USBFS_HCINTMSK1_CHHM (*((volatile unsigned int*)(0x4380A584UL))) +#define bM4_USBFS_HCINTMSK1_STALLM (*((volatile unsigned int*)(0x4380A58CUL))) +#define bM4_USBFS_HCINTMSK1_NAKM (*((volatile unsigned int*)(0x4380A590UL))) +#define bM4_USBFS_HCINTMSK1_ACKM (*((volatile unsigned int*)(0x4380A594UL))) +#define bM4_USBFS_HCINTMSK1_TXERRM (*((volatile unsigned int*)(0x4380A59CUL))) +#define bM4_USBFS_HCINTMSK1_BBERRM (*((volatile unsigned int*)(0x4380A5A0UL))) +#define bM4_USBFS_HCINTMSK1_FRMORM (*((volatile unsigned int*)(0x4380A5A4UL))) +#define bM4_USBFS_HCINTMSK1_DTERRM (*((volatile unsigned int*)(0x4380A5A8UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x4380A600UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x4380A604UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x4380A608UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4380A60CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x4380A610UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x4380A614UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x4380A618UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4380A61CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x4380A620UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x4380A624UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x4380A628UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4380A62CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x4380A630UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x4380A634UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x4380A638UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4380A63CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x4380A640UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x4380A644UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x4380A648UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4380A64CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x4380A650UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x4380A654UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x4380A658UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4380A65CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x4380A660UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x4380A664UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x4380A668UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4380A66CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x4380A670UL))) +#define bM4_USBFS_HCTSIZ1_DPID0 (*((volatile unsigned int*)(0x4380A674UL))) +#define bM4_USBFS_HCTSIZ1_DPID1 (*((volatile unsigned int*)(0x4380A678UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ0 (*((volatile unsigned int*)(0x4380A800UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ1 (*((volatile unsigned int*)(0x4380A804UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ2 (*((volatile unsigned int*)(0x4380A808UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ3 (*((volatile unsigned int*)(0x4380A80CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ4 (*((volatile unsigned int*)(0x4380A810UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ5 (*((volatile unsigned int*)(0x4380A814UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ6 (*((volatile unsigned int*)(0x4380A818UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ7 (*((volatile unsigned int*)(0x4380A81CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ8 (*((volatile unsigned int*)(0x4380A820UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ9 (*((volatile unsigned int*)(0x4380A824UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ10 (*((volatile unsigned int*)(0x4380A828UL))) +#define bM4_USBFS_HCCHAR2_EPNUM0 (*((volatile unsigned int*)(0x4380A82CUL))) +#define bM4_USBFS_HCCHAR2_EPNUM1 (*((volatile unsigned int*)(0x4380A830UL))) +#define bM4_USBFS_HCCHAR2_EPNUM2 (*((volatile unsigned int*)(0x4380A834UL))) +#define bM4_USBFS_HCCHAR2_EPNUM3 (*((volatile unsigned int*)(0x4380A838UL))) +#define bM4_USBFS_HCCHAR2_EPDIR (*((volatile unsigned int*)(0x4380A83CUL))) +#define bM4_USBFS_HCCHAR2_LSDEV (*((volatile unsigned int*)(0x4380A844UL))) +#define bM4_USBFS_HCCHAR2_EPTYP0 (*((volatile unsigned int*)(0x4380A848UL))) +#define bM4_USBFS_HCCHAR2_EPTYP1 (*((volatile unsigned int*)(0x4380A84CUL))) +#define bM4_USBFS_HCCHAR2_DAD0 (*((volatile unsigned int*)(0x4380A858UL))) +#define bM4_USBFS_HCCHAR2_DAD1 (*((volatile unsigned int*)(0x4380A85CUL))) +#define bM4_USBFS_HCCHAR2_DAD2 (*((volatile unsigned int*)(0x4380A860UL))) +#define bM4_USBFS_HCCHAR2_DAD3 (*((volatile unsigned int*)(0x4380A864UL))) +#define bM4_USBFS_HCCHAR2_DAD4 (*((volatile unsigned int*)(0x4380A868UL))) +#define bM4_USBFS_HCCHAR2_DAD5 (*((volatile unsigned int*)(0x4380A86CUL))) +#define bM4_USBFS_HCCHAR2_DAD6 (*((volatile unsigned int*)(0x4380A870UL))) +#define bM4_USBFS_HCCHAR2_ODDFRM (*((volatile unsigned int*)(0x4380A874UL))) +#define bM4_USBFS_HCCHAR2_CHDIS (*((volatile unsigned int*)(0x4380A878UL))) +#define bM4_USBFS_HCCHAR2_CHENA (*((volatile unsigned int*)(0x4380A87CUL))) +#define bM4_USBFS_HCINT2_XFRC (*((volatile unsigned int*)(0x4380A900UL))) +#define bM4_USBFS_HCINT2_CHH (*((volatile unsigned int*)(0x4380A904UL))) +#define bM4_USBFS_HCINT2_STALL (*((volatile unsigned int*)(0x4380A90CUL))) +#define bM4_USBFS_HCINT2_NAK (*((volatile unsigned int*)(0x4380A910UL))) +#define bM4_USBFS_HCINT2_ACK (*((volatile unsigned int*)(0x4380A914UL))) +#define bM4_USBFS_HCINT2_TXERR (*((volatile unsigned int*)(0x4380A91CUL))) +#define bM4_USBFS_HCINT2_BBERR (*((volatile unsigned int*)(0x4380A920UL))) +#define bM4_USBFS_HCINT2_FRMOR (*((volatile unsigned int*)(0x4380A924UL))) +#define bM4_USBFS_HCINT2_DTERR (*((volatile unsigned int*)(0x4380A928UL))) +#define bM4_USBFS_HCINTMSK2_XFRCM (*((volatile unsigned int*)(0x4380A980UL))) +#define bM4_USBFS_HCINTMSK2_CHHM (*((volatile unsigned int*)(0x4380A984UL))) +#define bM4_USBFS_HCINTMSK2_STALLM (*((volatile unsigned int*)(0x4380A98CUL))) +#define bM4_USBFS_HCINTMSK2_NAKM (*((volatile unsigned int*)(0x4380A990UL))) +#define bM4_USBFS_HCINTMSK2_ACKM (*((volatile unsigned int*)(0x4380A994UL))) +#define bM4_USBFS_HCINTMSK2_TXERRM (*((volatile unsigned int*)(0x4380A99CUL))) +#define bM4_USBFS_HCINTMSK2_BBERRM (*((volatile unsigned int*)(0x4380A9A0UL))) +#define bM4_USBFS_HCINTMSK2_FRMORM (*((volatile unsigned int*)(0x4380A9A4UL))) +#define bM4_USBFS_HCINTMSK2_DTERRM (*((volatile unsigned int*)(0x4380A9A8UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x4380AA00UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x4380AA04UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x4380AA08UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x4380AA0CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x4380AA10UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x4380AA14UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x4380AA18UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x4380AA1CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x4380AA20UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x4380AA24UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x4380AA28UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x4380AA2CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x4380AA30UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x4380AA34UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x4380AA38UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x4380AA3CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x4380AA40UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x4380AA44UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x4380AA48UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x4380AA4CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x4380AA50UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x4380AA54UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x4380AA58UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x4380AA5CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x4380AA60UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x4380AA64UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x4380AA68UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x4380AA6CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x4380AA70UL))) +#define bM4_USBFS_HCTSIZ2_DPID0 (*((volatile unsigned int*)(0x4380AA74UL))) +#define bM4_USBFS_HCTSIZ2_DPID1 (*((volatile unsigned int*)(0x4380AA78UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ0 (*((volatile unsigned int*)(0x4380AC00UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ1 (*((volatile unsigned int*)(0x4380AC04UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ2 (*((volatile unsigned int*)(0x4380AC08UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ3 (*((volatile unsigned int*)(0x4380AC0CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ4 (*((volatile unsigned int*)(0x4380AC10UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ5 (*((volatile unsigned int*)(0x4380AC14UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ6 (*((volatile unsigned int*)(0x4380AC18UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ7 (*((volatile unsigned int*)(0x4380AC1CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ8 (*((volatile unsigned int*)(0x4380AC20UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ9 (*((volatile unsigned int*)(0x4380AC24UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ10 (*((volatile unsigned int*)(0x4380AC28UL))) +#define bM4_USBFS_HCCHAR3_EPNUM0 (*((volatile unsigned int*)(0x4380AC2CUL))) +#define bM4_USBFS_HCCHAR3_EPNUM1 (*((volatile unsigned int*)(0x4380AC30UL))) +#define bM4_USBFS_HCCHAR3_EPNUM2 (*((volatile unsigned int*)(0x4380AC34UL))) +#define bM4_USBFS_HCCHAR3_EPNUM3 (*((volatile unsigned int*)(0x4380AC38UL))) +#define bM4_USBFS_HCCHAR3_EPDIR (*((volatile unsigned int*)(0x4380AC3CUL))) +#define bM4_USBFS_HCCHAR3_LSDEV (*((volatile unsigned int*)(0x4380AC44UL))) +#define bM4_USBFS_HCCHAR3_EPTYP0 (*((volatile unsigned int*)(0x4380AC48UL))) +#define bM4_USBFS_HCCHAR3_EPTYP1 (*((volatile unsigned int*)(0x4380AC4CUL))) +#define bM4_USBFS_HCCHAR3_DAD0 (*((volatile unsigned int*)(0x4380AC58UL))) +#define bM4_USBFS_HCCHAR3_DAD1 (*((volatile unsigned int*)(0x4380AC5CUL))) +#define bM4_USBFS_HCCHAR3_DAD2 (*((volatile unsigned int*)(0x4380AC60UL))) +#define bM4_USBFS_HCCHAR3_DAD3 (*((volatile unsigned int*)(0x4380AC64UL))) +#define bM4_USBFS_HCCHAR3_DAD4 (*((volatile unsigned int*)(0x4380AC68UL))) +#define bM4_USBFS_HCCHAR3_DAD5 (*((volatile unsigned int*)(0x4380AC6CUL))) +#define bM4_USBFS_HCCHAR3_DAD6 (*((volatile unsigned int*)(0x4380AC70UL))) +#define bM4_USBFS_HCCHAR3_ODDFRM (*((volatile unsigned int*)(0x4380AC74UL))) +#define bM4_USBFS_HCCHAR3_CHDIS (*((volatile unsigned int*)(0x4380AC78UL))) +#define bM4_USBFS_HCCHAR3_CHENA (*((volatile unsigned int*)(0x4380AC7CUL))) +#define bM4_USBFS_HCINT3_XFRC (*((volatile unsigned int*)(0x4380AD00UL))) +#define bM4_USBFS_HCINT3_CHH (*((volatile unsigned int*)(0x4380AD04UL))) +#define bM4_USBFS_HCINT3_STALL (*((volatile unsigned int*)(0x4380AD0CUL))) +#define bM4_USBFS_HCINT3_NAK (*((volatile unsigned int*)(0x4380AD10UL))) +#define bM4_USBFS_HCINT3_ACK (*((volatile unsigned int*)(0x4380AD14UL))) +#define bM4_USBFS_HCINT3_TXERR (*((volatile unsigned int*)(0x4380AD1CUL))) +#define bM4_USBFS_HCINT3_BBERR (*((volatile unsigned int*)(0x4380AD20UL))) +#define bM4_USBFS_HCINT3_FRMOR (*((volatile unsigned int*)(0x4380AD24UL))) +#define bM4_USBFS_HCINT3_DTERR (*((volatile unsigned int*)(0x4380AD28UL))) +#define bM4_USBFS_HCINTMSK3_XFRCM (*((volatile unsigned int*)(0x4380AD80UL))) +#define bM4_USBFS_HCINTMSK3_CHHM (*((volatile unsigned int*)(0x4380AD84UL))) +#define bM4_USBFS_HCINTMSK3_STALLM (*((volatile unsigned int*)(0x4380AD8CUL))) +#define bM4_USBFS_HCINTMSK3_NAKM (*((volatile unsigned int*)(0x4380AD90UL))) +#define bM4_USBFS_HCINTMSK3_ACKM (*((volatile unsigned int*)(0x4380AD94UL))) +#define bM4_USBFS_HCINTMSK3_TXERRM (*((volatile unsigned int*)(0x4380AD9CUL))) +#define bM4_USBFS_HCINTMSK3_BBERRM (*((volatile unsigned int*)(0x4380ADA0UL))) +#define bM4_USBFS_HCINTMSK3_FRMORM (*((volatile unsigned int*)(0x4380ADA4UL))) +#define bM4_USBFS_HCINTMSK3_DTERRM (*((volatile unsigned int*)(0x4380ADA8UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x4380AE00UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x4380AE04UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x4380AE08UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x4380AE0CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x4380AE10UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x4380AE14UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x4380AE18UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x4380AE1CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x4380AE20UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x4380AE24UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x4380AE28UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x4380AE2CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x4380AE30UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x4380AE34UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x4380AE38UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x4380AE3CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x4380AE40UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x4380AE44UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x4380AE48UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x4380AE4CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x4380AE50UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x4380AE54UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x4380AE58UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x4380AE5CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x4380AE60UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x4380AE64UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x4380AE68UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x4380AE6CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x4380AE70UL))) +#define bM4_USBFS_HCTSIZ3_DPID0 (*((volatile unsigned int*)(0x4380AE74UL))) +#define bM4_USBFS_HCTSIZ3_DPID1 (*((volatile unsigned int*)(0x4380AE78UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ0 (*((volatile unsigned int*)(0x4380B000UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ1 (*((volatile unsigned int*)(0x4380B004UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ2 (*((volatile unsigned int*)(0x4380B008UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ3 (*((volatile unsigned int*)(0x4380B00CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ4 (*((volatile unsigned int*)(0x4380B010UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ5 (*((volatile unsigned int*)(0x4380B014UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ6 (*((volatile unsigned int*)(0x4380B018UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ7 (*((volatile unsigned int*)(0x4380B01CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ8 (*((volatile unsigned int*)(0x4380B020UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ9 (*((volatile unsigned int*)(0x4380B024UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ10 (*((volatile unsigned int*)(0x4380B028UL))) +#define bM4_USBFS_HCCHAR4_EPNUM0 (*((volatile unsigned int*)(0x4380B02CUL))) +#define bM4_USBFS_HCCHAR4_EPNUM1 (*((volatile unsigned int*)(0x4380B030UL))) +#define bM4_USBFS_HCCHAR4_EPNUM2 (*((volatile unsigned int*)(0x4380B034UL))) +#define bM4_USBFS_HCCHAR4_EPNUM3 (*((volatile unsigned int*)(0x4380B038UL))) +#define bM4_USBFS_HCCHAR4_EPDIR (*((volatile unsigned int*)(0x4380B03CUL))) +#define bM4_USBFS_HCCHAR4_LSDEV (*((volatile unsigned int*)(0x4380B044UL))) +#define bM4_USBFS_HCCHAR4_EPTYP0 (*((volatile unsigned int*)(0x4380B048UL))) +#define bM4_USBFS_HCCHAR4_EPTYP1 (*((volatile unsigned int*)(0x4380B04CUL))) +#define bM4_USBFS_HCCHAR4_DAD0 (*((volatile unsigned int*)(0x4380B058UL))) +#define bM4_USBFS_HCCHAR4_DAD1 (*((volatile unsigned int*)(0x4380B05CUL))) +#define bM4_USBFS_HCCHAR4_DAD2 (*((volatile unsigned int*)(0x4380B060UL))) +#define bM4_USBFS_HCCHAR4_DAD3 (*((volatile unsigned int*)(0x4380B064UL))) +#define bM4_USBFS_HCCHAR4_DAD4 (*((volatile unsigned int*)(0x4380B068UL))) +#define bM4_USBFS_HCCHAR4_DAD5 (*((volatile unsigned int*)(0x4380B06CUL))) +#define bM4_USBFS_HCCHAR4_DAD6 (*((volatile unsigned int*)(0x4380B070UL))) +#define bM4_USBFS_HCCHAR4_ODDFRM (*((volatile unsigned int*)(0x4380B074UL))) +#define bM4_USBFS_HCCHAR4_CHDIS (*((volatile unsigned int*)(0x4380B078UL))) +#define bM4_USBFS_HCCHAR4_CHENA (*((volatile unsigned int*)(0x4380B07CUL))) +#define bM4_USBFS_HCINT4_XFRC (*((volatile unsigned int*)(0x4380B100UL))) +#define bM4_USBFS_HCINT4_CHH (*((volatile unsigned int*)(0x4380B104UL))) +#define bM4_USBFS_HCINT4_STALL (*((volatile unsigned int*)(0x4380B10CUL))) +#define bM4_USBFS_HCINT4_NAK (*((volatile unsigned int*)(0x4380B110UL))) +#define bM4_USBFS_HCINT4_ACK (*((volatile unsigned int*)(0x4380B114UL))) +#define bM4_USBFS_HCINT4_TXERR (*((volatile unsigned int*)(0x4380B11CUL))) +#define bM4_USBFS_HCINT4_BBERR (*((volatile unsigned int*)(0x4380B120UL))) +#define bM4_USBFS_HCINT4_FRMOR (*((volatile unsigned int*)(0x4380B124UL))) +#define bM4_USBFS_HCINT4_DTERR (*((volatile unsigned int*)(0x4380B128UL))) +#define bM4_USBFS_HCINTMSK4_XFRCM (*((volatile unsigned int*)(0x4380B180UL))) +#define bM4_USBFS_HCINTMSK4_CHHM (*((volatile unsigned int*)(0x4380B184UL))) +#define bM4_USBFS_HCINTMSK4_STALLM (*((volatile unsigned int*)(0x4380B18CUL))) +#define bM4_USBFS_HCINTMSK4_NAKM (*((volatile unsigned int*)(0x4380B190UL))) +#define bM4_USBFS_HCINTMSK4_ACKM (*((volatile unsigned int*)(0x4380B194UL))) +#define bM4_USBFS_HCINTMSK4_TXERRM (*((volatile unsigned int*)(0x4380B19CUL))) +#define bM4_USBFS_HCINTMSK4_BBERRM (*((volatile unsigned int*)(0x4380B1A0UL))) +#define bM4_USBFS_HCINTMSK4_FRMORM (*((volatile unsigned int*)(0x4380B1A4UL))) +#define bM4_USBFS_HCINTMSK4_DTERRM (*((volatile unsigned int*)(0x4380B1A8UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x4380B200UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x4380B204UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x4380B208UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4380B20CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x4380B210UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x4380B214UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x4380B218UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4380B21CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x4380B220UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x4380B224UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x4380B228UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4380B22CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x4380B230UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x4380B234UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x4380B238UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4380B23CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x4380B240UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x4380B244UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x4380B248UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4380B24CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x4380B250UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x4380B254UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x4380B258UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4380B25CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x4380B260UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x4380B264UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x4380B268UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4380B26CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x4380B270UL))) +#define bM4_USBFS_HCTSIZ4_DPID0 (*((volatile unsigned int*)(0x4380B274UL))) +#define bM4_USBFS_HCTSIZ4_DPID1 (*((volatile unsigned int*)(0x4380B278UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ0 (*((volatile unsigned int*)(0x4380B400UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ1 (*((volatile unsigned int*)(0x4380B404UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ2 (*((volatile unsigned int*)(0x4380B408UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ3 (*((volatile unsigned int*)(0x4380B40CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ4 (*((volatile unsigned int*)(0x4380B410UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ5 (*((volatile unsigned int*)(0x4380B414UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ6 (*((volatile unsigned int*)(0x4380B418UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ7 (*((volatile unsigned int*)(0x4380B41CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ8 (*((volatile unsigned int*)(0x4380B420UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ9 (*((volatile unsigned int*)(0x4380B424UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ10 (*((volatile unsigned int*)(0x4380B428UL))) +#define bM4_USBFS_HCCHAR5_EPNUM0 (*((volatile unsigned int*)(0x4380B42CUL))) +#define bM4_USBFS_HCCHAR5_EPNUM1 (*((volatile unsigned int*)(0x4380B430UL))) +#define bM4_USBFS_HCCHAR5_EPNUM2 (*((volatile unsigned int*)(0x4380B434UL))) +#define bM4_USBFS_HCCHAR5_EPNUM3 (*((volatile unsigned int*)(0x4380B438UL))) +#define bM4_USBFS_HCCHAR5_EPDIR (*((volatile unsigned int*)(0x4380B43CUL))) +#define bM4_USBFS_HCCHAR5_LSDEV (*((volatile unsigned int*)(0x4380B444UL))) +#define bM4_USBFS_HCCHAR5_EPTYP0 (*((volatile unsigned int*)(0x4380B448UL))) +#define bM4_USBFS_HCCHAR5_EPTYP1 (*((volatile unsigned int*)(0x4380B44CUL))) +#define bM4_USBFS_HCCHAR5_DAD0 (*((volatile unsigned int*)(0x4380B458UL))) +#define bM4_USBFS_HCCHAR5_DAD1 (*((volatile unsigned int*)(0x4380B45CUL))) +#define bM4_USBFS_HCCHAR5_DAD2 (*((volatile unsigned int*)(0x4380B460UL))) +#define bM4_USBFS_HCCHAR5_DAD3 (*((volatile unsigned int*)(0x4380B464UL))) +#define bM4_USBFS_HCCHAR5_DAD4 (*((volatile unsigned int*)(0x4380B468UL))) +#define bM4_USBFS_HCCHAR5_DAD5 (*((volatile unsigned int*)(0x4380B46CUL))) +#define bM4_USBFS_HCCHAR5_DAD6 (*((volatile unsigned int*)(0x4380B470UL))) +#define bM4_USBFS_HCCHAR5_ODDFRM (*((volatile unsigned int*)(0x4380B474UL))) +#define bM4_USBFS_HCCHAR5_CHDIS (*((volatile unsigned int*)(0x4380B478UL))) +#define bM4_USBFS_HCCHAR5_CHENA (*((volatile unsigned int*)(0x4380B47CUL))) +#define bM4_USBFS_HCINT5_XFRC (*((volatile unsigned int*)(0x4380B500UL))) +#define bM4_USBFS_HCINT5_CHH (*((volatile unsigned int*)(0x4380B504UL))) +#define bM4_USBFS_HCINT5_STALL (*((volatile unsigned int*)(0x4380B50CUL))) +#define bM4_USBFS_HCINT5_NAK (*((volatile unsigned int*)(0x4380B510UL))) +#define bM4_USBFS_HCINT5_ACK (*((volatile unsigned int*)(0x4380B514UL))) +#define bM4_USBFS_HCINT5_TXERR (*((volatile unsigned int*)(0x4380B51CUL))) +#define bM4_USBFS_HCINT5_BBERR (*((volatile unsigned int*)(0x4380B520UL))) +#define bM4_USBFS_HCINT5_FRMOR (*((volatile unsigned int*)(0x4380B524UL))) +#define bM4_USBFS_HCINT5_DTERR (*((volatile unsigned int*)(0x4380B528UL))) +#define bM4_USBFS_HCINTMSK5_XFRCM (*((volatile unsigned int*)(0x4380B580UL))) +#define bM4_USBFS_HCINTMSK5_CHHM (*((volatile unsigned int*)(0x4380B584UL))) +#define bM4_USBFS_HCINTMSK5_STALLM (*((volatile unsigned int*)(0x4380B58CUL))) +#define bM4_USBFS_HCINTMSK5_NAKM (*((volatile unsigned int*)(0x4380B590UL))) +#define bM4_USBFS_HCINTMSK5_ACKM (*((volatile unsigned int*)(0x4380B594UL))) +#define bM4_USBFS_HCINTMSK5_TXERRM (*((volatile unsigned int*)(0x4380B59CUL))) +#define bM4_USBFS_HCINTMSK5_BBERRM (*((volatile unsigned int*)(0x4380B5A0UL))) +#define bM4_USBFS_HCINTMSK5_FRMORM (*((volatile unsigned int*)(0x4380B5A4UL))) +#define bM4_USBFS_HCINTMSK5_DTERRM (*((volatile unsigned int*)(0x4380B5A8UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x4380B600UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x4380B604UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x4380B608UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4380B60CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x4380B610UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x4380B614UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x4380B618UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4380B61CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x4380B620UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x4380B624UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x4380B628UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4380B62CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x4380B630UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x4380B634UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x4380B638UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4380B63CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x4380B640UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x4380B644UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x4380B648UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4380B64CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x4380B650UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x4380B654UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x4380B658UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4380B65CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x4380B660UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x4380B664UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x4380B668UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4380B66CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x4380B670UL))) +#define bM4_USBFS_HCTSIZ5_DPID0 (*((volatile unsigned int*)(0x4380B674UL))) +#define bM4_USBFS_HCTSIZ5_DPID1 (*((volatile unsigned int*)(0x4380B678UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ0 (*((volatile unsigned int*)(0x4380B800UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ1 (*((volatile unsigned int*)(0x4380B804UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ2 (*((volatile unsigned int*)(0x4380B808UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ3 (*((volatile unsigned int*)(0x4380B80CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ4 (*((volatile unsigned int*)(0x4380B810UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ5 (*((volatile unsigned int*)(0x4380B814UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ6 (*((volatile unsigned int*)(0x4380B818UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ7 (*((volatile unsigned int*)(0x4380B81CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ8 (*((volatile unsigned int*)(0x4380B820UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ9 (*((volatile unsigned int*)(0x4380B824UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ10 (*((volatile unsigned int*)(0x4380B828UL))) +#define bM4_USBFS_HCCHAR6_EPNUM0 (*((volatile unsigned int*)(0x4380B82CUL))) +#define bM4_USBFS_HCCHAR6_EPNUM1 (*((volatile unsigned int*)(0x4380B830UL))) +#define bM4_USBFS_HCCHAR6_EPNUM2 (*((volatile unsigned int*)(0x4380B834UL))) +#define bM4_USBFS_HCCHAR6_EPNUM3 (*((volatile unsigned int*)(0x4380B838UL))) +#define bM4_USBFS_HCCHAR6_EPDIR (*((volatile unsigned int*)(0x4380B83CUL))) +#define bM4_USBFS_HCCHAR6_LSDEV (*((volatile unsigned int*)(0x4380B844UL))) +#define bM4_USBFS_HCCHAR6_EPTYP0 (*((volatile unsigned int*)(0x4380B848UL))) +#define bM4_USBFS_HCCHAR6_EPTYP1 (*((volatile unsigned int*)(0x4380B84CUL))) +#define bM4_USBFS_HCCHAR6_DAD0 (*((volatile unsigned int*)(0x4380B858UL))) +#define bM4_USBFS_HCCHAR6_DAD1 (*((volatile unsigned int*)(0x4380B85CUL))) +#define bM4_USBFS_HCCHAR6_DAD2 (*((volatile unsigned int*)(0x4380B860UL))) +#define bM4_USBFS_HCCHAR6_DAD3 (*((volatile unsigned int*)(0x4380B864UL))) +#define bM4_USBFS_HCCHAR6_DAD4 (*((volatile unsigned int*)(0x4380B868UL))) +#define bM4_USBFS_HCCHAR6_DAD5 (*((volatile unsigned int*)(0x4380B86CUL))) +#define bM4_USBFS_HCCHAR6_DAD6 (*((volatile unsigned int*)(0x4380B870UL))) +#define bM4_USBFS_HCCHAR6_ODDFRM (*((volatile unsigned int*)(0x4380B874UL))) +#define bM4_USBFS_HCCHAR6_CHDIS (*((volatile unsigned int*)(0x4380B878UL))) +#define bM4_USBFS_HCCHAR6_CHENA (*((volatile unsigned int*)(0x4380B87CUL))) +#define bM4_USBFS_HCINT6_XFRC (*((volatile unsigned int*)(0x4380B900UL))) +#define bM4_USBFS_HCINT6_CHH (*((volatile unsigned int*)(0x4380B904UL))) +#define bM4_USBFS_HCINT6_STALL (*((volatile unsigned int*)(0x4380B90CUL))) +#define bM4_USBFS_HCINT6_NAK (*((volatile unsigned int*)(0x4380B910UL))) +#define bM4_USBFS_HCINT6_ACK (*((volatile unsigned int*)(0x4380B914UL))) +#define bM4_USBFS_HCINT6_TXERR (*((volatile unsigned int*)(0x4380B91CUL))) +#define bM4_USBFS_HCINT6_BBERR (*((volatile unsigned int*)(0x4380B920UL))) +#define bM4_USBFS_HCINT6_FRMOR (*((volatile unsigned int*)(0x4380B924UL))) +#define bM4_USBFS_HCINT6_DTERR (*((volatile unsigned int*)(0x4380B928UL))) +#define bM4_USBFS_HCINTMSK6_XFRCM (*((volatile unsigned int*)(0x4380B980UL))) +#define bM4_USBFS_HCINTMSK6_CHHM (*((volatile unsigned int*)(0x4380B984UL))) +#define bM4_USBFS_HCINTMSK6_STALLM (*((volatile unsigned int*)(0x4380B98CUL))) +#define bM4_USBFS_HCINTMSK6_NAKM (*((volatile unsigned int*)(0x4380B990UL))) +#define bM4_USBFS_HCINTMSK6_ACKM (*((volatile unsigned int*)(0x4380B994UL))) +#define bM4_USBFS_HCINTMSK6_TXERRM (*((volatile unsigned int*)(0x4380B99CUL))) +#define bM4_USBFS_HCINTMSK6_BBERRM (*((volatile unsigned int*)(0x4380B9A0UL))) +#define bM4_USBFS_HCINTMSK6_FRMORM (*((volatile unsigned int*)(0x4380B9A4UL))) +#define bM4_USBFS_HCINTMSK6_DTERRM (*((volatile unsigned int*)(0x4380B9A8UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ0 (*((volatile unsigned int*)(0x4380BA00UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ1 (*((volatile unsigned int*)(0x4380BA04UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ2 (*((volatile unsigned int*)(0x4380BA08UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ3 (*((volatile unsigned int*)(0x4380BA0CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ4 (*((volatile unsigned int*)(0x4380BA10UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ5 (*((volatile unsigned int*)(0x4380BA14UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ6 (*((volatile unsigned int*)(0x4380BA18UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ7 (*((volatile unsigned int*)(0x4380BA1CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ8 (*((volatile unsigned int*)(0x4380BA20UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ9 (*((volatile unsigned int*)(0x4380BA24UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ10 (*((volatile unsigned int*)(0x4380BA28UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ11 (*((volatile unsigned int*)(0x4380BA2CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ12 (*((volatile unsigned int*)(0x4380BA30UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ13 (*((volatile unsigned int*)(0x4380BA34UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ14 (*((volatile unsigned int*)(0x4380BA38UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ15 (*((volatile unsigned int*)(0x4380BA3CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ16 (*((volatile unsigned int*)(0x4380BA40UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ17 (*((volatile unsigned int*)(0x4380BA44UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ18 (*((volatile unsigned int*)(0x4380BA48UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT0 (*((volatile unsigned int*)(0x4380BA4CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT1 (*((volatile unsigned int*)(0x4380BA50UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT2 (*((volatile unsigned int*)(0x4380BA54UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT3 (*((volatile unsigned int*)(0x4380BA58UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT4 (*((volatile unsigned int*)(0x4380BA5CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT5 (*((volatile unsigned int*)(0x4380BA60UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT6 (*((volatile unsigned int*)(0x4380BA64UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT7 (*((volatile unsigned int*)(0x4380BA68UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT8 (*((volatile unsigned int*)(0x4380BA6CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT9 (*((volatile unsigned int*)(0x4380BA70UL))) +#define bM4_USBFS_HCTSIZ6_DPID0 (*((volatile unsigned int*)(0x4380BA74UL))) +#define bM4_USBFS_HCTSIZ6_DPID1 (*((volatile unsigned int*)(0x4380BA78UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ0 (*((volatile unsigned int*)(0x4380BC00UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ1 (*((volatile unsigned int*)(0x4380BC04UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ2 (*((volatile unsigned int*)(0x4380BC08UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ3 (*((volatile unsigned int*)(0x4380BC0CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ4 (*((volatile unsigned int*)(0x4380BC10UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ5 (*((volatile unsigned int*)(0x4380BC14UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ6 (*((volatile unsigned int*)(0x4380BC18UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ7 (*((volatile unsigned int*)(0x4380BC1CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ8 (*((volatile unsigned int*)(0x4380BC20UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ9 (*((volatile unsigned int*)(0x4380BC24UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ10 (*((volatile unsigned int*)(0x4380BC28UL))) +#define bM4_USBFS_HCCHAR7_EPNUM0 (*((volatile unsigned int*)(0x4380BC2CUL))) +#define bM4_USBFS_HCCHAR7_EPNUM1 (*((volatile unsigned int*)(0x4380BC30UL))) +#define bM4_USBFS_HCCHAR7_EPNUM2 (*((volatile unsigned int*)(0x4380BC34UL))) +#define bM4_USBFS_HCCHAR7_EPNUM3 (*((volatile unsigned int*)(0x4380BC38UL))) +#define bM4_USBFS_HCCHAR7_EPDIR (*((volatile unsigned int*)(0x4380BC3CUL))) +#define bM4_USBFS_HCCHAR7_LSDEV (*((volatile unsigned int*)(0x4380BC44UL))) +#define bM4_USBFS_HCCHAR7_EPTYP0 (*((volatile unsigned int*)(0x4380BC48UL))) +#define bM4_USBFS_HCCHAR7_EPTYP1 (*((volatile unsigned int*)(0x4380BC4CUL))) +#define bM4_USBFS_HCCHAR7_DAD0 (*((volatile unsigned int*)(0x4380BC58UL))) +#define bM4_USBFS_HCCHAR7_DAD1 (*((volatile unsigned int*)(0x4380BC5CUL))) +#define bM4_USBFS_HCCHAR7_DAD2 (*((volatile unsigned int*)(0x4380BC60UL))) +#define bM4_USBFS_HCCHAR7_DAD3 (*((volatile unsigned int*)(0x4380BC64UL))) +#define bM4_USBFS_HCCHAR7_DAD4 (*((volatile unsigned int*)(0x4380BC68UL))) +#define bM4_USBFS_HCCHAR7_DAD5 (*((volatile unsigned int*)(0x4380BC6CUL))) +#define bM4_USBFS_HCCHAR7_DAD6 (*((volatile unsigned int*)(0x4380BC70UL))) +#define bM4_USBFS_HCCHAR7_ODDFRM (*((volatile unsigned int*)(0x4380BC74UL))) +#define bM4_USBFS_HCCHAR7_CHDIS (*((volatile unsigned int*)(0x4380BC78UL))) +#define bM4_USBFS_HCCHAR7_CHENA (*((volatile unsigned int*)(0x4380BC7CUL))) +#define bM4_USBFS_HCINT7_XFRC (*((volatile unsigned int*)(0x4380BD00UL))) +#define bM4_USBFS_HCINT7_CHH (*((volatile unsigned int*)(0x4380BD04UL))) +#define bM4_USBFS_HCINT7_STALL (*((volatile unsigned int*)(0x4380BD0CUL))) +#define bM4_USBFS_HCINT7_NAK (*((volatile unsigned int*)(0x4380BD10UL))) +#define bM4_USBFS_HCINT7_ACK (*((volatile unsigned int*)(0x4380BD14UL))) +#define bM4_USBFS_HCINT7_TXERR (*((volatile unsigned int*)(0x4380BD1CUL))) +#define bM4_USBFS_HCINT7_BBERR (*((volatile unsigned int*)(0x4380BD20UL))) +#define bM4_USBFS_HCINT7_FRMOR (*((volatile unsigned int*)(0x4380BD24UL))) +#define bM4_USBFS_HCINT7_DTERR (*((volatile unsigned int*)(0x4380BD28UL))) +#define bM4_USBFS_HCINTMSK7_XFRCM (*((volatile unsigned int*)(0x4380BD80UL))) +#define bM4_USBFS_HCINTMSK7_CHHM (*((volatile unsigned int*)(0x4380BD84UL))) +#define bM4_USBFS_HCINTMSK7_STALLM (*((volatile unsigned int*)(0x4380BD8CUL))) +#define bM4_USBFS_HCINTMSK7_NAKM (*((volatile unsigned int*)(0x4380BD90UL))) +#define bM4_USBFS_HCINTMSK7_ACKM (*((volatile unsigned int*)(0x4380BD94UL))) +#define bM4_USBFS_HCINTMSK7_TXERRM (*((volatile unsigned int*)(0x4380BD9CUL))) +#define bM4_USBFS_HCINTMSK7_BBERRM (*((volatile unsigned int*)(0x4380BDA0UL))) +#define bM4_USBFS_HCINTMSK7_FRMORM (*((volatile unsigned int*)(0x4380BDA4UL))) +#define bM4_USBFS_HCINTMSK7_DTERRM (*((volatile unsigned int*)(0x4380BDA8UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ0 (*((volatile unsigned int*)(0x4380BE00UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ1 (*((volatile unsigned int*)(0x4380BE04UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ2 (*((volatile unsigned int*)(0x4380BE08UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ3 (*((volatile unsigned int*)(0x4380BE0CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ4 (*((volatile unsigned int*)(0x4380BE10UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ5 (*((volatile unsigned int*)(0x4380BE14UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ6 (*((volatile unsigned int*)(0x4380BE18UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ7 (*((volatile unsigned int*)(0x4380BE1CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ8 (*((volatile unsigned int*)(0x4380BE20UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ9 (*((volatile unsigned int*)(0x4380BE24UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ10 (*((volatile unsigned int*)(0x4380BE28UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ11 (*((volatile unsigned int*)(0x4380BE2CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ12 (*((volatile unsigned int*)(0x4380BE30UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ13 (*((volatile unsigned int*)(0x4380BE34UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ14 (*((volatile unsigned int*)(0x4380BE38UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ15 (*((volatile unsigned int*)(0x4380BE3CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ16 (*((volatile unsigned int*)(0x4380BE40UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ17 (*((volatile unsigned int*)(0x4380BE44UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ18 (*((volatile unsigned int*)(0x4380BE48UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT0 (*((volatile unsigned int*)(0x4380BE4CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT1 (*((volatile unsigned int*)(0x4380BE50UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT2 (*((volatile unsigned int*)(0x4380BE54UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT3 (*((volatile unsigned int*)(0x4380BE58UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT4 (*((volatile unsigned int*)(0x4380BE5CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT5 (*((volatile unsigned int*)(0x4380BE60UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT6 (*((volatile unsigned int*)(0x4380BE64UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT7 (*((volatile unsigned int*)(0x4380BE68UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT8 (*((volatile unsigned int*)(0x4380BE6CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT9 (*((volatile unsigned int*)(0x4380BE70UL))) +#define bM4_USBFS_HCTSIZ7_DPID0 (*((volatile unsigned int*)(0x4380BE74UL))) +#define bM4_USBFS_HCTSIZ7_DPID1 (*((volatile unsigned int*)(0x4380BE78UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ0 (*((volatile unsigned int*)(0x4380C000UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ1 (*((volatile unsigned int*)(0x4380C004UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ2 (*((volatile unsigned int*)(0x4380C008UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ3 (*((volatile unsigned int*)(0x4380C00CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ4 (*((volatile unsigned int*)(0x4380C010UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ5 (*((volatile unsigned int*)(0x4380C014UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ6 (*((volatile unsigned int*)(0x4380C018UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ7 (*((volatile unsigned int*)(0x4380C01CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ8 (*((volatile unsigned int*)(0x4380C020UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ9 (*((volatile unsigned int*)(0x4380C024UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ10 (*((volatile unsigned int*)(0x4380C028UL))) +#define bM4_USBFS_HCCHAR8_EPNUM0 (*((volatile unsigned int*)(0x4380C02CUL))) +#define bM4_USBFS_HCCHAR8_EPNUM1 (*((volatile unsigned int*)(0x4380C030UL))) +#define bM4_USBFS_HCCHAR8_EPNUM2 (*((volatile unsigned int*)(0x4380C034UL))) +#define bM4_USBFS_HCCHAR8_EPNUM3 (*((volatile unsigned int*)(0x4380C038UL))) +#define bM4_USBFS_HCCHAR8_EPDIR (*((volatile unsigned int*)(0x4380C03CUL))) +#define bM4_USBFS_HCCHAR8_LSDEV (*((volatile unsigned int*)(0x4380C044UL))) +#define bM4_USBFS_HCCHAR8_EPTYP0 (*((volatile unsigned int*)(0x4380C048UL))) +#define bM4_USBFS_HCCHAR8_EPTYP1 (*((volatile unsigned int*)(0x4380C04CUL))) +#define bM4_USBFS_HCCHAR8_DAD0 (*((volatile unsigned int*)(0x4380C058UL))) +#define bM4_USBFS_HCCHAR8_DAD1 (*((volatile unsigned int*)(0x4380C05CUL))) +#define bM4_USBFS_HCCHAR8_DAD2 (*((volatile unsigned int*)(0x4380C060UL))) +#define bM4_USBFS_HCCHAR8_DAD3 (*((volatile unsigned int*)(0x4380C064UL))) +#define bM4_USBFS_HCCHAR8_DAD4 (*((volatile unsigned int*)(0x4380C068UL))) +#define bM4_USBFS_HCCHAR8_DAD5 (*((volatile unsigned int*)(0x4380C06CUL))) +#define bM4_USBFS_HCCHAR8_DAD6 (*((volatile unsigned int*)(0x4380C070UL))) +#define bM4_USBFS_HCCHAR8_ODDFRM (*((volatile unsigned int*)(0x4380C074UL))) +#define bM4_USBFS_HCCHAR8_CHDIS (*((volatile unsigned int*)(0x4380C078UL))) +#define bM4_USBFS_HCCHAR8_CHENA (*((volatile unsigned int*)(0x4380C07CUL))) +#define bM4_USBFS_HCINT8_XFRC (*((volatile unsigned int*)(0x4380C100UL))) +#define bM4_USBFS_HCINT8_CHH (*((volatile unsigned int*)(0x4380C104UL))) +#define bM4_USBFS_HCINT8_STALL (*((volatile unsigned int*)(0x4380C10CUL))) +#define bM4_USBFS_HCINT8_NAK (*((volatile unsigned int*)(0x4380C110UL))) +#define bM4_USBFS_HCINT8_ACK (*((volatile unsigned int*)(0x4380C114UL))) +#define bM4_USBFS_HCINT8_TXERR (*((volatile unsigned int*)(0x4380C11CUL))) +#define bM4_USBFS_HCINT8_BBERR (*((volatile unsigned int*)(0x4380C120UL))) +#define bM4_USBFS_HCINT8_FRMOR (*((volatile unsigned int*)(0x4380C124UL))) +#define bM4_USBFS_HCINT8_DTERR (*((volatile unsigned int*)(0x4380C128UL))) +#define bM4_USBFS_HCINTMSK8_XFRCM (*((volatile unsigned int*)(0x4380C180UL))) +#define bM4_USBFS_HCINTMSK8_CHHM (*((volatile unsigned int*)(0x4380C184UL))) +#define bM4_USBFS_HCINTMSK8_STALLM (*((volatile unsigned int*)(0x4380C18CUL))) +#define bM4_USBFS_HCINTMSK8_NAKM (*((volatile unsigned int*)(0x4380C190UL))) +#define bM4_USBFS_HCINTMSK8_ACKM (*((volatile unsigned int*)(0x4380C194UL))) +#define bM4_USBFS_HCINTMSK8_TXERRM (*((volatile unsigned int*)(0x4380C19CUL))) +#define bM4_USBFS_HCINTMSK8_BBERRM (*((volatile unsigned int*)(0x4380C1A0UL))) +#define bM4_USBFS_HCINTMSK8_FRMORM (*((volatile unsigned int*)(0x4380C1A4UL))) +#define bM4_USBFS_HCINTMSK8_DTERRM (*((volatile unsigned int*)(0x4380C1A8UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ0 (*((volatile unsigned int*)(0x4380C200UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ1 (*((volatile unsigned int*)(0x4380C204UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ2 (*((volatile unsigned int*)(0x4380C208UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ3 (*((volatile unsigned int*)(0x4380C20CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ4 (*((volatile unsigned int*)(0x4380C210UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ5 (*((volatile unsigned int*)(0x4380C214UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ6 (*((volatile unsigned int*)(0x4380C218UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ7 (*((volatile unsigned int*)(0x4380C21CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ8 (*((volatile unsigned int*)(0x4380C220UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ9 (*((volatile unsigned int*)(0x4380C224UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ10 (*((volatile unsigned int*)(0x4380C228UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ11 (*((volatile unsigned int*)(0x4380C22CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ12 (*((volatile unsigned int*)(0x4380C230UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ13 (*((volatile unsigned int*)(0x4380C234UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ14 (*((volatile unsigned int*)(0x4380C238UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ15 (*((volatile unsigned int*)(0x4380C23CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ16 (*((volatile unsigned int*)(0x4380C240UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ17 (*((volatile unsigned int*)(0x4380C244UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ18 (*((volatile unsigned int*)(0x4380C248UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT0 (*((volatile unsigned int*)(0x4380C24CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT1 (*((volatile unsigned int*)(0x4380C250UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT2 (*((volatile unsigned int*)(0x4380C254UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT3 (*((volatile unsigned int*)(0x4380C258UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT4 (*((volatile unsigned int*)(0x4380C25CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT5 (*((volatile unsigned int*)(0x4380C260UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT6 (*((volatile unsigned int*)(0x4380C264UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT7 (*((volatile unsigned int*)(0x4380C268UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT8 (*((volatile unsigned int*)(0x4380C26CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT9 (*((volatile unsigned int*)(0x4380C270UL))) +#define bM4_USBFS_HCTSIZ8_DPID0 (*((volatile unsigned int*)(0x4380C274UL))) +#define bM4_USBFS_HCTSIZ8_DPID1 (*((volatile unsigned int*)(0x4380C278UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ0 (*((volatile unsigned int*)(0x4380C400UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ1 (*((volatile unsigned int*)(0x4380C404UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ2 (*((volatile unsigned int*)(0x4380C408UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ3 (*((volatile unsigned int*)(0x4380C40CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ4 (*((volatile unsigned int*)(0x4380C410UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ5 (*((volatile unsigned int*)(0x4380C414UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ6 (*((volatile unsigned int*)(0x4380C418UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ7 (*((volatile unsigned int*)(0x4380C41CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ8 (*((volatile unsigned int*)(0x4380C420UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ9 (*((volatile unsigned int*)(0x4380C424UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ10 (*((volatile unsigned int*)(0x4380C428UL))) +#define bM4_USBFS_HCCHAR9_EPNUM0 (*((volatile unsigned int*)(0x4380C42CUL))) +#define bM4_USBFS_HCCHAR9_EPNUM1 (*((volatile unsigned int*)(0x4380C430UL))) +#define bM4_USBFS_HCCHAR9_EPNUM2 (*((volatile unsigned int*)(0x4380C434UL))) +#define bM4_USBFS_HCCHAR9_EPNUM3 (*((volatile unsigned int*)(0x4380C438UL))) +#define bM4_USBFS_HCCHAR9_EPDIR (*((volatile unsigned int*)(0x4380C43CUL))) +#define bM4_USBFS_HCCHAR9_LSDEV (*((volatile unsigned int*)(0x4380C444UL))) +#define bM4_USBFS_HCCHAR9_EPTYP0 (*((volatile unsigned int*)(0x4380C448UL))) +#define bM4_USBFS_HCCHAR9_EPTYP1 (*((volatile unsigned int*)(0x4380C44CUL))) +#define bM4_USBFS_HCCHAR9_DAD0 (*((volatile unsigned int*)(0x4380C458UL))) +#define bM4_USBFS_HCCHAR9_DAD1 (*((volatile unsigned int*)(0x4380C45CUL))) +#define bM4_USBFS_HCCHAR9_DAD2 (*((volatile unsigned int*)(0x4380C460UL))) +#define bM4_USBFS_HCCHAR9_DAD3 (*((volatile unsigned int*)(0x4380C464UL))) +#define bM4_USBFS_HCCHAR9_DAD4 (*((volatile unsigned int*)(0x4380C468UL))) +#define bM4_USBFS_HCCHAR9_DAD5 (*((volatile unsigned int*)(0x4380C46CUL))) +#define bM4_USBFS_HCCHAR9_DAD6 (*((volatile unsigned int*)(0x4380C470UL))) +#define bM4_USBFS_HCCHAR9_ODDFRM (*((volatile unsigned int*)(0x4380C474UL))) +#define bM4_USBFS_HCCHAR9_CHDIS (*((volatile unsigned int*)(0x4380C478UL))) +#define bM4_USBFS_HCCHAR9_CHENA (*((volatile unsigned int*)(0x4380C47CUL))) +#define bM4_USBFS_HCINT9_XFRC (*((volatile unsigned int*)(0x4380C500UL))) +#define bM4_USBFS_HCINT9_CHH (*((volatile unsigned int*)(0x4380C504UL))) +#define bM4_USBFS_HCINT9_STALL (*((volatile unsigned int*)(0x4380C50CUL))) +#define bM4_USBFS_HCINT9_NAK (*((volatile unsigned int*)(0x4380C510UL))) +#define bM4_USBFS_HCINT9_ACK (*((volatile unsigned int*)(0x4380C514UL))) +#define bM4_USBFS_HCINT9_TXERR (*((volatile unsigned int*)(0x4380C51CUL))) +#define bM4_USBFS_HCINT9_BBERR (*((volatile unsigned int*)(0x4380C520UL))) +#define bM4_USBFS_HCINT9_FRMOR (*((volatile unsigned int*)(0x4380C524UL))) +#define bM4_USBFS_HCINT9_DTERR (*((volatile unsigned int*)(0x4380C528UL))) +#define bM4_USBFS_HCINTMSK9_XFRCM (*((volatile unsigned int*)(0x4380C580UL))) +#define bM4_USBFS_HCINTMSK9_CHHM (*((volatile unsigned int*)(0x4380C584UL))) +#define bM4_USBFS_HCINTMSK9_STALLM (*((volatile unsigned int*)(0x4380C58CUL))) +#define bM4_USBFS_HCINTMSK9_NAKM (*((volatile unsigned int*)(0x4380C590UL))) +#define bM4_USBFS_HCINTMSK9_ACKM (*((volatile unsigned int*)(0x4380C594UL))) +#define bM4_USBFS_HCINTMSK9_TXERRM (*((volatile unsigned int*)(0x4380C59CUL))) +#define bM4_USBFS_HCINTMSK9_BBERRM (*((volatile unsigned int*)(0x4380C5A0UL))) +#define bM4_USBFS_HCINTMSK9_FRMORM (*((volatile unsigned int*)(0x4380C5A4UL))) +#define bM4_USBFS_HCINTMSK9_DTERRM (*((volatile unsigned int*)(0x4380C5A8UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ0 (*((volatile unsigned int*)(0x4380C600UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ1 (*((volatile unsigned int*)(0x4380C604UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ2 (*((volatile unsigned int*)(0x4380C608UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ3 (*((volatile unsigned int*)(0x4380C60CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ4 (*((volatile unsigned int*)(0x4380C610UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ5 (*((volatile unsigned int*)(0x4380C614UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ6 (*((volatile unsigned int*)(0x4380C618UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ7 (*((volatile unsigned int*)(0x4380C61CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ8 (*((volatile unsigned int*)(0x4380C620UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ9 (*((volatile unsigned int*)(0x4380C624UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ10 (*((volatile unsigned int*)(0x4380C628UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ11 (*((volatile unsigned int*)(0x4380C62CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ12 (*((volatile unsigned int*)(0x4380C630UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ13 (*((volatile unsigned int*)(0x4380C634UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ14 (*((volatile unsigned int*)(0x4380C638UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ15 (*((volatile unsigned int*)(0x4380C63CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ16 (*((volatile unsigned int*)(0x4380C640UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ17 (*((volatile unsigned int*)(0x4380C644UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ18 (*((volatile unsigned int*)(0x4380C648UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT0 (*((volatile unsigned int*)(0x4380C64CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT1 (*((volatile unsigned int*)(0x4380C650UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT2 (*((volatile unsigned int*)(0x4380C654UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT3 (*((volatile unsigned int*)(0x4380C658UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT4 (*((volatile unsigned int*)(0x4380C65CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT5 (*((volatile unsigned int*)(0x4380C660UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT6 (*((volatile unsigned int*)(0x4380C664UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT7 (*((volatile unsigned int*)(0x4380C668UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT8 (*((volatile unsigned int*)(0x4380C66CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT9 (*((volatile unsigned int*)(0x4380C670UL))) +#define bM4_USBFS_HCTSIZ9_DPID0 (*((volatile unsigned int*)(0x4380C674UL))) +#define bM4_USBFS_HCTSIZ9_DPID1 (*((volatile unsigned int*)(0x4380C678UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ0 (*((volatile unsigned int*)(0x4380C800UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ1 (*((volatile unsigned int*)(0x4380C804UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ2 (*((volatile unsigned int*)(0x4380C808UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ3 (*((volatile unsigned int*)(0x4380C80CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ4 (*((volatile unsigned int*)(0x4380C810UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ5 (*((volatile unsigned int*)(0x4380C814UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ6 (*((volatile unsigned int*)(0x4380C818UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ7 (*((volatile unsigned int*)(0x4380C81CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ8 (*((volatile unsigned int*)(0x4380C820UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ9 (*((volatile unsigned int*)(0x4380C824UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ10 (*((volatile unsigned int*)(0x4380C828UL))) +#define bM4_USBFS_HCCHAR10_EPNUM0 (*((volatile unsigned int*)(0x4380C82CUL))) +#define bM4_USBFS_HCCHAR10_EPNUM1 (*((volatile unsigned int*)(0x4380C830UL))) +#define bM4_USBFS_HCCHAR10_EPNUM2 (*((volatile unsigned int*)(0x4380C834UL))) +#define bM4_USBFS_HCCHAR10_EPNUM3 (*((volatile unsigned int*)(0x4380C838UL))) +#define bM4_USBFS_HCCHAR10_EPDIR (*((volatile unsigned int*)(0x4380C83CUL))) +#define bM4_USBFS_HCCHAR10_LSDEV (*((volatile unsigned int*)(0x4380C844UL))) +#define bM4_USBFS_HCCHAR10_EPTYP0 (*((volatile unsigned int*)(0x4380C848UL))) +#define bM4_USBFS_HCCHAR10_EPTYP1 (*((volatile unsigned int*)(0x4380C84CUL))) +#define bM4_USBFS_HCCHAR10_DAD0 (*((volatile unsigned int*)(0x4380C858UL))) +#define bM4_USBFS_HCCHAR10_DAD1 (*((volatile unsigned int*)(0x4380C85CUL))) +#define bM4_USBFS_HCCHAR10_DAD2 (*((volatile unsigned int*)(0x4380C860UL))) +#define bM4_USBFS_HCCHAR10_DAD3 (*((volatile unsigned int*)(0x4380C864UL))) +#define bM4_USBFS_HCCHAR10_DAD4 (*((volatile unsigned int*)(0x4380C868UL))) +#define bM4_USBFS_HCCHAR10_DAD5 (*((volatile unsigned int*)(0x4380C86CUL))) +#define bM4_USBFS_HCCHAR10_DAD6 (*((volatile unsigned int*)(0x4380C870UL))) +#define bM4_USBFS_HCCHAR10_ODDFRM (*((volatile unsigned int*)(0x4380C874UL))) +#define bM4_USBFS_HCCHAR10_CHDIS (*((volatile unsigned int*)(0x4380C878UL))) +#define bM4_USBFS_HCCHAR10_CHENA (*((volatile unsigned int*)(0x4380C87CUL))) +#define bM4_USBFS_HCINT10_XFRC (*((volatile unsigned int*)(0x4380C900UL))) +#define bM4_USBFS_HCINT10_CHH (*((volatile unsigned int*)(0x4380C904UL))) +#define bM4_USBFS_HCINT10_STALL (*((volatile unsigned int*)(0x4380C90CUL))) +#define bM4_USBFS_HCINT10_NAK (*((volatile unsigned int*)(0x4380C910UL))) +#define bM4_USBFS_HCINT10_ACK (*((volatile unsigned int*)(0x4380C914UL))) +#define bM4_USBFS_HCINT10_TXERR (*((volatile unsigned int*)(0x4380C91CUL))) +#define bM4_USBFS_HCINT10_BBERR (*((volatile unsigned int*)(0x4380C920UL))) +#define bM4_USBFS_HCINT10_FRMOR (*((volatile unsigned int*)(0x4380C924UL))) +#define bM4_USBFS_HCINT10_DTERR (*((volatile unsigned int*)(0x4380C928UL))) +#define bM4_USBFS_HCINTMSK10_XFRCM (*((volatile unsigned int*)(0x4380C980UL))) +#define bM4_USBFS_HCINTMSK10_CHHM (*((volatile unsigned int*)(0x4380C984UL))) +#define bM4_USBFS_HCINTMSK10_STALLM (*((volatile unsigned int*)(0x4380C98CUL))) +#define bM4_USBFS_HCINTMSK10_NAKM (*((volatile unsigned int*)(0x4380C990UL))) +#define bM4_USBFS_HCINTMSK10_ACKM (*((volatile unsigned int*)(0x4380C994UL))) +#define bM4_USBFS_HCINTMSK10_TXERRM (*((volatile unsigned int*)(0x4380C99CUL))) +#define bM4_USBFS_HCINTMSK10_BBERRM (*((volatile unsigned int*)(0x4380C9A0UL))) +#define bM4_USBFS_HCINTMSK10_FRMORM (*((volatile unsigned int*)(0x4380C9A4UL))) +#define bM4_USBFS_HCINTMSK10_DTERRM (*((volatile unsigned int*)(0x4380C9A8UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ0 (*((volatile unsigned int*)(0x4380CA00UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ1 (*((volatile unsigned int*)(0x4380CA04UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ2 (*((volatile unsigned int*)(0x4380CA08UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ3 (*((volatile unsigned int*)(0x4380CA0CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ4 (*((volatile unsigned int*)(0x4380CA10UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ5 (*((volatile unsigned int*)(0x4380CA14UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ6 (*((volatile unsigned int*)(0x4380CA18UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ7 (*((volatile unsigned int*)(0x4380CA1CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ8 (*((volatile unsigned int*)(0x4380CA20UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ9 (*((volatile unsigned int*)(0x4380CA24UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ10 (*((volatile unsigned int*)(0x4380CA28UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ11 (*((volatile unsigned int*)(0x4380CA2CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ12 (*((volatile unsigned int*)(0x4380CA30UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ13 (*((volatile unsigned int*)(0x4380CA34UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ14 (*((volatile unsigned int*)(0x4380CA38UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ15 (*((volatile unsigned int*)(0x4380CA3CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ16 (*((volatile unsigned int*)(0x4380CA40UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ17 (*((volatile unsigned int*)(0x4380CA44UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ18 (*((volatile unsigned int*)(0x4380CA48UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT0 (*((volatile unsigned int*)(0x4380CA4CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT1 (*((volatile unsigned int*)(0x4380CA50UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT2 (*((volatile unsigned int*)(0x4380CA54UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT3 (*((volatile unsigned int*)(0x4380CA58UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT4 (*((volatile unsigned int*)(0x4380CA5CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT5 (*((volatile unsigned int*)(0x4380CA60UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT6 (*((volatile unsigned int*)(0x4380CA64UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT7 (*((volatile unsigned int*)(0x4380CA68UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT8 (*((volatile unsigned int*)(0x4380CA6CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT9 (*((volatile unsigned int*)(0x4380CA70UL))) +#define bM4_USBFS_HCTSIZ10_DPID0 (*((volatile unsigned int*)(0x4380CA74UL))) +#define bM4_USBFS_HCTSIZ10_DPID1 (*((volatile unsigned int*)(0x4380CA78UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ0 (*((volatile unsigned int*)(0x4380CC00UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ1 (*((volatile unsigned int*)(0x4380CC04UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ2 (*((volatile unsigned int*)(0x4380CC08UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ3 (*((volatile unsigned int*)(0x4380CC0CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ4 (*((volatile unsigned int*)(0x4380CC10UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ5 (*((volatile unsigned int*)(0x4380CC14UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ6 (*((volatile unsigned int*)(0x4380CC18UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ7 (*((volatile unsigned int*)(0x4380CC1CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ8 (*((volatile unsigned int*)(0x4380CC20UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ9 (*((volatile unsigned int*)(0x4380CC24UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ10 (*((volatile unsigned int*)(0x4380CC28UL))) +#define bM4_USBFS_HCCHAR11_EPNUM0 (*((volatile unsigned int*)(0x4380CC2CUL))) +#define bM4_USBFS_HCCHAR11_EPNUM1 (*((volatile unsigned int*)(0x4380CC30UL))) +#define bM4_USBFS_HCCHAR11_EPNUM2 (*((volatile unsigned int*)(0x4380CC34UL))) +#define bM4_USBFS_HCCHAR11_EPNUM3 (*((volatile unsigned int*)(0x4380CC38UL))) +#define bM4_USBFS_HCCHAR11_EPDIR (*((volatile unsigned int*)(0x4380CC3CUL))) +#define bM4_USBFS_HCCHAR11_LSDEV (*((volatile unsigned int*)(0x4380CC44UL))) +#define bM4_USBFS_HCCHAR11_EPTYP0 (*((volatile unsigned int*)(0x4380CC48UL))) +#define bM4_USBFS_HCCHAR11_EPTYP1 (*((volatile unsigned int*)(0x4380CC4CUL))) +#define bM4_USBFS_HCCHAR11_DAD0 (*((volatile unsigned int*)(0x4380CC58UL))) +#define bM4_USBFS_HCCHAR11_DAD1 (*((volatile unsigned int*)(0x4380CC5CUL))) +#define bM4_USBFS_HCCHAR11_DAD2 (*((volatile unsigned int*)(0x4380CC60UL))) +#define bM4_USBFS_HCCHAR11_DAD3 (*((volatile unsigned int*)(0x4380CC64UL))) +#define bM4_USBFS_HCCHAR11_DAD4 (*((volatile unsigned int*)(0x4380CC68UL))) +#define bM4_USBFS_HCCHAR11_DAD5 (*((volatile unsigned int*)(0x4380CC6CUL))) +#define bM4_USBFS_HCCHAR11_DAD6 (*((volatile unsigned int*)(0x4380CC70UL))) +#define bM4_USBFS_HCCHAR11_ODDFRM (*((volatile unsigned int*)(0x4380CC74UL))) +#define bM4_USBFS_HCCHAR11_CHDIS (*((volatile unsigned int*)(0x4380CC78UL))) +#define bM4_USBFS_HCCHAR11_CHENA (*((volatile unsigned int*)(0x4380CC7CUL))) +#define bM4_USBFS_HCINT11_XFRC (*((volatile unsigned int*)(0x4380CD00UL))) +#define bM4_USBFS_HCINT11_CHH (*((volatile unsigned int*)(0x4380CD04UL))) +#define bM4_USBFS_HCINT11_STALL (*((volatile unsigned int*)(0x4380CD0CUL))) +#define bM4_USBFS_HCINT11_NAK (*((volatile unsigned int*)(0x4380CD10UL))) +#define bM4_USBFS_HCINT11_ACK (*((volatile unsigned int*)(0x4380CD14UL))) +#define bM4_USBFS_HCINT11_TXERR (*((volatile unsigned int*)(0x4380CD1CUL))) +#define bM4_USBFS_HCINT11_BBERR (*((volatile unsigned int*)(0x4380CD20UL))) +#define bM4_USBFS_HCINT11_FRMOR (*((volatile unsigned int*)(0x4380CD24UL))) +#define bM4_USBFS_HCINT11_DTERR (*((volatile unsigned int*)(0x4380CD28UL))) +#define bM4_USBFS_HCINTMSK11_XFRCM (*((volatile unsigned int*)(0x4380CD80UL))) +#define bM4_USBFS_HCINTMSK11_CHHM (*((volatile unsigned int*)(0x4380CD84UL))) +#define bM4_USBFS_HCINTMSK11_STALLM (*((volatile unsigned int*)(0x4380CD8CUL))) +#define bM4_USBFS_HCINTMSK11_NAKM (*((volatile unsigned int*)(0x4380CD90UL))) +#define bM4_USBFS_HCINTMSK11_ACKM (*((volatile unsigned int*)(0x4380CD94UL))) +#define bM4_USBFS_HCINTMSK11_TXERRM (*((volatile unsigned int*)(0x4380CD9CUL))) +#define bM4_USBFS_HCINTMSK11_BBERRM (*((volatile unsigned int*)(0x4380CDA0UL))) +#define bM4_USBFS_HCINTMSK11_FRMORM (*((volatile unsigned int*)(0x4380CDA4UL))) +#define bM4_USBFS_HCINTMSK11_DTERRM (*((volatile unsigned int*)(0x4380CDA8UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ0 (*((volatile unsigned int*)(0x4380CE00UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ1 (*((volatile unsigned int*)(0x4380CE04UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ2 (*((volatile unsigned int*)(0x4380CE08UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ3 (*((volatile unsigned int*)(0x4380CE0CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ4 (*((volatile unsigned int*)(0x4380CE10UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ5 (*((volatile unsigned int*)(0x4380CE14UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ6 (*((volatile unsigned int*)(0x4380CE18UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ7 (*((volatile unsigned int*)(0x4380CE1CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ8 (*((volatile unsigned int*)(0x4380CE20UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ9 (*((volatile unsigned int*)(0x4380CE24UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ10 (*((volatile unsigned int*)(0x4380CE28UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ11 (*((volatile unsigned int*)(0x4380CE2CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ12 (*((volatile unsigned int*)(0x4380CE30UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ13 (*((volatile unsigned int*)(0x4380CE34UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ14 (*((volatile unsigned int*)(0x4380CE38UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ15 (*((volatile unsigned int*)(0x4380CE3CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ16 (*((volatile unsigned int*)(0x4380CE40UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ17 (*((volatile unsigned int*)(0x4380CE44UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ18 (*((volatile unsigned int*)(0x4380CE48UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT0 (*((volatile unsigned int*)(0x4380CE4CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT1 (*((volatile unsigned int*)(0x4380CE50UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT2 (*((volatile unsigned int*)(0x4380CE54UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT3 (*((volatile unsigned int*)(0x4380CE58UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT4 (*((volatile unsigned int*)(0x4380CE5CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT5 (*((volatile unsigned int*)(0x4380CE60UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT6 (*((volatile unsigned int*)(0x4380CE64UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT7 (*((volatile unsigned int*)(0x4380CE68UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT8 (*((volatile unsigned int*)(0x4380CE6CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT9 (*((volatile unsigned int*)(0x4380CE70UL))) +#define bM4_USBFS_HCTSIZ11_DPID0 (*((volatile unsigned int*)(0x4380CE74UL))) +#define bM4_USBFS_HCTSIZ11_DPID1 (*((volatile unsigned int*)(0x4380CE78UL))) +#define bM4_USBFS_DCFG_DSPD0 (*((volatile unsigned int*)(0x43810000UL))) +#define bM4_USBFS_DCFG_DSPD1 (*((volatile unsigned int*)(0x43810004UL))) +#define bM4_USBFS_DCFG_NZLSOHSK (*((volatile unsigned int*)(0x43810008UL))) +#define bM4_USBFS_DCFG_DAD0 (*((volatile unsigned int*)(0x43810010UL))) +#define bM4_USBFS_DCFG_DAD1 (*((volatile unsigned int*)(0x43810014UL))) +#define bM4_USBFS_DCFG_DAD2 (*((volatile unsigned int*)(0x43810018UL))) +#define bM4_USBFS_DCFG_DAD3 (*((volatile unsigned int*)(0x4381001CUL))) +#define bM4_USBFS_DCFG_DAD4 (*((volatile unsigned int*)(0x43810020UL))) +#define bM4_USBFS_DCFG_DAD5 (*((volatile unsigned int*)(0x43810024UL))) +#define bM4_USBFS_DCFG_DAD6 (*((volatile unsigned int*)(0x43810028UL))) +#define bM4_USBFS_DCFG_PFIVL0 (*((volatile unsigned int*)(0x4381002CUL))) +#define bM4_USBFS_DCFG_PFIVL1 (*((volatile unsigned int*)(0x43810030UL))) +#define bM4_USBFS_DCTL_RWUSIG (*((volatile unsigned int*)(0x43810080UL))) +#define bM4_USBFS_DCTL_SDIS (*((volatile unsigned int*)(0x43810084UL))) +#define bM4_USBFS_DCTL_GINSTS (*((volatile unsigned int*)(0x43810088UL))) +#define bM4_USBFS_DCTL_GONSTS (*((volatile unsigned int*)(0x4381008CUL))) +#define bM4_USBFS_DCTL_SGINAK (*((volatile unsigned int*)(0x4381009CUL))) +#define bM4_USBFS_DCTL_CGINAK (*((volatile unsigned int*)(0x438100A0UL))) +#define bM4_USBFS_DCTL_SGONAK (*((volatile unsigned int*)(0x438100A4UL))) +#define bM4_USBFS_DCTL_CGONAK (*((volatile unsigned int*)(0x438100A8UL))) +#define bM4_USBFS_DCTL_POPRGDNE (*((volatile unsigned int*)(0x438100ACUL))) +#define bM4_USBFS_DSTS_SUSPSTS (*((volatile unsigned int*)(0x43810100UL))) +#define bM4_USBFS_DSTS_ENUMSPD0 (*((volatile unsigned int*)(0x43810104UL))) +#define bM4_USBFS_DSTS_ENUMSPD1 (*((volatile unsigned int*)(0x43810108UL))) +#define bM4_USBFS_DSTS_EERR (*((volatile unsigned int*)(0x4381010CUL))) +#define bM4_USBFS_DSTS_FNSOF0 (*((volatile unsigned int*)(0x43810120UL))) +#define bM4_USBFS_DSTS_FNSOF1 (*((volatile unsigned int*)(0x43810124UL))) +#define bM4_USBFS_DSTS_FNSOF2 (*((volatile unsigned int*)(0x43810128UL))) +#define bM4_USBFS_DSTS_FNSOF3 (*((volatile unsigned int*)(0x4381012CUL))) +#define bM4_USBFS_DSTS_FNSOF4 (*((volatile unsigned int*)(0x43810130UL))) +#define bM4_USBFS_DSTS_FNSOF5 (*((volatile unsigned int*)(0x43810134UL))) +#define bM4_USBFS_DSTS_FNSOF6 (*((volatile unsigned int*)(0x43810138UL))) +#define bM4_USBFS_DSTS_FNSOF7 (*((volatile unsigned int*)(0x4381013CUL))) +#define bM4_USBFS_DSTS_FNSOF8 (*((volatile unsigned int*)(0x43810140UL))) +#define bM4_USBFS_DSTS_FNSOF9 (*((volatile unsigned int*)(0x43810144UL))) +#define bM4_USBFS_DSTS_FNSOF10 (*((volatile unsigned int*)(0x43810148UL))) +#define bM4_USBFS_DSTS_FNSOF11 (*((volatile unsigned int*)(0x4381014CUL))) +#define bM4_USBFS_DSTS_FNSOF12 (*((volatile unsigned int*)(0x43810150UL))) +#define bM4_USBFS_DSTS_FNSOF13 (*((volatile unsigned int*)(0x43810154UL))) +#define bM4_USBFS_DIEPMSK_XFRCM (*((volatile unsigned int*)(0x43810200UL))) +#define bM4_USBFS_DIEPMSK_EPDM (*((volatile unsigned int*)(0x43810204UL))) +#define bM4_USBFS_DIEPMSK_TOM (*((volatile unsigned int*)(0x4381020CUL))) +#define bM4_USBFS_DIEPMSK_ITTXFEMSK (*((volatile unsigned int*)(0x43810210UL))) +#define bM4_USBFS_DIEPMSK_INEPNMM (*((volatile unsigned int*)(0x43810214UL))) +#define bM4_USBFS_DIEPMSK_INEPNEM (*((volatile unsigned int*)(0x43810218UL))) +#define bM4_USBFS_DOEPMSK_XFRCM (*((volatile unsigned int*)(0x43810280UL))) +#define bM4_USBFS_DOEPMSK_EPDM (*((volatile unsigned int*)(0x43810284UL))) +#define bM4_USBFS_DOEPMSK_STUPM (*((volatile unsigned int*)(0x4381028CUL))) +#define bM4_USBFS_DOEPMSK_OTEPDM (*((volatile unsigned int*)(0x43810290UL))) +#define bM4_USBFS_DAINT_IEPINT0 (*((volatile unsigned int*)(0x43810300UL))) +#define bM4_USBFS_DAINT_IEPINT1 (*((volatile unsigned int*)(0x43810304UL))) +#define bM4_USBFS_DAINT_IEPINT2 (*((volatile unsigned int*)(0x43810308UL))) +#define bM4_USBFS_DAINT_IEPINT3 (*((volatile unsigned int*)(0x4381030CUL))) +#define bM4_USBFS_DAINT_IEPINT4 (*((volatile unsigned int*)(0x43810310UL))) +#define bM4_USBFS_DAINT_IEPINT5 (*((volatile unsigned int*)(0x43810314UL))) +#define bM4_USBFS_DAINT_OEPINT0 (*((volatile unsigned int*)(0x43810340UL))) +#define bM4_USBFS_DAINT_OEPINT1 (*((volatile unsigned int*)(0x43810344UL))) +#define bM4_USBFS_DAINT_OEPINT2 (*((volatile unsigned int*)(0x43810348UL))) +#define bM4_USBFS_DAINT_OEPINT3 (*((volatile unsigned int*)(0x4381034CUL))) +#define bM4_USBFS_DAINT_OEPINT4 (*((volatile unsigned int*)(0x43810350UL))) +#define bM4_USBFS_DAINT_OEPINT5 (*((volatile unsigned int*)(0x43810354UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM0 (*((volatile unsigned int*)(0x43810380UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM1 (*((volatile unsigned int*)(0x43810384UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM2 (*((volatile unsigned int*)(0x43810388UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM3 (*((volatile unsigned int*)(0x4381038CUL))) +#define bM4_USBFS_DAINTMSK_IEPINTM4 (*((volatile unsigned int*)(0x43810390UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM5 (*((volatile unsigned int*)(0x43810394UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM0 (*((volatile unsigned int*)(0x438103C0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM1 (*((volatile unsigned int*)(0x438103C4UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM2 (*((volatile unsigned int*)(0x438103C8UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM3 (*((volatile unsigned int*)(0x438103CCUL))) +#define bM4_USBFS_DAINTMSK_OEPINTM4 (*((volatile unsigned int*)(0x438103D0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM5 (*((volatile unsigned int*)(0x438103D4UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM0 (*((volatile unsigned int*)(0x43810680UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM1 (*((volatile unsigned int*)(0x43810684UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM2 (*((volatile unsigned int*)(0x43810688UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM3 (*((volatile unsigned int*)(0x4381068CUL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM4 (*((volatile unsigned int*)(0x43810690UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM5 (*((volatile unsigned int*)(0x43810694UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43812000UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43812004UL))) +#define bM4_USBFS_DIEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381203CUL))) +#define bM4_USBFS_DIEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43812044UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43812048UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381204CUL))) +#define bM4_USBFS_DIEPCTL0_STALL (*((volatile unsigned int*)(0x43812054UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM0 (*((volatile unsigned int*)(0x43812058UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM1 (*((volatile unsigned int*)(0x4381205CUL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM2 (*((volatile unsigned int*)(0x43812060UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM3 (*((volatile unsigned int*)(0x43812064UL))) +#define bM4_USBFS_DIEPCTL0_CNAK (*((volatile unsigned int*)(0x43812068UL))) +#define bM4_USBFS_DIEPCTL0_SNAK (*((volatile unsigned int*)(0x4381206CUL))) +#define bM4_USBFS_DIEPCTL0_EPDIS (*((volatile unsigned int*)(0x43812078UL))) +#define bM4_USBFS_DIEPCTL0_EPENA (*((volatile unsigned int*)(0x4381207CUL))) +#define bM4_USBFS_DIEPINT0_XFRC (*((volatile unsigned int*)(0x43812100UL))) +#define bM4_USBFS_DIEPINT0_EPDISD (*((volatile unsigned int*)(0x43812104UL))) +#define bM4_USBFS_DIEPINT0_TOC (*((volatile unsigned int*)(0x4381210CUL))) +#define bM4_USBFS_DIEPINT0_TTXFE (*((volatile unsigned int*)(0x43812110UL))) +#define bM4_USBFS_DIEPINT0_INEPNE (*((volatile unsigned int*)(0x43812118UL))) +#define bM4_USBFS_DIEPINT0_TXFE (*((volatile unsigned int*)(0x4381211CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43812200UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43812204UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43812208UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381220CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43812210UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43812214UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43812218UL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4381224CUL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x43812250UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV0 (*((volatile unsigned int*)(0x43812300UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV1 (*((volatile unsigned int*)(0x43812304UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV2 (*((volatile unsigned int*)(0x43812308UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV3 (*((volatile unsigned int*)(0x4381230CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV4 (*((volatile unsigned int*)(0x43812310UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV5 (*((volatile unsigned int*)(0x43812314UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV6 (*((volatile unsigned int*)(0x43812318UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV7 (*((volatile unsigned int*)(0x4381231CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV8 (*((volatile unsigned int*)(0x43812320UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV9 (*((volatile unsigned int*)(0x43812324UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV10 (*((volatile unsigned int*)(0x43812328UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV11 (*((volatile unsigned int*)(0x4381232CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV12 (*((volatile unsigned int*)(0x43812330UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV13 (*((volatile unsigned int*)(0x43812334UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV14 (*((volatile unsigned int*)(0x43812338UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV15 (*((volatile unsigned int*)(0x4381233CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43812400UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43812404UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43812408UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381240CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43812410UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43812414UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43812418UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381241CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43812420UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43812424UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43812428UL))) +#define bM4_USBFS_DIEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381243CUL))) +#define bM4_USBFS_DIEPCTL1_EONUM_DPID (*((volatile unsigned int*)(0x43812440UL))) +#define bM4_USBFS_DIEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43812444UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43812448UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381244CUL))) +#define bM4_USBFS_DIEPCTL1_STALL (*((volatile unsigned int*)(0x43812454UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM0 (*((volatile unsigned int*)(0x43812458UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM1 (*((volatile unsigned int*)(0x4381245CUL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM2 (*((volatile unsigned int*)(0x43812460UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM3 (*((volatile unsigned int*)(0x43812464UL))) +#define bM4_USBFS_DIEPCTL1_CNAK (*((volatile unsigned int*)(0x43812468UL))) +#define bM4_USBFS_DIEPCTL1_SNAK (*((volatile unsigned int*)(0x4381246CUL))) +#define bM4_USBFS_DIEPCTL1_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812470UL))) +#define bM4_USBFS_DIEPCTL1_SODDFRM (*((volatile unsigned int*)(0x43812474UL))) +#define bM4_USBFS_DIEPCTL1_EPDIS (*((volatile unsigned int*)(0x43812478UL))) +#define bM4_USBFS_DIEPCTL1_EPENA (*((volatile unsigned int*)(0x4381247CUL))) +#define bM4_USBFS_DIEPINT1_XFRC (*((volatile unsigned int*)(0x43812500UL))) +#define bM4_USBFS_DIEPINT1_EPDISD (*((volatile unsigned int*)(0x43812504UL))) +#define bM4_USBFS_DIEPINT1_TOC (*((volatile unsigned int*)(0x4381250CUL))) +#define bM4_USBFS_DIEPINT1_TTXFE (*((volatile unsigned int*)(0x43812510UL))) +#define bM4_USBFS_DIEPINT1_INEPNE (*((volatile unsigned int*)(0x43812518UL))) +#define bM4_USBFS_DIEPINT1_TXFE (*((volatile unsigned int*)(0x4381251CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43812600UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43812604UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43812608UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381260CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43812610UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43812614UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43812618UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381261CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43812620UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43812624UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43812628UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381262CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43812630UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43812634UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43812638UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381263CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43812640UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43812644UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43812648UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381264CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43812650UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43812654UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43812658UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381265CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43812660UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43812664UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43812668UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381266CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43812670UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV0 (*((volatile unsigned int*)(0x43812700UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV1 (*((volatile unsigned int*)(0x43812704UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV2 (*((volatile unsigned int*)(0x43812708UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV3 (*((volatile unsigned int*)(0x4381270CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV4 (*((volatile unsigned int*)(0x43812710UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV5 (*((volatile unsigned int*)(0x43812714UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV6 (*((volatile unsigned int*)(0x43812718UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV7 (*((volatile unsigned int*)(0x4381271CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV8 (*((volatile unsigned int*)(0x43812720UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV9 (*((volatile unsigned int*)(0x43812724UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV10 (*((volatile unsigned int*)(0x43812728UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV11 (*((volatile unsigned int*)(0x4381272CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV12 (*((volatile unsigned int*)(0x43812730UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV13 (*((volatile unsigned int*)(0x43812734UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV14 (*((volatile unsigned int*)(0x43812738UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV15 (*((volatile unsigned int*)(0x4381273CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43812800UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43812804UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43812808UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381280CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43812810UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43812814UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43812818UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381281CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43812820UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43812824UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43812828UL))) +#define bM4_USBFS_DIEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381283CUL))) +#define bM4_USBFS_DIEPCTL2_EONUM_DPID (*((volatile unsigned int*)(0x43812840UL))) +#define bM4_USBFS_DIEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43812844UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43812848UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381284CUL))) +#define bM4_USBFS_DIEPCTL2_STALL (*((volatile unsigned int*)(0x43812854UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM0 (*((volatile unsigned int*)(0x43812858UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM1 (*((volatile unsigned int*)(0x4381285CUL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM2 (*((volatile unsigned int*)(0x43812860UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM3 (*((volatile unsigned int*)(0x43812864UL))) +#define bM4_USBFS_DIEPCTL2_CNAK (*((volatile unsigned int*)(0x43812868UL))) +#define bM4_USBFS_DIEPCTL2_SNAK (*((volatile unsigned int*)(0x4381286CUL))) +#define bM4_USBFS_DIEPCTL2_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812870UL))) +#define bM4_USBFS_DIEPCTL2_SODDFRM (*((volatile unsigned int*)(0x43812874UL))) +#define bM4_USBFS_DIEPCTL2_EPDIS (*((volatile unsigned int*)(0x43812878UL))) +#define bM4_USBFS_DIEPCTL2_EPENA (*((volatile unsigned int*)(0x4381287CUL))) +#define bM4_USBFS_DIEPINT2_XFRC (*((volatile unsigned int*)(0x43812900UL))) +#define bM4_USBFS_DIEPINT2_EPDISD (*((volatile unsigned int*)(0x43812904UL))) +#define bM4_USBFS_DIEPINT2_TOC (*((volatile unsigned int*)(0x4381290CUL))) +#define bM4_USBFS_DIEPINT2_TTXFE (*((volatile unsigned int*)(0x43812910UL))) +#define bM4_USBFS_DIEPINT2_INEPNE (*((volatile unsigned int*)(0x43812918UL))) +#define bM4_USBFS_DIEPINT2_TXFE (*((volatile unsigned int*)(0x4381291CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43812A00UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43812A04UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43812A08UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43812A0CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43812A10UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43812A14UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43812A18UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43812A1CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43812A20UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43812A24UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43812A28UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43812A2CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43812A30UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43812A34UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43812A38UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43812A3CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43812A40UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43812A44UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43812A48UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43812A4CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43812A50UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43812A54UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43812A58UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43812A5CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43812A60UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43812A64UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43812A68UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43812A6CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43812A70UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV0 (*((volatile unsigned int*)(0x43812B00UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV1 (*((volatile unsigned int*)(0x43812B04UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV2 (*((volatile unsigned int*)(0x43812B08UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV3 (*((volatile unsigned int*)(0x43812B0CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV4 (*((volatile unsigned int*)(0x43812B10UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV5 (*((volatile unsigned int*)(0x43812B14UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV6 (*((volatile unsigned int*)(0x43812B18UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV7 (*((volatile unsigned int*)(0x43812B1CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV8 (*((volatile unsigned int*)(0x43812B20UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV9 (*((volatile unsigned int*)(0x43812B24UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV10 (*((volatile unsigned int*)(0x43812B28UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV11 (*((volatile unsigned int*)(0x43812B2CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV12 (*((volatile unsigned int*)(0x43812B30UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV13 (*((volatile unsigned int*)(0x43812B34UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV14 (*((volatile unsigned int*)(0x43812B38UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV15 (*((volatile unsigned int*)(0x43812B3CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43812C00UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43812C04UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43812C08UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43812C0CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43812C10UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43812C14UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43812C18UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43812C1CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43812C20UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43812C24UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43812C28UL))) +#define bM4_USBFS_DIEPCTL3_USBAEP (*((volatile unsigned int*)(0x43812C3CUL))) +#define bM4_USBFS_DIEPCTL3_EONUM_DPID (*((volatile unsigned int*)(0x43812C40UL))) +#define bM4_USBFS_DIEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43812C44UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43812C48UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43812C4CUL))) +#define bM4_USBFS_DIEPCTL3_STALL (*((volatile unsigned int*)(0x43812C54UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM0 (*((volatile unsigned int*)(0x43812C58UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM1 (*((volatile unsigned int*)(0x43812C5CUL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM2 (*((volatile unsigned int*)(0x43812C60UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM3 (*((volatile unsigned int*)(0x43812C64UL))) +#define bM4_USBFS_DIEPCTL3_CNAK (*((volatile unsigned int*)(0x43812C68UL))) +#define bM4_USBFS_DIEPCTL3_SNAK (*((volatile unsigned int*)(0x43812C6CUL))) +#define bM4_USBFS_DIEPCTL3_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812C70UL))) +#define bM4_USBFS_DIEPCTL3_SODDFRM (*((volatile unsigned int*)(0x43812C74UL))) +#define bM4_USBFS_DIEPCTL3_EPDIS (*((volatile unsigned int*)(0x43812C78UL))) +#define bM4_USBFS_DIEPCTL3_EPENA (*((volatile unsigned int*)(0x43812C7CUL))) +#define bM4_USBFS_DIEPINT3_XFRC (*((volatile unsigned int*)(0x43812D00UL))) +#define bM4_USBFS_DIEPINT3_EPDISD (*((volatile unsigned int*)(0x43812D04UL))) +#define bM4_USBFS_DIEPINT3_TOC (*((volatile unsigned int*)(0x43812D0CUL))) +#define bM4_USBFS_DIEPINT3_TTXFE (*((volatile unsigned int*)(0x43812D10UL))) +#define bM4_USBFS_DIEPINT3_INEPNE (*((volatile unsigned int*)(0x43812D18UL))) +#define bM4_USBFS_DIEPINT3_TXFE (*((volatile unsigned int*)(0x43812D1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43812E00UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43812E04UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43812E08UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43812E0CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43812E10UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43812E14UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43812E18UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43812E1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43812E20UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43812E24UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43812E28UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43812E2CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43812E30UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43812E34UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43812E38UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43812E3CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43812E40UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43812E44UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43812E48UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43812E4CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43812E50UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43812E54UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43812E58UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43812E5CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43812E60UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43812E64UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43812E68UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43812E6CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43812E70UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV0 (*((volatile unsigned int*)(0x43812F00UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV1 (*((volatile unsigned int*)(0x43812F04UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV2 (*((volatile unsigned int*)(0x43812F08UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV3 (*((volatile unsigned int*)(0x43812F0CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV4 (*((volatile unsigned int*)(0x43812F10UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV5 (*((volatile unsigned int*)(0x43812F14UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV6 (*((volatile unsigned int*)(0x43812F18UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV7 (*((volatile unsigned int*)(0x43812F1CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV8 (*((volatile unsigned int*)(0x43812F20UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV9 (*((volatile unsigned int*)(0x43812F24UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV10 (*((volatile unsigned int*)(0x43812F28UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV11 (*((volatile unsigned int*)(0x43812F2CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV12 (*((volatile unsigned int*)(0x43812F30UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV13 (*((volatile unsigned int*)(0x43812F34UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV14 (*((volatile unsigned int*)(0x43812F38UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV15 (*((volatile unsigned int*)(0x43812F3CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43813000UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43813004UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43813008UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381300CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43813010UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43813014UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43813018UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381301CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43813020UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43813024UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43813028UL))) +#define bM4_USBFS_DIEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381303CUL))) +#define bM4_USBFS_DIEPCTL4_EONUM_DPID (*((volatile unsigned int*)(0x43813040UL))) +#define bM4_USBFS_DIEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43813044UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43813048UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381304CUL))) +#define bM4_USBFS_DIEPCTL4_STALL (*((volatile unsigned int*)(0x43813054UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM0 (*((volatile unsigned int*)(0x43813058UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM1 (*((volatile unsigned int*)(0x4381305CUL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM2 (*((volatile unsigned int*)(0x43813060UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM3 (*((volatile unsigned int*)(0x43813064UL))) +#define bM4_USBFS_DIEPCTL4_CNAK (*((volatile unsigned int*)(0x43813068UL))) +#define bM4_USBFS_DIEPCTL4_SNAK (*((volatile unsigned int*)(0x4381306CUL))) +#define bM4_USBFS_DIEPCTL4_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813070UL))) +#define bM4_USBFS_DIEPCTL4_SODDFRM (*((volatile unsigned int*)(0x43813074UL))) +#define bM4_USBFS_DIEPCTL4_EPDIS (*((volatile unsigned int*)(0x43813078UL))) +#define bM4_USBFS_DIEPCTL4_EPENA (*((volatile unsigned int*)(0x4381307CUL))) +#define bM4_USBFS_DIEPINT4_XFRC (*((volatile unsigned int*)(0x43813100UL))) +#define bM4_USBFS_DIEPINT4_EPDISD (*((volatile unsigned int*)(0x43813104UL))) +#define bM4_USBFS_DIEPINT4_TOC (*((volatile unsigned int*)(0x4381310CUL))) +#define bM4_USBFS_DIEPINT4_TTXFE (*((volatile unsigned int*)(0x43813110UL))) +#define bM4_USBFS_DIEPINT4_INEPNE (*((volatile unsigned int*)(0x43813118UL))) +#define bM4_USBFS_DIEPINT4_TXFE (*((volatile unsigned int*)(0x4381311CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43813200UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43813204UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43813208UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381320CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43813210UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43813214UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43813218UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381321CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43813220UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43813224UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43813228UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381322CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43813230UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43813234UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43813238UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381323CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43813240UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43813244UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43813248UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381324CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43813250UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43813254UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43813258UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381325CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43813260UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43813264UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43813268UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381326CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43813270UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV0 (*((volatile unsigned int*)(0x43813300UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV1 (*((volatile unsigned int*)(0x43813304UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV2 (*((volatile unsigned int*)(0x43813308UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV3 (*((volatile unsigned int*)(0x4381330CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV4 (*((volatile unsigned int*)(0x43813310UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV5 (*((volatile unsigned int*)(0x43813314UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV6 (*((volatile unsigned int*)(0x43813318UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV7 (*((volatile unsigned int*)(0x4381331CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV8 (*((volatile unsigned int*)(0x43813320UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV9 (*((volatile unsigned int*)(0x43813324UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV10 (*((volatile unsigned int*)(0x43813328UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV11 (*((volatile unsigned int*)(0x4381332CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV12 (*((volatile unsigned int*)(0x43813330UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV13 (*((volatile unsigned int*)(0x43813334UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV14 (*((volatile unsigned int*)(0x43813338UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV15 (*((volatile unsigned int*)(0x4381333CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43813400UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43813404UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43813408UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381340CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43813410UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43813414UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43813418UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381341CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43813420UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43813424UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43813428UL))) +#define bM4_USBFS_DIEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381343CUL))) +#define bM4_USBFS_DIEPCTL5_EONUM_DPID (*((volatile unsigned int*)(0x43813440UL))) +#define bM4_USBFS_DIEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43813444UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43813448UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381344CUL))) +#define bM4_USBFS_DIEPCTL5_STALL (*((volatile unsigned int*)(0x43813454UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM0 (*((volatile unsigned int*)(0x43813458UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM1 (*((volatile unsigned int*)(0x4381345CUL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM2 (*((volatile unsigned int*)(0x43813460UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM3 (*((volatile unsigned int*)(0x43813464UL))) +#define bM4_USBFS_DIEPCTL5_CNAK (*((volatile unsigned int*)(0x43813468UL))) +#define bM4_USBFS_DIEPCTL5_SNAK (*((volatile unsigned int*)(0x4381346CUL))) +#define bM4_USBFS_DIEPCTL5_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813470UL))) +#define bM4_USBFS_DIEPCTL5_SODDFRM (*((volatile unsigned int*)(0x43813474UL))) +#define bM4_USBFS_DIEPCTL5_EPDIS (*((volatile unsigned int*)(0x43813478UL))) +#define bM4_USBFS_DIEPCTL5_EPENA (*((volatile unsigned int*)(0x4381347CUL))) +#define bM4_USBFS_DIEPINT5_XFRC (*((volatile unsigned int*)(0x43813500UL))) +#define bM4_USBFS_DIEPINT5_EPDISD (*((volatile unsigned int*)(0x43813504UL))) +#define bM4_USBFS_DIEPINT5_TOC (*((volatile unsigned int*)(0x4381350CUL))) +#define bM4_USBFS_DIEPINT5_TTXFE (*((volatile unsigned int*)(0x43813510UL))) +#define bM4_USBFS_DIEPINT5_INEPNE (*((volatile unsigned int*)(0x43813518UL))) +#define bM4_USBFS_DIEPINT5_TXFE (*((volatile unsigned int*)(0x4381351CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43813600UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43813604UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43813608UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381360CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43813610UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43813614UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43813618UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381361CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43813620UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43813624UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43813628UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381362CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43813630UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43813634UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43813638UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381363CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43813640UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43813644UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43813648UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381364CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43813650UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43813654UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43813658UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381365CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43813660UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43813664UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43813668UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381366CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43813670UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV0 (*((volatile unsigned int*)(0x43813700UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV1 (*((volatile unsigned int*)(0x43813704UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV2 (*((volatile unsigned int*)(0x43813708UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV3 (*((volatile unsigned int*)(0x4381370CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV4 (*((volatile unsigned int*)(0x43813710UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV5 (*((volatile unsigned int*)(0x43813714UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV6 (*((volatile unsigned int*)(0x43813718UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV7 (*((volatile unsigned int*)(0x4381371CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV8 (*((volatile unsigned int*)(0x43813720UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV9 (*((volatile unsigned int*)(0x43813724UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV10 (*((volatile unsigned int*)(0x43813728UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV11 (*((volatile unsigned int*)(0x4381372CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV12 (*((volatile unsigned int*)(0x43813730UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV13 (*((volatile unsigned int*)(0x43813734UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV14 (*((volatile unsigned int*)(0x43813738UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV15 (*((volatile unsigned int*)(0x4381373CUL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43816000UL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43816004UL))) +#define bM4_USBFS_DOEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381603CUL))) +#define bM4_USBFS_DOEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43816044UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43816048UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381604CUL))) +#define bM4_USBFS_DOEPCTL0_SNPM (*((volatile unsigned int*)(0x43816050UL))) +#define bM4_USBFS_DOEPCTL0_STALL (*((volatile unsigned int*)(0x43816054UL))) +#define bM4_USBFS_DOEPCTL0_CNAK (*((volatile unsigned int*)(0x43816068UL))) +#define bM4_USBFS_DOEPCTL0_SNAK (*((volatile unsigned int*)(0x4381606CUL))) +#define bM4_USBFS_DOEPCTL0_EPDIS (*((volatile unsigned int*)(0x43816078UL))) +#define bM4_USBFS_DOEPCTL0_EPENA (*((volatile unsigned int*)(0x4381607CUL))) +#define bM4_USBFS_DOEPINT0_XFRC (*((volatile unsigned int*)(0x43816100UL))) +#define bM4_USBFS_DOEPINT0_EPDISD (*((volatile unsigned int*)(0x43816104UL))) +#define bM4_USBFS_DOEPINT0_STUP (*((volatile unsigned int*)(0x4381610CUL))) +#define bM4_USBFS_DOEPINT0_OTEPDIS (*((volatile unsigned int*)(0x43816110UL))) +#define bM4_USBFS_DOEPINT0_B2BSTUP (*((volatile unsigned int*)(0x43816118UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43816200UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43816204UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43816208UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381620CUL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43816210UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43816214UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43816218UL))) +#define bM4_USBFS_DOEPTSIZ0_PKTCNT (*((volatile unsigned int*)(0x4381624CUL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT0 (*((volatile unsigned int*)(0x43816274UL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT1 (*((volatile unsigned int*)(0x43816278UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43816400UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43816404UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43816408UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381640CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43816410UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43816414UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43816418UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381641CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43816420UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43816424UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43816428UL))) +#define bM4_USBFS_DOEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381643CUL))) +#define bM4_USBFS_DOEPCTL1_DPID (*((volatile unsigned int*)(0x43816440UL))) +#define bM4_USBFS_DOEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43816444UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43816448UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381644CUL))) +#define bM4_USBFS_DOEPCTL1_SNPM (*((volatile unsigned int*)(0x43816450UL))) +#define bM4_USBFS_DOEPCTL1_STALL (*((volatile unsigned int*)(0x43816454UL))) +#define bM4_USBFS_DOEPCTL1_CNAK (*((volatile unsigned int*)(0x43816468UL))) +#define bM4_USBFS_DOEPCTL1_SNAK (*((volatile unsigned int*)(0x4381646CUL))) +#define bM4_USBFS_DOEPCTL1_SD0PID (*((volatile unsigned int*)(0x43816470UL))) +#define bM4_USBFS_DOEPCTL1_SD1PID (*((volatile unsigned int*)(0x43816474UL))) +#define bM4_USBFS_DOEPCTL1_EPDIS (*((volatile unsigned int*)(0x43816478UL))) +#define bM4_USBFS_DOEPCTL1_EPENA (*((volatile unsigned int*)(0x4381647CUL))) +#define bM4_USBFS_DOEPINT1_XFRC (*((volatile unsigned int*)(0x43816500UL))) +#define bM4_USBFS_DOEPINT1_EPDISD (*((volatile unsigned int*)(0x43816504UL))) +#define bM4_USBFS_DOEPINT1_STUP (*((volatile unsigned int*)(0x4381650CUL))) +#define bM4_USBFS_DOEPINT1_OTEPDIS (*((volatile unsigned int*)(0x43816510UL))) +#define bM4_USBFS_DOEPINT1_B2BSTUP (*((volatile unsigned int*)(0x43816518UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43816600UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43816604UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43816608UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381660CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43816610UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43816614UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43816618UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381661CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43816620UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43816624UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43816628UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381662CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43816630UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43816634UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43816638UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381663CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43816640UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43816644UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43816648UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381664CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43816650UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43816654UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43816658UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381665CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43816660UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43816664UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43816668UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381666CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43816670UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43816800UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43816804UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43816808UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381680CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43816810UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43816814UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43816818UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381681CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43816820UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43816824UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43816828UL))) +#define bM4_USBFS_DOEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381683CUL))) +#define bM4_USBFS_DOEPCTL2_DPID (*((volatile unsigned int*)(0x43816840UL))) +#define bM4_USBFS_DOEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43816844UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43816848UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381684CUL))) +#define bM4_USBFS_DOEPCTL2_SNPM (*((volatile unsigned int*)(0x43816850UL))) +#define bM4_USBFS_DOEPCTL2_STALL (*((volatile unsigned int*)(0x43816854UL))) +#define bM4_USBFS_DOEPCTL2_CNAK (*((volatile unsigned int*)(0x43816868UL))) +#define bM4_USBFS_DOEPCTL2_SNAK (*((volatile unsigned int*)(0x4381686CUL))) +#define bM4_USBFS_DOEPCTL2_SD0PID (*((volatile unsigned int*)(0x43816870UL))) +#define bM4_USBFS_DOEPCTL2_SD1PID (*((volatile unsigned int*)(0x43816874UL))) +#define bM4_USBFS_DOEPCTL2_EPDIS (*((volatile unsigned int*)(0x43816878UL))) +#define bM4_USBFS_DOEPCTL2_EPENA (*((volatile unsigned int*)(0x4381687CUL))) +#define bM4_USBFS_DOEPINT2_XFRC (*((volatile unsigned int*)(0x43816900UL))) +#define bM4_USBFS_DOEPINT2_EPDISD (*((volatile unsigned int*)(0x43816904UL))) +#define bM4_USBFS_DOEPINT2_STUP (*((volatile unsigned int*)(0x4381690CUL))) +#define bM4_USBFS_DOEPINT2_OTEPDIS (*((volatile unsigned int*)(0x43816910UL))) +#define bM4_USBFS_DOEPINT2_B2BSTUP (*((volatile unsigned int*)(0x43816918UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43816A00UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43816A04UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43816A08UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43816A0CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43816A10UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43816A14UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43816A18UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43816A1CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43816A20UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43816A24UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43816A28UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43816A2CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43816A30UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43816A34UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43816A38UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43816A3CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43816A40UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43816A44UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43816A48UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43816A4CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43816A50UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43816A54UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43816A58UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43816A5CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43816A60UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43816A64UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43816A68UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43816A6CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43816A70UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43816C00UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43816C04UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43816C08UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43816C0CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43816C10UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43816C14UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43816C18UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43816C1CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43816C20UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43816C24UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43816C28UL))) +#define bM4_USBFS_DOEPCTL3_USBAEP (*((volatile unsigned int*)(0x43816C3CUL))) +#define bM4_USBFS_DOEPCTL3_DPID (*((volatile unsigned int*)(0x43816C40UL))) +#define bM4_USBFS_DOEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43816C44UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43816C48UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43816C4CUL))) +#define bM4_USBFS_DOEPCTL3_SNPM (*((volatile unsigned int*)(0x43816C50UL))) +#define bM4_USBFS_DOEPCTL3_STALL (*((volatile unsigned int*)(0x43816C54UL))) +#define bM4_USBFS_DOEPCTL3_CNAK (*((volatile unsigned int*)(0x43816C68UL))) +#define bM4_USBFS_DOEPCTL3_SNAK (*((volatile unsigned int*)(0x43816C6CUL))) +#define bM4_USBFS_DOEPCTL3_SD0PID (*((volatile unsigned int*)(0x43816C70UL))) +#define bM4_USBFS_DOEPCTL3_SD1PID (*((volatile unsigned int*)(0x43816C74UL))) +#define bM4_USBFS_DOEPCTL3_EPDIS (*((volatile unsigned int*)(0x43816C78UL))) +#define bM4_USBFS_DOEPCTL3_EPENA (*((volatile unsigned int*)(0x43816C7CUL))) +#define bM4_USBFS_DOEPINT3_XFRC (*((volatile unsigned int*)(0x43816D00UL))) +#define bM4_USBFS_DOEPINT3_EPDISD (*((volatile unsigned int*)(0x43816D04UL))) +#define bM4_USBFS_DOEPINT3_STUP (*((volatile unsigned int*)(0x43816D0CUL))) +#define bM4_USBFS_DOEPINT3_OTEPDIS (*((volatile unsigned int*)(0x43816D10UL))) +#define bM4_USBFS_DOEPINT3_B2BSTUP (*((volatile unsigned int*)(0x43816D18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43816E00UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43816E04UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43816E08UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43816E0CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43816E10UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43816E14UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43816E18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43816E1CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43816E20UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43816E24UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43816E28UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43816E2CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43816E30UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43816E34UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43816E38UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43816E3CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43816E40UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43816E44UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43816E48UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43816E4CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43816E50UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43816E54UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43816E58UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43816E5CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43816E60UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43816E64UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43816E68UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43816E6CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43816E70UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43817000UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43817004UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43817008UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381700CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43817010UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43817014UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43817018UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381701CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43817020UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43817024UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43817028UL))) +#define bM4_USBFS_DOEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381703CUL))) +#define bM4_USBFS_DOEPCTL4_DPID (*((volatile unsigned int*)(0x43817040UL))) +#define bM4_USBFS_DOEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43817044UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43817048UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381704CUL))) +#define bM4_USBFS_DOEPCTL4_SNPM (*((volatile unsigned int*)(0x43817050UL))) +#define bM4_USBFS_DOEPCTL4_STALL (*((volatile unsigned int*)(0x43817054UL))) +#define bM4_USBFS_DOEPCTL4_CNAK (*((volatile unsigned int*)(0x43817068UL))) +#define bM4_USBFS_DOEPCTL4_SNAK (*((volatile unsigned int*)(0x4381706CUL))) +#define bM4_USBFS_DOEPCTL4_SD0PID (*((volatile unsigned int*)(0x43817070UL))) +#define bM4_USBFS_DOEPCTL4_SD1PID (*((volatile unsigned int*)(0x43817074UL))) +#define bM4_USBFS_DOEPCTL4_EPDIS (*((volatile unsigned int*)(0x43817078UL))) +#define bM4_USBFS_DOEPCTL4_EPENA (*((volatile unsigned int*)(0x4381707CUL))) +#define bM4_USBFS_DOEPINT4_XFRC (*((volatile unsigned int*)(0x43817100UL))) +#define bM4_USBFS_DOEPINT4_EPDISD (*((volatile unsigned int*)(0x43817104UL))) +#define bM4_USBFS_DOEPINT4_STUP (*((volatile unsigned int*)(0x4381710CUL))) +#define bM4_USBFS_DOEPINT4_OTEPDIS (*((volatile unsigned int*)(0x43817110UL))) +#define bM4_USBFS_DOEPINT4_B2BSTUP (*((volatile unsigned int*)(0x43817118UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43817200UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43817204UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43817208UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381720CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43817210UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43817214UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43817218UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381721CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43817220UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43817224UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43817228UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381722CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43817230UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43817234UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43817238UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381723CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43817240UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43817244UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43817248UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381724CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43817250UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43817254UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43817258UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381725CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43817260UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43817264UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43817268UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381726CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43817270UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43817400UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43817404UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43817408UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381740CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43817410UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43817414UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43817418UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381741CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43817420UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43817424UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43817428UL))) +#define bM4_USBFS_DOEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381743CUL))) +#define bM4_USBFS_DOEPCTL5_DPID (*((volatile unsigned int*)(0x43817440UL))) +#define bM4_USBFS_DOEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43817444UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43817448UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381744CUL))) +#define bM4_USBFS_DOEPCTL5_SNPM (*((volatile unsigned int*)(0x43817450UL))) +#define bM4_USBFS_DOEPCTL5_STALL (*((volatile unsigned int*)(0x43817454UL))) +#define bM4_USBFS_DOEPCTL5_CNAK (*((volatile unsigned int*)(0x43817468UL))) +#define bM4_USBFS_DOEPCTL5_SNAK (*((volatile unsigned int*)(0x4381746CUL))) +#define bM4_USBFS_DOEPCTL5_SD0PID (*((volatile unsigned int*)(0x43817470UL))) +#define bM4_USBFS_DOEPCTL5_SD1PID (*((volatile unsigned int*)(0x43817474UL))) +#define bM4_USBFS_DOEPCTL5_EPDIS (*((volatile unsigned int*)(0x43817478UL))) +#define bM4_USBFS_DOEPCTL5_EPENA (*((volatile unsigned int*)(0x4381747CUL))) +#define bM4_USBFS_DOEPINT5_XFRC (*((volatile unsigned int*)(0x43817500UL))) +#define bM4_USBFS_DOEPINT5_EPDISD (*((volatile unsigned int*)(0x43817504UL))) +#define bM4_USBFS_DOEPINT5_STUP (*((volatile unsigned int*)(0x4381750CUL))) +#define bM4_USBFS_DOEPINT5_OTEPDIS (*((volatile unsigned int*)(0x43817510UL))) +#define bM4_USBFS_DOEPINT5_B2BSTUP (*((volatile unsigned int*)(0x43817518UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43817600UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43817604UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43817608UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381760CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43817610UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43817614UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43817618UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381761CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43817620UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43817624UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43817628UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381762CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43817630UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43817634UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43817638UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381763CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43817640UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43817644UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43817648UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381764CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43817650UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43817654UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43817658UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381765CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43817660UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43817664UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43817668UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381766CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43817670UL))) +#define bM4_USBFS_PCGCCTL_STPPCLK (*((volatile unsigned int*)(0x4381C000UL))) +#define bM4_USBFS_PCGCCTL_GATEHCLK (*((volatile unsigned int*)(0x4381C004UL))) +#define bM4_WDT_CR_PERI0 (*((volatile unsigned int*)(0x42920000UL))) +#define bM4_WDT_CR_PERI1 (*((volatile unsigned int*)(0x42920004UL))) +#define bM4_WDT_CR_CKS0 (*((volatile unsigned int*)(0x42920010UL))) +#define bM4_WDT_CR_CKS1 (*((volatile unsigned int*)(0x42920014UL))) +#define bM4_WDT_CR_CKS2 (*((volatile unsigned int*)(0x42920018UL))) +#define bM4_WDT_CR_CKS3 (*((volatile unsigned int*)(0x4292001CUL))) +#define bM4_WDT_CR_WDPT0 (*((volatile unsigned int*)(0x42920020UL))) +#define bM4_WDT_CR_WDPT1 (*((volatile unsigned int*)(0x42920024UL))) +#define bM4_WDT_CR_WDPT2 (*((volatile unsigned int*)(0x42920028UL))) +#define bM4_WDT_CR_WDPT3 (*((volatile unsigned int*)(0x4292002CUL))) +#define bM4_WDT_CR_SLPOFF (*((volatile unsigned int*)(0x42920040UL))) +#define bM4_WDT_CR_ITS (*((volatile unsigned int*)(0x4292007CUL))) +#define bM4_WDT_SR_CNT0 (*((volatile unsigned int*)(0x42920080UL))) +#define bM4_WDT_SR_CNT1 (*((volatile unsigned int*)(0x42920084UL))) +#define bM4_WDT_SR_CNT2 (*((volatile unsigned int*)(0x42920088UL))) +#define bM4_WDT_SR_CNT3 (*((volatile unsigned int*)(0x4292008CUL))) +#define bM4_WDT_SR_CNT4 (*((volatile unsigned int*)(0x42920090UL))) +#define bM4_WDT_SR_CNT5 (*((volatile unsigned int*)(0x42920094UL))) +#define bM4_WDT_SR_CNT6 (*((volatile unsigned int*)(0x42920098UL))) +#define bM4_WDT_SR_CNT7 (*((volatile unsigned int*)(0x4292009CUL))) +#define bM4_WDT_SR_CNT8 (*((volatile unsigned int*)(0x429200A0UL))) +#define bM4_WDT_SR_CNT9 (*((volatile unsigned int*)(0x429200A4UL))) +#define bM4_WDT_SR_CNT10 (*((volatile unsigned int*)(0x429200A8UL))) +#define bM4_WDT_SR_CNT11 (*((volatile unsigned int*)(0x429200ACUL))) +#define bM4_WDT_SR_CNT12 (*((volatile unsigned int*)(0x429200B0UL))) +#define bM4_WDT_SR_CNT13 (*((volatile unsigned int*)(0x429200B4UL))) +#define bM4_WDT_SR_CNT14 (*((volatile unsigned int*)(0x429200B8UL))) +#define bM4_WDT_SR_CNT15 (*((volatile unsigned int*)(0x429200BCUL))) +#define bM4_WDT_SR_UDF (*((volatile unsigned int*)(0x429200C0UL))) +#define bM4_WDT_SR_REF (*((volatile unsigned int*)(0x429200C4UL))) +#define bM4_WDT_RR_RF0 (*((volatile unsigned int*)(0x42920100UL))) +#define bM4_WDT_RR_RF1 (*((volatile unsigned int*)(0x42920104UL))) +#define bM4_WDT_RR_RF2 (*((volatile unsigned int*)(0x42920108UL))) +#define bM4_WDT_RR_RF3 (*((volatile unsigned int*)(0x4292010CUL))) +#define bM4_WDT_RR_RF4 (*((volatile unsigned int*)(0x42920110UL))) +#define bM4_WDT_RR_RF5 (*((volatile unsigned int*)(0x42920114UL))) +#define bM4_WDT_RR_RF6 (*((volatile unsigned int*)(0x42920118UL))) +#define bM4_WDT_RR_RF7 (*((volatile unsigned int*)(0x4292011CUL))) +#define bM4_WDT_RR_RF8 (*((volatile unsigned int*)(0x42920120UL))) +#define bM4_WDT_RR_RF9 (*((volatile unsigned int*)(0x42920124UL))) +#define bM4_WDT_RR_RF10 (*((volatile unsigned int*)(0x42920128UL))) +#define bM4_WDT_RR_RF11 (*((volatile unsigned int*)(0x4292012CUL))) +#define bM4_WDT_RR_RF12 (*((volatile unsigned int*)(0x42920130UL))) +#define bM4_WDT_RR_RF13 (*((volatile unsigned int*)(0x42920134UL))) +#define bM4_WDT_RR_RF14 (*((volatile unsigned int*)(0x42920138UL))) +#define bM4_WDT_RR_RF15 (*((volatile unsigned int*)(0x4292013CUL))) +#define bM4_WKTM_CR_WKTMCMP0 (*((volatile unsigned int*)(0x42988000UL))) +#define bM4_WKTM_CR_WKTMCMP1 (*((volatile unsigned int*)(0x42988004UL))) +#define bM4_WKTM_CR_WKTMCMP2 (*((volatile unsigned int*)(0x42988008UL))) +#define bM4_WKTM_CR_WKTMCMP3 (*((volatile unsigned int*)(0x4298800CUL))) +#define bM4_WKTM_CR_WKTMCMP4 (*((volatile unsigned int*)(0x42988010UL))) +#define bM4_WKTM_CR_WKTMCMP5 (*((volatile unsigned int*)(0x42988014UL))) +#define bM4_WKTM_CR_WKTMCMP6 (*((volatile unsigned int*)(0x42988018UL))) +#define bM4_WKTM_CR_WKTMCMP7 (*((volatile unsigned int*)(0x4298801CUL))) +#define bM4_WKTM_CR_WKTMCMP8 (*((volatile unsigned int*)(0x42988020UL))) +#define bM4_WKTM_CR_WKTMCMP9 (*((volatile unsigned int*)(0x42988024UL))) +#define bM4_WKTM_CR_WKTMCMP10 (*((volatile unsigned int*)(0x42988028UL))) +#define bM4_WKTM_CR_WKTMCMP11 (*((volatile unsigned int*)(0x4298802CUL))) +#define bM4_WKTM_CR_WKOVF (*((volatile unsigned int*)(0x42988030UL))) +#define bM4_WKTM_CR_WKCKS0 (*((volatile unsigned int*)(0x42988034UL))) +#define bM4_WKTM_CR_WKCKS1 (*((volatile unsigned int*)(0x42988038UL))) +#define bM4_WKTM_CR_WKTCE (*((volatile unsigned int*)(0x4298803CUL))) + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_H__ */ + diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h new file mode 100644 index 000000000..624519f9a --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.h + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version. + ** + ******************************************************************************/ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32f460SystemGroup HC32F460 System Configure + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + +#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL))) + +#if !defined (HRC_16MHz_VALUE) + #define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */ +#endif + +#if !defined (HRC_20MHz_VALUE) + #define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */ +#endif + +#if !defined (MRC_VALUE) +#define MRC_VALUE ((uint32_t)8000000) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE ((uint32_t)32768) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE ((uint32_t)8000000) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE ((uint32_t)32768) /*!< External low speed OSC freq. */ +#endif + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern uint32_t HRC_VALUE; // HRC Clock Frequency (Core Clock) +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit(void); // Initialize the system +extern void SystemCoreClockUpdate(void); // Update SystemCoreClock variable + +//@} // Hc32f460SystemGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR new file mode 100644 index 0000000000000000000000000000000000000000..2f6262eef9fdfe13b5850d50474f473115e9df14 GIT binary patch literal 1620497 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zOmAxAm0^0D5-P(SHYHSsIZSDyGR$FW*Z&`W CvZ(C< literal 0 HcmV?d00001 diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s new file mode 100644 index 000000000..40ebda2b8 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s @@ -0,0 +1,621 @@ +;/****************************************************************************** +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2018-10-13 */ +;/* Target-mcu HC32F460 */ +;/*****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler ; IRQ000_Handler + DCD IRQ001_Handler ; IRQ001_Handler + DCD IRQ002_Handler ; IRQ002_Handler + DCD IRQ003_Handler ; IRQ003_Handler + DCD IRQ004_Handler ; IRQ004_Handler + DCD IRQ005_Handler ; IRQ005_Handler + DCD IRQ006_Handler ; IRQ006_Handler + DCD IRQ007_Handler ; IRQ007_Handler + DCD IRQ008_Handler ; IRQ008_Handler + DCD IRQ009_Handler ; IRQ009_Handler + DCD IRQ010_Handler ; IRQ010_Handler + DCD IRQ011_Handler ; IRQ011_Handler + DCD IRQ012_Handler ; IRQ012_Handler + DCD IRQ013_Handler ; IRQ013_Handler + DCD IRQ014_Handler ; IRQ014_Handler + DCD IRQ015_Handler ; IRQ015_Handler + DCD IRQ016_Handler ; IRQ016_Handler + DCD IRQ017_Handler ; IRQ017_Handler + DCD IRQ018_Handler ; IRQ018_Handler + DCD IRQ019_Handler ; IRQ019_Handler + DCD IRQ020_Handler ; IRQ020_Handler + DCD IRQ021_Handler ; IRQ021_Handler + DCD IRQ022_Handler ; IRQ022_Handler + DCD IRQ023_Handler ; IRQ023_Handler + DCD IRQ024_Handler ; IRQ024_Handler + DCD IRQ025_Handler ; IRQ025_Handler + DCD IRQ026_Handler ; IRQ026_Handler + DCD IRQ027_Handler ; IRQ027_Handler + DCD IRQ028_Handler ; IRQ028_Handler + DCD IRQ029_Handler ; IRQ029_Handler + DCD IRQ030_Handler ; IRQ030_Handler + DCD IRQ031_Handler ; IRQ031_Handler + DCD IRQ032_Handler ; IRQ032_Handler + DCD IRQ033_Handler ; IRQ033_Handler + DCD IRQ034_Handler ; IRQ034_Handler + DCD IRQ035_Handler ; IRQ035_Handler + DCD IRQ036_Handler ; IRQ036_Handler + DCD IRQ037_Handler ; IRQ037_Handler + DCD IRQ038_Handler ; IRQ038_Handler + DCD IRQ039_Handler ; IRQ039_Handler + DCD IRQ040_Handler ; IRQ040_Handler + DCD IRQ041_Handler ; IRQ041_Handler + DCD IRQ042_Handler ; IRQ042_Handler + DCD IRQ043_Handler ; IRQ043_Handler + DCD IRQ044_Handler ; IRQ044_Handler + DCD IRQ045_Handler ; IRQ045_Handler + DCD IRQ046_Handler ; IRQ046_Handler + DCD IRQ047_Handler ; IRQ047_Handler + DCD IRQ048_Handler ; IRQ048_Handler + DCD IRQ049_Handler ; IRQ049_Handler + DCD IRQ050_Handler ; IRQ050_Handler + DCD IRQ051_Handler ; IRQ051_Handler + DCD IRQ052_Handler ; IRQ052_Handler + DCD IRQ053_Handler ; IRQ053_Handler + DCD IRQ054_Handler ; IRQ054_Handler + DCD IRQ055_Handler ; IRQ055_Handler + DCD IRQ056_Handler ; IRQ056_Handler + DCD IRQ057_Handler ; IRQ057_Handler + DCD IRQ058_Handler ; IRQ058_Handler + DCD IRQ059_Handler ; IRQ059_Handler + DCD IRQ060_Handler ; IRQ060_Handler + DCD IRQ061_Handler ; IRQ061_Handler + DCD IRQ062_Handler ; IRQ062_Handler + DCD IRQ063_Handler ; IRQ063_Handler + DCD IRQ064_Handler ; IRQ064_Handler + DCD IRQ065_Handler ; IRQ065_Handler + DCD IRQ066_Handler ; IRQ066_Handler + DCD IRQ067_Handler ; IRQ067_Handler + DCD IRQ068_Handler ; IRQ068_Handler + DCD IRQ069_Handler ; IRQ069_Handler + DCD IRQ070_Handler ; IRQ070_Handler + DCD IRQ071_Handler ; IRQ071_Handler + DCD IRQ072_Handler ; IRQ072_Handler + DCD IRQ073_Handler ; IRQ073_Handler + DCD IRQ074_Handler ; IRQ074_Handler + DCD IRQ075_Handler ; IRQ075_Handler + DCD IRQ076_Handler ; IRQ076_Handler + DCD IRQ077_Handler ; IRQ077_Handler + DCD IRQ078_Handler ; IRQ078_Handler + DCD IRQ079_Handler ; IRQ079_Handler + DCD IRQ080_Handler ; IRQ080_Handler + DCD IRQ081_Handler ; IRQ081_Handler + DCD IRQ082_Handler ; IRQ082_Handler + DCD IRQ083_Handler ; IRQ083_Handler + DCD IRQ084_Handler ; IRQ084_Handler + DCD IRQ085_Handler ; IRQ085_Handler + DCD IRQ086_Handler ; IRQ086_Handler + DCD IRQ087_Handler ; IRQ087_Handler + DCD IRQ088_Handler ; IRQ088_Handler + DCD IRQ089_Handler ; IRQ089_Handler + DCD IRQ090_Handler ; IRQ090_Handler + DCD IRQ091_Handler ; IRQ091_Handler + DCD IRQ092_Handler ; IRQ092_Handler + DCD IRQ093_Handler ; IRQ093_Handler + DCD IRQ094_Handler ; IRQ094_Handler + DCD IRQ095_Handler ; IRQ095_Handler + DCD IRQ096_Handler ; IRQ096_Handler + DCD IRQ097_Handler ; IRQ097_Handler + DCD IRQ098_Handler ; IRQ098_Handler + DCD IRQ099_Handler ; IRQ099_Handler + DCD IRQ100_Handler ; IRQ100_Handler + DCD IRQ101_Handler ; IRQ101_Handler + DCD IRQ102_Handler ; IRQ102_Handler + DCD IRQ103_Handler ; IRQ103_Handler + DCD IRQ104_Handler ; IRQ104_Handler + DCD IRQ105_Handler ; IRQ105_Handler + DCD IRQ106_Handler ; IRQ106_Handler + DCD IRQ107_Handler ; IRQ107_Handler + DCD IRQ108_Handler ; IRQ108_Handler + DCD IRQ109_Handler ; IRQ109_Handler + DCD IRQ110_Handler ; IRQ110_Handler + DCD IRQ111_Handler ; IRQ111_Handler + DCD IRQ112_Handler ; IRQ112_Handler + DCD IRQ113_Handler ; IRQ113_Handler + DCD IRQ114_Handler ; IRQ114_Handler + DCD IRQ115_Handler ; IRQ115_Handler + DCD IRQ116_Handler ; IRQ116_Handler + DCD IRQ117_Handler ; IRQ117_Handler + DCD IRQ118_Handler ; IRQ118_Handler + DCD IRQ119_Handler ; IRQ119_Handler + DCD IRQ120_Handler ; IRQ120_Handler + DCD IRQ121_Handler ; IRQ121_Handler + DCD IRQ122_Handler ; IRQ122_Handler + DCD IRQ123_Handler ; IRQ123_Handler + DCD IRQ124_Handler ; IRQ124_Handler + DCD IRQ125_Handler ; IRQ125_Handler + DCD IRQ126_Handler ; IRQ126_Handler + DCD IRQ127_Handler ; IRQ127_Handler + DCD IRQ128_Handler ; IRQ128_Handler + DCD IRQ129_Handler ; IRQ129_Handler + DCD IRQ130_Handler ; IRQ130_Handler + DCD IRQ131_Handler ; IRQ131_Handler + DCD IRQ132_Handler ; IRQ132_Handler + DCD IRQ133_Handler ; IRQ133_Handler + DCD IRQ134_Handler ; IRQ134_Handler + DCD IRQ135_Handler ; IRQ135_Handler + DCD IRQ136_Handler ; IRQ136_Handler + DCD IRQ137_Handler ; IRQ137_Handler + DCD IRQ138_Handler ; IRQ138_Handler + DCD IRQ139_Handler ; IRQ139_Handler + DCD IRQ140_Handler ; IRQ140_Handler + DCD IRQ141_Handler ; IRQ141_Handler + DCD IRQ142_Handler ; IRQ142_Handler + DCD IRQ143_Handler ; IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S new file mode 100644 index 000000000..b27e3bc75 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S @@ -0,0 +1,538 @@ +/* +;******************************************************************************* +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +*/ +/*****************************************************************************/ +/* Startup for GCC */ +/* Version V1.0 */ +/* Date 2019-03-13 */ +/* Target-mcu HC32F460 */ +/*****************************************************************************/ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00000400 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00000C00 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long IRQ016_Handler + .long IRQ017_Handler + .long IRQ018_Handler + .long IRQ019_Handler + .long IRQ020_Handler + .long IRQ021_Handler + .long IRQ022_Handler + .long IRQ023_Handler + .long IRQ024_Handler + .long IRQ025_Handler + .long IRQ026_Handler + .long IRQ027_Handler + .long IRQ028_Handler + .long IRQ029_Handler + .long IRQ030_Handler + .long IRQ031_Handler + .long IRQ032_Handler + .long IRQ033_Handler + .long IRQ034_Handler + .long IRQ035_Handler + .long IRQ036_Handler + .long IRQ037_Handler + .long IRQ038_Handler + .long IRQ039_Handler + .long IRQ040_Handler + .long IRQ041_Handler + .long IRQ042_Handler + .long IRQ043_Handler + .long IRQ044_Handler + .long IRQ045_Handler + .long IRQ046_Handler + .long IRQ047_Handler + .long IRQ048_Handler + .long IRQ049_Handler + .long IRQ050_Handler + .long IRQ051_Handler + .long IRQ052_Handler + .long IRQ053_Handler + .long IRQ054_Handler + .long IRQ055_Handler + .long IRQ056_Handler + .long IRQ057_Handler + .long IRQ058_Handler + .long IRQ059_Handler + .long IRQ060_Handler + .long IRQ061_Handler + .long IRQ062_Handler + .long IRQ063_Handler + .long IRQ064_Handler + .long IRQ065_Handler + .long IRQ066_Handler + .long IRQ067_Handler + .long IRQ068_Handler + .long IRQ069_Handler + .long IRQ070_Handler + .long IRQ071_Handler + .long IRQ072_Handler + .long IRQ073_Handler + .long IRQ074_Handler + .long IRQ075_Handler + .long IRQ076_Handler + .long IRQ077_Handler + .long IRQ078_Handler + .long IRQ079_Handler + .long IRQ080_Handler + .long IRQ081_Handler + .long IRQ082_Handler + .long IRQ083_Handler + .long IRQ084_Handler + .long IRQ085_Handler + .long IRQ086_Handler + .long IRQ087_Handler + .long IRQ088_Handler + .long IRQ089_Handler + .long IRQ090_Handler + .long IRQ091_Handler + .long IRQ092_Handler + .long IRQ093_Handler + .long IRQ094_Handler + .long IRQ095_Handler + .long IRQ096_Handler + .long IRQ097_Handler + .long IRQ098_Handler + .long IRQ099_Handler + .long IRQ100_Handler + .long IRQ101_Handler + .long IRQ102_Handler + .long IRQ103_Handler + .long IRQ104_Handler + .long IRQ105_Handler + .long IRQ106_Handler + .long IRQ107_Handler + .long IRQ108_Handler + .long IRQ109_Handler + .long IRQ110_Handler + .long IRQ111_Handler + .long IRQ112_Handler + .long IRQ113_Handler + .long IRQ114_Handler + .long IRQ115_Handler + .long IRQ116_Handler + .long IRQ117_Handler + .long IRQ118_Handler + .long IRQ119_Handler + .long IRQ120_Handler + .long IRQ121_Handler + .long IRQ122_Handler + .long IRQ123_Handler + .long IRQ124_Handler + .long IRQ125_Handler + .long IRQ126_Handler + .long IRQ127_Handler + .long IRQ128_Handler + .long IRQ129_Handler + .long IRQ130_Handler + .long IRQ131_Handler + .long IRQ132_Handler + .long IRQ133_Handler + .long IRQ134_Handler + .long IRQ135_Handler + .long IRQ136_Handler + .long IRQ137_Handler + .long IRQ138_Handler + .long IRQ139_Handler + .long IRQ140_Handler + .long IRQ141_Handler + .long IRQ142_Handler + .long IRQ143_Handler + + .space (80 * 4) /* Interrupts 144 .. 224 are left out */ +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: + /* Set stack top pointer. */ + ldr sp, =__StackTop +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ret_ram + ldr r2, =__data_start_ret_ram__ + ldr r3, =__data_end_ret_ram__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ret_ram__ + ldr r2, =__bss_end_ret_ram__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + +SetSRAM3Wait: + ldr r0, =0x40050804 + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x40050800 + mov r1, #0x1100 + str r1, [r0] + + ldr r0, =0x40050804 + mov r1, #0x76 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x76 + str r1, [r0] + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl main + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler IRQ016_Handler + Set_Default_Handler IRQ017_Handler + Set_Default_Handler IRQ018_Handler + Set_Default_Handler IRQ019_Handler + Set_Default_Handler IRQ020_Handler + Set_Default_Handler IRQ021_Handler + Set_Default_Handler IRQ022_Handler + Set_Default_Handler IRQ023_Handler + Set_Default_Handler IRQ024_Handler + Set_Default_Handler IRQ025_Handler + Set_Default_Handler IRQ026_Handler + Set_Default_Handler IRQ027_Handler + Set_Default_Handler IRQ028_Handler + Set_Default_Handler IRQ029_Handler + Set_Default_Handler IRQ030_Handler + Set_Default_Handler IRQ031_Handler + Set_Default_Handler IRQ032_Handler + Set_Default_Handler IRQ033_Handler + Set_Default_Handler IRQ034_Handler + Set_Default_Handler IRQ035_Handler + Set_Default_Handler IRQ036_Handler + Set_Default_Handler IRQ037_Handler + Set_Default_Handler IRQ038_Handler + Set_Default_Handler IRQ039_Handler + Set_Default_Handler IRQ040_Handler + Set_Default_Handler IRQ041_Handler + Set_Default_Handler IRQ042_Handler + Set_Default_Handler IRQ043_Handler + Set_Default_Handler IRQ044_Handler + Set_Default_Handler IRQ045_Handler + Set_Default_Handler IRQ046_Handler + Set_Default_Handler IRQ047_Handler + Set_Default_Handler IRQ048_Handler + Set_Default_Handler IRQ049_Handler + Set_Default_Handler IRQ050_Handler + Set_Default_Handler IRQ051_Handler + Set_Default_Handler IRQ052_Handler + Set_Default_Handler IRQ053_Handler + Set_Default_Handler IRQ054_Handler + Set_Default_Handler IRQ055_Handler + Set_Default_Handler IRQ056_Handler + Set_Default_Handler IRQ057_Handler + Set_Default_Handler IRQ058_Handler + Set_Default_Handler IRQ059_Handler + Set_Default_Handler IRQ060_Handler + Set_Default_Handler IRQ061_Handler + Set_Default_Handler IRQ062_Handler + Set_Default_Handler IRQ063_Handler + Set_Default_Handler IRQ064_Handler + Set_Default_Handler IRQ065_Handler + Set_Default_Handler IRQ066_Handler + Set_Default_Handler IRQ067_Handler + Set_Default_Handler IRQ068_Handler + Set_Default_Handler IRQ069_Handler + Set_Default_Handler IRQ070_Handler + Set_Default_Handler IRQ071_Handler + Set_Default_Handler IRQ072_Handler + Set_Default_Handler IRQ073_Handler + Set_Default_Handler IRQ074_Handler + Set_Default_Handler IRQ075_Handler + Set_Default_Handler IRQ076_Handler + Set_Default_Handler IRQ077_Handler + Set_Default_Handler IRQ078_Handler + Set_Default_Handler IRQ079_Handler + Set_Default_Handler IRQ080_Handler + Set_Default_Handler IRQ081_Handler + Set_Default_Handler IRQ082_Handler + Set_Default_Handler IRQ083_Handler + Set_Default_Handler IRQ084_Handler + Set_Default_Handler IRQ085_Handler + Set_Default_Handler IRQ086_Handler + Set_Default_Handler IRQ087_Handler + Set_Default_Handler IRQ088_Handler + Set_Default_Handler IRQ089_Handler + Set_Default_Handler IRQ090_Handler + Set_Default_Handler IRQ091_Handler + Set_Default_Handler IRQ092_Handler + Set_Default_Handler IRQ093_Handler + Set_Default_Handler IRQ094_Handler + Set_Default_Handler IRQ095_Handler + Set_Default_Handler IRQ096_Handler + Set_Default_Handler IRQ097_Handler + Set_Default_Handler IRQ098_Handler + Set_Default_Handler IRQ099_Handler + Set_Default_Handler IRQ100_Handler + Set_Default_Handler IRQ101_Handler + Set_Default_Handler IRQ102_Handler + Set_Default_Handler IRQ103_Handler + Set_Default_Handler IRQ104_Handler + Set_Default_Handler IRQ105_Handler + Set_Default_Handler IRQ106_Handler + Set_Default_Handler IRQ107_Handler + Set_Default_Handler IRQ108_Handler + Set_Default_Handler IRQ109_Handler + Set_Default_Handler IRQ110_Handler + Set_Default_Handler IRQ111_Handler + Set_Default_Handler IRQ112_Handler + Set_Default_Handler IRQ113_Handler + Set_Default_Handler IRQ114_Handler + Set_Default_Handler IRQ115_Handler + Set_Default_Handler IRQ116_Handler + Set_Default_Handler IRQ117_Handler + Set_Default_Handler IRQ118_Handler + Set_Default_Handler IRQ119_Handler + Set_Default_Handler IRQ120_Handler + Set_Default_Handler IRQ121_Handler + Set_Default_Handler IRQ122_Handler + Set_Default_Handler IRQ123_Handler + Set_Default_Handler IRQ124_Handler + Set_Default_Handler IRQ125_Handler + Set_Default_Handler IRQ126_Handler + Set_Default_Handler IRQ127_Handler + Set_Default_Handler IRQ128_Handler + Set_Default_Handler IRQ129_Handler + Set_Default_Handler IRQ130_Handler + Set_Default_Handler IRQ131_Handler + Set_Default_Handler IRQ132_Handler + Set_Default_Handler IRQ133_Handler + Set_Default_Handler IRQ134_Handler + Set_Default_Handler IRQ135_Handler + Set_Default_Handler IRQ136_Handler + Set_Default_Handler IRQ137_Handler + Set_Default_Handler IRQ138_Handler + Set_Default_Handler IRQ139_Handler + Set_Default_Handler IRQ140_Handler + Set_Default_Handler IRQ141_Handler + Set_Default_Handler IRQ142_Handler + Set_Default_Handler IRQ143_Handler + + .end diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c new file mode 100644 index 000000000..cdf68c023 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c @@ -0,0 +1,117 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.c + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +/** + ******************************************************************************* + ** \addtogroup Hc32f460SystemGroup + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +//@{ + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t HRC_VALUE = HRC_16MHz_VALUE; +uint32_t SystemCoreClock = MRC_VALUE; + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param None + ** \return None + ******************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +} + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + uint8_t tmp = 0u; + uint32_t plln = 19u, pllp = 1u, pllm = 0u, pllsource = 0u; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + /* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */ + /* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */ + if (1UL == (HRC_FREQ_MON() & 1UL)) + { + HRC_VALUE = HRC_16MHz_VALUE; + } + else + { + HRC_VALUE = HRC_20MHz_VALUE; + } + + tmp = M4_SYSREG->CMU_CKSWR_f.CKSW; + switch (tmp) + { + case 0x00: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + /* use exteranl high speed OSC as PLL source */ + if (0ul == pllsource) + { + SystemCoreClock = (XTAL_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + /* use interanl high RC as PLL source */ + else if (1ul == pllsource) + { + SystemCoreClock = (HRC_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + else + { + /* Reserved */ + } + break; + } +} +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 000000000..1c9674bc5 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 000000000..8224cdb37 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 000000000..d6b28d430 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 000000000..adbf296f1 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 000000000..b111f6248 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 000000000..6580cce3c --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 000000000..f2e274662 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h new file mode 100644 index 000000000..dfcdc4d12 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 000000000..344dca514 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 000000000..5ddb8aeda --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 000000000..773e6edf5 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 000000000..4c02ee9ad --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h new file mode 100644 index 000000000..83b8fc6a0 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 000000000..c355f6037 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 000000000..8157ca782 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 000000000..20bf69b12 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h new file mode 100644 index 000000000..d811b2a31 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 000000000..12c023b80 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 000000000..71e1459f5 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 000000000..cf92577b6 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 000000000..40f3af81b --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 000000000..4592d6087 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 000000000..e2b7c2849 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h b/bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 000000000..facc2c9a4 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h new file mode 100644 index 000000000..edaf0b9e8 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h @@ -0,0 +1,509 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.h + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ +#ifndef __HC32F460_ADC_H__ +#define __HC32F460_ADC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_ADC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AdcGroup Analog-to-Digital Converter(ADC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC average count. + ** + ******************************************************************************/ +typedef enum en_adc_avcnt +{ + AdcAvcnt_2 = 0x0, ///< Average after 2 conversions. + AdcAvcnt_4 = 0x1, ///< Average after 4 conversions. + AdcAvcnt_8 = 0x2, ///< Average after 8 conversions. + AdcAvcnt_16 = 0x3, ///< Average after 16 conversions. + AdcAvcnt_32 = 0x4, ///< Average after 32 conversions. + AdcAvcnt_64 = 0x5, ///< Average after 64 conversions. + AdcAvcnt_128 = 0x6, ///< Average after 128 conversions. + AdcAvcnt_256 = 0x7, ///< Average after 256 conversions. +} en_adc_avcnt_t; + +/** + ******************************************************************************* + ** \brief ADC data alignment + ** + ******************************************************************************/ +typedef enum en_adc_data_align +{ + AdcDataAlign_Right = 0x0, ///< Data right alignment. + AdcDataAlign_Left = 0x1, ///< Data left alignment. +} en_adc_data_align_t; + +/** + ******************************************************************************* + ** \brief Automatically clear data registers after reading data. + ** The auto clear function is mainly used to detect whether the data register + ** is updated. + ** + ******************************************************************************/ +typedef enum en_adc_clren +{ + AdcClren_Disable = 0x0, ///< Automatic clear function disable. + AdcClren_Enable = 0x1, ///< Automatic clear function enable. +} en_adc_clren_t; + +/** + ******************************************************************************* + ** \brief ADC resolution. + ** + ******************************************************************************/ +typedef enum en_adc_resolution +{ + AdcResolution_12Bit = 0x0, ///< Resolution is 12 bit. + AdcResolution_10Bit = 0x1, ///< Resolution is 10 bit. + AdcResolution_8Bit = 0x2, ///< Resolution is 8 bit. +} en_adc_resolution_t; + +/** + ******************************************************************************* + ** \brief ADC scan mode. + ** + ******************************************************************************/ +typedef enum en_adc_scan_mode +{ + AdcMode_SAOnce = 0x0, ///< Sequence A works once. + AdcMode_SAContinuous = 0x1, ///< Sequence A works always. + AdcMode_SAOnceSBOnce = 0x2, ///< Sequence A and sequence B work once. + AdcMode_SAContinuousSBOnce = 0x3, ///< Sequence A works always, sequence works once. +} en_adc_scan_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sequence A restart position. + ** + ******************************************************************************/ +typedef enum en_adc_rschsel +{ + AdcRschsel_Continue = 0x0, ///< After sequence A is interrupted by sequence B, + ///< sequence A continues to scan from the interrupt + ///< when it restarts. + + AdcRschsel_Restart = 0x1, ///< After sequence A is interrupted by sequence B, + ///< sequence A restarts scanning from the first channel + ///< when it restarts. +} en_adc_rschsel_t; + +/** + ******************************************************************************* + ** \brief ADC external or internal trigger source enable/disable . + ** + ******************************************************************************/ +typedef enum en_adc_trgen +{ + AdcTrgen_Disable = 0x0, ///< External or internal trigger source disable. + AdcTrgen_Enable = 0x1, ///< External or internal trigger source enable. +} en_adc_trgen_t; + +/** + ******************************************************************************* + ** \brief ADC sequence trigger source selection. + ** + ******************************************************************************/ +typedef enum en_adc_trgsel +{ + AdcTrgsel_ADTRGX = 0x0, ///< X = 1(use ADC1) / 2(use ADC2), same as below. + AdcTrgsel_TRGX0 = 0x1, ///< Pin IN_TRG10 / IN_TRG20. + AdcTrgsel_TRGX1 = 0x2, ///< Pin IN_TRG11 / IN_TRG21. + AdcTrgsel_TRGX0_TRGX1 = 0x3, ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21. +} en_adc_trgsel_t; + +/** + ******************************************************************************* + ** \brief Sequence A/B conversion completion interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_eocien +{ + AdcEocien_Disable = 0x0, ///< Conversion completion interrupt disable. + AdcEocien_Enable = 0x1, ///< Conversion completion interrupt enable. +} en_adc_eocien_t; + +/** + ******************************************************************************* + ** \brief ADC sync mode. + ** + ******************************************************************************/ +typedef enum en_adc_sync_mode +{ + AdcSync_SingleSerial = 0x0u, ///< Single: ADC1 and ADC2 only sample and convert once after triggering. + ///< Serial: ADC2 start after ADC1 N PCLK4 cycles. + AdcSync_SingleParallel = 0x2u, ///< Parallel: ADC1 and ADC2 start at the same time. + AdcSync_ContinuousSerial = 0x4u, ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering. + AdcSync_ContinuousParallel = 0x6u, +} en_adc_sync_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sync enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_syncen +{ + AdcSync_Disable = 0x0, ///< Disable sync mode. + AdcSync_Enable = 0x1, ///< Enable sync mode. +} en_adc_syncen_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awdien +{ + AdcAwdInt_Disable = 0x0, ///< Disable AWD interrupt. + AdcAwdInt_Enable = 0x1, ///< Enable AWD interrupt. +} en_adc_awdien_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt event sequence selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdss +{ + AdcAwdSel_SA_SB = 0x0, ///< Sequence A and B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SA = 0x1, ///< Sequence A output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB = 0x2, ///< Sequence B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB_SA = 0x3, ///< Same as AdcAwdSel_SA_SB. +} en_adc_awdss_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog comparison mode selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdmd +{ + AdcAwdCmpMode_0 = 0x0, ///< Upper limit is AWDDR0, lower limit is AWDDR1. + ///< If AWDDR0 > result or result > AWDDR1, + ///< the interrupt will be occur. + + AdcAwdCmpMode_1 = 0x1, ///< The range is [AWDDR0, AWDDR1]. + ///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur. +} en_adc_awdmd_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awden +{ + AdcAwd_Disable = 0x0, ///< Disable AWD. + AdcAwd_Enable = 0x1, ///< Enable AWD. +} en_adc_awden_t; + +/** + ******************************************************************************* + ** \brief PGA control. + ** + ******************************************************************************/ +typedef enum en_adc_pga_ctl +{ + AdcPgaCtl_Invalid = 0x0, ///< Amplifier is invalid. + AdcPgaCtl_Amplify = 0xE, ///< Amplifier effective. +} en_adc_pga_ctl_t; + +/** + ******************************************************************************* + ** \brief The amplification factor of the amplifier is as follows. + ** + ******************************************************************************/ +typedef enum en_adc_pga_factor +{ + AdcPgaFactor_2 = 0x0, ///< PGA magnification 2. + AdcPgaFactor_2P133 = 0x1, ///< PGA magnification 2.133. + AdcPgaFactor_2P286 = 0x2, ///< PGA magnification 2.286. + AdcPgaFactor_2P667 = 0x3, ///< PGA magnification 2.667. + AdcPgaFactor_2P909 = 0x4, ///< PGA magnification 2.909. + AdcPgaFactor_3P2 = 0x5, ///< PGA magnification 3.2. + AdcPgaFactor_3P556 = 0x6, ///< PGA magnification 3.556. + AdcPgaFactor_4 = 0x7, ///< PGA magnification 4. + AdcPgaFactor_4P571 = 0x8, ///< PGA magnification 4.571. + AdcPgaFactor_5P333 = 0x9, ///< PGA magnification 5.333. + AdcPgaFactor_6P4 = 0xA, ///< PGA magnification 6.4. + AdcPgaFactor_8 = 0xB, ///< PGA magnification 8. + AdcPgaFactor_10P667 = 0xC, ///< PGA magnification 10.667. + AdcPgaFactor_16 = 0xD, ///< PGA magnification 16. + AdcPgaFactor_32 = 0xE, ///< PGA magnification 32. +} en_adc_pga_factor_t; + +/** + ******************************************************************************* + ** \brief Negative phase input selection + ** + ******************************************************************************/ +typedef enum en_adc_pga_negative +{ + AdcPgaNegative_PGAVSS = 0x0, ///< Use external port PGAVSS as PGA negative input. + AdcPgaNegative_VSSA = 0x1, ///< Use internal analog ground VSSA as PGA negative input. +} en_adc_pga_negative_t; + +/** + ******************************************************************************* + ** \brief ADC common trigger source select + ** + ******************************************************************************/ +typedef enum en_adc_com_trigger +{ + AdcComTrigger_1 = 0x1, ///< Select common trigger 1. + AdcComTrigger_2 = 0x2, ///< Select common trigger 2. + AdcComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_adc_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Structure definition of ADC + ** + ******************************************************************************/ +typedef struct stc_adc_ch_cfg +{ + uint32_t u32Channel; ///< ADC channels mask. + uint8_t u8Sequence; ///< The sequence which the channel(s) belong to. + uint8_t *pu8SampTime; ///< Pointer to sampling time. +} stc_adc_ch_cfg_t; + +typedef struct stc_adc_awd_cfg +{ + en_adc_awdmd_t enAwdmd; ///< Comparison mode of the values. + en_adc_awdss_t enAwdss; ///< Interrupt output select. + uint16_t u16AwdDr0; ///< Your range DR0. + uint16_t u16AwdDr1; ///< Your range DR1. +} stc_adc_awd_cfg_t; + +typedef struct stc_adc_trg_cfg +{ + uint8_t u8Sequence; ///< The sequence will be configured trigger source. + en_adc_trgsel_t enTrgSel; ///< Trigger source type. + en_event_src_t enInTrg0; ///< Internal trigger 0 source number + ///< (event number @ref en_event_src_t). + en_event_src_t enInTrg1; ///< Internal trigger 1 source number + ///< (event number @ref en_event_src_t). +} stc_adc_trg_cfg_t; + +typedef struct stc_adc_init +{ + en_adc_resolution_t enResolution; ///< ADC resolution 12bit/10bit/8bit. + en_adc_data_align_t enDataAlign; ///< ADC data alignment. + en_adc_clren_t enAutoClear; ///< Automatically clear data register. + ///< after reading data register(enable/disable). + en_adc_scan_mode_t enScanMode; ///< ADC scan mode. + en_adc_rschsel_t enRschsel; ///< Restart or continue. +} stc_adc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC sequence definition. + ** + ******************************************************************************/ +/* ADC sequence definition */ +#define ADC_SEQ_A ((uint8_t)0) +#define ADC_SEQ_B ((uint8_t)1) + +/* ADC pin definition */ +#define ADC1_IN0 ((uint8_t)0) +#define ADC1_IN1 ((uint8_t)1) +#define ADC1_IN2 ((uint8_t)2) +#define ADC1_IN3 ((uint8_t)3) +#define ADC12_IN4 ((uint8_t)4) +#define ADC12_IN5 ((uint8_t)5) +#define ADC12_IN6 ((uint8_t)6) +#define ADC12_IN7 ((uint8_t)7) +#define ADC12_IN8 ((uint8_t)8) +#define ADC12_IN9 ((uint8_t)9) +#define ADC12_IN10 ((uint8_t)10) +#define ADC12_IN11 ((uint8_t)11) +#define ADC1_IN12 ((uint8_t)12) +#define ADC1_IN13 ((uint8_t)13) +#define ADC1_IN14 ((uint8_t)14) +#define ADC1_IN15 ((uint8_t)15) +#define ADC_PIN_INVALID ((uint8_t)0xFF) + +/* ADC channel index definition */ +#define ADC_CH_IDX0 (0u) +#define ADC_CH_IDX1 (1u) +#define ADC_CH_IDX2 (2u) +#define ADC_CH_IDX3 (3u) +#define ADC_CH_IDX4 (4u) +#define ADC_CH_IDX5 (5u) +#define ADC_CH_IDX6 (6u) +#define ADC_CH_IDX7 (7u) +#define ADC_CH_IDX8 (8u) +#define ADC_CH_IDX9 (9u) +#define ADC_CH_IDX10 (10u) +#define ADC_CH_IDX11 (11u) +#define ADC_CH_IDX12 (12u) +#define ADC_CH_IDX13 (13u) +#define ADC_CH_IDX14 (14u) +#define ADC_CH_IDX15 (15u) +#define ADC_CH_IDX16 (16u) + +/* ADC1 channel mask definition */ +#define ADC1_CH0 (0x1ul << 0u) ///< Default mapping pin ADC1_IN0 +#define ADC1_CH1 (0x1ul << 1u) ///< Default mapping pin ADC1_IN1 +#define ADC1_CH2 (0x1ul << 2u) ///< Default mapping pin ADC1_IN2 +#define ADC1_CH3 (0x1ul << 3u) ///< Default mapping pin ADC1_IN3 +#define ADC1_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN4 +#define ADC1_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN5 +#define ADC1_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN6 +#define ADC1_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN7 +#define ADC1_CH8 (0x1ul << 8u) ///< Default mapping pin ADC12_IN8 +#define ADC1_CH9 (0x1ul << 9u) ///< Default mapping pin ADC12_IN9 +#define ADC1_CH10 (0x1ul << 10u) ///< Default mapping pin ADC12_IN10 +#define ADC1_CH11 (0x1ul << 11u) ///< Default mapping pin ADC12_IN11 +#define ADC1_CH12 (0x1ul << 12u) ///< Default mapping pin ADC12_IN12 +#define ADC1_CH13 (0x1ul << 13u) ///< Default mapping pin ADC12_IN13 +#define ADC1_CH14 (0x1ul << 14u) ///< Default mapping pin ADC12_IN14 +#define ADC1_CH15 (0x1ul << 15u) ///< Default mapping pin ADC12_IN15 +#define ADC1_CH16 (0x1ul << 16u) +#define ADC1_CH_INTERNAL (ADC1_CH16) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC1_CH_ALL (0x0001FFFFul) +#define ADC1_PIN_MASK_ALL (ADC1_CH_ALL & ~ADC1_CH_INTERNAL) + +/* ADC2 channel definition */ +#define ADC2_CH0 (0x1ul << 0u) ///< Default mapping pin ADC12_IN4 +#define ADC2_CH1 (0x1ul << 1u) ///< Default mapping pin ADC12_IN5 +#define ADC2_CH2 (0x1ul << 2u) ///< Default mapping pin ADC12_IN6 +#define ADC2_CH3 (0x1ul << 3u) ///< Default mapping pin ADC12_IN7 +#define ADC2_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN8 +#define ADC2_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN9 +#define ADC2_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN10 +#define ADC2_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN11 +#define ADC2_CH8 (0x1ul << 8u) +#define ADC2_CH_INTERNAL (ADC2_CH8) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC2_CH_ALL (0x000001FFul) +#define ADC2_PIN_MASK_ALL (ADC2_CH_ALL & ~ADC2_CH_INTERNAL) + +/* +* PGA channel definition. +* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel. +*/ +#define PGA_CH0 (0x1ul << ADC1_IN0) ///< Mapping pin ADC1_IN0 +#define PGA_CH1 (0x1ul << ADC1_IN1) ///< Mapping pin ADC1_IN1 +#define PGA_CH2 (0x1ul << ADC1_IN2) ///< Mapping pin ADC1_IN2 +#define PGA_CH3 (0x1ul << ADC1_IN3) ///< Mapping pin ADC1_IN3 +#define PGA_CH4 (0x1ul << ADC12_IN4) ///< Mapping pin ADC12_IN4 +#define PGA_CH5 (0x1ul << ADC12_IN5) ///< Mapping pin ADC12_IN5 +#define PGA_CH6 (0x1ul << ADC12_IN6) ///< Mapping pin ADC12_IN6 +#define PGA_CH7 (0x1ul << ADC12_IN7) ///< Mapping pin ADC12_IN7 +#define PGA_CH8 (0x1ul << ADC12_IN8) ///< Mapping internal 8bit DAC1 output +#define PGA_CH_ALL (0x000001FFul) + +/* ADC1 has up to 17 channels */ +#define ADC1_CH_COUNT (17u) + +/* ADC2 has up to 9 channels */ +#define ADC2_CH_COUNT (9u) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit); +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx); + +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode); +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg); +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg); +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); + +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt); +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg); +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn); +void ADC_PgaCmd(en_functional_state_t enState); +void ADC_AddPgaChannel(uint32_t u32Channel); +void ADC_DelPgaChannel(uint32_t u32Channel); + +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay); +void ADC_SyncCmd(en_functional_state_t enState); + +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx); +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx); +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout); + +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length); +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh); + +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin); +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +//@} // AdcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_ADC_ENABLE */ + +#endif /* __HC32F460_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h new file mode 100644 index 000000000..eca2f48cb --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h @@ -0,0 +1,81 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.h + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ +#ifndef __HC32F460_AES_H__ +#define __HC32F460_AES_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_AES_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AesGroup Advanced Encryption Standard(AES) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* AES key length in bytes is 16. */ +#define AES_KEYLEN ((uint8_t)16) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext); + +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext); + +//@} // AesGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_AES_ENABLE */ + +#endif /* __HC32F460_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h new file mode 100644 index 000000000..9bba878b4 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h @@ -0,0 +1,514 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.h + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of CAN + ** + ******************************************************************************/ +#ifndef __HC32F460_CAN_H__ +#define __HC32F460_CAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CanGroup Controller Area Network(CAN) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The Can error types. + ******************************************************************************/ +typedef enum +{ + NO_ERROR = 0U, + BIT_ERROR = 1U, + FORM_ERROR = 2U, + STUFF_ERROR = 3U, + ACK_ERROR = 4U, + CRC_ERROR = 5U, + UNKOWN_ERROR = 6U, +}en_can_error_t; + +/** + ******************************************************************************* + ** \brief The Can transmit buffer select.(TCMD) + ******************************************************************************/ +typedef enum +{ + CanPTBSel = 0U, ///< high-priority buffer + CanSTBSel = 1U, ///< secondary buffer +}en_can_buffer_sel_t; + +/** + ******************************************************************************* + ** \brief The Can warning limits.(AFWL) + ******************************************************************************/ +typedef struct stc_can_warning_limit +{ + uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit + uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit +}stc_can_warning_limit_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Frame Format Check.(ACF) + ******************************************************************************/ +typedef enum en_can_acf_format_en +{ + CanStdFrames = 0x02u, ///< Accepts only Standard frames + CanExtFrames = 0x03u, ///< Accepts only Extended frames + CanAllFrames = 0x00u, ///< Accepts both standard or extended frames +}en_can_acf_format_en_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Enable.(ACFEN) + ******************************************************************************/ +typedef enum en_can_filter_sel +{ + CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable + CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable + CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable + CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable + CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable + CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable + CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable + CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable +}en_can_filter_sel_t; + +/** + ******************************************************************************* + ** \brief The can interrupt enable.(IE) + ******************************************************************************/ +typedef enum +{ + //<empty and =almost full, but not full and no overflow + CanRxBufFull = 3, ///< full +}en_can_rx_buf_status_t; + +/** + ******************************************************************************* + ** \brief The Can Transmission secondary Status.(TSSTAT) + ******************************************************************************/ +typedef enum +{ + CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty + ///< TTEN=1 and TTTBM=1: PTB and STB are empty + CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full + ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full + CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full + ///< TTEN=1 and TTTBM=1: None + CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full + ///< TTEN=1 and TTTBM=1: PTB and STB are full +}en_can_tx_buf_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Acceptance Filter Code and Mask. + ******************************************************************************/ +typedef struct stc_can_filter +{ + uint32_t u32CODE; ///< Acceptance CODE + uint32_t u32MASK; ///< Acceptance MASK + en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable + en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check. +}stc_can_filter_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Bit Timing. + ******************************************************************************/ +typedef struct stc_can_bt +{ + uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ) + uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ) + uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ) + uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ) +}stc_can_bt_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Control Frame. + ******************************************************************************/ +typedef struct +{ + uint32_t DLC : 4; ///< Data length code + uint32_t RESERVED0 : 2; ///< Ignore + uint32_t RTR : 1; ///< Remote transmission request + uint32_t IDE : 1; ///< IDentifier extension + uint32_t RESERVED1 : 24; ///< Ignore +}stc_can_txcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Tx Frame. + ******************************************************************************/ +typedef struct stc_can_txframe +{ + union + { + uint32_t TBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t TBUF32_1; ///< Ignore + stc_can_txcontrol_t Control_f; ///< CAN Tx Control + }; + union + { + uint32_t TBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; + en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select +}stc_can_txframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx Ctrl. + ******************************************************************************/ +typedef struct +{ + uint8_t DLC : 4; ///< Data length code + uint8_t RESERVED0 : 2; ///< Ignore + uint8_t RTR : 1; ///< Remote transmission request + uint8_t IDE : 1; ///< IDentifier extension +}stc_can_rxcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN status. + ******************************************************************************/ +typedef struct +{ + uint8_t RESERVED0 : 4; ///< Ignore + uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated + uint8_t KOER : 3; ///< Kind of error +}stc_can_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN control, status and cycletime. + ******************************************************************************/ +typedef struct +{ + stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t + stc_can_status_t Status_f; ///< @ref stc_can_status_t + uint16_t CycleTime; ///< TTCAN cycletime +}stc_can_cst_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_rxframe +{ + union + { + uint32_t RBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t RBUF32_1; ///< Ignore + stc_can_cst_t Cst; ///< @ref stc_can_cst_t + }; + union + { + uint32_t RBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; +}stc_can_rxframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_init_config +{ + en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t + en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t + en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t + en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t + stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t + stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t +}stc_can_init_config_t; + +/** + ******************************************************************************* + ** \brief CAN TTCAN + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN pointer to a TB message slot + ******************************************************************************/ +typedef enum +{ + CanTTcanPTBSel = 0x00u, ///< PTB + CanTTcanSTB1Sel = 0x01u, ///< STB1 + CanTTcanSTB2Sel = 0x02u, ///< STB2 + CanTTcanSTB3Sel = 0x03u, ///< STB3 + CanTTcanSTB4Sel = 0x04u, ///< STB4 +}en_can_ttcan_tbslot_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Timer prescaler + ******************************************************************************/ +typedef enum +{ + CanTTcanTprescDiv1 = 0x00u, ///< Div1 + CanTTcanTprescDiv2 = 0x01u, ///< Div2 + CanTTcanTprescDiv3 = 0x02u, ///< Div3 + CanTTcanTprescDiv4 = 0x03u, ///< Div4 +}en_can_ttcan_Tpresc_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Trigger type + ******************************************************************************/ +typedef enum +{ + CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission + CanTTcanTime = 0x01, ///< Time trigger for receive trigger + CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows + CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows + CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows +}en_can_ttcan_trigger_type_t; + +typedef enum +{ + CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt + CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt +}en_can_ttcan_irq_type_t; + + +typedef struct stc_can_ttcan_ref_msg +{ + uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard; + union ///< Reference message ID + { + uint32_t RefStdID; ///< Reference standard ID + uint32_t RefExtID; ///< Reference Extended ID + }; +}stc_can_ttcan_ref_msg_t; + +typedef struct stc_can_ttcan_trigger_config +{ + en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer + en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type + en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler + uint8_t u8Tew; ///< Transmit enable window + uint16_t u16TrigTime; ///< TTCAN trigger time + uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register +}stc_can_ttcan_trigger_config_t; + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CAN_Init(stc_can_init_config_t *pstcCanInitCfg); +void CAN_DeInit(void); +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState); +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState); +en_can_error_t CAN_ErrorStatusGet(void); +bool CAN_StatusGet(en_can_status_t enCanStatus); + +void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState); +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame); +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd); +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame); + +uint8_t CAN_ArbitrationLostCap(void); +uint8_t CAN_RxErrorCntGet(void); +uint8_t CAN_TxErrorCntGet(void); + + +//<< void CAN_TTCAN_Enable(void); +//<< void CAN_TTCAN_Disable(void); +//<< void CAN_TTCAN_IrqCmd(void); +//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg); +//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg); + +//@} // CanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CAN_ENABLE */ + +#endif /* __HC32F460_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h new file mode 100644 index 000000000..84c555dc2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h @@ -0,0 +1,647 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.h + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ +#ifndef __HC32F460_CLK_H__ +#define __HC32F460_CLK_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CLK_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmuGroup Clock Manage Unit(CMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The system clock source. + ** + ******************************************************************************/ + typedef enum en_clk_sys_source + { + ClkSysSrcHRC = 0u, ///< The system clock source is HRC. + ClkSysSrcMRC = 1u, ///< The system clock source is MRC. + ClkSysSrcLRC = 2u, ///< The system clock source is LRC. + ClkSysSrcXTAL = 3u, ///< The system clock source is XTAL. + ClkSysSrcXTAL32 = 4u, ///< The system clock source is XTAL32. + CLKSysSrcMPLL = 5u, ///< The system clock source is MPLL. + }en_clk_sys_source_t; + +/** + ******************************************************************************* + ** \brief The pll clock source. + ** + ******************************************************************************/ + typedef enum en_clk_pll_source + { + ClkPllSrcXTAL = 0u, ///< The pll clock source is XTAL. + ClkPllSrcHRC = 1u, ///< The pll clock source is HRC. + }en_clk_pll_source_t; + +/** + ******************************************************************************* + ** \brief The usb clock source. + ** + ******************************************************************************/ +typedef enum en_clk_usb_source +{ + ClkUsbSrcSysDiv2 = 2u, ///< The usb clock source is 1/2 system clock. + ClkUsbSrcSysDiv3 = 3u, ///< The usb clock source is 1/3 system clock. + ClkUsbSrcSysDiv4 = 4u, ///< The usb clock source is 1/4 system clock. + ClkUsbSrcMpllp = 8u, ///< The usb clock source is MPLLP. + ClkUsbSrcMpllq = 9u, ///< The usb clock source is MPLLQ. + ClkUsbSrcMpllr = 10u, ///< The usb clock source is MPLLR. + ClkUsbSrcUpllp = 11u, ///< The usb clock source is UPLLP. + ClkUsbSrcUpllq = 12u, ///< The usb clock source is UPLLQ. + ClkUsbSrcUpllr = 13u, ///< The usb clock source is UPLLR. +}en_clk_usb_source_t; + +/** + ******************************************************************************* + ** \brief The peripheral(adc/trng/I2S) clock source. + ** + ******************************************************************************/ +typedef enum en_clk_peri_source +{ + ClkPeriSrcPclk = 0u, ///< The peripheral(adc/trng/I2S) clock source is division from system clock. + ClkPeriSrcMpllp = 8u, ///< The peripheral(adc/trng/I2S) clock source is MPLLP. + ClkPeriSrcMpllq = 9u, ///< The peripheral(adc/trng/I2S) clock source is MPLLQ. + ClkPeriSrcMpllr = 10u, ///< The peripheral(adc/trng/I2S) clock source is MPLLR. + ClkPeriSrcUpllp = 11u, ///< The peripheral(adc/trng/I2S) clock source is UPLLP. + ClkPeriSrcUpllq = 12u, ///< The peripheral(adc/trng/I2S) clock source is UPLLQ. + ClkPeriSrcUpllr = 13u, ///< The peripheral(adc/trng/I2S) clock source is UPLLR. +}en_clk_peri_source_t; + +/** + ******************************************************************************* + ** \brief The clock output source. + ** + ******************************************************************************/ +typedef enum en_clk_output_source +{ + ClkOutputSrcHrc = 0u, ///< The clock output source is HRC + ClkOutputSrcMrc = 1u, ///< The clock output source is MRC. + ClkOutputSrcLrc = 2u, ///< The clock output source is LRC. + ClkOutputSrcXtal = 3u, ///< The clock output source is XTAL. + ClkOutputSrcXtal32 = 4u, ///< The clock output source is XTAL32 + ClkOutputSrcMpllp = 6u, ///< The clock output source is MPLLP. + ClkOutputSrcUpllp = 7u, ///< The clock output source is UPLLP. + ClkOutputSrcMpllq = 8u, ///< The clock output source is MPLLQ. + ClkOutputSrcUpllq = 9u, ///< The clock output source is UPLLQ. + ClkOutputSrcSysclk = 11u, ///< The clock output source is system clock. +}en_clk_output_source_t; + +/** + ******************************************************************************* + ** \brief The clock frequency source for measure or reference. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_source +{ + ClkFcmSrcXtal = 0u, ///< The clock frequency measure or reference source is XTAL + ClkFcmSrcXtal32 = 1u, ///< The clock frequency measure or reference source is XTAL32. + ClkFcmSrcHrc = 2u, ///< The clock frequency measure or reference source is HRC. + ClkFcmSrcLrc = 3u, ///< The clock frequency measure or reference source is LRC. + ClkFcmSrcSwdtrc = 4u, ///< The clock frequency measure or reference source is SWDTRC + ClkFcmSrcPclk1 = 5u, ///< The clock frequency measure or reference source is PCLK1. + ClkFcmSrcUpllp = 6u, ///< The clock frequency measure or reference source is UPLLP. + ClkFcmSrcMrc = 7u, ///< The clock frequency measure or reference source is MRC. + ClkFcmSrcMpllp = 8u, ///< The clock frequency measure or reference source is MPLLP. + ClkFcmSrcRtcLrc = 9u, ///< The clock frequency measure or reference source is RTCLRC. +}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t; + +/** + ******************************************************************************* + ** \brief The clock flag status. + ** + ******************************************************************************/ +typedef enum en_clk_flag +{ + ClkFlagHRCRdy = 0u, ///< The clock flag is HRC ready. + ClkFlagXTALRdy = 1u, ///< The clock flag is XTAL ready. + ClkFlagMPLLRdy = 2u, ///< The clock flag is MPLL ready. + ClkFlagUPLLRdy = 3u, ///< The clock flag is UPLL ready. + ClkFlagXTALStoppage = 4u, ///< The clock flag is XTAL stoppage. +}en_clk_flag_t; + +/** + ******************************************************************************* + ** \brief The clock frequency measure flag status. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_flag +{ + ClkFcmFlagErrf = 0u, ///< The clock frequency flag is frequency abnormal. + ClkFcmFlagMendf = 1u, ///< The clock frequency flag is end of measurement. + ClkFcmFlagOvf = 2u, ///< The clock frequency flag is counter overflow. +}en_clk_fcm_flag_t; + +/** + ******************************************************************************* + ** \brief The source of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_mode +{ + ClkXtalModeOsc = 0u, ///< Use external high speed osc as source. + ClkXtalModeExtClk = 1u, ///< Use external clk as source. +}en_clk_xtal_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_drv +{ + ClkXtalHighDrv = 0u, ///< High drive capability.20MHz~24MHz. + ClkXtalMidDrv = 1u, ///< Middle drive capability.16MHz~20MHz. + ClkXtalLowDrv = 2u, ///< Low drive capability.8MHz~16MHz. + ClkXtalTinyDrv = 3u, ///< Tiny drive capability.8MHz. +}en_clk_xtal_drv_t; + +/** + ******************************************************************************* + ** \brief The stable time of XTAL. + ** + ** \note It depends on SUPDRV bit. + ******************************************************************************/ +typedef enum en_clk_xtal_stb_cycle +{ + ClkXtalStbCycle35 = 1u, ///< stable time is 35(36) cycle. + ClkXtalStbCycle67 = 2u, ///< stable time is 67(68) cycle. + ClkXtalStbCycle131 = 3u, ///< stable time is 131(132) cycle. + ClkXtalStbCycle259 = 4u, ///< stable time is 259(260) cycle. + ClkXtalStbCycle547 = 5u, ///< stable time is 547(548) cycle. + ClkXtalStbCycle1059 = 6u, ///< stable time is 1059(1060) cycle. + ClkXtalStbCycle2147 = 7u, ///< stable time is 2147(2148) cycle. + ClkXtalStbCycle4291 = 8u, ///< stable time is 4291(4292) cycle. + ClkXtalStbCycle8163 = 9u, ///< stable time is 8163(8164) cycle. +}en_clk_xtal_stb_cycle_t; + +/** + ******************************************************************************* + ** \brief The handle of xtal stoppage. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_stp_mode +{ + ClkXtalStpModeInt = 0u, ///< The handle of stoppage is interrupt. + ClkXtalStpModeReset = 1u, ///< The handle of stoppage is reset. +}en_clk_xtal_stp_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_drv +{ + ClkXtal32MidDrv = 0u, ///< Middle drive capability.32.768KHz. + ClkXtal32HighDrv = 1u, ///< High drive capability.32.768KHz. +}en_clk_xtal32_drv_t; + +/** + ******************************************************************************* + ** \brief The filter mode of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_filter_mode +{ + ClkXtal32FilterModeFull = 0u, ///< Valid in run,stop,power down mode. + ClkXtal32FilterModePart = 2u, ///< Valid in run mode. + ClkXtal32FilterModeNone = 3u, ///< Invalid in run,stop,power down mode. +}en_clk_xtal32_filter_mode_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock. + ** + ******************************************************************************/ +typedef enum en_clk_sysclk_div_factor +{ + ClkSysclkDiv1 = 0u, ///< 1 division. + ClkSysclkDiv2 = 1u, ///< 2 division. + ClkSysclkDiv4 = 2u, ///< 4 division. + ClkSysclkDiv8 = 3u, ///< 8 division. + ClkSysclkDiv16 = 4u, ///< 16 division. + ClkSysclkDiv32 = 5u, ///< 32 division. + ClkSysclkDiv64 = 6u, ///< 64 division. +}en_clk_sysclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock.It will be used for debug clock. + ** + ******************************************************************************/ +typedef enum en_clk_tpiuclk_div_factor +{ + ClkTpiuclkDiv1 = 0u, ///< 1 division. + ClkTpiuclkDiv2 = 1u, ///< 2 division. + ClkTpiuclkDiv4 = 2u, ///< 4 division. +}en_clk_tpiuclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_div_factor +{ + ClkOutputDiv1 = 0u, ///< 1 division. + ClkOutputDiv2 = 1u, ///< 2 division. + ClkOutputDiv4 = 2u, ///< 4 division. + ClkOutputDiv8 = 3u, ///< 8 division. + ClkOutputDiv16 = 4u, ///< 16 division. + ClkOutputDiv32 = 5u, ///< 32 division. + ClkOutputDiv64 = 6u, ///< 64 division. + ClkOutputDiv128 = 7u, ///< 128 division. +}en_clk_output_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm measure source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_measure_div_factor +{ + ClkFcmMeaDiv1 = 0u, ///< 1 division. + ClkFcmMeaDiv4 = 1u, ///< 4 division. + ClkFcmMeaDiv8 = 2u, ///< 8 division. + ClkFcmMeaDiv32 = 3u, ///< 32 division. +}en_clk_fcm_measure_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_intref_div_factor +{ + ClkFcmIntrefDiv32 = 0u, ///< 32 division. + ClkFcmIntrefDiv128 = 1u, ///< 128 division. + ClkFcmIntrefDiv1024 = 2u, ///< 1024 division. + ClkFcmIntrefDiv8192 = 3u, ///< 8192 division. +}en_clk_fcm_intref_div_factor_t; + +/** + ******************************************************************************* + ** \brief The edge of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_edge +{ + ClkFcmEdgeRising = 0u, ///< Rising edge. + ClkFcmEdgeFalling = 1u, ///< Falling edge. + ClkFcmEdgeBoth = 2u, ///< Both edge. +}en_clk_fcm_edge_t; + +/** + ******************************************************************************* + ** \brief The filter clock of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_filter_clk +{ + ClkFcmFilterClkNone = 0u, ///< None filter. + ClkFcmFilterClkFcmSrc = 1u, ///< Use fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv4 = 2u, ///< Use 1/4 fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv16 = 3u, ///< Use 1/16 fcm measurement source as filter clock. +}en_clk_fcm_filter_clk_t; + +/** + ******************************************************************************* + ** \brief The fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_refer +{ + ClkFcmExtRef = 0u, ///< Use external reference. + ClkFcmInterRef = 1u, ///< Use internal reference. +}en_clk_fcm_refer_t; + +/** + ******************************************************************************* + ** \brief The handle of fcm abnormal. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_abnormal_handle +{ + ClkFcmHandleInterrupt = 0u, ///< The handle of fcm abnormal is interrupt. + ClkFcmHandleReset = 1u, ///< The handle of fcm abnormal is reset. +}en_clk_fcm_abnormal_handle_t; + +/** + ******************************************************************************* + ** \brief The channel of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_ch +{ + ClkOutputCh1 = 1u, ///< The output of clk is MCO_1. + ClkOutputCh2 = 2u, ///< The output of clk is MCO_2. +}en_clk_output_ch_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL. + ** + ** \note Configures the XTAL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_cfg +{ + en_functional_state_t enFastStartup; ///< Enable fast start up or not. + en_clk_xtal_mode_t enMode; ///< Select xtal mode. + en_clk_xtal_drv_t enDrv; ///< Select xtal drive capability. +}stc_clk_xtal_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL stoppage. + ** + ** \note Configures the XTAL stoppage if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_stp_cfg +{ + en_functional_state_t enDetect; ///< Enable detect stoppage or not. + en_clk_xtal_stp_mode_t enMode; ///< Select the handle of xtal stoppage. + en_functional_state_t enModeReset; ///< Enable reset for handle the xtal stoppage. + en_functional_state_t enModeInt; ///< Enable interrupt for handle the xtal stoppage. +}stc_clk_xtal_stp_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL32. + ** + ** \note Configures the XTAL32 if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal32_cfg +{ + en_clk_xtal32_drv_t enDrv; ///< Select xtal32 drive capability. + en_clk_xtal32_filter_mode_t enFilterMode; ///< The filter mode of xtal32. +}stc_clk_xtal32_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of PLL. + ** + ** \note Configures the PLL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_pll_cfg +{ + uint32_t PllpDiv; ///< Pllp clk, division factor of VCO out. + uint32_t PllqDiv; ///< Pllq clk, division factor of VCO out. + uint32_t PllrDiv; ///< Pllr clk, division factor of VCO out. + uint32_t plln; ///< Multiplication factor of vco out, ensure between 240M~480M + uint32_t pllmDiv; ///< Division factor of VCO in, ensure between 1M~12M. +}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of system clock. + ** + ** \note Configures the system clock if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_sysclk_cfg +{ + en_clk_sysclk_div_factor_t enHclkDiv; ///< Division for hclk. + en_clk_sysclk_div_factor_t enExclkDiv; ///< Division for exclk. + en_clk_sysclk_div_factor_t enPclk0Div; ///< Division for pclk0. + en_clk_sysclk_div_factor_t enPclk1Div; ///< Division for pclk1. + en_clk_sysclk_div_factor_t enPclk2Div; ///< Division for pclk2. + en_clk_sysclk_div_factor_t enPclk3Div; ///< Division for pclk3. + en_clk_sysclk_div_factor_t enPclk4Div; ///< Division for pclk4. +}stc_clk_sysclk_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of clock output. + ** + ** \note Configures the clock output if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_output_cfg +{ + en_clk_output_source_t enOutputSrc; ///< The clock output source. + en_clk_output_div_factor_t enOutputDiv; ///< The division factor of clock output source. +}stc_clk_output_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm window. + ** + ** \note Configures the fcm window if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_window_cfg +{ + uint16_t windowLower; ///< The lower value of the window. + uint16_t windowUpper; ///< The upper value of the window. +}stc_clk_fcm_window_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm measurement. + ** + ** \note Configures the fcm measurement if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_measure_cfg +{ + en_clk_fcm_measure_source_t enSrc; ///< The measurement source. + en_clk_fcm_measure_div_factor_t enSrcDiv; ///< The division factor of measurement source. +}stc_clk_fcm_measure_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm reference. + ** + ** \note Configures the fcm reference if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_reference_cfg +{ + en_functional_state_t enExtRef; ///< Enable external reference or not. + en_clk_fcm_edge_t enEdge; ///< The edge of internal reference. + en_clk_fcm_filter_clk_t enFilterClk; ///< The filter clock of internal reference. + en_clk_fcm_refer_t enRefSel; ///< Select reference. + en_clk_fcm_intref_source_t enIntRefSrc; ///< Select internal reference. + en_clk_fcm_intref_div_factor_t enIntRefDiv; ///< The division factor of internal reference. +}stc_clk_fcm_reference_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm interrupt. + ** + ** \note Configures the fcm interrupt if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_interrupt_cfg +{ + en_clk_fcm_abnormal_handle_t enHandleSel; ///< Use interrupt or reset. + en_functional_state_t enHandleReset; ///< Enable reset or not. + en_functional_state_t enHandleInterrupt; ///< Enable interrupt or not. + en_functional_state_t enOvfInterrupt; ///< Enable overflow interrupt or not. + en_functional_state_t enEndInterrupt; ///< Enable measurement end interrupt or not. +}stc_clk_fcm_interrupt_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm. + ** + ** \note Configures the fcm if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_cfg +{ + stc_clk_fcm_window_cfg_t *pstcFcmWindowCfg; ///< Window configuration struct. + stc_clk_fcm_measure_cfg_t *pstcFcmMeaCfg; ///< Measurement configuration struct. + stc_clk_fcm_reference_cfg_t *pstcFcmRefCfg; ///< Reference configuration struct. + stc_clk_fcm_interrupt_cfg_t *pstcFcmIntCfg; ///< Interrupt configuration struct. +}stc_clk_fcm_cfg_t; + +/** + ******************************************************************************* + ** \brief Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_clk_freq +{ + uint32_t sysclkFreq; ///< System clock frequency. + uint32_t hclkFreq; ///< Hclk frequency. + uint32_t exckFreq; ///< Exclk frequency. + uint32_t pclk0Freq; ///< Pclk0 frequency. + uint32_t pclk1Freq; ///< Pclk1 frequency. + uint32_t pclk2Freq; ///< Pclk2 frequency. + uint32_t pclk3Freq; ///< Pclk3 frequency. + uint32_t pclk4Freq; ///< Pclk4 frequency. +}stc_clk_freq_t; + +/** + ******************************************************************************* + ** \brief PLL Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_pll_clk_freq +{ + uint32_t mpllp; ///< mpllp clock frequency. + uint32_t mpllq; ///< mpllq clock frequency. + uint32_t mpllr; ///< mpllr clock frequency. + uint32_t upllp; ///< upllp clock frequency. + uint32_t upllq; ///< upllq clock frequency. + uint32_t upllr; ///< upllr clock frequency. +}stc_pll_clk_freq_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg); +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb); +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg); +en_result_t CLK_XtalCmd(en_functional_state_t enNewState); + +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg); +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t trimValue); +en_result_t CLK_HrcCmd(en_functional_state_t enNewState); + +void CLK_MrcTrim(int8_t trimValue); +en_result_t CLK_MrcCmd(en_functional_state_t enNewState); + +void CLK_LrcTrim(int8_t trimValue); +en_result_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc); +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg); +en_result_t CLK_MpllCmd(en_functional_state_t enNewState); + +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg); +en_result_t CLK_UpllCmd(en_functional_state_t enNewState); + +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc); +en_clk_sys_source_t CLK_GetSysClkSource(void); + +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg); +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq); +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq); + +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc); +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc); +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc); +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg); + +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv); +void CLK_TpiuClkCmd(en_functional_state_t enNewState); + +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg); +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState); +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag); + +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg); +void CLK_FcmCmd(en_functional_state_t enNewState); + +uint16_t CLK_GetFcmCounter(void); +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag); +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag); + +void CLK_ClearXtalStdFlag(void); + +//@} // CmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CLK_ENABLE */ + +#endif /* __HC32F460_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h new file mode 100644 index 000000000..19d4b632d --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h @@ -0,0 +1,279 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.h + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ +#ifndef __HC32F460_CMP_H__ +#define __HC32F460_CMP_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CMP_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmpGroup Comparator(CMP) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief CMP function enumeration + ******************************************************************************/ +typedef enum en_cmp_func +{ + CmpVcoutOutput = (1u << 12), ///< CMP vcout output enable function + CmpOutpuInv = (1u << 13), ///< CMP output invert enable function + CmpOutput = (1u << 14), ///< CMP output enable function +} en_cmp_func_t; + +/** + ******************************************************************************* + ** \brief CMP edge selection enumeration + ******************************************************************************/ +typedef enum en_cmp_edge_sel +{ + CmpNoneEdge = 0u, ///< None edge detection + CmpRisingEdge = 1u, ///< Rising edge detection + CmpFaillingEdge = 2u, ///< Falling edge detection + CmpBothEdge = 3u, ///< Falling or Rising edge detection +} en_cmp_edge_sel_t; + +/** + ******************************************************************************* + ** \brief CMP filter sample clock division enumeration + ******************************************************************************/ +typedef enum en_cmp_fltclk_div +{ + CmpNoneFlt = 0u, ///< Unuse filter + CmpFltPclk3Div1 = 1u, ///< PCLK3/1 + CmpFltPclk3Div2 = 2u, ///< PCLK3/2 + CmpFltPclk3Div4 = 3u, ///< PCLK3/4 + CmpFltPclk3Div8 = 4u, ///< PCLK3/8 + CmpFltPclk3Div16 = 5u, ///< PCLK3/16 + CmpFltPclk3Div32 = 6u, ///< PCLK3/32 + CmpFltPclk3Div64 = 7u, ///< PCLK3/64 +} en_cmp_fltclk_div_t; + +/** + ******************************************************************************* + ** \brief CMP INP4 input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp4_sel +{ + CmpInp4None = 0u, ///< None input + CmpInp4PGAO = 1u, ///< PGAO output + CmpInp4PGAO_BP = 2u, ///< PGAO_BP output + CmpInp4CMP1_INP4 = 4u, ///< CMP1_INP4 +} en_cmp_inp4_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp_sel +{ + CmpInpNone = 0u, ///< None input + CmpInp1 = 1u, ///< INP1 input + CmpInp2 = 2u, ///< INP2 input + CmpInp1_Inp2 = 3u, ///< INP1 INP2 input + CmpInp3 = 4u, ///< INP3 input + CmpInp1_Inp3 = 5u, ///< INP1 INP3 input + CmpInp2_Inp3 = 6u, ///< INP2 INP3 input + CmpInp1_Inp2_Inp3 = 7u, ///< INP1 INP2 INP3 input + CmpInp4 = 8u, ///< INP4 input + CmpInp1_Inp4 = 9u, ///< INP1 INP4 input + CmpInp2_Inp4 = 10u, ///< INP2 INP4 input + CmpInp1_Inp2_Inp4 = 11u, ///< INP1 INP2 INP4 input + CmpInp3_Inp4 = 12u, ///< INP3 INP4 input + CmpInp1_Inp3_Inp4 = 13u, ///< INP1 INP3 INP4 input + CmpInp2_Inp3_Inp4 = 14u, ///< INP2 INP3 INP4 input + CmpInp1_Inp2_Inp3_Inp4 = 15u, ///< INP1 INP2 INP3 INP4 input +} en_cmp_inp_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INM input enumeration + ******************************************************************************/ +typedef enum en_cmp_inm_sel +{ + CmpInmNone = 0u, ///< None input + CmpInm1 = 1u, ///< INM1 input + CmpInm2 = 2u, ///< INM2 input + CmpInm3 = 4u, ///< INM3 input + CmpInm4 = 8u, ///< INM4 input +} en_cmp_inm_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_inp_state +{ + CmpInpNoneState = 0u, ///< none input state + CmpInp1State = 1u, ///< INP1 input state + CmpInp2State = 2u, ///< INP2 input state + CmpInp3State = 4u, ///< INP3 input state + CmpInp4State = 8u, ///< INP4 input state +} en_cmp_inp_state_t; + +/** + ******************************************************************************* + ** \brief CMP Output State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_output_state +{ + CmpOutputLow = 0u, ///< Compare output Low "0" + CmpOutputHigh = 1u, ///< Compare output High "1" +} en_cmp_output_state_t; + +/** + ******************************************************************************* + ** \brief CMP input selection + ******************************************************************************/ +typedef struct stc_cmp_input_sel +{ + en_cmp_inm_sel_t enInmSel; ///< CMP INM sel + + en_cmp_inp_sel_t enInpSel; ///< CMP INP sel + + en_cmp_inp4_sel_t enInp4Sel; ///< CMP INP4 sel +} stc_cmp_input_sel_t; + +/** + ****************************************************************************** + ** \brief DAC channel + ******************************************************************************/ +typedef enum en_cmp_dac_ch +{ + CmpDac1 = 0u, ///< DAC1 + CmpDac2 = 1u, ///< DAC2 +} en_cmp_dac_ch_t; + +/** + ****************************************************************************** + ** \brief ADC internal reference voltage path + ******************************************************************************/ +typedef enum en_cmp_adc_int_ref_volt_path +{ + CmpAdcRefVoltPathDac1 = (1u << 0u), ///< ADC internal reference voltage path: DAC1 + CmpAdcRefVoltPathDac2 = (1u << 1u), ///< ADC internal reference voltage path: DAC2 + CmpAdcRefVoltPathVref = (1u << 4u), ///< ADC internal reference voltage path: VREF +} en_cmp_adc_int_ref_volt_path_t; + +/** + ******************************************************************************* + ** \brief CMP initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_init +{ + en_cmp_edge_sel_t enEdgeSel; ///< CMP edge sel + + en_cmp_fltclk_div_t enFltClkDiv; ///< CMP FLTclock division + + en_functional_state_t enCmpOutputEn; ///< CMP Output enable + + en_functional_state_t enCmpVcoutOutputEn; ///< CMP output result enable + + en_functional_state_t enCmpInvEn; ///< CMP INV sel for output + + en_functional_state_t enCmpIntEN; ///< CMP interrupt enable +} stc_cmp_init_t; + +/** + ******************************************************************************* + ** \brief CMP DAC initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_dac_init +{ + uint8_t u8DacData; ///< CMP DAC Data register value + + en_functional_state_t enCmpDacEN; ///< CMP DAC enable +} stc_cmp_dac_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg); +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx); +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod); +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd); +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv); +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel); +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx); +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel); +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel); +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel); +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel); +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx); +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx); +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx); +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg); +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh); +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd); +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData); +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh); +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath); + +//@} // CmpGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CMP_ENABLE */ + +#endif /* __HC32F460_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h new file mode 100644 index 000000000..756d24924 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.h + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ +#ifndef __HC32F460_CRC_H__ +#define __HC32F460_CRC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CRC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CrcGroup Cyclic Redundancy Check(CRC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Bits definitions of CRC control register(CRC_CR). */ +/* + * Definitions of CRC protocol. + * NOTE: CRC16 polynomial is X16 + X12 + X5 + 1 + * CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \ + * X8 + X7 + X5 + X4 + X2 + X + 1 + */ +#define CRC_SEL_16B ((uint32_t)0x0) +#define CRC_SEL_32B ((uint32_t)(0x1ul << 1u)) + +/* + * Identifies the transpose configuration of the source data. + * If this function is enabled, the source data's bits in bytes are transposed. + * e.g. There's a source data 0x1234 which will be calculated checksum and this + * function is enabled, the final data be calculated is 0x482C. + * 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48. + * 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C. + * The same to 32 bit data while using CRC32. + */ +#define CRC_REFIN_DISABLE ((uint32_t)0x0) +#define CRC_REFIN_ENABLE ((uint32_t)(0x1ul << 2u)) + +/* + * Identifies the transpose configuration of the checksum. + * If this function is enabled, bits of the checksum will be transposed. + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then + * this function is enabled, the checksum will be 0x1E6A. + * 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_REFOUT_DISABLE ((uint32_t)0x0) +#define CRC_REFOUT_ENABLE ((uint32_t)(0x1ul << 3u)) + +/* + * XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32). + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled. + * If this function enabled, the checksum will be 0xA987. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_XOROUT_DISABLE ((uint32_t)0x0) +#define CRC_XOROUT_ENABLE ((uint32_t)(0x1ul << 4u)) + +#define CRC_CONFIG_MASK ((uint32_t)(0x1Eu)) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CRC_Init(uint32_t u32Config); +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length); +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length); +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length); +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length); + +//@} // CrcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CRC_ENABLE */ + +#endif /* __HC32F460_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h new file mode 100644 index 000000000..9ed3942d7 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h @@ -0,0 +1,216 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.h + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ +#ifndef __HC32F460_DCU_H__ +#define __HC32F460_DCU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_DCU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DcuGroup Data Computing Unit(DCU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief DCU register data enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_register +{ + DcuRegisterData0 = 0u, ///< DCU DATA0 + DcuRegisterData1 = 1u, ///< DCU DATA1 + DcuRegisterData2 = 2u, ///< DCU DATA2 +} en_dcu_data_register_t; + +/** + ******************************************************************************* + ** \brief DCU operation enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_operation_mode +{ + DcuInvalid = 0u, ///< DCU Invalid + DcuOpAdd = 1u, ///< DCU operation: Add + DcuOpSub = 2u, ///< DCU operation: Sub + DcuHwTrigOpAdd = 3u, ///< DCU operation: Hardware trigger Add + DcuHwTrigOpSub = 4u, ///< DCU operation: Hardware trigger Sub + DcuOpCompare = 5u, ///< DCU operation: Compare +} en_dcu_operation_mode_t; + +/** + ******************************************************************************* + ** \brief DCU data size enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_size +{ + DcuDataBit8 = 0u, ///< DCU data size: 8 bit + DcuDataBit16 = 1u, ///< DCU data size: 16 bit + DcuDataBit32 = 2u, ///< DCU data size: 32 bit +} en_dcu_data_size_t; + +/** + ******************************************************************************* + ** \brief DCU compare operation trigger mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_cmp_trigger_mode +{ + DcuCmpTrigbyData0 = 0u, ///< DCU compare triggered by DATA0 + DcuCmpTrigbyData012 = 1u, ///< DCU compare triggered by DATA0 or DATA1 or DATA2 +} en_dcu_cmp_trigger_mode_t; + +/** + ******************************************************************************* + ** \brief DCU interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_sel +{ + DcuIntOp = (1ul << 0), ///< DCU overflow or underflow interrupt + DcuIntLs2 = (1ul << 1), ///< DCU DATA0 < DATA2 interrupt + DcuIntEq2 = (1ul << 2), ///< DCU DATA0 = DATA2 interrupt + DcuIntGt2 = (1ul << 3), ///< DCU DATA0 > DATA2 interrupt + DcuIntLs1 = (1ul << 4), ///< DCU DATA0 < DATA1 interrupt + DcuIntEq1 = (1ul << 5), ///< DCU DATA0 = DATA1 interrupt + DcuIntGt1 = (1ul << 6), ///< DCU DATA0 > DATA1 interrupt +} en_dcu_int_sel_t, en_dcu_flag_t; + +/** + ******************************************************************************* + ** \brief DCU window interrupt mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_win_mode +{ + DcuIntInvalid = 0u, ///< DCU don't occur interrupt + DcuWinIntInvalid = 1u, ///< DCU window interrupt is invalid. + DcuInsideWinCmpInt = 2u, ///< DCU occur interrupt when DATA2 ≤ DATA0 ≤ DATA2 + DcuOutsideWinCmpInt = 3u, ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 +} en_dcu_int_win_mode_t; + +/* DCU common trigger source select */ +typedef enum en_dcu_com_trigger +{ + DcuComTrigger_1 = 1u, ///< Select common trigger 1. + DcuComTrigger_2 = 2u, ///< Select common trigger 2. + DcuComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_dcu_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DCU initialization configuration + ** + ******************************************************************************/ +typedef struct stc_dcu_init +{ + uint32_t u32IntSel; ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t + + en_functional_state_t enIntCmd; ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function + + en_dcu_int_win_mode_t enIntWinMode; ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t + + en_dcu_data_size_t enDataSize; ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t + + en_dcu_operation_mode_t enOperation; ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t + + en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t + +} stc_dcu_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg); +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode); +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize); +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode); +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode); +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx); +en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx); +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd); +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, uint8_t u8Data); +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data); +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data); +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc); +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState); + +//@} // DcuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_DCU_ENABLE */ + +#endif /* __HC32F460_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h new file mode 100644 index 000000000..6a7537371 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h @@ -0,0 +1,363 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.h + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ +#ifndef __HC32F460_DMAC_H__ +#define __HC32F460_DMAC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_DMAC_ENABLE == DDL_ON) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief DMA Channel + ** + ******************************************************************************/ +typedef enum en_dma_channel +{ + DmaCh0 = 0u, ///< DMA channel 0 + DmaCh1 = 1u, ///< DMA channel 1 + DmaCh2 = 2u, ///< DMA channel 2 + DmaCh3 = 3u, ///< DMA channel 3 + DmaChMax = 4u ///< DMA channel max +}en_dma_channel_t; + +/** + ******************************************************************************* + ** \brief DMA transfer data width + ** + ******************************************************************************/ +typedef enum en_dma_transfer_width +{ + Dma8Bit = 0u, ///< 8 bit transfer via DMA + Dma16Bit = 1u, ///< 16 bit transfer via DMA + Dma32Bit = 2u ///< 32 bit transfer via DMA +}en_dma_transfer_width_t; + +/** + ******************************************************************************* + ** \brief DMA flag + ** + ******************************************************************************/ +typedef enum en_dma_flag +{ + DmaTransferComplete = 0u, ///< DMA transfer complete + DmaBlockComplete = 1u, ///< DMA block transfer complete + DmaTransferErr = 2u, ///< DMA transfer error + DmaReqErr = 3u, ///< DMA transfer request error + DmaFlagMax = 4u +}en_dma_flag_t; + +/** + ******************************************************************************* + ** \brief DMA address mode + ** + ******************************************************************************/ +typedef enum en_dma_address_mode +{ + AddressFix = 0u, ///< Address fixed + AddressIncrease = 1u, ///< Address increased + AddressDecrease = 2u, ///< Address decreased +}en_dma_address_mode_t; + +/** + ******************************************************************************* + ** \brief DMA link list pointer mode + ** + ******************************************************************************/ +typedef enum en_dma_llp_mode +{ + LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request + LlpRunNow = 1u, ///< DMA trigger transfer now +}en_dma_llp_mode_t; + +/** + ******************************************************************************* + ** \brief DMA interrupt selection + ** + ******************************************************************************/ +typedef enum en_dma_irq_sel +{ + TrnErrIrq = 0u, ///< Select DMA transfer error interrupt + TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt + TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt + BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt + DmaIrqSelMax = 4u +}en_dma_irq_sel_t; + +/** + ******************************************************************************* + ** \brief DMA re_config count mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_cnt_mode +{ + CntFix = 0u, ///< Fix + CntSrcAddr = 1u, ///< Source address mode + CntDesAddr = 2u, ///< Destination address mode +}en_dma_recfg_cnt_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config destination address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_daddr_mode +{ + DaddrFix = 0u, ///< Fix + DaddrNseq = 1u, ///< No_sequence address + DaddrRep = 2u, ///< Repeat address +}en_dma_recfg_daddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config source address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_saddr_mode +{ + SaddrFix = 0u, ///< Fix + SaddrNseq = 1u, ///< No_sequence address + SaddrRep = 2u, ///< Repeat address +}en_dma_recfg_saddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA channel status + ** + ******************************************************************************/ +typedef enum en_dma_ch_flag +{ + DmaSta = 0u, ///< DMA status. + ReCfgSta = 1u, ///< DMA re_configuration status. + DmaCh0Sta = 2u, ///< DMA channel 0 status. + DmaCh1Sta = 3u, ///< DMA channel 1 status. + DmaCh2Sta = 4u, ///< DMA channel 2 status. + DmaCh3Sta = 5u, ///< DMA channel 3 status. +}en_dma_ch_flag_t; + +/** + ******************************************************************************* + ** \brief DMA common trigger source select + ** + ******************************************************************************/ +typedef enum en_dma_com_trigger +{ + DmaComTrigger_1 = 0x1, ///< Select common trigger 1. + DmaComTrigger_2 = 0x2, ///< Select common trigger 2. + DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_dma_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DMA llp descriptor + ** + ******************************************************************************/ +typedef struct stc_dma_llp_descriptor +{ + uint32_t SARx; ///< DMA source address register + uint32_t DARx; ///< DMA destination address register + union + { + uint32_t DTCTLx; + stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register + }; + union + { + uint32_t RPTx; + stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register + }; + union + { + uint32_t SNSEQCTLx; + stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register + }; + union + { + __IO uint32_t DNSEQCTLx; + stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register + }; + union + { + uint32_t LLPx; + stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register + }; + union + { + uint32_t CHxCTL; + stc_dma_ch0ctl_field_t CHxCTL_f; ///< DMA channel control register + }; +}stc_dma_llp_descriptor_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseq_cfg +{ + uint32_t u32Offset; ///< DMA no-sequence offset. + uint16_t u16Cnt; ///< DMA no-sequence count. +}stc_dma_nseq_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseqb_cfg +{ + uint32_t u32NseqDist; ///< DMA no-sequence district interval. + uint16_t u16CntB; ///< DMA no-sequence count. +}stc_dma_nseqb_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA re_config configuration + ** + ******************************************************************************/ +typedef struct stc_dma_recfg_ctl +{ + uint16_t u16SrcRptBSize; ///< The source repeat size. + uint16_t u16DesRptBSize; ///< The destination repeat size. + en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode. + en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode. + en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode. + stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config. + stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config. +}stc_dma_recfg_ctl_t; + +/** + ******************************************************************************* + ** \brief DMA channel configuration + ** + ******************************************************************************/ +typedef struct stc_dma_ch_cfg +{ + en_dma_address_mode_t enSrcInc; ///< DMA source address update mode. + en_dma_address_mode_t enDesInc; ///< DMA destination address update mode. + en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not. + en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not. + en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not. + en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not. + en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width. + en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not. + en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode. + en_functional_state_t enIntEn; ///< Enable interrupt function or not. +}stc_dma_ch_cfg_t; + + +/** + ******************************************************************************* + ** \brief DMA configuration + ** + ******************************************************************************/ +typedef struct stc_dma_config +{ + uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set. + uint16_t u16TransferCnt; ///< Transfer counter. + uint32_t u32SrcAddr; ///< The source address. + uint32_t u32DesAddr; ///< The destination address. + uint16_t u16SrcRptSize; ///< The source repeat size. + uint16_t u16DesRptSize; ///< The destination repeat size. + uint32_t u32DmaLlp; ///< The Dma linked list pointer address + stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration. + stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration. + stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration. +}stc_dma_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState); +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState); +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg); +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState); +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag); + +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize); +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt); +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg); +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg); +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg); +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg); +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer); + +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc); +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc); +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); + +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg); +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg); +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); + + + +//@} // DmacGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_DMAC_ENABLE */ + +#endif /* __HC32F460_DMAC_H__*/ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h new file mode 100644 index 000000000..a6185bb01 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h @@ -0,0 +1,209 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.h + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ +#ifndef __HC32F460_EFM_H__ +#define __HC32F460_EFM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EFM_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EfmGroup Embedded Flash Management unit(EFM) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The flash status. + ** + ******************************************************************************/ +typedef enum en_efm_flash_status +{ + FlashReady = 1u, ///< The flash ready flag. + FlashRWErr = 2u, ///< The flash read/write error flag. + FlashEOP = 3u, ///< The flash end of operation flag. + FlashPgMissMatch = 4u, ///< The flash program miss match flag. + FlashPgSizeErr = 5u, ///< The flash program size error flag. + FlashPgareaPErr = 6u, ///< The flash program protect area error flag. + FlashWRPErr = 7u, ///< The flash write protect error flag. +}en_efm_flash_status_t; + +/** + ******************************************************************************* + ** \brief The flash read mode. + ** + ******************************************************************************/ +typedef enum en_efm_read_md +{ + NormalRead = 0u, ///< The flash normal read mode. + UltraPowerRead = 1u, ///< The flash ultra power read mode. +}en_efm_read_md_t; + +/** + ******************************************************************************* + ** \brief The flash interrupt select. + ** + ******************************************************************************/ +typedef enum en_efm_int_sel +{ + PgmErsErrInt = 0u, ///< The flash program / erase error interrupt. + EndPgmInt = 1u, ///< The flash end of program interrupt. + ColErrInt = 2u, ///< The flash read collided error interrupt. +}en_efm_int_sel_t; + +/** + ******************************************************************************* + ** \brief The bus state while flash program & erase. + ** + ******************************************************************************/ +typedef enum en_efm_bus_sta +{ + BusBusy = 0u, ///< The bus busy while flash program & erase. + BusRelease = 1u, ///< The bus release while flash program & erase. +}en_efm_bus_sta_t; + +/** + ******************************************************************************* + ** \brief Structure of windows protect address. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_win_protect_addr +{ + uint32_t StartAddr; ///< The protect start address. + uint32_t EndAddr; ///< The protect end address. +}stc_efm_win_protect_addr_t; + +/** + ******************************************************************************* + ** \brief Structure of unique ID. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_unique_id +{ + uint32_t uniqueID1; ///< unique ID 1. + uint32_t uniqueID2; ///< unique ID 2. + uint32_t uniqueID3; ///< unique ID 3. +}stc_efm_unique_id_t; +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* Flach latency cycle (0~15) */ +#define EFM_LATENCY_0 (0ul) +#define EFM_LATENCY_1 (1ul) +#define EFM_LATENCY_2 (2ul) +#define EFM_LATENCY_3 (3ul) +#define EFM_LATENCY_4 (4ul) +#define EFM_LATENCY_5 (5ul) +#define EFM_LATENCY_6 (6ul) +#define EFM_LATENCY_7 (7ul) +#define EFM_LATENCY_8 (8ul) +#define EFM_LATENCY_9 (9ul) +#define EFM_LATENCY_10 (10ul) +#define EFM_LATENCY_11 (11ul) +#define EFM_LATENCY_12 (12ul) +#define EFM_LATENCY_13 (13ul) +#define EFM_LATENCY_14 (14ul) +#define EFM_LATENCY_15 (15ul) + +/* Flash flag */ +#define EFM_FLAG_WRPERR (0x00000001ul) +#define EFM_FLAG_PEPRTERR (0x00000002ul) +#define EFM_FLAG_PGSZERR (0x00000004ul) +#define EFM_FLAG_PGMISMTCH (0x00000008ul) +#define EFM_FLAG_EOP (0x00000010ul) +#define EFM_FLAG_COLERR (0x00000020ul) +#define EFM_FLAG_RDY (0x00000100ul) + +/* Flash operate mode */ +#define EFM_MODE_READONLY (0ul) +#define EFM_MODE_SINGLEPROGRAM (1ul) +#define EFM_MODE_SINGLEPROGRAMRB (2ul) +#define EFM_MODE_SEQUENCEPROGRAM (3ul) +#define EFM_MODE_SECTORERASE (4ul) +#define EFM_MODE_CHIPERASE (5ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void EFM_Unlock(void); +void EFM_Lock(void); + +void EFM_FlashCmd(en_functional_state_t enNewState); +void EFM_SetLatency(uint32_t u32Latency); +void EFM_InstructionCacheCmd(en_functional_state_t enNewState); +void EFM_DataCacheRstCmd(en_functional_state_t enNewState); +void EFM_SetReadMode(en_efm_read_md_t enReadMD); +void EFM_ErasePgmCmd(en_functional_state_t enNewState); +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode); +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState); + +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag); +en_flag_status_t EFM_GetSwitchStatus(void); +void EFM_ClearFlag(uint32_t u32flag); +en_efm_flash_status_t EFM_GetStatus(void); +void EFM_SetBusState(en_efm_bus_sta_t enState); + +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr); + +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf); +en_result_t EFM_SectorErase(uint32_t u32Addr); +en_result_t EFM_MassErase(uint32_t u32Addr); + +en_result_t EFM_OtpLock(uint32_t u32Addr); +stc_efm_unique_id_t EFM_ReadUID(void); + + +//@} // EfmGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EFM_ENABLE */ + +#endif /* __HC32F460_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h new file mode 100644 index 000000000..0820870be --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h @@ -0,0 +1,205 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.h + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ +#ifndef __HC32F460_EMB_H__ +#define __HC32F460_EMB_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EMB_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup EMBGroup Emergency Brake(EMB) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief EMB status enumeration + ******************************************************************************/ +typedef enum en_emb_status +{ + EMBFlagPortIn = 0u, ///< EMB port in brake flag + EMBFlagPWMSame = 1u, ///< EMB PWM same brake flag + EMBFlagCmp = 2u, ///< EMB CMP brake flag + EMBFlagOSCFail = 3u, ///< EMB oscillator fail brake flag + EMBPortInState = 4u, ///< EMB port in state + EMBPWMState = 5u, ///< EMB PWM same state +} en_emb_status_t; + +/** + ******************************************************************************* + ** \brief EMB status clear(recover) enumeration + ******************************************************************************/ +typedef enum en_emb_status_clr +{ + EMBPortInFlagClr = 0u, ///< EMB port in brake flag clear + EMBPWMSameFlagCLr = 1u, ///< EMB PWM same brake flag clear + EMBCmpFlagClr = 2u, ///< EMB CMP brake flag clear + EMBOSCFailFlagCLr = 3u, ///< EMB oscillator fail brake flag clear +} en_emb_status_clr_t; + +/** + ******************************************************************************* + ** \brief EMB irq enumeration + ******************************************************************************/ +typedef enum en_emb_irq_type +{ + PORTBrkIrq = 0u, ///< EMB port brake interrupt + PWMSmBrkIrq = 1u, ///< EMB PWM same brake interrupt + CMPBrkIrq = 2u, ///< EMB CMP brake interrupt + OSCFailBrkIrq = 3u, ///< EMB oscillator fail brake interrupt +} en_emb_irq_type_t; + +/** + ******************************************************************************* + ** \brief EMB port in filter enumeration + ******************************************************************************/ +typedef enum en_emb_port_filter +{ + EMBPortFltDiv0 = 0u, ///< EMB port in filter with PCLK clock + EMBPortFltDiv8 = 1u, ///< EMB port in filter with PCLK/8 clock + EMBPortFltDiv32 = 2u, ///< EMB port in filter with PCLK/32 clock + EMBPortFltDiv128 = 3u, ///< EMB port in filter with PCLK/128 clock +} en_emb_port_filter_t; + +/** + ******************************************************************************* + ** \brief EMB CR0 for timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer6 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OSC fail brake + bool bEnTimer61PWMSBrake; ///< Enable tiemr61 PWM same brake + bool bEnTimer62PWMSBrake; ///< Enable tiemr62 PWM same brake + bool bEnTimer63PWMSBrake; ///< Enable tiemr63 PWM same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB CR1~3 for timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer4 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OS fail brake + bool bEnTimer4xWHLSammeBrake; ///< Enable tiemr4x PWM WH WL same brake + bool bEnTimer4xVHLSammeBrake; ///< Enable tiemr4x PWM VH VL same brake + bool bEnTimer4xUHLSammeBrake; ///< Enable tiemr4x PWM UH UL same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer4_t; + + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer6 +{ + bool bEnTimer61HighLevelDect; ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer62HighLevelDect; ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer63HighLevelDect; ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer4 +{ + bool bEnUHLPhaseHighLevelDect; ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel + bool bEnVHLPhaseHighLevelDect; ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel + bool bEnWHLphaseHighLevelDect; ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer4_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn); +/* Get status(flag) */ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus); +/* Status(flag) clear (recover) */ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr); +/* Control Register(CTL) config for timer6 */ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR); +/* Control Register(CTL) config for timer4 */ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR); +/* PWM level detect (short detection) selection config for timer6 */ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv); +/* PWM level detect (short detection) selection config for timer4 */ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv); +/* Software brake */ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn); + +//@} // EMBGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EMB_ENABLE */ + +#endif /* __HC32F460_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h new file mode 100644 index 000000000..88338297a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h @@ -0,0 +1,176 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.h + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EVENT_PORT_H__ +#define __HC32F460_EVENT_PORT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EventPortGroup Event Port (EventPort) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port Index enumeration + ** + ******************************************************************************/ +typedef enum en_event_port +{ + EventPort1 = 0, ///< Event port 1 + EventPort2 = 1, ///< Event port 2 + EventPort3 = 2, ///< Event port 3 + EventPort4 = 3, ///< Event port 4 +}en_event_port_t; + +/** + ******************************************************************************* + ** \brief Event Port Pin enumeration + ** + ******************************************************************************/ +typedef enum en_event_pin +{ + EventPin00 = 1u << 0, ///< Event port Pin 00 + EventPin01 = 1u << 1, ///< Event port Pin 01 + EventPin02 = 1u << 2, ///< Event port Pin 02 + EventPin03 = 1u << 3, ///< Event port Pin 03 + EventPin04 = 1u << 4, ///< Event port Pin 04 + EventPin05 = 1u << 5, ///< Event port Pin 05 + EventPin06 = 1u << 6, ///< Event port Pin 06 + EventPin07 = 1u << 7, ///< Event port Pin 07 + EventPin08 = 1u << 8, ///< Event port Pin 08 + EventPin09 = 1u << 9, ///< Event port Pin 09 + EventPin10 = 1u << 10, ///< Event port Pin 10 + EventPin11 = 1u << 11, ///< Event port Pin 11 + EventPin12 = 1u << 12, ///< Event port Pin 12 + EventPin13 = 1u << 13, ///< Event port Pin 13 + EventPin14 = 1u << 14, ///< Event port Pin 14 + EventPin15 = 1u << 15, ///< Event port Pin 15 + EventPinAll= 0xFFFF, ///< All event pins are selected +}en_event_pin_t; + +/** + ******************************************************************************* + ** \brief Event Port common trigger source select + ** + ******************************************************************************/ +typedef enum en_event_port_com_trigger +{ + EpComTrigger_1 = 0x1, ///< Select common trigger 1. + EpComTrigger_2 = 0x2, ///< Select common trigger 2. + EpComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_event_port_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Event Port direction enumeration + ** + ******************************************************************************/ +typedef enum en_event_port_dir +{ + EventPortIn = 0, ///< Event Port direction 'IN' + EventPortOut = 1, ///< Event Port direction 'OUT' +}en_event_port_dir_t; + +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for Event port detect + ** + ** \note + ******************************************************************************/ +typedef enum en_ep_flt_clk +{ + Pclk1Div1 = 0u, ///< PCLK1 as EP filter clock source + Pclk1Div8 = 1u, ///< PCLK1 div8 as EP filter clock source + Pclk1Div32 = 2u, ///< PCLK1 div32 as EP filter clock source + Pclk1Div64 = 3u, ///< PCLK1 div64 as EP filter clock source +}en_ep_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Event port init structure definition + ******************************************************************************/ +typedef struct stc_event_port_init +{ + en_event_port_dir_t enDirection; ///< Input/Output setting + en_functional_state_t enReset; ///< Corresponding pin reset after triggered + en_functional_state_t enSet; ///< Corresponding pin set after triggered + en_functional_state_t enRisingDetect; ///< Rising edge detect enable + en_functional_state_t enFallingDetect;///< Falling edge detect enable + en_functional_state_t enFilter; ///< Filter clock source select + en_ep_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_ep_flt_clk_t for details +}stc_event_port_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort, \ + uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit); +extern en_result_t EVENTPORT_DeInit(void); +extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc); +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState); +extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort); +extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, \ + en_event_pin_t enEventPin); +extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); +extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); + +//@} // EventPortGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EVENT_PORT_ENABLE */ + +#endif /* __HC32F460_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h new file mode 100644 index 000000000..eeb69fc7f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h @@ -0,0 +1,257 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.h + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EXINT_NMI_SWI_H__ +#define __HC32F460_EXINT_NMI_SWI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup ExintNmiSwiGroup External Interrupts (External Interrupt), \ + ** NMI (Non-Maskable Interrupt), SWI (Software Interrupt) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for EXINT and NMI + ** + ** \note + ******************************************************************************/ +typedef enum en_ei_flt_clk +{ + Pclk3Div1 = 0u, ///< PCLK3 as EP filter clock source + Pclk3Div8 = 1u, ///< PCLK3 div8 as EP filter clock source + Pclk3Div32 = 2u, ///< PCLK3 div32 as EP filter clock source + Pclk3Div64 = 3u, ///< PCLK3 div64 as EP filter clock source +}en_ei_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_lvl +{ + NmiFallingEdge = 0u, ///< Falling edge detection + NmiRisingEdge = 1u, ///< Rising edge detection +}en_nmi_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to EXTI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_exti_lvl +{ + ExIntFallingEdge = 0u, ///< Falling edge detection + ExIntRisingEdge = 1u, ///< Rising edge detection + ExIntBothEdge = 2u, ///< Falling or Rising edge detection + ExIntLowLevel = 3u, ///< "L" level detection +}en_exti_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define an index for EXINT + ******************************************************************************/ +typedef enum en_exti_ch +{ + ExtiCh00 = 0u, + ExtiCh01 = 1u, + ExtiCh02 = 2u, + ExtiCh03 = 3u, + ExtiCh04 = 4u, + ExtiCh05 = 5u, + ExtiCh06 = 6u, + ExtiCh07 = 7u, + ExtiCh08 = 8u, + ExtiCh09 = 9u, + ExtiCh10 = 10u, + ExtiCh11 = 11u, + ExtiCh12 = 12u, + ExtiCh13 = 13u, + ExtiCh14 = 14u, + ExtiCh15 = 15u, +}en_exti_ch_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define the SWI channel + ******************************************************************************/ +typedef enum en_swi_ch +{ + SwiCh00 = 1u << 0, + SwiCh01 = 1u << 1, + SwiCh02 = 1u << 2, + SwiCh03 = 1u << 3, + SwiCh04 = 1u << 4, + SwiCh05 = 1u << 5, + SwiCh06 = 1u << 6, + SwiCh07 = 1u << 7, + SwiCh08 = 1u << 8, + SwiCh09 = 1u << 9, + SwiCh10 = 1u << 10, + SwiCh11 = 1u << 11, + SwiCh12 = 1u << 12, + SwiCh13 = 1u << 13, + SwiCh14 = 1u << 14, + SwiCh15 = 1u << 15, + SwiCh16 = 1u << 16, + SwiCh17 = 1u << 17, + SwiCh18 = 1u << 18, + SwiCh19 = 1u << 19, + SwiCh20 = 1u << 20, + SwiCh21 = 1u << 21, + SwiCh22 = 1u << 22, + SwiCh23 = 1u << 23, + SwiCh24 = 1u << 24, + SwiCh25 = 1u << 25, + SwiCh26 = 1u << 26, + SwiCh27 = 1u << 27, + SwiCh28 = 1u << 28, + SwiCh29 = 1u << 29, + SwiCh30 = 1u << 30, + SwiCh31 = 1u << 31, +}en_swi_ch_t; + +/** + ******************************************************************************* + ** \brief External Interrupt configuration + ** + ** \note The EXINT configuration + ******************************************************************************/ +typedef struct stc_exint_config +{ + en_exti_ch_t enExitCh; ///< External Int CH.0~15 ref@ en_exti_ch_t + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFltClk; ///< Filter clock, ref@ en_ei_flt_clk_t for details + en_exti_lvl_t enExtiLvl; ///< Detection level, ref@ en_exti_lvl_t for details +}stc_exint_config_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI Trigger source + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_src +{ + NmiSrcNmi = 1u << 0, ///< NMI pin + NmiSrcSwdt = 1u << 1, ///< Special watch dog timer + NmiSrcVdu1 = 1u << 2, ///< Voltage detect 1 + NmiSrcVdu2 = 1u << 3, ///< Voltage detect 2 + NmiSrcXtalStop = 1u << 5, ///< Xtal stop + NmiSrcSramPE = 1u << 8, ///< SRAM1/2/HS/Ret parity error + NmiSrcSramDE = 1u << 9, ///< SRAM3 ECC error + NmiSrcMpu = 1u << 10, ///< MPU error + NmiSrcWdt = 1u << 11, ///< Watch dog timer +}en_nmi_src_t; + +/** + ******************************************************************************* + ** \brief Enumeration to software interrupt or event + ** + ** \note + ******************************************************************************/ +typedef enum en_swi_type +{ + SwEvent = 0u, ///< software event + SwInt = 1u, ///< software interrupt +}en_swi_type_t; + + +/** + ******************************************************************************* + ** \brief NMI configuration + ** + ** \note The NMI configuration + ******************************************************************************/ +typedef struct stc_nmi_config +{ + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_flt_clk_t for details + en_nmi_lvl_t enNmiLvl; ///< Detection level, ref@ en_nmi_lvl_t for details + uint16_t u16NmiSrc; ///< NMI trigger source, ref@ en_nmi_src_t for details + func_ptr_t pfnNmiCallback; ///< Callback pointers +}stc_nmi_config_t; + +/** + ******************************************************************************* + ** \brief SWI configuration + ** + ** \note The SWI configuration + ******************************************************************************/ +typedef struct stc_swi_config +{ + en_swi_ch_t enSwiCh; ///< SWI channel + en_swi_type_t enSwiType; ///< Select software interrupt or event + func_ptr_t pfnSwiCallback; ///< Callback pointers +}stc_swi_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig); +extern en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint); +extern en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint); +extern en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig); +extern en_result_t NMI_DeInit(void); +extern en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc); +extern en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc); +extern en_result_t SWI_Enable(uint32_t u32SwiCh); +extern en_result_t SWI_Disable(uint32_t u32SwiCh); + +//@} // ExintNmiSwiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +#endif /* __HC32F460_EXINT_NMI_SWI_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h new file mode 100644 index 000000000..b553de116 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h @@ -0,0 +1,294 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.h + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +#ifndef __HC32F460_GPIO_H__ +#define __HC32F460_GPIO_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup GpioGroup General Purpose Input/Output(GPIO) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief GPIO Configuration Mode enumeration + ** + ******************************************************************************/ +typedef enum en_pin_mode +{ + Pin_Mode_In = 0, ///< GPIO Input mode + Pin_Mode_Out = 1, ///< GPIO Output mode + Pin_Mode_Ana = 2, ///< GPIO Analog mode +}en_pin_mode_t; + +/** + ******************************************************************************* + ** \brief GPIO Drive Capacity enumeration + ** + ******************************************************************************/ +typedef enum en_pin_drv +{ + Pin_Drv_L = 0, ///< Low Drive Capacity + Pin_Drv_M = 1, ///< Middle Drive Capacity + Pin_Drv_H = 2, ///< High Drive Capacity +}en_pin_drv_t; + +/** + ******************************************************************************* + ** \brief GPIO Output Type enumeration + ******************************************************************************/ +typedef enum en_pin_o_type +{ + Pin_OType_Cmos = 0, ///< CMOS + Pin_OType_Od = 1, ///< Open Drain +}en_pin_o_type_t; + + +typedef enum en_debug_port +{ + TCK_SWCLK = 1 << 0, ///< TCK or SWCLK + TMS_SWDIO = 1 << 1, ///< TMS or SWDIO + TDO_SWO = 1 << 2, ///< TOD or SWD + TDI = 1 << 3, ///< TDI + TRST = 1 << 4, ///< TRest + ALL_DBG_PIN = 0x1Fu ///< All above +}en_debug_port_t; +/** + ******************************************************************************* + ** \brief GPIO Port Index enumeration + ******************************************************************************/ +typedef enum en_port +{ + PortA = 0, ///< port group A + PortB = 1, ///< port group B + PortC = 2, ///< port group C + PortD = 3, ///< port group D + PortE = 4, ///< port group E + PortH = 5, ///< port group H +}en_port_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin Index enumeration + ******************************************************************************/ +typedef enum en_pin +{ + Pin00 = (1 << 0), ///< Pin index 00 of each port group + Pin01 = (1 << 1), ///< Pin index 01 of each port group + Pin02 = (1 << 2), ///< Pin index 02 of each port group + Pin03 = (1 << 3), ///< Pin index 03 of each port group + Pin04 = (1 << 4), ///< Pin index 04 of each port group + Pin05 = (1 << 5), ///< Pin index 05 of each port group + Pin06 = (1 << 6), ///< Pin index 06 of each port group + Pin07 = (1 << 7), ///< Pin index 07 of each port group + Pin08 = (1 << 8), ///< Pin index 08 of each port group + Pin09 = (1 << 9), ///< Pin index 09 of each port group + Pin10 = (1 << 10), ///< Pin index 10 of each port group + Pin11 = (1 << 11), ///< Pin index 11 of each port group + Pin12 = (1 << 12), ///< Pin index 12 of each port group + Pin13 = (1 << 13), ///< Pin index 13 of each port group + Pin14 = (1 << 14), ///< Pin index 14 of each port group + Pin15 = (1 << 15), ///< Pin index 15 of each port group + PinAll= 0xFFFF, ///< All pins selected +}en_pin_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin read wait cycle enumeration + ******************************************************************************/ +typedef enum en_read_wait +{ + WaitCycle0 = 0, ///< no wait cycle, operation freq. lower than 42MHz + WaitCycle1 = 1, ///< one wait cycle, operation freq. @[42~84)MHz + WaitCycle2 = 2, ///< two wait cycles, operation freq. @[84~126)MHz + WaitCycle3 = 3, ///< three wait cycles, operation freq. @[126~200)MHz +}en_read_wait_t; + +/** + ******************************************************************************* + ** \brief GPIO Function enumeration + ******************************************************************************/ +typedef enum en_port_func +{ + Func_Gpio = 0u, ///< function set to gpio + Func_Fcmref = 1u, ///< function set to fcm reference + Func_Rtcout = 1u, ///< function set to rtc output + Func_Vcout = 1u, ///< function set to vc output + Func_Adtrg = 1u, ///< function set to adc trigger + Func_Mclkout = 1u, ///< function set to mclk output + Func_Tim4 = 2u, ///< function set to timer4 + Func_Tim6 = 3u, ///< function set to timer6 + Func_Tima0 = 4u, ///< function set to timerA + Func_Tima1 = 5u, ///< function set to timerA + Func_Tima2 = 6u, ///< function set to timerA + Func_Emb = 6u, ///< function set to emb + Func_Usart_Ck = 7u, ///< function set to usart clk + Func_Spi_Nss = 7u, ///< function set to spi nss + Func_Qspi = 7u, ///< function set to qspi + Func_Key = 8u, ///< function set to key + Func_Sdio = 9u, ///< function set to sdio + Func_I2s = 10u, ///< function set to i2s + Func_UsbF = 10u, ///< function set to usb full speed + Func_Evnpt = 14u, ///< function set to event port + Func_Eventout = 15u, ///< function set to event out + Func_Usart1_Tx = 32u, ///< function set to usart tx of ch.1 + Func_Usart3_Tx = 32u, ///< function set to usart tx of ch.3 + Func_Usart1_Rx = 33u, ///< function set to usart rx of ch.1 + Func_Usart3_Rx = 33u, ///< function set to usart rx of ch.3 + Func_Usart1_Rts = 34u, ///< function set to usart rts of ch.1 + Func_Usart3_Rts = 34u, ///< function set to usart rts of ch.3 + Func_Usart1_Cts = 35u, ///< function set to usart cts of ch.1 + Func_Usart3_Cts = 35u, ///< function set to usart cts of ch.3 + Func_Usart2_Tx = 36u, ///< function set to usart tx of ch.2 + Func_Usart4_Tx = 36u, ///< function set to usart tx of ch.4 + Func_Usart2_Rx = 37u, ///< function set to usart rx of ch.2 + Func_Usart4_Rx = 37u, ///< function set to usart rx of ch.4 + Func_Usart2_Rts = 38u, ///< function set to usart rts of ch.2 + Func_Usart4_Rts = 38u, ///< function set to usart rts of ch.4 + Func_Usart2_Cts = 39u, ///< function set to usart cts of ch.2 + Func_Usart4_Cts = 39u, ///< function set to usart cts of ch.4 + Func_Spi1_Mosi = 40u, ///< function set to spi mosi of ch.1 + Func_Spi3_Mosi = 40u, ///< function set to spi mosi of ch.3 + Func_Spi1_Miso = 41u, ///< function set to spi miso of ch.1 + Func_Spi3_Miso = 41u, ///< function set to spi miso of ch.3 + Func_Spi1_Nss0 = 42u, ///< function set to spi nss0 of ch.1 + Func_Spi3_Nss0 = 42u, ///< function set to spi nss0 of ch.3 + Func_Spi1_Sck = 43u, ///< function set to spi sck of ch.1 + Func_Spi3_Sck = 43u, ///< function set to spi sck of ch.3 + Func_Spi2_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi4_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi2_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi4_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi2_Nss0 = 46u, ///< function set to spi nss0 of ch.2 + Func_Spi4_Nss0 = 46u, ///< function set to spi nss0 of ch.4 + Func_Spi2_Sck = 47u, ///< function set to spi sck of ch.2 + Func_Spi4_Sck = 47u, ///< function set to spi sck of ch.4 + Func_I2c1_Sda = 48u, ///< function set to i2c sda of ch.1 + Func_I2c3_Sda = 48u, ///< function set to i2c sda of ch.3 + Func_I2c1_Scl = 49u, ///< function set to i2c scl of ch.1 + Func_I2c3_Scl = 49u, ///< function set to i2c scl of ch.3 + Func_I2c2_Sda = 50u, ///< function set to i2c sda of ch.2 + Func_Can1_Tx = 50u, ///< function set to can tx of ch.1 + Func_I2c2_Scl = 51u, ///< function set to i2c scl of ch.2 + Func_Can1_Rx = 51u, ///< function set to can rx of ch.1 + Func_I2s1_Sd = 52u, ///< function set to i2s sd of ch.1 + Func_I2s3_Sd = 52u, ///< function set to i2s sd of ch.3 + Func_I2s1_Sdin = 53u, ///< function set to i2s sdin of ch.1 + Func_I2s3_Sdin = 53u, ///< function set to i2s sdin of ch.3 + Func_I2s1_Ws = 54u, ///< function set to i2s ws of ch.1 + Func_I2s3_Ws = 54u, ///< function set to i2s ws of ch.3 + Func_I2s1_Ck = 55u, ///< function set to i2s ck of ch.1 + Func_I2s3_Ck = 55u, ///< function set to i2s ck of ch.3 + Func_I2s2_Sd = 56u, ///< function set to i2s sd of ch.2 + Func_I2s4_Sd = 56u, ///< function set to i2s sd of ch.4 + Func_I2s2_Sdin = 57u, ///< function set to i2s sdin of ch.2 + Func_I2s4_Sdin = 57u, ///< function set to i2s sdin of ch.4 + Func_I2s2_Ws = 58u, ///< function set to i2s ws of ch.2 + Func_I2s4_Ws = 58u, ///< function set to i2s ws of ch.4 + Func_I2s2_Ck = 59u, ///< function set to i2s ck of ch.2 + Func_I2s4_Ck = 59u, ///< function set to i2s ck of ch.4 +}en_port_func_t; + +/** + ******************************************************************************* + ** \brief GPIO init structure definition + ******************************************************************************/ +typedef struct stc_port_init +{ + en_pin_mode_t enPinMode; ///< Set pin mode @ref en_pin_mode_t + en_functional_state_t enLatch; ///< Pin output latch enable + en_functional_state_t enExInt; ///< External int enable + en_functional_state_t enInvert; ///< Pin input/output invert enable + en_functional_state_t enPullUp; ///< Internal pull-up resistor enable + en_pin_drv_t enPinDrv; ///< Drive capacity setting @ref en_pin_drv_t + en_pin_o_type_t enPinOType; ///< Output mode setting @ref en_pin_o_type_t + en_functional_state_t enPinSubFunc; ///< Pin sub-function enable +}stc_port_init_t; + +/** + ******************************************************************************* + ** \brief GPIO public setting structure definition + ******************************************************************************/ +typedef struct stc_port_pub_set +{ + en_port_func_t enSubFuncSel; ///< Sub-function setting @ref en_port_func_t + en_read_wait_t enReadWait; ///< Read wait cycle setting @ref en_read_wait_t +}stc_port_pub_set_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, \ + const stc_port_init_t *pstcPortInit); +extern en_result_t PORT_DeInit(void); +extern void PORT_Unlock(void); +extern void PORT_Lock(void); +extern en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc); +extern en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet); +extern uint16_t PORT_GetData(en_port_t enPort); +extern en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin); +extern en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState); +extern en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, \ + en_port_func_t enFuncSel, en_functional_state_t enSubFunc); +extern en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel); + +//@} // GpioGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_GPIO_ENABLE */ + +#endif /* __HC32F460_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h new file mode 100644 index 000000000..8ee1ce44d --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.h + ** + ** A detailed description is available at + ** @link HashGroup Hash description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of Hash. + ** + ******************************************************************************/ +#ifndef __HC32F460_HASH_H__ +#define __HC32F460_HASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_HASH_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup HashGroup Hash(HASH) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void HASH_Init(void); +void HASH_DeInit(void); +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout); + +//@} // HashGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_HASH_ENABLE */ + +#endif /* __HC32F460_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h new file mode 100644 index 000000000..dc8ea44b5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h @@ -0,0 +1,270 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.h + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2C_H__ +#define __HC32F460_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_I2C_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2cGroup Inter-Integrated Circuit (I2C) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2c configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_init +{ + uint32_t u32ClockDiv; ///< I2C clock division for i2c source clock + uint32_t u32Baudrate; ///< I2C baudrate config + uint32_t u32SclTime; ///< The SCL rising and falling time, count of T(i2c source clock after frequency divider) +}stc_i2c_init_t; + +/** + ******************************************************************************* + ** \brief I2c SMBUS configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_smbus_init +{ + en_functional_state_t enHostAdrMatchFunc; ///< SMBUS host address matching function + en_functional_state_t enDefaultAdrMatchFunc; ///< SMBUS default address matching function + en_functional_state_t enAlarmAdrMatchFunc; ///< SMBUS Alarm address matching function +}stc_i2c_smbus_init_t; + +/** + ******************************************************************************* + ** \brief I2c digital filter mode enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_digital_filter_mode +{ + Filter1BaseCycle = 0u, ///< I2C digital filter ability 1 base cycle + Filter2BaseCycle = 1u, ///< I2C digital filter ability 2 base cycle + Filter3BaseCycle = 2u, ///< I2C digital filter ability 3 base cycle + Filter4BaseCycle = 3u, ///< I2C digital filter ability 4 base cycle +}en_i2c_digital_filter_mode_t; + +/** + ******************************************************************************* + ** \brief I2c address bit enumeration + ** + ******************************************************************************/ +typedef enum en_address_bit +{ + Adr7bit = 0u, ///< I2C address length is 7 bits + Adr10bit = 1u, ///< I2C address length is 10 bits +}en_address_bit_t; + +/** + ******************************************************************************* + ** \brief I2c transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_trans_direction +{ + I2CDirTrans = 0u, + I2CDirReceive = 1u, +}en_trans_direction_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout switch enumeration + ** + ******************************************************************************/ +typedef enum en_clock_timeout_switch +{ + TimeoutFunOff = 0u, ///< I2C SCL pin time out function off + LowTimerOutOn = 3u, ///< I2C SCL pin high level time out function on + HighTimeOutOn = 5u, ///< I2C SCL pin low level time out function on + BothTimeOutOn = 7u, ///< I2C SCL pin both(low and high) level time out function on +}en_clock_timeout_switch_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout initialize structure + ** + ******************************************************************************/ +typedef struct stc_clock_timeout_init +{ + en_clock_timeout_switch_t enClkTimeOutSwitch; ///< I2C clock timeout function switch + uint16_t u16TimeOutHigh; ///< I2C clock timeout period for High level + uint16_t u16TimeOutLow; ///< I2C clock timeout period for Low level +}stc_clock_timeout_init_t; + +/** + ******************************************************************************* + ** \brief I2c ACK config enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_ack_config +{ + I2c_ACK = 0u, + I2c_NACK = 1u, +}en_i2c_ack_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define interrupt enable bit for I2C_CR2 register */ +#define I2C_CR2_STARTIE (0x00000001ul) +#define I2C_CR2_SLADDR0EN (0x00000002ul) +#define I2C_CR2_SLADDR1EN (0x00000004ul) +#define I2C_CR2_TENDIE (0x00000008ul) +#define I2C_CR2_STOPIE (0x00000010ul) +#define I2C_CR2_RFULLIE (0x00000040ul) +#define I2C_CR2_TEMPTYIE (0x00000080ul) +#define I2C_CR2_ARLOIE (0x00000200ul) +#define I2C_CR2_NACKIE (0x00001000ul) +#define I2C_CR2_TMOURIE (0x00004000ul) +#define I2C_CR2_GENCALLIE (0x00100000ul) +#define I2C_CR2_SMBDEFAULTIE (0x00200000ul) +#define I2C_CR2_SMBHOSTIE (0x00400000ul) +#define I2C_CR2_SMBALRTIE (0x00800000ul) + +/* define status bit for I2C_SR register */ +#define I2C_SR_STARTF (0x00000001ul) +#define I2C_SR_SLADDR0F (0x00000002ul) +#define I2C_SR_SLADDR1F (0x00000004ul) +#define I2C_SR_TENDF (0x00000008ul) +#define I2C_SR_STOPF (0x00000010ul) +#define I2C_SR_RFULLF (0x00000040ul) +#define I2C_SR_TEMPTYF (0x00000080ul) +#define I2C_SR_ARLOF (0x00000200ul) +#define I2C_SR_ACKRF (0x00000400ul) +#define I2C_SR_NACKF (0x00001000ul) +#define I2C_SR_TMOUTF (0x00004000ul) +#define I2C_SR_MSL (0x00010000ul) +#define I2C_SR_BUSY (0x00020000ul) +#define I2C_SR_TRA (0x00040000ul) +#define I2C_SR_GENCALLF (0x00100000ul) +#define I2C_SR_SMBDEFAULTF (0x00200000ul) +#define I2C_SR_SMBHOSTF (0x00400000ul) +#define I2C_SR_SMBALRTF (0x00800000ul) + +/* define status clear bit for I2C_CLR register*/ +#define I2C_CLR_STARTFCLR (0x00000001ul) +#define I2C_CLR_SLADDR0FCLR (0x00000002ul) +#define I2C_CLR_SLADDR1FCLR (0x00000004ul) +#define I2C_CLR_TENDFCLR (0x00000008ul) +#define I2C_CLR_STOPFCLR (0x00000010ul) +#define I2C_CLR_RFULLFCLR (0x00000040ul) +#define I2C_CLR_TEMPTYFCLR (0x00000080ul) +#define I2C_CLR_ARLOFCLR (0x00000200ul) +#define I2C_CLR_NACKFCLR (0x00001000ul) +#define I2C_CLR_TMOUTFCLR (0x00004000ul) +#define I2C_CLR_GENCALLFCLR (0x00100000ul) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000ul) +#define I2C_CLR_SMBHOSTFCLR (0x00400000ul) +#define I2C_CLR_SMBALRTFCLR (0x00800000ul) +#define I2C_CLR_MASK (0x00F056DFul) + +/* I2C_Clock_Division I2C clock division */ +#define I2C_CLK_DIV1 (0ul) /* I2c source clock/1 */ +#define I2C_CLK_DIV2 (1ul) /* I2c source clock/2 */ +#define I2C_CLK_DIV4 (2ul) /* I2c source clock/4 */ +#define I2C_CLK_DIV8 (3ul) /* I2c source clock/8 */ +#define I2C_CLK_DIV16 (4ul) /* I2c source clock/16 */ +#define I2C_CLK_DIV32 (5ul) /* I2c source clock/32 */ +#define I2C_CLK_DIV64 (6ul) /* I2c source clock/64 */ +#define I2C_CLK_DIV128 (7ul) /* I2c source clock/128 */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx); +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct); +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +//////////////////////////////////////////////////////////////////////////////////////// +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode); +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit); +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState); +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +/////////////////////////////////////////////////////////////////////////////////////// +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx); +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig); +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); + +/* High level functions for reference ********************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); + +//@} // I2cGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_I2C_ENABLE */ + +#endif /* __HC32F460_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h new file mode 100644 index 000000000..210cf667e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h @@ -0,0 +1,206 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.h + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2S_H__ +#define __HC32F460_I2S_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_I2S_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2sGroup Inter-IC Sound(I2S) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2S function + ******************************************************************************/ +typedef enum en_i2s_func +{ + TxEn = 0u, ///< Transfer enable function + TxIntEn = 1u, ///< Transfer interrupt enable function + RxEn = 2u, ///< receive enable function + RxIntEn = 3u, ///< receive interrupt enable function + ErrIntEn = 4u, ///< error interrupt enable function +}en_i2s_func_t; + + +/** + ******************************************************************************* + ** \brief I2S status flag + ******************************************************************************/ +typedef enum en_i2s_std +{ + TxBufAlarmFlag = 0u, + RxBufAlarmFlag = 1u, + TxBufEmptFlag = 2u, + TxBufFullFlag = 3u, + RxBufEmptFlag = 4u, + RxBufFullFlag = 5u, +}en_i2s_std_t; + +/** + ******************************************************************************* + ** \brief I2S clr flag + ******************************************************************************/ +typedef enum en_i2s_err_flag +{ + ClrTxErrFlag = 0u, + ClrRxErrFlag = 1u, +}en_i2s_err_flag_t; +/** + ******************************************************************************* + ** \brief I2S mode + ******************************************************************************/ +typedef enum en_i2s_mode +{ + I2sMaster = 0u, ///< I2S Master mode + I2sSlave = 1u, ///< I2S Slave mode +}en_i2s_mode_t; + +/** + ******************************************************************************* + ** \brief I2S full duplex mode + ******************************************************************************/ +typedef enum en_i2s_full_duplex_mode +{ + I2s_HalfDuplex = 0u, ///< I2S half duplex + I2s_FullDuplex = 1u, ///< I2S full duplex +}en_i2s_full_duplex_mode_t; + +/** + ******************************************************************************* + ** \brief I2S standard + ******************************************************************************/ +typedef enum en_i2s_standard +{ + Std_Philips = 0u, ///< I2S Philips standard + Std_MSBJust = 1u, ///< I2S MSB justified standart + Std_LSBJust = 2u, ///< I2S LSB justified standart + Std_PCM = 3u, ///< I2S PCM standart +}en_i2s_standard_t; + +/** + ******************************************************************************* + ** \brief I2S channel data length + ******************************************************************************/ +typedef enum en_i2s_ch_len +{ + I2s_ChLen_16Bit = 0u, + I2s_ChLen_32Bit = 1u, +}en_i2s_ch_len_t; + +/** + ******************************************************************************* + ** \brief I2S data length + ******************************************************************************/ +typedef enum en_i2s_data_len +{ + I2s_DataLen_16Bit = 0u, + I2s_DataLen_24Bit = 1u, + I2s_DataLen_32Bit = 2u, +}en_i2s_data_len_t; + +/** + ******************************************************************************* + ** \brief I2S configuration structure + ******************************************************************************/ +typedef struct stc_i2s_config +{ + en_i2s_mode_t enMode; ///< I2S mode + en_i2s_full_duplex_mode_t enFullDuplexMode; ///< I2S full duplex mode + uint32_t u32I2sInterClkFreq; ///< I2S internal clock frequency + en_i2s_standard_t enStandrad; ///< I2S standard + en_i2s_data_len_t enDataBits; ///< I2S data format, data bits + en_i2s_ch_len_t enChanelLen; ///< I2S channel length + en_functional_state_t enMcoOutEn; ///< I2S MCK output config + en_functional_state_t enExckEn; ///< I2S EXCK function config + uint32_t u32AudioFreq; ///< I2S audio frequecy +}stc_i2s_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define audio frequency */ +#define I2S_AudioFreq_192k (192000ul) +#define I2S_AudioFreq_96k (96000ul) +#define I2S_AudioFreq_48k (48000ul) +#define I2S_AudioFreq_44k (44100ul) +#define I2S_AudioFreq_32k (32000ul) +#define I2S_AudioFreq_22k (22050ul) +#define I2S_AudioFreq_16k (16000ul) +#define I2S_AudioFreq_11k (11025ul) +#define I2S_AudioFreq_8k (8000ul) +#define I2S_AudioFreq_Default (2ul) + +/* if use external clock open this define */ +#define I2S_EXTERNAL_CLOCK_VAL (12288000ul) + +/* 0,1 or 2 config for tx or tx buffer interrupt warning level */ +#define RXBUF_IRQ_WL (1ul) +#define TXBUF_IRQ_WL (1ul) + +/* 0: Short frame synchronization; 1: Long frame synchronization */ +#define PCM_SYNC_FRAME (0ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg); +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data); +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg); +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd); +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg); + +//@} // I2sGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_I2S_ENABLE */ + +#endif /* __HC32F460_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h new file mode 100644 index 000000000..d0c4c1663 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h @@ -0,0 +1,400 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.h + ** + ** A detailed description is available at + ** @link IcgGroup Initialize configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ +#ifndef __HC32F460_ICG_H__ +#define __HC32F460_ICG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_ICG_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup IcgGroup Initialize Configure(ICG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT running state after reset + ******************************************************************************/ +#define SWDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< SWDT Auto Start after reset +#define SWDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< SWDT stop after reset + +/** + ******************************************************************************* + ** \brief SWDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define SWDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define SWDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief SWDT count underflow cycle + ******************************************************************************/ +#define SWDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief SWDT count clock division + ******************************************************************************/ +#define SWDT_COUNT_SWDTCLK_DIV1 ((uint16_t)0x0000) ///< SWDTCLK +#define SWDT_COUNT_SWDTCLK_DIV16 ((uint16_t)0x0040) ///< SWDTCLK/16 +#define SWDT_COUNT_SWDTCLK_DIV32 ((uint16_t)0x0050) ///< SWDTCLK/32 +#define SWDT_COUNT_SWDTCLK_DIV64 ((uint16_t)0x0060) ///< SWDTCLK/64 +#define SWDT_COUNT_SWDTCLK_DIV128 ((uint16_t)0x0070) ///< SWDTCLK/128 +#define SWDT_COUNT_SWDTCLK_DIV256 ((uint16_t)0x0080) ///< SWDTCLK/256 +#define SWDT_COUNT_SWDTCLK_DIV2048 ((uint16_t)0x00B0) ///< SWDTCLK/2048 + +/** + ******************************************************************************* + ** \brief SWDT allow refresh percent range + ******************************************************************************/ +#define SWDT_100PCT ((uint16_t)0x0000) ///< 100% +#define SWDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define SWDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define SWDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define SWDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define SWDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define SWDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define SWDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define SWDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define SWDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define SWDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define SWDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define SWDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define SWDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define SWDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define SWDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief SWDT count control in the sleep/stop mode + ******************************************************************************/ +#define SWDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< SWDT count continue in the sleep/stop mode +#define SWDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< SWDT count stop in the sleep/stop mode + +/** + ******************************************************************************* + ** \brief WDT running state after reset + ******************************************************************************/ +#define WDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< WDT Auto Start after reset +#define WDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< WDT stop after reset + +/** + ******************************************************************************* + ** \brief WDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define WDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define WDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief WDT count underflow cycle + ******************************************************************************/ +#define WDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief WDT count clock division + ******************************************************************************/ +#define WDT_COUNT_PCLK3_DIV4 ((uint16_t)0x0020) ///< PCLK3/4 +#define WDT_COUNT_PCLK3_DIV64 ((uint16_t)0x0060) ///< PCLK3/64 +#define WDT_COUNT_PCLK3_DIV128 ((uint16_t)0x0070) ///< PCLK3/128 +#define WDT_COUNT_PCLK3_DIV256 ((uint16_t)0x0080) ///< PCLK3/256 +#define WDT_COUNT_PCLK3_DIV512 ((uint16_t)0x0090) ///< PCLK3/512 +#define WDT_COUNT_PCLK3_DIV1024 ((uint16_t)0x00A0) ///< PCLK3/1024 +#define WDT_COUNT_PCLK3_DIV2048 ((uint16_t)0x00B0) ///< PCLK3/2048 +#define WDT_COUNT_PCLK3_DIV8192 ((uint16_t)0x00D0) ///< PCLK3/8192 + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range + ******************************************************************************/ +#define WDT_100PCT ((uint16_t)0x0000) ///< 100% +#define WDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define WDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define WDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define WDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define WDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define WDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define WDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define WDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define WDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define WDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define WDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define WDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define WDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define WDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define WDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief WDT count control in the sleep mode + ******************************************************************************/ +#define WDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< WDT count continue in the sleep mode +#define WDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< WDT count stop in the sleep mode + +/** + ******************************************************************************* + ** \brief HRC frequency select + ******************************************************************************/ +#define HRC_FREQUENCY_20MHZ ((uint16_t)0x0000) ///< HRC frequency 20MHZ +#define HRC_FREQUENCY_16MHZ ((uint16_t)0x0001) ///< HRC frequency 16MHZ + +/** + ******************************************************************************* + ** \brief HRC oscillation state control + ******************************************************************************/ +#define HRC_OSCILLATION_START ((uint16_t)0x0000) ///< HRC oscillation start +#define HRC_OSCILLATION_STOP ((uint16_t)0x0100) ///< HRC oscillation stop + +/** + ******************************************************************************* + ** \brief VDU0 threshold voltage select + ******************************************************************************/ +#define VDU0_VOLTAGE_THRESHOLD_1P5 ((uint8_t)0x00) ///< VDU0 voltage threshold 1.9V +#define VDU0_VOLTAGE_THRESHOLD_2P0 ((uint8_t)0x01) ///< VDU0 voltage threshold 2.0V +#define VDU0_VOLTAGE_THRESHOLD_2P1 ((uint8_t)0x02) ///< VDU0 voltage threshold 2.1V +#define VDU0_VOLTAGE_THRESHOLD_2P3 ((uint8_t)0x03) ///< VDU0 voltage threshold 2.3V + +/** + ******************************************************************************* + ** \brief VDU0 running state after reset + ******************************************************************************/ +#define VDU0_START_AFTER_RESET ((uint8_t)0x00) ///< VDU0 start after reset +#define VDU0_STOP_AFTER_RESET ((uint8_t)0x04) ///< VDU0 stop after reset + +/** + ******************************************************************************* + ** \brief NMI pin filter sample clock division + ******************************************************************************/ +#define NMI_PIN_FILTER_PCLK3_DIV1 ((uint8_t)0x00) ///< PCLK3 +#define NMI_PIN_FILTER_PCLK3_DIV8 ((uint8_t)0x04) ///< PCLK3/8 +#define NMI_PIN_FILTER_PCLK3_DIV32 ((uint8_t)0x08) ///< PCLK3/32 +#define NMI_PIN_FILTER_PCLK3_DIV64 ((uint8_t)0x0C) ///< PCLK3/64 + +/** + ******************************************************************************* + ** \brief NMI pin trigger edge type + ******************************************************************************/ +#define NMI_PIN_TRIGGER_EDGE_FALLING ((uint8_t)0x00) ///< Falling edge trigger +#define NMI_PIN_TRIGGER_EDGE_RISING ((uint8_t)0x10) ///< Rising edge trigger + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin interrupt request + ******************************************************************************/ +#define NMI_PIN_IRQ_DISABLE ((uint8_t)0x00) ///< Disable NMI pin interrupt request +#define NMI_PIN_IRQ_ENABLE ((uint8_t)0x20) ///< Enable NMI pin interrupt request + +/** + ******************************************************************************* + ** \brief Enable or disable NMI digital filter function + ******************************************************************************/ +#define NMI_DIGITAL_FILTER_DISABLE ((uint8_t)0x00) ///< Disable NMI digital filter +#define NMI_DIGITAL_FILTER_ENABLE ((uint8_t)0x40) ///< Enable NMI digital filter + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin ICG function + ******************************************************************************/ +#define NMI_PIN_ICG_FUNCTION_DISABLE ((uint8_t)0x80) ///< Disable NMI pin ICG function +#define NMI_PIN_ICG_FUNCTION_ENABLE ((uint8_t)0x00) ///< Enable NMI pin ICG function + +/** + ******************************************************************************* + ** \brief ICG start configure function on/off + ******************************************************************************/ +#ifndef ICG_FUNCTION_ON +#define ICG_FUNCTION_ON (1u) +#endif + +#ifndef ICG_FUNCTION_OFF +#define ICG_FUNCTION_OFF (0u) +#endif + +/** + ******************************************************************************* + ** \brief SWDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable SWDT hardware start */ +#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< SWDT register config */ +#define ICG0_SWDT_AUTS (SWDT_STOP_AFTER_RESET) +#define ICG0_SWDT_ITS (SWDT_RESET_REQUEST) +#define ICG0_SWDT_PERI (SWDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_SWDT_CKS (SWDT_COUNT_SWDTCLK_DIV2048) +#define ICG0_SWDT_WDPT (SWDT_0To100PCT) +#define ICG0_SWDT_SLTPOFF (SWDT_SPECIAL_MODE_COUNT_STOP) + +/*!< SWDT register config value */ +#if ICG0_SWDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_SWDT_REG_CONFIG (ICG0_SWDT_AUTS | ICG0_SWDT_ITS | ICG0_SWDT_PERI | \ + ICG0_SWDT_CKS | ICG0_SWDT_WDPT | ICG0_SWDT_SLTPOFF) +#else +#define ICG0_SWDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief WDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable WDT hardware start */ +#define ICG0_WDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< WDT register config */ +#define ICG0_WDT_AUTS (WDT_STOP_AFTER_RESET) +#define ICG0_WDT_ITS (WDT_RESET_REQUEST) +#define ICG0_WDT_PERI (WDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_WDT_CKS (WDT_COUNT_PCLK3_DIV8192) +#define ICG0_WDT_WDPT (WDT_0To100PCT) +#define ICG0_WDT_SLPOFF (WDT_SPECIAL_MODE_COUNT_STOP) + +/*!< WDT register config value */ +#if ICG0_WDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_WDT_REG_CONFIG (ICG0_WDT_AUTS | ICG0_WDT_ITS | ICG0_WDT_PERI | \ + ICG0_WDT_CKS | ICG0_WDT_WDPT | ICG0_WDT_SLPOFF) +#else +#define ICG0_WDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief HRC hardware start configuration + ******************************************************************************/ +/*!< Enable or disable HRC hardware start */ +#define ICG1_HRC_HARDWARE_START (ICG_FUNCTION_ON) + +/*!< HRC register config */ +#define ICG1_HRC_FREQSEL (HRC_FREQUENCY_16MHZ) +#define ICG1_HRC_STOP (HRC_OSCILLATION_START) + +/*!< HRC register config value */ +#if ICG1_HRC_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_HRC_REG_CONFIG (ICG1_HRC_FREQSEL | ICG1_HRC_STOP) +#else +#define ICG1_HRC_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief VDU0 hardware start configuration + ******************************************************************************/ +/*!< Enable or disable VDU0 hardware start */ +#define ICG1_VDU0_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< VDU0 register config */ +#define ICG1_VDU0_BOR_LEV (VDU0_VOLTAGE_THRESHOLD_2P3) +#define ICG1_VDU0_BORDIS (VDU0_STOP_AFTER_RESET) + +/*!< VDU0 register config value */ +#if ICG1_VDU0_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_VDU0_REG_CONFIG (ICG1_VDU0_BOR_LEV | ICG1_VDU0_BORDIS) +#else +#define ICG1_VDU0_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief NMI hardware start configuration + ******************************************************************************/ +/*!< Enable or disable NMI hardware start */ +#define ICG1_NMI_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< NMI register config */ +#define ICG1_NMI_SMPCLK (NMI_PIN_FILTER_PCLK3_DIV1) +#define ICG1_NMI_TRG (NMI_PIN_TRIGGER_EDGE_RISING) +#define ICG1_NMI_IMR (NMI_PIN_IRQ_DISABLE) +#define ICG1_NMI_NFEN (NMI_DIGITAL_FILTER_DISABLE) +#define ICG1_NMI_ICGENA (NMI_PIN_ICG_FUNCTION_DISABLE) + +/*!< NMI register config value */ +#if ICG1_NMI_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_NMI_REG_CONFIG (ICG1_NMI_SMPCLK | ICG1_NMI_TRG | \ + ICG1_NMI_IMR | ICG1_NMI_NFEN | ICG1_NMI_ICGENA) +#else +#define ICG1_NMI_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief ICG registers configuration + ******************************************************************************/ +/*!< ICG0 register value */ +#define ICG0_REGISTER_CONSTANT (((uint32_t)ICG0_WDT_REG_CONFIG << 16) | \ + ((uint32_t)ICG0_SWDT_REG_CONFIG) | \ + ((uint32_t)0xE000E000ul)) +/*!< ICG1 register value */ +#define ICG1_REGISTER_CONSTANT (((uint32_t)ICG1_NMI_REG_CONFIG << 24) | \ + ((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \ + ((uint32_t)ICG1_HRC_REG_CONFIG) | \ + ((uint32_t)0x03F8FEFEul)) +/*!< ICG2~7 register reserved value */ +#define ICG2_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG3_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG4_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG5_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG6_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG7_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // IcgGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_ICG_ENABLE */ + +#endif /* __HC32F460_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h new file mode 100644 index 000000000..141b1d268 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h @@ -0,0 +1,570 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_interrupts.h + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ +#ifndef __HC32F460_INTERRUPTS_H___ +#define __HC32F460_INTERRUPTS_H___ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup InterruptGroup Interrupt + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief IRQ registration structure definition + ******************************************************************************/ +typedef struct stc_irq_regi_conf +{ + en_int_src_t enIntSrc; + IRQn_Type enIRQn; + func_ptr_t pfnCallback; +}stc_irq_regi_conf_t; + +/** + ******************************************************************************* + ** \brief stop mode interrupt wakeup source enumeration + ******************************************************************************/ +typedef enum en_int_wkup_src +{ + Extint0WU = 1u << 0, + Extint1WU = 1u << 1, + Extint2WU = 1u << 2, + Extint3WU = 1u << 3, + Extint4WU = 1u << 4, + Extint5WU = 1u << 5, + Extint6WU = 1u << 6, + Extint7WU = 1u << 7, + Extint8WU = 1u << 8, + Extint9WU = 1u << 9, + Extint10WU = 1u << 10, + Extint11WU = 1u << 11, + Extint12WU = 1u << 12, + Extint13WU = 1u << 13, + Extint14WU = 1u << 14, + Extint15WU = 1u << 15, + SwdtWU = 1u << 16, + Vdu1WU = 1u << 17, + Vdu2WU = 1u << 18, + CmpWU = 1u << 19, + WakeupTimerWU = 1u << 20, + RtcAlarmWU = 1u << 21, + RtcPeriodWU = 1u << 22, + Timer0WU = 1u << 23, + Usart1RxWU = 1u << 25, +}en_int_wkup_src_t; + +/** + ******************************************************************************* + ** \brief event enumeration + ******************************************************************************/ +typedef enum en_evt +{ + Event0 = 1u << 0, + Event1 = 1u << 1, + Event2 = 1u << 2, + Event3 = 1u << 3, + Event4 = 1u << 4, + Event5 = 1u << 5, + Event6 = 1u << 6, + Event7 = 1u << 7, + Event8 = 1u << 8, + Event9 = 1u << 9, + Event10 = 1u << 10, + Event11 = 1u << 11, + Event12 = 1u << 12, + Event13 = 1u << 13, + Event14 = 1u << 14, + Event15 = 1u << 15, + Event16 = 1u << 16, + Event17 = 1u << 17, + Event18 = 1u << 18, + Event19 = 1u << 19, + Event20 = 1u << 20, + Event21 = 1u << 21, + Event22 = 1u << 22, + Event23 = 1u << 23, + Event24 = 1u << 24, + Event25 = 1u << 25, + Event26 = 1u << 26, + Event27 = 1u << 27, + Event28 = 1u << 28, + Event29 = 1u << 29, + Event30 = 1u << 30, + Event31 = 1u << 31, +}en_evt_t; + +/** + ******************************************************************************* + ** \brief interrupt enumeration + ******************************************************************************/ +typedef enum en_int +{ + Int0 = 1u << 0, + Int1 = 1u << 1, + Int2 = 1u << 2, + Int3 = 1u << 3, + Int4 = 1u << 4, + Int5 = 1u << 5, + Int6 = 1u << 6, + Int7 = 1u << 7, + Int8 = 1u << 8, + Int9 = 1u << 9, + Int10 = 1u << 10, + Int11 = 1u << 11, + Int12 = 1u << 12, + Int13 = 1u << 13, + Int14 = 1u << 14, + Int15 = 1u << 15, + Int16 = 1u << 16, + Int17 = 1u << 17, + Int18 = 1u << 18, + Int19 = 1u << 19, + Int20 = 1u << 20, + Int21 = 1u << 21, + Int22 = 1u << 22, + Int23 = 1u << 23, + Int24 = 1u << 24, + Int25 = 1u << 25, + Int26 = 1u << 26, + Int27 = 1u << 27, + Int28 = 1u << 28, + Int29 = 1u << 29, + Int30 = 1u << 30, + Int31 = 1u << 31, +}en_int_t; +/** + * @defgroup EXINT_Channel_Sel External interrupt channel selection + * @{ + */ +#define EXINT_CH00 (1UL << 0U) +#define EXINT_CH01 (1UL << 1U) +#define EXINT_CH02 (1UL << 2U) +#define EXINT_CH03 (1UL << 3U) +#define EXINT_CH04 (1UL << 4U) +#define EXINT_CH05 (1UL << 5U) +#define EXINT_CH06 (1UL << 6U) +#define EXINT_CH07 (1UL << 7U) +#define EXINT_CH08 (1UL << 8U) +#define EXINT_CH09 (1UL << 9U) +#define EXINT_CH10 (1UL <<10U) +#define EXINT_CH11 (1UL <<11U) +#define EXINT_CH12 (1UL <<12U) +#define EXINT_CH13 (1UL <<13U) +#define EXINT_CH14 (1UL <<14U) +#define EXINT_CH15 (1UL <<15U) +#define EXINT_CH_MASK (EXINT_CH00 | EXINT_CH01 | EXINT_CH02 | EXINT_CH03 | \ + EXINT_CH04 | EXINT_CH05 | EXINT_CH06 | EXINT_CH07 | \ + EXINT_CH08 | EXINT_CH09 | EXINT_CH10 | EXINT_CH11 | \ + EXINT_CH12 | EXINT_CH13 | EXINT_CH14 | EXINT_CH15) +/** + * @} + */ + + +/*! Bit mask definition*/ +#define BIT_MASK_00 (1ul << 0) +#define BIT_MASK_01 (1ul << 1) +#define BIT_MASK_02 (1ul << 2) +#define BIT_MASK_03 (1ul << 3) +#define BIT_MASK_04 (1ul << 4) +#define BIT_MASK_05 (1ul << 5) +#define BIT_MASK_06 (1ul << 6) +#define BIT_MASK_07 (1ul << 7) +#define BIT_MASK_08 (1ul << 8) +#define BIT_MASK_09 (1ul << 9) +#define BIT_MASK_10 (1ul << 10) +#define BIT_MASK_11 (1ul << 11) +#define BIT_MASK_12 (1ul << 12) +#define BIT_MASK_13 (1ul << 13) +#define BIT_MASK_14 (1ul << 14) +#define BIT_MASK_15 (1ul << 15) +#define BIT_MASK_16 (1ul << 16) +#define BIT_MASK_17 (1ul << 17) +#define BIT_MASK_18 (1ul << 18) +#define BIT_MASK_19 (1ul << 19) +#define BIT_MASK_20 (1ul << 20) +#define BIT_MASK_21 (1ul << 21) +#define BIT_MASK_22 (1ul << 22) +#define BIT_MASK_23 (1ul << 23) +#define BIT_MASK_24 (1ul << 24) +#define BIT_MASK_25 (1ul << 25) +#define BIT_MASK_26 (1ul << 26) +#define BIT_MASK_27 (1ul << 27) +#define BIT_MASK_28 (1ul << 28) +#define BIT_MASK_29 (1ul << 29) +#define BIT_MASK_30 (1ul << 30) +#define BIT_MASK_31 (1ul << 31) + +/*! Default Priority for IRQ, Possible values are 0 (high priority) to 15 (low priority) */ +#define DDL_IRQ_PRIORITY_DEFAULT 15u + +/*! Interrupt priority level 00 ~ 15*/ +#define DDL_IRQ_PRIORITY_00 (0u) +#define DDL_IRQ_PRIORITY_01 (1u) +#define DDL_IRQ_PRIORITY_02 (2u) +#define DDL_IRQ_PRIORITY_03 (3u) +#define DDL_IRQ_PRIORITY_04 (4u) +#define DDL_IRQ_PRIORITY_05 (5u) +#define DDL_IRQ_PRIORITY_06 (6u) +#define DDL_IRQ_PRIORITY_07 (7u) +#define DDL_IRQ_PRIORITY_08 (8u) +#define DDL_IRQ_PRIORITY_09 (9u) +#define DDL_IRQ_PRIORITY_10 (10u) +#define DDL_IRQ_PRIORITY_11 (11u) +#define DDL_IRQ_PRIORITY_12 (12u) +#define DDL_IRQ_PRIORITY_13 (13u) +#define DDL_IRQ_PRIORITY_14 (14u) +#define DDL_IRQ_PRIORITY_15 (15u) + +/** + ******************************************************************************* + ** \brief AOS software trigger function + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + bM4_AOS_INT_SFTTRG_STRG = 1u; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 1 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig) +{ + M4_AOS->COMTRG1 = enTrig; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 2 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig) +{ + M4_AOS->COMTRG2 = enTrig; +} + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf); +extern en_result_t enIrqResign(IRQn_Type enIRQn); +extern en_result_t enShareIrqEnable(en_int_src_t enIntSrc); +extern en_result_t enShareIrqDisable(en_int_src_t enIntSrc); +extern en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc); +extern en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc); +extern en_result_t enEventEnable(uint32_t u32Event); +extern en_result_t enEventDisable(uint32_t u32Event); +extern en_result_t enIntEnable(uint32_t u32Int); +extern en_result_t enIntDisable(uint32_t u32Int); +extern en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh); +extern void EXINT_ClrExIntSrc(uint32_t u32ExIntCh); +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +__WEAKDEF void NMI_IrqHandler(void); +__WEAKDEF void HardFault_IrqHandler(void); +__WEAKDEF void MemManage_IrqHandler(void); +__WEAKDEF void BusFault_IrqHandler(void); +__WEAKDEF void UsageFault_IrqHandler(void); +__WEAKDEF void SVC_IrqHandler(void); +__WEAKDEF void DebugMon_IrqHandler(void); +__WEAKDEF void PendSV_IrqHandler(void); +__WEAKDEF void SysTick_IrqHandler(void); + +__WEAKDEF void Extint00_IrqHandler(void); +__WEAKDEF void Extint01_IrqHandler(void); +__WEAKDEF void Extint02_IrqHandler(void); +__WEAKDEF void Extint03_IrqHandler(void); +__WEAKDEF void Extint04_IrqHandler(void); +__WEAKDEF void Extint05_IrqHandler(void); +__WEAKDEF void Extint06_IrqHandler(void); +__WEAKDEF void Extint07_IrqHandler(void); +__WEAKDEF void Extint08_IrqHandler(void); +__WEAKDEF void Extint09_IrqHandler(void); +__WEAKDEF void Extint10_IrqHandler(void); +__WEAKDEF void Extint11_IrqHandler(void); +__WEAKDEF void Extint12_IrqHandler(void); +__WEAKDEF void Extint13_IrqHandler(void); +__WEAKDEF void Extint14_IrqHandler(void); +__WEAKDEF void Extint15_IrqHandler(void); + +__WEAKDEF void Dma1Tc0_IrqHandler(void); +__WEAKDEF void Dma1Tc1_IrqHandler(void); +__WEAKDEF void Dma1Tc2_IrqHandler(void); +__WEAKDEF void Dma1Tc3_IrqHandler(void); +__WEAKDEF void Dma2Tc0_IrqHandler(void); +__WEAKDEF void Dma2Tc1_IrqHandler(void); +__WEAKDEF void Dma2Tc2_IrqHandler(void); +__WEAKDEF void Dma2Tc3_IrqHandler(void); +__WEAKDEF void Dma1Btc0_IrqHandler(void); +__WEAKDEF void Dma1Btc1_IrqHandler(void); +__WEAKDEF void Dma1Btc2_IrqHandler(void); +__WEAKDEF void Dma1Btc3_IrqHandler(void); +__WEAKDEF void Dma2Btc0_IrqHandler(void); +__WEAKDEF void Dma2Btc1_IrqHandler(void); +__WEAKDEF void Dma2Btc2_IrqHandler(void); +__WEAKDEF void Dma2Btc3_IrqHandler(void); +__WEAKDEF void Dma1Err0_IrqHandler(void); +__WEAKDEF void Dma1Err1_IrqHandler(void); +__WEAKDEF void Dma1Err2_IrqHandler(void); +__WEAKDEF void Dma1Err3_IrqHandler(void); +__WEAKDEF void Dma2Err0_IrqHandler(void); +__WEAKDEF void Dma2Err1_IrqHandler(void); +__WEAKDEF void Dma2Err2_IrqHandler(void); +__WEAKDEF void Dma2Err3_IrqHandler(void); + +__WEAKDEF void EfmPgmEraseErr_IrqHandler(void); +__WEAKDEF void EfmColErr_IrqHandler(void); +__WEAKDEF void EfmOpEnd_IrqHandler(void); +__WEAKDEF void QspiInt_IrqHandler(void); +__WEAKDEF void Dcu1_IrqHandler(void); +__WEAKDEF void Dcu2_IrqHandler(void); +__WEAKDEF void Dcu3_IrqHandler(void); +__WEAKDEF void Dcu4_IrqHandler(void); + +__WEAKDEF void Timer01GCMA_IrqHandler(void); +__WEAKDEF void Timer01GCMB_IrqHandler(void); +__WEAKDEF void Timer02GCMA_IrqHandler(void); +__WEAKDEF void Timer02GCMB_IrqHandler(void); + +__WEAKDEF void MainOscStop_IrqHandler(void); +__WEAKDEF void WakeupTimer_IrqHandler(void); +__WEAKDEF void Swdt_IrqHandler(void); + +__WEAKDEF void Timer61GCMA_IrqHandler(void); +__WEAKDEF void Timer61GCMB_IrqHandler(void); +__WEAKDEF void Timer61GCMC_IrqHandler(void); +__WEAKDEF void Timer61GCMD_IrqHandler(void); +__WEAKDEF void Timer61GCME_IrqHandler(void); +__WEAKDEF void Timer61GCMF_IrqHandler(void); +__WEAKDEF void Timer61GOV_IrqHandler(void); +__WEAKDEF void Timer61GUD_IrqHandler(void); +__WEAKDEF void Timer61GDT_IrqHandler(void); +__WEAKDEF void Timer61SCMA_IrqHandler(void); +__WEAKDEF void Timer61SCMB_IrqHandler(void); + +__WEAKDEF void Timer62GCMA_IrqHandler(void); +__WEAKDEF void Timer62GCMB_IrqHandler(void); +__WEAKDEF void Timer62GCMC_IrqHandler(void); +__WEAKDEF void Timer62GCMD_IrqHandler(void); +__WEAKDEF void Timer62GCME_IrqHandler(void); +__WEAKDEF void Timer62GCMF_IrqHandler(void); +__WEAKDEF void Timer62GOV_IrqHandler(void); +__WEAKDEF void Timer62GUD_IrqHandler(void); +__WEAKDEF void Timer62GDT_IrqHandler(void); +__WEAKDEF void Timer62SCMA_IrqHandler(void); +__WEAKDEF void Timer62SCMB_IrqHandler(void); + +__WEAKDEF void Timer63GCMA_IrqHandler(void); +__WEAKDEF void Timer63GCMB_IrqHandler(void); +__WEAKDEF void Timer63GCMC_IrqHandler(void); +__WEAKDEF void Timer63GCMD_IrqHandler(void); +__WEAKDEF void Timer63GCME_IrqHandler(void); +__WEAKDEF void Timer63GCMF_IrqHandler(void); +__WEAKDEF void Timer63GOV_IrqHandler(void); +__WEAKDEF void Timer63GUD_IrqHandler(void); +__WEAKDEF void Timer63GDT_IrqHandler(void); +__WEAKDEF void Timer63SCMA_IrqHandler(void); +__WEAKDEF void Timer63SCMB_IrqHandler(void); + +__WEAKDEF void TimerA1OV_IrqHandler(void); +__WEAKDEF void TimerA1UD_IrqHandler(void); +__WEAKDEF void TimerA1CMP_IrqHandler(void); +__WEAKDEF void TimerA2OV_IrqHandler(void); +__WEAKDEF void TimerA2UD_IrqHandler(void); +__WEAKDEF void TimerA2CMP_IrqHandler(void); +__WEAKDEF void TimerA3OV_IrqHandler(void); +__WEAKDEF void TimerA3UD_IrqHandler(void); +__WEAKDEF void TimerA3CMP_IrqHandler(void); +__WEAKDEF void TimerA4OV_IrqHandler(void); +__WEAKDEF void TimerA4UD_IrqHandler(void); +__WEAKDEF void TimerA4CMP_IrqHandler(void); +__WEAKDEF void TimerA5OV_IrqHandler(void); +__WEAKDEF void TimerA5UD_IrqHandler(void); +__WEAKDEF void TimerA5CMP_IrqHandler(void); +__WEAKDEF void TimerA6OV_IrqHandler(void); +__WEAKDEF void TimerA6UD_IrqHandler(void); +__WEAKDEF void TimerA6CMP_IrqHandler(void); + +__WEAKDEF void UsbGlobal_IrqHandler(void); + +__WEAKDEF void Usart1RxErr_IrqHandler(void); +__WEAKDEF void Usart1RxEnd_IrqHandler(void); +__WEAKDEF void Usart1TxEmpty_IrqHandler(void); +__WEAKDEF void Usart1TxEnd_IrqHandler(void); +__WEAKDEF void Usart1RxTO_IrqHandler(void); +__WEAKDEF void Usart2RxErr_IrqHandler(void); +__WEAKDEF void Usart2RxEnd_IrqHandler(void); +__WEAKDEF void Usart2TxEmpty_IrqHandler(void); +__WEAKDEF void Usart2TxEnd_IrqHandler(void); +__WEAKDEF void Usart2RxTO_IrqHandler(void); +__WEAKDEF void Usart3RxErr_IrqHandler(void); +__WEAKDEF void Usart3RxEnd_IrqHandler(void); +__WEAKDEF void Usart3TxEmpty_IrqHandler(void); +__WEAKDEF void Usart3TxEnd_IrqHandler(void); +__WEAKDEF void Usart3RxTO_IrqHandler(void); +__WEAKDEF void Usart4RxErr_IrqHandler(void); +__WEAKDEF void Usart4RxEnd_IrqHandler(void); +__WEAKDEF void Usart4TxEmpty_IrqHandler(void); +__WEAKDEF void Usart4TxEnd_IrqHandler(void); +__WEAKDEF void Usart4RxTO_IrqHandler(void); + +__WEAKDEF void Spi1RxEnd_IrqHandler(void); +__WEAKDEF void Spi1TxEmpty_IrqHandler(void); +__WEAKDEF void Spi1Err_IrqHandler(void); +__WEAKDEF void Spi1Idle_IrqHandler(void); +__WEAKDEF void Spi2RxEnd_IrqHandler(void); +__WEAKDEF void Spi2TxEmpty_IrqHandler(void); +__WEAKDEF void Spi2Err_IrqHandler(void); +__WEAKDEF void Spi2Idle_IrqHandler(void); +__WEAKDEF void Spi3RxEnd_IrqHandler(void); +__WEAKDEF void Spi3TxEmpty_IrqHandler(void); +__WEAKDEF void Spi3Err_IrqHandler(void); +__WEAKDEF void Spi3Idle_IrqHandler(void); +__WEAKDEF void Spi4RxEnd_IrqHandler(void); +__WEAKDEF void Spi4TxEmpty_IrqHandler(void); +__WEAKDEF void Spi4Err_IrqHandler(void); +__WEAKDEF void Spi4Idle_IrqHandler(void); + +__WEAKDEF void Timer41GCMUH_IrqHandler(void); +__WEAKDEF void Timer41GCMUL_IrqHandler(void); +__WEAKDEF void Timer41GCMVH_IrqHandler(void); +__WEAKDEF void Timer41GCMVL_IrqHandler(void); +__WEAKDEF void Timer41GCMWH_IrqHandler(void); +__WEAKDEF void Timer41GCMWL_IrqHandler(void); +__WEAKDEF void Timer41GOV_IrqHandler(void); +__WEAKDEF void Timer41GUD_IrqHandler(void); +__WEAKDEF void Timer41ReloadU_IrqHandler(void); +__WEAKDEF void Timer41ReloadV_IrqHandler(void); +__WEAKDEF void Timer41ReloadW_IrqHandler(void); +__WEAKDEF void Timer42GCMUH_IrqHandler(void); +__WEAKDEF void Timer42GCMUL_IrqHandler(void); +__WEAKDEF void Timer42GCMVH_IrqHandler(void); +__WEAKDEF void Timer42GCMVL_IrqHandler(void); +__WEAKDEF void Timer42GCMWH_IrqHandler(void); +__WEAKDEF void Timer42GCMWL_IrqHandler(void); +__WEAKDEF void Timer42GOV_IrqHandler(void); +__WEAKDEF void Timer42GUD_IrqHandler(void); +__WEAKDEF void Timer42ReloadU_IrqHandler(void); +__WEAKDEF void Timer42ReloadV_IrqHandler(void); +__WEAKDEF void Timer42ReloadW_IrqHandler(void); +__WEAKDEF void Timer43GCMUH_IrqHandler(void); +__WEAKDEF void Timer43GCMUL_IrqHandler(void); +__WEAKDEF void Timer43GCMVH_IrqHandler(void); +__WEAKDEF void Timer43GCMVL_IrqHandler(void); +__WEAKDEF void Timer43GCMWH_IrqHandler(void); +__WEAKDEF void Timer43GCMWL_IrqHandler(void); +__WEAKDEF void Timer43GOV_IrqHandler(void); +__WEAKDEF void Timer43GUD_IrqHandler(void); +__WEAKDEF void Timer43ReloadU_IrqHandler(void); +__WEAKDEF void Timer43ReloadV_IrqHandler(void); +__WEAKDEF void Timer43ReloadW_IrqHandler(void); + +__WEAKDEF void Emb1_IrqHandler(void); +__WEAKDEF void Emb2_IrqHandler(void); +__WEAKDEF void Emb3_IrqHandler(void); +__WEAKDEF void Emb4_IrqHandler(void); + +__WEAKDEF void I2s1Tx_IrqHandler(void); +__WEAKDEF void I2s1Rx_IrqHandler(void); +__WEAKDEF void I2s1Err_IrqHandler(void); +__WEAKDEF void I2s2Tx_IrqHandler(void); +__WEAKDEF void I2s2Rx_IrqHandler(void); +__WEAKDEF void I2s2Err_IrqHandler(void); +__WEAKDEF void I2s3Tx_IrqHandler(void); +__WEAKDEF void I2s3Rx_IrqHandler(void); +__WEAKDEF void I2s3Err_IrqHandler(void); +__WEAKDEF void I2s4Tx_IrqHandler(void); +__WEAKDEF void I2s4Rx_IrqHandler(void); +__WEAKDEF void I2s4Err_IrqHandler(void); + +__WEAKDEF void I2c1RxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEmpty_IrqHandler(void); +__WEAKDEF void I2c1Err_IrqHandler(void); +__WEAKDEF void I2c2RxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEmpty_IrqHandler(void); +__WEAKDEF void I2c2Err_IrqHandler(void); +__WEAKDEF void I2c3RxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEmpty_IrqHandler(void); +__WEAKDEF void I2c3Err_IrqHandler(void); + +__WEAKDEF void Pvd1_IrqHandler(void); +__WEAKDEF void Pvd2_IrqHandler(void); + +__WEAKDEF void FcmErr_IrqHandler(void); +__WEAKDEF void FcmEnd_IrqHandler(void); +__WEAKDEF void FcmOV_IrqHandler(void); + +__WEAKDEF void Wdt_IrqHandler(void); + +__WEAKDEF void ADC1A_IrqHandler(void); +__WEAKDEF void ADC1B_IrqHandler(void); +__WEAKDEF void ADC1ChCmp_IrqHandler(void); +__WEAKDEF void ADC1SeqCmp_IrqHandler(void); +__WEAKDEF void ADC2A_IrqHandler(void); +__WEAKDEF void ADC2B_IrqHandler(void); +__WEAKDEF void ADC2ChCmp_IrqHandler(void); +__WEAKDEF void ADC2SeqCmp_IrqHandler(void); + +__WEAKDEF void Sdio1_IrqHandler(void); +__WEAKDEF void Sdio2_IrqHandler(void); + +__WEAKDEF void Can_IrqHandler(void); + +//@} // InterruptGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_INTERRUPTS_ENABLE */ + +#endif /* __HC32F460_INTERRUPTS_H___ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h new file mode 100644 index 000000000..a82474b0d --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h @@ -0,0 +1,191 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.h + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +#ifndef __HC32F460_KEYSCAN_H__ +#define __HC32F460_KEYSCAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup KeyscanGroup Matrix Key Scan Module (KeyScan) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to hi-z state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_hiz_cycle +{ + Hiz4 = 0u, + Hiz8 = 1u, + Hiz16 = 2u, + Hiz32 = 3u, + Hiz64 = 4u, + Hiz256 = 5u, + Hiz512 = 6u, + Hiz1K = 7u, +}en_hiz_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to low state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_low_cycle +{ + Low8 = 3u, + Low16 = 4u, + Low32 = 5u, + Low64 = 6u, + Low128 = 7u, + Low256 = 8u, + Low512 = 9u, + Low1K = 10u, + Low2K = 11u, + Low4K = 12u, + Low8K = 13u, + Low16K = 14u, + Low32K = 15u, + Low64K = 16u, + Low128K = 17u, + Low256K = 18u, + Low512K = 19u, + Low1M = 20u, + Low2M = 21u, + Low4M = 22u, + Low8M = 23u, + Low16M = 24u, +}en_low_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to key scan clock + ** + ** \note + ******************************************************************************/ +typedef enum en_keyscan_clk +{ + KeyscanHclk = 0u, ///< use HCLK as scan clock + KeyscanLrc = 1u, ///< use internal Low RC as scan clock + KeyscanXtal32 = 2u, ///< use external XTAL32 as scan clock +}en_keyscan_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYOUT combination + ******************************************************************************/ +typedef enum en_keyout_sel +{ + Keyout0To1 = 1u, ///< KEYOUT 0 to 1 are selected + Keyout0To2 = 2u, ///< KEYOUT 0 to 2 are selected + Keyout0To3 = 3u, ///< KEYOUT 0 to 3 are selected + Keyout0To4 = 4u, ///< KEYOUT 0 to 4 are selected + Keyout0To5 = 5u, ///< KEYOUT 0 to 5 are selected + Keyout0To6 = 6u, ///< KEYOUT 0 to 6 are selected + Keyout0To7 = 7u, ///< KEYOUT 0 to 7 are selected +}en_keyout_sel_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYIN combination + ******************************************************************************/ +typedef enum en_keyin_sel +{ + Keyin00 = 1u << 0, ///< KEYIN 0 is selected + Keyin01 = 1u << 1, ///< KEYIN 1 is selected + Keyin02 = 1u << 2, ///< KEYIN 2 is selected + Keyin03 = 1u << 3, ///< KEYIN 3 is selected + Keyin04 = 1u << 4, ///< KEYIN 4 is selected + Keyin05 = 1u << 5, ///< KEYIN 5 is selected + Keyin06 = 1u << 6, ///< KEYIN 6 is selected + Keyin07 = 1u << 7, ///< KEYIN 7 is selected + Keyin08 = 1u << 8, ///< KEYIN 8 is selected + Keyin09 = 1u << 9, ///< KEYIN 9 is selected + Keyin10 = 1u << 10, ///< KEYIN 10 is selected + Keyin11 = 1u << 11, ///< KEYIN 11 is selected + Keyin12 = 1u << 12, ///< KEYIN 12 is selected + Keyin13 = 1u << 13, ///< KEYIN 13 is selected + Keyin14 = 1u << 14, ///< KEYIN 14 is selected + Keyin15 = 1u << 15, ///< KEYIN 15 is selected +}en_keyin_sel_t; + +/** + ******************************************************************************* + ** \brief Keyscan configuration + ** + ** \note The Keyscan configuration structure + ******************************************************************************/ +typedef struct stc_keyscan_config +{ + en_hiz_cycle_t enHizCycle; ///< KEYOUT Hiz state cycles, ref @ en_hiz_cycle_t for details + en_low_cycle_t enLowCycle; ///< KEYOUT Low state cycles, ref @ en_low_cycle_t for details + en_keyscan_clk_t enKeyscanClk; ///< Key scan clock, ref @ en_keyscan_clk_t for details + en_keyout_sel_t enKeyoutSel; ///< KEYOUT selection, ref @ en_keyout_sel_t for details + uint16_t u16KeyinSel; ///< KEYIN selection, ref @ en_keyin_sel_t for details +}stc_keyscan_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig); +extern en_result_t KEYSCAN_DeInit(void); +extern en_result_t KEYSCAN_Start(void); +extern en_result_t KEYSCAN_Stop(void); +extern uint8_t KEYSCAN_GetColIdx(void); + +//@} // KeyscanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_KEYSCAN_ENABLE */ + +#endif /* __HC32F460_KEYSCAN_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h new file mode 100644 index 000000000..b46e6ce7a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h @@ -0,0 +1,293 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.h + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ +#ifndef __HC32F460_MPU_H__ +#define __HC32F460_MPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_MPU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup MpuGroup Memory Protection Unit(MPU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief MPU region number enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_num +{ + MpuRegionNum0 = 0u, ///< MPU region number 0 + MpuRegionNum1 = 1u, ///< MPU region number 1 + MpuRegionNum2 = 2u, ///< MPU region number 2 + MpuRegionNum3 = 3u, ///< MPU region number 3 + MpuRegionNum4 = 4u, ///< MPU region number 4 + MpuRegionNum5 = 5u, ///< MPU region number 5 + MpuRegionNum6 = 6u, ///< MPU region number 6 + MpuRegionNum7 = 7u, ///< MPU region number 7 + MpuRegionNum8 = 8u, ///< MPU region number 8 + MpuRegionNum9 = 9u, ///< MPU region number 9 + MpuRegionNum10 = 10u, ///< MPU region number 10 + MpuRegionNum11 = 11u, ///< MPU region number 11 + MpuRegionNum12 = 12u, ///< MPU region number 12 + MpuRegionNum13 = 13u, ///< MPU region number 13 + MpuRegionNum14 = 14u, ///< MPU region number 14 + MpuRegionNum15 = 15u, ///< MPU region number 15 +} en_mpu_region_num_t; + +/** + ******************************************************************************* + ** \brief MPU region size enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_size +{ + MpuRegionSize32Byte = 4u, ///< 32 Byte + MpuRegionSize64Byte = 5u, ///< 64 Byte + MpuRegionSize128Byte = 6u, ///< 126 Byte + MpuRegionSize256Byte = 7u, ///< 256 Byte + MpuRegionSize512Byte = 8u, ///< 512 Byte + MpuRegionSize1KByte = 9u, ///< 1K Byte + MpuRegionSize2KByte = 10u, ///< 2K Byte + MpuRegionSize4KByte = 11u, ///< 4K Byte + MpuRegionSize8KByte = 12u, ///< 8K Byte + MpuRegionSize16KByte = 13u, ///< 16K Byte + MpuRegionSize32KByte = 14u, ///< 32K Byte + MpuRegionSize64KByte = 15u, ///< 64K Byte + MpuRegionSize128KByte = 16u, ///< 128K Byte + MpuRegionSize256KByte = 17u, ///< 256K Byte + MpuRegionSize512KByte = 18u, ///< 512K Byte + MpuRegionSize1MByte = 19u, ///< 1M Byte + MpuRegionSize2MByte = 20u, ///< 2M Byte + MpuRegionSize4MByte = 21u, ///< 4M Byte + MpuRegionSize8MByte = 22u, ///< 8M Byte + MpuRegionSize16MByte = 23u, ///< 16M Byte + MpuRegionSize32MByte = 24u, ///< 32M Byte + MpuRegionSize64MByte = 25u, ///< 64M Byte + MpuRegionSize128MByte = 26u, ///< 128M Byte + MpuRegionSize256MByte = 27u, ///< 256M Byte + MpuRegionSize512MByte = 28u, ///< 512M Byte + MpuRegionSize1GByte = 29u, ///< 1G Byte + MpuRegionSize2GByte = 30u, ///< 2G Byte + MpuRegionSize4GByte = 31u, ///< 4G Byte +} en_mpu_region_size_t; + +/** + ******************************************************************************* + ** \brief MPU region enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_type +{ + SMPU1Region = 0u, ///< System DMA_1 MPU + SMPU2Region = 1u, ///< System DMA_2 MPU + FMPURegion = 2u, ///< System USBFS_DMA MPU +} en_mpu_region_type_t; + +/** + ******************************************************************************* + ** \brief MPU action selection enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_action_sel +{ + MpuNoneAction = 0u, ///< MPU don't action. + MpuTrigBusError = 1u, ///< MPU trigger bus error + MpuTrigNmi = 2u, ///< MPU trigger bus NMI interrupt + MpuTrigReset = 3u, ///< MPU trigger reset +} en_mpu_action_sel_t; + +/** + ******************************************************************************* + ** \brief MPU IP protection mode enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_ip_prot_mode +{ + AesReadProt = (1ul << 0), ///< AES read protection + AesWriteProt = (1ul << 1), ///< AES write protection + HashReadProt = (1ul << 2), ///< HASH read protection + HashWriteProt = (1ul << 3), ///< HASH write protection + TrngReadProt = (1ul << 4), ///< TRNG read protection + TrngWriteProt = (1ul << 5), ///< TRNG write protection + CrcReadProt = (1ul << 6), ///< CRC read protection + CrcWriteProt = (1ul << 7), ///< CRC write protection + FmcReadProt = (1ul << 8), ///< FMC read protection + FmcWriteProt = (1ul << 9), ///< FMC write protection + WdtReadProt = (1ul << 12), ///< WDT read protection + WdtWriteProt = (1ul << 13), ///< WDT write protection + SwdtReadProt = (1ul << 14), ///< WDT read protection + SwdtWriteProt = (1ul << 15), ///< WDT write protection + BksramReadProt = (1ul << 16), ///< BKSRAM read protection + BksramWriteProt = (1ul << 17), ///< BKSRAM write protection + RtcReadProt = (1ul << 18), ///< RTC read protection + RtcWriteProt = (1ul << 19), ///< RTC write protection + DmpuReadProt = (1ul << 20), ///< DMPU read protection + DmpuWriteProt = (1ul << 21), ///< DMPU write protection + SramcReadProt = (1ul << 22), ///< SRAMC read protection + SramcWriteProt = (1ul << 23), ///< SRAMC write protection + IntcReadProt = (1ul << 24), ///< INTC read protection + IntcWriteProt = (1ul << 25), ///< INTC write protection + SyscReadProt = (1ul << 26), ///< SYSC read protection + SyscWriteProt = (1ul << 27), ///< SYSC write protection + MstpReadProt = (1ul << 28), ///< MSTP read protection + MstpWriteProt = (1ul << 29), ///< MSTP write protection + BusErrProt = (1ul << 31), ///< BUSERR write protection +} en_mpu_ip_prot_mode_t; + +/** + ******************************************************************************* + ** \brief MPU protection region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_permission +{ + en_mpu_action_sel_t enAction; ///< Specifies MPU action + + en_functional_state_t enRegionEnable; ///< Disable: Disable region protection; Enable:Enable region protection + + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read + +} stc_mpu_prot_region_permission_t; + +/** + ******************************************************************************* + ** \brief MPU background region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_permission +{ + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read +} stc_mpu_bkgd_region_permission_t_t; + +/** + ******************************************************************************* + ** \brief MPU background region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_init +{ + stc_mpu_bkgd_region_permission_t_t stcSMPU1BkgdPermission; ///< Specifies SMPU1 background permission and this stuctrue detail refer of @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcSMPU2BkgdPermission; ///< Specifies SMPU2 background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcFMPUBkgdPermission; ///< Specifies FMPU background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t +} stc_mpu_bkgd_region_init_t; + +/** + ******************************************************************************* + ** \brief MPU protect region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_init +{ + uint32_t u32RegionBaseAddress; ///< Specifies region base address + + en_mpu_region_size_t enRegionSize; ///< Specifies region size and This parameter can be a value of @ref en_mpu_region_size_t + + stc_mpu_prot_region_permission_t stcSMPU1Permission; ///< Specifies DMA1 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcSMPU2Permission; ///< Specifies DMA2 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcFMPUPermission; ///< Specifies USBFS-DMA MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t +} stc_mpu_prot_region_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg); +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg); +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize); +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr); +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel); +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_WriteProtCmd(en_functional_state_t enState); +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState); + +//@} // MpuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_MPU_ENABLE */ + +#endif /* __HC32F460_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h new file mode 100644 index 000000000..53a00ff1b --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h @@ -0,0 +1,139 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.h + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ +#ifndef __HC32F460_OTS_H__ +#define __HC32F460_OTS_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_OTS_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup OtsGroup On-chip Temperature Sensor(OTS) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Automatically turn off the analog temperature sensor after the temperature + measurement is over. */ +typedef enum en_ots_auto_off +{ + OtsAutoOff_Disable = 0x0, ///< Disable automatically turn off OTS. + OtsAutoOff_Enable = 0x1, ///< Enable automatically turn off OTS. +} en_ots_auto_off_t; + +/* Temperature measurement end interrupt request. */ +typedef enum en_ots_ie +{ + OtsInt_Disable = 0x0, ///< Disable OTS interrupt. + OtsInt_Enable = 0x1, ///< Enable OTS interrupt. +} en_ots_ie_t; + +/* OTS clock selection. */ +typedef enum en_ots_clk_sel +{ + OtsClkSel_Xtal = 0x0, ///< Select XTAL as OTS clock. + OtsClkSel_Hrc = 0x1, ///< Select HRC as OTS clock. +} en_ots_clk_sel_t; + +/* OTS OTS initialization structure definition. */ +typedef struct stc_ots_init +{ + en_ots_auto_off_t enAutoOff; ///< @ref en_ots_auto_off_t. + en_ots_clk_sel_t enClkSel; ///< @ref en_ots_clk_sel_t. + float32_t f32SlopeK; ///< K: Temperature slope (calculated by calibration experiment). */ + float32_t f32OffsetM; ///< M: Temperature offset (calculated by calibration experiment). */ +} stc_ots_init_t; + +/* OTS common trigger source select */ +typedef enum en_ots_com_trigger +{ + OtsComTrigger_1 = 0x1, ///< Select common trigger 1. + OtsComTrigger_2 = 0x2, ///< Select common trigger 2. + OtsComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_ots_com_trigger_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)1u; +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)0u; +} + +en_result_t OTS_Init(const stc_ots_init_t *pstcInit); +void OTS_DeInit(void); + +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); +void OTS_SetTriggerSrc(en_event_src_t enEvent); +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout); + +float OTS_CalculateTemp(void); + +//@} // OtsGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_OTS_ENABLE */ + +#endif /* __HC32F460_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h new file mode 100644 index 000000000..f170784d5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h @@ -0,0 +1,567 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.h + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ +#ifndef __HC32F460_PWC_H__ +#define __HC32F460_PWC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_PWC_ENABLE == DDL_ON) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup PwcGroup Power Control(PWC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_powerdown_md +{ + PowerDownMd1 = 0u, ///< Power down mode 1. + PowerDownMd2 = 1u, ///< Power down mode 2. + PowerDownMd3 = 2u, ///< Power down mode 3. + PowerDownMd4 = 3u, ///< Power down mode 4. +}en_pwc_powerdown_md_t; + +/** + ******************************************************************************* + ** \brief The IO retain status under power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_iortn +{ + IoPwrDownRetain = 0u, ///< Io keep under power down mode. + IoPwrRstRetain = 1u, ///< Io keep after power reset. + IoHighImp = 2u, ///< IO high impedance either power down or power reset. +}en_pwc_iortn_t; + +/** + ******************************************************************************* + ** \brief The driver ability while different speed mode enter stop mode. + ** + ******************************************************************************/ +typedef enum en_pwc_stopdas +{ + StopHighspeed = 0u, ///< The driver ability while high speed mode enter stop mode. + StopUlowspeed = 3u, ///< The driver ability while ultra_low speed mode enter stop mode. +}en_pwc_stopdas_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver voltage select. + ** + ******************************************************************************/ +typedef enum en_pwc_rundrvs +{ + RunUHighspeed = 0u, ///< The ultra_high speed. + RunUlowspeed = 2u, ///< The ultra_low speed. + RunHighspeed = 3u, ///< The high speed. +}en_pwc_rundrvs_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver ability scaling. + ** + ******************************************************************************/ +typedef enum en_pwc_drvability_sca +{ + Ulowspeed = 8u, ///< The ultra_low speed. + HighSpeed = 15u, ///< The high speed. +}en_pwc_drvability_sca_t; + +/** + ******************************************************************************* + ** \brief The power down wake up time select. + ** + ******************************************************************************/ +typedef enum en_pwc_waketime_sel +{ + Vcap01 = 0u, ///< Wake up while vcap capacitance 2*0.1uf. + Vcap0047 = 1u, ///< Wake up while vcap capacitance 2*0.047uf. +}en_pwc_waketime_sel_t; + +/** + ******************************************************************************* + ** \brief The wait or not wait flash stable while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_flash_sel +{ + Wait = 0u, ///< wait flash stable. + NotWait = 1u, ///< Not Wait flash stable. +}en_pwc_stop_flash_sel_t; + +/** + ******************************************************************************* + ** \brief The clk value while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_clk_sel +{ + ClkFix = 0u, ///< clock fix. + ClkMrc = 1u, ///< clock source is MRC, only ram code. +}en_pwc_stop_clk_sel_t; + +/** + ******************************************************************************* + ** \brief The power down wake up event edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_edge_sel +{ + EdgeFalling = 0u, ///< Falling edge. + EdgeRising = 1u, ///< Rising edge. +}en_pwc_edge_sel_t; + +/** + ******************************************************************************* + ** \brief The voltage detect edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdedge_sel +{ + OverVcc = 0u, ///< PVD > VCC. + BelowVcc = 1u, ///< PVD < VCC. +}en_pwc_pvdedge_sel_t; + +/** + ******************************************************************************* + ** \brief The flag of wake_up timer compare result. + ** + ******************************************************************************/ +typedef enum en_pwc_wkover_flag +{ + UnEqual = 0u, ///< Timer value unequal with the wake_up compare value whitch set. + Equal = 1u, ///< Timer value equal with the wake_up compare value whitch set.. +}en_pwc_wkover_flag_t; + +/** + ******************************************************************************* + ** \brief The RAM operating mode. + ** + ******************************************************************************/ +typedef enum en_pwc_ram_op_md +{ + HighSpeedMd = 0x8043, ///< Work at high speed. + UlowSpeedMd = 0x9062, ///< Work at ultra low speed. +}en_pwc_ram_op_md_t; + +/** + ******************************************************************************* + ** \brief The wake up clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_wkclk_sel +{ + Wk64hz = 0u, ///< 64Hz. + WkXtal32 = 1u, ///< Xtal32. + WkLrc = 2u, ///< Lrc. +}en_pwc_wkclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd digital filtering sampling clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdfiltclk_sel +{ + PvdLrc025 = 0u, ///< 0.25 LRC cycle. + PvdLrc05 = 1u, ///< 0.5 LRC cycle. + PvdLrc1 = 2u, ///< LRC 1 div. + PvdLrc2 = 3u, ///< LRC 2 div. +}en_pwc_pvdfiltclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd2 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd2level_sel +{ + Pvd2Level0 = 0u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd2Level1 = 1u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd2Level2 = 2u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd2Level3 = 3u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd2Level4 = 4u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd2Level5 = 5u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd2Level6 = 6u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. + Pvd2Level7 = 7u, ///< 1.1V.while high_speed & ultra_low speed mode, 1.15V.while ultra_high speed mode. +}en_pwc_pvd2level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd1 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd1level_sel +{ + Pvd1Level0 = 0u, ///< 2.0V.while high_speed & ultra_low speed mode, 2.09V.while ultra_high speed mode. + Pvd1Level1 = 1u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd1Level2 = 2u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd1Level3 = 3u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd1Level4 = 4u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd1Level5 = 5u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd1Level6 = 6u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd1Level7 = 7u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. +}en_pwc_pvd1level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd interrupt select. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_int_sel +{ + NonMskInt = 0u, ///< Non-maskable Interrupt. + MskInt = 1u, ///< Maskable Interrupt. +}en_pwc_pvd_int_sel_t; + +/** + ******************************************************************************* + ** \brief The handle of pvd mode. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_md +{ + PvdInt = 0u, ///< The handle of pvd is interrupt. + PvdReset = 1u, ///< The handle of pvd is reset. +}en_pwc_pvd_md_t; + +/** + ******************************************************************************* + ** \brief The unit of pvd detect. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd +{ + PvdU1 = 0u, ///< The uint1 of pvd detect. + PvdU2 = 1u, ///< The unit2 of pvd detect. +}en_pwc_pvd_t; + +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pwr_mode_cfg +{ + en_pwc_powerdown_md_t enPwrDownMd; ///< Power down mode. + en_functional_state_t enRLdo; ///< Enable or disable RLDO. + en_functional_state_t enRetSram; ///< Enable or disable Ret_Sram. + en_pwc_iortn_t enIoRetain; ///< IO retain. + en_pwc_waketime_sel_t enPwrDWkupTm; ///< The power down wake up time select. +}stc_pwc_pwr_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_stop_mode_cfg +{ + en_pwc_stopdas_t enStpDrvAbi; ///< Driver ability while enter stop mode. + en_pwc_stop_flash_sel_t enStopFlash; ///< Flash mode while stop mode awake. + en_pwc_stop_clk_sel_t enStopClk; ///< Clock value while stop mode awake. + en_functional_state_t enPll; ///< Whether the PLL enable or disable while enter stop mode. +}stc_pwc_stop_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up timer control. + ** + ******************************************************************************/ +typedef struct stc_pwc_wktm_ctl +{ + uint16_t u16WktmCmp; ///< The wake_up timer compare value. + en_pwc_wkover_flag_t enWkOverFlag; ///< The flag of compare result. + en_pwc_wkclk_sel_t enWkclk; ///< The clock of wake_up timer. + en_functional_state_t enWktmEn; ///< Enable or disable wake_up timer. +}stc_pwc_wktm_ctl_t; + +/** + ******************************************************************************* + ** \brief The pvd control. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_ctl +{ + en_functional_state_t enPvdIREn; ///< Enable or disable pvd interrupt(reset). + en_pwc_pvd_md_t enPvdMode; ///< The handle of pvd is interrupt or reset. + en_functional_state_t enPvdCmpOutEn; ///< Enable or disable pvd output compare result . +}stc_pwc_pvd_ctl_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up event configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_cfg +{ + stc_pwc_pvd_ctl_t stcPvd1Ctl; ///< Pvd1 control configuration. + stc_pwc_pvd_ctl_t stcPvd2Ctl; ///< Pvd2 control configuration. + en_functional_state_t enPvd1FilterEn; ///< Pvd1 filtering enable or disable. + en_functional_state_t enPvd2FilterEn; ///< Pvd2 filtering enable or disable. + en_pwc_pvdfiltclk_sel_t enPvd1Filtclk; ///< Pvd1 filtering sampling clock. + en_pwc_pvdfiltclk_sel_t enPvd2Filtclk; ///< Pvd2 filtering sampling clock. + en_pwc_pvd1level_sel_t enPvd1Level; ///< Pvd1 voltage. + en_pwc_pvd2level_sel_t enPvd2Level; ///< Pvd2 voltage. + en_pwc_pvd_int_sel_t enPvd1Int; ///< Pvd1 interrupt. + en_pwc_pvd_int_sel_t enPvd2Int; ///< Pvd2 interrupt. +}stc_pwc_pvd_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define PWC_PDWKEN0_WKUP00 ((uint8_t)0x01) +#define PWC_PDWKEN0_WKUP01 ((uint8_t)0x02) +#define PWC_PDWKEN0_WKUP02 ((uint8_t)0x04) +#define PWC_PDWKEN0_WKUP03 ((uint8_t)0x08) +#define PWC_PDWKEN0_WKUP10 ((uint8_t)0x10) +#define PWC_PDWKEN0_WKUP11 ((uint8_t)0x20) +#define PWC_PDWKEN0_WKUP12 ((uint8_t)0x40) +#define PWC_PDWKEN0_WKUP13 ((uint8_t)0x80) + +#define PWC_PDWKEN1_WKUP20 ((uint8_t)0x01) +#define PWC_PDWKEN1_WKUP21 ((uint8_t)0x02) +#define PWC_PDWKEN1_WKUP22 ((uint8_t)0x04) +#define PWC_PDWKEN1_WKUP23 ((uint8_t)0x08) +#define PWC_PDWKEN1_WKUP30 ((uint8_t)0x10) +#define PWC_PDWKEN1_WKUP31 ((uint8_t)0x20) +#define PWC_PDWKEN1_WKUP32 ((uint8_t)0x40) +#define PWC_PDWKEN1_WKUP33 ((uint8_t)0x80) + +#define PWC_PDWKEN2_PVD1 ((uint8_t)0x01) +#define PWC_PDWKEN2_PVD2 ((uint8_t)0x02) +#define PWC_PDWKEN2_NMI ((uint8_t)0x04) +#define PWC_PDWKEN2_RTCPRD ((uint8_t)0x10) +#define PWC_PDWKEN2_RTCAL ((uint8_t)0x20) +#define PWC_PDWKEN2_WKTM ((uint8_t)0x80) + +#define PWC_PDWKUP_EDGE_WKP0 ((uint8_t)0x01) +#define PWC_PDWKUP_EDGE_WKP1 ((uint8_t)0x02) +#define PWC_PDWKUP_EDGE_WKP2 ((uint8_t)0x04) +#define PWC_PDWKUP_EDGE_WKP3 ((uint8_t)0x08) +#define PWC_PDWKUP_EDGE_PVD1 ((uint8_t)0x10) +#define PWC_PDWKUP_EDGE_PVD2 ((uint8_t)0x20) +#define PWC_PDWKUP_EDGE_NMI ((uint8_t)0x40) + +#define PWC_RAMPWRDOWN_SRAM1 ((uint32_t)0x00000001) +#define PWC_RAMPWRDOWN_SRAM2 ((uint32_t)0x00000002) +#define PWC_RAMPWRDOWN_SRAM3 ((uint32_t)0x00000004) +#define PWC_RAMPWRDOWN_SRAMH ((uint32_t)0x00000008) +#define PWC_RAMPWRDOWN_USBFS ((uint32_t)0x00000010) +#define PWC_RAMPWRDOWN_SDIOC0 ((uint32_t)0x00000020) +#define PWC_RAMPWRDOWN_SDIOC1 ((uint32_t)0x00000040) +#define PWC_RAMPWRDOWN_CAN ((uint32_t)0x00000080) +#define PWC_RAMPWRDOWN_CACHE ((uint32_t)0x00000100) +#define PWC_RAMPWRDOWN_FULL ((uint32_t)0x000001FF) + +#define PWC_STOPWKUPEN_EIRQ0 ((uint32_t)0x00000001) +#define PWC_STOPWKUPEN_EIRQ1 ((uint32_t)0x00000002) +#define PWC_STOPWKUPEN_EIRQ2 ((uint32_t)0x00000004) +#define PWC_STOPWKUPEN_EIRQ3 ((uint32_t)0x00000008) +#define PWC_STOPWKUPEN_EIRQ4 ((uint32_t)0x00000010) +#define PWC_STOPWKUPEN_EIRQ5 ((uint32_t)0x00000020) +#define PWC_STOPWKUPEN_EIRQ6 ((uint32_t)0x00000040) +#define PWC_STOPWKUPEN_EIRQ7 ((uint32_t)0x00000080) +#define PWC_STOPWKUPEN_EIRQ8 ((uint32_t)0x00000100) +#define PWC_STOPWKUPEN_EIRQ9 ((uint32_t)0x00000200) +#define PWC_STOPWKUPEN_EIRQ10 ((uint32_t)0x00000400) +#define PWC_STOPWKUPEN_EIRQ11 ((uint32_t)0x00000800) +#define PWC_STOPWKUPEN_EIRQ12 ((uint32_t)0x00001000) +#define PWC_STOPWKUPEN_EIRQ13 ((uint32_t)0x00002000) +#define PWC_STOPWKUPEN_EIRQ14 ((uint32_t)0x00004000) +#define PWC_STOPWKUPEN_EIRQ15 ((uint32_t)0x00008000) +#define PWC_STOPWKUPEN_SWDT ((uint32_t)0x00010000) +#define PWC_STOPWKUPEN_VDU1 ((uint32_t)0x00020000) +#define PWC_STOPWKUPEN_VDU2 ((uint32_t)0x00040000) +#define PWC_STOPWKUPEN_CMPI0 ((uint32_t)0x00080000) +#define PWC_STOPWKUPEN_WKTM ((uint32_t)0x00100000) +#define PWC_STOPWKUPEN_RTCAL ((uint32_t)0x00200000) +#define PWC_STOPWKUPEN_RTCPRD ((uint32_t)0x00400000) +#define PWC_STOPWKUPEN_TMR0 ((uint32_t)0x00800000) +#define PWC_STOPWKUPEN_USARTRXD ((uint32_t)0x02000000) + +#define PWC_PTWK0_WKUPFLAG ((uint8_t)0x01) +#define PWC_PTWK1_WKUPFLAG ((uint8_t)0x02) +#define PWC_PTWK2_WKUPFLAG ((uint8_t)0x04) +#define PWC_PTWK3_WKUPFLAG ((uint8_t)0x08) +#define PWC_PVD1_WKUPFLAG ((uint8_t)0x10) +#define PWC_PVD2_WKUPFLAG ((uint8_t)0x20) +#define PWC_NMI_WKUPFLAG ((uint8_t)0x40) + +#define PWC_RTCPRD_WKUPFALG ((uint8_t)0x10) +#define PWC_RTCAL_WKUPFLAG ((uint8_t)0x20) +#define PWC_WKTM_WKUPFLAG ((uint8_t)0x80) + +#define PWC_WKTMCMP_MSK ((uint16_t)0x0FFF) + +#define PWC_FCG0_PERIPH_SRAMH ((uint32_t)0x00000001) +#define PWC_FCG0_PERIPH_SRAM12 ((uint32_t)0x00000010) +#define PWC_FCG0_PERIPH_SRAM3 ((uint32_t)0x00000100) +#define PWC_FCG0_PERIPH_SRAMRET ((uint32_t)0x00000400) +#define PWC_FCG0_PERIPH_DMA1 ((uint32_t)0x00004000) +#define PWC_FCG0_PERIPH_DMA2 ((uint32_t)0x00008000) +#define PWC_FCG0_PERIPH_FCM ((uint32_t)0x00010000) +#define PWC_FCG0_PERIPH_AOS ((uint32_t)0x00020000) +#define PWC_FCG0_PERIPH_AES ((uint32_t)0x00100000) +#define PWC_FCG0_PERIPH_HASH ((uint32_t)0x00200000) +#define PWC_FCG0_PERIPH_TRNG ((uint32_t)0x00400000) +#define PWC_FCG0_PERIPH_CRC ((uint32_t)0x00800000) +#define PWC_FCG0_PERIPH_DCU1 ((uint32_t)0x01000000) +#define PWC_FCG0_PERIPH_DCU2 ((uint32_t)0x02000000) +#define PWC_FCG0_PERIPH_DCU3 ((uint32_t)0x04000000) +#define PWC_FCG0_PERIPH_DCU4 ((uint32_t)0x08000000) +#define PWC_FCG0_PERIPH_KEY ((uint32_t)0x80000000) + + +#define PWC_FCG1_PERIPH_CAN ((uint32_t)0x00000001) +#define PWC_FCG1_PERIPH_QSPI ((uint32_t)0x00000008) +#define PWC_FCG1_PERIPH_I2C1 ((uint32_t)0x00000010) +#define PWC_FCG1_PERIPH_I2C2 ((uint32_t)0x00000020) +#define PWC_FCG1_PERIPH_I2C3 ((uint32_t)0x00000040) +#define PWC_FCG1_PERIPH_USBFS ((uint32_t)0x00000100) +#define PWC_FCG1_PERIPH_SDIOC1 ((uint32_t)0x00000400) +#define PWC_FCG1_PERIPH_SDIOC2 ((uint32_t)0x00000800) +#define PWC_FCG1_PERIPH_I2S1 ((uint32_t)0x00001000) +#define PWC_FCG1_PERIPH_I2S2 ((uint32_t)0x00002000) +#define PWC_FCG1_PERIPH_I2S3 ((uint32_t)0x00004000) +#define PWC_FCG1_PERIPH_I2S4 ((uint32_t)0x00008000) +#define PWC_FCG1_PERIPH_SPI1 ((uint32_t)0x00010000) +#define PWC_FCG1_PERIPH_SPI2 ((uint32_t)0x00020000) +#define PWC_FCG1_PERIPH_SPI3 ((uint32_t)0x00040000) +#define PWC_FCG1_PERIPH_SPI4 ((uint32_t)0x00080000) +#define PWC_FCG1_PERIPH_USART1 ((uint32_t)0x01000000) +#define PWC_FCG1_PERIPH_USART2 ((uint32_t)0x02000000) +#define PWC_FCG1_PERIPH_USART3 ((uint32_t)0x04000000) +#define PWC_FCG1_PERIPH_USART4 ((uint32_t)0x08000000) + +#define PWC_FCG2_PERIPH_TIM01 ((uint32_t)0x00000001) +#define PWC_FCG2_PERIPH_TIM02 ((uint32_t)0x00000002) +#define PWC_FCG2_PERIPH_TIMA1 ((uint32_t)0x00000004) +#define PWC_FCG2_PERIPH_TIMA2 ((uint32_t)0x00000008) +#define PWC_FCG2_PERIPH_TIMA3 ((uint32_t)0x00000010) +#define PWC_FCG2_PERIPH_TIMA4 ((uint32_t)0x00000020) +#define PWC_FCG2_PERIPH_TIMA5 ((uint32_t)0x00000040) +#define PWC_FCG2_PERIPH_TIMA6 ((uint32_t)0x00000080) +#define PWC_FCG2_PERIPH_TIM41 ((uint32_t)0x00000100) +#define PWC_FCG2_PERIPH_TIM42 ((uint32_t)0x00000200) +#define PWC_FCG2_PERIPH_TIM43 ((uint32_t)0x00000400) +#define PWC_FCG2_PERIPH_EMB ((uint32_t)0x00008000) +#define PWC_FCG2_PERIPH_TIM61 ((uint32_t)0x00010000) +#define PWC_FCG2_PERIPH_TIM62 ((uint32_t)0x00020000) +#define PWC_FCG2_PERIPH_TIM63 ((uint32_t)0x00040000) + +#define PWC_FCG3_PERIPH_ADC1 ((uint32_t)0x00000001) +#define PWC_FCG3_PERIPH_ADC2 ((uint32_t)0x00000002) +#define PWC_FCG3_PERIPH_CMP ((uint32_t)0x00000100) +#define PWC_FCG3_PERIPH_OTS ((uint32_t)0x00001000) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg); +void PWC_EnterPowerDownMd(void); + +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState); +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState); +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge); + +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag); +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag); +void PWC_PwrMonitorCmd(en_functional_state_t enNewState); + +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg); +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); + +void PWC_EnterStopMd(void); +void PWC_EnterSleepMd(void); + +void PWC_Xtal32CsCmd(en_functional_state_t enNewState); +void PWC_HrcPwrCmd(en_functional_state_t enNewState); +void PWC_PllPwrCmd(en_functional_state_t enNewState); +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState); +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd); + +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl); + +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg); +void PWC_Pvd1Cmd(en_functional_state_t enNewState); +void PWC_Pvd2Cmd(en_functional_state_t enNewState); +void PWC_ExVccCmd(en_functional_state_t enNewState); +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd); + +void PWC_enNvicBackup(void); +void PWC_enNvicRecover(void); +void PWC_ClkBackup(void); +void PWC_ClkRecover(void); +void PWC_IrqClkBackup(void); +void PWC_IrqClkRecover(void); + +en_result_t PWC_HS2LS(void); +en_result_t PWC_LS2HS(void); +en_result_t PWC_HS2HP(void); +en_result_t PWC_HP2HS(void); +en_result_t PWC_LS2HP(void); +en_result_t PWC_HP2LS(void); + +//@} // PwcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_PWC_ENABLE */ + +#endif /* __HC32F460_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h new file mode 100644 index 000000000..6bcbf6de0 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h @@ -0,0 +1,402 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.h + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ +#ifndef __HC32F460_QSPI_H__ +#define __HC32F460_QSPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup QspiGroup Queued SPI(QSPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief QSPI spi protocol enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_protocol +{ + QspiProtocolExtendSpi = 0u, ///< Extend spi protocol + QspiProtocolTwoWiresSpi = 1u, ///< Two wires spi protocol + QspiProtocolFourWiresSpi = 2u, ///< Four wires spi protocol +} en_qspi_spi_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI spi Mode enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_mode +{ + QspiSpiMode0 = 0u, ///< Spi mode 0(QSCK normalcy is Low level) + QspiSpiMode3 = 1u, ///< Spi mode 3(QSCK normalcy is High level) +} en_qspi_spi_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI bus communication mode enumeration + ******************************************************************************/ +typedef enum en_qspi_bus_mode +{ + QspiBusModeRomAccess = 0u, ///< Rom access mode + QspiBusModeDirectAccess = 1u, ///< Direct communication mode +} en_qspi_bus_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI prefetch data stop config enumeration + ******************************************************************************/ +typedef enum en_qspi_prefetch_config +{ + QspiPrefetchStopComplete = 0u, ///< Stop after prefetch data complete + QspiPrefetchStopImmediately = 1u, ///< Immediately stop prefetch +} en_qspi_prefetch_config_t; + +/** + ******************************************************************************* + ** \brief QSPI read mode enumeration + ******************************************************************************/ +typedef enum en_qspi_read_mode +{ + QspiReadModeStandard = 0u, ///< Standard read + QspiReadModeFast = 1u, ///< Fast read + QspiReadModeTwoWiresOutput = 2u, ///< Two wires output fast read + QspiReadModeTwoWiresIO = 3u, ///< Two wires input/output fast read + QspiReadModeFourWiresOutput = 4u, ///< Four wires output fast read + QspiReadModeFourWiresIO = 5u, ///< Four wires input/output fast read + QspiReadModeCustomStandard = 6u, ///< Custom standard read + QspiReadModeCustomFast = 7u, ///< Custom fast read +} en_qspi_read_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN valid extend time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_valid_extend_time +{ + QspiQssnValidExtendNot = 0u, ///< Don't extend QSSN valid time + QspiQssnValidExtendSck32 = 1u, ///< QSSN valid time extend 32 QSCK cycles + QspiQssnValidExtendSck128 = 2u, ///< QSSN valid time extend 138 QSCK cycles + QspiQssnValidExtendSckEver = 3u, ///< QSSN valid time extend to ever +} en_qspi_qssn_valid_extend_time_t; + +/** + ******************************************************************************* + ** \brief QSPI QSCK duty cycle correction enumeration + ******************************************************************************/ +typedef enum en_qspi_qsck_duty_correction +{ + QspiQsckDutyCorrNot = 0u, ///< Don't correction duty cycle + QspiQsckDutyCorrHalfHclk = 1u, ///< QSCK's rising edge delay 0.5 HCLK cycle when Qsck select HCLK is odd +} en_qspi_qsck_duty_correction_t; + +/** + ******************************************************************************* + ** \brief QSPI WP Pin output level enumeration + ******************************************************************************/ +typedef enum en_qspi_wp_pin_level +{ + QspiWpPinOutputLow = 0u, ///< WP pin(QIO2) output low level + QspiWpPinOutputHigh = 1u, ///< WP pin(QIO2) output high level +} en_qspi_wp_pin_level_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN setup delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_setup_delay +{ + QspiQssnSetupDelayHalfQsck = 0u, ///< QSSN setup delay 0.5 QSCK output than QSCK first rising edge + QspiQssnSetupDelay1Dot5Qsck = 1u, ///< QSSN setup delay 1.5 QSCK output than QSCK first rising edge +} en_qspi_qssn_setup_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN hold delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_hold_delay +{ + QspiQssnHoldDelayHalfQsck = 0u, ///< QSSN hold delay 0.5 QSCK release than QSCK last rising edge + QspiQssnHoldDelay1Dot5Qsck = 1u, ///< QSSN hold delay 1.5 QSCK release than QSCK last rising edge +} en_qspi_qssn_hold_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI address width enumeration + ******************************************************************************/ +typedef enum en_qspi_addr_width +{ + QspiAddressByteOne = 0u, ///< One byte address + QspiAddressByteTwo = 1u, ///< Two byte address + QspiAddressByteThree = 2u, ///< Three byte address + QspiAddressByteFour = 3u, ///< Four byte address +} en_qspi_addr_width_t; + +/** + ******************************************************************************* + ** \brief QSPI flag type enumeration + ******************************************************************************/ +typedef enum en_qspi_flag_type +{ + QspiFlagBusBusy = 0u, ///< QSPI bus work status flag in direct communication mode + QspiFlagXipMode = 1u, ///< XIP mode status signal + QspiFlagRomAccessError = 2u, ///< Trigger rom access error flag in direct communication mode + QspiFlagPrefetchBufferFull = 3u, ///< Prefetch buffer area status signal + QspiFlagPrefetchStop = 4u, ///< Prefetch action status signal +} en_qspi_flag_type_t; + +/** + ******************************************************************************* + ** \brief QSPI clock division enumeration + ******************************************************************************/ +typedef enum en_qspi_clk_div +{ + QspiHclkDiv2 = 0u, ///< Clock source: HCLK/2 + QspiHclkDiv3 = 2u, ///< Clock source: HCLK/3 + QspiHclkDiv4 = 3u, ///< Clock source: HCLK/4 + QspiHclkDiv5 = 4u, ///< Clock source: HCLK/5 + QspiHclkDiv6 = 5u, ///< Clock source: HCLK/6 + QspiHclkDiv7 = 6u, ///< Clock source: HCLK/7 + QspiHclkDiv8 = 7u, ///< Clock source: HCLK/8 + QspiHclkDiv9 = 8u, ///< Clock source: HCLK/9 + QspiHclkDiv10 = 9u, ///< Clock source: HCLK/10 + QspiHclkDiv11 = 10u, ///< Clock source: HCLK/11 + QspiHclkDiv12 = 11u, ///< Clock source: HCLK/12 + QspiHclkDiv13 = 12u, ///< Clock source: HCLK/13 + QspiHclkDiv14 = 13u, ///< Clock source: HCLK/14 + QspiHclkDiv15 = 14u, ///< Clock source: HCLK/15 + QspiHclkDiv16 = 15u, ///< Clock source: HCLK/16 + QspiHclkDiv17 = 16u, ///< Clock source: HCLK/17 + QspiHclkDiv18 = 17u, ///< Clock source: HCLK/18 + QspiHclkDiv19 = 18u, ///< Clock source: HCLK/19 + QspiHclkDiv20 = 19u, ///< Clock source: HCLK/20 + QspiHclkDiv21 = 20u, ///< Clock source: HCLK/21 + QspiHclkDiv22 = 21u, ///< Clock source: HCLK/22 + QspiHclkDiv23 = 22u, ///< Clock source: HCLK/23 + QspiHclkDiv24 = 23u, ///< Clock source: HCLK/24 + QspiHclkDiv25 = 24u, ///< Clock source: HCLK/25 + QspiHclkDiv26 = 25u, ///< Clock source: HCLK/26 + QspiHclkDiv27 = 26u, ///< Clock source: HCLK/27 + QspiHclkDiv28 = 27u, ///< Clock source: HCLK/28 + QspiHclkDiv29 = 28u, ///< Clock source: HCLK/29 + QspiHclkDiv30 = 29u, ///< Clock source: HCLK/30 + QspiHclkDiv31 = 30u, ///< Clock source: HCLK/31 + QspiHclkDiv32 = 31u, ///< Clock source: HCLK/32 + QspiHclkDiv33 = 32u, ///< Clock source: HCLK/33 + QspiHclkDiv34 = 33u, ///< Clock source: HCLK/34 + QspiHclkDiv35 = 34u, ///< Clock source: HCLK/35 + QspiHclkDiv36 = 35u, ///< Clock source: HCLK/36 + QspiHclkDiv37 = 36u, ///< Clock source: HCLK/37 + QspiHclkDiv38 = 37u, ///< Clock source: HCLK/38 + QspiHclkDiv39 = 38u, ///< Clock source: HCLK/39 + QspiHclkDiv40 = 39u, ///< Clock source: HCLK/40 + QspiHclkDiv41 = 40u, ///< Clock source: HCLK/41 + QspiHclkDiv42 = 41u, ///< Clock source: HCLK/42 + QspiHclkDiv43 = 42u, ///< Clock source: HCLK/43 + QspiHclkDiv44 = 43u, ///< Clock source: HCLK/44 + QspiHclkDiv45 = 44u, ///< Clock source: HCLK/45 + QspiHclkDiv46 = 45u, ///< Clock source: HCLK/46 + QspiHclkDiv47 = 46u, ///< Clock source: HCLK/47 + QspiHclkDiv48 = 47u, ///< Clock source: HCLK/48 + QspiHclkDiv49 = 48u, ///< Clock source: HCLK/49 + QspiHclkDiv50 = 49u, ///< Clock source: HCLK/50 + QspiHclkDiv51 = 50u, ///< Clock source: HCLK/51 + QspiHclkDiv52 = 51u, ///< Clock source: HCLK/52 + QspiHclkDiv53 = 52u, ///< Clock source: HCLK/53 + QspiHclkDiv54 = 53u, ///< Clock source: HCLK/54 + QspiHclkDiv55 = 54u, ///< Clock source: HCLK/55 + QspiHclkDiv56 = 55u, ///< Clock source: HCLK/56 + QspiHclkDiv57 = 56u, ///< Clock source: HCLK/57 + QspiHclkDiv58 = 57u, ///< Clock source: HCLK/58 + QspiHclkDiv59 = 58u, ///< Clock source: HCLK/59 + QspiHclkDiv60 = 59u, ///< Clock source: HCLK/60 + QspiHclkDiv61 = 60u, ///< Clock source: HCLK/61 + QspiHclkDiv62 = 61u, ///< Clock source: HCLK/62 + QspiHclkDiv63 = 62u, ///< Clock source: HCLK/63 + QspiHclkDiv64 = 63u, ///< Clock source: HCLK/64 +} en_qspi_clk_div_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN minimum interval time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_interval_time +{ + QspiQssnIntervalQsck1 = 0u, ///< QSSN signal min interval time 1 QSCK + QspiQssnIntervalQsck2 = 1u, ///< QSSN signal min interval time 2 QSCK + QspiQssnIntervalQsck3 = 2u, ///< QSSN signal min interval time 3 QSCK + QspiQssnIntervalQsck4 = 3u, ///< QSSN signal min interval time 4 QSCK + QspiQssnIntervalQsck5 = 4u, ///< QSSN signal min interval time 5 QSCK + QspiQssnIntervalQsck6 = 5u, ///< QSSN signal min interval time 6 QSCK + QspiQssnIntervalQsck7 = 6u, ///< QSSN signal min interval time 7 QSCK + QspiQssnIntervalQsck8 = 7u, ///< QSSN signal min interval time 8 QSCK + QspiQssnIntervalQsck9 = 8u, ///< QSSN signal min interval time 9 QSCK + QspiQssnIntervalQsck10 = 9u, ///< QSSN signal min interval time 10 QSCK + QspiQssnIntervalQsck11 = 10u, ///< QSSN signal min interval time 11 QSCK + QspiQssnIntervalQsck12 = 11u, ///< QSSN signal min interval time 12 QSCK + QspiQssnIntervalQsck13 = 12u, ///< QSSN signal min interval time 13 QSCK + QspiQssnIntervalQsck14 = 13u, ///< QSSN signal min interval time 14 QSCK + QspiQssnIntervalQsck15 = 14u, ///< QSSN signal min interval time 15 QSCK + QspiQssnIntervalQsck16 = 15u, ///< QSSN signal min interval time 16 QSCK +} en_qspi_qssn_interval_time_t; + +/** + ******************************************************************************* + ** \brief QSPI virtual period enumeration + ******************************************************************************/ +typedef enum en_qspi_virtual_period +{ + QspiVirtualPeriodQsck3 = 0u, ///< Virtual period select 3 QSCK + QspiVirtualPeriodQsck4 = 1u, ///< Virtual period select 4 QSCK + QspiVirtualPeriodQsck5 = 2u, ///< Virtual period select 5 QSCK + QspiVirtualPeriodQsck6 = 3u, ///< Virtual period select 6 QSCK + QspiVirtualPeriodQsck7 = 4u, ///< Virtual period select 7 QSCK + QspiVirtualPeriodQsck8 = 5u, ///< Virtual period select 8 QSCK + QspiVirtualPeriodQsck9 = 6u, ///< Virtual period select 9 QSCK + QspiVirtualPeriodQsck10 = 7u, ///< Virtual period select 10 QSCK + QspiVirtualPeriodQsck11 = 8u, ///< Virtual period select 11 QSCK + QspiVirtualPeriodQsck12 = 9u, ///< Virtual period select 12 QSCK + QspiVirtualPeriodQsck13 = 10u, ///< Virtual period select 13 QSCK + QspiVirtualPeriodQsck14 = 11u, ///< Virtual period select 14 QSCK + QspiVirtualPeriodQsck15 = 12u, ///< Virtual period select 15 QSCK + QspiVirtualPeriodQsck16 = 13u, ///< Virtual period select 16 QSCK + QspiVirtualPeriodQsck17 = 14u, ///< Virtual period select 17 QSCK + QspiVirtualPeriodQsck18 = 15u, ///< Virtual period select 18 QSCK +} en_qspi_virtual_period_t; + +/** + ******************************************************************************* + ** \brief QSPI communication protocol structure definition + ******************************************************************************/ +typedef struct stc_qspi_comm_protocol +{ + en_qspi_spi_protocol_t enReceProtocol; ///< Receive data stage SPI protocol + en_qspi_spi_protocol_t enTransAddrProtocol; ///< Transmit address stage SPI protocol + en_qspi_spi_protocol_t enTransInstrProtocol; ///< Transmit instruction stage SPI protocol + en_qspi_read_mode_t enReadMode; ///< Serial interface read mode +} stc_qspi_comm_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI init structure definition + ******************************************************************************/ +typedef struct stc_qspi_init +{ + en_qspi_clk_div_t enClkDiv; ///< Clock division + en_qspi_spi_mode_t enSpiMode; ///< Specifies SPI mode + en_qspi_bus_mode_t enBusCommMode; ///< Bus communication mode + en_qspi_prefetch_config_t enPrefetchMode; ///< Config prefetch stop location + en_functional_state_t enPrefetchFuncEn; ///< Disable: disable prefetch function, Enable: enable prefetch function + stc_qspi_comm_protocol_t stcCommProtocol; ///< Qspi communication protocol config + en_qspi_qssn_valid_extend_time_t enQssnValidExtendTime; ///< QSSN valid extend time function select after QSPI access bus + en_qspi_qssn_interval_time_t enQssnIntervalTime; ///< QSSN minimum interval time + en_qspi_qsck_duty_correction_t enQsckDutyCorr; ///< QSCK output duty cycles correction + en_qspi_virtual_period_t enVirtualPeriod; ///< Virtual period config + en_qspi_wp_pin_level_t enWpPinLevel; ///< WP pin(QIO2) level select + en_qspi_qssn_setup_delay_t enQssnSetupDelayTime; ///< QSSN setup delay time choose + en_qspi_qssn_hold_delay_t enQssnHoldDelayTime; ///< QSSN hold delay time choose + en_functional_state_t enFourByteAddrReadEn; ///< Read instruction code select when set address width is four bytes + en_qspi_addr_width_t enAddrWidth; ///< Serial interface address width choose + uint8_t u8RomAccessInstr; ///< Rom access mode instruction +} stc_qspi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< 4-byte instruction mode using instruction set */ +#define QSPI_4BINSTR_STANDARD_READ 0x13u +#define QSPI_4BINSTR_FAST_READ 0x0Cu +#define QSPI_4BINSTR_TWO_WIRES_OUTPUT_READ 0x3Cu +#define QSPI_4BINSTR_TWO_WIRES_IO_READ 0xBCu +#define QSPI_4BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Cu +#define QSPI_4BINSTR_FOUR_WIRES_IO_READ 0xECu +#define QSPI_4BINSTR_EXIT_4BINSTR_MODE 0xB7u + +/*!< 3-byte instruction mode using instruction set */ +#define QSPI_3BINSTR_STANDARD_READ 0x03u +#define QSPI_3BINSTR_FAST_READ 0x0Bu +#define QSPI_3BINSTR_TWO_WIRES_OUTPUT_READ 0x3Bu +#define QSPI_3BINSTR_TWO_WIRES_IO_READ 0xBBu +#define QSPI_3BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Bu +#define QSPI_3BINSTR_FOUR_WIRES_IO_READ 0xEBu +#define QSPI_3BINSTR_ENTER_4BINSTR_MODE 0xE9u + +/*!< General instruction set */ +#define QSPI_WRITE_MODE_ENABLE 0x06u + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t QSPI_DeInit(void); +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg); +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth); +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr); +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol); +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta); +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv); +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel); + +/* Rom access mode functions */ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr); +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta); + +/* Direct communication mode functions */ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val); +uint8_t QSPI_ReadDirectCommValue(void); +en_result_t QSPI_EnterDirectCommMode(void); +en_result_t QSPI_ExitDirectCommMode(void); + +/* Flags and get buffer functions */ +uint8_t QSPI_GetPrefetchBufferNum(void); +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag); +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag); + +//@} // QspiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_QSPI_ENABLE */ + +#endif /* __HC32F460_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h new file mode 100644 index 000000000..1217490bf --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h @@ -0,0 +1,96 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.h + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU + ** + ******************************************************************************/ +#ifndef __HC32F460_RMU_H__ +#define __HC32F460_RMU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_RMU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RmuGroup Reset Management Unit(RMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief system reset cause flag + ** + ******************************************************************************/ +typedef struct stc_rmu_rstcause +{ + en_flag_status_t enMultiRst; ///< Multiply reset cause + en_flag_status_t enXtalErr; ///< Xtal error reset + en_flag_status_t enClkFreqErr; ///< Clk freqence error reset + en_flag_status_t enRamEcc; ///< Ram ECC reset + en_flag_status_t enRamParityErr; ///< Ram parity error reset + en_flag_status_t enMpuErr; ///< Mpu error reset + en_flag_status_t enSoftware; ///< Software reset + en_flag_status_t enPowerDown; ///< Power down reset + en_flag_status_t enSwdt; ///< Special watchdog timer reset + en_flag_status_t enWdt; ///< Watchdog timer reset + en_flag_status_t enPvd2; ///< Program voltage Dectection 2 reset + en_flag_status_t enPvd1; ///< Program voltage Dectection 1 reset + en_flag_status_t enBrownOut; ///< Brown out reset + en_flag_status_t enRstPin; ///< Reset pin reset + en_flag_status_t enPowerOn; ///< Power on reset +}stc_rmu_rstcause_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData); +en_result_t RMU_ClrResetFlag(void); + +//@} // RmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_RMU_ENABLE */ + +#endif /* __HC32F460_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h new file mode 100644 index 000000000..31544f03f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h @@ -0,0 +1,274 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.h + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ +#ifndef __HC32F460_RTC_H__ +#define __HC32F460_RTC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_RTC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RtcGroup Real-Time Clock(RTC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief RTC period interrupt type enumeration + ******************************************************************************/ +typedef enum en_rtc_period_int_type +{ + RtcPeriodIntInvalid = 0u, ///< Period interrupt invalid + RtcPeriodIntHalfSec = 1u, ///< 0.5 second period interrupt + RtcPeriodIntOneSec = 2u, ///< 1 second period interrupt + RtcPeriodIntOneMin = 3u, ///< 1 minute period interrupt + RtcPeriodIntOneHour = 4u, ///< 1 hour period interrupt + RtcPeriodIntOneDay = 5u, ///< 1 day period interrupt + RtcPeriodIntOneMon = 6u ///< 1 month period interrupt +} en_rtc_period_int_type_t; + +/** + ******************************************************************************* + ** \brief RTC time format enumeration + ******************************************************************************/ +typedef enum en_rtc_time_format +{ + RtcTimeFormat12Hour = 0u, ///< 12 hours mode + RtcTimeFormat24Hour = 1u, ///< 24 hours mode +} en_rtc_time_format_t; + +/** + ******************************************************************************* + ** \brief RTC 1Hz output compensation way enumeration + ******************************************************************************/ +typedef enum en_rtc_output_compen +{ + RtcOutputCompenDistributed = 0u, ///< Distributed compensation 1hz output + RtcOutputCompenUniform = 1u, ///< Uniform Compensation 1hz output +} en_rtc_output_compen_t; + +/** + ******************************************************************************* + ** \brief RTC work mode enumeration + ******************************************************************************/ +typedef enum en_rtc_work_mode +{ + RtcModeNormalCount = 0u, ///< Normal count mode + RtcModeReadOrWrite = 1u, ///< Read or write mode +} en_rtc_work_mode_t; + +/** + ******************************************************************************* + ** \brief RTC count clock source enumeration + ******************************************************************************/ +typedef enum en_rtc_clk_source +{ + RtcClkXtal32 = 0u, ///< XTAL32 as clock source + RtcClkLrc = 1u, ///< LRC as clock source +} en_rtc_clk_source_t; + +/** + ******************************************************************************* + ** \brief RTC data format enumeration + ******************************************************************************/ +typedef enum en_rtc_data_format +{ + RtcDataFormatDec = 0u, ///< Decimal format + RtcDataFormatBcd = 1u, ///< BCD format +} en_rtc_data_format_t; + +/** + ******************************************************************************* + ** \brief RTC 12 hour AM/PM enumeration + ******************************************************************************/ +typedef enum en_rtc_hour12_ampm +{ + RtcHour12Am = 0u, ///< Ante meridiem + RtcHour12Pm = 1u, ///< Post meridiem +} en_rtc_hour12_ampm_t; + +/** + ******************************************************************************* + ** \brief RTC month enumeration + ******************************************************************************/ +typedef enum en_rtc_month +{ + RtcMonthJanuary = 1u, ///< January + RtcMonthFebruary = 2u, ///< February + RtcMonthMarch = 3u, ///< March + RtcMonthApril = 4u, ///< April + RtcMonthMay = 5u, ///< May + RtcMonthJune = 6u, ///< June + RtcMonthJuly = 7u, ///< July + RtcMonthAugust = 8u, ///< August + RtcMonthSeptember = 9u, ///< September + RtcMonthOctober = 10u, ///< October + RtcMonthNovember = 11u, ///< November + RtcMonthDecember = 12u, ///< December +} en_rtc_month_t; + +/** + ******************************************************************************* + ** \brief RTC weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_weekday +{ + RtcWeekdaySunday = 0u, ///< Sunday + RtcWeekdayMonday = 1u, ///< Monday + RtcWeekdayTuesday = 2u, ///< Tuesday + RtcWeekdayWednesday = 3u, ///< Wednesday + RtcWeekdayThursday = 4u, ///< Thursday + RtcWeekdayFriday = 5u, ///< Friday + RtcWeekdaySaturday = 6u ///< Saturday +} en_rtc_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC alarm weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_alarm_weekday +{ + RtcAlarmWeekdaySunday = 0x01u, ///< Sunday + RtcAlarmWeekdayMonday = 0x02u, ///< Monday + RtcAlarmWeekdayTuesday = 0x04u, ///< Tuesday + RtcAlarmWeekdayWednesday = 0x08u, ///< Wednesday + RtcAlarmWeekdayThursday = 0x10u, ///< Thursday + RtcAlarmWeekdayFriday = 0x20u, ///< Friday + RtcAlarmWeekdaySaturday = 0x40u, ///< Saturday +} en_rtc_alarm_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC interrupt request type enumeration + ******************************************************************************/ +typedef enum en_rtc_irq_type_ +{ + RtcIrqPeriod = 0u, ///< Period count interrupt request + RtcIrqAlarm = 1u, ///< Alarm interrupt request +} en_rtc_irq_type_t; + +/** + ******************************************************************************* + ** \brief RTC date and time structure definition + ******************************************************************************/ +typedef struct stc_rtc_date_time +{ + uint8_t u8Year; ///< Year (range 0-99) + uint8_t u8Month; ///< Month (range 1-12) + uint8_t u8Day; ///< Day (range 1-31) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Second; ///< Seconds (range 0-59) + uint8_t u8Weekday; ///< Weekday (range 0-6) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_date_time_t; + +/** + ******************************************************************************* + ** \brief RTC alarm time structure definition + ******************************************************************************/ +typedef struct stc_rtc_alarm_time +{ + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Weekday; ///< Weekday (range RtcAlarmWeekdaySunday to RtcAlarmWeekdaySaturday) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_alarm_time_t; + +/** + ******************************************************************************* + ** \brief RTC init structure definition + ******************************************************************************/ +typedef struct stc_rtc_init +{ + en_rtc_clk_source_t enClkSource; ///< Clock source + en_rtc_period_int_type_t enPeriodInt; ///< Period interrupt condition + en_rtc_time_format_t enTimeFormat; ///< RTC time format + en_rtc_output_compen_t enCompenWay; ///< 1HZ output compensation way + uint16_t u16CompenVal; ///< Clock error compensation value + en_functional_state_t enCompenEn; ///< Enable/Disable clock error compensation +} stc_rtc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t RTC_DeInit(void); +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +en_result_t RTC_Cmd(en_functional_state_t enNewSta); +en_result_t RTC_EnterRwMode(void); +en_result_t RTC_ExitRwMode(void); + +/* Extend functions */ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType); +en_result_t RTC_LowPowerSwitch(void); +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal); +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta); +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta); + +/* Date and time functions */ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn); +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime); + +/* Alarm functions */ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta); + +/* Interrupt and flags management functions ******************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta); +en_flag_status_t RTC_GetAlarmFlag(void); +en_result_t RTC_ClearAlarmFlag(void); + +//@} // RtcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_RTC_ENABLE */ + +#endif /* __HC32F460_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h new file mode 100644 index 000000000..2fd546a97 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h @@ -0,0 +1,559 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.h + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ +#ifndef __HC32F460_SDIOC_H__ +#define __HC32F460_SDIOC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SDIOC mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_mode +{ + SdiocModeSD = 0u, ///< The SD mode + SdiocModeMMC = 1u, ///< The MMC mode +} en_sdioc_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC transfer bus width enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_bus_width +{ + SdiocBusWidth4Bit = 0u, ///< The SDIOC bus width 4 bit + SdiocBusWidth8Bit = 1u, ///< The SDIOC bus width 8 bit + SdiocBusWidth1Bit = 2u, ///< The SDIOC bus width 1 bit +} en_sdioc_bus_width_t; + +/** + ******************************************************************************* + ** \brief SDIOC clock division enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_div +{ + SdiocClkDiv_1 = 0x00u, ///< EXCLK/1 + SdiocClkDiv_2 = 0x01u, ///< EXCLK/2 + SdiocClkDiv_4 = 0x02u, ///< EXCLK/4 + SdiocClkDiv_8 = 0x04u, ///< EXCLK/8 + SdiocClkDiv_16 = 0x08u, ///< EXCLK/16 + SdiocClkDiv_32 = 0x10u, ///< EXCLK/32 + SdiocClkDiv_64 = 0x20u, ///< EXCLK/64 + SdiocClkDiv_128 = 0x40u, ///< EXCLK/128 + SdiocClkDiv_256 = 0x80u, ///< EXCLK/256 +} en_sdioc_clk_div_t; + +/** + ******************************************************************************* + ** \brief SDIOC response type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_type +{ + SdiocResponseNoneBit = 0u, ///< No Response + SdiocResponse136Bit = 1u, ///< Response Length 136 + SdiocResponse48Bit = 2u, ///< Response Length 48 + SdiocResponse48BitCheckBusy = 3u, ///< Response Length 48 check Busy after response +} en_sdioc_response_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC response index enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_index +{ + SdiocCmdNoRsp = 0u, ///< No Response + SdiocCmdRspR1 = 1u, ///< Command Response 1 + SdiocCmdRspR1b = 2u, ///< Command Response 1 with busy + SdiocCmdRspR2 = 3u, ///< Command Response 2 + SdiocCmdRspR3 = 4u, ///< Command Response 3 + SdiocCmdRspR4 = 5u, ///< Command Response 4 + SdiocCmdRspR5 = 6u, ///< Command Response 5 + SdiocCmdRspR5b = 7u, ///< Command Response 5 with busy + SdiocCmdRspR6 = 8u, ///< Command Response 6 + SdiocCmdRspR7 = 9u, ///< Command Response 7 +} en_sdioc_response_index_t; + +/** + ******************************************************************************* + ** \brief SDIOC command type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_cmd_type +{ + SdiocCmdNormal = 0u, ///< Other commands + SdiocCmdSuspend = 1u, ///< CMD52 for writing "Bus Suspend" in CCCR + SdiocCmdResume = 2u, ///< CMD52 for writing "Function Select" in CCCR + SdiocCmdAbort = 3u, ///< CMD12, CMD52 for writing "I/O Abort" in CCCR +} en_sdioc_cmd_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_dir +{ + SdiocTransferToCard = 0u, ///< Write (Host to Card) + SdiocTransferToHost = 1u, ///< Read (Card to Host) +} en_sdioc_transfer_dir_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_mode +{ + SdiocTransferSingle = 0u, ///< Single Block transfer + SdiocTransferInfinite = 1u, ///< Infinite Block transfer + SdiocTransferMultiple = 2u, ///< Multiple Block transfer + SdiocTransferStopMultiple = 3u, ///< Stop Multiple Block transfer +} en_sdioc_transfer_mode_t; + +/** + ******************************************************************************* + ** \brief SD data timeout time enumeration + ** + ******************************************************************************/ +typedef enum en_sd_data_timeout +{ + SdiocDtoSdclk_2_13 = 0u, ///< Timeout time: SDCLK*2^13 + SdiocDtoSdclk_2_14 = 1u, ///< Timeout time: SDCLK*2^14 + SdiocDtoSdclk_2_15 = 2u, ///< Timeout time: SDCLK*2^15 + SdiocDtoSdclk_2_16 = 3u, ///< Timeout time: SDCLK*2^16 + SdiocDtoSdclk_2_17 = 4u, ///< Timeout time: SDCLK*2^17 + SdiocDtoSdclk_2_18 = 5u, ///< Timeout time: SDCLK*2^18 + SdiocDtoSdclk_2_19 = 6u, ///< Timeout time: SDCLK*2^19 + SdiocDtoSdclk_2_20 = 7u, ///< Timeout time: SDCLK*2^20 + SdiocDtoSdclk_2_21 = 8u, ///< Timeout time: SDCLK*2^21 + SdiocDtoSdclk_2_22 = 9u, ///< Timeout time: SDCLK*2^22 + SdiocDtoSdclk_2_23 = 10u, ///< Timeout time: SDCLK*2^23 + SdiocDtoSdclk_2_24 = 11u, ///< Timeout time: SDCLK*2^24 + SdiocDtoSdclk_2_25 = 12u, ///< Timeout time: SDCLK*2^25 + SdiocDtoSdclk_2_26 = 13u, ///< Timeout time: SDCLK*2^26 + SdiocDtoSdclk_2_27 = 14u, ///< Timeout time: SDCLK*2^27 +} en_sdioc_data_timeout_t; + +/** + ******************************************************************************* + ** \brief SDIOC dat line type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_dat_line_type +{ + SdiocDat0Line = 0u, ///< DAT0 Line + SdiocDat1Line = 1u, ///< DAT1 Line + SdiocDat2Line = 2u, ///< DAT2 Line + SdiocDat3Line = 3u, ///< DAT3 Line +} en_sdioc_dat_line_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC software reset type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_sw_reset +{ + SdiocSwResetDatLine = 0u, ///< Only part of data circuit is reset. + SdiocSwResetCmdLine = 1u, ///< Only part of command circuit is reset. + SdiocSwResetAll = 2u, ///< Reset the entire Host Controller except for the card detection circuit. +} en_sdioc_sw_reset_t; + +/** + ******************************************************************************* + ** \brief SDIOC host status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_host_status +{ + SdiocCommandInhibitCmd = (1u << 0), ///< Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + SdiocCommandInhibitData = (1u << 1), ///< Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + SdiocDataLineActive = (1u << 2), ///< 1: DAT Line Active; 0: DAT Line Inactive + SdiocWriteTransferActive = (1u << 8), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocReadTransferActive = (1u << 9), ///< Read Transfer Active.1: Transferring data; 0: No valid data + SdiocBufferWriteEnble = (1u << 10), ///< 1: Write enable; 0: Write Disable + SdiocBufferReadEnble = (1u << 11), ///< 1: Read enable; 0: Read Disable + SdiocCardInserted = (1u << 16), ///< 1: Card Inserted; 0: Reset or Debouncing or No Card + SdiocCardStateStable = (1u << 17), ///< 1: No Card or Inserted; 0: Reset or Debouncing + SdiocCardDetectPinLvl = (1u << 18), ///< 1: Card present; 0: No card present + SdiocWriteProtectPinLvl = (1u << 19), ///< 1: Write enabled; 0: Write protected + SdiocData0PinLvl = (1u << 20), ///< 1: DAT0 line signal level high; 0: DAT0 line signal level low + SdiocData1PinLvl = (1u << 21), ///< 1: DAT1 line signal level high; 0: DAT1 line signal level low + SdiocData2PinLvl = (1u << 22), ///< 1: DAT2 line signal level high; 0: DAT2 line signal level low + SdiocData3PinLvl = (1u << 23), ///< 1: DAT3 line signal level high; 0: DAT3 line signal level low + SdiocCmdPinLvl = (1u << 24), ///< 1: CMD line signal level high; 0: CMD line signal level low +} en_sdioc_host_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_nor_int_sel +{ + SdiocCommandComplete = (1u << 0), ///< Command Complete. 1: Command complete; 0:No command complete + SdiocTransferComplete = (1u << 1), ///< Transfer Complete. 1: Data transfer complete; 0:No transfer complete + SdiocBlockGapEvent = (1u << 2), ///< Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + SdiocBufferWriteReady = (1u << 4), ///< Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + SdiocBufferReadReady = (1u << 5), ///< Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + SdiocCardInsertedInt = (1u << 6), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocCardRemoval = (1u << 7), ///< Card Removal. 1: Card removed; 0: Card state stable or Debouncing + SdiocCardInt = (1u << 8), ///< Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + SdiocErrorInt = (1u << 15), ///< Error Interrupt. 1: Error; 0: No Error +} en_sdioc_nor_int_sel_t, en_sdioc_nor_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC error interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_err_int_sel +{ + SdiocCmdTimeoutErr = (1u << 0), ///< Command Timeout Error. 1: Timer out; 0:No Error + SdiocCmdCrcErr = (1u << 1), ///< Command CRC Error. 1: Command CRC Error Generated; 0:No Error + SdiocCmdEndBitErr = (1u << 2), ///< Command End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocCmdIndexErr = (1u << 3), ///< Command Index Error. 1: Command Index Error Generatedr; 0:No Error + SdiocDataTimeoutErr = (1u << 4), ///< Data Timeout Error. 1: Timer out; 0:No Error + SdiocDataCrcErr = (1u << 5), ///< Data CRC Error. 1: Data CRC Error Generated; 0:No Error + SdiocDataEndBitErr = (1u << 6), ///< Data End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocAutoCmd12Err = (1u << 8), ///< Auto CMD12 Error. 1: Error; 0:No Error +} en_sdioc_err_int_sel_t, en_sdioc_err_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC auto CMD12 error status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_atuo_cmd_err_status +{ + SdiocAutoCmd12NotExecuted = (1u << 0), ///< Auto CMD12 Not Executed. 1: Not executed; 0:Executed + SdiocAutoCmd12Timeout = (1u << 1), ///< Auto CMD12 Timeout Error. 1: Time out; 0:No error + SdiocAutoCmd12CrcErr = (1u << 2), ///< Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + SdiocAutoCmd12EndBitErr = (1u << 3), ///< Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + SdiocAutoCmd12IndexErr = (1u << 4), ///< Auto CMD12 Index Error. 1: Error; 0: No error + SdiocCmdNotIssuedErr = (1u << 7), ///< Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error +} en_sdioc_atuo_cmd_err_sel_t, en_sdioc_atuo_cmd_err_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC speed mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_speed_mode +{ + SdiocNormalSpeedMode = 0u, ///< Normal speed mode + SdiocHighSpeedMode = 1u, ///< High speed mode +} en_sdioc_speed_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC response register enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_reg +{ + SdiocRegResp01 = 0x00u, ///< Response 0/1 Register + SdiocRegResp23 = 0x04u, ///< Response 2/3 Register + SdiocRegResp45 = 0x08u, ///< Response 4/5 Register + SdiocRegResp67 = 0x0Cu, ///< Response 5/6 Register +} en_sdioc_response_reg_t; + +/** + ****************************************************************************** + ** \brief SDIOC output clock frequency enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_freq +{ + SdiocClk400K = 400000u, ///< SDIOC clock: 40KHz + SdiocClk20M = 20000000u, ///< SDIOC clock: 20MHz + SdiocClk25M = 25000000u, ///< SDIOC clock: 25MHz + SdiocClk40M = 40000000u, ///< SDIOC clock: 40MHz + SdiocClk50M = 50000000u, ///< SDIOC clock: 50MHz +} en_sdioc_clk_freq_t; + +/** + ****************************************************************************** + ** \brief SDIOC detect the source of card enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_detect_signal +{ + SdiocSdcdPinLevel = 0u, ///< SDCD# is selected (for normal use) + SdiocCardDetectTestLevel = 1u, ///< The Card Detect Test Level is selected(for test purpose) +} en_sdioc_detect_signal_t; + +/** + ******************************************************************************* + ** \brief SDIOC Command configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_cmd_cfg +{ + uint8_t u8CmdIndex; ///< Command index + + uint32_t u32Argument; ///< The argument of command + + en_sdioc_cmd_type_t enCmdType; ///< Command type + + en_sdioc_response_index_t enRspIndex; ///< Response index, refer @ref en_sdioc_response_index_t for details + + en_functional_state_t enDataPresentEnable; ///< Enable: Data is present and shall be transferred using the DAT line, Disable: Commands using only CMD line +} stc_sdioc_cmd_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC Data configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_data_cfg +{ + uint16_t u16BlkSize; ///< Block size + + uint16_t u16BlkCnt; ///< Block count + + en_functional_state_t enAutoCmd12Enable; ///< Enable: Auto CMD12 enable, Disable: Auto CMD12 disable + + en_sdioc_transfer_dir_t enTransferDir; ///< Specifies the data transfer direction of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_dir_t. + + en_sdioc_data_timeout_t enDataTimeOut; ///< Specifies the data timeout period in card bus clock periods. + ///< This parameter can be a value of @ref en_sdioc_data_timeout_t. + + en_sdioc_transfer_mode_t enTransferMode; ///< Specifies the data transfer mode of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_mode_t. +} stc_sdioc_data_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_en +{ + union + { + uint16_t u16NormalIntsgEn; ///< SDIOC normal interrupt enable + stc_sdioc_errintsgen_field_t stcNormalIntsgEn; ///< SDIOC normal interrupt enable bit-field structure + }; +} stc_sdioc_normal_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_en +{ + union + { + uint16_t u16ErrorIntsgEn; ///< SDIOC error interrupt enable + stc_sdioc_errintsgen_field_t stcErrorIntsgEn; ///< SDIOC error interrupt enable bit-field structure + }; +} stc_sdioc_error_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_cb +{ + func_ptr_t pfnCommandCompleteIrqCb; ///< Pointer to command complete callback function + + func_ptr_t pfnTransferCompleteIrqCb; ///< Pointer to transfer complete callback function + + func_ptr_t pfnBlockGapIrqCb; ///< Pointer to Block gap callback function + + func_ptr_t pfnBufferWriteReadyIrqCb; ///< Pointer to buffer write ready callback function + + func_ptr_t pfnBufferReadReadyIrqCb; ///< Pointer to buffer read ready callback function + + func_ptr_t pfnCardInsertIrqCb; ///< Pointer to card insertion callback function + + func_ptr_t pfnCardRemovalIrqCb; ///< Pointer to card removal callback function + + func_ptr_t pfnCardIrqCb; ///< Pointer to card interrupt callback function +} stc_sdioc_normal_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_cb +{ + func_ptr_t pfnCmdTimeoutErrIrqCb; ///< Pointer to command timeout error interrupt callback function + + func_ptr_t pfnCmdCrcErrIrqCb; ///< Pointer to command CRC error interrupt callback function + + func_ptr_t pfnCmdEndBitErrIrqCb; ///< Pointer to command end bit error interrupt callback function + + func_ptr_t pfnCmdIndexErrIrqCb; ///< Pointer to command index error interrupt callback function + + func_ptr_t pfnDataTimeoutErrIrqCb; ///< Pointer to data timeout error interrupt callback function + + func_ptr_t pfnDataCrcErrIrqCb; ///< Pointer to data CRC error interrupt callback function + + func_ptr_t pfnDataEndBitErrIrqCb; ///< Pointer to data end bit error interrupt callback function + + func_ptr_t pfnAutoCmdErrIrqCb; ///< Pointer to command error interrupt callback function +} stc_sdioc_error_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC initialization configuration + ** + ******************************************************************************/ +typedef struct stc_sdioc_init +{ + stc_sdioc_normal_irq_en_t *pstcNormalIrqEn; ///< Pointer to normal interrupt enable structure + + stc_sdioc_normal_irq_cb_t *pstcNormalIrqCb; ///< Pointer to normal interrupt callback function structure + + stc_sdioc_error_irq_en_t *pstcErrorIrqEn; ///< Pointer to error interrupt enable structure + + stc_sdioc_error_irq_cb_t *pstcErrorIrqCb; ///< Pointer to error interrupt callback structure +} stc_sdioc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg); +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode); +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg); +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg); +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg); +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv); +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq); +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth); +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode); +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout); +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal); +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType); +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus); +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt); +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr); +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr); + +//@} // SdiocGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SDIOC_ENABLE */ + +#endif /* __HC32F460_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h new file mode 100644 index 000000000..5afbf57b7 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h @@ -0,0 +1,426 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.h + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ +#ifndef __HC32F460_SPI_H__ +#define __HC32F460_SPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SPI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SpiGroup Serial Peripheral Interface(SPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SPI parity enumeration + ******************************************************************************/ +typedef enum en_spi_parity +{ + SpiParityEven = 0u, ///< Select even parity send and receive + SpiParityOdd = 1u, ///< Select odd parity send and receive +} en_spi_parity_t; + +/** + ******************************************************************************* + ** \brief SPI master/slave mode enumeration + ******************************************************************************/ +typedef enum en_spi_master_slave_mode +{ + SpiModeSlave = 0u, ///< Spi slave mode + SpiModeMaster = 1u, ///< Spi master mode +} en_spi_master_slave_mode_t; + +/** + ******************************************************************************* + ** \brief SPI transmission mode enumeration + ******************************************************************************/ +typedef enum en_spi_trans_mode +{ + SpiTransFullDuplex = 0u, ///< Full duplex sync serial communication + SpiTransOnlySend = 1u, ///< Only send serial communication +} en_spi_trans_mode_t; + +/** + ******************************************************************************* + ** \brief SPI work mode enumeration + ******************************************************************************/ +typedef enum en_spi_work_mode +{ + SpiWorkMode4Line = 0u, ///< 4 lines spi work mode + SpiWorkMode3Line = 1u, ///< 3 lines spi work mode(clock sync running) +} en_spi_work_mode_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time +{ + SpiSsIntervalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalSck2PlusPck2 = 1u, ///< Spi SS interval time 2 SCK plus 2 PCLK1 + SpiSsIntervalSck3PlusPck2 = 2u, ///< Spi SS interval time 3 SCK plus 2 PCLK1 + SpiSsIntervalSck4PlusPck2 = 3u, ///< Spi SS interval time 4 SCK plus 2 PCLK1 + SpiSsIntervalSck5PlusPck2 = 4u, ///< Spi SS interval time 5 SCK plus 2 PCLK1 + SpiSsIntervalSck6PlusPck2 = 5u, ///< Spi SS interval time 6 SCK plus 2 PCLK1 + SpiSsIntervalSck7PlusPck2 = 6u, ///< Spi SS interval time 7 SCK plus 2 PCLK1 + SpiSsIntervalSck8PlusPck2 = 7u, ///< Spi SS interval time 8 SCK plus 2 PCLK1 +} en_spi_ss_interval_time_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay +{ + SpiSsSetupDelaySck1 = 0u, ///< Spi SS setup delay 1 SCK + SpiSsSetupDelaySck2 = 1u, ///< Spi SS setup delay 2 SCK + SpiSsSetupDelaySck3 = 2u, ///< Spi SS setup delay 3 SCK + SpiSsSetupDelaySck4 = 3u, ///< Spi SS setup delay 4 SCK + SpiSsSetupDelaySck5 = 4u, ///< Spi SS setup delay 5 SCK + SpiSsSetupDelaySck6 = 5u, ///< Spi SS setup delay 6 SCK + SpiSsSetupDelaySck7 = 6u, ///< Spi SS setup delay 7 SCK + SpiSsSetupDelaySck8 = 7u, ///< Spi SS setup delay 8 SCK +} en_spi_ss_setup_delay_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay +{ + SpiSsHoldDelaySck1 = 0u, ///< Spi SS hold delay 1 SCK + SpiSsHoldDelaySck2 = 1u, ///< Spi SS hold delay 2 SCK + SpiSsHoldDelaySck3 = 2u, ///< Spi SS hold delay 3 SCK + SpiSsHoldDelaySck4 = 3u, ///< Spi SS hold delay 4 SCK + SpiSsHoldDelaySck5 = 4u, ///< Spi SS hold delay 5 SCK + SpiSsHoldDelaySck6 = 5u, ///< Spi SS hold delay 6 SCK + SpiSsHoldDelaySck7 = 6u, ///< Spi SS hold delay 7 SCK + SpiSsHoldDelaySck8 = 7u, ///< Spi SS hold delay 8 SCK +} en_spi_ss_hold_delay_t; + +/** + ******************************************************************************* + ** \brief SPI slave select polarity enumeration + ******************************************************************************/ +typedef enum en_spi_ss_polarity +{ + SpiSsLowValid = 0u, ///< SS0~3 signal low level valid + SpiSsHighValid = 1u, ///< SS0~3 signal high level valid +} en_spi_ss_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI data register read object enumeration + ******************************************************************************/ +typedef enum en_spi_read_object +{ + SpiReadReceiverBuffer = 0u, ///< Read receive buffer + SpiReadSendBuffer = 1u, ///< Read send buffer(must be read when TDEF=1) +} en_spi_read_object_t; + +/** + ******************************************************************************* + ** \brief SPI frame number enumeration + ******************************************************************************/ +typedef enum en_spi_frame_number +{ + SpiFrameNumber1 = 0u, ///< 1 frame data + SpiFrameNumber2 = 1u, ///< 2 frame data + SpiFrameNumber3 = 2u, ///< 3 frame data + SpiFrameNumber4 = 3u, ///< 4 frame data +} en_spi_frame_number_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay_option +{ + SpiSsSetupDelayTypicalSck1 = 0u, ///< SS setup delay 1 SCK + SpiSsSetupDelayCustomValue = 1u, ///< SS setup delay SCKDL register set value +} en_spi_ss_setup_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay_option +{ + SpiSsHoldDelayTypicalSck1 = 0u, ///< SS hold delay 1 SCK + SpiSsHoldDelayCustomValue = 1u, ///< SS hold delay SSDL register set value +} en_spi_ss_hold_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time_option +{ + SpiSsIntervalTypicalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalCustomValue = 1u, ///< Spi SS interval time NXTDL register set value +} en_spi_ss_interval_time_option_t; + +/** + ******************************************************************************* + ** \brief SPI first bit position enumeration + ******************************************************************************/ +typedef enum en_spi_first_bit_position +{ + SpiFirstBitPositionMSB = 0u, ///< Spi first bit to MSB + SpiFirstBitPositionLSB = 1u, ///< Spi first bit to LSB +} en_spi_first_bit_position_t; + +/** + ******************************************************************************* + ** \brief SPI data length enumeration + ******************************************************************************/ +typedef enum en_spi_data_length +{ + SpiDataLengthBit4 = 0u, ///< 4 bits + SpiDataLengthBit5 = 1u, ///< 5 bits + SpiDataLengthBit6 = 2u, ///< 6 bits + SpiDataLengthBit7 = 3u, ///< 7 bits + SpiDataLengthBit8 = 4u, ///< 8 bits + SpiDataLengthBit9 = 5u, ///< 9 bits + SpiDataLengthBit10 = 6u, ///< 10 bits + SpiDataLengthBit11 = 7u, ///< 11 bits + SpiDataLengthBit12 = 8u, ///< 12 bits + SpiDataLengthBit13 = 9u, ///< 13 bits + SpiDataLengthBit14 = 10u, ///< 14 bits + SpiDataLengthBit15 = 11u, ///< 15 bits + SpiDataLengthBit16 = 12u, ///< 16 bits + SpiDataLengthBit20 = 13u, ///< 20 bits + SpiDataLengthBit24 = 14u, ///< 24 bits + SpiDataLengthBit32 = 15u, ///< 32 bits +} en_spi_data_length_t; + +/** + ******************************************************************************* + ** \brief SPI SS valid channel select enumeration + ******************************************************************************/ +typedef enum en_spi_ss_valid_channel +{ + SpiSsValidChannel0 = 0u, ///< Select SS0 valid + SpiSsValidChannel1 = 1u, ///< Select SS1 valid + SpiSsValidChannel2 = 2u, ///< Select SS2 valid + SpiSsValidChannel3 = 3u, ///< Select SS3 valid +} en_spi_ss_valid_channel_t; + +/** + ******************************************************************************* + ** \brief SPI clock division enumeration + ******************************************************************************/ +typedef enum en_spi_clk_div +{ + SpiClkDiv2 = 0u, ///< Spi pclk1 division 2 + SpiClkDiv4 = 1u, ///< Spi pclk1 division 4 + SpiClkDiv8 = 2u, ///< Spi pclk1 division 8 + SpiClkDiv16 = 3u, ///< Spi pclk1 division 16 + SpiClkDiv32 = 4u, ///< Spi pclk1 division 32 + SpiClkDiv64 = 5u, ///< Spi pclk1 division 64 + SpiClkDiv128 = 6u, ///< Spi pclk1 division 128 + SpiClkDiv256 = 7u, ///< Spi pclk1 division 256 +} en_spi_clk_div_t; + +/** + ******************************************************************************* + ** \brief SPI SCK polarity enumeration + ******************************************************************************/ +typedef enum en_spi_sck_polarity +{ + SpiSckIdleLevelLow = 0u, ///< SCK is low level when SCK idle + SpiSckIdleLevelHigh = 1u, ///< SCK is high level when SCK idle +} en_spi_sck_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI SCK phase enumeration + ******************************************************************************/ +typedef enum en_spi_sck_phase +{ + SpiSckOddSampleEvenChange = 0u, ///< SCK Odd edge data sample,even edge data change + SpiSckOddChangeEvenSample = 1u, ///< SCK Odd edge data change,even edge data sample +} en_spi_sck_phase_t; + +/** + ******************************************************************************* + ** \brief SPI interrupt request type enumeration + ******************************************************************************/ +typedef enum en_spi_irq_type +{ + SpiIrqIdle = 0u, ///< Spi idle interrupt request + SpiIrqReceive = 1u, ///< Spi receive interrupt request + SpiIrqSend = 2u, ///< Spi send interrupt request + SpiIrqError = 3u, ///< Spi error interrupt request +} en_spi_irq_type_t; + +/** + ******************************************************************************* + ** \brief SPI flag type enumeration + ******************************************************************************/ +typedef enum en_spi_flag_type +{ + SpiFlagReceiveBufferFull = 0u, ///< Receive buffer full flag + SpiFlagSendBufferEmpty = 1u, ///< Send buffer empty flag + SpiFlagUnderloadError = 2u, ///< Underload error flag + SpiFlagParityError = 3u, ///< Parity error flag + SpiFlagModeFaultError = 4u, ///< Mode fault error flag + SpiFlagSpiIdle = 5u, ///< SPI idle flag + SpiFlagOverloadError = 6u, ///< Overload error flag +} en_spi_flag_type_t; + +/** + ******************************************************************************* + ** \brief SPI SS channel enumeration + ******************************************************************************/ +typedef enum en_spi_ss_channel +{ + SpiSsChannel0 = 0u, ///< SS0 channel + SpiSsChannel1 = 1u, ///< SS1 channel + SpiSsChannel2 = 2u, ///< SS2 channel + SpiSsChannel3 = 3u, ///< SS3 channel +} en_spi_ss_channel_t; + +/** + ******************************************************************************* + ** \brief SPI bus delay structure definition + ** + ** \note Slave mode stc_spi_delay_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_delay_config +{ + en_spi_ss_setup_delay_option_t enSsSetupDelayOption; ///< SS setup delay time option + en_spi_ss_setup_delay_t enSsSetupDelayTime; ///< SS setup delay time(the value valid when enSsSetupDelayOption is custom) + en_spi_ss_hold_delay_option_t enSsHoldDelayOption; ///< SS hold delay time option + en_spi_ss_hold_delay_t enSsHoldDelayTime; ///< SS hold delay time(the value valid when enSsHoldDelayOption is custom) + en_spi_ss_interval_time_option_t enSsIntervalTimeOption; ///< SS interval time option + en_spi_ss_interval_time_t enSsIntervalTime; ///< SS interval time(the value valid when enSsIntervalTimeOption is custom) +} stc_spi_delay_config_t; + +/** + ******************************************************************************* + ** \brief SPI SS config structure definition + ** + ** \note 3 lines mode stc_spi_ss_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_ss_config +{ + en_spi_ss_valid_channel_t enSsValidBit; ///< SS valid channel select + en_spi_ss_polarity_t enSs0Polarity; ///< SS0 signal polarity + en_spi_ss_polarity_t enSs1Polarity; ///< SS1 signal polarity + en_spi_ss_polarity_t enSs2Polarity; ///< SS2 signal polarity + en_spi_ss_polarity_t enSs3Polarity; ///< SS3 signal polarity +} stc_spi_ss_config_t; + +/** + ******************************************************************************* + ** \brief SPI init structure definition + ******************************************************************************/ +typedef struct stc_spi_init_t +{ + stc_spi_delay_config_t stcDelayConfig; ///< SPI delay structure(Slave mode is invalid) + stc_spi_ss_config_t stcSsConfig; ///< SS polarity and channel structure(3 lines mode invalid) + en_spi_read_object_t enReadBufferObject; ///< Data register read object select(must be read when TDEF=1) + en_spi_sck_polarity_t enSckPolarity; ///< Sck polarity + en_spi_sck_phase_t enSckPhase; ///< Sck phase(This value must be SpiSckOddChangeEvenSample in 3-line mode) + en_spi_clk_div_t enClkDiv; ///< SPI clock division + en_spi_data_length_t enDataLength; ///< Data length + en_spi_first_bit_position_t enFirstBitPosition; ///< Data first bit position + en_spi_frame_number_t enFrameNumber; ///< Data frame number + en_spi_work_mode_t enWorkMode; ///< Spi work mode + en_spi_trans_mode_t enTransMode; ///< transmission mode + en_spi_master_slave_mode_t enMasterSlaveMode; ///< Spi master/slave mode + en_functional_state_t enCommAutoSuspendEn; ///< Enable/disable Communication auto suspend + en_functional_state_t enModeFaultErrorDetectEn; ///< Enable/disable Mode fault error detect + en_functional_state_t enParitySelfDetectEn; ///< Enable/disable Parity self detect + en_functional_state_t enParityEn; ///< Enable/disable Parity(if enable parity and SPI_CR1.TXMDS=1, receive data don't parity) + en_spi_parity_t enParity; ///< Parity mode select +} stc_spi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx); +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg); +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); + +/* Send and receive data functions */ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data); +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data); +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data); +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx); +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx); +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx); + +/* Communication configure functions */ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity); +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel); +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject); +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum); +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength); +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition); +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv); + +/* Interrupt and flags functions */ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); + +//@} // SpiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SPI_ENABLE */ + +#endif /* __HC32F460_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h new file mode 100644 index 000000000..cc7147d0c --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h @@ -0,0 +1,190 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.h + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +#ifndef __HC32F460_SRAM_H__ +#define __HC32F460_SRAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup SramGroup Internal SRAM + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +///< SRAM wait cycle register, parity/ECC check register protect code definition +#define SRAM_PROTECT_CODE (0x0000003Bu) + +/******************************************************************************* + Start addr. End addr. Size Function + SRAM1 0x20000000 0x2000FFFF 64KB Even Parity Check + SRAM2 0x20010000 0x2001FFFF 64KB Even Parity Check + SRAM3 0x20020000 0x20026FFF 28KB ECC Check + SRAM_Ret 0x200F0000 0x200F0FFF 4KB Even Parity Check + SRAM_HS 0x1FFF8000 0x1FFFFFFF 32KB Even Parity Check + ******************************************************************************/ +///< SRAM1 base address definition +#define SRAM1_BASE_ADDR (*((volatile unsigned int*)(0x20000000UL))) + +///< SRAM2 base address definition +#define SRAM2_BASE_ADDR (*((volatile unsigned int*)(0x20010000UL))) + +///< SRAM3 base address definition +#define SRAM3_BASE_ADDR (*((volatile unsigned int*)(0x20020000UL))) + +///< Retention SRAM base address definition +#define SRAMRET_BASE_ADDR (*((volatile unsigned int*)(0x200F0000UL))) + +///< High speed SRAM base address definition +#define SRAMHS_BASE_ADDR (*((volatile unsigned int*)(0x1FFF8000UL))) + + +typedef enum en_sram_index +{ + Sram12Idx = 1u << 0, + Sram3Idx = 1u << 1, + SramHsIdx = 1u << 2, + SramRetIdx = 1u << 3, +}en_sram_index_t; +/** + ******************************************************************************* + ** \brief Enumeration to the write/read cycles of SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_rw_cycle +{ + SramCycle1 = 0u, + SramCycle2 = 1u, + SramCycle3 = 2u, + SramCycle4 = 3u, + SramCycle5 = 4u, + SramCycle6 = 5u, + SramCycle7 = 6u, + SramCycle8 = 7u, +}en_sram_rw_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to ECC check mode + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_mode +{ + EccMode0 = 0u, ///< disable ECC check function + EccMode1 = 1u, ///< no 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode2 = 2u, ///< generate 1 bit ECC flag, but no interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode3 = 3u, ///< generate 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected +}en_ecc_mode_t; + +/** + ******************************************************************************* + ** \brief Enumeration to operation after ECC/Parity error + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_py_err_op +{ + SramNmi = 0u, ///< Generate NMI after ECC/Parity error detected + SramReset = 1u, ///< Generate Reset after ECC/Parity error detected +}en_ecc_py_err_op_t; + +/** + ******************************************************************************* + ** \brief Enumeration to the ECC/Parity error status of each SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_err_status +{ + Sram3EccErr1 = 1u << 0, ///< SRAM3 1 bit ECC error + Sram3EccErr2 = 1u << 1, ///< SRAM3 2 bit ECC error + Sram12ParityErr = 1u << 2, ///< SRAM1/2 parity error + SramHSParityErr = 1u << 3, ///< High speed SRAM parity error + SramRetParityErr = 1u << 4, ///< Retention SRAM parity error +}en_sram_err_status_t; + +/** + ******************************************************************************* + ** \brief SRAM configuration + ** + ** \note The SRAM configuration structure + ******************************************************************************/ +typedef struct stc_sram_config +{ + uint8_t u8SramIdx; ///< SRAM index, ref @ en_sram_index_t for details + en_sram_rw_cycle_t enSramRC; ///< SRAM read wait cycle setting + en_sram_rw_cycle_t enSramWC; ///< SRAM write wait cycle setting + en_ecc_mode_t enSramEccMode; ///< SRAM ECC mode setting + en_ecc_py_err_op_t enSramEccOp; ///< SRAM3 ECC error handling setting + en_ecc_py_err_op_t enSramPyOp; ///< SRAM1/2/HS/Ret Parity error handling setting + +}stc_sram_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig); +extern en_result_t SRAM_DeInit(void); +extern en_result_t SRAM_WT_Disable(void); +extern en_result_t SRAM_WT_Enable(void); +extern en_result_t SRAM_CK_Disable(void); +extern en_result_t SRAM_CK_Enable(void); +extern en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus); +extern en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus); + +//@} // SramGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SRAM_ENABLE */ + +#endif /* __HC32F460_SRAM_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h new file mode 100644 index 000000000..63d94c4d1 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.h + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_SWDT_H__ +#define __HC32F460_SWDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SwdtGroup Special Watchdog Counter(SWDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT flag type enumeration + ******************************************************************************/ +typedef enum en_swdt_flag_type +{ + SwdtFlagCountUnderflow = 0u, ///< Count underflow flag + SwdtFlagRefreshError = 1u, ///< Refresh error flag +} en_swdt_flag_type_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SWDT_RefreshCounter(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag); +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag); + +//@} // SwdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SWDT_ENABLE */ + +#endif /* __HC32F460_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h new file mode 100644 index 000000000..46b570fe4 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h @@ -0,0 +1,209 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.h + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +#ifndef __HC32F460_TIMER0_H__ +#define __HC32F460_TIMER0_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TIMER0_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Timer0Group Timer0 + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timer0 channel enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_channel +{ + Tim0_ChannelA = 0x00u, + Tim0_ChannelB = 0x01u +}en_tim0_channel_t; + +/** + ******************************************************************************* + ** \brief Timer0 Async Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_async_clock_src +{ + Tim0_LRC = 0x00u, + Tim0_XTAL32 = 0x01u +}en_tim0_async_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 Sync Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_sync_clock_src +{ + Tim0_Pclk1 = 0x00u, + Tim0_InsideHardTrig = 0x01u +}en_tim0_sync_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 counter mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_counter_mode +{ + Tim0_Sync = 0x00u, + Tim0_Async = 0x01u +}en_tim0_counter_mode_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger event mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_function +{ + Tim0_OutputCapare = 0x00u, + Tim0_InputCaptrue = 0x01u +}en_tim0_function_t; + +/** + ******************************************************************************* + ** \brief Timer0 clock division enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_clock_div +{ + Tim0_ClkDiv0 = 0u, + Tim0_ClkDiv2, + Tim0_ClkDiv4, + Tim0_ClkDiv8, + Tim0_ClkDiv16, + Tim0_ClkDiv32, + Tim0_ClkDiv64, + Tim0_ClkDiv128, + Tim0_ClkDiv256, + Tim0_ClkDiv512, + Tim0_ClkDiv1024 +}en_tim0_clock_div_t; + +/** + ******************************************************************************* + ** \brief Timer0 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_com_trigger +{ + Tim0ComTrigger_1 = 1u, ///< Select common trigger 1. + Tim0ComTrigger_2 = 2u, ///< Select common trigger 2. + Tim0ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_tim0_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger function init structrue definition + ** + ******************************************************************************/ +typedef struct stc_tim0_trigger_init +{ + en_tim0_function_t Tim0_OCMode; ///GCMAR / GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR / GCMDR-->GCMBR + ** Double buffer stransfer: Compare Ouput: GCMER-->GCMCR-->GCMAR / GCMFR-->GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR-->GCMER /GCMFR-->GCMDR-->GCMBR + ** For Period register: + ** Single buffer stransfer: PERBR-->PERAR + ** Double buffer stransfer: PERCR-->PERBR-->PERAR + ******************************************************************************/ +typedef enum en_timer6_buf_gcmp_prd +{ + Timer6GcmpPrdSingleBuf = 0u, ///< Single buffer stransfer + Timer6GcmpPrdDoubleBuf = 1u, ///< Double buffer stransfer +}en_timer6_buf_gcmp_prd_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer function selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_cmp +{ + Timer6SpclSingleBuf = 0u, ///< Single buffer stransfer: Compare Ouput: SCMCR-->SCMAR / SCMDR-->SCMBR + Timer6SpclDoubleBuf = 1u, ///< Double buffer stransfer: Compare Ouput: SCMER-->SCMCR-->SCMAR / SCMFR-->SCMDR-->SCMBR +}en_timer6_buf_spcl_cmp_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer opportunity selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_opt +{ + Timer6SplcOptNone = 0u, ///< No transfer + Timer6SplcOptOverFlow = 1u, ///< Transfer when over flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptUnderFlow = 2u, ///< Transfer when under flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptBoth = 3u, ///< Transfer when over flow or under flow (About sawtooth mode,accord to the count direction) +}en_timer6_buf_spcl_opt_t; + +/** + ****************************************************************************** + ** \brief ADT dead timer control - PWMx dead timer separate set + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_dconr_sepa +{ + Timer6PWMxDtSeparate = 0u, ///< The dead timer of up count and down count separate set by DTUAR and DTDAR + Timer6PWMxDtEqual = 1u, ///< the values of DTUAR and DTDAR are equal automatically +}en_timer6_dconr_sepa_t; + +/** + ****************************************************************************** + ** \brief ADT filter control- TRIx/PWMx port filter sample clock selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_fconr_fltclk +{ + Timer6FltClkPclk0Div1 = 0u, ///< PCLK0 + Timer6FltClkPclk0Div4 = 1u, ///< PCLK0/4 + Timer6FltClkPclk0Div16 = 2u, ///< PCLK0/16 + Timer6FltClkPclk0Div64 = 3u, ///< PCLK0/64 +}en_timer6_fconr_fltclk_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- TIMx valid period repeat function selection(trigger interrupt or AOS event) + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnts +{ + Timer6PeriodCnts0 = 0u, ///< Valid period repeat function disable + Timer6PeriodCnts1 = 1u, ///< Enable every other one period + Timer6PeriodCnts2 = 2u, ///< Enable every other two periods + Timer6PeriodCnts3 = 3u, ///< Enable every other three periods + Timer6PeriodCnts4 = 4u, ///< Enable every other four periods + Timer6PeriodCnts5 = 5u, ///< Enable every other five periods + Timer6PeriodCnts6 = 6u, ///< Enable every other six periods + Timer6PeriodCnts7 = 7u, ///< Enable every other seven periods +}en_timer6_vperr_pcnts_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- Count condition select + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnte +{ + Timer6PeriodCnteDisable = 0u, ///< Valid period repeat function disable + Timer6PeriodCnteMin = 1u, ///< Over flow and under flow point of Sawtooth wave mode, or under flow point of Triangular wave mode + Timer6PeriodCnteMax = 2u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow point of Triangular wave mode + Timer6PeriodCnteBoth = 3u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow and under flow point of Triangular wave mode +}en_timer6_vperr_pcnte_t; + +/** + ****************************************************************************** + ** \brief Timer6 Hardware(Start/Stop/Clear/Capture) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_trig +{ + Timer6HwTrigAos0 = 0u, ///< Hardware trigger event from AOS0(HTSSR0) + Timer6HwTrigAos1 = 1u, ///< Hardware trigger event from AOS1(HTSSR1) + Timer6HwTrigPWMARise = 4u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMAFall = 5u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigPWMBRise = 6u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMBFall = 7u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigTimTriARise = 8u, ///< Hardware trigger event from TRIGA rising + Timer6HwTrigTimTriAFall = 9u, ///< Hardware trigger event from TRIGA falling + Timer6HwTrigTimTriBRise = 10u, ///< Hardware trigger event from TRIGB rising + Timer6HwTrigTimTriBFall = 11u, ///< Hardware trigger event from TRIGB falling + Timer6HwTrigEnd = 16u, +}en_timer6_hw_trig_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware (up count/down count) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_cnt +{ + Timer6HwCntPWMALowPWMBRise = 0u, ///< PWMB Rising trigger when PWMA is low level + Timer6HwCntPWMALowPWMBFall = 1u, ///< PWMB falling trigger when PWMA is low level + Timer6HwCntPWMAHighPWMBRise = 2u, ///< PWMB Rising trigger when PWMA is high level + Timer6HwCntPWMAHighPWMBFall = 3u, ///< PWMB falling trigger when PWMA is high level + Timer6HwCntPWMBLowPWMARise = 4u, ///< PWMA Rising trigger when PWMB is low level + Timer6HwCntPWMBLowPWMAFall = 5u, ///< PWMA falling trigger when PWMB is low level + Timer6HwCntPWMBHighPWMARise = 6u, ///< PWMA Rising trigger when PWMB is high level + Timer6HwCntPWMBHighPWMAFall = 7u, ///< PWMA falling trigger when PWMB is high level + Timer6HwCntTRIGARise = 8u, ///< TRIGA rising trigger + Timer6HwCntTRIGAFall = 9u, ///< TRIGA falling trigger + Timer6HwCntTRIGBRise = 10u, ///< TRIGB rising trigger + Timer6HwCntTRIGBFall = 11u, ///< TRIGB falling trigger + Timer6HwCntAos0 = 16u, ///< AOS0 trigger + Timer6HwCntAos1 = 17u, ///< AOS1 trigger + Timer6HwCntMax = 18u, +}en_timer6_hw_cnt_t; + + +/** + ****************************************************************************** + ** \brief Timer6 interrupt type + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_irq_type +{ + Timer6INTENA = 0u, ///< Interrupt of count equal to GCMA (or capture input A) + Timer6INTENB = 1u, ///< Interrupt of count equal to GCMB (or capture input B) + Timer6INTENC = 2u, ///< Interrupt of count equal to GCMC + Timer6INTEND = 3u, ///< Interrupt of count equal to GCMD + Timer6INTENE = 4u, ///< Interrupt of count equal to GCME + Timer6INTENF = 5u, ///< Interrupt of count equal to GCMF + Timer6INTENOVF = 6u, ///< Interrupt of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6INTENUDF = 7u, ///< Interrupt of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6INTENDTE = 8u, ///< Interrupt of dead timer error + Timer6INTENSAU = 16u, ///< Interrupt of count up equally compared with SCMA + Timer6INTENSAD = 17u, ///< Interrupt of count down equally compared with SCMA + Timer6INTENSBU = 18u, ///< Interrupt of count up equally compared with SCMB + Timer6INTENSBD = 19u, ///< Interrupt of count down equally compared with SCMB +}en_timer6_irq_type_t; + + +/** + ****************************************************************************** + ** \brief Timer6 status flag + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_status +{ + Timer6CMAF = 0u, ///< Status flag of count equal to GCMA (or capture input A) + Timer6CMBF = 1u, ///< Status flag of count equal to GCMB (or capture input B) + Timer6CMCF = 2u, ///< Status flag of count equal to GCMC + Timer6CMDF = 3u, ///< Status flag of count equal to GCMD + Timer6CMEF = 4u, ///< Status flag of count equal to GCME + Timer6CMFF = 5u, ///< Status flag of count equal to GCMF + Timer6OVFF = 6u, ///< Status flag of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6UDFF = 7u, ///< Status flag of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6DTEF = 8u, ///< Status flag of dead timer error + Timer6CMSAUF = 9u, ///< Status flag of count up equally compared with SCMA + Timer6CMSADF = 10u, ///< Status flag of count down equally compared with SCMA + Timer6CMSBUF = 11u, ///< Status flag of count up equally compared with SCMB + Timer6CMSBDF = 12u, ///< Status flag of count down equally compared with SCMB + Timer6VPERNUM = 21, ///< Number of valid period + Timer6DIRF = 31, ///< Count direction +}en_timer6_status_t; + +/** + ******************************************************************************* + ** \brief Timer6 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_timer6_com_trigger +{ + Timer6ComTrigger_1 = 1u, ///< Select common trigger 1. + Timer6ComTrigger_2 = 2u, ///< Select common trigger 2. + Timer6ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timer6_com_trigger_t; + +/** + ****************************************************************************** + ** \brief Timer6 software synchronous config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_sw_sync +{ + bool bTimer61; ///< Timer6 unit1 + bool bTimer62; ///< Timer6 unit2 + bool bTimer63; ///< Timer6 unit3 +}stc_timer6_sw_sync_t; + +/** + ****************************************************************************** + ** \brief Timer6 base init structure definition + ** \note + ******************************************************************************/ +typedef struct stc_timer6_basecnt_cfg +{ + en_timer6_count_mode_t enCntMode; ///< Count mode + en_timer6_count_dir_t enCntDir; ///< Count direction + en_timer6_clk_div_t enCntClkDiv; ///< Count clock division select +}stc_timer6_basecnt_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Trig port config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_port_trig_cfg +{ + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_tiemr6_port_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 port output config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_output_cfg +{ + en_timer6_func_mode_t enPortMode; ///< Port mode + bool bOutEn; ///< Output enable / disable + en_timer6_pconr_cmpc_t enPerc; ///< Port state when counter match the period + en_timer6_pconr_cmpc_t enCmpc; ///< Port state when counter match GCMAR(GCMBR) + en_timer6_pconr_stastps_t enStaStp; ///< Post state selection when count start/stop + en_timer6_pconr_port_out_t enStaOut; ///< Port state when count start + en_timer6_pconr_port_out_t enStpOut; ///< port stop when count stop + en_timer6_pconr_disval_t enDisVal; ///< Port output state when brake +}stc_timer6_port_output_cfg_t; + + +/** + ****************************************************************************** + ** \brief Timer6 port input config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_input_cfg +{ + en_timer6_input_port_t enPortSel; ///< Port select + en_timer6_func_mode_t enPortMode; ///< Port mode + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_timer6_port_input_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware dead time function config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_deadtime_cfg +{ + bool bEnDeadtime; ///< Enable hardware dead time function + bool bEnDtBufUp; ///< Enable buffer transfer for up count dead time register(DTUBR-->DTUAR) + bool bEnDtBufDwn; ///< Enable buffer transfer for down count dead time register(DTDBR-->DTDAR) + bool bEnDtEqualUpDwn; ///< Enable down count dead time register equal to up count DT register +}stc_timer6_deadtime_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_validper_cfg +{ + en_timer6_vperr_pcnts_t enValidCntNum; ///< Valid period selection + en_timer6_vperr_pcnte_t enValidCdtEn; ///< Count condition of valid period + bool bPeriodSCMA; ///< Sepcial signal A valid period selection enable + bool bPeriodSCMB; ///< Sepcial signal A valid period selection enable +}stc_timer6_validper_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 general compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_gcmp_buf_cfg +{ + bool bEnGcmpTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enGcmpBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_gcmp_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 period register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_period_buf_cfg +{ + bool bEnPeriodTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enPeriodBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_period_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Specila compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_spcl_buf_cfg +{ + bool bEnSpclTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_spcl_cmp_t enSpclBufTransType; ///< Sigle or double buffer transfer + en_timer6_buf_spcl_opt_t enSpclBufOptType; ///< Buffer transfer opportunity +}stc_timer6_spcl_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Z phase input mask config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_zmask_cfg +{ + en_timer6_gconr_zmsk_t enZMaskCycle; ///< Z phase input mask periods selection + bool bFltPosCntMaksEn; ///< As position count timer, position counter clear function enable(TRUE) or disable(FALSE) during the time of Z phase input mask + bool bFltRevCntMaksEn; ///< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) during the time of Z phase input mask +}stc_timer6_zmask_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn); +/* Get status(flag) */ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus); + +/* Base functions */ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x); +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg); +/* Timer6 unit start count*/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit stop count*/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Set Count Value*/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value); +/* Timer6 unit Get Count Value*/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Clear Count Value*/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x); + +/* Timer6 unit Set Period and buffer Value*/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period); +/* Timer6 unit set general compare register value*/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare); +/* Timer6 unit set specoal compare register value*/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp); +/* Timer6 unit get general compare register value*/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare); + +/* Timer6 unit set period buffer transfer function*/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg); +/* Timer6 unit set general compare buffer transfer function*/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg); +/* Timer6 unit set special compare buffer transfer function*/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg); + +/* Timer6 unit Set valid period Value*/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg); + +/* Config Input prot and filter function */ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg); +/* Config output prot function */ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg); + +/* Set dead time register value */ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue); +/* Config dead time function */ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg); + +/* Config Software Synchrony Stop */ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart); +/* Config Software Synchrony Start */ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop); +/* Config Software Synchrony Clear */ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear); +/* Get Software Synchrony Status */ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState); + +/* Config Hardware up count event */ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp); +/* Clear Hardware up count event */ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware down count event */ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn); +/* Clear Hardware down count event */ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware start event */ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart); +/* Clear Hardware start event */ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware start event */ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware start event */ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware stop event */ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop); +/* Clear Hardware stop event */ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware stop event */ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x); +/* Disable Hardware stop event */ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware clear event */ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear); +/* Clear Hardware clear event */ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware clear event */ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware clear event */ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware capture event A */ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA); +/* Clear Hardware capture event A */ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware capture event B */ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB); +/* Clear Hardware capture event B */ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x); + + +/* Set trigger source 0 of hardware event */ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc); +/* Set trigger source 1 of hardware event */ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc); +/* Enable or disable Timer6 common trigger for Hardware trigger source 0 */ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); +/* Enable or disable Timer6 common trigger for Hardware trigger source 1 */ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); + +/* Z phase input mask config */ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg); + +//@} // Timer6Group + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TIMER6_ENABLE */ + +#endif /* __HC32F460_TIMER6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h new file mode 100644 index 000000000..5143819fe --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h @@ -0,0 +1,493 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.h + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ +#ifndef __HC32F460_TIMERA_H__ +#define __HC32F460_TIMERA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TIMERA_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TimeraGroup Timer A(Timera) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timera channel enumeration + ******************************************************************************/ +typedef enum en_timera_channel +{ + TimeraCh1 = 0u, ///< Timera channel 1 + TimeraCh2 = 1u, ///< Timera channel 2 + TimeraCh3 = 2u, ///< Timera channel 3 + TimeraCh4 = 3u, ///< Timera channel 4 + TimeraCh5 = 4u, ///< Timera channel 5 + TimeraCh6 = 5u, ///< Timera channel 6 + TimeraCh7 = 6u, ///< Timera channel 7 + TimeraCh8 = 7u, ///< Timera channel 8 +} en_timera_channel_t; + +/** + ******************************************************************************* + ** \brief Clock division enumeration + ******************************************************************************/ +typedef enum en_timera_clk_div +{ + TimeraPclkDiv1 = 0u, ///< Count clock: pclk + TimeraPclkDiv2 = 1u, ///< Count clock: pclk/2 + TimeraPclkDiv4 = 2u, ///< Count clock: pclk/4 + TimeraPclkDiv8 = 3u, ///< Count clock: pclk/8 + TimeraPclkDiv16 = 4u, ///< Count clock: pclk/16 + TimeraPclkDiv32 = 5u, ///< Count clock: pclk/32 + TimeraPclkDiv64 = 6u, ///< Count clock: pclk/64 + TimeraPclkDiv128 = 7u, ///< Count clock: pclk/128 + TimeraPclkDiv256 = 8u, ///< Count clock: pclk/256 + TimeraPclkDiv512 = 9u, ///< Count clock: pclk/512 + TimeraPclkDiv1024 = 10u, ///< Count clock: pclk/1024 +} en_timera_clk_div_t; + +/** + ******************************************************************************* + ** \brief Count mode enumeration + ******************************************************************************/ +typedef enum en_timera_count_mode +{ + TimeraCountModeSawtoothWave = 0u, ///< Sawtooth wave mode + TimeraCountModeTriangularWave = 1u, ///< Triangular wave mode +} en_timera_count_mode_t; + +/** + ******************************************************************************* + ** \brief Count direction enumeration + ******************************************************************************/ +typedef enum en_timera_count_dir +{ + TimeraCountDirDown = 0u, ///< Counter counting down + TimeraCountDirUp = 1u, ///< Counter counting up +} en_timera_count_dir_t; + +/** + ******************************************************************************* + ** \brief Input port filter clock division enumeration + ******************************************************************************/ +typedef enum en_timera_filter_clk_div +{ + TimeraFilterPclkDiv1 = 0u, ///< Filter clock: pclk + TimeraFilterPclkDiv4 = 1u, ///< Filter clock: pclk/4 + TimeraFilterPclkDiv16 = 2u, ///< Filter clock: pclk/16 + TimeraFilterPclkDiv64 = 3u, ///< Filter clock: pclk/64 +} en_timera_filter_clk_div_t; + +/** + ******************************************************************************* + ** \brief Input port filter source enumeration + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef enum en_timera_filter_source +{ + TimeraFilterSourceCh1 = 0u, ///< TIMA__PWM1 input port + TimeraFilterSourceCh2 = 1u, ///< TIMA__PWM2 input port + TimeraFilterSourceCh3 = 2u, ///< TIMA__PWM3 input port + TimeraFilterSourceCh4 = 3u, ///< TIMA__PWM4 input port + TimeraFilterSourceCh5 = 4u, ///< TIMA__PWM5 input port + TimeraFilterSourceCh6 = 5u, ///< TIMA__PWM6 input port + TimeraFilterSourceCh7 = 6u, ///< TIMA__PWM7 input port + TimeraFilterSourceCh8 = 7u, ///< TIMA__PWM8 input port + TimeraFilterSourceClkA = 8u, ///< TIMA__CLKA input port + TimeraFilterSourceClkB = 9u, ///< TIMA__CLKB input port + TimeraFilterSourceTrig = 10u, ///< TIMA__TRIG input port +} en_timera_filter_source_t; + +/** + ******************************************************************************* + ** \brief Timera interrupt request type enumeration + ******************************************************************************/ +typedef enum en_timera_irq_type +{ + TimeraIrqCaptureOrCompareCh1 = 0u, ///< Interrupt request when channel 1 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh2 = 1u, ///< Interrupt request when channel 2 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh3 = 2u, ///< Interrupt request when channel 3 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh4 = 3u, ///< Interrupt request when channel 4 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh5 = 4u, ///< Interrupt request when channel 5 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh6 = 5u, ///< Interrupt request when channel 6 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh7 = 6u, ///< Interrupt request when channel 7 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh8 = 7u, ///< Interrupt request when channel 8 trigger capture event or compare value equal count value + TimeraIrqOverflow = 8u, ///< Count overflow interrupt request + TimeraIrqUnderflow = 9u, ///< Count underflow interrupt request +} en_timera_irq_type_t; + +/** + ******************************************************************************* + ** \brief Timera flag type enumeration + ******************************************************************************/ +typedef enum en_timera_flag_type +{ + TimeraFlagCaptureOrCompareCh1 = 0u, ///< Match flag when channel 1 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh2 = 1u, ///< Match flag when channel 2 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh3 = 2u, ///< Match flag when channel 3 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh4 = 3u, ///< Match flag when channel 4 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh5 = 4u, ///< Match flag when channel 5 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh6 = 5u, ///< Match flag when channel 6 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh7 = 6u, ///< Match flag when channel 7 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh8 = 7u, ///< Match flag when channel 8 trigger capture complete or compare value equal count value + TimeraFlagOverflow = 8u, ///< Count overflow flag + TimeraFlagUnderflow = 9u, ///< Count underflow flag +} en_timera_flag_type_t; + +/** + ******************************************************************************* + ** \brief Timera function mode selection enumeration + ******************************************************************************/ +typedef enum en_timera_func_mode +{ + TimeraModeCompareOutput = 0u, ///< Compare output function + TimeraModeCaptureInput = 1u, ///< Capture input function +} en_timera_func_mode_t; + +/** + ******************************************************************************* + ** \brief Timera count start port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_start_output +{ + TimeraCountStartOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStartOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStartOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_start_output_t; + +/** + ******************************************************************************* + ** \brief Timera count stop port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_stop_output +{ + TimeraCountStopOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStopOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStopOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_stop_output_t; + +/** + ******************************************************************************* + ** \brief Timera compare value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_compare_match_output +{ + TimeraCompareMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCompareMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCompareMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraCompareMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_compare_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera period value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_period_match_output +{ + TimeraPeriodMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraPeriodMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraPeriodMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraPeriodMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_period_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera specify output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_specify_output +{ + TimeraSpecifyOutputInvalid = 0u, ///< TIMA__PWMn port output invalid + TimeraSpecifyOutputLow = 2u, ///< TIMA__PWMn port output low level from next period + TimeraSpecifyOutputHigh = 3u, ///< TIMA__PWMn port output high level from next period +} en_timera_specify_output_t; + +/** + ******************************************************************************* + ** \brief Timera common trigger source enumeration + ******************************************************************************/ +typedef enum en_timera_com_trigger +{ + TimeraComTrigger_1 = 1u, ///< Select common trigger 1. + TimeraComTrigger_2 = 2u, ///< Select common trigger 2. + TimeraComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timera_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timera base init structure definition + ******************************************************************************/ +typedef struct stc_timera_base_init +{ + en_timera_clk_div_t enClkDiv; ///< Count clock division select,This is invalid when counting internal or external event + en_timera_count_mode_t enCntMode; ///< Timera count mode + en_timera_count_dir_t enCntDir; ///< Timera count direction + en_functional_state_t enSyncStartupEn; ///< Enable/disable synchronization startup when unit 1 startup,unit 1 set bit invalid + uint16_t u16PeriodVal; ///< Period value +} stc_timera_base_init_t; + +/** + ******************************************************************************* + ** \brief Timera compare output init structure definition + ******************************************************************************/ +typedef struct stc_timera_compare_init +{ + uint16_t u16CompareVal; ///< Compare value + en_timera_count_start_output_t enStartCountOutput; ///< Port status set when count start + en_timera_count_stop_output_t enStopCountOutput; ///< Port status set when count stop + en_timera_compare_match_output_t enCompareMatchOutput; ///< Port status set when compare value match + en_timera_period_match_output_t enPeriodMatchOutput; ///< Port status set when period value match + en_timera_specify_output_t enSpecifyOutput; ///< Specify port status,next period valid,priority more than other port status set + en_functional_state_t enCacheEn; ///< Enable/Disable cache，Only unit 1、3、5、7 valid + en_functional_state_t enTriangularTroughTransEn; ///< Enable/Disable triangular wave trough transmit cache value，Only unit 1、3、5、7 valid + en_functional_state_t enTriangularCrestTransEn; ///< Enable/Disable triangular wave crest transmit cache value，Only unit 1、3、5、7 valid + uint16_t u16CompareCacheVal; ///< Compare cache value,Only unit 1、3、5、7 valid +} stc_timera_compare_init_t; + +/** + ******************************************************************************* + ** \brief Timera capture input init structure definition + ******************************************************************************/ +typedef struct stc_timera_capture_init +{ + en_functional_state_t enCapturePwmRisingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample rising + en_functional_state_t enCapturePwmFallingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample falling + en_functional_state_t enCaptureSpecifyEventEn; ///< Enable/Disable capture channel n active when specify event trigger,event value is TMRA_HTSSR1 + en_timera_filter_clk_div_t enPwmClkDiv; ///< TIMA__PWMn filter clock select + en_functional_state_t enPwmFilterEn; ///< Enable/Disable TIMA__PWMn filter functions + en_functional_state_t enCaptureTrigRisingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample rising, only CCONR4 valid + en_functional_state_t enCaptureTrigFallingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample falling, only CCONR4 valid + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select, only CCONR4 valid + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions , only CCONR4 valid +} stc_timera_capture_init_t; + +/** + ******************************************************************************* + ** \brief Timera Orthogonal coding init structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6 + ******************************************************************************/ +typedef struct stc_timera_orthogonal_coding_init +{ + en_functional_state_t enIncClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enIncTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enIncSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enIncAnotherUnitOverflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enIncAnotherUnitUnderflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_functional_state_t enDecClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enDecTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enDecSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enDecAnotherUnitUnderflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enDecAnotherUnitOverflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_timera_filter_clk_div_t enClkAClkDiv; ///< TIMA__CLKA filter clock select + en_functional_state_t enClkAFilterEn; ///< Enable/Disable TIMA__CLKA filter functions + en_timera_filter_clk_div_t enClkBClkDiv; ///< TIMA__CLKB filter clock select + en_functional_state_t enClkBFilterEn; ///< Enable/Disable TIMA__CLKB filter functions + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions +} stc_timera_orthogonal_coding_init_t; + +/** + ******************************************************************************* + ** \brief Timera hardware startup config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note TMRA_HTSSR0 trigger startup only when unit 2~6 valid,unit 1 is invalid + ******************************************************************************/ +typedef struct stc_timera_hw_startup_config +{ + en_functional_state_t enTrigRisingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample rising edge(sync start valid) + en_functional_state_t enTrigFallingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample falling edge(sync start valid) + en_functional_state_t enSpecifyEventStartupEn; ///< Hardware startup TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_startup_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware stop config structure definition + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef struct stc_timera_hw_stop_config +{ + en_functional_state_t enTrigRisingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventStopEn; ///< Hardware stop TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_stop_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware clear config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6 + ******************************************************************************/ +typedef struct stc_timera_hw_clear_config +{ + en_functional_state_t enTrigRisingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventClearEn; ///< Hardware clear TIMA_ when TIMA_HTSSR0 register Specify event trigger + en_functional_state_t enAnotherUnitTrigRisingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample rising when current unit is m. + en_functional_state_t enAnotherUnitTrigFallingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample falling when current unit is m. + en_functional_state_t enChannel3RisingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample rising edge + en_functional_state_t enChannel3FallingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample falling edge +} stc_timera_hw_clear_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware trigger init structure definition + ******************************************************************************/ +typedef struct stc_timera_hw_trigger_init +{ + stc_timera_hw_startup_config_t stcHwStartup; ///< Hardware startup condition config + stc_timera_hw_stop_config_t stcHwStop; ///< Hardware stop condition config + stc_timera_hw_clear_config_t stcHwClear; ///< Hardware clear condition config +} stc_timera_hw_trigger_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit); +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt); +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period); +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); + +/* Compare output functions */ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit); +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal); +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache); +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta); +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); + +/* Capture input functions */ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit); +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); + +/* Orthogonal coding functions */ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit); +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt); +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); + +/* Hardware control functions */ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit); +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup); +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop); +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear); + +/* interrupt and flags functions */ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); + +/* Event config functions */ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); + +//@} // TimeraGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TIMERA_ENABLE */ + +#endif /* __HC32F460_TIMERA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h new file mode 100644 index 000000000..6131a9ca1 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h @@ -0,0 +1,100 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.h + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ +#ifndef __HC32F460_TRNG_H__ +#define __HC32F460_TRNG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TrngGroup True Random Number Generator(TRNG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* The data register loads the new initial value from the random number + generator before the random number is generated. */ +typedef enum en_trng_load_ctrl +{ + TrngLoadNewInitValue_Disable = 0x0, ///< Disable load new initial values. + TrngLoadNewInitValue_Enable = 0x1, ///< Enable load new initial values. +} en_trng_load_ctrl_t; + +/* Shift n times when capturing random noise. */ +typedef enum en_trng_shift_cnt +{ + TrngShiftCount_32 = 0x3, ///< Shift 32 times when capturing random noise. + TrngShiftCount_64 = 0x4, ///< Shift 64 times when capturing random noise. + TrngShiftCount_128 = 0x5, ///< Shift 128 times when capturing random noise. + TrngShiftCount_256 = 0x6, ///< Shift 256 times when capturing random noise. +} en_trng_shift_cnt_t; + +/* TRNG initialization structure definition. */ +typedef struct stc_trng_init +{ + en_trng_load_ctrl_t enLoadCtrl; ///< @ref en_trng_load_ctrl_t. + en_trng_shift_cnt_t enShiftCount; ///< @ref en_trng_shift_cnt_t. +} stc_trng_init_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit); +void TRNG_DeInit(void); +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout); + +void TRNG_StartIT(void); +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length); + +//@} // TrngGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TRNG_ENABLE */ + +#endif /* __HC32F460_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h new file mode 100644 index 000000000..144745581 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h @@ -0,0 +1,359 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.h + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ +#ifndef __HC32F460_USART_H__ +#define __HC32F460_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_USART_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup UsartGroup Universal Synchronous Asynchronous Receiver \ + ** Transmitter(USART) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief USART tx mode in multiple processor mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_mp_tx_mode +{ + UsartMpTxData = 0u, ///< USART Send data in multiple-processor mode + UsartMpTxId = 1u, ///< USART Send ID in multiple-processor mode +} en_usart_mp_tx_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock prescale enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_div +{ + UsartClkDiv_1 = 0u, ///< PCLK/1 + UsartClkDiv_4 = 1u, ///< PCLK/4 + UsartClkDiv_16 = 2u, ///< PCLK/16 + UsartClkDiv_64 = 3u, ///< PCLK/64 +} en_usart_clk_div_t; + +/** + ****************************************************************************** + ** \brief USART mode + ** + ******************************************************************************/ +typedef enum en_usart_mode +{ + UsartUartMode = 0u, ///< UART mode + UsartClkSyncMode = 1u, ///< Clock sync mode + UsartSmartCardMode = 2u, ///< Smart card mode +} en_usart_mode_t; + +/** + ****************************************************************************** + ** \brief USART data direction + ** + ******************************************************************************/ +typedef enum en_usart_data_dir +{ + UsartDataLsbFirst = 0u, ///< LSB first + UsartDataMsbFirst = 1u, ///< MSB first +} en_usart_data_dir_t; + +/** + ****************************************************************************** + ** \brief USART sample mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sample_mode +{ + UsartSampleBit16 = 0u, ///< 16 Bit + UsartSampleBit8 = 1u, ///< 8 Bit +} en_usart_sample_mode_t; + +/** + ****************************************************************************** + ** \brief USART data length enumeration + ** + ******************************************************************************/ +typedef enum en_usart_data_len +{ + UsartDataBits8 = 0u, ///< 8 Bit + UsartDataBits9 = 1u, ///< 9 Bit +} en_usart_data_len_t; + +/** + ****************************************************************************** + ** \brief USART parity format enumeration + ** + ******************************************************************************/ +typedef enum en_usart_parity +{ + UsartParityNone = 0u, ///< No parity bit is used. + UsartParityEven = 1u, ///< Even parity bit is used. + UsartParityOdd = 2u, ///< Odd parity bit is used. +} en_usart_parity_t; + +/** + ****************************************************************************** + ** \brief USART functions enumeration + ** + ******************************************************************************/ +typedef enum en_usart_func +{ + UsartRx = 0u, ///< UART RX function + UsartRxInt = 1u, ///< USART RX interrupt function + UsartTx = 2u, ///< UART TX function + UsartTxEmptyInt = 3u, ///< USART TX empty interrupt function + UsartTimeOut = 4u, ///< UART RX timeout function + UsartTimeOutInt = 5u, ///< UART RX timeout interrupt function + UsartSilentMode = 6u, ///< USART silent function + UsartTxCmpltInt = 7u, ///< USART TX complete interrupt function + UsartTxAndTxEmptyInt = 8u, ///< USART TX function and USART TX empty interrupt function + UsartParityCheck = 9u, ///< USART Parity check function + UsartNoiseFilter = 10u, ///< USART noise filter function + UsartFracBaudrate = 11u, ///< USART fractional baudrate function + UsartMulProcessor = 12u, ///< USART multiple processor function + UsartSmartCard = 13u, ///< USART smart card mode function + UsartCts = 14u, ///< USART CTS function +} en_usart_func_t; + +/** + ******************************************************************************* + ** \brief USART status type enumeration + ** + ******************************************************************************/ +typedef enum en_usart_status +{ + UsartParityErr = (1u << 0), ///< USART parity error + UsartFrameErr = (1u << 1), ///< USART receive frame error + UsartOverrunErr = (1u << 3), ///< USART receive over-run error + UsartRxNoEmpty = (1u << 5), ///< USART data receive register is not empty + UsartTxComplete = (1u << 6), ///< USART transfer completely + UsartTxEmpty = (1u << 7), ///< USART data transfer register is empty + UsartRxTimeOut = (1u << 8), ///< USART data receive timeout + UsartRxMpb = (1u << 16), ///< USART multiple processor id or normal data, 0: receive date; 1: received ID +} en_usart_status_t; + +/** + ******************************************************************************* + ** \brief USART Stop bit length select enumeration + ** + ******************************************************************************/ +typedef enum en_usart_stop_bit +{ + UsartOneStopBit = 0u, ///< 1 Stop Bit + UsartTwoStopBit = 1u, ///< 2 Stop Bit +} en_usart_stop_bit_t; + +/** + ******************************************************************************* + ** \brief USART start bit detect mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sb_detect_mode +{ + UsartStartBitLowLvl = 0u, ///< Start bit: RD pin low level + UsartStartBitFallEdge = 1u, ///< Start bit: RD pin falling edge +} en_usart_sb_detect_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_mode +{ + UsartIntClkCkNoOutput = 0u, ///< Select internal clock source and don't output clock. + UsartIntClkCkOutput = 1u, ///< Select internal clock source and output clock. + UsartExtClk = 2u, ///< Select external clock source. +} en_usart_clk_mode_t; + +/** + ******************************************************************************* + ** \brief USART smart-card mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_hw_flow_ctrl +{ + UsartRtsEnable = 0u, ///< Enable RTS function. + UsartCtsEnable = 1u, ///< Enable CTS function. +} en_usart_hw_flow_ctrl_t; + +/** + ****************************************************************************** + ** \brief USART etu clocks of smart card enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sc_etu_clk +{ + UsartScEtuClk32 = 0u, ///< 1 etu = 32/f + UsartScEtuClk64 = 1u, ///< 1 etu = 64/f + UsartScEtuClk128 = 3u, ///< 1 etu = 128/f + UsartScEtuClk256 = 5u, ///< 1 etu = 256/f + UsartScEtuClk372 = 6u, ///< 1 etu = 372/f +} en_usart_sc_etu_clk_t; + +/** + ******************************************************************************* + ** \brief Uart mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_uart_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_len_t enDataLength; ///< 8/9 Bit character length and this parameter can be a value of @ref en_usart_data_len_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_stop_bit_t enStopBit; ///< Stop bit and this parameter can be a value of @ref en_usart_stop_bit_t + + en_usart_parity_t enParity; ///< Parity format and this parameter can be a value of @ref en_usart_parity_t + + en_usart_sample_mode_t enSampleMode; ///< USART sample mode, and this parameter can be a value of @ref en_usart_sample_mode_t + + en_usart_sb_detect_mode_t enDetectMode; ///< USART start bit detect mode and this parameter can be a value of @ref en_usart_sb_detect_mode_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_uart_init_t; + +/** + ******************************************************************************* + ** \brief Clock sync mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_clksync_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_clksync_init_t; + +/** + ******************************************************************************* + ** \brief Smart card mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_sc_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t +} stc_usart_sc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg); +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg); +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg); +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx); +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd); +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity); +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx); +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode); +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir); +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen); +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode); +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode); +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit); +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode); +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl); +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale); +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx); +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk); +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx); +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data); +uint16_t USART_RecData(M4_USART_TypeDef *USARTx); +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +//@} // UsartGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_USART_ENABLE */ + +#endif /* __HC32F460_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h new file mode 100644 index 000000000..d4eda9861 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h @@ -0,0 +1,108 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.h + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ +#ifndef __HC32F460_UTILITY_H__ +#define __HC32F460_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlUtilityGroup Device Driver Library Utility(DDLUTILITY) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/* A approximate delay */ +void Ddl_Delay1ms(uint32_t u32Cnt); +void Ddl_Delay1us(uint32_t u32Cnt); + +/* Systick functions */ +en_result_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +/*! Ddl assert, you can add your own assert functions by implement the function +Ddl_AssertHook definition follow the function Ddl_AssertHook declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do{ \ + ((x) ? (void)0 : Ddl_AssertHandler((uint8_t *)__FILE__, __LINE__)); \ +}while(0) +/* Exported function */ +void Ddl_AssertHandler(uint8_t *file, int16_t line); +#else +#define DDL_ASSERT(x) (void)(0) +#endif /* __DEBUG */ + +#if (DDL_PRINT_ENABLE == DDL_ON) +#include + +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)); + +#define DDL_PrintfInit (void)UART_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(x, y, z) +#define DDL_Printf(fmt, ...) +#endif + +//@} // DdlUtilityGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_UTILITY_ENABLE */ + +#endif /* __HC32F460_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h new file mode 100644 index 000000000..0ae3521d2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.h + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_WDT_H__ +#define __HC32F460_WDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_WDT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup WdtGroup WatchDog Counter(WDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief WDT count cycle enumeration + ******************************************************************************/ +typedef enum en_wdt_count_cycle +{ + WdtCountCycle256 = 0u, ///< 256 cycle + WdtCountCycle4096 = 1u, ///< 4096 cycle + WdtCountCycle16384 = 2u, ///< 16384 cycle + WdtCountCycle65536 = 3u, ///< 65536 cycle +} en_wdt_count_cycle_t; + +/** + ******************************************************************************* + ** \brief WDT count clock division enumeration + ******************************************************************************/ +typedef enum en_wdt_clk_div +{ + WdtPclk3Div4 = 2u, ///< PCLK3/4 + WdtPclk3Div64 = 6u, ///< PCLK3/64 + WdtPclk3Div128 = 7u, ///< PCLK3/128 + WdtPclk3Div256 = 8u, ///< PCLK3/256 + WdtPclk3Div512 = 9u, ///< PCLK3/512 + WdtPclk3Div1024 = 10u, ///< PCLK3/1024 + WdtPclk3Div2048 = 11u, ///< PCLK3/2048 + WdtPclk3Div8192 = 13u, ///< PCLK3/8192 +} en_wdt_clk_div_t; + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range enumeration + ******************************************************************************/ +typedef enum en_wdt_refresh_range +{ + WdtRefresh100Pct = 0u, ///< 100% + WdtRefresh0To25Pct = 1u, ///< 0%~25% + WdtRefresh25To50Pct = 2u, ///< 25%~50% + WdtRefresh0To50Pct = 3u, ///< 0%~50% + WdtRefresh50To75Pct = 4u, ///< 50%~75% + WdtRefresh0To25PctAnd50To75Pct = 5u, ///< 0%~25% & 50%~75% + WdtRefresh25To75Pct = 6u, ///< 25%~75% + WdtRefresh0To75Pct = 7u, ///< 0%~75% + WdtRefresh75To100Pct = 8u, ///< 75%~100% + WdtRefresh0To25PctAnd75To100Pct = 9u, ///< 0%~25% & 75%~100% + WdtRefresh25To50PctAnd75To100Pct = 10u, ///< 25%~50% & 75%~100% + WdtRefresh0To50PctAnd75To100Pct = 11u, ///< 0%~50% & 75%~100% + WdtRefresh50To100Pct = 12u, ///< 50%~100% + WdtRefresh0To25PctAnd50To100Pct = 13u, ///< 0%~25% & 50%~100% + WdtRefresh25To100Pct = 14u, ///< 25%~100% + WdtRefresh0To100Pct = 15u, ///< 0%~100% +} en_wdt_refresh_range_t; + +/** + ******************************************************************************* + ** \brief WDT refresh error or count underflow trigger event type enumeration + ******************************************************************************/ +typedef enum en_wdt_event_request_type +{ + WdtTriggerInterruptRequest = 0u, ///< Interrupt request + WdtTriggerResetRequest = 1u, ///< Reset request +} en_wdt_event_request_type_t; + +/** + ******************************************************************************* + ** \brief WDT flag type enumeration + ******************************************************************************/ +typedef enum en_wdt_flag_type +{ + WdtFlagCountUnderflow = 0u, ///< Count underflow flag + WdtFlagRefreshError = 1u, ///< Refresh error flag +} en_wdt_flag_type_t; + +/** + ******************************************************************************* + ** \brief WDT init structure definition + ******************************************************************************/ +typedef struct stc_wdt_init +{ + en_wdt_count_cycle_t enCountCycle; ///< Count cycle + en_wdt_clk_div_t enClkDiv; ///< Count clock division + en_wdt_refresh_range_t enRefreshRange; ///< Allow refresh percent range + en_functional_state_t enSleepModeCountEn; ///< Enable/disable count in the sleep mode + en_wdt_event_request_type_t enRequestType; ///< Refresh error or count underflow trigger event type +} stc_wdt_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +en_result_t WDT_RefreshCounter(void); +uint16_t WDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag); +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag); + +//@} // WdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_WDT_ENABLE */ + +#endif /* __HC32F460_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c new file mode 100644 index 000000000..da61a4ca9 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c @@ -0,0 +1,1739 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.c + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_adc.h" +#include "hc32f460_utility.h" + +#if (DDL_ADC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ADC peripherals. */ +#define IS_ADC_PERIPH(ADCx) \ +( ((ADCx) == M4_ADC1) || \ + ((ADCx) == M4_ADC2)) + +/*! Parameter validity check for ADC1 channel index. */ +#define IS_ADC1_CH_INDEX(x) \ +( ((x) < ADC1_CH_COUNT)) + +/*! Parameter validity check for ADC2 channel index. */ +#define IS_ADC2_CH_INDEX(x) \ +( ((x) < ADC2_CH_COUNT)) + +/*! Parameter validity check for ADC average count. */ +#define IS_ADC_AVCNT(AVCNT) \ +( ((AVCNT) == AdcAvcnt_2) || \ + (((AVCNT) >= AdcAvcnt_4) && ((AVCNT) <= AdcAvcnt_256))) + +/*! Parameter validity check for ADC data alignment. */ +#define IS_ADC_DATA_ALIGN(ALIGN) \ +( ((ALIGN) == AdcDataAlign_Right) || \ + ((ALIGN) == AdcDataAlign_Left)) + +/*! Parameter validity check for ADC auto clear DR. */ +#define IS_ADC_CLREN(EN) \ +( ((EN) == AdcClren_Enable) || \ + ((EN) == AdcClren_Disable)) + +/*! Parameter validity check for ADC resolution. */ +#define IS_ADC_RESOLUTION(RESOLUTION) \ +( ((RESOLUTION) == AdcResolution_8Bit) || \ + ((RESOLUTION) == AdcResolution_10Bit) || \ + ((RESOLUTION) == AdcResolution_12Bit)) + +/*! Parameter validity check for ADC scan convert mode. */ +#define IS_ADC_SCAN_MODE(MODE) \ +( ((MODE) == AdcMode_SAOnce) || \ + ((MODE) == AdcMode_SAContinuous) || \ + ((MODE) == AdcMode_SAOnceSBOnce) || \ + ((MODE) == AdcMode_SAContinuousSBOnce)) + +/*! Parameter validity check for ADC RSCHSEL. */ +#define IS_ADC_RSCHSEL(SEL) \ +( ((SEL) == AdcRschsel_Continue) || \ + ((SEL) == AdcRschsel_Restart)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGEN(EN) \ +( ((EN) == AdcTrgen_Enable) || \ + ((EN) == AdcTrgen_Disable)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGSEL(SEL) \ +( ((SEL) == AdcTrgsel_ADTRGX) || \ + ((SEL) == AdcTrgsel_TRGX0) || \ + ((SEL) == AdcTrgsel_TRGX1) || \ + ((SEL) == AdcTrgsel_TRGX0_TRGX1)) + +/*! Parameter validity check for ADC common trigger. */ +#define IS_ADC_COM_TRIGGER(x) \ +( ((x) == AdcComTrigger_1) || \ + ((x) == AdcComTrigger_2) || \ + ((x) == AdcComTrigger_1_2)) + +/*! Parameter validity check for ADC EOCAIEN/ENCBIEN. */ +#define IS_ADC_EOCIEN(EN) \ +( ((EN) == AdcEocien_Disable) || \ + ((EN) == AdcEocien_Enable)) + +/*! Parameter validity check for ADC sampling time. */ +#define IS_ADC_SAMPLE_TIME(TIME) \ +( ((TIME) == 255u) || \ + (((TIME) >= 5u) && ((TIME) <= 254u))) + +/*! Parameter validity check for ADC sync trigger mode. */ +#define IS_ADC_SYNC_MODE(MODE) \ +( ((MODE) == AdcSync_SingleSerial) || \ + ((MODE) == AdcSync_SingleParallel) || \ + ((MODE) == AdcSync_ContinuousSerial) || \ + ((MODE) == AdcSync_ContinuousParallel)) + +/*! Parameter validity check for ADC sync able. */ +#define IS_ADC_SYNC_ENABLE(EN) \ +( ((EN) == AdcSync_Disable) || \ + ((EN) == AdcSync_Enable)) + +/*! Parameter validity check for ADC ADWIEN */ +#define IS_ADC_AWDIEN(EN) \ +( ((EN) == AdcAwdInt_Disable) || \ + ((EN) == AdcAwdInt_Enable)) + +/*! Parameter validity check for ADC AWDSS */ +#define IS_ADC_AWDSS(SS) \ +( ((SS) == AdcAwdSel_SA_SB) || \ + ((SS) == AdcAwdSel_SA) || \ + ((SS) == AdcAwdSel_SB) || \ + ((SS) == AdcAwdSel_SB_SA)) + +/*! Parameter validity check for ADC AWDMD */ +#define IS_ADC_AWDMD(MD) \ +( ((MD) == AdcAwdCmpMode_0) || \ + ((MD) == AdcAwdCmpMode_1)) + +/*! Parameter validity check for ADC AWDEN */ +#define IS_ADC_AWDEN(EN) \ +( ((EN) == AdcAwd_Disable) || \ + ((EN) == AdcAwd_Enable)) + +/*! Parameter validity check for ADC PGA control */ +#define IS_ADC_PGA_CTL(CTL) \ +( ((CTL) == AdcPgaCtl_Invalid) || \ + ((CTL) == AdcPgaCtl_Amplify)) + +/*! Parameter validity check for ADC gain factor. */ +#define IS_ADC_PGA_FACTOR(FACTOR) \ +( ((FACTOR) == AdcPgaFactor_2) || \ + (((FACTOR) >= AdcPgaFactor_2P133) && ((FACTOR) <= AdcPgaFactor_32))) + +/*! Parameter validity check for ADC PGA negative. */ +#define IS_ADC_PGA_NEGATIVE(N) \ +( ((N) == AdcPgaNegative_VSSA) || \ + ((N) == AdcPgaNegative_PGAVSS)) + +/*! Parameter validity check for ADC trigger source event . */ +#define IS_ADC_TRIG_SRC_EVENT(x) \ +( ((x) == EVT_PORT_EIRQ0) || \ + (((x) > EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcInit Pointer to ADC initialization structure. + ** See @ref stc_adc_init_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcInit)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcInit->enResolution)); + DDL_ASSERT(IS_ADC_DATA_ALIGN(pstcInit->enDataAlign)); + DDL_ASSERT(IS_ADC_CLREN(pstcInit->enAutoClear)); + DDL_ASSERT(IS_ADC_SCAN_MODE(pstcInit->enScanMode)); + DDL_ASSERT(IS_ADC_RSCHSEL(pstcInit->enRschsel)); + + /* Stop ADC conversion. */ + ADCx->STR = 0u; + + ADCx->CR0_f.ACCSEL = pstcInit->enResolution; + ADCx->CR0_f.DFMT = pstcInit->enDataAlign; + ADCx->CR0_f.CLREN = pstcInit->enAutoClear; + ADCx->CR0_f.MS = pstcInit->enScanMode; + ADCx->CR1_f.RSCHSEL = pstcInit->enRschsel; + + /* Disable EOC(End Of Conversion) interrupts default. */ + ADCx->ICR = (uint8_t)0x0; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + /* Set the value of all registers to the reset value. */ + /* Stop ADC conversion. */ + ADCx->STR = 0u; + ADCx->CR0 = 0u; + ADCx->CR1 = 0u; + ADCx->TRGSR = 0u; + ADCx->CHSELRA0 = 0u; + ADCx->CHSELRB0 = 0u; + ADCx->AVCHSELR0 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->SSTR0 = (uint8_t)0x0B; + ADCx->SSTR1 = (uint8_t)0x0B; + ADCx->SSTR2 = (uint8_t)0x0B; + ADCx->SSTR3 = (uint8_t)0x0B; + ADCx->SSTR4 = (uint8_t)0x0B; + ADCx->SSTR5 = (uint8_t)0x0B; + ADCx->SSTR6 = (uint8_t)0x0B; + ADCx->SSTR7 = (uint8_t)0x0B; + ADCx->SSTR8 = (uint8_t)0x0B; + ADCx->CHMUXR0 = (uint16_t)0x3210; + ADCx->CHMUXR1 = (uint16_t)0x7654; + ADCx->ISR = 0u; + ADCx->ICR = (uint8_t)0x03; + ADCx->AWDCR = 0u; + ADCx->AWDDR0 = 0u; + ADCx->AWDDR1 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->AWDSR0 = 0u; + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 = 0u; + ADCx->CHSELRB1 = 0u; + ADCx->AVCHSELR1 = 0u; + ADCx->CHMUXR2 = (uint16_t)0xBA98; + ADCx->CHMUXR3 = (uint16_t)0xFEDC; + ADCx->SYNCCR = (uint16_t)0x0C00; + ADCx->AWDCHSR1 = 0u; + ADCx->AWDSR1 = 0u; + ADCx->PGACR = 0u; + ADCx->PGAGSR = 0u; + ADCx->PGAINSR0 = 0u; + ADCx->PGAINSR1 = 0u; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan mode. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param[in] enMode See @ref en_adc_scan_mode_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_SCAN_MODE(enMode)); + + ADCx->CR0_f.MS = enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcTrgCfg Pointer to ADC trigger source configuration structure. + ** \arg u8Sequence The sequence which you want to set it's trigger source. + ** \arg enTrgEnable Enable or disable trigger source. + ** \arg enTrgSel The type of trigger source. + ** \arg enInTrg0 Event number @ref en_event_src_t. + ** \arg enInTrg1 Event number @ref en_event_src_t. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same trigger source. + ** + ******************************************************************************/ +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, + const stc_adc_trg_cfg_t *pstcTrgCfg) +{ + uint32_t u32TrgSelR; + __IO uint32_t *io32AdcxTrgSelR0; + __IO uint32_t *io32AdcxTrgSelR1; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && + (NULL != pstcTrgCfg) && + (pstcTrgCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(pstcTrgCfg->enTrgSel)); + + if (ADC_SEQ_A == pstcTrgCfg->u8Sequence) + { + ADCx->TRGSR_f.TRGSELA = pstcTrgCfg->enTrgSel; + } + else + { + ADCx->TRGSR_f.TRGSELB = pstcTrgCfg->enTrgSel; + } + + if (AdcTrgsel_ADTRGX != pstcTrgCfg->enTrgSel) + { + if (M4_ADC1 == ADCx) + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC1_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC1_ITRGSELR1); + } + else + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC2_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC2_ITRGSELR1); + } + + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg0)); + + u32TrgSelR = *io32AdcxTrgSelR0; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg0; + *io32AdcxTrgSelR0 = u32TrgSelR; + } + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg1)); + + u32TrgSelR = *io32AdcxTrgSelR1; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg1; + *io32AdcxTrgSelR1 = u32TrgSelR; + } + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to set it's trigger source. + ** + ** \param [in] enState Enable or disable trigger source. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (ADC_SEQ_A == u8Seq) + { + ADCx->TRGSR_f.TRGENA = enState; + } + else + { + ADCx->TRGSR_f.TRGENB = enState; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC common trigger. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enTrgSel ADC trigger source type. See @ref en_adc_trgsel_t for details. + ** + ** \param [in] enComTrigger ADC common trigger selection. See @ref en_adc_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + uint32_t u32ITRGSELRAddr; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(enTrgSel) && (enTrgSel != AdcTrgsel_ADTRGX)); + DDL_ASSERT(IS_ADC_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (M4_ADC1 == ADCx) + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC1_ITRGSELR0; + } + else + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC2_ITRGSELR0; + } + + u32ComTrig <<= 30u; + + if ((enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } + + if ((enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + u32ITRGSELRAddr += 4ul; + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } +} + +/** + ******************************************************************************* + ** \brief Add ADC channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcChCfg Pointer to ADC channel configuration structure. + ** \arg u32Channel The channel(s) you want to configure. + ** \arg u8Sequence The sequence which the channel(s) belong(s) to. + ** \arg pu8SampTime Pointer to sampling time. + ** eg. u32Channel = 1001b + ** pu8SampTime[0] = channel 0's time + ** pu8SampTime[1] = channel 3's time + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same channel!!! + ** + ******************************************************************************/ +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32ChannelSel; + __IO uint8_t *io8Sstr; + + if ((NULL != ADCx) && + (NULL != pstcChCfg) && + (pstcChCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32ChannelSel = pstcChCfg->u32Channel & ADC1_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRA1 |= (uint16_t)(u32ChannelSel >> 16u); + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRB1 |= (uint16_t)(u32ChannelSel >> 16u); + } + } + else + { + u32ChannelSel = pstcChCfg->u32Channel & ADC2_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + } + } + + /* Set sampling time */ + i = 0u; + j = 0u; + io8Sstr = &(ADCx->SSTR0); + while (0u != u32ChannelSel) + { + if (u32ChannelSel & 0x1ul) + { + io8Sstr[i] = pstcChCfg->pu8SampTime[j++]; + } + u32ChannelSel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete ADC channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s) you want to delete. + ** \arg ADC1_CH0 ~ ADC1_CH16 + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note You can use this function to delete ADC channel(s) + ** and then set the corresponding pin(s) of the channel(s) + ** to the other mode you need in your application. + ** + ******************************************************************************/ +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->CHSELRA0 &= (uint16_t)(~u16ChSelR0); + ADCx->CHSELRB0 &= (uint16_t)(~u16ChSelR0); + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 &= (uint16_t)(~u16ChSelR1); + ADCx->CHSELRB1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC interrupt configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence to be configured. + ** + ** \param [in] enState Enable or Disable sequence conversion done interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8Msk = 0u; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u8Msk = (uint8_t)(0x1ul << u8Seq); + ADCx->ISR &= (uint8_t)(~u8Msk); + + if (Enable == enState) + { + ADCx->ICR |= u8Msk; + } + else + { + ADCx->ICR &= (uint8_t)(~u8Msk); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC average conversion configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enAvgCnt Average after enAvgCnt conversions. + ** See @ref en_adc_avcnt_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AVCNT(enAvgCnt)); + + ADCx->CR0_f.AVCNT = enAvgCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as average channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 |= u16AvgChR0; + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 |= u16AvgChR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The average channel(s) which you want to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 &= (uint16_t)(~u16AvgChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 &= (uint16_t)(~u16AvgChR1); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC AWD(analog watch dog) configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcAwdCfg Pointer to the configuration structure. + ** See @ref stc_adc_awd_cfg_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcAwdCfg)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AWDMD(pstcAwdCfg->enAwdmd)); + DDL_ASSERT(IS_ADC_AWDSS(pstcAwdCfg->enAwdss)); + + ADCx->AWDCR_f.AWDEN = AdcAwd_Disable; + ADCx->AWDCR_f.AWDIEN = AdcAwdInt_Disable; + ADCx->AWDCR_f.AWDMD = pstcAwdCfg->enAwdmd; + ADCx->AWDCR_f.AWDSS = pstcAwdCfg->enAwdss; + + ADCx->AWDDR0 = pstcAwdCfg->u16AwdDr0; + ADCx->AWDDR1 = pstcAwdCfg->u16AwdDr1; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog) interrupt. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDIEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as AWD channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 |= u16ChSelR0; + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 |= u16ChSelR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The AWD channel(s) which you are going to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 &= (uint16_t)(~u16ChSelR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC programmable gain amplifier(PGA) configuration. + ** + ** \param [in] enFactor PGA gain factor. + ** \param [in] enNegativeIn PGA negative input select. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. + ** + ******************************************************************************/ +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn) +{ + DDL_ASSERT(IS_ADC_PGA_FACTOR(enFactor)); + DDL_ASSERT(IS_ADC_PGA_NEGATIVE(enNegativeIn)); + + M4_ADC1->PGAGSR_f.GAIN = enFactor; + M4_ADC1->PGAINSR1_f.PGAVSSEN = enNegativeIn; +} + +/** + ******************************************************************************* + ** \brief Enable or disable PGA. + ** + ** \param [in] enState Enable or disable PGA. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_PgaCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (Enable == enState) + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Amplify; + } + else + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Invalid; + } +} + +/** + ******************************************************************************* + ** \brief Add PGA channel(s). + ** + ** \param[in] u32Channel The channel(s), which you want to gain. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. The channel must first + ** be configured as an analog channel + ** by function ADC_AddAdcChannel + ** + ******************************************************************************/ +void ADC_AddPgaChannel(uint32_t u32Channel) +{ + M4_ADC1->PGAINSR0 |= ((uint16_t)(u32Channel & PGA_CH_ALL)); +} + +/** + ******************************************************************************* + ** \brief Delete PGA channel(s). + ** + ** \param[in] u32Channel The PGA channel(s) which will be deleted. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_DelPgaChannel(uint32_t u32Channel) +{ + M4_ADC1->PGAINSR0 &= (uint16_t)(~u32Channel); +} + +/** + ******************************************************************************* + ** \brief ADC sync mode configuration. + ** + ** \param [in] enMode Synchronous mode types. + ** \param [in] u8TrgDelay ADC2 trigger delay time. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay) +{ + DDL_ASSERT(IS_ADC_SYNC_MODE(enMode)); + + /* Disable synchronous mode first. */ + M4_ADC1->SYNCCR_f.SYNCEN = AdcSync_Disable; + + M4_ADC1->SYNCCR_f.SYNCMD = enMode; + M4_ADC1->SYNCCR_f.SYNCDLY = u8TrgDelay; +} + +/** + ******************************************************************************* + ** \brief Enable or disable sync mode. + ** + ** \param [in] enState Enable or disable sync mode. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_SyncCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_ADC1->SYNCCR_f.SYNCEN = enState; +} + +/** + ******************************************************************************* + ** \brief Start an ADC conversion. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note Software startup only support sequence A. + ** + ******************************************************************************/ +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->STR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop an ADC conversion and clear flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32TimeCount = 0u; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + /* Make sure the ADC is really stopped. */ + while (ADCx->STR == 1u) + { + /* Stop ADC conversion. */ + ADCx->STR = 0u; + if (++u32TimeCount > 10000u) + { + enRet = ErrorTimeout; + break; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the conversion status flag. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to get + ** it's conversion status flag. + ** + ** \retval Set ADC converted done. + ** \retval Reset ADC is converting or parameter error. + ** + ******************************************************************************/ +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (ADCx->ISR & ((uint8_t)(0x1ul << u8Seq))) + { + enFlag = Set; + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear conversion status flag of sequence A or sequence B. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to clear + ** it's conversion status flag. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->ISR &= (uint8_t)(~(0x1ul << u8Seq)); + } +} + +/** + ******************************************************************************* + ** \brief ADC start sequence A, check it's EOC status and get the data. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address to store ADC value. + ** The location of the data store depends on + ** the parameter u8Length. + ** u8Length >= ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** all of the ADC data regs will be read: + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** u8Length < ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** only the data of the enabled channles will be read: + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval OperationInProgress ADC is converting. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, + uint16_t *pu16AdcData, + uint8_t u8Length, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8AllDataLength = 0u; + uint32_t u32Channel = 0u; + uint32_t u32AdcTimeout = 0u; + __IO uint32_t u32TimeCount = 0u; + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + if (u8Length >= ADC1_CH_COUNT) + { + u8AllDataLength = ADC1_CH_COUNT; + } + else + { + u32Channel = (uint32_t)ADCx->CHSELRA1; + u32Channel <<= 16u; + u32Channel |= (uint32_t)ADCx->CHSELRA0; + } + } + else + { + if (u8Length >= ADC2_CH_COUNT) + { + u8AllDataLength = ADC2_CH_COUNT; + } + else + { + u32Channel = (uint32_t)M4_ADC1->CHSELRA0; + } + } + + /* Start ADC conversion. */ + ADCx->STR = (uint8_t)0x01; + + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32AdcTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32AdcTimeout) + { + if (ADCx->ISR_f.EOCAF) + { + /* Get ADC data. */ + if (u8AllDataLength) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8AllDataLength); + } + else + { + ADC_GetChData(ADCx, u32Channel, pu16AdcData, u8Length); + } + + /* Clear sequence A flag. */ + ADCx->ISR_f.EOCAF = 0u; + enRet = Ok; + break; + } + u32TimeCount++; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading all data regs of an ADC. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + if (((M4_ADC1 == ADCx) && (u8Length >= ADC1_CH_COUNT)) || + ((M4_ADC2 == ADCx) && (u8Length >= ADC2_CH_COUNT))) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8Length); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading the data of the specified channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u32TargetCh The specified channel(s) + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** eg. u32TargetCh = 1001b + ** pu16AdcData[0] = Channel 0's data, + ** pu16AdcData[1] = Channel 3's data, + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, + uint32_t u32TargetCh, + uint16_t *pu16AdcData, + uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32Channel; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel = u32TargetCh & ADC1_CH_ALL; + } + else + { + u32Channel = u32TargetCh & ADC2_CH_ALL; + } + + i = 0u; + j = 0u; + while ((0u != u32Channel) && (0u != u8Length)) + { + if (0u != (u32Channel & 0x1ul)) + { + pu16AdcData[j] = pu16DataReg[i]; + j++; + u8Length--; + } + + u32Channel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the value of a specified channel via channel index. + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u8ChIndex The index of the specified channel. + ** u8ChIndex < ADC1_CH_COUNT while ADCx == M4_ADC1; + ** u8ChIndex < ADC2_CH_COUNT while ADCx == M4_ADC2. + ** + ** \retval An uint16_t value -- the ADC value of the specified channel. + ** + ******************************************************************************/ +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + return pu16DataReg[u8ChIndex]; +} + +/** + ******************************************************************************* + ** \brief Get all AWD channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval u32AwdFlag 0 -- No ADC channel meets AWD comparison conditions. + ** !0 -- The bit value of the channel that satisfies the + ** AWD condition is 1. + ** + ******************************************************************************/ +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx) +{ + uint32_t u32AwdFlag; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32AwdFlag = ADCx->AWDSR1; + u32AwdFlag <<= 16u; + u32AwdFlag |= ADCx->AWDSR0; + } + else + { + u32AwdFlag = ADCx->AWDSR0; + } + + return u32AwdFlag; +} + +/** + ******************************************************************************* + ** \brief Clear all AWD channels status flags + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->AWDSR0 = 0u; + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR0 = 0u; + ADCx->AWDSR1 = 0u; + } + } +} + +/** + ******************************************************************************* + ** \brief Clear AWD specified channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32AwdCh The channel(s) which you want to clear it's flag(s). + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh) +{ + uint16_t u16ChR0; + uint16_t u16ChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChR0 = (uint16_t)u32AwdCh; + u16ChR1 = (uint16_t)(u32AwdCh >> 16u); + + ADCx->AWDSR0 &= (uint16_t)(~u16ChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR1 &= (uint16_t)(~u16ChR1); + } + } +} + +/** + ******************************************************************************* + ** \brief Remap an ADC pin to channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32DestChannel Destination channel(s). + ** + ** \param [in] u8AdcPin ADC pin number. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, + uint32_t u32DestChannel, + uint8_t u8AdcPin) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint16_t u16AdcPin = u8AdcPin; + __IO uint16_t *io16Chmuxr = NULL; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + if (M4_ADC1 == ADCx) + { + if (u16AdcPin <= ADC1_IN15) + { + u32DestChannel &= ADC1_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + else + { + if ((u16AdcPin > ADC12_IN4) && (u16AdcPin < ADC12_IN11)) + { + u16AdcPin -= 4u; + u32DestChannel &= ADC2_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + i = 0u; + while (0u != u32DestChannel) + { + if (u32DestChannel & 0x1ul) + { + u8OffsetReg = i / 4u; + u8ChPos = (i % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + *io16Chmuxr &= (uint16_t)(~(0xFul << u8ChPos)); + *io16Chmuxr |= (uint16_t)(u16AdcPin << u8ChPos); + } + + u32DestChannel >>= 1u; + i++; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the number of the pin corresponding to the specified channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8ChIndex This channel that you want to get its pin number. + ** + ** \retval [0, 15] The correct ADC pin number. + ** \retval [0xFF] The invalid ADC pin number. + ** + ******************************************************************************/ +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + uint8_t u8OffsetPin; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint8_t u8AdcPin = ADC_PIN_INVALID; + __IO const uint16_t *io16Chmuxr = NULL; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + DDL_ASSERT(IS_ADC1_CH_INDEX(u8ChIndex)); + u8OffsetPin = 0u; + } + else + { + DDL_ASSERT(IS_ADC2_CH_INDEX(u8ChIndex)); + u8OffsetPin = 4u; + } + + u8OffsetReg = u8ChIndex / 4u; + u8ChPos = (u8ChIndex % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + u8AdcPin = (uint8_t)((*io16Chmuxr >> u8ChPos) & ((uint16_t)0xF)); + u8AdcPin += u8OffsetPin; + + return u8AdcPin; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Read all data of an ADC. pu16AdcData[0] = DR0, pu16AdcData[1] = DR1, ... + ** + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + uint8_t i; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + for (i = 0u; i < u8Length; i++) + { + pu16AdcData[i] = pu16DataReg[i]; + } +} + +//@} // AdcGroup + +#endif /* DDL_ADC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c new file mode 100644 index 000000000..d549d30a8 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c @@ -0,0 +1,311 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.c + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_aes.h" +#include "hc32f460_utility.h" + +#if (DDL_AES_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup AesGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* AES block length in bytes is 16. */ +#define AES_BLOCK_LEN ((uint8_t)16) + +/* Each encryption operation takes 440 system clock cycles. */ +#define AES_ENCRYPT_TIMEOUT (440u) + +/* Each decryption operation takes 580 system clock cycles. */ +#define AES_DECRYPT_TIMEOUT (580u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData); +static void AES_ReadData(uint8_t *pu8Dest); +static void AES_WriteKey(const uint8_t *pu8Key); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief AES128 encryption(ECB mode). + ** + ** \param [in] pu8Plaintext Pointer to plaintext(the source data which will be encrypted) + ** + ** \param [in] u32PlaintextSize Length of plaintext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Ciphertext The destination address to store the result of the encryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Plaintext) && + (0u != u32PlaintextSize) && + (NULL != pu8Key) && + (NULL != pu8Ciphertext) && + (0u == (u32PlaintextSize & 0xFu)) && /* u32PlaintextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Plaintext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32PlaintextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Plaintext[u32Index]); + + /* Set AES encrypt. */ + bM4_AES_CR_MODE = 0u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_ENCRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Ciphertext[u32Index]); + u32PlaintextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief AES128 decryption(ECB mode). + ** + ** \param [in] pu8Ciphertext Pointer to ciphertext(the source data which will be decrypted) + ** + ** \param [in] u32CiphertextSize Length of ciphertext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Plaintext The destination address to store the result of the decryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Ciphertext) && + (0u != u32CiphertextSize) && + (NULL != pu8Key) && + (NULL != pu8Plaintext) && + (0u == (u32CiphertextSize & 0xFu)) && /* u32CiphertextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Plaintext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32CiphertextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Ciphertext[u32Index]); + + /* Set AES decrypt. */ + bM4_AES_CR_MODE = 1u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_DECRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Plaintext[u32Index]); + u32CiphertextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint32_t u32SrcAddr = (uint32_t)pu8SrcData; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32DrAddr = *(uint32_t*)u32SrcAddr; + u32SrcAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Reads the from data register. + ** + ** \param [out] pu8Dest Pointer to the destination buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_ReadData(uint8_t *pu8Dest) +{ + uint8_t i; + uint32_t u32DestAddr = (uint32_t)pu8Dest; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(uint32_t*)u32DestAddr = *(__IO uint32_t *)u32DrAddr; + u32DestAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Writes the input buffer in key register. + ** + ** \param [in] pu8Key Pointer to AES key. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteKey(const uint8_t *pu8Key) +{ + uint8_t i; + uint32_t u32SrcKeyAddr = (uint32_t)pu8Key; + uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32KeyAddr = *(uint32_t*)u32SrcKeyAddr; + u32SrcKeyAddr += 4u; + u32KeyAddr += 4u; + } +} + +//@} // AesGroup + +#endif /* DDL_AES_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c new file mode 100644 index 000000000..ff08fe118 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c @@ -0,0 +1,532 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.c + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-12-13 CDT First version for Device Driver Library of CAN. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_can.h" +#include "hc32f460_utility.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CanGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u) +#define CAN_RESET_DISABLE() \ +do{ \ + do{ \ + M4_CAN->CFG_STAT_f.RESET = 0u; \ +}while(M4_CAN->CFG_STAT_f.RESET); \ +}while(0) + +#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr)) + +#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u) +#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u) + + +/*! Parameter validity check for CAN Mode \a CanMode. */ +#define IS_CAN_MODE_VALID(CanMode) \ +( (CanExternalLoopBackMode == (CanMode)) || \ + (CanInternalLoopBackMode == (CanMode)) || \ + (CanTxSignalPrimaryMode == (CanMode)) || \ + (CanTxSignalSecondaryMode == (CanMode)) || \ + (CanListenOnlyMode == (CanMode)) \ +) + +/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */ +#define IS_TX_CMD_VALID(TxCmd) \ +( (CanPTBTxCmd == (TxCmd)) || \ + (CanPTBTxAbortCmd == (TxCmd)) || \ + (CanSTBTxOneCmd == (TxCmd)) || \ + (CanSTBTxAllCmd == (TxCmd)) || \ + (CanSTBTxAbortCmd == (TxCmd)) \ +) + +/*! Parameter validity check for CAN status \a enCanStatus. */ +#define IS_CAN_STATUS_VALID(enCanStatus) \ +( (CanRxActive == (enCanStatus)) || \ + (CanTxActive == (enCanStatus)) || \ + (CanBusoff == (enCanStatus)) \ +) + +/*! Parameter validity check for CAN Irq type \a enCanIrqType. */ +#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \ +( (CanRxIrqEn == (enCanIrqType)) || \ + (CanRxOverIrqEn == (enCanIrqType)) || \ + (CanRxBufFullIrqEn == (enCanIrqType)) || \ + (CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \ + (CanTxPrimaryIrqEn == (enCanIrqType)) || \ + (CanTxSecondaryIrqEn == (enCanIrqType)) || \ + (CanErrorIrqEn == (enCanIrqType)) || \ + (CanErrorPassiveIrqEn == (enCanIrqType)) || \ + (CanArbiLostIrqEn == (enCanIrqType)) || \ + (CanBusErrorIrqEn == (enCanIrqType)) \ +) + +/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */ +#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \ +( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxIrqFlg == (enCanIrqFLg)) || \ + (CanRxOverIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \ + (CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \ + (CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \ + (CanErrorIrqFlg == (enCanIrqFLg)) || \ + (CanAbortIrqFlg == (enCanIrqFLg)) || \ + (CanErrorWarningIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \ + (CanArbiLostIrqFlg == (enCanIrqFLg)) || \ + (CanBusErrorIrqFlg == (enCanIrqFLg)) \ +) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the can base functions + ** + ** \param [in] pstcCanInitCfg The can initial config struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_Init(stc_can_init_config_t *pstcCanInitCfg) +{ + if (NULL != pstcCanInitCfg) + { + M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck; + M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode; + M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll; + M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode; + + M4_CAN->RTIE = 0x00u; + + CAN_RESET_ENABLE(); + + M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC; + M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1; + M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2; + M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW; + + M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal; + M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal; + + CAN_RESET_DISABLE(); + } +} + +/** + ******************************************************************************* + ** \brief De-Init (RESET CAN register) + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_DeInit(void) +{ + CAN_RESET_ENABLE(); +} + +/** + ******************************************************************************* + ** \brief Configures the can Mode + ** + ** \param [in] enMode The can mode enum. @ref en_can_mode_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_MODE_VALID(enMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(CanListenOnlyMode == enMode) + { + M4_CAN->TCMD_f.LOM = enNewState; + }else + { + if(Enable == enNewState) + { + M4_CAN->CFG_STAT |= enMode; + }else + { + M4_CAN->CFG_STAT &= ~enMode; + } + } + +} + + +/** + ******************************************************************************* + ** \brief Configures the can acceptance filter + ** + ** \param [in] pstcFilter The can filter config struct. + ** @ref stc_can_filter_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState) +{ + if(NULL != pstcFilter) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CAN_RESET_ENABLE(); + + //<ACFCTRL_f.ACFADR = pstcFilter->enFilterSel; + + //<ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL; + M4_CAN->ACF = pstcFilter->u32CODE; + + //<ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL; + M4_CAN->ACF = pstcFilter->u32MASK; + + //<ACF_f.AIDEE = ((pstcFilter->enAcfFormat >> 1ul) & 0x01u); + M4_CAN->ACF_f.AIDE = (pstcFilter->enAcfFormat & 0x01ul); + + if(Enable == enNewState) + { + M4_CAN->ACFEN |= (uint8_t)(1ul << pstcFilter->enFilterSel); + }else + { + M4_CAN->ACFEN &= (uint8_t)(~(1ul << (pstcFilter->enFilterSel))); + } + + CAN_RESET_DISABLE(); + } +} + + +/** + ******************************************************************************* + ** \brief Configures the can Tx frame set + ** + ** \param [in] pstcTxFrame The can Tx frame struct. + ** @ref stc_can_txframe_t + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame) +{ + uint32_t u32TBUFAddr; + + if(NULL != pstcTxFrame) + { + u32TBUFAddr = (uint32_t)&M4_CAN->TBUF; + M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel; + CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0; + CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1; + CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0]; + CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1]; + + if(CanSTBSel == pstcTxFrame->enBufferSel) + { + M4_CAN->TCTRL_f.TSNEXT = Enable; + } + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx Command + ** + ** \param [in] enTxCmd The can Tx Command. + ** + ** \retval Can Tx buffer status @ref en_can_tx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd) +{ + DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd)); + + M4_CAN->TCMD |= enTxCmd; + + return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT; + +} + +/** + ******************************************************************************* + ** \brief Configures the can Rx frame + ** + ** \param [in] pstcRxFrame The can Rx frame. + ** @ref stc_can_rxframe_t + ** \retval Can rx buffer status @ref en_can_rx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame) +{ + uint32_t u32RBUFAddr; + + if(NULL != pstcRxFrame) + { + u32RBUFAddr = (uint32_t)&M4_CAN->RBUF; + pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr); + pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4); + pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8); + pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12); + + M4_CAN->RCTRL_f.RREL = 1u; + } + return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSSTAT; +} + + +/** + ******************************************************************************* + ** \brief Get the can Error Status + ** + ** \param None + ** + ** \retval en_can_error_t The can error status + ** + ** \note None + ** + ******************************************************************************/ +en_can_error_t CAN_ErrorStatusGet(void) +{ + en_can_error_t enRet = UNKOWN_ERROR; + + if(6u > M4_CAN->EALCAP_f.KOER) + { + enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER; + } + return enRet; + +} + +/** + ******************************************************************************* + ** \brief Get the can Status + ** + ** \param enCanStatus The can status + ** \arg true + ** \arg false + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_StatusGet(en_can_status_t enCanStatus) +{ + bool bRet = false; + DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus)); + + if(M4_CAN->CFG_STAT & enCanStatus) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Configures the can Interrupt enable + ** + ** \param [in] enCanIrqType The can interrupt type. + ** \param [in] enNewState The new state of the can interrupt. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState) +{ + volatile uint32_t *u32pIE; + + DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if(Enable == enNewState) + { + *u32pIE |= enCanIrqType; + }else + { + *u32pIE &= ~((uint32_t)enCanIrqType); + } + +} + +/** + ******************************************************************************* + ** \brief Get the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt Flag. + ** + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + bool bRet = false; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if( *u32pIE & enCanIrqFlgType) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Clear the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt type. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + uint32_t u32IETempMsk = 0xFF2A00FF; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + *u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType); +} + + +/** + ******************************************************************************* + ** \brief Get the can Rx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_RxErrorCntGet(void) +{ + return M4_CAN->RECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Tx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_TxErrorCntGet(void) +{ + return M4_CAN->TECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Arbitration lost captrue + ** + ** \param None + ** + ** \retval address(0~31) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_ArbitrationLostCap(void) +{ + return M4_CAN->EALCAP_f.ALC; +} + + +//@} // CanGroup + +#endif /* DDL_CAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c new file mode 100644 index 000000000..eda867759 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c @@ -0,0 +1,1813 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.c + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_clk.h" +#include "hc32f460_utility.h" + +#if (DDL_CLK_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_XTAL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_XTAL32_TIMEOUT ((uint8_t)0x05u) +#define CLK_HRC_TIMEOUT ((uint16_t)0x1000u) +#define CLK_MRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_LRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_MPLL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_UPLL_TIMEOUT ((uint16_t)0x1000u) + +/* TBDs 30us based 200M frequency. */ +#define CLK_FCG_STABLE ((uint16_t)0x200u) +#define CLK_SYSCLK_STABLE ((uint16_t)0x200u) +#define CLK_USBCLK_STABLE ((uint16_t)0x200u) + +#define CLK_PLL_DIV_MIN (2u) +#define CLK_PLL_DIV_MAX (16u) + +#define CLK_PLLQ_DIV_MIN (1u) +#define CLK_PLLQ_DIV_MAX (16u) + +#define CLK_PLLN_MIN (20u) +#define CLK_PLLN_MAX (480u) + +#define CLK_PLLM_MIN (1u) +#define CLK_PLLM_MAX (24u) + +#define CLK_UPLLM_MIN (2u) +#define CLK_UPLLM_MAX (24u) + +#define CLK_PLL_VCO_IN_MIN (1u*1000u*1000u) +#define CLK_PLL_VCO_IN_MAX (24u*1000u*1000u) + +#define CLK_PLL_VCO_OUT_MIN (240u*1000u*1000u) +#define CLK_PLL_VCO_OUT_MAX (480u*1000u*1000u) + +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa501u) +#define DISABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~1u)))) + +#define ENABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + + +#define DEFAULT_FCG0 (0xFFFFFAEEul) +#define DEFAULT_FCG1 (0xFFFFFFFFul) +#define DEFAULT_FCG2 (0xFFFFFFFFul) +#define DEFAULT_FCG3 (0xFFFFFFFFul) +#define FCG2_WITHOUT_EMB (0xFFFF7FFFul) + +#define FCG0_OFFSET_FCM (16ul) +#define FCG1_OFFSET_CAN (0ul) +#define FCG1_OFFSET_QSPI (3ul) +#define FCG1_OFFSET_USBFS (8ul) +#define FCG1_OFFSET_SPI1 (16ul) +#define FCG1_OFFSET_SPI2 (17ul) +#define FCG1_OFFSET_SPI3 (18ul) +#define FCG1_OFFSET_SPI4 (19ul) +#define FCG3_OFFSET_ADC1 (0ul) +#define FCG3_OFFSET_ADC2 (1ul) +#define FCG3_OFFSET_DAC (4ul) + +/*! Parameter validity check for XTAL stablization time \a stb. */ +#define IS_XTAL_STB_VALID(stb) \ +( (ClkXtalStbCycle35 <= (stb)) && \ + (ClkXtalStbCycle8163 >= (stb))) + +/*! Parameter validity check for pll source \a src. */ +#define IS_PLL_SOURCE(src) \ +( (ClkPllSrcXTAL == (src)) || \ + (ClkPllSrcHRC == (src))) + +/*! Parameter validity check for mpll div \a pllp, pllr, upll div \a pllp, pllq, pllr*/ +#define IS_PLL_DIV_VALID(pllx) \ +( (CLK_PLL_DIV_MIN <= (pllx)) && \ + (CLK_PLL_DIV_MAX >= (pllx))) + +/*! Parameter validity check for pll div \a pllq. */ +#define IS_PLLQ_DIV_VALID(pllx) \ +( (CLK_PLLQ_DIV_MIN <= (pllx)) && \ + (CLK_PLLQ_DIV_MAX >= (pllx))) + +/*! Parameter validity check for plln \a plln. */ +#define IS_PLLN_VALID(plln) \ +( (CLK_PLLN_MIN <= (plln)) && \ + (CLK_PLLN_MAX >= (plln))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_PLLM_VALID(pllm) \ +( (CLK_PLLM_MIN <= (pllm)) && \ + (CLK_PLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_UPLLM_VALID(pllm) \ +( (CLK_UPLLM_MIN <= (pllm)) && \ + (CLK_UPLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllsource/pllm \a vco_in. */ +#define IS_PLL_VCO_IN_VALID(vco_in) \ +( (CLK_PLL_VCO_IN_MIN <= (vco_in)) && \ + (CLK_PLL_VCO_IN_MAX >= (vco_in))) + +/*! Parameter validity check for pllsource/pllm*plln \a vco_out. */ +#define IS_PLL_VCO_OUT_VALID(vco_out) \ +( (CLK_PLL_VCO_OUT_MIN <= (vco_out)) && \ + (CLK_PLL_VCO_OUT_MAX >= (vco_out))) + +/*! Parameter validity check for system clock source \a syssrc. */ +#define IS_SYSCLK_SOURCE(syssrc) \ +( (ClkSysSrcHRC == (syssrc)) || \ + ((ClkSysSrcMRC <= (syssrc)) && \ + (CLKSysSrcMPLL >= (syssrc)))) + +/*! Parameter validity check for usb clock source \a usbsrc. */ +#define IS_USBCLK_SOURCE(usbsrc) \ +( ((ClkUsbSrcSysDiv2 <= (usbsrc)) && \ + (ClkUsbSrcSysDiv4 >= (usbsrc))) || \ + ((ClkUsbSrcMpllp <= (usbsrc)) && \ + (ClkUsbSrcUpllr >= (usbsrc)))) + +/*! Parameter validity check for peripheral(adc/trng/I2S) clock source \a adcsrc. */ +#define IS_PERICLK_SOURCE(adcsrc) \ +( (ClkPeriSrcPclk == (adcsrc)) || \ + ((ClkPeriSrcMpllp <= (adcsrc)) && \ + (ClkPeriSrcUpllr >= (adcsrc)))) + +/*! Parameter validity check for output clock source \a outsrc. */ +#define IS_OUTPUTCLK_SOURCE(outsrc) \ +( (ClkOutputSrcHrc == (outsrc)) || \ + (ClkOutputSrcMrc == (outsrc)) || \ + (ClkOutputSrcLrc == (outsrc)) || \ + (ClkOutputSrcXtal == (outsrc)) || \ + (ClkOutputSrcXtal32 == (outsrc)) || \ + (ClkOutputSrcMpllp == (outsrc)) || \ + (ClkOutputSrcUpllp == (outsrc)) || \ + (ClkOutputSrcMpllq == (outsrc)) || \ + (ClkOutputSrcUpllq == (outsrc)) || \ + (ClkOutputSrcSysclk == (outsrc))) + +/*! Parameter validity check for fcm source \a fcmsrc. */ +#define IS_FCM_SOURCE(fcmsrc) \ +( (ClkFcmSrcXtal == (fcmsrc)) || \ + ((ClkFcmSrcXtal32 <= (fcmsrc)) && \ + (ClkFcmSrcRtcLrc >= (fcmsrc)))) + +/*! Parameter validity check for output clock channel \a outch. */ +#define IS_OUTPUTCLK_CHANNEL(outch) \ +( (ClkOutputCh1 == (outch)) || \ + (ClkOutputCh2 == (outch))) + +/*! Parameter validity check for fcm reference \a ref. */ +#define IS_FCM_REF(ref) \ +( (ClkFcmExtRef == (ref)) || \ + (ClkFcmInterRef == (ref))) + +/*! Parameter validity check for fcm edge \a edge. */ +#define IS_FCM_EDGE(edge) \ +( (ClkFcmEdgeRising == (edge)) || \ + (ClkFcmEdgeFalling == (edge)) || \ + (ClkFcmEdgeBoth == (edge))) + +/*! Parameter validity check for fcm filter clock \a clk. */ +#define IS_FCM_FILTER_CLK(clk) \ +( (ClkFcmFilterClkNone == (clk)) || \ + (ClkFcmFilterClkFcmSrc == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv4 == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv16 == (clk))) + +/*! Parameter validity check for fcm abnormal handle \a handle. */ +#define IS_FCM_HANDLE(handle) \ +( (ClkFcmHandleInterrupt == (handle)) || \ + (ClkFcmHandleReset == (handle))) + +/*! Parameter validity check for debug clock division \a div. */ +#define IS_TPIUCLK_DIV_VALID(div) \ +( (ClkTpiuclkDiv1 == (div)) || \ + (ClkTpiuclkDiv2 == (div)) || \ + (ClkTpiuclkDiv4 == (div))) + +/*! Parameter validity check for output clock division \a div. */ +#define IS_OUTPUTCLK_DIV_VALID(div) \ +( (ClkOutputDiv1 == (div)) || \ + ((ClkOutputDiv2 <= (div)) && \ + (ClkOutputDiv128 >= (div)))) + +/*! Parameter validity check for fcm measurement source division \a div. */ +#define IS_FCM_MEASRC_DIV_VALID(div) \ +( (ClkFcmMeaDiv1 == (div)) || \ + (ClkFcmMeaDiv4 == (div)) || \ + (ClkFcmMeaDiv8 == (div)) || \ + (ClkFcmMeaDiv32 == (div))) + +/*! Parameter validity check for internal reference source division \a div. */ +#define IS_FCM_INTREF_DIV_VALID(div) \ +( (ClkFcmIntrefDiv32 == (div)) || \ + (ClkFcmIntrefDiv128 == (div)) || \ + (ClkFcmIntrefDiv1024 == (div)) || \ + (ClkFcmIntrefDiv8192 == (div))) + +/*! Parameter validity check for system clock config \a cfg. */ +#define IS_SYSCLK_CONFIG_VALID(cfg) \ +( ((cfg)->enHclkDiv <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk3Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk4Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk3Div)) && \ + (((cfg)->enPclk2Div-(cfg)->enPclk4Div == 3) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 2) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 1) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 0) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 1) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 2) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 3))) + + +/*! Parameter validity check for clock status \a flag. */ +#define IS_CLK_FLAG(flag) \ +( (ClkFlagHRCRdy == (flag)) || \ + (ClkFlagXTALRdy == (flag)) || \ + (ClkFlagMPLLRdy == (flag)) || \ + (ClkFlagUPLLRdy == (flag)) || \ + (ClkFlagXTALStoppage == (flag))) +/*! Parameter validity check for fcm status \a flag. */ +#define IS_FCM_FLAG(flag) \ +( (ClkFcmFlagOvf == (flag)) || \ + (ClkFcmFlagMendf == (flag)) || \ + (ClkFcmFlagErrf == (flag))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the external high speed oscillator(XTAL). + ** + ** \param [in] pstcXtalCfg The XTAL configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg) +{ + if(NULL != pstcXtalCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALCFGR_f.SUPDRV = pstcXtalCfg->enFastStartup; + M4_SYSREG->CMU_XTALCFGR_f.XTALMS = pstcXtalCfg->enMode; + M4_SYSREG->CMU_XTALCFGR_f.XTALDRV = pstcXtalCfg->enDrv; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stable time. + ** + ** \param [in] enXtalStb The XTAL stable time. + ** + ** \retval None + ** + ** \note One of the stable clock is 1/8 LRC clock. + ** + ******************************************************************************/ +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb) +{ + DDL_ASSERT(IS_XTAL_STB_VALID(enXtalStb)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTBCR_f.XTALSTB = enXtalStb; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stoppage. + ** + ** \param [in] pstcXtalStpCfg The XTAL stoppage configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg) +{ + if(NULL != pstcXtalStpCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDE = pstcXtalStpCfg->enDetect; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRIS = pstcXtalStpCfg->enMode; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRE = pstcXtalStpCfg->enModeReset; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDIE = pstcXtalStpCfg->enModeInt; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL. + ** + ** \param [in] enNewState The new state of the XTAL. + ** \arg Enable Enable XTAL. + ** \arg Disable Disable XTAL. + ** + ** \retval en_result_t + ** + ** \note XTAL can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0u; + en_flag_status_t status; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagXTALRdy); + timeout++; + }while((timeout < CLK_XTAL_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the external low speed oscillator(XTAL32). + ** + ** \param [in] pstcXtal32Cfg The XTAL32 configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg) +{ + if(NULL != pstcXtal32Cfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTAL32CFGR_f.XTAL32DRV = pstcXtal32Cfg->enDrv; + M4_SYSREG->CMU_XTAL32NFR_f.XTAL32NF = pstcXtal32Cfg->enFilterMode; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL32. + ** + ** \param [in] enNewState The new state of the XTAL32. + ** \arg Enable Enable XTAL32. + ** \arg Disable Disable XTAL32. + ** + ** \retval en_result_t + ** + ** \note XTAL32 can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL32 == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 0u; + do + { + timeout++; + }while(timeout < CLK_XTAL32_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal high speed oscillator(HRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_HrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_HRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the HRC. + ** + ** \param [in] enNewState The new state of the HRC. + ** \arg Enable Enable HRC. + ** \arg Disable Disable HRC. + ** + ** \retval en_result_t + ** + ** \note HRC can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + en_result_t enRet = Ok; + + ENABLE_CLOCK_REG_WRITE(); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if(Disable == enNewState) + { + if(ClkSysSrcHRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcHRC == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagHRCRdy); + timeout++; + }while((timeout < CLK_HRC_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal middle speed oscillator(MRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_MrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_MRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MRC. + ** + ** \param [in] enNewState The new state of the MRC. + ** \arg Enable Enable MRC. + ** \arg Disable Disable MRC. + ** + ** \retval en_result_t + ** + ** \note MRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcMRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_MRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal low speed oscillator(LRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_LrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_LRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the LRC. + ** + ** \param [in] enNewState The new state of the LRC. + ** \arg Enable Enable LRC. + ** \arg Disable Disable LRC. + ** + ** \retval en_result_t + ** + ** \note LRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcLRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_LRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select pll clock source. + ** + ** \param [in] enPllSrc The pll clock source. + ** \arg ClkPllSrcXTAL Select XTAL as pll clock source. + ** \arg ClkPllSrcHRC Select HRC as pll clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc) +{ + DDL_ASSERT(IS_PLL_SOURCE(enPllSrc)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.PLLSRC = enPllSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the MPLL. + ** + ** \param [in] pstcMpllCfg The MPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcMpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLLQ_DIV_VALID(pstcMpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcMpllCfg->plln)); + DDL_ASSERT(IS_PLLM_VALID(pstcMpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcMpllCfg->pllmDiv); + vcoOut = vcoIn * pstcMpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.MPLLP = pstcMpllCfg->PllpDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLQ = pstcMpllCfg->PllqDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLR = pstcMpllCfg->PllrDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLN = pstcMpllCfg->plln - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLM = pstcMpllCfg->pllmDiv - 1ul; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MPLL. + ** + ** \param [in] enNewState The new state of the MPLL. + ** \arg Enable Enable MPLL. + ** \arg Disable Disable MPLL. + ** + ** \retval en_result_t + ** + ** \note MPLL can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagMPLLRdy); + timeout++; + }while((timeout < CLK_MPLL_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the UPLL. + ** + ** \param [in] pstcUpllCfg The UPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcUpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcUpllCfg->plln)); + DDL_ASSERT(IS_UPLLM_VALID(pstcUpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcUpllCfg->pllmDiv); + vcoOut = vcoIn * pstcUpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCFGR_f.UPLLP = pstcUpllCfg->PllpDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ = pstcUpllCfg->PllqDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLR = pstcUpllCfg->PllrDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLN = pstcUpllCfg->plln - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLM = pstcUpllCfg->pllmDiv - 1u; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the UPLL. + ** + ** \param [in] enNewState The new state of the UPLL. + ** \arg Enable Enable UPLL. + ** \arg Disable Disable UPLL. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t CLK_UpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCR_f.UPLLOFF = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_CLOCK_REG_WRITE(); + + do + { + status = CLK_GetFlagStatus(ClkFlagUPLLRdy); + timeout++; + }while((timeout < CLK_UPLL_TIMEOUT) && (status != ((Enable == enNewState) ? Set : Reset))); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] enTargetSysSrc The system clock source. + ** \arg ClkSysSrcHRC Select HRC as system clock source. + ** \arg ClkSysSrcMRC Select MRC as system clock source. + ** \arg ClkSysSrcLRC Select LRC as system clock source. + ** \arg ClkSysSrcXTAL Select XTAL as system clock source. + ** \arg ClkSysSrcXTAL32 Select XTAL32 as system clock source. + ** \arg CLKSysSrcMPLL Select MPLL as system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** + ******************************************************************************/ +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + DDL_ASSERT(IS_SYSCLK_SOURCE(enTargetSysSrc)); + + ENABLE_FCG0_REG_WRITE(); + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) || + (CLKSysSrcMPLL == enTargetSysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = enTargetSysSrc; + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + + SystemCoreClockUpdate(); +} + +/** + ******************************************************************************* + ** \brief Get system clock source. + ** + ** \param None + ** + ** \retval The system clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_sys_source_t CLK_GetSysClkSource(void) +{ + return (en_clk_sys_source_t)M4_SYSREG->CMU_CKSWR_f.CKSW; +} + + +/** + ******************************************************************************* + ** \brief Configures the division factor for hclk,exck,pclk0,pclk1,pclk2,pclk3, + ** pclk4 from system clock. + ** + ** \param [in] pstcSysclkCfg The system clock configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + ENABLE_FCG0_REG_WRITE(); + + if(NULL != pstcSysclkCfg) + { + DDL_ASSERT(IS_SYSCLK_CONFIG_VALID(pstcSysclkCfg)); + + /* Only current system clock source is MPLL need to close fcg0~fcg3 and + open fcg0~fcg3 during switch system clock division. + We need to backup fcg0~fcg3 before close them. */ + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock division. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_SCFGR = ( (uint32_t)pstcSysclkCfg->enPclk0Div | + ((uint32_t)pstcSysclkCfg->enPclk1Div << 4u) | + ((uint32_t)pstcSysclkCfg->enPclk2Div << 8u) | + ((uint32_t)pstcSysclkCfg->enPclk3Div << 12u) | + ((uint32_t)pstcSysclkCfg->enPclk4Div << 16u) | + ((uint32_t)pstcSysclkCfg->enExclkDiv << 20u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 24u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 28u)); + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + else + { + /* code */ + } +} + + +/** + ******************************************************************************* + ** \brief Get clock frequency. + ** + ** \param [in] pstcClkFreq The clock source struct. + ** + ** \retval The clock frequency include system clock,hclk,exck,pclk0,pclk1,pclk2 + ** pclk3,pclk4. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq) +{ + uint32_t plln = 0u, pllp = 0u, pllm = 0u, pllsource = 0u; + + if(NULL != pstcClkFreq) + { + /* Get system clock. */ + switch(M4_SYSREG->CMU_CKSWR_f.CKSW) + { + case ClkSysSrcHRC: + /* HRC used as system clock. */ + pstcClkFreq->sysclkFreq = HRC_VALUE; + break; + case ClkSysSrcMRC: + /* MRC used as system clock. */ + pstcClkFreq->sysclkFreq = MRC_VALUE; + break; + case ClkSysSrcLRC: + /* LRC used as system clock. */ + pstcClkFreq->sysclkFreq = LRC_VALUE; + break; + case ClkSysSrcXTAL: + /* XTAL used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL_VALUE; + break; + case ClkSysSrcXTAL32: + /* XTAL32 used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL32_VALUE; + break; + default: + /* MPLLP used as system clock. */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + if (ClkPllSrcXTAL == pllsource) + { + pstcClkFreq->sysclkFreq = (XTAL_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcClkFreq->sysclkFreq = (HRC_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else + { + //else + } + break; + } + + /* Get hclk. */ + pstcClkFreq->hclkFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.HCLKS; + + /* Get exck. */ + pstcClkFreq->exckFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.EXCKS; + + /* Get pclk0. */ + pstcClkFreq->pclk0Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK0S; + + /* Get pclk1. */ + pstcClkFreq->pclk1Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK1S; + + /* Get pclk2. */ + pstcClkFreq->pclk2Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK2S; + + /* Get pclk3. */ + pstcClkFreq->pclk3Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK3S; + + /* Get pclk4. */ + pstcClkFreq->pclk4Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK4S; + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Get PLL clock frequency. + ** + ** \param [in] pstcPllClkFreq The PLL clock source struct. + ** + ** \retval The clock frequency include mpllp, mpllq, mpllr, upllp, upllq, upllr. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq) +{ + uint32_t pllsource; + uint32_t mplln = 0u, mpllp = 0u, mpllq = 0u, mpllr = 0u, mpllm = 0u; + uint32_t uplln = 0u, upllp = 0u, upllq = 0u, upllr = 0u, upllm = 0u; + + /* Get pll clock source */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + + /* Get Mpll parameter value */ + mpllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + mpllq = M4_SYSREG->CMU_PLLCFGR_f.MPLLQ; + mpllr = M4_SYSREG->CMU_PLLCFGR_f.MPLLR; + mplln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + mpllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* Get Upll paramter value */ + upllp = M4_SYSREG->CMU_UPLLCFGR_f.UPLLP; + upllq = M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ; + upllr = M4_SYSREG->CMU_UPLLCFGR_f.UPLLR; + uplln = M4_SYSREG->CMU_UPLLCFGR_f.UPLLN; + upllm = M4_SYSREG->CMU_UPLLCFGR_f.UPLLM; + + /* Get mpllp ,mpllr, mpllq, upllp, upllq, upllr clock frequency */ + if (ClkPllSrcXTAL == pllsource) + { + pstcPllClkFreq->mpllp = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcPllClkFreq->mpllp = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Select usb clock source. + ** + ** \param [in] enTargetUsbSrc The usb clock source. + ** \arg ClkUsbSrcSysDiv2 Select 1/2 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv3 Select 1/3 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv4 Select 1/4 system clock as usb clock source. + ** \arg ClkUsbSrcMpllp Select MPLLP as usb clock source. + ** \arg ClkUsbSrcMpllq Select MPLLQ as usb clock source. + ** \arg ClkUsbSrcMpllr Select MPLLR as usb clock source. + ** \arg ClkUsbSrcUpllp Select UPLLP as usb clock source. + ** \arg ClkUsbSrcUpllq Select UPLLQ as usb clock source. + ** \arg ClkUsbSrcUpllr Select UPLLR as usb clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc) +{ + + DDL_ASSERT(IS_USBCLK_SOURCE(enTargetUsbSrc)); + + /* Switch to target usb clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UFSCKCFGR_f.USBCKS = enTargetUsbSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select peripheral(adc/trng) clock source. + ** + ** \param [in] enTargetPeriSrc The peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcPclk Select PCLK2 as adc analog clok, PCLK4 as adc digital clock. Select PCLK4 as trng clock. + ** \arg ClkPeriSrcMpllp Select MPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as peripheral(adc/trng) clock source. + ** + ** \retval None + ** + ******************************************************************************/ +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + /* Switch to target adc clock source. */ + M4_SYSREG->CMU_PERICKSEL_f.PERICKSEL = enTargetPeriSrc; + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] enTargetPeriSrc The I2S clock source. + ** \arg ClkPeriSrcPclk Select PCLK3 as I2S clock source. + ** \arg ClkPeriSrcMpllp Select MPLLP as I2S clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as I2S clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as I2S clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as I2S clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as I2S clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as I2S clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + if(M4_I2S1 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL = enTargetPeriSrc; + } + else if(M4_I2S2 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL = enTargetPeriSrc; + } + else if(M4_I2S3 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL = enTargetPeriSrc; + } + else if(M4_I2S4 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL = enTargetPeriSrc; + } + else + { + /* code */ + } + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval en_clk_peri_source_t The I2S clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg) +{ + en_clk_peri_source_t enI2sClkSource = ClkPeriSrcPclk; + + if(M4_I2S1 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL; + } + else if(M4_I2S2 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL; + } + else if(M4_I2S3 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL; + } + else if(M4_I2S4 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL; + } + else + { + /* code */ + } + + return enI2sClkSource; +} + +/** + ******************************************************************************* + ** \brief Configures the debug clock. + ** + ** \param [in] enTpiuDiv The division of debug clock from system + ** clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv) +{ + DDL_ASSERT(IS_TPIUCLK_DIV_VALID(enTpiuDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKS = enTpiuDiv; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the debug clock. + ** + ** \param [in] enNewState The new state of the debug clock. + ** \arg Enable Enable debug clock. + ** \arg Disable Disable debug clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKOE = enNewState; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the output clock. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] pstcOutputCfg The clock output configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg) +{ + if(NULL != pstcOutputCfg) + { + DDL_ASSERT(IS_OUTPUTCLK_CHANNEL(enCh)); + DDL_ASSERT(IS_OUTPUTCLK_SOURCE(pstcOutputCfg->enOutputSrc)); + DDL_ASSERT(IS_OUTPUTCLK_DIV_VALID(pstcOutputCfg->enOutputDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO1CFGR_f.MCO1DIV = pstcOutputCfg->enOutputDiv; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO2CFGR_f.MCO2DIV = pstcOutputCfg->enOutputDiv; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock output. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1EN = enNewState; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2EN = enNewState; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); +} + + +/** + ******************************************************************************* + ** \brief Get the specified clock flag status. + ** + ** \param [in] enClkFlag The specified clock flag. + ** \arg ClkFlagHRCRdy HRC is ready or not. + ** \arg ClkFlagXTALRdy XTAL is ready or not. + ** \arg ClkFlagMPLLRdy MPLL is ready or not. + ** \arg ClkFlagUPLLRdy UPLL is ready or not. + ** \arg ClkFlagXTALStoppage XTAL is detected stoppage or not. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag) +{ + en_flag_status_t status; + + DDL_ASSERT(IS_CLK_FLAG(enClkFlag)); + + switch(enClkFlag) + { + case ClkFlagHRCRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF) ? Set : Reset); + break; + case ClkFlagXTALRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.XTALSTBF) ? Set : Reset); + break; + case ClkFlagMPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.MPLLSTBF) ? Set : Reset); + break; + case ClkFlagUPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.UPLLSTBF) ? Set : Reset); + break; + default: + status = ((1u == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) ? Set : Reset); + break; + } + + return status; +} + + +/** + ******************************************************************************* + ** \brief Configures the clock frequency measurement. + ** + ** \param [in] pstcClkFcmCfg The clock frequency measurement configures + ** struct. + ** + ** \retval None + ** + ** \note Configures the window,measurement,reference and interrupt independently. + ** + ******************************************************************************/ +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg) +{ + if(NULL != pstcClkFcmCfg) + { + /* Window config. */ + if(pstcClkFcmCfg->pstcFcmWindowCfg) + { + /* Set window lower. */ + M4_FCM->LVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowLower; + /* Set window upper. */ + M4_FCM->UVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowUpper; + } + + /* Measure config. */ + if(pstcClkFcmCfg->pstcFcmMeaCfg) + { + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmMeaCfg->enSrc)); + DDL_ASSERT(IS_FCM_MEASRC_DIV_VALID(pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv)); + + /* Measure source. */ + M4_FCM->MCCR_f.MCKS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrc; + /* Measure source division. */ + M4_FCM->MCCR_f.MDIVS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv; + } + + /* Reference config. */ + if(pstcClkFcmCfg->pstcFcmRefCfg) + { + DDL_ASSERT(IS_FCM_REF(pstcClkFcmCfg->pstcFcmRefCfg->enRefSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmRefCfg->enExtRef)); + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc)); + DDL_ASSERT(IS_FCM_INTREF_DIV_VALID(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv)); + DDL_ASSERT(IS_FCM_EDGE(pstcClkFcmCfg->pstcFcmRefCfg->enEdge)); + DDL_ASSERT(IS_FCM_FILTER_CLK(pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk)); + + M4_FCM->RCCR_f.INEXS = pstcClkFcmCfg->pstcFcmRefCfg->enRefSel; + M4_FCM->RCCR_f.EXREFE = pstcClkFcmCfg->pstcFcmRefCfg->enExtRef; + M4_FCM->RCCR_f.RCKS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc; + M4_FCM->RCCR_f.RDIVS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv; + M4_FCM->RCCR_f.EDGES = pstcClkFcmCfg->pstcFcmRefCfg->enEdge; + M4_FCM->RCCR_f.DNFS = pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk; + } + + /* Interrupt config. */ + if(pstcClkFcmCfg->pstcFcmIntCfg) + { + DDL_ASSERT(IS_FCM_HANDLE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt)); + + M4_FCM->RIER_f.ERRINTRS = pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel; + M4_FCM->RIER_f.ERRE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset; + M4_FCM->RIER_f.ERRIE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt; + M4_FCM->RIER_f.MENDIE = pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt; + M4_FCM->RIER_f.OVFIE = pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt; + } + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock frequency measurement. + ** + ** \param [in] enNewState The new state of the clock frequency + ** measurement. + ** \arg Enable Enable clock frequency measurement. + ** \arg Disable Disable clock frequency measurement. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_FcmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_FCM->STR = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get fcm counter value. + ** + ** \param None + ** + ** \retval The fcm counter value. + ** + ** \note None + ** + ******************************************************************************/ +uint16_t CLK_GetFcmCounter(void) +{ + return (uint16_t)(M4_FCM->CNTR & 0xFFFFu); +} + +/** + ******************************************************************************* + ** \brief Get the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf The fcm counter overflow or not. + ** \arg ClkFcmFlagMendf The end of the measurement or not. + ** \arg ClkFcmFlagErrf Whether the frequency is abnormal or not. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + en_flag_status_t status = Reset; + + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + status = (en_flag_status_t)M4_FCM->SR_f.OVF; + break; + case ClkFcmFlagMendf: + status = (en_flag_status_t)M4_FCM->SR_f.MENDF; + break; + case ClkFcmFlagErrf: + status = (en_flag_status_t)M4_FCM->SR_f.ERRF; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief Clear the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf Clear the fcm counter overflow flag. + ** \arg ClkFcmFlagMendf Clear the end of the measurement flag. + ** \arg ClkFcmFlagErrf Clear the frequency abnormal flag. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + M4_FCM->CLR_f.OVFCLR = Set; + break; + case ClkFcmFlagMendf: + M4_FCM->CLR_f.MENDFCLR = Set; + break; + case ClkFcmFlagErrf: + M4_FCM->CLR_f.ERRFCLR = Set; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Clear the XTAL error flag. + ** + ** \param None + ** + ** \retval None + ** + ** \note The system clock should not be XTAL before call this function. + ** + ******************************************************************************/ +void CLK_ClearXtalStdFlag(void) +{ + /* Enable register write. */ + ENABLE_CLOCK_REG_WRITE(); + + if(Set == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) + { + /* Clear the XTAL STD flag */ + M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF = Reset; + } + + /* Disbale register write. */ + DISABLE_CLOCK_REG_WRITE(); +} + + +//@} // CmuGroup + +#endif /* DDL_CLK_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c new file mode 100644 index 000000000..dde45b783 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c @@ -0,0 +1,1046 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.c + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_cmp.h" +#include "hc32f460_utility.h" + +#if (DDL_CMP_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CmpGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for CMP Instances. */ +#define IS_VALID_CMP(__CMPx__) \ +( (M4_CMP1 == (__CMPx__)) || \ + (M4_CMP2 == (__CMPx__)) || \ + (M4_CMP3 == (__CMPx__))) + +/*!< Parameter valid check for CMP function */ +#define IS_VALID_CMP_FUNCTION(x) \ +( (CmpOutput == (x)) || \ + (CmpOutpuInv == (x)) || \ + (CmpVcoutOutput == (x))) + +/*! Parameter validity check for edge sel. */ +#define IS_VALID_EDGESEL(x) \ +( (CmpNoneEdge == (x)) || \ + (CmpBothEdge == (x)) || \ + (CmpRisingEdge == (x)) || \ + (CmpFaillingEdge == (x))) + +/*!< Parameter CMP FLT validity check for clock division. */ +#define IS_VALID_FLTCLK_DIVISION(x) \ +( (CmpNoneFlt == (x)) || \ + (CmpFltPclk3Div1 == (x)) || \ + (CmpFltPclk3Div2 == (x)) || \ + (CmpFltPclk3Div4 == (x)) || \ + (CmpFltPclk3Div8 == (x)) || \ + (CmpFltPclk3Div16 == (x)) || \ + (CmpFltPclk3Div32 == (x)) || \ + (CmpFltPclk3Div64 == (x))) + +/*!< Parameter validity check for INP4 SEL. */ +#define IS_VALID_INP4SEL(x) \ +( (CmpInp4None == (x)) || \ + (CmpInp4PGAO == (x)) || \ + (CmpInp4PGAO_BP == (x)) || \ + (CmpInp4CMP1_INP4 == (x))) + +/*!< Parameter validity check for INP INPUT SEL. */ +#define IS_VALID_INPSEL(x) \ +( (CmpInpNone == (x)) || \ + (CmpInp1 == (x)) || \ + (CmpInp2 == (x)) || \ + (CmpInp3 == (x)) || \ + (CmpInp4 == (x)) || \ + (CmpInp1_Inp2 == (x)) || \ + (CmpInp1_Inp3 == (x)) || \ + (CmpInp2_Inp3 == (x)) || \ + (CmpInp1_Inp4 == (x)) || \ + (CmpInp2_Inp4 == (x)) || \ + (CmpInp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3 == (x)) || \ + (CmpInp1_Inp2_Inp4 == (x)) || \ + (CmpInp1_Inp3_Inp4 == (x)) || \ + (CmpInp2_Inp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3_Inp4 == (x))) + +/*!< Parameter validity check for INM INPUT SEL. */ +#define IS_VALID_INMSEL(x) \ +( (CmpInm1 == (x)) || \ + (CmpInm2 == (x)) || \ + (CmpInm3 == (x)) || \ + (CmpInm4 == (x)) || \ + (CmpInmNone == (x))) + +/*!< Parameter validity check for CMP_CR channel. */ +#define IS_VALID_CMP_CR_CH(x) \ +( (CmpDac1 == (x)) || \ + (CmpDac2 == (x))) + +/*!< Parameter validity check for ADC internal reference voltage path. */ +#define IS_VALID_ADC_REF_VOLT_PATH(x) \ +( (CmpAdcRefVoltPathDac1 == (x)) || \ + (CmpAdcRefVoltPathDac2 == (x)) || \ + (CmpAdcRefVoltPathVref == (x))) + +/*!< RVADC Write Protection Key. */ +#define RVADC_WRITE_PROT_KEY (0x5500u) + +/*!< Timer4x ECER register address. */ +#define CMP_CR_DADRx(__DACx__) \ +( (CmpDac1 == (__DACx__)) ? &M4_CMP_CR->DADR1 : &M4_CMP_CR->DADR2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the specified CMP. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CMP configure structure + ** \arg This parameter detail refer @ref stc_cmp_init_t + ** + ** \retval Ok CMP is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - CMPx is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInitCfg pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInitCfg)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(pstcInitCfg->enEdgeSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpIntEN)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpInvEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpOutputEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpVcoutOutputEn)); + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(pstcInitCfg->enFltClkDiv)); + + /* De-Initialize CMP */ + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + + CMPx->CTRL_f.IEN = (uint16_t)pstcInitCfg->enCmpIntEN; + CMPx->CTRL_f.INV = (uint16_t)pstcInitCfg->enCmpInvEn; + CMPx->CTRL_f.EDGSL = (uint16_t)pstcInitCfg->enEdgeSel; + CMPx->CTRL_f.FLTSL = (uint16_t)pstcInitCfg->enFltClkDiv; + CMPx->CTRL_f.CMPOE = (uint16_t)pstcInitCfg->enCmpOutputEn; + CMPx->CTRL_f.OUTEN = (uint16_t)pstcInitCfg->enCmpVcoutOutputEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP working + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP function state + ** \arg Disable Disable CMP working + ** \arg Enable Enable CMP working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + CMPx->CTRL_f.CMPON = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP interrupt request + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP interrupt function state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.IEN = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan time(scan stable&&period) + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] u8ScanStable CMP scan stable value + ** \arg u8ScanStable < 16 + ** \param [in] u8ScanPeriod CMP scan period value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ** \note u8ScanStable && u8ScanPeriod value must meet following condition: + ** u8ScanPeriod > u8ScanStable + FLTSL_DIV*4 + 5 + ** FLTSL_DIV is filter sample period division(refer CMPx->CTRL_f.FLTSL) + ** + ******************************************************************************/ +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod) +{ + uint16_t u16Flts; + uint16_t u16FltslDiv; + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if ((!IS_VALID_CMP(CMPx)) || (u8ScanStable & 0xF0u)) + { + enRet = ErrorInvalidParameter; + } + else + { + u16Flts = CMPx->CTRL_f.FLTSL; + u16FltslDiv = ((uint16_t)1u << (u16Flts - 1u)); + + if ((0u != u16Flts) && + (u8ScanPeriod <= (u8ScanStable + u16FltslDiv * 4u + 5u))) + { + enRet = ErrorInvalidParameter; + } + else + { + CMPx->CVSSTB_f.STB = u8ScanStable; + CMPx->CVSPRD_f.PRD = u8ScanPeriod; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified CMP function. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFunc CMP function selection + ** \arg CmpVcoutOutput CMP Vcout output enable function + ** \arg CmpOutpuInv CMP output invert enable function + ** \arg CmpOutput CMP output enable function + ** \param [in] enCmd CMP functional state + ** \arg Enable Enable the specified CMP function + ** \arg Disable Disable the specified CMP function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CMP_FUNCTION(enFunc)); + + if (Enable == enCmd) + { + CMPx->CTRL |= (uint16_t)enFunc; + } + else + { + CMPx->CTRL &= (uint16_t)(~((uint16_t)enFunc)); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Start successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Stop successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFltClkDiv The CMP filter sample clock division selection + ** \arg CmpNoneFlt Unuse filter + ** \arg CmpFltPclk3Div1 PCLK3/1 + ** \arg CmpFltPclk3Div2 PCLK3/2 + ** \arg CmpFltPclk3Div4 PCLK3/4 + ** \arg CmpFltPclk3Div8 PCLK3/8 + ** \arg CmpFltPclk3Div16 PCLK3/16 + ** \arg CmpFltPclk3Div32 PCLK3/32 + ** \arg CmpFltPclk3Div64 PCLK3/64 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(enFltClkDiv)); + CMPx->CTRL_f.FLTSL = (uint16_t)enFltClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneFlt Unuse filter + ** \retval CmpFltPclk3Div1 PCLK3/1 + ** \retval CmpFltPclk3Div2 PCLK3/2 + ** \retval CmpFltPclk3Div4 PCLK3/4 + ** \retval CmpFltPclk3Div8 PCLK3/8 + ** \retval CmpFltPclk3Div16 PCLK3/16 + ** \retval CmpFltPclk3Div32 PCLK3/32 + ** \retval CmpFltPclk3Div64 PCLK3/64 + ** + ******************************************************************************/ +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_fltclk_div_t)CMPx->CTRL_f.FLTSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enEdgeSel The CMP detection edge selection + ** \arg CmpNoneEdge None edge detection + ** \arg CmpRisingEdge Rising edge detection + ** \arg CmpFaillingEdge Falling edge detection + ** \arg CmpBothEdge Falling or Rising edge detection + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(enEdgeSel)); + CMPx->CTRL_f.EDGSL = (uint16_t)enEdgeSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneEdge None edge detection + ** \retval CmpRisingEdge Rising edge detection + ** \retval CmpFaillingEdge Falling edge detection + ** \retval CmpBothEdge Falling or Rising edge detection + ** + ******************************************************************************/ +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_edge_sel_t)CMPx->CTRL_f.EDGSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP input sel + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInputSel The CMP input selection structure + ** \arg This parameter detail refer @ref stc_cmp_input_sel_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInputSel pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInputSel)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(pstcInputSel->enInmSel)); + DDL_ASSERT(IS_VALID_INPSEL(pstcInputSel->enInpSel)); + DDL_ASSERT(IS_VALID_INP4SEL(pstcInputSel->enInp4Sel)); + + if ((CmpInp4PGAO == pstcInputSel->enInp4Sel) || + (CmpInp4PGAO_BP == pstcInputSel->enInp4Sel)) + { + if (M4_CMP3 != CMPx) + { + enRet = Ok; + } + } + else if (CmpInp4CMP1_INP4 == pstcInputSel->enInp4Sel) + { + if (M4_CMP1 == CMPx) + { + enRet = Ok; + } + } + else + { + enRet = Ok; + } + + if (enRet == Ok) + { + CMPx->VLTSEL_f.CVSL = (uint16_t)pstcInputSel->enInpSel; + CMPx->VLTSEL_f.RVSL = (uint16_t)pstcInputSel->enInmSel; + CMPx->VLTSEL_f.C4SL = (uint16_t)pstcInputSel->enInp4Sel; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInpNone None input + ** \arg CmpInp1 INP1 input + ** \arg CmpInp2 INP2 input + ** \arg CmpInp1_Inp2 INP1 INP2 input + ** \arg CmpInp3 INP3 input + ** \arg CmpInp1_Inp3 INP1 INP3 input + ** \arg CmpInp2_Inp3 INP2 INP3 input + ** \arg CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \arg CmpInp4 INP4 input + ** \arg CmpInp1_Inp4 INP1 INP4 input + ** \arg CmpInp2_Inp4 INP2 INP4 input + ** \arg CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \arg CmpInp3_Inp4 INP3 INP4 input + ** \arg CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \arg CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \arg CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INPSEL(enInputSel)); + CMPx->VLTSEL_f.CVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInpNone None input + ** \retval CmpInp1 INP1 input + ** \retval CmpInp2 INP2 input + ** \retval CmpInp1_Inp2 INP1 INP2 input + ** \retval CmpInp3 INP3 input + ** \retval CmpInp1_Inp3 INP1 INP3 input + ** \retval CmpInp2_Inp3 INP2 INP3 input + ** \retval CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \retval CmpInp4 INP4 input + ** \retval CmpInp1_Inp4 INP1 INP4 input + ** \retval CmpInp2_Inp4 INP2 INP4 input + ** \retval CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \retval CmpInp3_Inp4 INP3 INP4 input + ** \retval CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \retval CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \retval CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ******************************************************************************/ +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_sel_t)CMPx->VLTSEL_f.CVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInmNone None input + ** \arg CmpInm1 INM1 input + ** \arg CmpInm2 INM2 input + ** \arg CmpInm3 INM3 input + ** \arg CmpInm4 INM4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(enInputSel)); + CMPx->VLTSEL_f.RVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInmNone None input + ** \retval CmpInm1 INM1 input + ** \retval CmpInm2 INM2 input + ** \retval CmpInm3 INM3 input + ** \retval CmpInm4 INM4 input + ** + ******************************************************************************/ +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inm_sel_t)CMPx->VLTSEL_f.RVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInp4None None input + ** \arg CmpInp4PGAO PGAO output + ** \arg CmpInp4PGAO_BP PGAO_BP output + ** \arg CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + DDL_ASSERT(M4_CMP3 != CMPx); + DDL_ASSERT(IS_VALID_INP4SEL(enInputSel)); + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->VLTSEL_f.C4SL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInp4None None input + ** \retval CmpInp4PGAO PGAO output + ** \retval CmpInp4PGAO_BP PGAO_BP output + ** \retval CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp4_sel_t)CMPx->VLTSEL_f.C4SL; +} + +/** + ******************************************************************************* + ** \brief Get CMP output state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_output_state_t)(CMPx->MON_f.OMON); +} + +/** + ******************************************************************************* + ** \brief Get CMP INP state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_state_t)(CMPx->MON_f.CVST); +} + +/** + ******************************************************************************* + ** \brief Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] pstcInitCfg Pointer to CMP DAC configure structure + ** \arg This parameter detail refer @ref stc_cmp_dac_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_CMP_CR_CH(enCh)) && (pstcInitCfg != NULL)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpDacEN)); + + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); /* Disable DAC */ + + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = pstcInitCfg->u8DacData; /* Set DAC data */ + + if (Enable == pstcInitCfg->enCmpDacEN) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); /* Enable DAC */ + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP DAC working + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP DAC channel: DAC1 + ** \arg CmpDac2 CMP DAC channel: DAC2 + ** \param [in] enCmd The CMP DAC function state + ** \arg Disable Disable CMP DAC working + ** \arg Enable Enable CMP DAC working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + if(Enable == enCmd) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); + } + else + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] u8DacData DAC data register value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = u8DacData; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval DAC data register value + ** + ******************************************************************************/ +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP_CR_CH(enCh)); + + return *(__IO uint8_t *)CMP_CR_DADRx(enCh); +} + +/** + ******************************************************************************* + ** \brief Set ADC internal reference voltage path + ** + ** \param [in] enRefVoltPath ADC internal reference voltage path + ** \arg CmpAdcRefVoltPathDac1 ADC internal reference voltage path: DAC1 + ** \arg CmpAdcRefVoltPathDac2 ADC internal reference voltage path: DAC2 + ** \arg CmpAdcRefVoltPathVref ADC internal reference voltage path: VREF + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enRefVoltPath is invalid. + ** + ******************************************************************************/ +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_ADC_REF_VOLT_PATH(enRefVoltPath)) + { + M4_CMP_CR->RVADC = RVADC_WRITE_PROT_KEY; /* Release write protection */ + M4_CMP_CR->RVADC = enRefVoltPath; /* Set reference voltage path */ + enRet = Ok; + } + + return enRet; +} + +//@} // CmpGroup + +#endif /* DDL_CMP_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c new file mode 100644 index 000000000..1cdf7fb24 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c @@ -0,0 +1,327 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.c + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_crc.h" +#include "hc32f460_utility.h" + +#if (DDL_CRC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Definition of CRC16 data register. */ +#define M4_CRC16_DAT (*((__IO uint16_t *)&M4_CRC->DAT0)) + +/* Definition of CRC16 checksum register. */ +#define M4_CRC16_RSLT (*((__IO uint16_t *)&M4_CRC->RESLT)) + +/* Definition of CRC16 initial value register. */ +#define M4_CRC16_INIT (M4_CRC16_RSLT) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum); +static uint32_t CRC_ReverseBits(uint32_t u32Data); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the CRC. + ** + ** \param [in] u32Config Bit[1]: CRC_SEL_16B or CRC_SEL_32B. + ** Bit[2]: CRC_REFIN_DISABLE or CRC_REFIN_ENABLE. + ** Bit[3]: CRC_REFOUT_DISABLE or CRC_REFOUT_ENABLE. + ** Bit[4]: CRC_XOROUT_DISABLE or CRC_XOROUT_ENABLE. + ** See the definitions for details. + ** + ** \retval None + ** + ******************************************************************************/ +void CRC_Init(uint32_t u32Config) +{ + u32Config &= CRC_CONFIG_MASK; + + M4_CRC->CR = u32Config; +} + +/** + ******************************************************************************* + ** \brief CRC16 calculation. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 16-bit CRC checksum. + ** + ******************************************************************************/ +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length) +{ + uint16_t u16Ret = 0u; + uint32_t u32Count; + + if (NULL != pu16Data) + { + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + u16Ret = M4_CRC16_RSLT; + } + + return u16Ret; +} + +/** + ******************************************************************************* + ** \brief CRC32 calculation. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 32-bit CRC checksum. + ** + ******************************************************************************/ +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length) +{ + uint32_t u32Ret = 0u; + uint32_t u32Count; + + M4_CRC->RESLT = u32InitVal; + + if (NULL != pu32Data) + { + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + u32Ret = M4_CRC->RESLT; + } + + return u32Ret; +} + +/** + ******************************************************************************* + ** \brief CRC16 check. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] u16Checksum CRC16 checksum of the source data. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC16 checks successfully. + ** \retval false CRC16 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16Checksum, const uint16_t *pu16Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint16_t u16CrcChecksum; + + if (NULL != pu16Data) + { + u16CrcChecksum = (uint16_t)CRC_ProcChecksum((uint32_t)u16Checksum); + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + M4_CRC16_DAT = u16CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/** + ******************************************************************************* + ** \brief CRC32 check. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] u32Checksum CRC32 checksum of the source data. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC32 checks successfully. + ** \retval false CRC32 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32Checksum, const uint32_t *pu32Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint32_t u32CrcChecksum; + + if (NULL != pu32Data) + { + u32CrcChecksum = CRC_ProcChecksum(u32Checksum); + M4_CRC->RESLT = u32InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + M4_CRC->DAT0 = u32CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Processes the checksum of CRC. + ** + ** \param [in] u32Checksum The checksum of CRC16 or CRC32. + ** + ** \retval 32-bit new checksum will be used by CRC checking. + ** + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum) +{ + uint8_t i; + uint8_t u8Size = 16u; + uint8_t u8Offset; + uint32_t u32Config; + uint32_t u32FinalChecksum; + uint32_t u32Temp; + + u32Config = M4_CRC->CR; + u32FinalChecksum = u32Checksum; + + if ((u32Config & CRC_SEL_32B) == CRC_SEL_32B) + { + u8Size = 32u; + } + + if ((u32Config & CRC_REFOUT_ENABLE) == CRC_REFOUT_DISABLE) + { + /* Bits reversing. */ + u32FinalChecksum = CRC_ReverseBits(u32Checksum); + if (u8Size == 16u) + { + u32FinalChecksum >>= 16u; + u32FinalChecksum &= 0xFFFFu; + } + } + + if ((u32Config & CRC_XOROUT_ENABLE) == CRC_XOROUT_DISABLE) + { + /* Bits NOT. */ + u32FinalChecksum = ~u32FinalChecksum; + } + + if ((u32Config & CRC_REFIN_ENABLE) == CRC_REFIN_DISABLE) + { + u8Size /= 8u; + /* Bits reversing in bytes. */ + for (i = 0u; i < u8Size; i++) + { + u8Offset = i * 8u; + u32Temp = (u32FinalChecksum >> u8Offset) & 0xFFul; + u32Temp = CRC_ReverseBits(u32Temp); + u32Temp = u32Temp >> (24u - u8Offset); + u32FinalChecksum &= ~((uint32_t)0xFF << u8Offset); + u32FinalChecksum |= u32Temp; + } + } + + return u32FinalChecksum; +} + +/** + ******************************************************************************* + ** \brief Reverse bits. + ** + ** \param [in] u32Data The data to be reversed bits. + ** + ** \retval 32-bit new data. + ** + ******************************************************************************/ +static uint32_t CRC_ReverseBits(uint32_t u32Data) +{ + u32Data = (((u32Data & 0xAAAAAAAAul) >> 1u) | ((u32Data & 0x55555555ul) << 1u)); + u32Data = (((u32Data & 0xCCCCCCCCul) >> 2u) | ((u32Data & 0x33333333ul) << 2u)); + u32Data = (((u32Data & 0xF0F0F0F0ul) >> 4u) | ((u32Data & 0x0F0F0F0Ful) << 4u)); + u32Data = (((u32Data & 0xFF00FF00ul) >> 8u) | ((u32Data & 0x00FF00FFul) << 8u)); + + return ((u32Data >> 16u) | (u32Data << 16u)); +} + +//@} // CrcGroup + +#endif /* DDL_CRC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c new file mode 100644 index 000000000..71fdbede5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c @@ -0,0 +1,975 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.c + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dcu.h" +#include "hc32f460_utility.h" + +#if (DDL_DCU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DcuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for DCU Instances. */ +#define IS_VALID_DCU(__DCUx__) \ +( (M4_DCU1 == (__DCUx__)) || \ + (M4_DCU2 == (__DCUx__)) || \ + (M4_DCU3 == (__DCUx__)) || \ + (M4_DCU4 == (__DCUx__))) + +/*!< Parameter valid check for DCU DATA register. */ +#define IS_VALID_DCU_DATA_REG(x) \ +( (DcuRegisterData0 == (x)) || \ + (DcuRegisterData1 == (x)) || \ + (DcuRegisterData2 == (x))) + +/*!< Parameter valid check for DCU operation mode. */ +#define IS_VALID_DCU_OPERATION(x) \ +( (DcuOpAdd == (x)) || \ + (DcuOpSub == (x)) || \ + (DcuInvalid == (x)) || \ + (DcuOpCompare == (x)) || \ + (DcuHwTrigOpAdd == (x)) || \ + (DcuHwTrigOpSub == (x))) + +/*!< Parameter valid check for DCU data size. */ +#define IS_VALID_DCU_DATAZ_SIZE(x) \ +( (DcuDataBit8 == (x)) || \ + (DcuDataBit16 == (x)) || \ + (DcuDataBit32 == (x))) + +/*!< Parameter valid check for DCU compare trigger mode type. */ +#define IS_VALID_DCU_CMP_TRIG_MODE(x) \ +( (DcuCmpTrigbyData0 == (x)) || \ + (DcuCmpTrigbyData012 == (x))) + +/*!< Parameter valid check for DCU interrupt. */ +#define IS_VALID_DCU_INT(x) \ +( (DcuIntOp == (x)) || \ + (DcuIntLs2 == (x)) || \ + (DcuIntEq2 == (x)) || \ + (DcuIntGt2 == (x)) || \ + (DcuIntLs1 == (x)) || \ + (DcuIntEq1 == (x)) || \ + (DcuIntGt1 == (x))) + +/*!< Parameter valid check for DCU interrupt mode. */ +#define IS_VALID_DCU_INT_WIN_MODE(x) \ +( (DcuIntInvalid == (x)) || \ + (DcuWinIntInvalid == (x)) || \ + (DcuInsideWinCmpInt == (x)) || \ + (DcuOutsideWinCmpInt == (x))) + +/*!< Parameter valid check for external trigger event. */ +#define IS_VALID_TRG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter valid check for DCU common trigger. */ +#define IS_DCU_COM_TRIGGER(x) \ +( ((x) == DcuComTrigger_1) || \ + ((x) == DcuComTrigger_2) || \ + ((x) == DcuComTrigger_1_2)) + +/*!< Get the specified DATA register address of the specified DCU unit */ +#define DCU_DATAx(__DCUx__, __DATAx__) ((uint32_t)(&(__DCUx__)->DATA0) + ((uint32_t)(__DATAx__)) * 4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to DCU configure structure + ** \arg This parameter detail refer @ref stc_dcu_init_t + ** + ** \retval Ok DCU is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx && pstcInitCfg pointer */ + if ((IS_VALID_DCU(DCUx)) && (NULL != pstcInitCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enIntCmd)); + DDL_ASSERT(IS_VALID_DCU_OPERATION(pstcInitCfg->enOperation)); + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(pstcInitCfg->enDataSize)); + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(pstcInitCfg->enIntWinMode)); + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(pstcInitCfg->enCmpTriggerMode)); + + /* De-initialize dcu register value */ + DCUx->CTL = 0ul; + DCUx->INTSEL = 0ul; + DCUx->FLAGCLR = 0x7Ful; + + /* Set dcu operation mode */ + DCUx->CTL_f.MODE = (uint32_t)pstcInitCfg->enOperation; + + /* Set dcu data sieze */ + DCUx->CTL_f.DATASIZE = (uint32_t)pstcInitCfg->enDataSize; + + /* Set dcu compare trigger mode */ + DCUx->CTL_f.COMP_TRG = (uint32_t)pstcInitCfg->enCmpTriggerMode; + + /* Set dcu interrupt window mode */ + DCUx->INTSEL_f.INT_WIN = (uint32_t)pstcInitCfg->enIntWinMode; + + DCUx->INTSEL = pstcInitCfg->u32IntSel; + DCUx->CTL_f.INTEN = (uint32_t)(pstcInitCfg->enIntCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval Ok De-Initialized successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* De-initialize dcu register value */ + DCUx->CTL = 0u; + DCUx->INTSEL = 0u; + DCUx->FLAGCLR = 0x7Fu; + *TRGSELx = EVT_MAX; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enMode DCU operation mode + ** \arg DcuInvalid Invalid + ** \arg DcuOpAdd Operation: Add + ** \arg DcuOpSub Operation: Sub + ** \arg DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \arg DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \arg DcuOpCompare Operation: Compare + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_OPERATION(enMode)); + + DCUx->CTL_f.MODE = (uint32_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuInvalid Invalid + ** \retval DcuOpAdd Operation: Add + ** \retval DcuOpSub Operation: Sub + ** \retval DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \retval DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \retval DcuOpCompare Operation: Compare + ** + ******************************************************************************/ +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_operation_mode_t)DCUx->CTL_f.MODE; +} + +/** + ******************************************************************************* + ** \brief Set DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enSize DCU data size + ** \arg DcuDataBit8 8 bit + ** \arg DcuDataBit16 16 bit + ** \arg DcuDataBit32 32 bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(enSize)); + + DCUx->CTL_f.DATASIZE = (uint32_t)enSize; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuDataBit8 8 bit + ** \retval DcuDataBit16 16 bit + ** \retval DcuDataBit32 32 bit + ** + ******************************************************************************/ +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_data_size_t)(DCUx->CTL_f.DATASIZE); +} + +/** + ******************************************************************************* + ** \brief Set DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntWinMode Interrupt window mode + ** \arg DcuIntInvalid DCU don't occur interrupt + ** \arg DcuWinIntInvalid DCU window interrupt is invalid. + ** \arg DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \arg DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(enIntWinMode)); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + DCUx->INTSEL_f.INT_WIN = (uint32_t)enIntWinMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuIntInvalid DCU don't occur interrupt + ** \retval DcuWinIntInvalid DCU window interrupt is invalid. + ** \retval DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \retval DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ******************************************************************************/ +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_int_win_mode_t)(DCUx->INTSEL_f.INT_WIN); +} + +/** + ******************************************************************************* + ** \brief Set DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerMode DCU compare trigger mode + ** \arg DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \arg DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(enTriggerMode)); + + DCUx->CTL_f.COMP_TRG = (uint32_t)enTriggerMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \retval DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ******************************************************************************/ +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_cmp_trigger_mode_t)(DCUx->CTL_f.COMP_TRG); +} + +/** + ******************************************************************************* + ** \brief Enable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enCmd DCU interrupt state + ** \arg Enable Enable the DCU interrupt function + ** \arg Disable Disable the DCU interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + DCUx->CTL_f.INTEN = (uint32_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag The specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + + return ((DCUx->FLAG & enFlag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag the specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + DCUx->FLAGCLR = (uint32_t)enFlag; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntSel DCU interrupt selection + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified DCU interrupt function + ** \arg Disable Disable the specified DCU interrupt function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - enIntSel is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enIntSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + enRet = Ok; + switch(enIntSel) + { + case DcuIntOp: + DCUx->INTSEL_f.INT_OP = (uint32_t)enCmd; + break; + case DcuIntLs2: + DCUx->INTSEL_f.INT_LS2 = (uint32_t)enCmd; + break; + case DcuIntEq2: + DCUx->INTSEL_f.INT_EQ2 = (uint32_t)enCmd; + break; + case DcuIntGt2: + DCUx->INTSEL_f.INT_GT2 = (uint32_t)enCmd; + break; + case DcuIntLs1: + DCUx->INTSEL_f.INT_LS1 = (uint32_t)enCmd; + break; + case DcuIntEq1: + DCUx->INTSEL_f.INT_EQ1 = (uint32_t)enCmd; + break; + case DcuIntGt1: + DCUx->INTSEL_f.INT_GT1 = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint8_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u8Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint8_t *)DCU_DATAx(DCUx, enDataReg) = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint16_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u16Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint16_t *)DCU_DATAx(DCUx, enDataReg) = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint32_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u32Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint32_t *)DCU_DATAx(DCUx, enDataReg) = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU trigger source number + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerSrc The trigger source. + ** \arg This parameter can be any value of @ref en_event_src_t + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_TRG_SRC_EVENT(enTriggerSrc)); + + *TRGSELx = (*TRGSELx & (~((uint32_t)EVT_MAX))) | (uint32_t)enTriggerSrc; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable DCU common trigger. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enComTrigger DCU common trigger selection. See @ref en_dcu_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_DCU_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Get DCU trigger source register address + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DCUx_TRGSEL address DCUx is valid + ** \retval NULL DCUx is invalid + ** + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx) +{ + __IO uint32_t *TRGSELx = NULL; + + if (M4_DCU1 == DCUx) + { + TRGSELx = &M4_AOS->DCU1_TRGSEL; + } + else if (M4_DCU2 == DCUx) + { + TRGSELx = &M4_AOS->DCU2_TRGSEL; + } + else if (M4_DCU3 == DCUx) + { + TRGSELx = &M4_AOS->DCU3_TRGSEL; + } + else if (M4_DCU4 == DCUx) + { + TRGSELx = &M4_AOS->DCU4_TRGSEL; + } + else + { + TRGSELx = NULL; + } + + return TRGSELx; +} + +//@} // DcuGroup + +#endif /* DDL_DCU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c new file mode 100644 index 000000000..a4eba02b5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c @@ -0,0 +1,1827 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.c + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dmac.h" +#include "hc32f460_utility.h" + +#if (DDL_DMAC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DmacGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define DMA_CNT (10u) +#define DMA_IDLE (0u) +#define DMA_BUSY (1u) + +#define DMACH0 (0x01u) +#define DMACH1 (0x02u) +#define DMACH2 (0x04u) +#define DMACH3 (0x08u) + +#define DMATIMEOUT1 (0x5000u) +#define DMATIMEOUT2 (0x1000u) + +#define DMA_CHCTL_DEFAULT (0x00001000ul) +#define DMA_DTCTL_DEFAULT (0x00000001ul) +#define DMA_DAR_DEFAULT (0x00000000ul) +#define DMA_SAR_DEFAULT (0x00000000ul) +#define DMA_RPT_DEFAULT (0x00000000ul) +#define DMA_LLP_DEFAULT (0x00000000ul) +#define DMA_SNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_DNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_RCFGCTL_DEFAULT (0x00000000ul) + +/***************** Bits definition for DMA_INTSTAT0 register ****************/ +#define DMA_INTSTAT0_TRNERR_Pos (0U) /*!< DMA_INTSTAT0: TRNERR Position */ +#define DMA_INTSTAT0_REQERR_Pos (16U) /*!< DMA_INTSTAT0: REQERR Position */ + +/***************** Bits definition for DMA_INTSTAT1 register ****************/ +#define DMA_INTSTAT1_TC_Pos (0U) /*!< DMA_INTSTAT1: TC Position */ +#define DMA_INTSTAT1_BTC_Pos (16U) /*!< DMA_INTSTAT1: BTC Position */ + +/***************** Bits definition for DMA_INTMASK0 register ****************/ +#define DMA_INTMASK0_MSKTRNERR_Pos (0U) /*!< DMA_INTMASK0: MSKTRNERR Position */ +#define DMA_INTMASK0_MSKREQERR_Pos (16U) /*!< DMA_INTMASK0: MSKREQERR Position */ + +/***************** Bits definition for DMA_INTMASK1 register ****************/ +#define DMA_INTMASK1_MSKTC_Pos (0U) /*!< DMA_INTMASK1: MSKTC Position */ +#define DMA_INTMASK1_MSKBTC_Pos (16U) /*!< DMA_INTMASK1: MSKBTC Position */ + +/***************** Bits definition for DMA_INTCLR0 register *****************/ +#define DMA_INTCLR0_CLRTRNERR_Pos (0U) /*!< DMA_INTCLR0: CLRTRNERR Position */ +#define DMA_INTCLR0_CLRREQERR_Pos (16U) /*!< DMA_INTCLR0: CLRREQERR Position */ + +/***************** Bits definition for DMA_INTCLR1 register *****************/ +#define DMA_INTCLR1_CLRTC_Pos (0U) /*!< DMA_INTCLR1: CLRTC Position */ +#define DMA_INTCLR1_CLRBTC_Pos (16U) /*!< DMA_INTCLR1: CLRBTC Position */ + +/******************* Bits definition for DMA_CHEN register ******************/ +#define DMA_CHEN_CHEN_Pos (0U) /*!< DMA_CHEN: CHEN Position */ + +/************** Bits definition for DMA_DTCTLx(x=0~3) register **************/ +#define DMA_DTCTL_BLKSIZE_Pos (0ul) /*!< DMA_DTCTLx: BLKSIZE Position */ +#define DMA_DTCTL_BLKSIZE_Msk (0x3FFul << DMA_DTCTL_BLKSIZE_Pos) /*!< DMA_DTCTLx: BLKSIZE Mask 0x000003FF */ +#define DMA_DTCTL_BLKSIZE (DMA_DTCTL_BLKSIZE_Msk) + +#define DMA_DTCTL_CNT_Pos (16ul) /*!< DMA_DTCTLx: CNT Position */ +#define DMA_DTCTL_CNT_Msk (0xFFFFul << DMA_DTCTL_CNT_Pos) /*!< DMA_DTCTLx: CNT Mask 0xFFFF0000 */ +#define DMA_DTCTL_CNT (DMA_DTCTL_CNT_Msk) + +/*************** Bits definition for DMA_RPTx(x=0~3) register ***************/ +#define DMA_RPT_SRPT_Pos (0ul) /*!< DMA_RPTx: SRPT Position */ +#define DMA_RPT_SRPT_Msk (0x3FFul << DMA_RPT_SRPT_Pos) /*!< DMA_RPTx: SRPT Mask 0x000003FF */ +#define DMA_RPT_SRPT (DMA_RPT_SRPT_Msk) + +#define DMA_RPT_DRPT_Pos (16ul) /*!< DMA_RPTx: DRPT Position */ +#define DMA_RPT_DRPT_Msk (0x3FFul << DMA_RPT_DRPT_Pos) /*!< DMA_RPTx: DRPT Mask 0x03FF0000 */ +#define DMA_RPT_DRPT (DMA_RPT_DRPT_Msk) + +/*************** Bits definition for DMA_RPTBx(x=0~3) register ***************/ +#define DMA_RPTB_SRPTB_Pos (0ul) /*!< DMA_RPTBx: SRPTB Position */ +#define DMA_RPTB_SRPTB_Msk (0x3FFul << DMA_RPTB_SRPTB_Pos) /*!< DMA_RPTBx: SRPTB Mask 0x000003FF */ +#define DMA_RPTB_SRPTB (DMA_RPTB_SRPTB_Msk) + +#define DMA_RPTB_DRPTB_Pos (16ul) /*!< DMA_RPTBx: DRPTB Position */ +#define DMA_RPTB_DRPTB_Msk (0x3FFul << DMA_RPTB_DRPTB_Pos) /*!< DMA_RPTBx: DRPTB Mask 0x03FF0000 */ +#define DMA_RPTB_DRPTB (DMA_RPTB_DRPTB_Msk) + +/************* Bits definition for DMA_SNSEQCTLx(x=0~3) register ************/ +#define DMA_SNSEQCTL_SOFFSET_Pos (0ul) /*!< DMA_SNSEQCTLx: SOFFSET Position */ +#define DMA_SNSEQCTL_SOFFSET_Msk (0xFFFFFul << DMA_SNSEQCTL_SOFFSET_Pos) /*!< DMA_SNSEQCTLx: SOFFSET Mask 0x000FFFFF */ +#define DMA_SNSEQCTL_SOFFSET (DMA_SNSEQCTL_SOFFSET_Msk) + +#define DMA_SNSEQCTL_SNSCNT_Pos (20ul) /*!< DMA_SNSEQCTLx: SNSCNT Position */ +#define DMA_SNSEQCTL_SNSCNT_Msk (0xFFFul << DMA_SNSEQCTL_SNSCNT_Pos) /*!< DMA_SNSEQCTLx: SNSCNT Mask 0xFFF00000 */ +#define DMA_SNSEQCTL_SNSCNT (DMA_SNSEQCTL_SNSCNT_Msk) + +/************* Bits definition for DMA_SNSEQCTLBx(x=0~3) register ************/ +#define DMA_SNSEQCTLB_SNSDIST_Pos (0ul) /*!< DMA_SNSEQCTLBx: SNSDIST Position */ +#define DMA_SNSEQCTLB_SNSDIST_Msk (0xFFFFFul << DMA_SNSEQCTLB_SNSDIST_Pos) /*!< DMA_SNSEQCTLBx: SNSDIST Mask 0x000FFFFF */ +#define DMA_SNSEQCTLB_SNSDIST (DMA_SNSEQCTLB_SNSDIST_Msk) + +#define DMA_SNSEQCTLB_SNSCNTB_Pos (20ul) /*!< DMA_SNSEQCTLBx: SNSCNTB Position */ +#define DMA_SNSEQCTLB_SNSCNTB_Msk (0xFFFul << DMA_SNSEQCTLB_SNSCNTB_Pos) /*!< DMA_SNSEQCTLBx: SNSCNTB Mask 0xFFF00000 */ +#define DMA_SNSEQCTLB_SNSCNTB (DMA_SNSEQCTLB_SNSCNTB_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTL_DOFFSET_Pos (0ul) /*!< DMA_DNSEQCTLx: DOFFSET Position */ +#define DMA_DNSEQCTL_DOFFSET_Msk (0xFFFFFul << DMA_DNSEQCTL_DOFFSET_Pos) /*!< DMA_DNSEQCTLx: DOFFSET Mask 0x000FFFFF */ +#define DMA_DNSEQCTL_DOFFSET (DMA_DNSEQCTL_DOFFSET_Msk) + +#define DMA_DNSEQCTL_DNSCNT_Pos (20ul) /*!< DMA_DNSEQCTLx: DNSCNT Position */ +#define DMA_DNSEQCTL_DNSCNT_Msk (0xFFFul << DMA_DNSEQCTL_DNSCNT_Pos) /*!< DMA_DNSEQCTLx: DNSCNT Mask 0xFFF00000 */ +#define DMA_DNSEQCTL_DNSCNT (DMA_DNSEQCTL_DNSCNT_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTLB_DNSDIST_Pos (0ul) /*!< DMA_DNSEQCTLBx: DNSDIST Position */ +#define DMA_DNSEQCTLB_DNSDIST_Msk (0xFFFFFul << DMA_DNSEQCTLB_DNSDIST_Pos) /*!< DMA_DNSEQCTLBx: DNSDIST Mask 0x000FFFFF */ +#define DMA_DNSEQCTLB_DNSDIST (DMA_DNSEQCTLB_DNSDIST_Msk) + +#define DMA_DNSEQCTLB_DNSCNTB_Pos (20ul) /*!< DMA_DNSEQCTLBx: DNSCNTB Position */ +#define DMA_DNSEQCTLB_DNSCNTB_Msk (0xFFFul << DMA_DNSEQCTLB_DNSCNTB_Pos) /*!< DMA_DNSEQCTLBx: DNSCNTB Mask 0xFFF00000 */ +#define DMA_DNSEQCTLB_DNSCNTB (DMA_DNSEQCTLB_DNSCNTB_Msk) + +/**************** Bits definition for DMA_LLPx(x=0~7) register **************/ +#define DMA_LLP_LLP_Pos (2ul) /*!< DMA_LLPx: LLP Position */ +#define DMA_LLP_LLP_Msk (0x3FFFFFFFul << DMA_LLP_LLP_Pos) /*!< DMA_LLPx: LLP Mask 0xFFFFFFC */ +#define DMA_LLP_LLP (DMA_LLP_LLP_Msk) + +/*************** Bits definition for DMA_CHxCTL(x=0~3) register *************/ +#define DMA_CHCTL_SINC_Pos (0ul) /*!< DMA_CHxCTL: SINC Position */ +#define DMA_CHCTL_SINC_Msk (0x3ul << DMA_CHCTL_SINC_Pos) /*!< DMA_CHxCTL: SINC Mask 0x00000003 */ +#define DMA_CHCTL_SINC (DMA_CHCTL_SINC_Msk) + +#define DMA_CHCTL_DINC_Pos (2ul) /*!< DMA_CHxCTL: DINC Position */ +#define DMA_CHCTL_DINC_Msk (0x3ul << DMA_CHCTL_DINC_Pos) /*!< DMA_CHxCTL: DINC Mask 0x0000000C */ +#define DMA_CHCTL_DINC (DMA_CHCTL_DINC_Msk) + +#define DMA_CHCTL_SRPTEN_Pos (4ul) /*!< DMA_CHxCTL: SRPTEN Position */ +#define DMA_CHCTL_SRPTEN_Msk (0x1ul << DMA_CHCTL_SRPTEN_Pos) /*!< DMA_CHxCTL: SRPTEN Mask 0x00000010 */ +#define DMA_CHCTL_SRPTEN (DMA_CHCTL_SRPTEN_Msk) + +#define DMA_CHCTL_DRPTEN_Pos (5ul) /*!< DMA_CHxCTL: DRPTEN Position */ +#define DMA_CHCTL_DRPTEN_Msk (0x1ul << DMA_CHCTL_DRPTEN_Pos) /*!< DMA_CHxCTL: DRPTEN Mask 0x00000020 */ +#define DMA_CHCTL_DRPTEN (DMA_CHCTL_DRPTEN_Msk) + +#define DMA_CHCTL_SNSEQEN_Pos (6ul) /*!< DMA_CHxCTL: SNSEQEN Position */ +#define DMA_CHCTL_SNSEQEN_Msk (0x1ul << DMA_CHCTL_SNSEQEN_Pos) /*!< DMA_CHxCTL: SNSEQEN Mask 0x00000040 */ +#define DMA_CHCTL_SNSEQEN (DMA_CHCTL_SNSEQEN_Msk) + +#define DMA_CHCTL_DNSEQEN_Pos (7ul) /*!< DMA_CHxCTL: DNSEQEN Position */ +#define DMA_CHCTL_DNSEQEN_Msk (0x1ul << DMA_CHCTL_DNSEQEN_Pos) /*!< DMA_CHxCTL: DNSEQEN Mask 0x00000080 */ +#define DMA_CHCTL_DNSEQEN (DMA_CHCTL_DNSEQEN_Msk) + +#define DMA_CHCTL_HSIZE_Pos (8ul) /*!< DMA_CHxCTL: HSIZE Position */ +#define DMA_CHCTL_HSIZE_Msk (0x3ul << DMA_CHCTL_HSIZE_Pos) /*!< DMA_CHxCTL: HSIZE Mask 0x00000300 */ +#define DMA_CHCTL_HSIZE (DMA_CHCTL_HSIZE_Msk) + +#define DMA_CHCTL_LLPEN_Pos (10ul) /*!< DMA_CHxCTL: LLPEN Position */ +#define DMA_CHCTL_LLPEN_Msk (0x1ul << DMA_CHCTL_LLPEN_Pos) /*!< DMA_CHxCTL: LLPEN Mask 0x00000400 */ +#define DMA_CHCTL_LLPEN (DMA_CHCTL_LLPEN_Msk) + +#define DMA_CHCTL_LLPRUN_Pos (11ul) /*!< DMA_CHxCTL: LLPRUN Position */ +#define DMA_CHCTL_LLPRUN_Msk (0x1ul << DMA_CHCTL_LLPRUN_Pos) /*!< DMA_CHxCTL: LLPRUN Mask 0x00000800 */ +#define DMA_CHCTL_LLPRUN (DMA_CHCTL_LLPRUN_Msk) + +#define DMA_CHCTL_IE_Pos (12ul) /*!< DMA_CHxCTL: IE Position */ +#define DMA_CHCTL_IE_Msk (0x1ul << DMA_CHCTL_IE_Pos) /*!< DMA_CHxCTL: IE Mask 0x00001000 */ +#define DMA_CHCTL_IE (DMA_CHCTL_IE_Msk) + +/*********************** DMA REGISTERx(x=0~3) register **********************/ +#define _DMA_CH_REG_OFFSET(ch) ((ch) * 0x40ul) +#define _DMA_CH_REG(reg_base, ch) (*(volatile uint32_t *)((uint32_t)(reg_base) + _DMA_CH_REG_OFFSET(ch))) + +#define WRITE_DMA_CH_REG(reg_base, ch, val) (_DMA_CH_REG((reg_base), (ch)) = (val)) +#define READ_DMA_CH_REG(reg_base, ch) (_DMA_CH_REG((reg_base), (ch))) + +#define SET_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) |= (1ul << (pos))) +#define CLR_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) &= (~(1ul << (pos)))) + +#define WRITE_DMA_CH_TRGSEL(reg_base, ch, val) ((*(volatile uint32_t *)((uint32_t)(reg_base) + (ch) * 4ul)) = (val)) + +#define MODIFY_DMA_CH_REG(reg_base, ch, msk, val) {do { \ + WRITE_DMA_CH_REG((reg_base), (ch), ((READ_DMA_CH_REG((reg_base), (ch)) & (~(msk))) | ((val) << (msk##_Pos)))); \ +} while(0);} + +/*! Parameter valid check for Dmac register pointer. */ +#define IS_VALID_DMA_REG(x) \ +( (M4_DMA1 == (x)) || \ + (M4_DMA2 == (x))) + +/*! Parameter valid check for Dmac Channel. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x)) || \ + (DmaCh2 == (x)) || \ + (DmaCh3 == (x))) + +/*! Parameter valid check for Dmac irq selection. */ +#define IS_VALID_IRQ_SEL(x) \ +( (TrnErrIrq == (x)) || \ + (TrnReqErrIrq == (x)) || \ + (TrnCpltIrq == (x)) || \ + (BlkTrnCpltIrq == (x))) + +/*! Parameter valid check for Dmac re_config count mode. */ +#define IS_VALID_CNT_MODE(x) \ +( (CntFix == (x)) || \ + (CntSrcAddr == (x)) || \ + (CntDesAddr == (x))) + +/*! Parameter valid check for Dmac re_config source address mode. */ +#define IS_VALID_SADDR_MODE(x) \ +( (SaddrFix == (x)) || \ + (SaddrNseq == (x)) || \ + (SaddrRep == (x))) + +/*! Parameter valid check for Dmac re_config destination address mode. */ +#define IS_VALID_DADDR_MODE(x) \ +( (DaddrFix == (x)) || \ + (DaddrNseq == (x)) || \ + (DaddrRep == (x))) + +/*! Parameter valid check for Dmac status. */ +#define IS_VALID_DMA_STA(x) \ +( (DmaSta == (x)) || \ + (ReCfgSta == (x)) || \ + (DmaCh0Sta == (x)) || \ + (DmaCh1Sta == (x)) || \ + (DmaCh2Sta == (x)) || \ + (DmaCh3Sta == (x))) + +/*! Parameter valid check for Dmac transfer data width. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (Dma8Bit == (x)) || \ + (Dma16Bit == (x)) || \ + (Dma32Bit == (x))) + +/*! Parameter valid check for Dmac address mode. */ +#define IS_VALID_ADDR_MODE(x) \ +( (AddressFix == (x)) || \ + (AddressIncrease == (x)) || \ + (AddressDecrease == (x))) + +/*! Parameter valid check for Dmac link-list-pointer mode. */ +#define IS_VALID_LLP_MODE(x) \ +( (LlpWaitNextReq == (x)) || \ + (LlpRunNow == (x))) + +/*! Parameter validity check for DMA common trigger. */ +#define IS_DMA_COM_TRIGGER(x) \ +( ((x) == DmaComTrigger_1) || \ + ((x) == DmaComTrigger_2) || \ + ((x) == DmaComTrigger_1_2)) + +/*! Parameter valid check for Dmac transfer block size. */ +#define IS_VALID_BLKSIZE(x) \ +( !((x) & (uint16_t)(~(DMA_DTCTL_BLKSIZE_Msk >> DMA_DTCTL_BLKSIZE_Pos)))) + +/*! Parameter valid check for Dmac transfer count. */ +#define IS_VALID_TRNCNT(x) \ +( !((x) & ~(DMA_DTCTL_CNT_Msk >> DMA_DTCTL_CNT_Pos))) + +/*! Parameter valid check for Dmac source repeat size. */ +#define IS_VALID_SRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_SRPT_Msk >> DMA_RPT_SRPT_Pos))) + +/*! Parameter valid check for Dmac destination repeat size. */ +#define IS_VALID_DRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_DRPT_Msk >> DMA_RPT_DRPT_Pos))) + +/*! Parameter valid check for Dmac source repeatB size. */ +#define IS_VALID_SRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_SRPTB_Msk >> DMA_RPTB_SRPTB_Pos))) + +/*! Parameter valid check for Dmac destinationB repeat size. */ +#define IS_VALID_DRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_DRPTB_Msk >> DMA_RPTB_DRPTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence count. */ +#define IS_VALID_SNSCNT(x) \ +( !((x) & ~(DMA_SNSEQCTL_SNSCNT_Msk >> DMA_SNSEQCTL_SNSCNT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence offset. */ +#define IS_VALID_SNSOFFSET(x) \ +( !((x) & ~(DMA_SNSEQCTL_SOFFSET_Msk >> DMA_SNSEQCTL_SOFFSET_Pos))) + +/*! Parameter valid check for Dmac source no-sequence countB. */ +#define IS_VALID_SNSCNTB(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSCNTB_Msk >> DMA_SNSEQCTLB_SNSCNTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence distance. */ +#define IS_VALID_SNSDIST(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSDIST_Msk >> DMA_SNSEQCTLB_SNSDIST_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence count. */ +#define IS_VALID_DNSCNT(x) \ +( !((x) & ~(DMA_DNSEQCTL_DNSCNT_Msk >> DMA_DNSEQCTL_DNSCNT_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence offset. */ +#define IS_VALID_DNSOFFSET(x) \ +( !((x) & ~(DMA_DNSEQCTL_DOFFSET_Msk >> DMA_DNSEQCTL_DOFFSET_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence countB. */ +#define IS_VALID_DNSCNTB(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSCNTB_Msk >> DMA_DNSEQCTLB_DNSCNTB_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence distance. */ +#define IS_VALID_DNSDIST(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSDIST_Msk >> DMA_DNSEQCTLB_DNSDIST_Pos))) + +/*! Parameter valid check for Dmac link-list-pointer. */ +#define IS_VALID_LLP(x) (!((x) & ~DMA_LLP_LLP_Msk)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static volatile uint8_t DmaChEnState = DMA_IDLE; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Enable or disable the dma. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->EN_f.EN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt enabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt disabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma interrupt flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + switch(enIrqSel) + { + case TrnErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_TRNERR_Pos))); + break; + case TrnReqErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_REQERR_Pos))); + break; + case TrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_TC_Pos))); + break; + case BlkTrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_BTC_Pos))); + break; + default: + break; + } + + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint16_t u16Timeout = 0u; + uint32_t u32Temp = 0u; + uint32_t u32Cnt; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(DMA_IDLE == DmaChEnState) + { + DmaChEnState = DMA_BUSY; + + /* Read back channel enable register except current channel */ + u32Temp = (pstcDmaReg->CHEN & (~(1ul << u8Ch))); + if(0ul != u32Temp) + { + if(((pstcDmaReg->CHEN & 0x01ul) == 0x01ul) && (u8Ch != DmaCh0)) + { + u32Cnt = pstcDmaReg->DTCTL0_f.CNT; + if(pstcDmaReg->MONDTCTL0_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL0_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x01ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x02ul) == 0x02ul) && (u8Ch != DmaCh1)) + { + u32Cnt = pstcDmaReg->DTCTL1_f.CNT; + if(pstcDmaReg->MONDTCTL1_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL1_f.CNT < u32Cnt) + { + u16Timeout = 0u; + while(Reset != (pstcDmaReg->CHEN & 0x02ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x04ul) == 0x04ul) && (u8Ch != DmaCh2)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL2_f.CNT; + if(pstcDmaReg->MONDTCTL2_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL2_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x04ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x08ul) == 0x08ul) && (u8Ch != DmaCh3)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL3_f.CNT; + if(pstcDmaReg->MONDTCTL3_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL3_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x08ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + } + + switch(enNewState) + { + case Enable: + pstcDmaReg->CHEN |= (1ul << (u8Ch + DMA_CHEN_CHEN_Pos)) & 0x0fu; + break; + case Disable: + pstcDmaReg->CHEN &= (~(1ul << (u8Ch + DMA_CHEN_CHEN_Pos))) & 0x0fu; + break; + } + + DmaChEnState = DMA_IDLE; + return Ok; + } + + return Error; +} + +/** + ******************************************************************************* + ** \brief DMA repeat & non_sequence Re_Config control configuration. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaReCfg The configuration struct of DMA. + ** \arg u16SrcRptBSize The source repeat size. + ** \arg u16SrcRptBSize; The source repeat size. + ** \arg u16DesRptBSize; The destination repeat size. + ** \arg enSaddrMd; DMA re_config source address mode. + ** \arg enDaddrMd; DMA re_config destination address mode. + ** \arg enCntMd; DMA re_config count mode. + ** \arg stcSrcNseqBCfg; The source no_sequence re_config. + ** \arg stcDesNseqBCfg; The destination no_sequence re_config. + ** + ** \retval None + ** + ** \note This function should be used while DMA disable. + ** + ******************************************************************************/ +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_recfg_ctl_t* pstcDmaReCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcDmaReCfg->enCntMd)); + DDL_ASSERT(IS_VALID_DADDR_MODE(pstcDmaReCfg->enDaddrMd)); + DDL_ASSERT(IS_VALID_SADDR_MODE(pstcDmaReCfg->enSaddrMd)); + + pstcDmaReg->RCFGCTL_f.SARMD = pstcDmaReCfg->enSaddrMd; + pstcDmaReg->RCFGCTL_f.DARMD = pstcDmaReCfg->enDaddrMd; + pstcDmaReg->RCFGCTL_f.CNTMD = pstcDmaReCfg->enCntMd; + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + + if(SaddrRep == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaReCfg->u16SrcRptBSize); + } + else if(SaddrNseq == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaReCfg->stcSrcNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaReCfg->stcSrcNseqBCfg.u16Cnt); + } + else + { + /* */ + } + + if(DaddrRep == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaReCfg->u16DesRptBSize); + } + else if(DaddrNseq == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaReCfg->stcDesNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaReCfg->stcDesNseqBCfg.u16Cnt); + } + else + { + /* */ + } +} + +/** + ******************************************************************************* + ** \brief Disable or enable DMA Re_Config. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Configure DMA Re_Config LLP. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgLlp(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + pstcDmaReg->RCFGCTL_f.RCFGLLP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enDmaChFlag The specified dma flag. + ** \arg DmaSta The DMA status. + ** \arg ReCfgSta The DMA re_config stauts. + ** \arg DmaCh0Sta The DMA channel 0 status. + ** \arg DmaCh1Sta The DMA channel 1 status. + ** \arg DmaCh2Sta The DMA channel 2 status. + ** \arg DmaCh3Sta The DMA channel 3 status. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_DMA_STA(enDmaChFlag)); + + switch(enDmaChFlag) + { + case DmaSta: + u32IntStat = pstcDmaReg->CHSTAT_f.DMAACT; + break; + case ReCfgSta: + u32IntStat = pstcDmaReg->CHSTAT_f.RCFGACT; + break; + case DmaCh0Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH0); + break; + case DmaCh1Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH1); + break; + case DmaCh2Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH2); + break; + case DmaCh3Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH3); + break; + default: + break; + } + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Set the source address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The source address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONSAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The destination address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONDAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + } + } + + return enRet; + +} + + +/** + ******************************************************************************* + ** \brief Set the block size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16BlkSize The block size. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(u16BlkSize)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + + /* Ensure the block size has been writed */ + while(u16BlkSize != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_BLKSIZE)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the transfer count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16TrnCnt The transfer count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_TRNCNT(u16TrnCnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + + /* Ensure the transfer count has been writed */ + while(u16TrnCnt != ((READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_SRPT)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_DRPT) >> DMA_RPT_DRPT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_SRPTB)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptBSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_DRPTB) >> DMA_RPTB_DRPTB_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqCfg + ** \arg u32offset The source no-sequence offset. + ** \arg u16cnt The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcSrcNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSOFFSET(pstcSrcNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_SNSCNT(pstcSrcNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqCfg->u32Offset | ((uint32_t)pstcSrcNseqCfg->u16Cnt << DMA_SNSEQCTL_SNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONSNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqBCfg + ** \arg u32NseqDist The source no-sequence distance. + ** \arg u16cntB The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSDIST(pstcSrcNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_SNSCNTB(pstcSrcNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqBCfg->u32NseqDist | ((uint32_t)pstcSrcNseqBCfg->u16CntB << DMA_SNSEQCTLB_SNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcDesNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSOFFSET(pstcDesNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_DNSCNT(pstcDesNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqCfg->u32Offset | ((uint32_t)pstcDesNseqCfg->u16Cnt << DMA_DNSEQCTL_DNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONDNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqBCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcDesNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSDIST(pstcDesNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_DNSCNTB(pstcDesNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqBCfg->u32NseqDist | ((uint32_t)pstcDesNseqBCfg->u16CntB << DMA_DNSEQCTLB_DNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Pointer The decriptor pointer. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_LLP(u32Pointer)); + + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + + /* Ensure the destination repeat size has been writed */ + while(u32Pointer != ((READ_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch) & DMA_LLP_LLP) >> DMA_LLP_LLP_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set The DMA trigger source. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, shoud ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + + if(M4_DMA1 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA1_TRGSEL0,u8Ch,enSrc); + } + else if(M4_DMA2 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA2_TRGSEL0,u8Ch,enSrc); + } + else + { + //else + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA common trigger.. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + __IO uint32_t *TRGSELx; + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (M4_DMA1 == pstcDmaReg) + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA1_TRGSEL0) + u8Ch*4UL); + } + else + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA2_TRGSEL0) + u8Ch*4UL); + } + + if (Enable == enNewState) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA re-config common trigger.. + ** + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + + if (Enable == enNewState) + { + M4_AOS->DMA_TRGSELRC |= (u32ComTrig << 30u); + } + else + { + M4_AOS->DMA_TRGSELRC &= ~(u32ComTrig << 30u); + } +} +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, should ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc) +{ + + M4_AOS->DMA_TRGSELRC_f.TRGSEL = enSrc; + +} +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcChCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_ch_cfg_t* pstcChCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enSrcInc)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enDesInc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcNseqEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesNseqEn)); + DDL_ASSERT(IS_VALID_TRN_WIDTH(pstcChCfg->enTrnWidth)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enLlpEn)); + DDL_ASSERT(IS_VALID_LLP_MODE(pstcChCfg->enLlpMd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enIntEn)); + + /* Set the source address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SINC, pstcChCfg->enSrcInc); + /* Set the destination address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DINC, pstcChCfg->enDesInc); + /* Enable or disable source repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SRPTEN, pstcChCfg->enSrcRptEn); + /* Enable or disable destination repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DRPTEN, pstcChCfg->enDesRptEn); + /* Enable or disable source no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SNSEQEN, pstcChCfg->enSrcNseqEn); + /* Enable or disable destination no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DNSEQEN, pstcChCfg->enDesNseqEn); + /* Set the transfer data width. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_HSIZE, pstcChCfg->enTrnWidth); + /* Enable or disable linked list pointer no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_LLPEN, pstcChCfg->enLlpEn); + /* Set the linked list pointer mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_LLPRUN, pstcChCfg->enLlpMd); + /* Enable or disable channel interrupt function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_IE, pstcChCfg->enIntEn); +} + +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note This function should be used after enable DMAx clk(PWC_Fcg0PeriphClockCmd) + ** and before channel enable. + ** + ******************************************************************************/ +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_config_t* pstcDmaCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(pstcDmaCfg->u16BlockSize)); + DDL_ASSERT(IS_VALID_TRNCNT(pstcDmaCfg->u16TransferCnt)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(pstcDmaCfg->u16SrcRptSize)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(pstcDmaCfg->u16DesRptSize)); + + /* Enable DMA. */ + DMA_Cmd(pstcDmaReg, Enable); + /* Disable DMA interrupt */ + CLR_DMA_CH_REG_BIT(&pstcDmaReg->CH0CTL , u8Ch, DMA_CHCTL_IE_Pos); + /* Set DMA source address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, pstcDmaCfg->u32SrcAddr); + /* Set DMA destination address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, pstcDmaCfg->u32DesAddr); + /* Set DMA transfer block size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)pstcDmaCfg->u16BlockSize); + /* Set DMA transfer count. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)pstcDmaCfg->u16TransferCnt); + /* Set DMA source repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaCfg->u16SrcRptSize); + /* Set DMA destination repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaCfg->u16DesRptSize); + /* Set DMA source no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaCfg->stcSrcNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaCfg->stcSrcNseqCfg.u16Cnt); + /* Set DMA destination no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaCfg->stcDesNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaCfg->stcDesNseqCfg.u16Cnt); + /* Set DMA linked list pointer. */ + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, pstcDmaCfg->u32DmaLlp); + /* Set DMA channel parameter. */ + DMA_ChannelCfg(pstcDmaReg, u8Ch, &pstcDmaCfg->stcDmaChCfg); +} + +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + /* reset dma channel */ + WRITE_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, DMA_DAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, DMA_SAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, DMA_LLP_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RCFGCTL, u8Ch, DMA_RCFGCTL_DEFAULT); + + /* Set trigger source event max */ + DMA_SetTriggerSrc(pstcDmaReg, u8Ch, EVT_MAX); + /* disable channel */ + DMA_ChannelCmd(pstcDmaReg, u8Ch, Disable); +} + +#endif /* DDL_DMAC_ENABLE */ + +//@} // DmacGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c new file mode 100644 index 000000000..4625f3d39 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c @@ -0,0 +1,942 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.c + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_efm.h" +#include "hc32f460_utility.h" + +#if (DDL_EFM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EfmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EFM_LOCK (0x00000000u) +#define EFM_UNLOCK (0x00000001u) +#define EFM_KEY1 (0x0123ul) +#define EFM_KEY2 (0x3210ul) + +#define EFM_PROTECT_ADDR_MSK (0x000FFFFFu) + +/* Parameter validity check for pointer. */ +#define IS_VALID_POINTER(x) (NULL != (x)) + +/* Parameter validity check for flash latency. */ +#define IS_VALID_FLASH_LATENCY(x) \ +( ((x) == EFM_LATENCY_0) || \ + ((x) == EFM_LATENCY_1) || \ + ((x) == EFM_LATENCY_2) || \ + ((x) == EFM_LATENCY_3) || \ + ((x) == EFM_LATENCY_4) || \ + ((x) == EFM_LATENCY_5) || \ + ((x) == EFM_LATENCY_6) || \ + ((x) == EFM_LATENCY_7) || \ + ((x) == EFM_LATENCY_8) || \ + ((x) == EFM_LATENCY_9) || \ + ((x) == EFM_LATENCY_10) || \ + ((x) == EFM_LATENCY_11) || \ + ((x) == EFM_LATENCY_12) || \ + ((x) == EFM_LATENCY_13) || \ + ((x) == EFM_LATENCY_14) || \ + ((x) == EFM_LATENCY_15)) + +/* Parameter validity check for read mode. */ +#define IS_VALID_READ_MD(MD) \ +( ((MD) == NormalRead) || \ + ((MD) == UltraPowerRead)) + +/* Parameter validity check for erase/program mode. */ +#define IS_VALID_ERASE_PGM_MD(MD) \ +( ((MD) == EFM_MODE_READONLY) || \ + ((MD) == EFM_MODE_SINGLEPROGRAM) || \ + ((MD) == EFM_MODE_SINGLEPROGRAMRB) || \ + ((MD) == EFM_MODE_SEQUENCEPROGRAM) || \ + ((MD) == EFM_MODE_SECTORERASE) || \ + ((MD) == EFM_MODE_CHIPERASE)) + +/* Parameter validity check for flash flag. */ +#define IS_VALID_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR) || \ + ((flag) == EFM_FLAG_RDY)) + +/* Parameter validity check for flash clear flag. */ +#define IS_VALID_CLEAR_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR)) + +/* Parameter validity check for flash interrupt. */ +#define IS_VALID_EFM_INT_SEL(int) \ +( ((int) == PgmErsErrInt) || \ + ((int) == EndPgmInt) || \ + ((int) == ColErrInt)) + +/* Parameter validity check for flash address. */ +#define IS_VALID_FLASH_ADDR(addr) \ +( ((addr) == 0x00000000u) || \ + (((addr) >= 0x00000001u) && \ + ((addr) <= 0x0007FFDFu))) + +/* Parameter validity check for flash address. */ +#define IS_VALID_OTP_LOCK_ADDR(addr) \ +( ((addr) >= 0x03000FC0u) || \ + ((addr) <= 0x03000FF8u)) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Unlock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Unlock(void) +{ + M4_EFM->FAPRT = EFM_KEY1; + M4_EFM->FAPRT = EFM_KEY2; +} + +/** + ******************************************************************************* + ** \brief Lock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Lock(void) +{ + if(EFM_UNLOCK == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = EFM_KEY2; + M4_EFM->FAPRT = EFM_KEY2; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash. + ** + ** \param [in] enNewState The new state of the flash. + ** \arg Enable Enable flash. + ** \arg Disable Stop flash. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_FlashCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FSTP_f.FSTP = ((Enable == enNewState) ? 0ul : 1ul); +} +/** + ******************************************************************************* + ** \brief Sets the code latency value.. + ** + ** \param [in] u32Latency specifies the FLASH Latency value. + ** \arg EFM_LATENCY_0 FLASH 0 Latency cycle + ** \arg EFM_LATENCY_1 FLASH 1 Latency cycle + ** \arg EFM_LATENCY_2 FLASH 2 Latency cycles + ** \arg EFM_LATENCY_3 FLASH 3 Latency cycles + ** \arg EFM_LATENCY_4 FLASH 4 Latency cycles + ** \arg EFM_LATENCY_5 FLASH 5 Latency cycles + ** \arg EFM_LATENCY_6 FLASH 6 Latency cycles + ** \arg EFM_LATENCY_7 FLASH 7 Latency cycles + ** \arg EFM_LATENCY_8 FLASH 8 Latency cycles + ** \arg EFM_LATENCY_9 FLASH 9 Latency cycles + ** \arg EFM_LATENCY_10 FLASH 10 Latency cycles + ** \arg EFM_LATENCY_11 FLASH 11 Latency cycles + ** \arg EFM_LATENCY_12 FLASH 12 Latency cycles + ** \arg EFM_LATENCY_13 FLASH 13 Latency cycles + ** \arg EFM_LATENCY_14 FLASH 14 Latency cycles + ** \arg EFM_LATENCY_15 FLASH 15 Latency cycles + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetLatency(uint32_t u32Latency) +{ + DDL_ASSERT(IS_VALID_FLASH_LATENCY(u32Latency)); + + M4_EFM->FRMC_f.FLWT = u32Latency; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash instruction cache. + ** + ** \param [in] enNewState The new state of the flash instruction cache. + ** \arg Enable Enable flash instruction cache. + ** \arg Disable Disable flash instruction cache. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InstructionCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CACHE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the data cache reset. + ** + ** \param [in] enNewState The new state of the data cache reset. + ** \arg Enable Enable data cache reset. + ** \arg Disable Disable data cache reset. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_DataCacheRstCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash read mode. + ** + ** \param [in] enReadMD The flash read mode. + ** \arg NormalRead Normal read mode. + ** \arg UltraPowerRead Ultra_Low power read mode. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetReadMode(en_efm_read_md_t enReadMD) +{ + DDL_ASSERT(IS_VALID_READ_MD(enReadMD)); + M4_EFM->FRMC_f.SLPMD = enReadMD; +} + +/** + ******************************************************************************* + ** \brief Enable or disable erase / program. + ** + ** \param [in] enNewState The new state of the erase / program. + ** \arg Enable Enable erase / program. + ** \arg Disable Disable erase / program. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ErasePgmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FWMC_f.PEMODE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash erase program mode. + ** + ** \param [in] u32Mode The flash erase program mode. + ** \arg EFM_MODE_READONLY The flash read only. + ** \arg EFM_MODE_SINGLEPROGRAM The flash single program. + ** \arg EFM_MODE_SINGLEPROGRAMRB The flash single program with read back. + ** \arg EFM_MODE_SEQUENCEPROGRAM The flash sequence program. + ** \arg EFM_MODE_SECTORERASE The flash sector erase. + ** \arg EFM_MODE_CHIPERASE The flash mass erase. + ** + ** \retval en_result_t. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode) +{ + en_result_t enRet = Ok; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_ERASE_PGM_MD(u32Mode)); + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + break; + } + } + if(Ok == enRet) + { + M4_EFM->FWMC_f.PEMODE = Enable; + M4_EFM->FWMC_f.PEMOD = u32Mode; + M4_EFM->FWMC_f.PEMODE = Disable; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable the specified interrupt. + ** + ** \param [in] enInt The specified interrupt. + ** \arg PgmErsErrInt Program erase error interrupt. + ** \arg EndPgmInt End of Program interrupt. + ** \arg ReadErrInt Read collided error flag. + ** + ** \param [in] enNewState The new state of the specified interrupt. + ** \arg Enable Enable the specified interrupt. + ** \arg Disable Disable the specified interrupt. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_INT_SEL(enInt)); + + switch(enInt) + { + case PgmErsErrInt: + M4_EFM->FITE_f.PEERRITE = enNewState; + break; + case EndPgmInt: + M4_EFM->FITE_f.OPTENDITE = enNewState; + break; + case ColErrInt: + M4_EFM->FITE_f.COLERRITE = enNewState; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to check. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** \arg EFM_FLAG_RDY Flash ready flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag) +{ + DDL_ASSERT(IS_VALID_FLASH_FLAG(u32flag)); + + return ((0ul == (M4_EFM->FSR & u32flag)) ? Reset :Set); +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to clear. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ClearFlag(uint32_t u32flag) +{ + //DDL_ASSERT(IS_VALID_CLEAR_FLASH_FLAG(u32flag)); + + M4_EFM->FSCLR = u32flag; +} +/** + ******************************************************************************* + ** \brief Get the flash status. + ** + ** \param None + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_efm_flash_status_t EFM_GetStatus(void) +{ + en_efm_flash_status_t enFlashStatus = FlashEOP; + + if(1ul == M4_EFM->FSR_f.RDY ) + { + enFlashStatus = FlashReady; + } + else if(1ul == M4_EFM->FSR_f.COLERR) + { + enFlashStatus = FlashRWErr; + } + else if(1ul == M4_EFM->FSR_f.OPTEND) + { + enFlashStatus = FlashEOP; + } + else if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enFlashStatus = FlashPgMissMatch; + } + else if(1ul == M4_EFM->FSR_f.PGSZERR) + { + enFlashStatus = FlashPgSizeErr; + } + else if(1ul == M4_EFM->FSR_f.PEPRTERR) + { + enFlashStatus = FlashPgareaPErr; + } + else if(1ul == M4_EFM->FSR_f.PEWERR) + { + enFlashStatus = FlashWRPErr; + } + else + { + //else + } + + return enFlashStatus; +} + +/** + ******************************************************************************* + ** \brief Set flash the windows protect address. + ** + ** \param [in] stcAddr The specified windows protect address. + ** \arg StartAddr The start of windows protect address. + ** \arg EndAddr The end of windows protect address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr) +{ + M4_EFM->FPMTSW_f.FPMTSW = (stcAddr.StartAddr & EFM_PROTECT_ADDR_MSK); + M4_EFM->FPMTEW_f.FPMTEW = (stcAddr.EndAddr & EFM_PROTECT_ADDR_MSK); +} + +/** + ******************************************************************************* + ** \brief Set bus state while flash program & erase. + ** + ** \param [in] enState The specified bus state while flash program & erase. + ** \arg BusBusy The bus busy. + ** \arg BusRelease The bus release. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetBusState(en_efm_bus_sta_t enState) +{ + M4_EFM->FWMC_f.BUSHLDCTL = enState; +} + +/** + ******************************************************************************* + ** \brief Flash single program without read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(u32Data != *(uint32_t*)u32Addr) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash single program with read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp = 0u; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program with read back mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAMRB; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +static void *EFM_Memcpy(void *pvDst, void *pvSrc, uint32_t u32Count) +{ + uint8_t *u8TmpDst = (uint8_t *)pvDst; + uint8_t *u8TmpSrc = (uint8_t *)pvSrc; + + DDL_ASSERT(IS_VALID_POINTER(pvDst)); + DDL_ASSERT(IS_VALID_POINTER(pvSrc)); + + while (u32Count--) + { + *u8TmpDst++ = *u8TmpSrc++; + } + + return pvDst; +} +/** + ******************************************************************************* + ** \brief Flash sequence program. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Len The len of specified program data. + ** \param [in] *pBuf The pointer of specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint32_t i; + uint16_t u16Timeout = 0u; + uint32_t u32Tmp = 0xFFFFFFFFul; + uint32_t *u32pSrc = pBuf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LoopWords = u32Len >> 2ul; + uint32_t u32RemainBytes = u32Len % 4ul; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_POINTER(pBuf)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set sequence program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SEQUENCEPROGRAM; + /* clear read collided error flag.*/ + EFM_ClearFlag(EFM_FLAG_COLERR); + EFM_ClearFlag(EFM_FLAG_WRPERR); + + /* program data. */ + for(i = 0ul; i < u32LoopWords; i++) + { + *u32pDest++ = *u32pSrc++; + /* wait operate end. */ + while(1ul != M4_EFM->FSR_f.OPTEND) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + /* clear end flag. */ + EFM_ClearFlag(EFM_FLAG_EOP); + } + if(u32RemainBytes) + { + EFM_Memcpy(&u32Tmp, u32pSrc, u32RemainBytes); + *u32pDest++ = u32Tmp; + } + + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + + u16Timeout = 0u; + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash sector erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the specified sector. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_SectorErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SECTORERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash mass erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the flash. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_MassErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_CHIPERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flash switch status. + ** + ** \param None. + ** + ** \retval en_flag_status_t + ** \arg Set The flash has switched, the start address is sector1. + ** \arg Reset The flash did not switch, the start address is sector0. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetSwitchStatus(void) +{ + return ((0u == M4_EFM->FSWP_f.FSWP) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Lock OTP data block. + ** + ** \param u32Addr The addr to lock. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_OtpLock(uint32_t u32Addr) +{ + DDL_ASSERT(IS_VALID_OTP_LOCK_ADDR(u32Addr)); + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + + /* Lock the otp block. */ + *(uint32_t*)u32Addr = 0ul; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + return enRet; +} +/** + ******************************************************************************* + ** \brief read unique ID. + ** + ** \param None + ** + ** \retval uint32_t + ** + ** \note None + ** + ******************************************************************************/ +stc_efm_unique_id_t EFM_ReadUID(void) +{ + stc_efm_unique_id_t stcUID; + + stcUID.uniqueID1 = M4_EFM->UQID1; + stcUID.uniqueID2 = M4_EFM->UQID2; + stcUID.uniqueID3 = M4_EFM->UQID3; + + return stcUID; +} + +//@} // EfmGroup + +#endif /* DDL_EFM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c new file mode 100644 index 000000000..9fe58408a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c @@ -0,0 +1,487 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.c + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_emb.h" +#include "hc32f460_utility.h" + +#if (DDL_EMB_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EMBGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for emb unit */ +#define IS_VALID_EMB_UNIT(__EMBx__) \ +( (M4_EMB1 == (__EMBx__)) || \ + (M4_EMB2 == (__EMBx__)) || \ + (M4_EMB3 == (__EMBx__)) || \ + (M4_EMB4 == (__EMBx__))) + +/*!< Parameter valid check for emb status*/ +#define IS_VALID_EMB_STATUS_TYPE(x) \ +( (EMBFlagPortIn == (x)) || \ + (EMBFlagPWMSame == (x)) || \ + (EMBFlagCmp == (x)) || \ + (EMBFlagOSCFail == (x)) || \ + (EMBPortInState == (x)) || \ + (EMBPWMState == (x))) + +/*!< Parameter valid check for emb status clear*/ +#define IS_VALID_EMB_STATUS_CLR(x) \ +( (EMBPortInFlagClr == (x)) || \ + (EMBPWMSameFlagCLr == (x)) || \ + (EMBCmpFlagClr == (x)) || \ + (EMBOSCFailFlagCLr == (x))) + +/*!< Parameter valid check for emb irq enable*/ +#define IS_VALID_EMB_IRQ(x) \ +( (PORTBrkIrq == (x)) || \ + (PWMSmBrkIrq == (x)) || \ + (CMPBrkIrq == (x)) || \ + (OSCFailBrkIrq == (x))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief EMB interrupt request enable or disable + * + * \param [in] EMBx EMB unit + * \param [in] enEMBIrq Irq type + * \param [in] bEn true/false + * + * \retval en_result_t Ok: config success + ******************************************************************************/ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_IRQ(enEMBIrq)); + + enRet = Ok; + switch (enEMBIrq) + { + case PORTBrkIrq: + EMBx->INTEN_f.PORTINTEN = (uint32_t)bEn; + break; + case PWMSmBrkIrq: + EMBx->INTEN_f.PWMINTEN = (uint32_t)bEn; + break; + case CMPBrkIrq: + EMBx->INTEN_f.CMPINTEN = (uint32_t)bEn; + break; + case OSCFailBrkIrq: + EMBx->INTEN_f.OSINTEN = (uint32_t)bEn; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get EMB status + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatus EMB status type + ** + ** \retval EMB status + ** + ******************************************************************************/ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus) +{ + bool status = false; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + DDL_ASSERT(IS_VALID_EMB_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case EMBFlagPortIn: + status = EMBx->STAT_f.PORTINF; + break; + case EMBFlagPWMSame: + status = EMBx->STAT_f.PWMSF; + break; + case EMBFlagCmp: + status = EMBx->STAT_f.CMPF; + break; + case EMBFlagOSCFail: + status = EMBx->STAT_f.OSF; + break; + case EMBPortInState: + status = EMBx->STAT_f.PORTINST; + break; + case EMBPWMState: + status = EMBx->STAT_f.PWMST; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief EMB clear status(Recover from protection state) + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatusClr EMB status clear type + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATUS_CLR(enStatusClr)); + + enRet = Ok; + switch (enStatusClr) + { + case EMBPortInFlagClr: + EMBx->STATCLR_f.PORTINFCLR = 1ul; + break; + case EMBPWMSameFlagCLr: + EMBx->STATCLR_f.PWMSFCLR = 1ul; + break; + case EMBCmpFlagClr: + EMBx->STATCLR_f.CMPFCLR = 1ul; + break; + case EMBOSCFailFlagCLr: + EMBx->STATCLR_f.OSFCLR = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBConfigCR) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer61PWMSBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer62PWMSBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer63PWMSBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + M4_EMB1->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((M4_EMB1 != EMBx) && \ + (IS_VALID_EMB_UNIT(EMBx)) && \ + (NULL != pstcEMBConfigCR)) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer4xWHLSammeBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer4xVHLSammeBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer4xUHLSammeBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + EMBx->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBPWMlv) + { + if (pstcEMBPWMlv->bEnTimer61HighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnTimer62HighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnTimer63HighLevelDect) + { + u32Val |= 0x4ul; + } + + M4_EMB1->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_EMB_UNIT(EMBx)) && \ + (M4_EMB1 != EMBx) && \ + (NULL != pstcEMBPWMlv)) + { + if (pstcEMBPWMlv->bEnWHLphaseHighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnVHLPhaseHighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnUHLPhaseHighLevelDect) + { + u32Val |= 0x4ul; + } + + EMBx->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief EMB Software brake + ** + ** \param [in] EMBx EMB unit + ** +** \param [in] bEn true: Software Brake Enable / false: Software Brake Disable + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + + EMBx->SOE_f.SOE = (uint32_t)bEn; + + return Ok; +} + +//@} // EMBGroup + +#endif /* DDL_EMB_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c new file mode 100644 index 000000000..fafc2adc7 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c @@ -0,0 +1,468 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.c + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_event_port.h" +#include "hc32f460_utility.h" + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EventPortGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EP1_BASE 0x40010800ul + 0x0100ul +#define EP2_BASE 0x40010800ul + 0x011Cul +#define EP3_BASE 0x40010800ul + 0x0138ul +#define EP4_BASE 0x40010800ul + 0x0154ul +#define EP1_DIR_BASE 0x00ul +#define EP1_IDR_BASE 0x04ul +#define EP1_ODR_BASE 0x08ul +#define EP1_ORR_BASE 0x0Cul +#define EP1_OSR_BASE 0x10ul +#define EP1_RISR_BASE 0x14ul +#define EP1_FAL_BASE 0x18ul +#define EP_NFCR_BASE 0x40010800ul + 0x0170ul + + +/*! Parameter validity check for port group. */ +#define IS_VALID_EVENT_PORT(x) \ +( ((x) == EventPort1) || \ + ((x) == EventPort2) || \ + ((x) == EventPort3) || \ + ((x) == EventPort4)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_EVENT_PIN(x) \ +( ((x) == EventPin00) || \ + ((x) == EventPin01) || \ + ((x) == EventPin02) || \ + ((x) == EventPin03) || \ + ((x) == EventPin04) || \ + ((x) == EventPin05) || \ + ((x) == EventPin06) || \ + ((x) == EventPin07) || \ + ((x) == EventPin08) || \ + ((x) == EventPin09) || \ + ((x) == EventPin10) || \ + ((x) == EventPin11) || \ + ((x) == EventPin12) || \ + ((x) == EventPin13) || \ + ((x) == EventPin14) || \ + ((x) == EventPin15)) + +/*! Parameter valid check for Event Port common trigger. */ +#define IS_EP_COM_TRIGGER(x) \ +( ((x) == EpComTrigger_1) || \ + ((x) == EpComTrigger_2) || \ + ((x) == EpComTrigger_1_2)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port init + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \param [in] pstcEventPortInit Structure pointer of event port configuration + ** + ** \retval Ok Init successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_Init(en_event_port_t enEventPort, uint16_t u16EventPin, \ + const stc_event_port_init_t *pstcEventPortInit) +{ + en_result_t enRet = Ok; + + uint32_t *EPDIRx; ///< Direction register + uint32_t *EPORRx; ///< Reset after trigger enable register + uint32_t *EPOSRx; ///< Set after trigger enable register + uint32_t *EPRISRx; ///< Rising edge detect enable register + uint32_t *EPFALx; ///< Falling edge detect enable register + + EPDIRx = (uint32_t *)(EP1_BASE + EP1_DIR_BASE + (0x1C * enEventPort)); + EPORRx = (uint32_t *)(EP1_BASE + EP1_ORR_BASE + (0x1C * enEventPort)); + EPOSRx = (uint32_t *)(EP1_BASE + EP1_OSR_BASE + (0x1C * enEventPort)); + EPRISRx= (uint32_t *)(EP1_BASE + EP1_RISR_BASE+ (0x1C * enEventPort)); + EPFALx = (uint32_t *)(EP1_BASE + EP1_FAL_BASE + (0x1C * enEventPort)); + + /* Direction configure */ + if (EventPortOut == pstcEventPortInit->enDirection) + { + *EPDIRx |= u16EventPin; + } + else + { + *EPDIRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Reset if be triggered */ + if (Enable == pstcEventPortInit->enReset) + { + *EPORRx |= u16EventPin; + } + else + { + *EPORRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Set if be triggered */ + if (Enable == pstcEventPortInit->enSet) + { + *EPOSRx |= u16EventPin; + } + else + { + *EPOSRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Rising edge detect setting */ + if (Enable == pstcEventPortInit->enRisingDetect) + { + *EPRISRx |= u16EventPin; + } + else + { + *EPRISRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Falling edge detect setting */ + if (Enable == pstcEventPortInit->enFallingDetect) + { + *EPFALx |= u16EventPin; + } + else + { + *EPFALx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Noise filter setting */ + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTNFCR_f.NFEN1 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS1 = pstcEventPortInit->enFilterClk; + break; + case EventPort2: + M4_AOS->PEVNTNFCR_f.NFEN2 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS2 = pstcEventPortInit->enFilterClk; + break; + case EventPort3: + M4_AOS->PEVNTNFCR_f.NFEN3 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS3 = pstcEventPortInit->enFilterClk; + break; + case EventPort4: + M4_AOS->PEVNTNFCR_f.NFEN4 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS4 = pstcEventPortInit->enFilterClk; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event Port de-init, restore all registers to default value + ** + ** \param None + ** + ** \retval Ok De-init successful + ** + ******************************************************************************/ +en_result_t EVENTPORT_DeInit(void) +{ + uint32_t EPDIRx ; + uint32_t EPODRx ; + uint32_t EPORRx ; + uint32_t EPOSRx ; + uint32_t EPRISRx; + uint32_t EPFALx ; + uint8_t u8EPCnt; + + EPDIRx = (uint32_t)(EP1_BASE + EP1_DIR_BASE); + EPODRx = (uint32_t)(EP1_BASE + EP1_ODR_BASE); + EPORRx = (uint32_t)(EP1_BASE + EP1_ORR_BASE); + EPOSRx = (uint32_t)(EP1_BASE + EP1_OSR_BASE); + EPRISRx = (uint32_t)(EP1_BASE + EP1_RISR_BASE); + EPFALx = (uint32_t)(EP1_BASE + EP1_FAL_BASE); + + /* Restore all registers to default value */ + M4_AOS->PORT_PEVNTTRGSR12 = 0x1FFul; + M4_AOS->PORT_PEVNTTRGSR34 = 0x1FFul; + M4_AOS->PEVNTNFCR = 0ul; + for (u8EPCnt = 0u; u8EPCnt < 4u; u8EPCnt++) + { + *(uint32_t *)(EPDIRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPODRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPORRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPOSRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPRISRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPFALx + 0x1Cul * u8EPCnt) = 0ul; + } + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event Port trigger source select + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enTriggerSrc Event port trigger source. This parameter + ** can be any value of @ref en_event_src_t + ** \retval Ok Trigger source is set + ** ErrorInvalidParameter Invalid event port enum + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + if ((EventPort1 == enEventPort) || (EventPort2 == enEventPort)) + { + M4_AOS->PORT_PEVNTTRGSR12 = enTriggerSrc; + } + else if ((EventPort3 == enEventPort) || (EventPort4 == enEventPort)) + { + M4_AOS->PORT_PEVNTTRGSR34 = enTriggerSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Event Port common trigger. + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enComTrigger Event port common trigger selection. + ** See @ref en_event_port_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx; + + TRGSELx = (__IO uint32_t *)((uint32_t)&M4_AOS->PORT_PEVNTTRGSR12 + (4UL * ((uint32_t)enEventPort/2UL))); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_EP_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Read Event Port value after be triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t EVENTPORT_GetData(en_event_port_t enEventPort) +{ + uint16_t u16Data = 0u; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + switch (enEventPort) + { + case EventPort1: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR1 & 0xFFFFul); + break; + case EventPort2: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR2 & 0xFFFFul); + break; + case EventPort3: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR3 & 0xFFFFul); + break; + case EventPort4: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR4 & 0xFFFFul); + break; + } + return u16Data; +} + +/** + ******************************************************************************* + ** \brief Read Event Pin value after triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enEventPin GPIO pin index, This parameter can be + ** any value of @ref en_event_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, en_event_pin_t enEventPin) +{ + bool bBitValue = false; + + switch (enEventPort) + { + case EventPort1: + bBitValue = M4_AOS->PEVNTIDR1 & enEventPin; + break; + case EventPort2: + bBitValue = M4_AOS->PEVNTIDR2 & enEventPin; + break; + case EventPort3: + bBitValue = M4_AOS->PEVNTIDR3 & enEventPin; + break; + case EventPort4: + bBitValue = M4_AOS->PEVNTIDR4 & enEventPin; + break; + } + return (en_flag_status_t)(bool)((!!bBitValue)); +} + +/** + ******************************************************************************* + ** \brief Set Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Set successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 |= u16EventPin; + break; + case EventPort2: + M4_AOS->PEVNTODR2 |= u16EventPin; + break; + case EventPort3: + M4_AOS->PEVNTODR3 |= u16EventPin; + break; + case EventPort4: + M4_AOS->PEVNTODR4 |= u16EventPin; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reset Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Reset successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort2: + M4_AOS->PEVNTODR2 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort3: + M4_AOS->PEVNTODR3 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort4: + M4_AOS->PEVNTODR4 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +//@} // EventPortGroup + +#endif /* DDL_EVENT_PORT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c new file mode 100644 index 000000000..56f5e9c18 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c @@ -0,0 +1,337 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.c + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_exint_nmi_swi.h" +#include "hc32f460_utility.h" + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup ExintNmiSwiGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + /*! Parameter validity check for external interrupt channel. */ +#define IS_VALID_CH(x) \ +( ((x) == ExtiCh00) || \ + ((x) == ExtiCh01) || \ + ((x) == ExtiCh02) || \ + ((x) == ExtiCh03) || \ + ((x) == ExtiCh04) || \ + ((x) == ExtiCh05) || \ + ((x) == ExtiCh06) || \ + ((x) == ExtiCh07) || \ + ((x) == ExtiCh08) || \ + ((x) == ExtiCh09) || \ + ((x) == ExtiCh10) || \ + ((x) == ExtiCh11) || \ + ((x) == ExtiCh12) || \ + ((x) == ExtiCh13) || \ + ((x) == ExtiCh14) || \ + ((x) == ExtiCh15)) + +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Parameter validity check for external interrupt trigger method. */ +#define IS_VALID_LEVEL(x) \ +( ((x) == ExIntLowLevel) || \ + ((x) == ExIntBothEdge) || \ + ((x) == ExIntRisingEdge) || \ + ((x) == ExIntFallingEdge)) + +/*! Parameter validity check for NMI interrupt source. */ +#define IS_VALID_NMI_SRC(x) \ +( ((x) == NmiSrcNmi) || \ + ((x) == NmiSrcSwdt) || \ + ((x) == NmiSrcVdu1) || \ + ((x) == NmiSrcVdu2) || \ + ((x) == NmiSrcXtalStop) || \ + ((x) == NmiSrcSramPE) || \ + ((x) == NmiSrcSramDE) || \ + ((x) == NmiSrcMpu) || \ + ((x) == NmiSrcWdt)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnNmiCallback; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief External Int initialization + ** + ** \param [in] pstcExtiConfig EXTI configure structure + ** + ** \retval Ok EXTI initialized + ** + ******************************************************************************/ +en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig) +{ + stc_intc_eirqcr_field_t *EIRQCRx; + + DDL_ASSERT(IS_VALID_CH(pstcExtiConfig->enExitCh)); + + EIRQCRx = (stc_intc_eirqcr_field_t *)((uint32_t)(&M4_INTC->EIRQCR0) + \ + (uint32_t)(4ul * (uint32_t)(pstcExtiConfig->enExitCh))); + + /* Set filter function */ + EIRQCRx->EFEN = pstcExtiConfig->enFilterEn; + EIRQCRx->EISMPCLK = pstcExtiConfig->enFltClk; + + /* Set detection level */ + EIRQCRx->EIRQTRG = pstcExtiConfig->enExtiLvl; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get External interrupt request flag + ** + ** \param [in] enExint NMI Int source, This parameter can be + ** any value of @ref en_exti_ch_t + ** + ** \retval Set Corresponding Ex.Int request flag be set + ** Reset Corresponding Ex.Int request flag not be set + ** + ******************************************************************************/ +en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint) +{ + en_int_status_t enRet; + DDL_ASSERT(IS_VALID_CH(enExint)); + + enRet = (1u == !!(M4_INTC->EIFR & (1ul<EICFR |= (uint32_t)(1ul << enExint); + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI initialization + ** + ** \param [in] pstcNmiConfig NMI configure structure + ** + ** \retval Ok NMI initialized + ** ErrorInvalidParameter NMI configuration pointer is null + ** + ******************************************************************************/ +en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcNmiConfig) + { + /* NMI callback function */ + pfnNmiCallback = pstcNmiConfig->pfnNmiCallback; + /* Set filter function */ + M4_INTC->NMICR_f.NFEN = pstcNmiConfig->enFilterEn; + /* Set filter clock */ + M4_INTC->NMICR_f.NSMPCLK = pstcNmiConfig->enFilterClk; + /* Set detection level */ + M4_INTC->NMICR_f.NMITRG = pstcNmiConfig->enNmiLvl; + /* Set NMI source */ + M4_INTC->NMIENR = (uint32_t)pstcNmiConfig->u16NmiSrc; + enRet = Ok; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Init Non-Maskable Interrupt (NMI) + ** + ** \param None + ** + ** \retval Ok NMI De-initialized + ** + ******************************************************************************/ +en_result_t NMI_DeInit(void) +{ + /* Set internal data */ + pfnNmiCallback = NULL; + + /* clear NMI control register */ + M4_INTC->NMICR = 0u; + + /* clear NMI enable register */ + M4_INTC->NMIENR = 0u; + + /* clear all NMI flags */ + M4_INTC->NMIFR = 0u; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get NMI interrupt request flag + ** + ** \param [in] enNmiSrc NMI Int source, This parameter can be + ** any value of @ref en_nmi_src_t + ** + ** \retval Set Corresponding NMI flag be set + ** Reset Corresponding NMI flag not be set + ** + ******************************************************************************/ +en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc) +{ + DDL_ASSERT(IS_VALID_NMI_SRC(enNmiSrc)); + + en_int_status_t enRet = Reset; + switch (enNmiSrc) + { + case NmiSrcNmi: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.NMIFR); + break; + case NmiSrcSwdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.SWDTFR); + break; + case NmiSrcVdu1: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD1FR); + break; + case NmiSrcVdu2: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD2FR); + break; + case NmiSrcXtalStop: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.XTALSTPFR); + break; + case NmiSrcSramPE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.REPFR); + break; + case NmiSrcSramDE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.RECCFR); + break; + case NmiSrcMpu: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.BUSMFR); + break; + case NmiSrcWdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.WDTFR); + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear NMI interrupt request flag + ** + ** \param [in] u16NmiSrc NMI Int source, This parameter can be + ** any composited value of @ref en_nmi_src_t + ** + ** \retval Ok Interrupt source be cleared + ** + ******************************************************************************/ +en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc) +{ + M4_INTC->NMICFR |= u16NmiSrc; + return Ok; +} + +/** + ******************************************************************************* + ** \brief ISR for NMI + ** + ******************************************************************************/ +void NMI_IrqHandler(void) +{ + DDL_ASSERT(IS_NULL_POINT(pfnNmiCallback)); + + pfnNmiCallback(); +} + +/** + ******************************************************************************* + ** \brief Enable Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI initialized + ** + ******************************************************************************/ +en_result_t SWI_Enable(uint32_t u32SwiCh) +{ + M4_INTC->SWIER |= u32SwiCh; + return Ok; +} + +/** + ******************************************************************************* + ** \brief De-Init Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI de-initialized + ** + ******************************************************************************/ +en_result_t SWI_Disable(uint32_t u32SwiCh) +{ + /* clear software interrupt enable register */ + M4_INTC->SWIER &= ~u32SwiCh; + + return Ok; +} + +//@} // ExintNmiSwiGroup + +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c new file mode 100644 index 000000000..16b8656f9 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c @@ -0,0 +1,671 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.c + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_gpio.h" +#include "hc32f460_utility.h" + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define GPIO_BASE (0x40053800ul) +#define PODR_BASE (0x0004ul) +#define POER_BASE (0x0006ul) +#define POSR_BASE (0x0008ul) +#define PORR_BASE (0x000Aul) +#define PCR_BASE (0x0400ul) +#define PFSR_BASE (0x0402ul) + +/*! Parameter validity check for port group. */ +#define IS_VALID_PORT(x) \ +( ((x) == PortA) || \ + ((x) == PortB) || \ + ((x) == PortC) || \ + ((x) == PortD) || \ + ((x) == PortE) || \ + ((x) == PortH)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_PIN(x) \ +( ((x) == Pin00) || \ + ((x) == Pin01) || \ + ((x) == Pin02) || \ + ((x) == Pin03) || \ + ((x) == Pin04) || \ + ((x) == Pin05) || \ + ((x) == Pin06) || \ + ((x) == Pin07) || \ + ((x) == Pin08) || \ + ((x) == Pin09) || \ + ((x) == Pin10) || \ + ((x) == Pin11) || \ + ((x) == Pin12) || \ + ((x) == Pin13) || \ + ((x) == Pin14) || \ + ((x) == Pin15)) + +/*! Parameter validity check for debug pins. */ +#define IS_VALID_DEBUGPIN(x) ((x) <= 0x1Fu) + +/*! Parameter validity check for pin mode. */ +#define IS_VALID_PINMODE(x) \ +( ((x) == Pin_Mode_In) || \ + ((x) == Pin_Mode_Out) || \ + ((x) == Pin_Mode_Ana)) + +/*! Parameter validity check for pin drive capacity. */ +#define IS_VALID_PINDRV(x) \ +( ((x) == Pin_Drv_L) || \ + ((x) == Pin_Drv_M) || \ + ((x) == Pin_Drv_H)) + +/*! Parameter validity check for pin output type. */ +#define IS_VALID_PINTYPE(x) \ +( ((x) == Pin_OType_Cmos) || \ + ((x) == Pin_OType_Od)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_VALID_READWAIT(x) \ +( ((x) == WaitCycle0) || \ + ((x) == WaitCycle1) || \ + ((x) == WaitCycle2) || \ + ((x) == WaitCycle3)) + +/*! Parameter validity check for pin function */ +#define IS_VALID_FUNC(x) \ +( ((x) == Func_Gpio) || \ + (((x) >= Func_Fcmref) && \ + ((x) <= Func_I2s)) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout) || \ + (((x) >= Func_Usart1_Tx) && \ + ((x) <= Func_I2s2_Ck))) + +/*! Parameter validity check for pin sub-function */ +#define IS_VALID_SUBFUNC(x) \ +( ((x) == Func_Gpio) || \ + ((x) == Func_Fcmref) || \ + ((x) == Func_Rtcout) || \ + ((x) == Func_Vcout) || \ + ((x) == Func_Adtrg) || \ + ((x) == Func_Mclkout) || \ + ((x) == Func_Tim4) || \ + ((x) == Func_Tim6) || \ + ((x) == Func_Tima0) || \ + ((x) == Func_Tima1) || \ + ((x) == Func_Tima2) || \ + ((x) == Func_Emb) || \ + ((x) == Func_Usart_Ck) || \ + ((x) == Func_Spi_Nss) || \ + ((x) == Func_Qspi) || \ + ((x) == Func_Key) || \ + ((x) == Func_Sdio) || \ + ((x) == Func_I2s) || \ + ((x) == Func_UsbF) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Port init + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] pstcPortInit Structure pointer of port configuration + ** + ** \retval Ok Port initial successful + ** + ******************************************************************************/ +en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, const stc_port_init_t *pstcPortInit) +{ + stc_port_pcr_field_t *PCRx; + stc_port_pfsr_field_t * PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + DDL_ASSERT(IS_VALID_PINMODE(pstcPortInit->enPinMode)); + DDL_ASSERT(IS_VALID_PINDRV(pstcPortInit->enPinDrv)); + DDL_ASSERT(IS_VALID_PINTYPE(pstcPortInit->enPinOType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enLatch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enExInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enInvert)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPullUp)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPinSubFunc)); + + PORT_Unlock(); + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (1ul<PCRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + + /* Input latch function setting */ + PCRx->LTE = pstcPortInit->enLatch; + + /* External interrupt input enable setting */ + PCRx->INTE = pstcPortInit->enExInt; + + /* In_Out invert setting */ + PCRx->INVE = pstcPortInit->enInvert; + + /* Pin pull-up setting */ + PCRx->PUU = pstcPortInit->enPullUp; + + /* CMOS/OD output setting */ + PCRx->NOD = pstcPortInit->enPinOType; + + /* Pin drive mode setting */ + PCRx->DRV = pstcPortInit->enPinDrv; + + /* Pin mode setting */ + switch (pstcPortInit->enPinMode) + { + case Pin_Mode_In: + PCRx->DDIS = 0u; + PCRx->POUTE = 0u; + break; + case Pin_Mode_Out: + PCRx->DDIS = 0u; + PCRx->POUTE = 1u; + break; + case Pin_Mode_Ana: + PCRx->DDIS = 1u; + break; + default: + break; + } + /* Sub function enable setting */ + PFSRx->BFE = pstcPortInit->enPinSubFunc; + } + } + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port de-init + ** + ** \param None + ** + ** \retval Ok GPIO de-initial successful + ** + ******************************************************************************/ +en_result_t PORT_DeInit(void) +{ + uint8_t u8PortIdx, u8PinIdx; + PORT_Unlock(); + + for (u8PortIdx = (uint8_t)PortA; u8PortIdx <= (uint8_t)PortH; u8PortIdx++) + { + *(uint16_t *)(GPIO_BASE + PODR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POER_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POSR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + PORR_BASE + u8PortIdx * 0x10ul) = 0u; + for (u8PinIdx = 0u; u8PinIdx < 16u; u8PinIdx++) + { + if (((uint8_t)PortH == u8PortIdx) && (3u == u8PinIdx)) + { + break; + } + *(uint16_t *)(GPIO_BASE + PCR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + *(uint16_t *)(GPIO_BASE + PFSR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + } + } + M4_PORT->PCCR = 0u; + M4_PORT->PINAER = 0u; + M4_PORT->PSPCR = 0x1Fu; + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Special control register Setting + ** + ** \param [in] u8DebugPort Debug port setting register, This parameter + ** can be any composed value of @ref en_debug_port_t + ** + ** \param [in] enFunc The new state of the debug ports. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Debug port set successful + ** + ******************************************************************************/ +en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_DEBUGPIN(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enFunc)); + + PORT_Unlock(); + + if (Enable == enFunc) + { + M4_PORT->PSPCR |= (uint16_t)(u8DebugPort & 0x1Ful); + } + else + { + M4_PORT->PSPCR &= (uint16_t)(~(u8DebugPort & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Public Setting + ** + ** \param [in] pstcPortPubSet Structure pointer of public setting (PCCR) + ** + ** \retval Ok Port public register set successful + ** + ******************************************************************************/ +en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet) +{ + DDL_ASSERT(IS_VALID_FUNC(pstcPortPubSet->enSubFuncSel)); + DDL_ASSERT(IS_VALID_READWAIT(pstcPortPubSet->enReadWait)); + PORT_Unlock(); + + /* PCCR setting */ + /* Sub function setting */ + M4_PORT->PCCR_f.BFSEL = pstcPortPubSet->enSubFuncSel; + + /* PIDRx, PCRxy read wait cycle setting */ + M4_PORT->PCCR_f.RDWT = pstcPortPubSet->enReadWait; + + PORT_Lock(); + return Ok; +} + + +/** + ******************************************************************************* + ** \brief PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Unlock(void) +{ + M4_PORT->PWPR = 0xA501u; +} + +/** + ******************************************************************************* + ** \brief SPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Lock(void) +{ + M4_PORT->PWPR = 0xA500u; +} + +/** + ******************************************************************************* + ** \brief Read Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t PORT_GetData(en_port_t enPort) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + uint32_t *PIDRx; + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (uint16_t)(*PIDRx); +} + +/** + ******************************************************************************* + ** \brief Read Pin value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enPin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin) +{ + uint32_t *PIDRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_PIN(enPin)); + + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (en_flag_status_t)((bool)(!!(*PIDRx & (enPin)))); +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be set to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be reset to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx &= (uint16_t)(~u16Pin); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Pin Output enable + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] enNewState The new state of pin direction setting + ** \retval Ok Set successful to corresponding port/pin + ** + ******************************************************************************/ +en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint16_t *POERx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POERx = (uint16_t *)((uint32_t)(&M4_PORT->POERA) + 0x10ul * enPort); + if (Enable == enNewState) + { + *POERx |= u16Pin; + } + else + { + *POERx &= (uint16_t)(~u16Pin); + } + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Set Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POSRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POSRx = (uint16_t *)((uint32_t)(&M4_PORT->POSRA) + 0x10u * enPort); + *POSRx |= u16Pin; + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Reset Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PORRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PORRx = (uint16_t *)((uint32_t)(&M4_PORT->PORRA) + 0x10u * enPort); + *PORRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Toggle Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POTRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POTRx = (uint16_t *)((uint32_t)(&M4_PORT->POTRA) + 0x10u * enPort); + *POTRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set port always ON + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enNewState The new state of the port always ON function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_AlwaysOn(en_port_t enPort, en_functional_state_t enNewState) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + PORT_Unlock(); + + if (Enable == enNewState) + { + M4_PORT->PINAER |= Enable << (uint8_t)enPort; + } + else + { + M4_PORT->PINAER &= (uint16_t)(~(((1ul << (uint8_t)enPort)) & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port Pin function + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \param [in] enFuncSel Function selection, This parameter can be + ** any value of @ref en_port_func_t + ** + ** \param [in] enSubFunc The new state of the gpio sub-function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, en_port_func_t enFuncSel, \ + en_functional_state_t enSubFunc) +{ + stc_port_pfsr_field_t *PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_FUNC(enFuncSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enSubFunc)); + + PORT_Unlock(); + + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (uint16_t)(1ul<PFSRA0) \ + + 0x40ul * enPort + 0x4ul * u8PinPos); + + /* main function setting */ + PFSRx->FSEL = enFuncSel; + + /* sub function enable setting */ + PFSRx->BFE = (Enable == enSubFunc ? Enable : Disable); + } + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set global sub-function + ** + ** \param [in] enFuncSel Function selection, This parameter can be + ** some values of @ref en_port_func_t, cannot + ** large than 15u + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_SUBFUNC(enFuncSel)); + + PORT_Unlock(); + + M4_PORT->PCCR_f.BFSEL = enFuncSel; + + PORT_Lock(); + return Ok; +} + +//@} // GpioGroup + +#endif /* DDL_GPIO_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c new file mode 100644 index 000000000..393736bac --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c @@ -0,0 +1,301 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.c + ** + ** A detailed description is available at + ** @link HashGroup HASH description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of HASH. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_hash.h" +#include "hc32f460_utility.h" + +#if (DDL_HASH_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup HashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Constants definitions. */ +#define HASH_GROUP_LEN (64u) +#define LAST_GROUP_MAX_LEN (56u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData); +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_Init(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; +} + +/** + ******************************************************************************* + ** \brief DeInitialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_DeInit(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; + + /* Reset register CR. */ + M4_HASH->CR = 0u; +} + +/** + ******************************************************************************* + ** \brief HASH(SHA256) processes pu8SrcData. + ** + ** \param [in] pu8SrcData Pointer to the source data buffer (buffer to + ** be hashed). + ** + ** \param [in] u32SrcDataSize Length of the input buffer in bytes. + ** + ** \param [out] pu8MsgDigest Pointer to the computed digest. Its size + ** must be 32 bytes. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout HASH works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8FillBuffer[HASH_GROUP_LEN]; + uint8_t u8FirstGroup = 0u; + uint8_t u8HashEnd = 0u; + uint8_t u8DataEndMark = 0u; + uint32_t u32Index = 0u; + uint32_t u32BitLenHi; + uint32_t u32BitLenLo; + uint32_t u32HashTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8SrcData) && + (0u != u32SrcDataSize) && + (NULL != pu8MsgDigest) && + (0u != u32Timeout)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32HashTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32BitLenHi = (u32SrcDataSize >> 29u) & 0x7u; + u32BitLenLo = (u32SrcDataSize << 3u); + + while (1u) + { + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + + if (u32SrcDataSize >= HASH_GROUP_LEN) + { + HASH_WriteData(&pu8SrcData[u32Index]); + u32SrcDataSize -= HASH_GROUP_LEN; + u32Index += HASH_GROUP_LEN; + } + else if (u32SrcDataSize >= LAST_GROUP_MAX_LEN) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + u8FillBuffer[u32SrcDataSize] = 0x80u; + u8DataEndMark = 1u; + HASH_WriteData(u8FillBuffer); + u32SrcDataSize = 0u; + } + else + { + u8HashEnd = 1u; + } + + if (u8HashEnd != 0u) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + if (u32SrcDataSize > 0u) + { + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + } + if (u8DataEndMark == 0u) + { + u8FillBuffer[u32SrcDataSize] = 0x80u; + } + u8FillBuffer[63u] = (uint8_t)(u32BitLenLo); + u8FillBuffer[62u] = (uint8_t)(u32BitLenLo >> 8u); + u8FillBuffer[61u] = (uint8_t)(u32BitLenLo >> 16u); + u8FillBuffer[60u] = (uint8_t)(u32BitLenLo >> 24u); + u8FillBuffer[59u] = (uint8_t)(u32BitLenHi); + u8FillBuffer[58u] = (uint8_t)(u32BitLenHi >> 8u); + u8FillBuffer[57u] = (uint8_t)(u32BitLenHi >> 16u); + u8FillBuffer[56u] = (uint8_t)(u32BitLenHi >> 24u); + HASH_WriteData(u8FillBuffer); + } + + /* check if first group */ + if (0u == u8FirstGroup) + { + u8FirstGroup = 1u; + /* Set first group. */ + bM4_HASH_CR_FST_GRP = 1u; + } + else + { + /* Set continuous group. */ + bM4_HASH_CR_FST_GRP = 0u; + } + + /* Start hash calculating. */ + bM4_HASH_CR_START = 1u; + + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32HashTimeout) + { + if (bM4_HASH_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if ((ErrorTimeout == enRet) || (u8HashEnd != 0u)) + { + break; + } + } + + if (Ok == enRet) + { + /* HASH calculated done */ + HASH_GetMsgDigest(pu8MsgDigest); + } + + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashDr = &(M4_HASH->DR15); + + for (i = 0u; i < 16u; i++) + { + j = i * 4u + 3u; + u32Temp = (uint32_t)pu8SrcData[j]; + u32Temp |= ((uint32_t)pu8SrcData[j-1u]) << 8u; + u32Temp |= ((uint32_t)pu8SrcData[j-2u]) << 16u; + u32Temp |= ((uint32_t)pu8SrcData[j-3u]) << 24u; + + *io32HashDr = u32Temp; + io32HashDr++; + } +} + +/** + ******************************************************************************* + ** \brief Provides the message digest result. + ** + ** \param [out] pu8MsgDigest Pointer to the message digest. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashHr = &(M4_HASH->HR7); + + for (i = 0u; i < 8u; i++) + { + j = i * 4u + 3u; + u32Temp = *io32HashHr; + + pu8MsgDigest[j] = (uint8_t)u32Temp; + pu8MsgDigest[j-1u] = (uint8_t)(u32Temp >> 8u); + pu8MsgDigest[j-2u] = (uint8_t)(u32Temp >> 16u); + pu8MsgDigest[j-3u] = (uint8_t)(u32Temp >> 24u); + + io32HashHr++; + } +} + +//@} // HashGroup + +#endif /* DDL_HASH_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c new file mode 100644 index 000000000..f5b4fddcd --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c @@ -0,0 +1,1318 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.c + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2c.h" +#include "hc32f460_utility.h" + +#if (DDL_I2C_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Config I2C peripheral */ +#define I2C_SRC_CLK (SystemCoreClock >> M4_SYSREG->CMU_SCFGR_f.PCLK3S) +#define I2C_ANA_FILTER_VALID (1U) +#define I2C_CLK_TIMEOUT_VALID (1U) + +#define I2C_BAUDRATE_MAX (400000ul) + +/*! Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_I2C1) || \ + ((x) == M4_I2C2) || \ + ((x) == M4_I2C3)) + +/*! Parameter check for I2C baudrate value !*/ +#define IS_VALID_SPEED(speed) ((speed) <= (I2C_BAUDRATE_MAX)) + +/*! Parameter check for I2C baudrate calculate prccess !*/ +#define IS_VALID_FDIV(x) \ +( ((x) == I2C_CLK_DIV1) || \ + ((x) == I2C_CLK_DIV2) || \ + ((x) == I2C_CLK_DIV4) || \ + ((x) == I2C_CLK_DIV8) || \ + ((x) == I2C_CLK_DIV16) || \ + ((x) == I2C_CLK_DIV32) || \ + ((x) == I2C_CLK_DIV64) || \ + ((x) == I2C_CLK_DIV128)) + +#define IS_VALID_BAUDWIDTH(result) ((result) == true) + +/*! Parameter check for Digital filter config !*/ +#define IS_VALID_DIGITAL_FILTER(x) \ +( ((x) == Filter1BaseCycle) || \ + ((x) == Filter2BaseCycle) || \ + ((x) == Filter3BaseCycle) || \ + ((x) == Filter4BaseCycle)) + +/*! Parameter check for address mode !*/ +#define IS_VALID_ADRMODE(x) \ +( ((x) == Adr7bit) || \ + ((x) == Adr10bit)) + +/*! Parameter check for I2C transfer direction !*/ +#define IS_VALID_TRANS_DIR(x) \ +( ((x) == I2CDirReceive) || \ + ((x) == I2CDirTrans)) + +/*! Parameter check for Time out control switch !*/ +#define IS_VALID_TIMOUT_SWITCH(x) \ +( ((x) == TimeoutFunOff) || \ + ((x) == LowTimerOutOn) || \ + ((x) == HighTimeOutOn) || \ + ((x) == BothTimeOutOn)) + +/*! Parameter check for I2C 7 bit address range !*/ +#define IS_VALID_7BIT_ADR(x) ((x) <= 0x7F) + +/*! Parameter check for I2C 10 bit address range !*/ +#define IS_VALID_10BIT_ADR(x) ((x) <= 0x3FF) + +/*! Parameter check for readable I2C status bit !*/ +#define IS_VALID_RD_STATUS_BIT(x) \ +( ((x) == I2C_SR_STARTF) || \ + ((x) == I2C_SR_SLADDR0F) || \ + ((x) == I2C_SR_SLADDR1F) || \ + ((x) == I2C_SR_TENDF) || \ + ((x) == I2C_SR_STOPF) || \ + ((x) == I2C_SR_RFULLF) || \ + ((x) == I2C_SR_TEMPTYF) || \ + ((x) == I2C_SR_ARLOF) || \ + ((x) == I2C_SR_ACKRF) || \ + ((x) == I2C_SR_NACKF) || \ + ((x) == I2C_SR_TMOUTF) || \ + ((x) == I2C_SR_MSL) || \ + ((x) == I2C_SR_BUSY) || \ + ((x) == I2C_SR_TRA) || \ + ((x) == I2C_SR_GENCALLF) || \ + ((x) == I2C_SR_SMBDEFAULTF) || \ + ((x) == I2C_SR_SMBHOSTF) || \ + ((x) == I2C_SR_SMBALRTF)) + +#define IS_VALID_ACK_CONFIG(x) \ +( ((x) == I2c_ACK) || \ + ((x) == I2c_NACK)) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1F * (float32_t)2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Try to wait a status of specified flags + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Flag specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \param [in] enStatus Expected status, This parameter can be one of + ** the following values: + ** Set + ** Reset + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Successfully gotten the expected status of the specified flags + ** \retval ErrorTimeout Failed to get expected status of specified flags. + ******************************************************************************/ +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorTimeout; + uint32_t u32RegStatusBit; + + for(;;) + { + u32RegStatusBit = (pstcI2Cx->SR & u32Flag); + if(((enStatus == Set) && (u32Flag == u32RegStatusBit)) + || ((enStatus == Reset) && (0UL == u32RegStatusBit))) + { + enRet = Ok; + } + + if((Ok == enRet) || (0UL == u32Timeout)) + { + break; + } + else + { + u32Timeout--; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C generate start condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState new state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.START = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C generate restart condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.RESTART = enNewState; + +} + +/** + ******************************************************************************* + ** \brief I2C generate stop condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.STOP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the baudrate for I2C peripheral. + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div + ** from @ref I2C_Clock_Division. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRet = Ok; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1ul << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if(1u == pstcI2Cx->FLTR_f.DNFEN) + { + dnfsum = pstcI2Cx->FLTR_f.DNF+1ul; + } + + /* Judge if clock divider on*/ + if(I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) + { + divsum = 3ul; + } + + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F*(float32_t)divsum) + (2.0F*(float32_t)dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) + { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } + else + { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if(WidthTotal <= SumTotal) + { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + if(WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) + { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + + /* Write register */ + pstcI2Cx->CCR_f.FREQ = pstcI2cInit->u32ClockDiv; + pstcI2Cx->CCR_f.SLOWW = (uint32_t)WidthHL/2u; + pstcI2Cx->CCR_f.SHIGHW = (uint32_t)WidthHL - ((uint32_t)WidthHL)/2u; + } + } + } + + if((NULL != pf32Error) && (Ok == enRet)) + { + *pf32Error = fErr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize I2C unit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval Ok Process finished. + ******************************************************************************/ +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Reset peripheral register and internal status*/ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Initialize I2C peripheral according to the structure + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div + ** from @ref I2C_Clock_Division. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRes = Ok; + if((NULL == pstcI2cInit) || (NULL == pstcI2Cx)) + { + enRes = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + + pstcI2Cx->CR1_f.PE = 1u; + + enRes = I2C_BaudrateConfig(pstcI2Cx, pstcI2cInit, pf32Error); + + pstcI2Cx->CR1_f.ENGC = 0u; + pstcI2Cx->CR1_f.SWRST = 0u; + pstcI2Cx->CR1_f.PE = 0u; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief I2C slave address0 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR0_f.SLADDR0EN = enNewState; + pstcI2Cx->SLR0_f.ADDRMOD0 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C slave address1 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR1_f.SLADDR1EN = enNewState; + pstcI2Cx->SLR1_f.ADDRMOD1 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.PE = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C fast ACK function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR3_f.FACKEN = 0ul; + } + else + { + pstcI2Cx->CR3_f.FACKEN = 1ul; + } +} + +/** + ******************************************************************************* + ** \brief I2C bus wait function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + uint32_t u32CR4_Reg = ((uint32_t)&pstcI2Cx->CR3) + 4ul; + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + *(__IO uint32_t *)u32CR4_Reg |= (1ul << 10ul); + } + else + { + *(__IO uint32_t *)u32CR4_Reg &= ~(1ul << 10ul); + } +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2C_SmbusInitStruct + ** Pointer to I2C SMBUS configuration structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct) +{ + en_result_t enRet = Ok; + if(NULL != pstcI2C_SmbusInitStruct) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enHostAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc)); + + pstcI2Cx->CR1_f.SMBHOSTEN = pstcI2C_SmbusInitStruct->enHostAdrMatchFunc; + pstcI2Cx->CR1_f.SMBDEFAULTEN = pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc; + pstcI2Cx->CR1_f.SMBALRTEN = pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SMBUS = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enDigiFilterMode Chose the digital filter mode, This parameter + ** can be one of the following values: + ** Filter1BaseCycle + ** Filter2BaseCycle + ** Filter3BaseCycle + ** Filter4BaseCycle + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_DIGITAL_FILTER(enDigiFilterMode)); + + pstcI2Cx->FLTR_f.DNF = enDigiFilterMode; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.DNFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C analog filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.ANFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C general call function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.ENGC = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C status bit get + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \retval en_flag_status_t The status of the I2C status flag, may be Set or Reset. + ******************************************************************************/ +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + en_flag_status_t enRet = Reset; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_RD_STATUS_BIT(u32StatusBit)); + + if(0ul != (pstcI2Cx->SR & u32StatusBit)) + { + enRet = Set; + } + else + { + enRet = Reset; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2C status flag + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to clear, + ** This parameter can be any combination of the following values: + ** I2C_CLR_STARTFCLR + ** I2C_CLR_SLADDR0FCLR + ** I2C_CLR_SLADDR1FCLR + ** I2C_CLR_TENDFCLR + ** I2C_CLR_STOPFCLR + ** I2C_CLR_RFULLFCLR + ** I2C_CLR_TEMPTYFCLR + ** I2C_CLR_ARLOFCLR + ** I2C_CLR_NACKFCLR + ** I2C_CLR_TMOUTFCLR + ** I2C_CLR_GENCALLFCLR + ** I2C_CLR_SMBDEFAULTFCLR + ** I2C_CLR_SMBHOSTFCLR + ** I2C_CLR_SMBALRTFCLR + ** \retval None + ******************************************************************************/ +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->CLR |= (u32StatusBit & I2C_CLR_MASK); +} + +/** + ******************************************************************************* + ** \brief I2C software reset function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SWRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C interrupt function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32IntEn Specifies the I2C interrupts sources to be configuration + ** This parameter can be any combination of the following values: + ** I2C_CR2_STARTIE + ** I2C_CR2_SLADDR0EN + ** I2C_CR2_SLADDR1EN + ** I2C_CR2_TENDIE + ** I2C_CR2_STOPIE + ** I2C_CR2_RFULLIE + ** I2C_CR2_TEMPTYIE + ** I2C_CR2_ARLOIE + ** I2C_CR2_NACKIE + ** I2C_CR2_TMOURIE + ** I2C_CR2_GENCALLIE + ** I2C_CR2_SMBDEFAULTIE + ** I2C_CR2_SMBHOSTIE + ** I2C_CR2_SMBALRTIE + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR2 |= u32IntEn; + } + else + { + pstcI2Cx->CR2 &= ~u32IntEn; + } +} + +/** + ******************************************************************************* + ** \brief I2C write data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Data The data to be send + ** \retval None + ******************************************************************************/ +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->DTR = u8Data; +} + +/** + ******************************************************************************* + ** \brief I2C read data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval uint8_t The value of the received data + ******************************************************************************/ +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + return pstcI2Cx->DRR; +} + +/** + ******************************************************************************* + ** \brief I2C ACK status configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32AckConfig I2C ACK configurate. + ** I2c_ACK: Send ACK after date received. + ** I2c_NACK: Send NACK after date received. + ** \retval None + ******************************************************************************/ +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_ACK_CONFIG(u32AckConfig)); + + pstcI2Cx->CR1_f.ACK = u32AckConfig; +} + +/** + ******************************************************************************* + ** \brief I2C clock timer out function config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcTimoutInit Pointer to I2C timeout function structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit) +{ + en_result_t enRet = Ok; + if(NULL != pstcTimoutInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_TIMOUT_SWITCH(pstcTimoutInit->enClkTimeOutSwitch)); + + pstcI2Cx->SLTR_f.TOUTHIGH = pstcTimoutInit->u16TimeOutHigh; + pstcI2Cx->SLTR_f.TOUTLOW = pstcTimoutInit->u16TimeOutLow; + + pstcI2Cx->CR3 &= ~0x00000007ul; + pstcI2Cx->CR3 |= pstcTimoutInit->enClkTimeOutSwitch; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx start + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Start success + ** \retval ErrorTimeout Start time out + ******************************************************************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_BUSY, Reset, u32Timeout); + + if(Ok == enRet) + { + /* generate start signal */ + I2C_GenerateStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx restart + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Restart successfully + ** \retval ErrorTimeout Restart time out + ******************************************************************************/ +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + /* Send restart condition */ + I2C_GenerateReStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_7BIT_ADR(u8Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Send I2C address */ + I2C_WriteData(pstcI2Cx, (u8Addr << 1u) | (uint8_t)enDir); + + if(I2CDirTrans == enDir) + { + /* If in master transfer process, Need wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + } + else + { + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + } + + if(enRet == Ok) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Set) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address 10 bit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u16Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_10BIT_ADR(u16Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirTrans); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + /* If receive ACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Reset) + { + /* Write SLA(bit7:0)*/ + I2C_WriteData(pstcI2Cx, (uint8_t)(u16Addr & 0xFFu)); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + else + { + enRet = Error; + } + } + } + + if((I2CDirReceive == enDir) && (Ok == enRet)) + { + /* Restart */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + I2C_GenerateReStart(pstcI2Cx, Enable); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STARTF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirReceive); + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + + if(Ok == enRet) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] au8TxData The data array to be sent + ** \param [in] u32Size Number of data in array pau8TxData + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval ErrorTimeout: Send data time out + ** \retval ErrorInvalidParameter: au8TxData is NULL + ******************************************************************************/ +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + en_result_t enRet = Ok; + __IO uint32_t u32Cnt = 0ul; + + if(au8TxData != NULL) + { + while((u32Cnt != u32Size) && (enRet == Ok)) + { + /* Wait tx buffer empty */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(enRet == Ok) + { + /* Send one byte data */ + I2C_WriteData(pstcI2Cx, au8TxData[u32Cnt]); + + /* Wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + /* If receive NACK in slave tx mode */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_NACKF) == Set) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_NACKFCLR); + /* Exit data transfer */ + break; + } + + u32Cnt++; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx receive data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx master receive data and stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* Stop before read last data */ + if(i == (u32Size - 1ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + I2C_GenerateStop(pstcI2Cx, Enable); + } + + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + + /* Wait stop flag after DRR read */ + if(i == (u32Size - 1ul)) + { + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + } + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ******************************************************************************/ +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear stop flag */ + while((Set == I2C_GetStatus(pstcI2Cx, I2C_SR_STOPF)) && (u32Timeout > 0ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + u32Timeout--; + } + I2C_GenerateStop(pstcI2Cx, Enable); + /* Wait stop flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + + return enRet; +} + +//@} // I2cGroup + +#endif /* DDL_I2C_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c new file mode 100644 index 000000000..ab18d3a2f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c @@ -0,0 +1,437 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.c + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2s.h" +#include "hc32f460_utility.h" + +#if (DDL_I2S_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup I2sGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for I2S register pointer */ +#define IS_VALID_I2S_REG(x) \ +( (M4_I2S1 == (x)) || \ + (M4_I2S2 == (x)) || \ + (M4_I2S3 == (x)) || \ + (M4_I2S4 == (x))) + +/*!< Parameter valid check for I2S function */ +#define IS_VALID_I2S_FUNCTION(x) \ +( (TxEn == (x)) || \ + (TxIntEn == (x)) || \ + (RxEn == (x)) || \ + (RxIntEn == (x)) || \ + (ErrIntEn == (x))) + +/*!< Parameter valid check for I2S status bits */ +#define IS_VALID_I2S_STATUS(x) \ +( (TxBufAlarmFlag == (x)) || \ + (RxBufAlarmFlag == (x)) || \ + (TxBufEmptFlag == (x)) || \ + (TxBufFullFlag == (x)) || \ + (RxBufEmptFlag == (x)) || \ + (RxBufFullFlag == (x))) + +/*!< Parameter valid check for I2S error flag */ +#define IS_VALID_I2S_ERR_FLAG(x) \ +( (ClrTxErrFlag == (x)) || \ + (ClrRxErrFlag == (x))) + +/*!< Parameter valid check for I2S mode */ +#define IS_VALID_I2S_MODE(x) \ +( (I2sMaster == (x)) || \ + (I2sSlave == (x))) + +/*!< Parameter valid check for I2S full duplex mode */ +#define IS_VALID_I2S_DUPLEX_MODE(x) \ +( (I2s_HalfDuplex == (x)) || \ + (I2s_FullDuplex == (x))) + +/*!< Parameter valid check for I2S standard */ +#define IS_VALID_I2S_STANDARD(x) \ +( (Std_Philips == (x)) || \ + (Std_MSBJust == (x)) || \ + (Std_LSBJust == (x)) || \ + (Std_PCM == (x))) + +/*!< Parameter valid check for I2S data length */ +#define IS_VALID_I2S_DATA_LEN(x) \ +( (I2s_DataLen_16Bit == (x)) || \ + (I2s_DataLen_24Bit == (x)) || \ + (I2s_DataLen_32Bit == (x))) + +/*!< Parameter valid check for I2S channel data length */ +#define IS_VALID_I2S_CHANNEL_LEN(x) \ +( (I2s_ChLen_16Bit == (x)) || \ + (I2s_ChLen_32Bit == (x))) + +/*!< Parameter valid check for I2S MCK output config */ +#define IS_VALID_I2S_MCKOUT(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S EXCK config */ +#define IS_VALID_I2S_EXCK(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S audio frequecy */ +#define IS_I2S_AUDIO_FREQ(FREQ) \ +( (((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) + +/*! I2S registers reset value */ +#define I2S_REG_CTRL_RESET_VALUE (0x00002200ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief I2S function command + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enFunc I2S function + ** \arg Refer @ref en_i2s_func_t + ** \param [in] enNewState New status + ** \arg Refer @ref en_functional_state_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_FUNCTION(enFunc)); + + if(Enable == enNewState) + { + if(0ul == (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL |= (1ul << enFunc); + } + } + else + { + if(0ul != (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL &= ~(1ul << (uint8_t)enFunc); + } + } +} + +/** + ******************************************************************************* + ** \brief Get I2S status bit + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enStd I2S status bit + ** \arg Refer @ref en_i2s_std_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd) +{ + en_flag_status_t enRet = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_STATUS(enStd)); + + if (0ul != ((uint32_t)(pstcI2sReg->SR & (1ul << (uint8_t)enStd)))) + { + enRet = Set; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + pstcI2sReg->ER |= (1ul << (uint8_t)enErrFlag); +} + +/** + ******************************************************************************* + ** \brief Get I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, + en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + return (en_flag_status_t)((uint32_t)(pstcI2sReg->ER | (1ul << (uint8_t)enErrFlag))); +} + +/** + ******************************************************************************* + ** \brief Write data to I2s data send register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] u32Data Data to be send + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + pstcI2sReg->TXBUF = u32Data; +} + +/** + ******************************************************************************* + ** \brief Read data from I2s data receive register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** + ** \retval uint32_t The data read out + ** + ******************************************************************************/ +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + return pstcI2sReg->RXBUF; +} + +/** + ******************************************************************************* + ** \brief Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] pstcI2sCfg Pointer to I2S configuration structure + ** + ** \retval Ok Initialize successfully done + ** + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg) +{ + uint32_t i2sclk = 0ul, tmp=0ul; + uint8_t u8ChanelDataBit,u8ChanMul; + uint16_t i2sdiv, i2sodd; + stc_i2s_cfgr_field_t stcCFGR_Tmp = {0}; + stc_i2s_ctrl_field_t stcCTRL_Tmp = {0}; + en_result_t enRes = Ok; + uint32_t u32AdrTmp = 0ul; + + if((NULL == pstcI2sReg)||(NULL == pstcI2sCfg)) + { + enRes = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_MODE(pstcI2sCfg->enMode)); + DDL_ASSERT(IS_VALID_I2S_DUPLEX_MODE(pstcI2sCfg->enFullDuplexMode)); + DDL_ASSERT(IS_VALID_I2S_STANDARD(pstcI2sCfg->enStandrad)); + DDL_ASSERT(IS_VALID_I2S_DATA_LEN(pstcI2sCfg->enDataBits)); + DDL_ASSERT(IS_VALID_I2S_CHANNEL_LEN(pstcI2sCfg->enChanelLen)); + DDL_ASSERT(IS_VALID_I2S_MCKOUT(pstcI2sCfg->enMcoOutEn)); + DDL_ASSERT(IS_VALID_I2S_EXCK(pstcI2sCfg->enExckEn)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sCfg->u32AudioFreq)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1ul; + pstcI2sReg->ER_f.RXERR = 1ul; + + //*(uint32_t*)&stcCTRL_Tmp = pstcI2sReg->CTRL; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + *(uint32_t*)u32AdrTmp = pstcI2sReg->CTRL; + + /* ---- config I2s clock source---- */ + if(Enable == pstcI2sCfg->enExckEn) + { + /* Set external clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 1ul; + stcCTRL_Tmp.I2SPLLSEL = 0ul; + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + } + else + { + /* Set internal clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 0ul; + stcCTRL_Tmp.I2SPLLSEL = 1ul; + /* Get i2s clock internal frequency */ + i2sclk = pstcI2sCfg->u32I2sInterClkFreq; + } + /* config audio sampple rate */ + if(I2s_ChLen_16Bit == pstcI2sCfg->enChanelLen) + { + u8ChanelDataBit = 16u; + u8ChanMul = 8u; + } + else + { + u8ChanelDataBit = 32u; + u8ChanMul = 4u; + } + + /*config I2S clock*/ + if(true == pstcI2sCfg->enMcoOutEn) + { + /* MCLK output is enabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul * u8ChanMul); + } + else + { + /* MCLK output is disabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul); + } + i2sodd = (uint16_t)(tmp & 0x0001ul); + i2sdiv = (uint16_t)((tmp - (uint32_t)i2sodd) / 2ul); + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2u) || (i2sdiv > 0xFFu)) + { + /* Set the default values */ + i2sdiv = 2u; + i2sodd = 0u; + } + + /* Write I2SPR register */ + pstcI2sReg->PR_f.I2SDIV = (uint8_t)i2sdiv; + + /* Config and write I2S_CFGR */ + stcCFGR_Tmp.CHLEN = pstcI2sCfg->enChanelLen; + stcCFGR_Tmp.DATLEN = pstcI2sCfg->enDataBits; + stcCFGR_Tmp.I2SSTD = pstcI2sCfg->enStandrad; + stcCFGR_Tmp.PCMSYNC = PCM_SYNC_FRAME; + pstcI2sReg->CFGR_f = stcCFGR_Tmp; + + /* Config CTRL register */ + stcCTRL_Tmp.WMS = pstcI2sCfg->enMode; + stcCTRL_Tmp.DUPLEX = pstcI2sCfg->enFullDuplexMode; + if(I2sMaster == pstcI2sCfg->enMode) + { + stcCTRL_Tmp.CKOE = 1u; + stcCTRL_Tmp.LRCKOE = 1u; + } + stcCTRL_Tmp.SDOE = 1u; + stcCTRL_Tmp.MCKOE = pstcI2sCfg->enMcoOutEn; + stcCTRL_Tmp.ODD = (uint8_t)i2sodd; + stcCTRL_Tmp.RXBIRQWL = RXBUF_IRQ_WL; + stcCTRL_Tmp.TXBIRQWL = TXBUF_IRQ_WL; + //pstcI2sReg->CTRL = *(uint32_t*)&stcCTRL_Tmp; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + pstcI2sReg->CTRL = *(uint32_t*)u32AdrTmp; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief De-Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1u; + pstcI2sReg->ER_f.RXERR = 1u; + + return Ok; +} + +//@} // I2sGroup + +#endif /* DDL_I2S_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c new file mode 100644 index 000000000..a3033d09b --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c @@ -0,0 +1,83 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.c + ** + ** A detailed description is available at + ** @link IcgGroup Initialize Configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_icg.h" + +#if (DDL_ICG_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup IcgGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICG[] __attribute__((at(0x400))) = +#elif defined (__ICCARM__) +__root const uint32_t u32ICG[] @ 0x400 = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~ 3 */ + ICG0_REGISTER_CONSTANT, + ICG1_REGISTER_CONSTANT, + ICG2_REGISTER_CONSTANT, + ICG3_REGISTER_CONSTANT, + /* ICG 4~ 7 */ + ICG4_REGISTER_CONSTANT, + ICG5_REGISTER_CONSTANT, + ICG6_REGISTER_CONSTANT, + ICG7_REGISTER_CONSTANT, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +//@} // IcgGroup + +#endif /* DDL_ICG_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c new file mode 100644 index 000000000..f7565d260 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c @@ -0,0 +1,3844 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/*****************************************************************************/ +/** \file hc32f460_interrupts.c + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_interrupts.h" +#include "hc32f460_utility.h" + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup InterruptGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Max IRQ Handler. */ +#define IRQ_NUM_MAX (128u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +func_ptr_t IrqHandler[IRQ_NUM_MAX] = {NULL}; + +/*! Parameter validity check for EXINT channel. */ +#define IS_EXINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXINT_CH_MASK) == EXINT_CH_MASK)) + +/** + ******************************************************************************* + ** \brief IRQ Registration + ** + ** param [in] pstcIrqRegiConf, IRQ registration + ** configure structure + ** + ** retval Ok, IRQ register successfully. + ** ErrorInvalidParameter, IRQ No. and + ** Vector No. are not match. + ** ErrorUninitialized, Make sure the + ** Interrupt select register (INTSEL) is + ** default value (0x1FFu) before setting. + ** + *****************************************************************************/ +en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf) +{ + // todo, assert ... + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + //DDL_ASSERT(NULL != pstcIrqRegiConf->pfnCallback); + DDL_ASSERT(IS_NULL_POINT(pstcIrqRegiConf->pfnCallback)); + + /* IRQ032~127 whether out of range */ + if (((((pstcIrqRegiConf->enIntSrc/32)*6 + 32) > pstcIrqRegiConf->enIRQn) || \ + (((pstcIrqRegiConf->enIntSrc/32)*6 + 37) < pstcIrqRegiConf->enIRQn)) && \ + (pstcIrqRegiConf->enIRQn >= 32)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + \ + (4u * pstcIrqRegiConf->enIRQn)); + if (0x1FFu == stcIntSel->INTSEL) + { + stcIntSel->INTSEL = pstcIrqRegiConf->enIntSrc; + IrqHandler[pstcIrqRegiConf->enIRQn] = pstcIrqRegiConf->pfnCallback; + } + else + { + enRet = ErrorUninitialized; + } + } + return enRet; +} +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval Set: Specified channel of external interrupt is triggered + * Reset: Specified channel of external interrupt is not triggered + */ +en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_CH(u32ExIntCh)); + + return ((READ_REG16(M4_INTC->EIFR) & u32ExIntCh) != 0U) ? Set : Reset; +} +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval None + */ +void EXINT_ClrExIntSrc(uint32_t u32ExIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_CH(u32ExIntCh)); + + SET_REG32_BIT(M4_INTC->EICFR, u32ExIntCh); +} +/** + ******************************************************************************* + ** \brief IRQ Resign + ** + ** param [in] enIRQn, IRQ enumunation (Int000_IRQn ~ + ** Int127_IRQn + ** + ** retval Ok, IRQ resign sucessfully. + ** ErrorInvalidParameter, IRQ No. is out + ** of range + ** + *****************************************************************************/ +en_result_t enIrqResign(IRQn_Type enIRQn) +{ + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + if ((enIRQn < Int000_IRQn) || (enIRQn > Int127_IRQn)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * enIRQn)); + stcIntSel->INTSEL = 0x1FFu; + IrqHandler[enIRQn] = NULL; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler enable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqEnable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx |= (uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler disable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqDisable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx &= ~(uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be enabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000ul)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN |= u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Disable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be disabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000u)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN &= ~u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be enabled + ** + ******************************************************************************/ +en_result_t enEventEnable(uint32_t u32Event) +{ + M4_INTC->EVTER |= u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be disabled + ** + ******************************************************************************/ +en_result_t enEventDisable(uint32_t u32Event) +{ + M4_INTC->EVTER &= ~u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt enable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be enabled + ** + ******************************************************************************/ +en_result_t enIntEnable(uint32_t u32Int) +{ + M4_INTC->IER |= u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt disable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be disabled + ** + ******************************************************************************/ +en_result_t enIntDisable(uint32_t u32Int) +{ + M4_INTC->IER &= ~u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI IRQ handler + ** + ******************************************************************************/ +void NMI_Handler(void) +{ + NMI_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Hard Fault IRQ handler + ** + ******************************************************************************/ +//void HardFault_Handler(void) +//{ +// HardFault_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief MPU Fault IRQ handler + ** + ******************************************************************************/ +void MemManage_Handler(void) +{ + MemManage_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Bus Fault IRQ handler + ** + ******************************************************************************/ +void BusFault_Handler(void) +{ + BusFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Usage Fault IRQ handler + ** + ******************************************************************************/ +void UsageFault_Handler(void) +{ + UsageFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief SVCall IRQ handler + ** + ******************************************************************************/ +void SVC_Handler(void) +{ + SVC_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief DebugMon IRQ handler + ** + ******************************************************************************/ +void DebugMon_Handler(void) +{ + DebugMon_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief PendSV IRQ handler + ** + ******************************************************************************/ +//void PendSV_Handler(void) +//{ +// PendSV_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief Systick IRQ handler + ** + ******************************************************************************/ +//void SysTick_Handler(void) +//{ +// SysTick_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief Int No.000 IRQ handler + ** + ******************************************************************************/ +void IRQ000_Handler(void) +{ + if (NULL != IrqHandler[Int000_IRQn]) + { + IrqHandler[Int000_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.001 IRQ handler + ** + ******************************************************************************/ +void IRQ001_Handler(void) +{ + if (NULL != IrqHandler[Int001_IRQn]) + { + IrqHandler[Int001_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.002 IRQ handler + ** + ******************************************************************************/ +void IRQ002_Handler(void) +{ + if (NULL != IrqHandler[Int002_IRQn]) + { + IrqHandler[Int002_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.003 IRQ handler + ** + ******************************************************************************/ +void IRQ003_Handler(void) +{ + if (NULL != IrqHandler[Int003_IRQn]) + { + IrqHandler[Int003_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.004 IRQ handler + ** + ******************************************************************************/ +void IRQ004_Handler(void) +{ + if (NULL != IrqHandler[Int004_IRQn]) + { + IrqHandler[Int004_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.005 IRQ handler + ** + ******************************************************************************/ +void IRQ005_Handler(void) +{ + if (NULL != IrqHandler[Int005_IRQn]) + { + IrqHandler[Int005_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.006 IRQ handler + ** + ******************************************************************************/ +void IRQ006_Handler(void) +{ + if (NULL != IrqHandler[Int006_IRQn]) + { + IrqHandler[Int006_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.007 IRQ handler + ** + ******************************************************************************/ +void IRQ007_Handler(void) +{ + if (NULL != IrqHandler[Int007_IRQn]) + { + IrqHandler[Int007_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.008 IRQ handler + ** + ******************************************************************************/ +void IRQ008_Handler(void) +{ + if (NULL != IrqHandler[Int008_IRQn]) + { + IrqHandler[Int008_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.009 IRQ handler + ** + ******************************************************************************/ +void IRQ009_Handler(void) +{ + if (NULL != IrqHandler[Int009_IRQn]) + { + IrqHandler[Int009_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.010 IRQ handler + ** + ******************************************************************************/ +void IRQ010_Handler(void) +{ + if (NULL != IrqHandler[Int010_IRQn]) + { + IrqHandler[Int010_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.011 IRQ handler + ** + ******************************************************************************/ +void IRQ011_Handler(void) +{ + if (NULL != IrqHandler[Int011_IRQn]) + { + IrqHandler[Int011_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.012 IRQ handler + ** + ******************************************************************************/ +void IRQ012_Handler(void) +{ + if (NULL != IrqHandler[Int012_IRQn]) + { + IrqHandler[Int012_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.013 IRQ handler + ** + ******************************************************************************/ +void IRQ013_Handler(void) +{ + if (NULL != IrqHandler[Int013_IRQn]) + { + IrqHandler[Int013_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.014 IRQ handler + ** + ******************************************************************************/ +void IRQ014_Handler(void) +{ + if (NULL != IrqHandler[Int014_IRQn]) + { + IrqHandler[Int014_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.015 IRQ handler + ** + ******************************************************************************/ +void IRQ015_Handler(void) +{ + if (NULL != IrqHandler[Int015_IRQn]) + { + IrqHandler[Int015_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.016 IRQ handler + ** + ******************************************************************************/ +void IRQ016_Handler(void) +{ + if (NULL != IrqHandler[Int016_IRQn]) + { + IrqHandler[Int016_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.017 IRQ handler + ** + ******************************************************************************/ +void IRQ017_Handler(void) +{ + if (NULL != IrqHandler[Int017_IRQn]) + { + IrqHandler[Int017_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.018 IRQ handler + ** + ******************************************************************************/ +void IRQ018_Handler(void) +{ + if (NULL != IrqHandler[Int018_IRQn]) + { + IrqHandler[Int018_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.019 IRQ handler + ** + ******************************************************************************/ +void IRQ019_Handler(void) +{ + if (NULL != IrqHandler[Int019_IRQn]) + { + IrqHandler[Int019_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.020 IRQ handler + ** + ******************************************************************************/ +void IRQ020_Handler(void) +{ + if (NULL != IrqHandler[Int020_IRQn]) + { + IrqHandler[Int020_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.021 IRQ handler + ** + ******************************************************************************/ +void IRQ021_Handler(void) +{ + if (NULL != IrqHandler[Int021_IRQn]) + { + IrqHandler[Int021_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.022 IRQ handler + ** + ******************************************************************************/ +void IRQ022_Handler(void) +{ + if (NULL != IrqHandler[Int022_IRQn]) + { + IrqHandler[Int022_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.023 IRQ handler + ** + ******************************************************************************/ +void IRQ023_Handler(void) +{ + if (NULL != IrqHandler[Int023_IRQn]) + { + IrqHandler[Int023_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.024 IRQ handler + ** + ******************************************************************************/ +void IRQ024_Handler(void) +{ + if (NULL != IrqHandler[Int024_IRQn]) + { + IrqHandler[Int024_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.025 IRQ handler + ** + ******************************************************************************/ +void IRQ025_Handler(void) +{ + if (NULL != IrqHandler[Int025_IRQn]) + { + IrqHandler[Int025_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.026 IRQ handler + ** + ******************************************************************************/ +void IRQ026_Handler(void) +{ + if (NULL != IrqHandler[Int026_IRQn]) + { + IrqHandler[Int026_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.027 IRQ handler + ** + ******************************************************************************/ +void IRQ027_Handler(void) +{ + if (NULL != IrqHandler[Int027_IRQn]) + { + IrqHandler[Int027_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.028 IRQ handler + ** + ******************************************************************************/ +void IRQ028_Handler(void) +{ + if (NULL != IrqHandler[Int028_IRQn]) + { + IrqHandler[Int028_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.029 IRQ handler + ** + ******************************************************************************/ +void IRQ029_Handler(void) +{ + if (NULL != IrqHandler[Int029_IRQn]) + { + IrqHandler[Int029_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.030 IRQ handler + ** + ******************************************************************************/ +void IRQ030_Handler(void) +{ + if (NULL != IrqHandler[Int030_IRQn]) + { + IrqHandler[Int030_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.031 IRQ handler + ** + ******************************************************************************/ +void IRQ031_Handler(void) +{ + if (NULL != IrqHandler[Int031_IRQn]) + { + IrqHandler[Int031_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.032 IRQ handler + ** + ******************************************************************************/ +void IRQ032_Handler(void) +{ + if (NULL != IrqHandler[Int032_IRQn]) + { + IrqHandler[Int032_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.033 IRQ handler + ** + ******************************************************************************/ +void IRQ033_Handler(void) +{ + if (NULL != IrqHandler[Int033_IRQn]) + { + IrqHandler[Int033_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.034 IRQ handler + ** + ******************************************************************************/ +void IRQ034_Handler(void) +{ + if (NULL != IrqHandler[Int034_IRQn]) + { + IrqHandler[Int034_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.035 IRQ handler + ** + ******************************************************************************/ +void IRQ035_Handler(void) +{ + if (NULL != IrqHandler[Int035_IRQn]) + { + IrqHandler[Int035_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.036 IRQ handler + ** + ******************************************************************************/ +void IRQ036_Handler(void) +{ + if (NULL != IrqHandler[Int036_IRQn]) + { + IrqHandler[Int036_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.037 IRQ handler + ** + ******************************************************************************/ +void IRQ037_Handler(void) +{ + if (NULL != IrqHandler[Int037_IRQn]) + { + IrqHandler[Int037_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.038 IRQ handler + ** + ******************************************************************************/ +void IRQ038_Handler(void) +{ + if (NULL != IrqHandler[Int038_IRQn]) + { + IrqHandler[Int038_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.039 IRQ handler + ** + ******************************************************************************/ +void IRQ039_Handler(void) +{ + if (NULL != IrqHandler[Int039_IRQn]) + { + IrqHandler[Int039_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.040 IRQ handler + ** + ******************************************************************************/ +void IRQ040_Handler(void) +{ + if (NULL != IrqHandler[Int040_IRQn]) + { + IrqHandler[Int040_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.041 IRQ handler + ** + ******************************************************************************/ +void IRQ041_Handler(void) +{ + if (NULL != IrqHandler[Int041_IRQn]) + { + IrqHandler[Int041_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.042 IRQ handler + ** + ******************************************************************************/ +void IRQ042_Handler(void) +{ + if (NULL != IrqHandler[Int042_IRQn]) + { + IrqHandler[Int042_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.043 IRQ handler + ** + ******************************************************************************/ +void IRQ043_Handler(void) +{ + if (NULL != IrqHandler[Int043_IRQn]) + { + IrqHandler[Int043_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.044 IRQ handler + ** + ******************************************************************************/ +void IRQ044_Handler(void) +{ + if (NULL != IrqHandler[Int044_IRQn]) + { + IrqHandler[Int044_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.045 IRQ handler + ** + ******************************************************************************/ +void IRQ045_Handler(void) +{ + if (NULL != IrqHandler[Int045_IRQn]) + { + IrqHandler[Int045_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.046 IRQ handler + ** + ******************************************************************************/ +void IRQ046_Handler(void) +{ + if (NULL != IrqHandler[Int046_IRQn]) + { + IrqHandler[Int046_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.047 IRQ handler + ** + ******************************************************************************/ +void IRQ047_Handler(void) +{ + if (NULL != IrqHandler[Int047_IRQn]) + { + IrqHandler[Int047_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.048 IRQ handler + ** + ******************************************************************************/ +void IRQ048_Handler(void) +{ + if (NULL != IrqHandler[Int048_IRQn]) + { + IrqHandler[Int048_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.049 IRQ handler + ** + ******************************************************************************/ +void IRQ049_Handler(void) +{ + if (NULL != IrqHandler[Int049_IRQn]) + { + IrqHandler[Int049_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.050 IRQ handler + ** + ******************************************************************************/ +void IRQ050_Handler(void) +{ + if (NULL != IrqHandler[Int050_IRQn]) + { + IrqHandler[Int050_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.051 IRQ handler + ** + ******************************************************************************/ +void IRQ051_Handler(void) +{ + if (NULL != IrqHandler[Int051_IRQn]) + { + IrqHandler[Int051_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.052 IRQ handler + ** + ******************************************************************************/ +void IRQ052_Handler(void) +{ + if (NULL != IrqHandler[Int052_IRQn]) + { + IrqHandler[Int052_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.053 IRQ handler + ** + ******************************************************************************/ +void IRQ053_Handler(void) +{ + if (NULL != IrqHandler[Int053_IRQn]) + { + IrqHandler[Int053_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.054 IRQ handler + ** + ******************************************************************************/ +void IRQ054_Handler(void) +{ + if (NULL != IrqHandler[Int054_IRQn]) + { + IrqHandler[Int054_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.055 IRQ handler + ** + ******************************************************************************/ +void IRQ055_Handler(void) +{ + if (NULL != IrqHandler[Int055_IRQn]) + { + IrqHandler[Int055_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.056 IRQ handler + ** + ******************************************************************************/ +void IRQ056_Handler(void) +{ + if (NULL != IrqHandler[Int056_IRQn]) + { + IrqHandler[Int056_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.057 IRQ handler + ** + ******************************************************************************/ +void IRQ057_Handler(void) +{ + if (NULL != IrqHandler[Int057_IRQn]) + { + IrqHandler[Int057_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.058 IRQ handler + ** + ******************************************************************************/ +void IRQ058_Handler(void) +{ + if (NULL != IrqHandler[Int058_IRQn]) + { + IrqHandler[Int058_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.059 IRQ handler + ** + ******************************************************************************/ +void IRQ059_Handler(void) +{ + if (NULL != IrqHandler[Int059_IRQn]) + { + IrqHandler[Int059_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.060 IRQ handler + ** + ******************************************************************************/ +void IRQ060_Handler(void) +{ + if (NULL != IrqHandler[Int060_IRQn]) + { + IrqHandler[Int060_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.061 IRQ handler + ** + ******************************************************************************/ +void IRQ061_Handler(void) +{ + if (NULL != IrqHandler[Int061_IRQn]) + { + IrqHandler[Int061_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.062 IRQ handler + ** + ******************************************************************************/ +void IRQ062_Handler(void) +{ + if (NULL != IrqHandler[Int062_IRQn]) + { + IrqHandler[Int062_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.063 IRQ handler + ** + ******************************************************************************/ +void IRQ063_Handler(void) +{ + if (NULL != IrqHandler[Int063_IRQn]) + { + IrqHandler[Int063_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.064 IRQ handler + ** + ******************************************************************************/ +void IRQ064_Handler(void) +{ + if (NULL != IrqHandler[Int064_IRQn]) + { + IrqHandler[Int064_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.065 IRQ handler + ** + ******************************************************************************/ +void IRQ065_Handler(void) +{ + if (NULL != IrqHandler[Int065_IRQn]) + { + IrqHandler[Int065_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.066 IRQ handler + ** + ******************************************************************************/ +void IRQ066_Handler(void) +{ + if (NULL != IrqHandler[Int066_IRQn]) + { + IrqHandler[Int066_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.067 IRQ handler + ** + ******************************************************************************/ +void IRQ067_Handler(void) +{ + if (NULL != IrqHandler[Int067_IRQn]) + { + IrqHandler[Int067_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.068 IRQ handler + ** + ******************************************************************************/ +void IRQ068_Handler(void) +{ + if (NULL != IrqHandler[Int068_IRQn]) + { + IrqHandler[Int068_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.069 IRQ handler + ** + ******************************************************************************/ +void IRQ069_Handler(void) +{ + if (NULL != IrqHandler[Int069_IRQn]) + { + IrqHandler[Int069_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.070 IRQ handler + ** + ******************************************************************************/ +void IRQ070_Handler(void) +{ + if (NULL != IrqHandler[Int070_IRQn]) + { + IrqHandler[Int070_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.071 IRQ handler + ** + ******************************************************************************/ +void IRQ071_Handler(void) +{ + if (NULL != IrqHandler[Int071_IRQn]) + { + IrqHandler[Int071_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.072 IRQ handler + ** + ******************************************************************************/ +void IRQ072_Handler(void) +{ + if (NULL != IrqHandler[Int072_IRQn]) + { + IrqHandler[Int072_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.073 IRQ handler + ** + ******************************************************************************/ +void IRQ073_Handler(void) +{ + if (NULL != IrqHandler[Int073_IRQn]) + { + IrqHandler[Int073_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.074 IRQ handler + ** + ******************************************************************************/ +void IRQ074_Handler(void) +{ + if (NULL != IrqHandler[Int074_IRQn]) + { + IrqHandler[Int074_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.075 IRQ handler + ** + ******************************************************************************/ +void IRQ075_Handler(void) +{ + if (NULL != IrqHandler[Int075_IRQn]) + { + IrqHandler[Int075_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.076 IRQ handler + ** + ******************************************************************************/ +void IRQ076_Handler(void) +{ + if (NULL != IrqHandler[Int076_IRQn]) + { + IrqHandler[Int076_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.077 IRQ handler + ** + ******************************************************************************/ +void IRQ077_Handler(void) +{ + if (NULL != IrqHandler[Int077_IRQn]) + { + IrqHandler[Int077_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.078 IRQ handler + ** + ******************************************************************************/ +void IRQ078_Handler(void) +{ + if (NULL != IrqHandler[Int078_IRQn]) + { + IrqHandler[Int078_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.079 IRQ handler + ** + ******************************************************************************/ +void IRQ079_Handler(void) +{ + if (NULL != IrqHandler[Int079_IRQn]) + { + IrqHandler[Int079_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.080 IRQ handler + ** + ******************************************************************************/ +void IRQ080_Handler(void) +{ + if (NULL != IrqHandler[Int080_IRQn]) + { + IrqHandler[Int080_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.081 IRQ handler + ** + ******************************************************************************/ +void IRQ081_Handler(void) +{ + if (NULL != IrqHandler[Int081_IRQn]) + { + IrqHandler[Int081_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.082 IRQ handler + ** + ******************************************************************************/ +void IRQ082_Handler(void) +{ + if (NULL != IrqHandler[Int082_IRQn]) + { + IrqHandler[Int082_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.083 IRQ handler + ** + ******************************************************************************/ +void IRQ083_Handler(void) +{ + if (NULL != IrqHandler[Int083_IRQn]) + { + IrqHandler[Int083_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.084 IRQ handler + ** + ******************************************************************************/ +void IRQ084_Handler(void) +{ + if (NULL != IrqHandler[Int084_IRQn]) + { + IrqHandler[Int084_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.085 IRQ handler + ** + ******************************************************************************/ +void IRQ085_Handler(void) +{ + if (NULL != IrqHandler[Int085_IRQn]) + { + IrqHandler[Int085_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.086 IRQ handler + ** + ******************************************************************************/ +void IRQ086_Handler(void) +{ + if (NULL != IrqHandler[Int086_IRQn]) + { + IrqHandler[Int086_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.087 IRQ handler + ** + ******************************************************************************/ +void IRQ087_Handler(void) +{ + if (NULL != IrqHandler[Int087_IRQn]) + { + IrqHandler[Int087_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.088 IRQ handler + ** + ******************************************************************************/ +void IRQ088_Handler(void) +{ + if (NULL != IrqHandler[Int088_IRQn]) + { + IrqHandler[Int088_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.089 IRQ handler + ** + ******************************************************************************/ +void IRQ089_Handler(void) +{ + if (NULL != IrqHandler[Int089_IRQn]) + { + IrqHandler[Int089_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.090 IRQ handler + ** + ******************************************************************************/ +void IRQ090_Handler(void) +{ + if (NULL != IrqHandler[Int090_IRQn]) + { + IrqHandler[Int090_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.091 IRQ handler + ** + ******************************************************************************/ +void IRQ091_Handler(void) +{ + if (NULL != IrqHandler[Int091_IRQn]) + { + IrqHandler[Int091_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.092 IRQ handler + ** + ******************************************************************************/ +void IRQ092_Handler(void) +{ + if (NULL != IrqHandler[Int092_IRQn]) + { + IrqHandler[Int092_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.093 IRQ handler + ** + ******************************************************************************/ +void IRQ093_Handler(void) +{ + if (NULL != IrqHandler[Int093_IRQn]) + { + IrqHandler[Int093_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.094 IRQ handler + ** + ******************************************************************************/ +void IRQ094_Handler(void) +{ + if (NULL != IrqHandler[Int094_IRQn]) + { + IrqHandler[Int094_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.095 IRQ handler + ** + ******************************************************************************/ +void IRQ095_Handler(void) +{ + if (NULL != IrqHandler[Int095_IRQn]) + { + IrqHandler[Int095_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.096 IRQ handler + ** + ******************************************************************************/ +void IRQ096_Handler(void) +{ + if (NULL != IrqHandler[Int096_IRQn]) + { + IrqHandler[Int096_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.097 IRQ handler + ** + ******************************************************************************/ +void IRQ097_Handler(void) +{ + if (NULL != IrqHandler[Int097_IRQn]) + { + IrqHandler[Int097_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.098 IRQ handler + ** + ******************************************************************************/ +void IRQ098_Handler(void) +{ + if (NULL != IrqHandler[Int098_IRQn]) + { + IrqHandler[Int098_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.099 IRQ handler + ** + ******************************************************************************/ +void IRQ099_Handler(void) +{ + if (NULL != IrqHandler[Int099_IRQn]) + { + IrqHandler[Int099_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.100 IRQ handler + ** + ******************************************************************************/ +void IRQ100_Handler(void) +{ + if (NULL != IrqHandler[Int100_IRQn]) + { + IrqHandler[Int100_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.101 IRQ handler + ** + ******************************************************************************/ +void IRQ101_Handler(void) +{ + if (NULL != IrqHandler[Int101_IRQn]) + { + IrqHandler[Int101_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.102 IRQ handler + ** + ******************************************************************************/ +void IRQ102_Handler(void) +{ + if (NULL != IrqHandler[Int102_IRQn]) + { + IrqHandler[Int102_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.103 IRQ handler + ** + ******************************************************************************/ +void IRQ103_Handler(void) +{ + if (NULL != IrqHandler[Int103_IRQn]) + { + IrqHandler[Int103_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.104 IRQ handler + ** + ******************************************************************************/ +void IRQ104_Handler(void) +{ + if (NULL != IrqHandler[Int104_IRQn]) + { + IrqHandler[Int104_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.105 IRQ handler + ** + ******************************************************************************/ +void IRQ105_Handler(void) +{ + if (NULL != IrqHandler[Int105_IRQn]) + { + IrqHandler[Int105_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.106 IRQ handler + ** + ******************************************************************************/ +void IRQ106_Handler(void) +{ + if (NULL != IrqHandler[Int106_IRQn]) + { + IrqHandler[Int106_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.107 IRQ handler + ** + ******************************************************************************/ +void IRQ107_Handler(void) +{ + if (NULL != IrqHandler[Int107_IRQn]) + { + IrqHandler[Int107_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.108 IRQ handler + ** + ******************************************************************************/ +void IRQ108_Handler(void) +{ + if (NULL != IrqHandler[Int108_IRQn]) + { + IrqHandler[Int108_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.109 IRQ handler + ** + ******************************************************************************/ +void IRQ109_Handler(void) +{ + if (NULL != IrqHandler[Int109_IRQn]) + { + IrqHandler[Int109_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.110 IRQ handler + ** + ******************************************************************************/ +void IRQ110_Handler(void) +{ + if (NULL != IrqHandler[Int110_IRQn]) + { + IrqHandler[Int110_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.111 IRQ handler + ** + ******************************************************************************/ +void IRQ111_Handler(void) +{ + if (NULL != IrqHandler[Int111_IRQn]) + { + IrqHandler[Int111_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.112 IRQ handler + ** + ******************************************************************************/ +void IRQ112_Handler(void) +{ + if (NULL != IrqHandler[Int112_IRQn]) + { + IrqHandler[Int112_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.113 IRQ handler + ** + ******************************************************************************/ +void IRQ113_Handler(void) +{ + if (NULL != IrqHandler[Int113_IRQn]) + { + IrqHandler[Int113_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.114 IRQ handler + ** + ******************************************************************************/ +void IRQ114_Handler(void) +{ + if (NULL != IrqHandler[Int114_IRQn]) + { + IrqHandler[Int114_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.115 IRQ handler + ** + ******************************************************************************/ +void IRQ115_Handler(void) +{ + if (NULL != IrqHandler[Int115_IRQn]) + { + IrqHandler[Int115_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.116 IRQ handler + ** + ******************************************************************************/ +void IRQ116_Handler(void) +{ + if (NULL != IrqHandler[Int116_IRQn]) + { + IrqHandler[Int116_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.117 IRQ handler + ** + ******************************************************************************/ +void IRQ117_Handler(void) +{ + if (NULL != IrqHandler[Int117_IRQn]) + { + IrqHandler[Int117_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.118 IRQ handler + ** + ******************************************************************************/ +void IRQ118_Handler(void) +{ + if (NULL != IrqHandler[Int118_IRQn]) + { + IrqHandler[Int118_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.119 IRQ handler + ** + ******************************************************************************/ +void IRQ119_Handler(void) +{ + if (NULL != IrqHandler[Int119_IRQn]) + { + IrqHandler[Int119_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.120 IRQ handler + ** + ******************************************************************************/ +void IRQ120_Handler(void) +{ + if (NULL != IrqHandler[Int120_IRQn]) + { + IrqHandler[Int120_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.121 IRQ handler + ** + ******************************************************************************/ +void IRQ121_Handler(void) +{ + if (NULL != IrqHandler[Int121_IRQn]) + { + IrqHandler[Int121_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.122 IRQ handler + ** + ******************************************************************************/ +void IRQ122_Handler(void) +{ + if (NULL != IrqHandler[Int122_IRQn]) + { + IrqHandler[Int122_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.123 IRQ handler + ** + ******************************************************************************/ +void IRQ123_Handler(void) +{ + if (NULL != IrqHandler[Int123_IRQn]) + { + IrqHandler[Int123_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.124 IRQ handler + ** + ******************************************************************************/ +void IRQ124_Handler(void) +{ + if (NULL != IrqHandler[Int124_IRQn]) + { + IrqHandler[Int124_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.125 IRQ handler + ** + ******************************************************************************/ +void IRQ125_Handler(void) +{ + if (NULL != IrqHandler[Int125_IRQn]) + { + IrqHandler[Int125_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.126 IRQ handler + ** + ******************************************************************************/ +void IRQ126_Handler(void) +{ + if (NULL != IrqHandler[Int126_IRQn]) + { + IrqHandler[Int126_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.127 IRQ handler + ** + ******************************************************************************/ +void IRQ127_Handler(void) +{ + if (NULL != IrqHandler[Int127_IRQn]) + { + IrqHandler[Int127_IRQn](); + } +} + +#if (DDL_INTERRUPTS_SHARE_ENABLE == DDL_ON) +/** + ******************************************************************************* + ** \brief Int No.128 share IRQ handler + ** + ******************************************************************************/ +void IRQ128_Handler(void) +{ + uint32_t VSSEL128 = M4_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1ul == bM4_INTC_EIFR_EIFR0) && (VSSEL128 & BIT_MASK_00)) + { + Extint00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1ul == bM4_INTC_EIFR_EIFR1) && (VSSEL128 & BIT_MASK_01)) + { + Extint01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1ul == bM4_INTC_EIFR_EIFR2) && (VSSEL128 & BIT_MASK_02)) + { + Extint02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1ul == bM4_INTC_EIFR_EIFR3) && (VSSEL128 & BIT_MASK_03)) + { + Extint03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1ul == bM4_INTC_EIFR_EIFR4) && (VSSEL128 & BIT_MASK_04)) + { + Extint04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1ul == bM4_INTC_EIFR_EIFR5) && (VSSEL128 & BIT_MASK_05)) + { + Extint05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1ul == bM4_INTC_EIFR_EIFR6) && (VSSEL128 & BIT_MASK_06)) + { + Extint06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1ul == bM4_INTC_EIFR_EIFR7) && (VSSEL128 & BIT_MASK_07)) + { + Extint07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1ul == bM4_INTC_EIFR_EIFR8) && (VSSEL128 & BIT_MASK_08)) + { + Extint08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1ul == bM4_INTC_EIFR_EIFR9) && (VSSEL128 & BIT_MASK_09)) + { + Extint09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1ul == bM4_INTC_EIFR_EIFR10) && (VSSEL128 & BIT_MASK_10)) + { + Extint10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1ul == bM4_INTC_EIFR_EIFR11) && (VSSEL128 & BIT_MASK_11)) + { + Extint11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1ul == bM4_INTC_EIFR_EIFR12) && (VSSEL128 & BIT_MASK_12)) + { + Extint12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1ul == bM4_INTC_EIFR_EIFR13) && (VSSEL128 & BIT_MASK_13)) + { + Extint13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1ul == bM4_INTC_EIFR_EIFR14) && (VSSEL128 & BIT_MASK_14)) + { + Extint14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1ul == bM4_INTC_EIFR_EIFR15) && (VSSEL128 & BIT_MASK_15)) + { + Extint15_IrqHandler(); + } +} + + +/** + ******************************************************************************* + ** \brief Int No.129 share IRQ handler + ** + ******************************************************************************/ +void IRQ129_Handler(void) +{ + uint32_t VSSEL129 =M4_INTC->VSSEL129; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + + if (1ul == bM4_DMA1_CH0CTL_IE) + { + /* DMA1 ch.0 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_00)) + { + Dma1Tc0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_08)) + { + Dma1Btc0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH1CTL_IE) + { + /* DMA1 ch.1 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_01)) + { + Dma1Tc1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_09)) + { + Dma1Btc1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH2CTL_IE) + { + /* DMA1 ch.2 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_02)) + { + Dma1Tc2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_10)) + { + Dma1Btc2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH3CTL_IE) + { + /* DMA1 ch.3 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_03)) + { + Dma1Tc3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_11)) + { + Dma1Btc3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err3_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH0CTL_IE) + { + /* DMA2 ch.0 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_04)) + { + Dma2Tc0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_12)) + { + Dma2Btc0_IrqHandler(); + } + } + /* DMA2 Ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH1CTL_IE) + { + /* DMA2 ch.1 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_05)) + { + Dma2Tc1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_13)) + { + Dma2Btc1_IrqHandler(); + } + } + /* DMA2 Ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH2CTL_IE) + { + /* DMA2 ch.2 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_06)) + { + Dma2Tc2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_14)) + { + Dma2Btc2_IrqHandler(); + } + } + /* DMA2 Ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH3CTL_IE) + { + /* DMA2 ch.3 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_07)) + { + Dma2Tc3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_15)) + { + Dma2Btc3_IrqHandler(); + } + } + /* DMA2 Ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err3_IrqHandler(); + } + } + /* EFM program/erase Error */ + if (1ul == bM4_EFM_FITE_PEERRITE) + { + if ((M4_EFM->FSR & 0x0Fu) && (VSSEL129 & BIT_MASK_18)) + { + EfmPgmEraseErr_IrqHandler(); + } + } + /* EFM collision Error */ + if (1ul == bM4_EFM_FITE_COLERRITE) + { + if ((1ul == bM4_EFM_FSR_COLERR) && (VSSEL129 & BIT_MASK_19)) + { + EfmColErr_IrqHandler(); + } + } + /* EFM operate end */ + if (1ul == bM4_EFM_FITE_OPTENDITE) + { + if ((1ul == bM4_EFM_FSR_OPTEND) && (VSSEL129 & BIT_MASK_20)) + { + EfmOpEnd_IrqHandler(); + } + } + /* QSPI interrupt */ + if ((1ul == M4_QSPI->SR_f.RAER) && (VSSEL129 & BIT_MASK_22)) + { + QspiInt_IrqHandler(); + } + /* DCU ch.1 */ + u32Tmp1 = M4_DCU1->INTSEL; + u32Tmp2 = M4_DCU1->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_23)) + { + Dcu1_IrqHandler(); + } + /* DCU ch.2 */ + u32Tmp1 = M4_DCU2->INTSEL; + u32Tmp2 = M4_DCU2->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_24)) + { + Dcu2_IrqHandler(); + } + /* DCU ch.3 */ + u32Tmp1 = M4_DCU3->INTSEL; + u32Tmp2 = M4_DCU3->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_25)) + { + Dcu3_IrqHandler(); + } + /* DCU ch.4 */ + u32Tmp1 = M4_DCU4->INTSEL; + u32Tmp2 = M4_DCU4->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_26)) + { + Dcu4_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.130 share IRQ handler + ** + ******************************************************************************/ +void IRQ130_Handler(void) +{ + uint32_t VSSEL130 = M4_INTC->VSSEL130; + /* Timer0 Ch. 1 A compare match */ + if (1ul == bM4_TMR01_BCONR_INTENA) + { + if ((1ul == bM4_TMR01_STFLR_CMAF) && (VSSEL130 & BIT_MASK_00)) + { + Timer01GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 1 B compare match */ + if (1ul == bM4_TMR01_BCONR_INTENB) + { + if ((1ul == bM4_TMR01_STFLR_CMBF) && (VSSEL130 & BIT_MASK_01)) + { + Timer01GCMB_IrqHandler(); + } + } + /* Timer0 Ch. 2 A compare match */ + if (1ul == bM4_TMR02_BCONR_INTENA) + { + if ((1ul == bM4_TMR02_STFLR_CMAF) && (VSSEL130 & BIT_MASK_02)) + { + Timer02GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 2 B compare match */ + if (1ul == bM4_TMR02_BCONR_INTENB) + { + if ((1ul == bM4_TMR02_STFLR_CMBF) && (VSSEL130 & BIT_MASK_03)) + { + Timer02GCMB_IrqHandler(); + } + } + /* Main-OSC stop */ + if (1ul == bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE) + { + if ((1ul == bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF) && (VSSEL130 & BIT_MASK_21)) + { + MainOscStop_IrqHandler(); + } + } + /* Wakeup timer */ + if ((1ul == bM4_WKTM_CR_WKOVF) && (VSSEL130 & BIT_MASK_22)) + { + WakeupTimer_IrqHandler(); + } + /* SWDT */ + if ((M4_SWDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL130 & BIT_MASK_23)) + { + Swdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.131 share IRQ handler + ** + ******************************************************************************/ +void IRQ131_Handler(void) +{ + uint32_t VSSEL131 = M4_INTC->VSSEL131; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.1 A compare match */ + if (1ul == bM4_TMR61_ICONR_INTENA) + { + if ((1ul == bM4_TMR61_STFLR_CMAF) && (VSSEL131 & BIT_MASK_00)) + { + Timer61GCMA_IrqHandler(); + } + } + /* Timer6 Ch.1 B compare match */ + if (1ul == bM4_TMR61_ICONR_INTENB) + { + if ((1ul == bM4_TMR61_STFLR_CMBF) && (VSSEL131 & BIT_MASK_01)) + { + Timer61GCMB_IrqHandler(); + } + } + /* Timer6 Ch.1 C compare match */ + if (1ul == bM4_TMR61_ICONR_INTENC) + { + if ((1ul == bM4_TMR61_STFLR_CMCF) && (VSSEL131 & BIT_MASK_02)) + { + Timer61GCMC_IrqHandler(); + } + } + /* Timer6 Ch.1 D compare match */ + if (1ul == bM4_TMR61_ICONR_INTEND) + { + if ((1ul == bM4_TMR61_STFLR_CMDF) && (VSSEL131 & BIT_MASK_03)) + { + Timer61GCMD_IrqHandler(); + } + } + /* Timer6 Ch.1 E compare match */ + if (1ul == bM4_TMR61_ICONR_INTENE) + { + if ((1ul == bM4_TMR61_STFLR_CMEF) && (VSSEL131 & BIT_MASK_04)) + { + Timer61GCME_IrqHandler(); + } + } + /* Timer6 Ch.1 F compare match */ + if (1ul == bM4_TMR61_ICONR_INTENF) + { + if ((1ul == bM4_TMR61_STFLR_CMFF) && (VSSEL131 & BIT_MASK_05)) + { + Timer61GCMF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow */ + if (1ul == bM4_TMR61_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR61_STFLR_OVFF) && (VSSEL131 & BIT_MASK_06)) + { + Timer61GOV_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow */ + if (1ul == bM4_TMR61_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR61_STFLR_UDFF) && (VSSEL131 & BIT_MASK_07)) + { + Timer61GUD_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1ul == bM4_TMR61_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR61_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_08)) + { + Timer61GDT_IrqHandler(); + } + } + /* Timer6 Ch.1 A up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_11)) + { + Timer61SCMA_IrqHandler(); + } + /* Timer6 Ch.1 B up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_12)) + { + Timer61SCMB_IrqHandler(); + } + /* Timer6 Ch.2 A compare match */ + if (1ul == bM4_TMR62_ICONR_INTENA) + { + if ((1ul == bM4_TMR62_STFLR_CMAF) && (VSSEL131 & BIT_MASK_16)) + { + Timer62GCMA_IrqHandler(); + } + } + /* Timer6 Ch.2 B compare match */ + if (1ul == bM4_TMR62_ICONR_INTENB) + { + if ((1ul == bM4_TMR62_STFLR_CMBF) && (VSSEL131 & BIT_MASK_17)) + { + Timer62GCMB_IrqHandler(); + } + } + /* Timer6 Ch.2 C compare match */ + if (1ul == bM4_TMR62_ICONR_INTENC) + { + if ((1ul == bM4_TMR62_STFLR_CMCF) && (VSSEL131 & BIT_MASK_18)) + { + Timer62GCMC_IrqHandler(); + } + } + /* Timer6 Ch.2 D compare match */ + if (1ul == bM4_TMR62_ICONR_INTEND) + { + if ((1ul == bM4_TMR62_STFLR_CMDF) && (VSSEL131 & BIT_MASK_19)) + { + Timer62GCMD_IrqHandler(); + } + } + /* Timer6 Ch.2 E compare match */ + if (1ul == bM4_TMR62_ICONR_INTENE) + { + if ((1ul == bM4_TMR62_STFLR_CMEF) && (VSSEL131 & BIT_MASK_20)) + { + Timer62GCME_IrqHandler(); + } + } + /* Timer6 Ch.2 F compare match */ + if (1ul == bM4_TMR62_ICONR_INTENF) + { + if ((1ul == bM4_TMR62_STFLR_CMFF) && (VSSEL131 & BIT_MASK_21)) + { + Timer62GCMF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow */ + if (1ul == bM4_TMR62_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR62_STFLR_OVFF) && (VSSEL131 & BIT_MASK_22)) + { + Timer62GOV_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow */ + if (1ul == bM4_TMR62_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR62_STFLR_UDFF) && (VSSEL131 & BIT_MASK_23)) + { + Timer62GUD_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1ul == bM4_TMR62_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR62_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_24)) + { + Timer62GDT_IrqHandler(); + } + } + /* Timer6 Ch.2 A up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_27)) + { + Timer62SCMA_IrqHandler(); + } + /* Timer6 Ch.2 B up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_28)) + { + Timer62SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.132 share IRQ handler + ** + ******************************************************************************/ +void IRQ132_Handler(void) +{ + uint32_t VSSEL132 = M4_INTC->VSSEL132; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.3 A compare match */ + if (1ul == bM4_TMR63_ICONR_INTENA) + { + if ((1ul == bM4_TMR63_STFLR_CMAF) && (VSSEL132 & BIT_MASK_00)) + { + Timer63GCMA_IrqHandler(); + } + } + /* Timer6 Ch.3 B compare match */ + if (1ul == bM4_TMR63_ICONR_INTENB) + { + if ((1ul == bM4_TMR63_STFLR_CMBF) && (VSSEL132 & BIT_MASK_01)) + { + Timer63GCMB_IrqHandler(); + } + } + /* Timer6 Ch.3 C compare match */ + if (1ul == bM4_TMR63_ICONR_INTENC) + { + if ((1ul == bM4_TMR63_STFLR_CMCF) && (VSSEL132 & BIT_MASK_02)) + { + Timer63GCMC_IrqHandler(); + } + } + /* Timer6 Ch.3 D compare match */ + if (1ul == bM4_TMR63_ICONR_INTEND) + { + if ((1ul == bM4_TMR63_STFLR_CMDF) && (VSSEL132 & BIT_MASK_03)) + { + Timer63GCMD_IrqHandler(); + } + } + /* Timer6 Ch.3 E compare match */ + if (1ul == bM4_TMR63_ICONR_INTENE) + { + if ((1ul == bM4_TMR63_STFLR_CMEF) && (VSSEL132 & BIT_MASK_04)) + { + Timer63GCME_IrqHandler(); + } + } + /* Timer6 Ch.3 F compare match */ + if (1ul == bM4_TMR63_ICONR_INTENF) + { + if ((1ul == bM4_TMR63_STFLR_CMFF) && (VSSEL132 & BIT_MASK_05)) + { + Timer63GCMF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow */ + if (1ul == bM4_TMR63_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR63_STFLR_OVFF) && (VSSEL132 & BIT_MASK_06)) + { + Timer63GOV_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow */ + if (1ul == bM4_TMR63_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR63_STFLR_UDFF) && (VSSEL132 & BIT_MASK_07)) + { + Timer63GUD_IrqHandler(); + } + } + /* Timer6 Ch.3 dead time */ + if (1ul == bM4_TMR63_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR63_STFLR_DTEF)) && (VSSEL132 & BIT_MASK_08)) + { + Timer63GDT_IrqHandler(); + } + } + /* Timer6 Ch.3 A up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_11)) + { + Timer63SCMA_IrqHandler(); + } + /* Timer6 Ch.3 B up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_12)) + { + Timer63SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.136 share IRQ handler + ** + ******************************************************************************/ +void IRQ136_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL136 = M4_INTC->VSSEL136; + + u32Tmp1 = M4_TMRA1->BCSTR; + /* TimerA Ch.1 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_00)) + { + TimerA1OV_IrqHandler(); + } + /* TimerA Ch.1 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_01)) + { + TimerA1UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA1->ICONR; + u32Tmp2 = M4_TMRA1->STFLR; + /* TimerA Ch.1 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_02)) + { + TimerA1CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA2->BCSTR; + /* TimerA Ch.2 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_03)) + { + TimerA2OV_IrqHandler(); + } + /* TimerA Ch.2 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_04)) + { + TimerA2UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA2->ICONR; + u32Tmp2 = M4_TMRA2->STFLR; + /* TimerA Ch.2 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_05)) + { + TimerA2CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA3->BCSTR; + /* TimerA Ch.3 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_06)) + { + TimerA3OV_IrqHandler(); + } + /* TimerA Ch.3 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_07)) + { + TimerA3UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA3->ICONR; + u32Tmp2 = M4_TMRA3->STFLR; + /* TimerA Ch.3 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_08)) + { + TimerA3CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA4->BCSTR; + /* TimerA Ch.4 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_09)) + { + TimerA4OV_IrqHandler(); + } + /* TimerA Ch.4 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_10)) + { + TimerA4UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA4->ICONR; + u32Tmp2 = M4_TMRA4->STFLR; + /* TimerA Ch.4 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_11)) + { + TimerA4CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA5->BCSTR; + /* TimerA Ch.5 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_12)) + { + TimerA5OV_IrqHandler(); + } + /* TimerA Ch.5 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_13)) + { + TimerA5UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA5->ICONR; + u32Tmp2 = M4_TMRA5->STFLR; + /* TimerA Ch.5 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_14)) + { + TimerA5CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA6->BCSTR; + /* TimerA Ch.6 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_16)) + { + TimerA6OV_IrqHandler(); + } + /* TimerA Ch.6 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_17)) + { + TimerA6UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA6->ICONR; + u32Tmp2 = M4_TMRA6->STFLR; + /* TimerA Ch.6 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_18)) + { + TimerA6CMP_IrqHandler(); + } + /* USBFS global interrupt */ + if(1ul == bM4_USBFS_GAHBCFG_GINTMSK) + { + u32Tmp1 = M4_USBFS->GINTMSK & 0xF77CFCFBul; + u32Tmp2 = M4_USBFS->GINTSTS & 0xF77CFCFBul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL136 & BIT_MASK_19)) + { + UsbGlobal_IrqHandler(); + } + } + + u32Tmp1 = M4_USART1->SR; + u32Tmp2 = M4_USART1->CR1; + /* USART Ch.1 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_22)) + { + Usart1RxErr_IrqHandler(); + } + /* USART Ch.1 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_23)) + { + Usart1RxEnd_IrqHandler(); + } + /* USART Ch.1 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_24)) + { + Usart1TxEmpty_IrqHandler(); + } + /* USART Ch.1 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_25)) + { + Usart1TxEnd_IrqHandler(); + } + /* USART Ch.1 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_26)) + { + Usart1RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART2->SR; + u32Tmp2 = M4_USART2->CR1; + /* USART Ch.2 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_27)) + { + Usart2RxErr_IrqHandler(); + } + /* USART Ch.2 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_28)) + { + Usart2RxEnd_IrqHandler(); + } + /* USART Ch.2 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_29)) + { + Usart2TxEmpty_IrqHandler(); + } + /* USART Ch.2 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_30)) + { + Usart2TxEnd_IrqHandler(); + } + /* USART Ch.2 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_31)) + { + Usart2RxTO_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.137 share IRQ handler + ** + ******************************************************************************/ +void IRQ137_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL137 = M4_INTC->VSSEL137; + + u32Tmp1 = M4_USART3->SR; + u32Tmp2 = M4_USART3->CR1; + /* USART Ch.3 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_00)) + { + Usart3RxErr_IrqHandler(); + } + /* USART Ch.3 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_01)) + { + Usart3RxEnd_IrqHandler(); + } + /* USART Ch.3 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_02)) + { + Usart3TxEmpty_IrqHandler(); + } + /* USART Ch.3 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_03)) + { + Usart3TxEnd_IrqHandler(); + } + /* USART Ch.3 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_04)) + { + Usart3RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART4->SR; + u32Tmp2 = M4_USART4->CR1; + /* USART Ch.4 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_05)) + { + Usart4RxErr_IrqHandler(); + } + /* USART Ch.4 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_06)) + { + Usart4RxEnd_IrqHandler(); + } + /* USART Ch.4 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_07)) + { + Usart4TxEmpty_IrqHandler(); + } + /* USART Ch.4 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_08)) + { + Usart4TxEnd_IrqHandler(); + } + /* USART Ch.4 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_09)) + { + Usart4RxTO_IrqHandler(); + } + + u32Tmp1 = M4_SPI1->CR1; + u32Tmp2 = M4_SPI1->SR; + /* SPI Ch.1 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_11)) + { + Spi1RxEnd_IrqHandler(); + } + /* SPI Ch.1 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_12)) + { + Spi1TxEmpty_IrqHandler(); + } + /* SPI Ch.1 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_13)) + { + Spi1Idle_IrqHandler(); + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_14)) + { + Spi1Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI2->CR1; + u32Tmp2 = M4_SPI2->SR; + /* SPI Ch.2 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_16)) + { + Spi2RxEnd_IrqHandler(); + } + /* SPI Ch.2 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_17)) + { + Spi2TxEmpty_IrqHandler(); + } + /* SPI Ch.2 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_18)) + { + Spi2Idle_IrqHandler(); + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_19)) + { + Spi2Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI3->CR1; + u32Tmp2 = M4_SPI3->SR; + /* SPI Ch.3 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_21)) + { + Spi3RxEnd_IrqHandler(); + } + /* SPI Ch.3 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_22)) + { + Spi3TxEmpty_IrqHandler(); + } + /* SPI Ch.3 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_23)) + { + Spi3Idle_IrqHandler(); + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_24)) + { + Spi3Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI4->CR1; + u32Tmp2 = M4_SPI4->SR; + /* SPI Ch.4 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_26)) + { + Spi4RxEnd_IrqHandler(); + } + /* SPI Ch.4 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_27)) + { + Spi4TxEmpty_IrqHandler(); + } + /* SPI Ch.4 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_28)) + { + Spi4Idle_IrqHandler(); + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_29)) + { + Spi4Err_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.138 share IRQ handler + ** + ******************************************************************************/ +void IRQ138_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL138 = M4_INTC->VSSEL138; + + u32Tmp1 = M4_TMR41->OCSRU; + /* Timer4 Ch.1 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.1 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRV; + /* Timer4 Ch.1 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMVH_IrqHandler(); + } + /* Timer4 Ch.1 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRW; + /* Timer4 Ch.1 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMWH_IrqHandler(); + } + /* Timer4 Ch.1 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->CCSR; + /* Timer4 Ch.1 overflow */ + if ((VSSEL138 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer41GOV_IrqHandler(); + } + /* Timer4 Ch.1 underflow */ + if ((VSSEL138 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer41GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->RCSR; + /* Timer4 Ch.1 U phase reload */ + if ((VSSEL138 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.1 V phase reload */ + if ((VSSEL138 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer41ReloadV_IrqHandler(); + } + /* Timer4 Ch.1 W phase reload */ + if ((VSSEL138 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer41ReloadW_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRU; + /* Timer4 Ch.2 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_16) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.2 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_17) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRV; + /* Timer4 Ch.2 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_18) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMVH_IrqHandler(); + } + /* Timer4 Ch.2 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_19) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRW; + /* Timer4 Ch.2 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_20) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMWH_IrqHandler(); + } + /* Timer4 Ch.2 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_21) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->CCSR; + /* Timer4 Ch.2 overflow */ + if ((VSSEL138 & BIT_MASK_22) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer42GOV_IrqHandler(); + } + /* Timer4 Ch.2 underflow */ + if ((VSSEL138 & BIT_MASK_23) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer42GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->RCSR; + /* Timer4 Ch.2 U phase reload */ + if ((VSSEL138 & BIT_MASK_24) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer42ReloadU_IrqHandler(); + } + /* Timer4 Ch.2 V phase reload */ + if ((VSSEL138 & BIT_MASK_25) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer42ReloadV_IrqHandler(); + } + /* Timer4 Ch.2 W phase reload */ + if ((VSSEL138 & BIT_MASK_26) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer42ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.139 share IRQ handler + ** + ******************************************************************************/ +void IRQ139_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL139 = M4_INTC->VSSEL139; + + u32Tmp1 = M4_TMR43->OCSRU; + /* Timer4 Ch.3 U phase higher compare match */ + if ((VSSEL139 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMUH_IrqHandler(); + } + /* Timer4 Ch.3 U phase lower compare match */ + if ((VSSEL139 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRV; + /* Timer4 Ch.3 V phase higher compare match */ + if ((VSSEL139 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMVH_IrqHandler(); + } + /* Timer4 Ch.3 V phase lower compare match */ + if ((VSSEL139 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRW; + /* Timer4 Ch.3 W phase higher compare match */ + if ((VSSEL139 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMWH_IrqHandler(); + } + /* Timer4 Ch.3 W phase lower compare match */ + if ((VSSEL139 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->CCSR; + /* Timer4 Ch.3 overflow */ + if ((VSSEL139 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer43GOV_IrqHandler(); + } + /* Timer4 Ch.3 underflow */ + if ((VSSEL139 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer43GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->RCSR; + /* Timer4 Ch.3 U phase reload */ + if ((VSSEL139 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.3 V phase reload */ + if ((VSSEL139 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer43ReloadV_IrqHandler(); + } + /* Timer4 Ch.3 W phase reload */ + if ((VSSEL139 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer43ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.140 share IRQ handler + ** + ******************************************************************************/ +void IRQ140_Handler(void) +{ + uint32_t VSSEL140 = M4_INTC->VSSEL140; + uint32_t u32Tmp1 = 0u; + uint32_t u32Tmp2 = 0u; + /* EMB1 */ + u32Tmp1 = M4_EMB1->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB1->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_06)) + { + Emb1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = M4_EMB2->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB2->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_07)) + { + Emb2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = M4_EMB3->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB3->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_08)) + { + Emb3_IrqHandler(); + } + /* EMB4*/ + u32Tmp1 = M4_EMB4->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB4->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_09)) + { + Emb4_IrqHandler(); + } + + /* I2S Ch.1 Transmit */ + if(1ul == bM4_I2S1_CTRL_TXIE) + { + if ((1ul == bM4_I2S1_SR_TXBA) && (VSSEL140 & BIT_MASK_16)) + { + I2s1Tx_IrqHandler(); + } + } + /* I2S Ch.1 Receive */ + if(1ul == bM4_I2S1_CTRL_RXIE) + { + if ((1ul == bM4_I2S1_SR_RXBA) && (VSSEL140 & BIT_MASK_17)) + { + I2s1Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if(1ul == bM4_I2S1_CTRL_EIE) + { + if ((M4_I2S1->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_18)) + { + I2s1Err_IrqHandler(); + } + } + /* I2S Ch.2 Transmit */ + if(1ul == bM4_I2S2_CTRL_TXIE) + { + if ((1ul == bM4_I2S2_SR_TXBA) && (VSSEL140 & BIT_MASK_19)) + { + I2s2Tx_IrqHandler(); + } + } + /* I2S Ch.2 Receive */ + if(1ul == bM4_I2S2_CTRL_RXIE) + { + if ((1ul == bM4_I2S2_SR_RXBA) && (VSSEL140 & BIT_MASK_20)) + { + I2s2Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if(1ul == bM4_I2S2_CTRL_EIE) + { + if ((M4_I2S2->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_21)) + { + I2s2Err_IrqHandler(); + } + } + /* I2S Ch.3 Transmit */ + if(1ul == bM4_I2S3_CTRL_TXIE) + { + if ((1ul == bM4_I2S3_SR_TXBA) && (VSSEL140 & BIT_MASK_22)) + { + I2s3Tx_IrqHandler(); + } + } + /* I2S Ch.3 Receive */ + if(1ul == bM4_I2S3_CTRL_RXIE) + { + if ((1ul == bM4_I2S3_SR_RXBA) && (VSSEL140 & BIT_MASK_23)) + { + I2s3Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if(1ul == bM4_I2S3_CTRL_EIE) + { + if ((M4_I2S3->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_24)) + { + I2s3Err_IrqHandler(); + } + } + /* I2S Ch.4 Transmit */ + if(1ul == bM4_I2S4_CTRL_TXIE) + { + if ((1ul == bM4_I2S4_SR_TXBA) && (VSSEL140 & BIT_MASK_25)) + { + I2s4Tx_IrqHandler(); + } + } + /* I2S Ch.4 Receive */ + if(1ul == bM4_I2S4_CTRL_RXIE) + { + if ((1ul == bM4_I2S4_SR_RXBA) && (VSSEL140 & BIT_MASK_26)) + { + I2s4Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if(1ul == bM4_I2S4_CTRL_EIE) + { + if ((M4_I2S4->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_27)) + { + I2s4Err_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.141 share IRQ handler + ** + ******************************************************************************/ +void IRQ141_Handler(void) +{ + uint32_t VSSEL141 = M4_INTC->VSSEL141; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* I2C Ch.1 Receive completed */ + if(1ul == bM4_I2C1_CR2_RFULLIE) + { + if ((1ul == bM4_I2C1_SR_RFULLF) && (VSSEL141 & BIT_MASK_04)) + { + I2c1RxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Transmit data empty */ + if(1ul == bM4_I2C1_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C1_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_05)) + { + I2c1TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Transmit completed */ + if(1ul == bM4_I2C1_CR2_TENDIE) + { + if ((1ul == bM4_I2C1_SR_TENDF) && (VSSEL141 & BIT_MASK_06)) + { + I2c1TxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = M4_I2C1->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C1->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_07)) + { + I2c1Err_IrqHandler(); + } + /* I2C Ch.2 Receive completed */ + if(1ul == bM4_I2C2_CR2_RFULLIE) + { + if ((1ul == bM4_I2C2_SR_RFULLF) && (VSSEL141 & BIT_MASK_08)) + { + I2c2RxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Transmit data empty */ + if(1ul == bM4_I2C2_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C2_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_09)) + { + I2c2TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Transmit completed */ + if(1ul == bM4_I2C2_CR2_TENDIE) + { + if ((1ul == bM4_I2C2_SR_TENDF) && (VSSEL141 & BIT_MASK_10)) + { + I2c2TxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = M4_I2C2->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C2->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_11)) + { + I2c2Err_IrqHandler(); + } + /* I2C Ch.3 Receive completed */ + if(1ul == bM4_I2C3_CR2_RFULLIE) + { + if ((1ul == bM4_I2C3_SR_RFULLF) && (VSSEL141 & BIT_MASK_12)) + { + I2c3RxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Transmit data empty */ + if(1ul == bM4_I2C3_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C3_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_13)) + { + I2c3TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Transmit completed */ + if(1ul == bM4_I2C3_CR2_TENDIE) + { + if ((1ul == bM4_I2C3_SR_TENDF) && (VSSEL141 & BIT_MASK_14)) + { + I2c3TxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = M4_I2C3->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C3->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_15)) + { + I2c3Err_IrqHandler(); + } + /* PVD Ch.1 detected */ + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG) + { + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG) && (VSSEL141 & BIT_MASK_17)) + { + Pvd1_IrqHandler(); + } + } + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG) + { + /* PVD Ch.2 detected */ + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG) && (VSSEL141 & BIT_MASK_18)) + { + Pvd2_IrqHandler(); + } + } + /* Freq. calculate error detected */ + if(1ul == bM4_FCM_RIER_ERRIE) + { + if((1ul == bM4_FCM_SR_ERRF) && (VSSEL141 & BIT_MASK_20)) + { + FcmErr_IrqHandler(); + } + } + /* Freq. calculate completed */ + if(1ul == bM4_FCM_RIER_MENDIE) + { + if((1ul == bM4_FCM_SR_MENDF) && (VSSEL141 & BIT_MASK_21)) + { + FcmEnd_IrqHandler(); + } + } + /* Freq. calculate overflow */ + if(1ul == bM4_FCM_RIER_OVFIE) + { + if((1ul == bM4_FCM_SR_OVF) && (VSSEL141 & BIT_MASK_22)) + { + FcmOV_IrqHandler(); + } + } + + /* WDT */ + if ((M4_WDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL141 & BIT_MASK_23)) + { + Wdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.142 share IRQ handler + ** + ******************************************************************************/ +void IRQ142_Handler(void) +{ + uint32_t u32VSSEL142 = M4_INTC->VSSEL142; + uint16_t u16Tmp = 0u; + /* ADC unit.1 seq. A */ + if (1ul == bM4_ADC1_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_00)) + { + ADC1A_IrqHandler(); + } + } + /* ADC unit.1 seq. B */ + if (1ul == bM4_ADC1_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_01)) + { + ADC1B_IrqHandler(); + } + } + /* ADC unit.1 seq. A */ + u16Tmp = M4_ADC1->AWDSR0; + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_02)) + { + ADC1ChCmp_IrqHandler(); + } + } + /* ADC unit.1 seq. cmp */ + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_03)) + { + ADC1SeqCmp_IrqHandler(); + } + } + + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_04)) + { + ADC2A_IrqHandler(); + } + } + /* ADC unit.2 seq. B */ + if (1ul == bM4_ADC2_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_05)) + { + ADC2B_IrqHandler(); + } + } + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_06)) + { + ADC2ChCmp_IrqHandler(); + } + } + /* ADC unit.2 seq. cmp */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_07)) + { + ADC2SeqCmp_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.143 share IRQ handler + ** + ******************************************************************************/ +void IRQ143_Handler(void) +{ + uint8_t RTIF = 0u; + uint8_t RTIE = 0u; + uint8_t ERRINT = 0u; + uint8_t TTCFG = 0u; + uint16_t NORINTST = 0u; + uint16_t NORINTSGEN = 0u; + uint16_t ERRINTST = 0u; + uint16_t ERRINTSGEN = 0u; + + /* SDIO Ch.1 */ + if (1ul == bM4_INTC_VSSEL143_VSEL2) + { + NORINTST = M4_SDIOC1->NORINTST; + NORINTSGEN = M4_SDIOC1->NORINTSGEN; + ERRINTST = M4_SDIOC1->ERRINTST; + ERRINTSGEN = M4_SDIOC1->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio1_IrqHandler(); + } + } + + /* SDIO Ch.2 */ + if (1ul == bM4_INTC_VSSEL143_VSEL5) + { + NORINTST = M4_SDIOC2->NORINTST; + NORINTSGEN = M4_SDIOC2->NORINTSGEN; + ERRINTST = M4_SDIOC2->ERRINTST; + ERRINTSGEN = M4_SDIOC2->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio2_IrqHandler(); + } + } + + /* CAN */ + if (1ul == bM4_INTC_VSSEL143_VSEL6) + { + RTIF = M4_CAN->RTIF; + RTIE = M4_CAN->RTIE; + ERRINT = M4_CAN->ERRINT; + TTCFG = M4_CAN->TTCFG; + if ( (TTCFG & BIT_MASK_05) || \ + (RTIF & BIT_MASK_00) || \ + (RTIF & RTIE & 0xFEu) || \ + ((ERRINT & BIT_MASK_00) && (ERRINT & BIT_MASK_01)) || \ + ((ERRINT & BIT_MASK_02) && (ERRINT & BIT_MASK_03)) || \ + ((ERRINT & BIT_MASK_04) && (ERRINT & BIT_MASK_05)) || \ + ((TTCFG & BIT_MASK_03) && (TTCFG & BIT_MASK_04)) || \ + ((TTCFG & BIT_MASK_06) && (TTCFG & BIT_MASK_07))) + { + Can_IrqHandler(); + } + } +} + +#endif + +//@} // InterruptGroup + +#endif /* DDL_INTERRUPTS_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c new file mode 100644 index 000000000..43f2fab5a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c @@ -0,0 +1,207 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.c + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_keyscan.h" +#include "hc32f460_utility.h" + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup KeyscanGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for Hiz cycle */ +#define IS_VALID_HIZ_CLCYE(x) \ +( ((x) == Hiz4) || \ + ((x) == Hiz8) || \ + ((x) == Hiz16) || \ + ((x) == Hiz32) || \ + ((x) == Hiz64) || \ + ((x) == Hiz256) || \ + ((x) == Hiz512) || \ + ((x) == Hiz1K)) + +/*! Parameter validity check for Low cycle */ +#define IS_VALID_LOW_CLCYE(x) \ +( ((x) == Low8) || \ + ((x) == Low16) || \ + ((x) == Low32) || \ + ((x) == Low64) || \ + ((x) == Low128) || \ + ((x) == Low256) || \ + ((x) == Low512) || \ + ((x) == Low1K) || \ + ((x) == Low2K) || \ + ((x) == Low4K) || \ + ((x) == Low8K) || \ + ((x) == Low16K) || \ + ((x) == Low32K) || \ + ((x) == Low64K) || \ + ((x) == Low128K) || \ + ((x) == Low256K) || \ + ((x) == Low512K) || \ + ((x) == Low1M) || \ + ((x) == Low2M) || \ + ((x) == Low4M) || \ + ((x) == Low8M) || \ + ((x) == Low16M)) + +/*! Parameter validity check for scan clock */ +#define IS_VALID_SCAN_CLK(x) \ +( ((x) == KeyscanHclk) || \ + ((x) == KeyscanLrc) || \ + ((x) == KeyscanXtal32)) + +/*! Parameter validity check for keyout selection */ +#define IS_VALID_KEY_OUT(x) \ +( ((x) == Keyout0To1) || \ + ((x) == Keyout0To2) || \ + ((x) == Keyout0To3) || \ + ((x) == Keyout0To4) || \ + ((x) == Keyout0To5) || \ + ((x) == Keyout0To6) || \ + ((x) == Keyout0To7)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief KEYSCAN initialization + ** + ** \param [in] pstcKeyscanConfig KEYSCAN configure structure + ** + ** \retval Ok KEYSCAN initialized + ** ErrorInvalidMode Uninitialized, cannot configure it properly + ** + ******************************************************************************/ +en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_HIZ_CLCYE(pstcKeyscanConfig->enHizCycle)); + DDL_ASSERT(IS_VALID_LOW_CLCYE(pstcKeyscanConfig->enLowCycle)); + DDL_ASSERT(IS_VALID_SCAN_CLK(pstcKeyscanConfig->enKeyscanClk)); + DDL_ASSERT(IS_VALID_KEY_OUT(pstcKeyscanConfig->enKeyoutSel)); + + /* cannot configure keyscan control register when running */ + if (Set == M4_KEYSCAN->SER_f.SEN) + { + enRet = ErrorInvalidMode; + } + else + { + M4_KEYSCAN->SCR_f.T_HIZ = pstcKeyscanConfig->enHizCycle; + M4_KEYSCAN->SCR_f.T_LLEVEL = pstcKeyscanConfig->enLowCycle; + M4_KEYSCAN->SCR_f.CKSEL = pstcKeyscanConfig->enKeyscanClk; + M4_KEYSCAN->SCR_f.KEYOUTSEL = pstcKeyscanConfig->enKeyoutSel; + M4_KEYSCAN->SCR_f.KEYINSEL = pstcKeyscanConfig->u16KeyinSel; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief KEYSCAN de-initialization + ** + ** \param None + ** + ** \retval Ok KEYSCAN de-initialized + ** + ******************************************************************************/ +en_result_t KEYSCAN_DeInit(void) +{ + M4_KEYSCAN->SER = 0ul; + M4_KEYSCAN->SCR = 0ul; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Start keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function started + ** + ******************************************************************************/ +en_result_t KEYSCAN_Start(void) +{ + M4_KEYSCAN->SER_f.SEN = Set; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Stop keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function stopped + ** + ******************************************************************************/ +en_result_t KEYSCAN_Stop(void) +{ + M4_KEYSCAN->SER_f.SEN = Reset; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Key column index + ** + ** \param None + ** + ** \retval uint8_t Index of KEYOUT + ** + ******************************************************************************/ +uint8_t KEYSCAN_GetColIdx(void) +{ + return (uint8_t)(M4_KEYSCAN->SSR_f.INDEX); +} + +//@} // KeyscanGroup + +#endif /* DDL_KEYSCAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c new file mode 100644 index 000000000..d0b394072 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c @@ -0,0 +1,1057 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.c + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_mpu.h" +#include "hc32f460_utility.h" + +#if (DDL_MPU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup MpuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for MPU region number. */ +#define IS_VALID_MPU_REGION_NUM(x) \ +( (MpuRegionNum0 == (x)) || \ + (MpuRegionNum1 == (x)) || \ + (MpuRegionNum2 == (x)) || \ + (MpuRegionNum3 == (x)) || \ + (MpuRegionNum4 == (x)) || \ + (MpuRegionNum5 == (x)) || \ + (MpuRegionNum6 == (x)) || \ + (MpuRegionNum7 == (x)) || \ + (MpuRegionNum8 == (x)) || \ + (MpuRegionNum9 == (x)) || \ + (MpuRegionNum10 == (x)) || \ + (MpuRegionNum11 == (x)) || \ + (MpuRegionNum12 == (x)) || \ + (MpuRegionNum13 == (x)) || \ + (MpuRegionNum14 == (x)) || \ + (MpuRegionNum15 == (x))) + +/*!< Parameter valid check for MPU region size. */ +#define IS_VALID_MPU_REGION_SIZE(x) \ +( (MpuRegionSize32Byte == (x)) || \ + (MpuRegionSize64Byte == (x)) || \ + (MpuRegionSize128Byte == (x)) || \ + (MpuRegionSize256Byte == (x)) || \ + (MpuRegionSize512Byte == (x)) || \ + (MpuRegionSize1KByte == (x)) || \ + (MpuRegionSize2KByte == (x)) || \ + (MpuRegionSize4KByte == (x)) || \ + (MpuRegionSize8KByte == (x)) || \ + (MpuRegionSize16KByte == (x)) || \ + (MpuRegionSize32KByte == (x)) || \ + (MpuRegionSize64KByte == (x)) || \ + (MpuRegionSize128KByte == (x)) || \ + (MpuRegionSize256KByte == (x)) || \ + (MpuRegionSize512KByte == (x)) || \ + (MpuRegionSize1MByte == (x)) || \ + (MpuRegionSize2MByte == (x)) || \ + (MpuRegionSize4MByte == (x)) || \ + (MpuRegionSize8MByte == (x)) || \ + (MpuRegionSize16MByte == (x)) || \ + (MpuRegionSize32MByte == (x)) || \ + (MpuRegionSize64MByte == (x)) || \ + (MpuRegionSize128MByte == (x)) || \ + (MpuRegionSize256MByte == (x)) || \ + (MpuRegionSize512MByte == (x)) || \ + (MpuRegionSize1GByte == (x)) || \ + (MpuRegionSize2GByte == (x)) || \ + (MpuRegionSize4GByte == (x))) + +/*!< Parameter valid check for MPU region type. */ +#define IS_VALID_MPU_REGION_TYPE(x) \ +( (SMPU1Region == (x)) || \ + (SMPU2Region == (x)) || \ + (FMPURegion == (x))) + +/*!< Parameter valid check for MPU action. */ +#define IS_VALID_MPU_ACTION(x) \ +( (MpuTrigNmi == (x)) || \ + (MpuTrigReset == (x)) || \ + (MpuNoneAction == (x)) || \ + (MpuTrigBusError == (x))) + +/******************************************************************************/ +/* MPU */ +/******************************************************************************/ +/*!< Get the RGD register address of the specified MPU region */ +#define MPU_RGDx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGD0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< Get the RGCR register address of the specified MPU region */ +#define MPU_RGCRx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGCR0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< MPU RGD register: RGADDR position */ +#define MPU_RGD_RGADDR_Pos (5u) /*!< MPU_RGD: RGADDR Position */ + +/*!< MPU write protection key */ +#define MPU_WRITE_PROT_KEY (0x96A4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Configure MPU protect region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] pstcInitCfg Pointer to MPU protection region configuration structure + ** \arg the structure detail refer @ref stc_mpu_prot_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32WriteProt = M4_MPU->WP; + stc_mpu_rgd0_field_t *RGD_f = NULL; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(pstcInitCfg->enRegionSize)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU1Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU2Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcFMPUPermission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enReadEnable)); + + /* Check base address and region size */ + if (!(pstcInitCfg->u32RegionBaseAddress & (~ (0xFFFFFFFFUL << ((uint32_t)pstcInitCfg->enRegionSize + 1UL))))) + { + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Get RGD && RGCR register address */ + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + /* Disable region protection function */ + RGCR_f->FRG0E = (uint32_t)0ul; + RGCR_f->S1RG0E = (uint32_t)0ul; + RGCR_f->S2RG0E = (uint32_t)0ul; + + /* Set region size */ + RGD_f->MPURG0SIZE = (uint32_t)(pstcInitCfg->enRegionSize); + + /* Set region base address */ + RGD_f->MPURG0ADDR = (pstcInitCfg->u32RegionBaseAddress >> MPU_RGD_RGADDR_Pos); + + /* Set region FMPU */ + RGCR_f->FRG0RP = (pstcInitCfg->stcFMPUPermission.enReadEnable) ? 0ul : 1ul; + RGCR_f->FRG0WP = (pstcInitCfg->stcFMPUPermission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->FRG0E = (uint32_t)(pstcInitCfg->stcFMPUPermission.enRegionEnable); + M4_MPU->CR_f.FMPUACT = (uint32_t)(pstcInitCfg->stcFMPUPermission.enAction); + + /* Set region SMPU1 */ + RGCR_f->S1RG0RP = (pstcInitCfg->stcSMPU1Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S1RG0WP = (pstcInitCfg->stcSMPU1Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S1RG0E = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enRegionEnable); + M4_MPU->CR_f.SMPU1ACT = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enAction); + + /* Set region SMPU2 */ + RGCR_f->S2RG0RP = (pstcInitCfg->stcSMPU2Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S2RG0WP = (pstcInitCfg->stcSMPU2Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S2RG0E = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enRegionEnable); + M4_MPU->CR_f.SMPU2ACT = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enAction); + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure MPU background region. + ** + ** \param [in] pstcInitCfg Pointer to MPU background region configuration structure + ** \arg the structure detail refer @ref stc_mpu_bkgd_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg) +{ + uint32_t u32WriteProt = M4_MPU->WP; + en_result_t enRet = ErrorInvalidParameter; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enReadEnable)); + + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Set SMPU1 */ + M4_MPU->CR_f.SMPU1BWP = (pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU1BRP = (pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set SMPU2 */ + M4_MPU->CR_f.SMPU2BWP = (pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU2BRP = (pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set FMPU */ + M4_MPU->CR_f.FMPUBWP = (pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.FMPUBRP = (pstcInitCfg->stcFMPUBkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enRegionSize MPU region size + ** \arg This parameter can be a value of @ref en_mpu_region_size_t + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(enRegionSize)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURG0SIZE = (uint32_t)enRegionSize; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** + ** \retval MPU size of the specified region. + ** + ******************************************************************************/ +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + + return (en_mpu_region_size_t)(RGD_f->MPURG0SIZE); +} + +/** + ******************************************************************************* + ** \brief Set MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] u32RegionBaseAddr the specified base address + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURG0ADDR = (u32RegionBaseAddr >> MPU_RGD_RGADDR_Pos); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t +s ** + ** \retval MPU base address of the specified region. + ** + ******************************************************************************/ +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + + return (RGD_f->MPURG0ADDR << MPU_RGD_RGADDR_Pos); +} + +/** + ******************************************************************************* + ** \brief Set the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enActionSel MPU action + ** \arg MpuNoneAction MPU don't action. + ** \arg MpuTrigBusError MPU trigger bus error + ** \arg MpuTrigNmi MPU trigger bus NMI interrupt + ** \arg MpuTrigReset MPU trigger reset + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enActionSel is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_ACTION(enActionSel)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1ACT = (uint32_t)enActionSel; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2ACT = (uint32_t)enActionSel; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUACT = (uint32_t)enActionSel; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval MpuNoneAction MPU don't action. + ** \retval MpuTrigBusError MPU trigger bus error + ** \retval MpuTrigNmi MPU trigger bus NMI interrupt + ** \retval MpuTrigReset MPU trigger reset + ** + ******************************************************************************/ +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32ActionSel = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32ActionSel = M4_MPU->CR_f.SMPU1ACT; + break; + case SMPU2Region: + u32ActionSel = M4_MPU->CR_f.SMPU2ACT; + break; + case FMPURegion: + u32ActionSel = M4_MPU->CR_f.FMPUACT; + break; + default: + break; + } + + return (en_mpu_action_sel_t)(u32ActionSel); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region function + ** \arg Disable Disable the specified MPU region function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0E = (uint32_t)enState; + break; + case SMPU2Region: + RGCR_f->S2RG0E = (uint32_t)enState; + break; + case FMPURegion: + RGCR_f->FRG0E = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified type region function of MPU + ** \arg Disable Disable the specified type region function of MPU + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1E = (uint32_t)enState; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2E = (uint32_t)enState; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUE = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU status + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enMpuRegionType is invalid. + ** + ******************************************************************************/ +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32Flag = 0ul; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32Flag = M4_MPU->SR_f.SMPU1EAF; + break; + case SMPU2Region: + u32Flag = M4_MPU->SR_f.SMPU2EAF; + break; + case FMPURegion: + u32Flag = M4_MPU->SR_f.FMPUEAF; + break; + default: + break; + } + + return (en_flag_status_t)(u32Flag); +} + +/** + ******************************************************************************* + ** \brief Clear MPU status. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->ECLR_f.SMPU1ECLR = 1u; + break; + case SMPU2Region: + M4_MPU->ECLR_f.SMPU2ECLR = 1u; + break; + case FMPURegion: + M4_MPU->ECLR_f.FMPUECLR = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case SMPU2Region: + RGCR_f->S2RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case FMPURegion: + RGCR_f->FRG0RP = (Enable == enState) ? 0ul : 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0RP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0RP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0RP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + RGCR_f->S2RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + RGCR_f->FRG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0WP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0WP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0WP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBRP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BRP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BRP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBRP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBWP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BWP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BWP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBWP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enState MPU write protection state + ** \arg Enable Enable the write protection function + ** \arg Disable Disable the write protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_WriteProtCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_MPU->WP = (MPU_WRITE_PROT_KEY | ((Enable == enState) ? 0ul : 1ul)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable the specified IP Write/Read protection. + ** + ** \param [in] u32ProtMode Ip protection mode + ** \arg AesReadProt AES read protection + ** \arg AesWriteProt AES write protection + ** \arg HashReadProt HASH read protection + ** \arg HashWriteProt HASH write protection + ** \arg TrngReadProt TRNG read protection + ** \arg TrngWriteProt TRNG write protection + ** \arg CrcReadProt CRC read protection + ** \arg CrcWriteProt CRC write protection + ** \arg FmcReadProt FMC read protection + ** \arg FmcWriteProt FMC write protection + ** \arg WdtReadProt WDT read protection + ** \arg WdtWriteProt WDT write protection + ** \arg SwdtReadProt WDT read protection + ** \arg SwdtWriteProt WDT write protection + ** \arg BksramReadProt BKSRAM read protection + ** \arg BksramWriteProt BKSRAM write protection + ** \arg RtcReadProt RTC read protection + ** \arg RtcWriteProt RTC write protection + ** \arg DmpuReadProt DMPU read protection + ** \arg DmpuWriteProt DMPU write protection + ** \arg SramcReadProt SRAMC read protection + ** \arg SramcWriteProt SRAMC write protection + ** \arg IntcReadProt INTC read protection + ** \arg IntcWriteProt INTC write protection + ** \arg SyscReadProt SYSC read protection + ** \arg SyscWriteProt SYSC write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg BusErrProt BUSERR write protection + ** \param [in] enState MPU IP protection state + ** \arg Enable Enable the IP protection function + ** \arg Disable Disable the IP protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if(Enable == enState) + { + M4_SYSREG->MPU_IPPR |= u32ProtMode; + } + else + { + M4_SYSREG->MPU_IPPR &= (~u32ProtMode); + } + + return Ok; +} + +//@} // MpuGroup + +#endif /* DDL_MPU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c new file mode 100644 index 000000000..74ddaba77 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c @@ -0,0 +1,386 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.c + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_ots.h" +#include "hc32f460_utility.h" + +#if (DDL_OTS_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup OtsGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for OTS auto off configuration value. */ +#define IS_OTS_AUTO_OFF(EN) \ +( ((EN) == OtsAutoOff_Disable) || \ + ((EN) == OtsAutoOff_Enable)) + +/*! Parameter validity check for OTS interrupt enable/disable. */ +#define IS_OTS_IE(IE) \ +( ((IE) == OtsInt_Disable) || \ + ((IE) == OtsInt_Enable)) + +/*! Parameter validity check for OTS clock selection configuration value. */ +#define IS_OTS_CLK_SEL(CLK) \ +( ((CLK) == OtsClkSel_Xtal) || \ + ((CLK) == OtsClkSel_Hrc)) + +/*! Parameter validity check for OTS trigger source event . */ +#define IS_OTS_TRIG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter validity check for OTS common trigger. */ +#define IS_OTS_COM_TRIGGER(x) \ +( ((x) == OtsComTrigger_1) || \ + ((x) == OtsComTrigger_2) || \ + ((x) == OtsComTrigger_1_2)) + +#define EXPERIMENT_COUNT ((uint8_t)10) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static float32_t m_f32SlopeK = 0.0f; +static float32_t m_f32OffsetM = 0.0f; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief Initializes the OTS. + ** + ** \param [in] pstcInit See @ref stc_ots_init_t for details. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Init(const stc_ots_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + DDL_ASSERT(IS_OTS_AUTO_OFF(pstcInit->enAutoOff)); + DDL_ASSERT(IS_OTS_CLK_SEL(pstcInit->enClkSel)); + + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + /* Disable OTS interrupt default. */ + bM4_OTS_CTL_OTSIE = OtsInt_Disable; + + bM4_OTS_CTL_TSSTP = pstcInit->enAutoOff; + bM4_OTS_CTL_OTSCK = pstcInit->enClkSel; + m_f32SlopeK = pstcInit->f32SlopeK; + m_f32OffsetM = pstcInit->f32OffsetM; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_DeInit(void) +{ + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + + /* Set the value of all registers to the reset value. */ + M4_OTS->CTL = 0u; + M4_OTS->DR1 = 0u; + M4_OTS->DR2 = 0u; + M4_OTS->ECR = 0u; +} + +/** + ******************************************************************************* + ** \brief Get temperature via normal mode. + ** + ** \param [out] pf32Temp The address to store the temperature value. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout OTS works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pf32Temp != NULL) + { + enRet = ErrorTimeout; + + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + *pf32Temp = OTS_CalculateTemp(); + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable OTS interrupt. + ** + ** \param [in] enState Enable or disable OTS interrupt. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_IntCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + bM4_OTS_CTL_OTSIE = (uint32_t)enState; +} + +/** + ******************************************************************************* + ** \brief Set OTS AOS trigger source. + ** + ** \param [in] enEvent See @ref en_event_src_t for details. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_SetTriggerSrc(en_event_src_t enEvent) +{ + uint32_t u32OtrTrg = M4_AOS->OTS_TRG; + + DDL_ASSERT(IS_OTS_TRIG_SRC_EVENT(enEvent) && (EVT_OTS != enEvent)); + + u32OtrTrg &= ~0x1FFul; + u32OtrTrg |= enEvent; + + M4_AOS->OTS_TRG = u32OtrTrg; +} + +/** + ******************************************************************************* + ** \brief Enable or disable OTS common trigger. + ** + ** \param [in] enComTrigger OTS common trigger selection. See @ref en_ots_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + + DDL_ASSERT(IS_OTS_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u32ComTrig <<= 30u; + + if (enState == Enable) + { + M4_AOS->OTS_TRG |= u32ComTrig; + } + else + { + M4_AOS->OTS_TRG &= ~u32ComTrig; + } +} + +/** +******************************************************************************* +** \brief OTS scaling experiment. If you want to get a more accurate temperature value, +** you need to do a calibration experiment. +** +** \param [out] pu16Dr1 Address to store OTS data register 1. +** +** \param [out] pu16Dr2 Address to store OTS data register 2. +** +** \param [out] pu16Ecr Address to store OTS error compensation register. +** +** \param [out] pf32A Address to store parameter A(for calibration experiments). +** +** \param [in] u32Timeout Timeout value. +** +** \retval Ok No error occurred. +** \retval ErrorTimeout OTS works timeout. +** \retval ErrorInvalidParameter Parameter error. +******************************************************************************/ +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) + { + enRet = ErrorTimeout; + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + + if (enRet == Ok) + { + *pu16Dr1 = M4_OTS->DR1; + *pu16Dr2 = M4_OTS->DR2; + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Hrc) + { + *pu16Ecr = M4_OTS->ECR; + f32Ecr = (float32_t)(*pu16Ecr); + } + else + { + *pu16Ecr = 1U; + f32Ecr = 1.0f; + } + + if ((*pu16Dr1 != 0U) && (*pu16Dr2 != 0U) && (*pu16Ecr != 0U)) + { + *pf32A = ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr; + } + } + } + + return enRet; +} + + +/** +******************************************************************************* +** \brief Calculate the value of temperature. +** +** \retval A float32_t type value of temperature value. +******************************************************************************/ +float OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0f; + uint16_t u16Dr1 = M4_OTS->DR1; + uint16_t u16Dr2 = M4_OTS->DR2; + uint16_t u16Ecr = M4_OTS->ECR; + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Xtal) + { + f32Ecr = 1.0f; + } + + if ((u16Dr1 != 0U) && (u16Dr2 != 0U) && (u16Ecr != 0U)) + { + f32Ret = m_f32SlopeK * ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +//@} // OtsGroup + +#endif /* DDL_OTS_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c new file mode 100644 index 000000000..9d0bb3574 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c @@ -0,0 +1,2025 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.c + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_pwc.h" +#include "hc32f460_utility.h" + +#if (DDL_PWC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup PwcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa503u) +#define DISABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~3u)))) + +#define ENABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + +#define ENABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa508u) +#define DISABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~8u)))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP_EVENT(evt) ((0x00u) != ((evt) & (0xFF))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP2_EVENT(evt) ((0x00u) != ((evt) & (0xB7))) + +#define IS_PWC_WKUP_EDGE_EVENT(evt) ((0x00u) != ((evt) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP0_FLAG(flag) ((0x00u) != ((flag) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP1_FLAG(flag) ((0x07u) != ((flag) & (0xB8))) + +/*! Parameter validity check for power down mode. */ +#define IS_PWC_PWR_DOWN_MODE(md) \ +( ((md) == PowerDownMd1) || \ + ((md) == PowerDownMd2) || \ + ((md) == PowerDownMd3) || \ + ((md) == PowerDownMd4)) + +/*! Parameter validity check for power down wake_up time control. */ +#define IS_PWC_PWR_DOWN_WKUP_TIM(x) \ +( ((x) == Vcap01) || \ + ((x) == Vcap0047)) + +/*! Parameter validity check for IO retain state while power down. */ +#define IS_PWC_PWR_DWON_IO_STATE(x) \ +( ((x) == IoPwrDownRetain) || \ + ((x) == IoPwrRstRetain) || \ + ((x) == IoHighImp)) + +/*! Parameter validity check for driver ability while enter stop mode. */ +#define IS_PWC_STP_DRIVER_ABILITY(x) \ +( ((x) == StopHighspeed) || \ + ((x) == StopUlowspeed)) + +/*! Parameter validity check for driver ability. */ +#define IS_PWC_DRIVER_ABILITY(x) \ +( ((x) == Ulowspeed) || \ + ((x) == HighSpeed)) + +/*! Parameter validity check for dynamic voltage. */ +#define IS_PWC_DYNAMIC_VOLTAGE(val) \ +( ((val) == RunUHighspeed) || \ + ((val) == RunUlowspeed) || \ + ((val) == RunHighspeed)) + +/*! Parameter validity check for wake_up edge. */ +#define IS_PWC_EDGE_SEL(edg) \ +( ((edg) == EdgeFalling) || \ + ((edg) == EdgeRising)) + +/*! Parameter validity check for peripheral in fcg0. */ +#define IS_PWC_FCG0_PERIPH(per) \ +( (((per) & (0x700C3AEEu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg1. */ +#define IS_PWC_FCG1_PERIPH(per) \ +( (((per) & (0xF0F00286u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg2. */ +#define IS_PWC_FCG2_PERIPH(per) \ +( (((per) & (0xFFF87800u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg3. */ +#define IS_PWC_FCG3_PERIPH(per) \ +( (((per) & (0xFFFFEEECu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for clock value while stop mode mode. */ +#define IS_PWC_STOP_MODE_CLK(clk) \ +( ((clk) == ClkFix) || \ + ((clk) == ClkMrc)) + +/*! Parameter validity check for flash mode while stop mode mode. */ +#define IS_PWC_STOP_MODE_FLASH(x) \ +( ((x) == Wait) || \ + ((x) == NotWait)) + +/*! Parameter validity check for wake_up timer over flag. */ +#define IS_PWC_WKTMOVER_FLAG(flag) \ +( ((flag) == UnEqual) || \ + ((flag) == Equal)) + +/*! Parameter validity check for ram operate mode. */ +#define IS_PWC_RAM_OP_MD(x) \ +( ((x) == HighSpeedMd) || \ + ((x) == UlowSpeedMd)) + +/*! Parameter validity check for wake_up timer clock. */ +#define IS_PWC_WKTM_CLK(clk) \ +( ((clk) == Wk64hz) || \ + ((clk) == WkXtal32) || \ + ((clk) == WkLrc)) + + +/*! Parameter validity check for handle of pvd. */ +#define IS_PWC_PVD_MD(x) \ +( ((x) == PvdInt) || \ + ((x) == PvdReset)) + + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD_FILTER_CLK(clk) \ +( ((clk) == PvdLrc025) || \ + ((clk) == PvdLrc05) || \ + ((clk) == PvdLrc1) || \ + ((clk) == PvdLrc2)) + +/*! Parameter validity check for pvd2 level. */ +#define IS_PWC_PVD2_LEVEL(lvl) \ +( ((lvl) == Pvd2Level0) || \ + ((lvl) == Pvd2Level1) || \ + ((lvl) == Pvd2Level2) || \ + ((lvl) == Pvd2Level3) || \ + ((lvl) == Pvd2Level4) || \ + ((lvl) == Pvd2Level5) || \ + ((lvl) == Pvd2Level6) || \ + ((lvl) == Pvd2Level7)) + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD1_LEVEL(lvl) \ +( ((lvl) == Pvd1Level0) || \ + ((lvl) == Pvd1Level1) || \ + ((lvl) == Pvd1Level2) || \ + ((lvl) == Pvd1Level3) || \ + ((lvl) == Pvd1Level4) || \ + ((lvl) == Pvd1Level5) || \ + ((lvl) == Pvd1Level6) || \ + ((lvl) == Pvd1Level7)) + +/*! Parameter validity check for pvd interrupt. */ +#define IS_PWC_PVD_INT_SEL(x) \ +( ((x) == NonMskInt) || \ + ((x) == MskInt)) + +/*! Parameter validity check for valid wakeup source from stop mode. */ +#define IS_VALID_WKUP_SRC(x) \ +( ((x) == INT_USART1_WUPI) || \ + ((x) == INT_TMR01_GCMA) || \ + ((x) == INT_RTC_ALM) || \ + ((x) == INT_RTC_PRD) || \ + ((x) == INT_WKTM_PRD) || \ + ((x) == INT_ACMP1) || \ + ((x) == INT_PVD_PVD1) || \ + ((x) == INT_PVD_PVD2) || \ + ((x) == INT_SWDT_REFUDF) || \ + ((x) == INT_PORT_EIRQ0) || \ + ((x) == INT_PORT_EIRQ1) || \ + ((x) == INT_PORT_EIRQ2) || \ + ((x) == INT_PORT_EIRQ3) || \ + ((x) == INT_PORT_EIRQ4) || \ + ((x) == INT_PORT_EIRQ5) || \ + ((x) == INT_PORT_EIRQ6) || \ + ((x) == INT_PORT_EIRQ7) || \ + ((x) == INT_PORT_EIRQ8) || \ + ((x) == INT_PORT_EIRQ9) || \ + ((x) == INT_PORT_EIRQ10) || \ + ((x) == INT_PORT_EIRQ11) || \ + ((x) == INT_PORT_EIRQ12) || \ + ((x) == INT_PORT_EIRQ13) || \ + ((x) == INT_PORT_EIRQ14) || \ + ((x) == INT_PORT_EIRQ15)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t NVIC_ISER_BAK[5]; +uint8_t u8HrcState = 0u; +uint8_t u8MrcState = 0u; +uint8_t u8WkupIntCnt = 0u; +uint8_t u8StopFlag = 0u; +uint8_t u8SysClkSrc = 1u; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ** \param [in] pstcPwrMdCfg The power mode configuration. + ** \arg enPwrDownMd The power down mode. + ** \arg enRLdo Enable or disable RLDO. + ** \arg enRetSram Enable or disable RetSram. + ** \arg enIoRetain The IO state while power down. + ** \arg enPwrDWkupTm The wake_up timer while power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg) +{ + DDL_ASSERT(IS_PWC_PWR_DOWN_MODE(pstcPwrMdCfg->enPwrDownMd )); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRLdo)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRetSram)); + DDL_ASSERT(IS_PWC_PWR_DWON_IO_STATE(pstcPwrMdCfg->enIoRetain)); + DDL_ASSERT(IS_PWC_PWR_DOWN_WKUP_TIM(pstcPwrMdCfg->enPwrDWkupTm)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC0 = (pstcPwrMdCfg->enPwrDownMd | + (uint8_t)(((Enable == pstcPwrMdCfg->enRLdo) ? 0u : 1u) << 2u) | + (uint8_t)(((Enable == pstcPwrMdCfg->enRetSram) ? 0u : 1u) << 3u) | + (pstcPwrMdCfg->enIoRetain << 4u)); + + M4_SYSREG->PWR_PWRC3 = (pstcPwrMdCfg->enPwrDWkupTm | (0x03)); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enter power down mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be put ram + ** + ******************************************************************************/ +__RAM_FUNC void PWC_EnterPowerDownMd(void) +{ + ENABLE_PVD_REG_WRITE(); + + /* Reset PVD1IRS & PVD2IRS */ + M4_SYSREG->PWR_PVDCR1 &= 0xddu; + + DISABLE_PVD_REG_WRITE(); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + + __disable_irq(); + M4_SYSREG->PWR_PWRC0_f.PWDN = 1u; + for(uint8_t i = 0u; i < 10u; i++) + { + __NOP(); + } + __enable_irq(); + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN0_WKUP00 Wake_up 0_0 event + ** \arg PWC_PDWKEN0_WKUP01 Wake_up 0_1 event + ** \arg PWC_PDWKEN0_WKUP02 Wake_up 0_2 event + ** \arg PWC_PDWKEN0_WKUP03 Wake_up 0_3 event + ** \arg PWC_PDWKEN0_WKUP10 Wake_up 1_0 event + ** \arg PWC_PDWKEN0_WKUP11 Wake_up 1_1 event + ** \arg PWC_PDWKEN0_WKUP12 Wake_up 1_2 event + ** \arg PWC_PDWKEN0_WKUP13 Wake_up 1_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup0Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE0 |= (uint8_t)u32Wkup0Event; + } + else + { + M4_SYSREG->PWR_PDWKE0 &= (uint8_t)(~u32Wkup0Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup1Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN1_WKUP20 Wake_up 2_0 event + ** \arg PWC_PDWKEN1_WKUP21 Wake_up 2_1 event + ** \arg PWC_PDWKEN1_WKUP22 Wake_up 2_2 event + ** \arg PWC_PDWKEN1_WKUP23 Wake_up 2_3 event + ** \arg PWC_PDWKEN1_WKUP30 Wake_up 3_0 event + ** \arg PWC_PDWKEN1_WKUP31 Wake_up 3_1 event + ** \arg PWC_PDWKEN1_WKUP32 Wake_up 3_2 event + ** \arg PWC_PDWKEN1_WKUP33 Wake_up 3_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup1Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE1 |= (uint8_t)u32Wkup1Event; + } + else + { + M4_SYSREG->PWR_PDWKE1 &= (uint8_t)(~u32Wkup1Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup2Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN2_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKEN2_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKEN2_NMI Wake_up NMI event + ** \arg PWC_PDWKEN2_RTCPRD Wake_up RTCPRD event + ** \arg PWC_PDWKEN2_RTCAL Wake_up RTCAL event + ** \arg PWC_PDWKEN2_WKTM Wake_up WKTM event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP2_EVENT(u32Wkup2Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE2 |= (uint8_t)u32Wkup2Event; + } + else + { + M4_SYSREG->PWR_PDWKE2 &= (uint8_t)(~u32Wkup2Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configure the power down wake up event edge. + ** + ** \param [in] u8WkupEvent The wake_up event in PDWKEN0. + ** \arg PWC_PDWKUP_EDGE_WKP0 Wake_up WKP0 event + ** \arg PWC_PDWKUP_EDGE_WKP1 Wake_up WKP1 event + ** \arg PWC_PDWKUP_EDGE_WKP2 Wake_up WKP2 event + ** \arg PWC_PDWKUP_EDGE_WKP3 Wake_up WKP3 event + ** \arg PWC_PDWKUP_EDGE_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKUP_EDGE_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKUP_EDGE_NMI Wake_up NMI event + ** + ** \param [in] enEdge The wake_up event edge select. + ** \arg EdgeRising Wake_up event edge rising. + ** \arg EdgeFalling Wake_up event edge falling. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge) +{ + DDL_ASSERT(IS_PWC_WKUP_EDGE_EVENT(u8WkupEvent)); + DDL_ASSERT(IS_PWC_EDGE_SEL(enEdge)); + + ENABLE_PWR_REG_WRITE(); + + if(EdgeRising == enEdge) + { + M4_SYSREG->PWR_PDWKES |= (uint8_t)u8WkupEvent; + } + else + { + M4_SYSREG->PWR_PDWKES &= (uint8_t)(~u8WkupEvent); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF0 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF1 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF0 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF1 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable power monitor . + ** + ** \param [in] enNewState The power monitor state. + ** \arg Enable Enable power monitor. + ** \arg Disable Disable power monitor. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PwrMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWCMR_f.ADBUFE = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG0 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg0Periph The peripheral in FCG0. + ** \arg PWC_FCG0_PERIPH_SRAMH RAMHS clock + ** \arg PWC_FCG0_PERIPH_SRAM12 RAM0 clock + ** \arg PWC_FCG0_PERIPH_SRAM3 ECCRAM clock + ** \arg PWC_FCG0_PERIPH_SRAMRET RetRAM clock + ** \arg PWC_FCG0_PERIPH_DMA1 DMA1 clock + ** \arg PWC_FCG0_PERIPH_DMA2 DMA2 clock + ** \arg PWC_FCG0_PERIPH_FCM FCM clock + ** \arg PWC_FCG0_PERIPH_AOS PTDIS clock + ** \arg PWC_FCG0_PERIPH_AES AES clock + ** \arg PWC_FCG0_PERIPH_HASH HASH clock + ** \arg PWC_FCG0_PERIPH_TRNG TRNG clock + ** \arg PWC_FCG0_PERIPH_CRC CRC clock + ** \arg PWC_FCG0_PERIPH_DCU1 DCU1 clock + ** \arg PWC_FCG0_PERIPH_DCU2 DCU2 clock + ** \arg PWC_FCG0_PERIPH_DCU3 DCU3 clock + ** \arg PWC_FCG0_PERIPH_DCU4 DCU4 clock + ** \arg PWC_FCG0_PERIPH_KEY KEY clock + + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_FCG0_REG_WRITE(); + + if(Enable == enNewState) + { + M4_MSTP->FCG0 &= ~u32Fcg0Periph; + } + else + { + M4_MSTP->FCG0 |= u32Fcg0Periph; + } + + DISABLE_FCG0_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG1 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg1Periph The peripheral in FCG1. + ** \arg PWC_FCG1_PERIPH_CAN CAN clock + ** \arg PWC_FCG1_PERIPH_QSPI QSPI clock + ** \arg PWC_FCG1_PERIPH_I2C1 I2C1 clock + ** \arg PWC_FCG1_PERIPH_I2C2 I2C2 clock + ** \arg PWC_FCG1_PERIPH_I2C3 I2C3 clock + ** \arg PWC_FCG1_PERIPH_USBFS USBFS clock + ** \arg PWC_FCG1_PERIPH_SDIOC1 SDIOC1 clock + ** \arg PWC_FCG1_PERIPH_SDIOC2 SDIOC2 clock + ** \arg PWC_FCG1_PERIPH_I2S1 I2S1 clock + ** \arg PWC_FCG1_PERIPH_I2S2 I2S2 clock + ** \arg PWC_FCG1_PERIPH_I2S3 I2S3 clock + ** \arg PWC_FCG1_PERIPH_I2S4 I2S4 clock + ** \arg PWC_FCG1_PERIPH_SPI1 SPI1 clock + ** \arg PWC_FCG1_PERIPH_SPI2 SPI2 clock + ** \arg PWC_FCG1_PERIPH_SPI3 SPI3 clock + ** \arg PWC_FCG1_PERIPH_SPI4 SPI4 clock + ** \arg PWC_FCG1_PERIPH_USART1 USART1 clock + ** \arg PWC_FCG1_PERIPH_USART2 USART2 clock + ** \arg PWC_FCG1_PERIPH_USART3 USART3 clock + ** \arg PWC_FCG1_PERIPH_USART4 USART4 clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG1 &= ~u32Fcg1Periph; + } + else + { + M4_MSTP->FCG1 |= u32Fcg1Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG2 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg2Periph The peripheral in FCG2. + ** \arg PWC_FCG2_PERIPH_TIM01 TIM01 clock + ** \arg PWC_FCG2_PERIPH_TIM02 TIM02 clock + ** \arg PWC_FCG2_PERIPH_TIMA1 TIMA1 clock + ** \arg PWC_FCG2_PERIPH_TIMA2 TIMA2 clock + ** \arg PWC_FCG2_PERIPH_TIMA3 TIMA3 clock + ** \arg PWC_FCG2_PERIPH_TIMA4 TIMA4 clock + ** \arg PWC_FCG2_PERIPH_TIMA5 TIMA5 clock + ** \arg PWC_FCG2_PERIPH_TIMA6 TIMA6 clock + ** \arg PWC_FCG2_PERIPH_TIM41 TIM41 clock + ** \arg PWC_FCG2_PERIPH_TIM42 TIM42 clock + ** \arg PWC_FCG2_PERIPH_TIM43 TIM43 clock + ** \arg PWC_FCG2_PERIPH_EMB EMB clock + ** \arg PWC_FCG2_PERIPH_TIM61 TIM61 clock + ** \arg PWC_FCG2_PERIPH_TIM62 TIM62 clock + ** \arg PWC_FCG2_PERIPH_TIM63 TIM63 clock + + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG2 &= ~u32Fcg2Periph; + } + else + { + M4_MSTP->FCG2 |= u32Fcg2Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG3 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg3Periph The peripheral in FCG3. + ** \arg PWC_FCG3_PERIPH_ADC1 ADC1 clock + ** \arg PWC_FCG3_PERIPH_ADC2 ADC2 clock + ** \arg PWC_FCG3_PERIPH_CMP CMP clock + ** \arg PWC_FCG3_PERIPH_OTS OTS clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG3 &= ~u32Fcg3Periph; + } + else + { + M4_MSTP->FCG3 |= u32Fcg3Periph; + } +} + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ** \param [in] pstcStpMdCfg Pointer to stop mode configuration structure. + ** \arg Enable Enable stop mode. + ** \arg Disable Disable stop mode. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_PWC_STOP_MODE_FLASH(pstcStpMdCfg->enStopFlash)); + DDL_ASSERT(IS_PWC_STOP_MODE_CLK(pstcStpMdCfg->enStopClk)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR = (pstcStpMdCfg->enStopFlash | + (pstcStpMdCfg->enStopClk << 1u) | + (1u << 14u)); + + /* if should close HRC & PLL while stop mode, please disable before modifying the register */ + if(Disable == pstcStpMdCfg->enPll) + { + /* PLL is system clock */ + if(5u == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Disable PLL */ + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + + /* Hrc power should be enable. */ + M4_SYSREG->PWR_PWRC1_f.VHRCSD = 0u; + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == pstcStpMdCfg->enPll) ? 0u : 1u); + M4_SYSREG->PWR_PWRC1_f.STPDAS = pstcStpMdCfg->enStpDrvAbi; + + DISABLE_PWR_REG0_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_STOPWKUPEN_EIRQ0 EIRQ0 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ1 EIRQ1 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ2 EIRQ2 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ3 EIRQ3 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ4 EIRQ4 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ5 EIRQ5 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ6 EIRQ6 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ7 EIRQ7 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ8 EIRQ8 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ9 EIRQ9 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ10 EIRQ10 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ11 EIRQ11 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ12 EIRQ12 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ13 EIRQ13 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ14 EIRQ14 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ15 EIRQ15 wake_up event + ** \arg PWC_STOPWKUPEN_SWDT SWDT wake_up event + ** \arg PWC_STOPWKUPEN_VDU1 VDU1 wake_up event + ** \arg PWC_STOPWKUPEN_VDU2 VDU2 wake_up event + ** \arg PWC_STOPWKUPEN_CMPI0 CMPI0 wake_up event + ** \arg PWC_STOPWKUPEN_WKTM WKTM wake_up event + ** \arg PWC_STOPWKUPEN_RTCAL RTCAL wake_up event + ** \arg PWC_STOPWKUPEN_RTCPRD RTCPRD wake_up event + ** \arg PWC_STOPWKUPEN_TMR0 TMR0 wake_up event + ** \arg PWC_STOPWKUPEN_USARTRXD USARTRXD wake_up event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_INTC->WUPEN |= u32Wkup0Event; + } + else + { + M4_INTC->WUPEN &= ~u32Wkup0Event; + } +} + +/** + ******************************************************************************* + ** \brief Enter sleep mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterSleepMd(void) +{ + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 0u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} +/** + ******************************************************************************* + ** \brief Ram area power down commond. + ** + ** \param [in] u32RamCtlBit The ram area contol. + ** \arg PWC_RAMPWRDOWN_SRAM1 Ram0(0x20000000-0x2000FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM2 Ram1(0x20010000-0x2001FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM3 Ram2(0x20020000-0x20026FFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAMH Ram3(0x1FFF8000-0x1FFFFFFF) power down control. + ** \arg PWC_RAMPWRDOWN_USBFS Usbfs power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC0 Sdioc0 power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC1 Sdioc1 power down control. + ** \arg PWC_RAMPWRDOWN_CAN Can power down control. + ** \arg PWC_RAMPWRDOWN_CACHE Cache power down control. + ** \arg PWC_RAMPWRDOWN_FULL Full. + ** + ** \param [in] enNewState The new state of the Ram area. + ** \arg Enable Ten ram area run. + ** \arg Disable The ram area power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_RAMPC0 &= ~u32RamCtlBit; + } + else + { + M4_SYSREG->PWR_RAMPC0 |= u32RamCtlBit; + } + + DISABLE_PWR_REG_WRITE(); +} + +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd) +{ + DDL_ASSERT(IS_PWC_RAM_OP_MD(enRamOpMd)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_RAMOPM = enRamOpMd; + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable XTAL/RTC/WKTM bias current. + ** + ** \param [in] enNewState The XTAL/RTC/WKTM bias current state. + ** \arg Enable Enable XTAL/RTC/WKTM bias current. + ** \arg Disable Disable XTAL/RTC/WKTM bias current. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Xtal32CsCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_XTAL32CS_f.CSDIS = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief wake_up timer control. + ** + ** \param [in] pstcWktmCtl The wake_up timer configuration. + ** \arg enWktmEn Enable or disable wake_up timer. + ** \arg enWkclk The wake_up timer clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWktmCtl->enWktmEn)); + DDL_ASSERT(IS_PWC_WKTM_CLK(pstcWktmCtl->enWkclk)); + DDL_ASSERT(IS_PWC_WKTMOVER_FLAG(pstcWktmCtl->enWkOverFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_WKTM->CR = ((pstcWktmCtl->u16WktmCmp & PWC_WKTMCMP_MSK) | + (pstcWktmCtl->enWkOverFlag << 12) | + (pstcWktmCtl->enWkclk << 13) | + (pstcWktmCtl->enWktmEn << 15)); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief The pvd configuration. + ** + ** \param [in] pstcPvdCfg The pvd configuration. + ** \arg enPtwk0Edge Ptwk0 edge + ** \arg enPtwk1Edge Ptwk1 edge + ** \arg enPtwk2Edge Ptwk2 edge + ** \arg enPtwk3Edge Ptwk3 edge + ** \arg enPvd1Edge Pvd1 edge + ** \arg enPvd1Edge Pvd2 edge + ** \arg enNmiEdge Nmi edge + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd1Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd2Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd1FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd1Filtclk)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd2FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd2Filtclk)); + DDL_ASSERT(IS_PWC_PVD1_LEVEL(pstcPvdCfg->enPvd1Level)); + DDL_ASSERT(IS_PWC_PVD2_LEVEL(pstcPvdCfg->enPvd2Level)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd1Int)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd2Int)); + + ENABLE_PVD_REG_WRITE(); + + /* Config Pvd control. */ + M4_SYSREG->PWR_PVDCR1 = (pstcPvdCfg->stcPvd1Ctl.enPvdIREn | + (pstcPvdCfg->stcPvd1Ctl.enPvdMode << 1) | + (pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn << 2) | + (pstcPvdCfg->stcPvd2Ctl.enPvdIREn<< 4) | + (pstcPvdCfg->stcPvd2Ctl.enPvdMode << 5) | + (pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn << 6)); + /* Set pvd filter sampling. */ + M4_SYSREG->PWR_PVDFCR = (~(pstcPvdCfg->enPvd1FilterEn) | + (pstcPvdCfg->enPvd1Filtclk << 1) | + ((~pstcPvdCfg->enPvd2FilterEn) << 4) | + (pstcPvdCfg->enPvd2Filtclk << 5)); + /* Set pvd level. */ + M4_SYSREG->PWR_PVDLCR = (pstcPvdCfg->enPvd1Level | + (pstcPvdCfg->enPvd2Level << 4)); + /* Set pvd interrupt(non_maskable or maskable). */ + M4_SYSREG->PWR_PVDICR = (pstcPvdCfg->enPvd1Int | + (pstcPvdCfg->enPvd2Int << 4)); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd1. + ** + ** \param [in] enNewState The pvd1 state. + ** \arg Enable Enable pvd1. + ** \arg Disable Disable pvd1. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd1Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD1EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd2. + ** + ** \param [in] enNewState The pvd2 state. + ** \arg Enable Enable pvd2. + ** \arg Disable Disable pvd2. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd2Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD2EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable external vcc. + ** + ** \param [in] enNewState The external vcc state. + ** \arg Enable Enable external vcc. + ** \arg Disable Disable external vcc. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ExVccCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.EXVCCINEN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection status. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1MON; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2MON; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd) +{ + ENABLE_PVD_REG_WRITE(); + switch(enPvd) + { + case PvdU1: + M4_SYSREG->PWR_PVDDSR_f.PVD1MON = 0u; + break; + case PvdU2: + M4_SYSREG->PWR_PVDDSR_f.PVD2MON = 0u; + break; + default: + break; + } + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable HRC power. + ** + ** \param [in] enNewState The HRC power state. + ** \arg Enable Enable HRC power. + ** \arg Disable Disable HRC power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_HrcPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VHRCSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable PLL power. + ** + ** \param [in] enNewState The PLL power state. + ** \arg Enable Enable PLL power. + ** \arg Disable Disable PLL power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_PllPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief NVIC backup and disable before entry from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicBackup(void) +{ + uint8_t u8Cnt; + stc_intc_sel_field_t *stcIntSel; + uint32_t u32WakeupSrc = INT_MAX; + + /* Backup NVIC set enable register for IRQ0~143*/ + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC_ISER_BAK[u8Cnt] = NVIC->ISER[u8Cnt]; + } + + /* Disable share vector */ + for (u8Cnt = 128u; u8Cnt < 144u; u8Cnt++) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + + for (u8Cnt = 0u; u8Cnt < 128u; u8Cnt++) + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * u8Cnt)); + /* Disable NVIC if it is the wakeup-able source from stop mode */ + u32WakeupSrc = stcIntSel->INTSEL; + if (IS_VALID_WKUP_SRC(u32WakeupSrc)) + { + switch (stcIntSel->INTSEL) + { + case INT_USART1_WUPI: + if (Reset == bM4_INTC_WUPEN_RXWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_TMR01_GCMA: + if (Reset == bM4_INTC_WUPEN_TMR0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_ALM: + if (Reset == bM4_INTC_WUPEN_RTCALMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_PRD: + if (Reset == bM4_INTC_WUPEN_RTCPRDWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_WKTM_PRD: + if (Reset == bM4_INTC_WUPEN_WKTMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_ACMP1: + if (Reset == bM4_INTC_WUPEN_CMPI0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD1: + if (Reset == bM4_INTC_WUPEN_PVD1WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD2: + if (Reset == bM4_INTC_WUPEN_PVD2WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_SWDT_REFUDF: + if (Reset == bM4_INTC_WUPEN_SWDTWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ0: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN0) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ1: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN1) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ2: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN2) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ3: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN3) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ4: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN4) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ5: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN5) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ6: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN6) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ7: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN7) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ8: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN8) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ9: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN9) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ10: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN10) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ11: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN11) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ12: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN12) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ13: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN13) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ14: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN14) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ15: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN15) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + default: + break; + } + } + /* Disable NVIC for all none-wakeup source */ + else if (INT_MAX != stcIntSel->INTSEL) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + else + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief NVIC recover after wakeup from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicRecover(void) +{ + uint8_t u8Cnt; + + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC->ISER[u8Cnt] = NVIC_ISER_BAK[u8Cnt]; + } +} + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] u8SysSrc The system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** This function only be called in func. PWC_enClockBackup and + ** PWC_enClockRecover. + ** If need to switch system clock please call CLK_SetSysClkSource. + ** + ******************************************************************************/ +static void PWC_SetSysClk(uint8_t u8SysSrc) +{ + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((5u == M4_SYSREG->CMU_CKSWR_f.CKSW) || (5u == u8SysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = 0xFFFFFAEEul; + M4_MSTP->FCG1 = 0xFFFFFFFFul; + M4_MSTP->FCG2 = 0xFFFFFFFFul; + M4_MSTP->FCG3 = 0xFFFFFFFFul; + + Ddl_Delay1us(1ul); + } + + /* Switch to target system clock source. */ + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = u8SysSrc; + + DISABLE_PWR_REG0_WRITE(); + + /* update system clock frequency. */ + SystemCoreClockUpdate(); + + Ddl_Delay1us(1ul); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + Ddl_Delay1us(1ul); +} +/** + ******************************************************************************* + ** \brief Backup HRC/MRC state and system clock , enable HRC/MRC ,set MRC as + ** system clock before enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockBackup(void) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status = Reset; + + /* HRC state backup. */ + u8HrcState = (uint8_t)bM4_SYSREG_CMU_HRCCR_HRCSTP; + /* System clock backup*/ + u8SysClkSrc = M4_SYSREG->CMU_CKSWR_f.CKSW; + + ENABLE_PWR_REG0_WRITE(); + + /* Enable HRC before enter stop mode. */ + if(0u != u8HrcState) + { + bM4_SYSREG_CMU_HRCCR_HRCSTP = 0u; + do + { + status = (en_flag_status_t)M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF; + timeout++; + }while((timeout < 0x1000ul) && (status != Set)); + } + else + { + /* code */ + } + /* When system clock source is HRC and MPLL, set MRC as system clock. . */ + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* MRC state backup. */ + u8MrcState = (uint8_t)bM4_SYSREG_CMU_MRCCR_MRCSTP; + if(0u != u8MrcState) + { + bM4_SYSREG_CMU_MRCCR_MRCSTP = 0u; + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + PWC_SetSysClk(1u); + } + else + { + /* code */ + } + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Recover HRC/MRC state and system clock after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockRecover(void) +{ + ENABLE_PWR_REG0_WRITE(); + + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* Recover MRC state & system clock source. */ + M4_SYSREG->CMU_MRCCR_f.MRCSTP = u8MrcState; + PWC_SetSysClk(u8SysClkSrc); + } + /* Recover HRC state after wakeup stop mode. */ + M4_SYSREG->CMU_HRCCR_f.HRCSTP = u8HrcState; + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before enter stop mode and mark it. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkBackup(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* HRC/MRC backup and switch system clock as MRC before entry from stop mode. */ + PWC_enClockBackup(); + + /* Mark the system clock has been switch as MRC, and will enter the stop mode. */ + u8StopFlag = 1u; + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock recover after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called after func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkRecover(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* Mark the system clock will be switch as MRC, and has waked_up from stop mode. */ + u8StopFlag = 0u; + + /* Recover HRC/MRC state and system clock after wakeup stop mode. */ + PWC_enClockRecover(); + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before exit wakup interrupt. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before exit wakup interrput. + ******************************************************************************/ +void PWC_IrqClkBackup(void) +{ + if((1ul == u8StopFlag) && (1ul == u8WkupIntCnt)) + { + /* HRC/MRC backup and switch system clock as MRC. */ + PWC_enClockBackup(); + } + u8WkupIntCnt--; +} + +/** + ******************************************************************************* + ** \brief Clock recover after enter wakeup interrupt. + ** + ** \param None + ** + ** \retval None + ** +** \note This function should be called after enter wakup interrput. + ******************************************************************************/ +void PWC_IrqClkRecover(void) +{ + /* The varibale to display how many waked_up interrupt has been occured + simultaneously and to decided whether backup clock before exit wake_up + interrupt. */ + u8WkupIntCnt++; + + if(1ul == u8StopFlag) + { + /* Recover HRC/MRC state and system clock. */ + PWC_enClockRecover(); + } +} + +/** + ******************************************************************************* + ** \brief Enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterStopMd(void) +{ + /* NVIC backup and disable before entry from stop mode.*/ + PWC_enNvicBackup(); + /* Clock backup and switch system clock as MRC before entry from stop mode. */ + PWC_ClkBackup(); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG0_WRITE(); + + __WFI(); + + /* Recover HRC/MRC state and system clock after wakeup from stop mode. */ + PWC_ClkRecover(); + /* NVIC recover after wakeup from stop mode. */ + PWC_enNvicRecover(); +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low_speed (HCLK < 8MHz) to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + M4_SYSREG->PWR_PWRC2 = 0xE1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to low_speed (HCLK < 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HS(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1ul); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2HP(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2HS(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low-speed (HCLK <= 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HP(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to low-speed (HCLK <= 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + u32To = 10000ul; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + M4_SYSREG->PWR_PWRC2 = 0xD1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1); + + return Ok; +} + +#endif /* DDL_PWC_ENABLE */ + +//@} // PwcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c new file mode 100644 index 000000000..1f471aa6b --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c @@ -0,0 +1,756 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.c + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_qspi.h" +#include "hc32f460_utility.h" + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup QspiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( ((x) == QspiHclkDiv2) || \ + (((x) >= QspiHclkDiv3) && ((x) <= QspiHclkDiv64))) + +/*!< Parameter valid check for spi mode */ +#define IS_VALID_SPI_MODE(x) \ +( (QspiSpiMode0 == (x)) || \ + (QspiSpiMode3 == (x))) + +/*!< Parameter valid check for bus communication mode */ +#define IS_VALID_BUS_COMM_MODE(x) \ +( (QspiBusModeRomAccess == (x)) || \ + (QspiBusModeDirectAccess == (x))) + +/*!< Parameter valid check for prefetch stop location */ +#define IS_VALID_PREFETCH_STOP_LOCATION(x) \ +( (QspiPrefetchStopComplete == (x)) || \ + (QspiPrefetchStopImmediately == (x))) + +/*!< Parameter valid check for receive data protocol */ +#define IS_VALID_RECE_DATA_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit address protocol */ +#define IS_VALID_TRANS_ADDR_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit instruction protocol */ +#define IS_VALID_TRANS_INSTRUCT_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for serial interface read mode */ +#define IS_VALID_INTERFACE_READ_MODE(x) \ +( (QspiReadModeStandard == (x)) || \ + (QspiReadModeFast == (x)) || \ + (QspiReadModeTwoWiresOutput == (x)) || \ + (QspiReadModeTwoWiresIO == (x)) || \ + (QspiReadModeFourWiresOutput == (x)) || \ + (QspiReadModeFourWiresIO == (x)) || \ + (QspiReadModeCustomStandard == (x)) || \ + (QspiReadModeCustomFast == (x))) + +/*!< Parameter valid check for QSSN valid extend delay time */ +#define IS_VALID_QSSN_VALID_EXTEND_TIME(x) \ +( (QspiQssnValidExtendNot == (x)) || \ + (QspiQssnValidExtendSck32 == (x)) || \ + (QspiQssnValidExtendSck128 == (x)) || \ + (QspiQssnValidExtendSckEver == (x))) + +/*!< Parameter valid check for QSSN minimum interval time */ +#define IS_VALID_QSSN_INTERVAL_TIME(x) \ +( (QspiQssnIntervalQsck1 == (x)) || \ + (QspiQssnIntervalQsck2 == (x)) || \ + (QspiQssnIntervalQsck3 == (x)) || \ + (QspiQssnIntervalQsck4 == (x)) || \ + (QspiQssnIntervalQsck5 == (x)) || \ + (QspiQssnIntervalQsck6 == (x)) || \ + (QspiQssnIntervalQsck7 == (x)) || \ + (QspiQssnIntervalQsck8 == (x)) || \ + (QspiQssnIntervalQsck9 == (x)) || \ + (QspiQssnIntervalQsck10 == (x)) || \ + (QspiQssnIntervalQsck11 == (x)) || \ + (QspiQssnIntervalQsck12 == (x)) || \ + (QspiQssnIntervalQsck13 == (x)) || \ + (QspiQssnIntervalQsck14 == (x)) || \ + (QspiQssnIntervalQsck15 == (x)) || \ + (QspiQssnIntervalQsck16 <= (x))) + +/*!< Parameter valid check for QSCK duty correction */ +#define IS_VALID_QSCK_DUTY_CORR(x) \ +( (QspiQsckDutyCorrNot == (x)) || \ + (QspiQsckDutyCorrHalfHclk == (x))) + +/*!< Parameter valid check for virtual cycles */ +#define IS_VALID_VIRTUAL_CYCLES(x) \ +( (QspiVirtualPeriodQsck3 == (x)) || \ + (QspiVirtualPeriodQsck4 == (x)) || \ + (QspiVirtualPeriodQsck5 == (x)) || \ + (QspiVirtualPeriodQsck6 == (x)) || \ + (QspiVirtualPeriodQsck7 == (x)) || \ + (QspiVirtualPeriodQsck8 == (x)) || \ + (QspiVirtualPeriodQsck9 == (x)) || \ + (QspiVirtualPeriodQsck10 == (x)) || \ + (QspiVirtualPeriodQsck11 == (x)) || \ + (QspiVirtualPeriodQsck12 == (x)) || \ + (QspiVirtualPeriodQsck13 == (x)) || \ + (QspiVirtualPeriodQsck14 == (x)) || \ + (QspiVirtualPeriodQsck15 == (x)) || \ + (QspiVirtualPeriodQsck16 == (x)) || \ + (QspiVirtualPeriodQsck17 == (x)) || \ + (QspiVirtualPeriodQsck18 == (x))) + +/*!< Parameter valid check for WP pin output level */ +#define IS_VALID_WP_OUTPUT_LEVEL(x) \ +( (QspiWpPinOutputLow == (x)) || \ + (QspiWpPinOutputHigh == (x))) + +/*!< Parameter valid check for QSSN setup delay time */ +#define IS_VALID_QSSN_SETUP_DELAY(x) \ +( (QspiQssnSetupDelayHalfQsck == (x)) || \ + (QspiQssnSetupDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for QSSN hold delay time */ +#define IS_VALID_QSSN_HOLD_TIME(x) \ +( (QspiQssnHoldDelayHalfQsck == (x)) || \ + (QspiQssnHoldDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for interface address width */ +#define IS_VALID_INTERFACE_ADDR_WIDTH(x) \ +( (QspiAddressByteOne == (x)) || \ + (QspiAddressByteTwo == (x)) || \ + (QspiAddressByteThree == (x)) || \ + (QspiAddressByteFour == (x))) + +/*!< Parameter valid check for extend address */ +#define IS_VALID_SET_EXTEND_ADDR(x) ((x) <= 0x3Fu) + +/*!< Parameter valid check for get flag type */ +#define IS_VALID_GET_FLAG_TYPE(x) \ +( (QspiFlagBusBusy == (x)) || \ + (QspiFlagXipMode == (x)) || \ + (QspiFlagRomAccessError == (x)) || \ + (QspiFlagPrefetchBufferFull == (x)) || \ + (QspiFlagPrefetchStop == (x))) + +/*!< Parameter valid check for clear flag type */ +#define IS_VALID_CLEAR_FLAG_TYPE(x) (QspiFlagRomAccessError == (x)) + +/*!< QSPI registers reset value */ +#define QSPI_REG_CR_RESET_VALUE (0x003F0000ul) +#define QSPI_REG_CSCR_RESET_VALUE (0x0000000Ful) +#define QSPI_REG_FCR_RESET_VALUE (0x000080B3ul) +#define QSPI_REG_SR_RESET_VALUE (0x00008000ul) +#define QSPI_REG_CCMD_RESET_VALUE (0x00000000ul) +#define QSPI_REG_XCMD_RESET_VALUE (0x000000FFul) +#define QSPI_REG_EXAR_RESET_VALUE (0x00000000ul) +#define QSPI_REG_SR2_RESET_VALUE (0x00000000ul) +#define QSPI_REG_DCOM_RESET_VALUE (0x00000000ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize QSPI unit + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_DeInit(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR = QSPI_REG_CR_RESET_VALUE; + if (1u == M4_QSPI->SR_f.RAER) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + M4_QSPI->CSCR = QSPI_REG_CSCR_RESET_VALUE; + M4_QSPI->FCR = QSPI_REG_FCR_RESET_VALUE; + M4_QSPI->EXAR = QSPI_REG_EXAR_RESET_VALUE; + M4_QSPI->SR = QSPI_REG_SR_RESET_VALUE; + M4_QSPI->CCMD = QSPI_REG_CCMD_RESET_VALUE; + M4_QSPI->XCMD = QSPI_REG_XCMD_RESET_VALUE; + M4_QSPI->DCOM = QSPI_REG_DCOM_RESET_VALUE; + M4_QSPI->SR2 = QSPI_REG_SR2_RESET_VALUE; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize QSPI unit + ** + ** \param [in] pstcQspiInitCfg Pointer to qspi configuration + ** \arg See the struct #stc_qspi_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcQspiInitCfg) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_DIV(pstcQspiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_SPI_MODE(pstcQspiInitCfg->enSpiMode)); + DDL_ASSERT(IS_VALID_BUS_COMM_MODE(pstcQspiInitCfg->enBusCommMode)); + DDL_ASSERT(IS_VALID_PREFETCH_STOP_LOCATION(pstcQspiInitCfg->enPrefetchMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enPrefetchFuncEn)); + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcQspiInitCfg->stcCommProtocol.enReadMode)); + DDL_ASSERT(IS_VALID_QSSN_VALID_EXTEND_TIME(pstcQspiInitCfg->enQssnValidExtendTime)); + DDL_ASSERT(IS_VALID_QSSN_INTERVAL_TIME(pstcQspiInitCfg->enQssnIntervalTime)); + DDL_ASSERT(IS_VALID_QSCK_DUTY_CORR(pstcQspiInitCfg->enQsckDutyCorr)); + DDL_ASSERT(IS_VALID_VIRTUAL_CYCLES(pstcQspiInitCfg->enVirtualPeriod)); + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(pstcQspiInitCfg->enWpPinLevel)); + DDL_ASSERT(IS_VALID_QSSN_SETUP_DELAY(pstcQspiInitCfg->enQssnSetupDelayTime)); + DDL_ASSERT(IS_VALID_QSSN_HOLD_TIME(pstcQspiInitCfg->enQssnHoldDelayTime)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enFourByteAddrReadEn)); + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(pstcQspiInitCfg->enAddrWidth)); + + /* Configure control register */ + M4_QSPI->CR_f.DIV = pstcQspiInitCfg->enClkDiv; + M4_QSPI->CR_f.SPIMD3 = pstcQspiInitCfg->enSpiMode; + M4_QSPI->CR_f.PFE = pstcQspiInitCfg->enPrefetchFuncEn; + M4_QSPI->CR_f.PFSAE = pstcQspiInitCfg->enPrefetchMode; + M4_QSPI->CR_f.MDSEL = pstcQspiInitCfg->stcCommProtocol.enReadMode; + + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcQspiInitCfg->stcCommProtocol.enReadMode) || + (QspiReadModeCustomStandard == pstcQspiInitCfg->stcCommProtocol.enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcQspiInitCfg->stcCommProtocol.enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + + /* Configure chip select control register */ + M4_QSPI->CSCR_f.SSNW = pstcQspiInitCfg->enQssnValidExtendTime; + M4_QSPI->CSCR_f.SSHW = pstcQspiInitCfg->enQssnIntervalTime; + + /* Configure format control register */ + if (((pstcQspiInitCfg->enClkDiv % 2) != 0) && + (pstcQspiInitCfg->enQsckDutyCorr != QspiQsckDutyCorrNot)) + { + M4_QSPI->FCR_f.DUTY = QspiQsckDutyCorrNot; + } + else + { + M4_QSPI->FCR_f.DUTY = pstcQspiInitCfg->enQsckDutyCorr; + } + M4_QSPI->FCR_f.DMCYCN = pstcQspiInitCfg->enVirtualPeriod; + M4_QSPI->FCR_f.WPOL = pstcQspiInitCfg->enWpPinLevel; + M4_QSPI->FCR_f.SSNLD = pstcQspiInitCfg->enQssnSetupDelayTime; + M4_QSPI->FCR_f.SSNHD = pstcQspiInitCfg->enQssnHoldDelayTime; + M4_QSPI->FCR_f.FOUR_BIC = pstcQspiInitCfg->enFourByteAddrReadEn; + M4_QSPI->FCR_f.AWSL = pstcQspiInitCfg->enAddrWidth; + M4_QSPI->CR_f.DCOME = pstcQspiInitCfg->enBusCommMode; + + /* Configure ROM access instruction */ + M4_QSPI->CCMD = pstcQspiInitCfg->u8RomAccessInstr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Config communication protocol structure + ** + ** \param [in] pstcCommProtocol Pointer to qspi communication protocol configuration + ** \arg See the struct #stc_qspi_comm_protocol_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol) +{ + en_result_t enRet = Ok; + + if (NULL == pstcCommProtocol) + { + enRet = Error; + } + else + { + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcCommProtocol->enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcCommProtocol->enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcCommProtocol->enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcCommProtocol->enReadMode)); + + M4_QSPI->CR_f.MDSEL = pstcCommProtocol->enReadMode; + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcCommProtocol->enReadMode) || + (QspiReadModeCustomStandard == pstcCommProtocol->enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcCommProtocol->enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcCommProtocol->enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcCommProtocol->enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable prefetch function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable prefetch function + ** \arg Enable Enable prefetch function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->CR_f.PFE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set clock division + ** + ** \param [in] enClkDiv Clock division + ** \arg QspiHclkDiv2 Clock source: HCLK/2 + ** \arg QspiHclkDiv3 Clock source: HCLK/3 + ** \arg QspiHclkDiv4 Clock source: HCLK/4 + ** \arg QspiHclkDiv5 Clock source: HCLK/5 + ** \arg QspiHclkDiv6 Clock source: HCLK/6 + ** \arg QspiHclkDiv7 Clock source: HCLK/7 + ** \arg QspiHclkDiv8 Clock source: HCLK/8 + ** \arg QspiHclkDiv9 Clock source: HCLK/9 + ** \arg QspiHclkDiv10 Clock source: HCLK/10 + ** \arg QspiHclkDiv11 Clock source: HCLK/11 + ** \arg QspiHclkDiv12 Clock source: HCLK/12 + ** \arg QspiHclkDiv13 Clock source: HCLK/13 + ** \arg QspiHclkDiv14 Clock source: HCLK/14 + ** \arg QspiHclkDiv15 Clock source: HCLK/15 + ** \arg QspiHclkDiv16 Clock source: HCLK/16 + ** \arg QspiHclkDiv17 Clock source: HCLK/17 + ** \arg QspiHclkDiv18 Clock source: HCLK/18 + ** \arg QspiHclkDiv19 Clock source: HCLK/19 + ** \arg QspiHclkDiv20 Clock source: HCLK/20 + ** \arg QspiHclkDiv21 Clock source: HCLK/21 + ** \arg QspiHclkDiv22 Clock source: HCLK/22 + ** \arg QspiHclkDiv23 Clock source: HCLK/23 + ** \arg QspiHclkDiv24 Clock source: HCLK/24 + ** \arg QspiHclkDiv25 Clock source: HCLK/25 + ** \arg QspiHclkDiv26 Clock source: HCLK/26 + ** \arg QspiHclkDiv27 Clock source: HCLK/27 + ** \arg QspiHclkDiv28 Clock source: HCLK/28 + ** \arg QspiHclkDiv29 Clock source: HCLK/29 + ** \arg QspiHclkDiv30 Clock source: HCLK/30 + ** \arg QspiHclkDiv31 Clock source: HCLK/31 + ** \arg QspiHclkDiv32 Clock source: HCLK/32 + ** \arg QspiHclkDiv33 Clock source: HCLK/33 + ** \arg QspiHclkDiv34 Clock source: HCLK/34 + ** \arg QspiHclkDiv35 Clock source: HCLK/35 + ** \arg QspiHclkDiv36 Clock source: HCLK/36 + ** \arg QspiHclkDiv37 Clock source: HCLK/37 + ** \arg QspiHclkDiv38 Clock source: HCLK/38 + ** \arg QspiHclkDiv39 Clock source: HCLK/39 + ** \arg QspiHclkDiv40 Clock source: HCLK/40 + ** \arg QspiHclkDiv41 Clock source: HCLK/41 + ** \arg QspiHclkDiv42 Clock source: HCLK/42 + ** \arg QspiHclkDiv43 Clock source: HCLK/43 + ** \arg QspiHclkDiv44 Clock source: HCLK/44 + ** \arg QspiHclkDiv45 Clock source: HCLK/45 + ** \arg QspiHclkDiv46 Clock source: HCLK/46 + ** \arg QspiHclkDiv47 Clock source: HCLK/47 + ** \arg QspiHclkDiv48 Clock source: HCLK/48 + ** \arg QspiHclkDiv49 Clock source: HCLK/49 + ** \arg QspiHclkDiv50 Clock source: HCLK/50 + ** \arg QspiHclkDiv51 Clock source: HCLK/51 + ** \arg QspiHclkDiv52 Clock source: HCLK/52 + ** \arg QspiHclkDiv53 Clock source: HCLK/53 + ** \arg QspiHclkDiv54 Clock source: HCLK/54 + ** \arg QspiHclkDiv55 Clock source: HCLK/55 + ** \arg QspiHclkDiv56 Clock source: HCLK/56 + ** \arg QspiHclkDiv57 Clock source: HCLK/57 + ** \arg QspiHclkDiv58 Clock source: HCLK/58 + ** \arg QspiHclkDiv59 Clock source: HCLK/59 + ** \arg QspiHclkDiv60 Clock source: HCLK/60 + ** \arg QspiHclkDiv61 Clock source: HCLK/61 + ** \arg QspiHclkDiv62 Clock source: HCLK/62 + ** \arg QspiHclkDiv63 Clock source: HCLK/63 + ** \arg QspiHclkDiv64 Clock source: HCLK/64 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + M4_QSPI->CR_f.DIV = enClkDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set WP Pin level + ** + ** \param [in] enWpLevel WP pin level + ** \arg QspiWpPinOutputLow WP pin(QIO2) output low level + ** \arg QspiWpPinOutputHigh WP pin(QIO2) output high level + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(enWpLevel)); + + M4_QSPI->FCR_f.WPOL = enWpLevel; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set communication address width + ** + ** \param [in] enAddrWidth Communication address width + ** \arg QspiAddressByteOne One byte address + ** \arg QspiAddressByteTwo Two byte address + ** \arg QspiAddressByteThree Three byte address + ** \arg QspiAddressByteFour Four byte address + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(enAddrWidth)); + + M4_QSPI->FCR_f.AWSL = enAddrWidth; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set extend address value + ** + ** \param [in] u8Addr Extend address value + ** \arg 0~0x3F + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_SET_EXTEND_ADDR(u8Addr)); + + M4_QSPI->EXAR_f.EXADR = u8Addr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set rom access instruction + ** + ** \param [in] u8Instr Rom access instruction + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr) +{ + en_result_t enRet = Ok; + + M4_QSPI->CCMD = u8Instr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write direct communication value + ** + ** \param [in] u8Val Direct communication value + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val) +{ + en_result_t enRet = Ok; + + M4_QSPI->DCOM = u8Val; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read direct communication value + ** + ** \param [in] None + ** + ** \retval uint8_t Direct communication read value + ** + ******************************************************************************/ +uint8_t QSPI_ReadDirectCommValue(void) +{ + return ((uint8_t)M4_QSPI->DCOM); +} + +/** + ******************************************************************************* + ** \brief Enable or disable xip mode + ** + ** \param [in] u8Instr Enable or disable xip mode instruction + ** \arg 0~0xFF + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable xip mode + ** \arg Enable Enable xip mode + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->XCMD = u8Instr; + if (Enable == enNewSta) + { + M4_QSPI->CR_f.XIPE = 1u; + } + else + { + M4_QSPI->CR_f.XIPE = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ** \note If you are in XIP mode, you need to exit XIP mode and then start direct communication mode. + ** + ******************************************************************************/ +en_result_t QSPI_EnterDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 1u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_ExitDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 0u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get prefetch buffer current byte number + ** + ** \param [in] None + ** + ** \retval uint8_t Current buffer byte number + ** + ******************************************************************************/ +uint8_t QSPI_GetPrefetchBufferNum(void) +{ + return ((uint8_t)M4_QSPI->SR_f.PFNUM); +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagBusBusy QSPI bus work status flag in direct communication mode + ** \arg QspiFlagXipMode XIP mode status signal + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** \arg QspiFlagPrefetchBufferFull Prefetch buffer area status signal + ** \arg QspiFlagPrefetchStop Prefetch action status signal + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + DDL_ASSERT(IS_VALID_GET_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case QspiFlagBusBusy: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.BUSY; + break; + case QspiFlagXipMode: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.XIPF; + break; + case QspiFlagRomAccessError: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.RAER; + break; + case QspiFlagPrefetchBufferFull: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFFUL; + break; + case QspiFlagPrefetchStop: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFAN; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + if (QspiFlagRomAccessError == enFlag) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +//@} // QspiGroup + +#endif /* DDL_QSPI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c new file mode 100644 index 000000000..301f462f9 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.c + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rmu.h" +#include "hc32f460_utility.h" + +#if (DDL_RMU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup RmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa502u) +#define DISABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa500u) + +#define RMU_FLAG_TIM ((uint16_t)0x1000u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Get the chip reset cause. + ** + ** \param [in] pstcData Pointer to return reset cause structure. + ** + ** \retval Ok Get successfully. + ** + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData) +{ + uint16_t u16RstCause = 0u; + stc_sysreg_rmu_rstf0_field_t *RMU_RSTF0_f = NULL; + + if(NULL == pstcData) + { + return ErrorInvalidParameter; + } + + u16RstCause = M4_SYSREG->RMU_RSTF0; + RMU_RSTF0_f = (stc_sysreg_rmu_rstf0_field_t *)(&u16RstCause); + + pstcData->enMultiRst = (en_flag_status_t)(RMU_RSTF0_f->MULTIRF == 1u); + pstcData->enXtalErr = (en_flag_status_t)(RMU_RSTF0_f->XTALERF == 1u); + pstcData->enClkFreqErr = (en_flag_status_t)(RMU_RSTF0_f->CKFERF == 1u); + pstcData->enRamEcc = (en_flag_status_t)(RMU_RSTF0_f->RAECRF == 1u); + pstcData->enRamParityErr = (en_flag_status_t)(RMU_RSTF0_f->RAPERF == 1u); + pstcData->enMpuErr = (en_flag_status_t)(RMU_RSTF0_f->MPUERF == 1u); + pstcData->enSoftware = (en_flag_status_t)(RMU_RSTF0_f->SWRF == 1u); + pstcData->enPowerDown = (en_flag_status_t)(RMU_RSTF0_f->PDRF == 1u); + pstcData->enSwdt = (en_flag_status_t)(RMU_RSTF0_f->SWDRF == 1u); + pstcData->enWdt = (en_flag_status_t)(RMU_RSTF0_f->WDRF == 1u); + pstcData->enPvd2 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enPvd1 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enBrownOut = (en_flag_status_t)(RMU_RSTF0_f->BORF == 1u); + pstcData->enRstPin = (en_flag_status_t)(RMU_RSTF0_f->PINRF == 1u); + pstcData->enPowerOn = (en_flag_status_t)(RMU_RSTF0_f->PORF == 1u); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Clear the reset flag. + ** + ** \param None + ** + ** \retval Ok Clear successfully. + ** + ** \note clear reset flag should be done after read RMU_RSTF0 register. + ******************************************************************************/ +en_result_t RMU_ClrResetFlag(void) +{ + uint16_t u16status = 0u; + uint32_t u32timeout = 0u; + + ENABLE_RMU_REG_WRITE(); + + do + { + u32timeout++; + M4_SYSREG->RMU_RSTF0_f.CLRF = 1u; + u16status = M4_SYSREG->RMU_RSTF0; + }while((u32timeout != RMU_FLAG_TIM) && u16status); + + DISABLE_RMU_REG_WRITE(); + + if(u32timeout >= RMU_FLAG_TIM) + { + return ErrorTimeout; + } + + return Ok; +} + + +//@} // RmuGroup + +#endif /* DDL_RMU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c new file mode 100644 index 000000000..577f46fa6 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c @@ -0,0 +1,978 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.c + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rtc.h" +#include "hc32f460_utility.h" + +#if (DDL_RTC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock source type */ +#define IS_VALID_CLK_SOURCE_TYPE(x) \ +( (RtcClkXtal32 == (x)) || \ + (RtcClkLrc == (x))) + +/*!< Parameter valid check for period interrupt condition */ +#define IS_VALID_PERIOD_INT_CONDITION(x) \ +( (RtcPeriodIntInvalid == (x)) || \ + (RtcPeriodIntHalfSec == (x)) || \ + (RtcPeriodIntOneSec == (x)) || \ + (RtcPeriodIntOneMin == (x)) || \ + (RtcPeriodIntOneHour == (x)) || \ + (RtcPeriodIntOneDay == (x)) || \ + (RtcPeriodIntOneMon == (x))) + +/*!< Parameter valid check for time format */ +#define IS_VALID_TIME_FORMAT(x) \ +( (RtcTimeFormat12Hour == (x)) || \ + (RtcTimeFormat24Hour == (x))) + +/*!< Parameter valid check for compensation way */ +#define IS_VALID_COMPEN_WAY(x) \ +( (RtcOutputCompenDistributed == (x)) || \ + (RtcOutputCompenUniform == (x))) + +/*!< Parameter valid check for compensation value range */ +#define IS_VALID_COMPEN_VALUE_RANGE(x) ((x) <= 0x1FFu) + +/*!< Parameter valid check for data format */ +#define IS_VALID_DATA_FORMAT(x) \ +( (RtcDataFormatDec == (x)) || \ + (RtcDataFormatBcd == (x))) + +/*!< Parameter valid check for time second */ +#define IS_VALID_TIME_SECOND(x) ((x) <= 59u) + +/*!< Parameter valid check for time minute */ +#define IS_VALID_TIME_MINUTE(x) ((x) <= 59u) + +/*!< Parameter valid check for time hour */ +#define IS_VALID_TIME_HOUR12(x) (((x) >= 1u) && ((x) <= 12u)) +#define IS_VALID_TIME_HOUR24(x) ((x) <= 23u) + +/*!< Parameter valid check for date weekday */ +#define IS_VALID_DATE_WEEKDAY(x) ((x) <= 6u) + +/*!< Parameter valid check for date day */ +#define IS_VALID_DATE_DAY(x) (((x) >= 1u) && ((x) <= 31u)) + +/*!< Parameter valid check for date month */ +#define IS_VALID_DATE_MONTH(x) (((x) >= 1u) && ((x) <= 12u)) + +/*!< Parameter valid check for date year */ +#define IS_VALID_DATE_YEAR(x) ((x) <= 99u) + +/*!< Parameter valid check for hour12 am/pm */ +#define IS_VALID_HOUR12_AMPM(x) \ +( (RtcHour12Am == (x)) || \ + (RtcHour12Pm == (x))) + +/*!< Parameter valid check for alarm weekday */ +#define IS_VALID_ALARM_WEEKDAY(x) (((x) >= 1u) && ((x) <= 0x7Fu)) + +/*!< Parameter valid check for interrupt request type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (RtcIrqPeriod == (x)) || \ + (RtcIrqAlarm == (x))) + +/*!< 12 hour format am/pm status bit */ +#define RTC_HOUR12_AMPM_MASK (0x20u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize RTC + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout De-Initialize timeout + ** + ******************************************************************************/ +en_result_t RTC_DeInit(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + M4_RTC->CR0_f.RESET = 0u; + /* Waiting for normal count status or end of RTC software reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR0_f.RESET; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + /* Initialize all RTC registers */ + M4_RTC->CR0_f.RESET = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize RTC + ** + ** \param [in] pstcRtcInit Pointer to RTC init configuration + ** \arg See the struct #stc_rtc_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_SOURCE_TYPE(pstcRtcInit->enClkSource)); + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(pstcRtcInit->enPeriodInt)); + DDL_ASSERT(IS_VALID_TIME_FORMAT(pstcRtcInit->enTimeFormat)); + DDL_ASSERT(IS_VALID_COMPEN_WAY(pstcRtcInit->enCompenWay)); + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(pstcRtcInit->u16CompenVal)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcRtcInit->enCompenEn)); + + /* Configure clock */ + if (RtcClkLrc == pstcRtcInit->enClkSource) + { + M4_RTC->CR3_f.LRCEN = 1u; + } + M4_RTC->CR3_f.RCKSEL = pstcRtcInit->enClkSource; + + /* Configure control register */ + M4_RTC->CR1_f.PRDS = pstcRtcInit->enPeriodInt; + M4_RTC->CR1_f.AMPM = pstcRtcInit->enTimeFormat; + M4_RTC->CR1_f.ONEHZSEL = pstcRtcInit->enCompenWay; + + /* Configure clock error compensation register */ + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)pstcRtcInit->u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)pstcRtcInit->u16CompenVal & 0x00FFu; + M4_RTC->ERRCRH_f.COMPEN = pstcRtcInit->enCompenEn; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Enter mode timeout + ** + ******************************************************************************/ +en_result_t RTC_EnterRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RWEN bit set */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Exit mode timeout + ** + ******************************************************************************/ +en_result_t RTC_ExitRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RWEN bit reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC count + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC count + ** \arg Enable Enable RTC count + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_Cmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.START = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC period interrupt config + ** + ** \param [in] enIntType Period interrupt request type + ** \arg RtcPeriodIntInvalid Period interrupt invalid + ** \arg RtcPeriodIntHalfSec 0.5 second period interrupt + ** \arg RtcPeriodIntOneSec 1 second period interrupt + ** \arg RtcPeriodIntOneMin 1 minute period interrupt + ** \arg RtcPeriodIntOneHour 1 hour period interrupt + ** \arg RtcPeriodIntOneDay 1 day period interrupt + ** \arg RtcPeriodIntOneMon 1 month period interrupt + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(enIntType)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.PRDIE; + /* Disable period interrupt when START=1 and PRDIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 0u; + } + M4_RTC->CR1_f.PRDS = enIntType; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC switch to low power mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode RTC count not start + ** \retval ErrorTimeout Switch timeout + ** + ******************************************************************************/ +en_result_t RTC_LowPowerSwitch(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = ErrorInvalidMode; + + /* Check RTC work status */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RTC RWEN bit set */ + u32Timeout = SystemCoreClock / 100u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RTC RWEN bit reset */ + u32TimeCnt = 0u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC 1hz output compensation value + ** + ** \param [in] u16CompenVal Clock compensation value + ** \arg 0~0x1FF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(u16CompenVal)); + + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)u16CompenVal & 0x00FFu; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable clock compensation + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC clock compensation + ** \arg Enable Enable RTC clock compensation + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->ERRCRH_f.COMPEN = enNewSta; + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Enable or disable RTC 1hz output + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC 1hz output + ** \arg Enable Enable RTC 1hz output + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.ONEHZOE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \param [in] enUpdateDateEn The function new state(Contain year/month/day/weekday) + ** \arg Disable Disable update RTC date + ** \arg Enable Enable update RTC date + ** + ** \param [in] enUpdateTimeEn The function new state(Contain hour/minute/second) + ** \arg Disable Disable update RTC time + ** \arg Enable Enable update RTC time + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** \retval ErrorInvalidParameter Parameter enUpdateDateEn or enUpdateTimeEn invalid + ** + ******************************************************************************/ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateDateEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateTimeEn)); + + /* Check update status */ + if (((Disable == enUpdateDateEn) && (Disable == enUpdateTimeEn)) || (NULL == pstcRtcDateTime)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check the date parameters */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + DDL_ASSERT(IS_VALID_DATE_YEAR(pstcRtcDateTime->u8Year)); + DDL_ASSERT(IS_VALID_DATE_MONTH(pstcRtcDateTime->u8Month)); + DDL_ASSERT(IS_VALID_DATE_DAY(pstcRtcDateTime->u8Day)); + } + else + { + DDL_ASSERT(IS_VALID_DATE_YEAR(BCD2DEC(pstcRtcDateTime->u8Year))); + DDL_ASSERT(IS_VALID_DATE_MONTH(BCD2DEC(pstcRtcDateTime->u8Month))); + DDL_ASSERT(IS_VALID_DATE_DAY(BCD2DEC(pstcRtcDateTime->u8Day))); + } + DDL_ASSERT(IS_VALID_DATE_WEEKDAY(pstcRtcDateTime->u8Weekday)); + } + /* Check the time parameters */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcDateTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcDateTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcDateTime->u8Minute)); + DDL_ASSERT(IS_VALID_TIME_SECOND(pstcRtcDateTime->u8Second)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcDateTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcDateTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcDateTime->u8Minute))); + DDL_ASSERT(IS_VALID_TIME_SECOND(BCD2DEC(pstcRtcDateTime->u8Second))); + } + } + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Update date */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + M4_RTC->YEAR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Year); + M4_RTC->MON = DEC2BCD((uint32_t)pstcRtcDateTime->u8Month); + M4_RTC->DAY = DEC2BCD((uint32_t)pstcRtcDateTime->u8Day); + } + else + { + M4_RTC->YEAR = pstcRtcDateTime->u8Year; + M4_RTC->MON = pstcRtcDateTime->u8Month; + M4_RTC->DAY = pstcRtcDateTime->u8Day; + } + M4_RTC->WEEK = pstcRtcDateTime->u8Weekday; + } + /* Update time */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour); + } + M4_RTC->MIN = DEC2BCD((uint32_t)pstcRtcDateTime->u8Minute); + M4_RTC->SEC = DEC2BCD((uint32_t)pstcRtcDateTime->u8Second); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour; + } + M4_RTC->MIN = pstcRtcDateTime->u8Minute; + M4_RTC->SEC = pstcRtcDateTime->u8Second; + } + } + /* Exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** + ******************************************************************************/ +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcDateTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Get RTC date and time registers */ + pstcRtcDateTime->u8Year = (uint8_t)(M4_RTC->YEAR); + pstcRtcDateTime->u8Month = (uint8_t)(M4_RTC->MON); + pstcRtcDateTime->u8Day = (uint8_t)(M4_RTC->DAY); + pstcRtcDateTime->u8Weekday = (uint8_t)(M4_RTC->WEEK); + pstcRtcDateTime->u8Hour = (uint8_t)(M4_RTC->HOUR); + pstcRtcDateTime->u8Minute = (uint8_t)(M4_RTC->MIN); + pstcRtcDateTime->u8Second = (uint8_t)(M4_RTC->SEC); + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if (RTC_HOUR12_AMPM_MASK == (pstcRtcDateTime->u8Hour & RTC_HOUR12_AMPM_MASK)) + { + pstcRtcDateTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcDateTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcDateTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcDateTime->u8Year = BCD2DEC(pstcRtcDateTime->u8Year); + pstcRtcDateTime->u8Month = BCD2DEC(pstcRtcDateTime->u8Month); + pstcRtcDateTime->u8Day = BCD2DEC(pstcRtcDateTime->u8Day); + pstcRtcDateTime->u8Hour = BCD2DEC(pstcRtcDateTime->u8Hour); + pstcRtcDateTime->u8Minute = BCD2DEC(pstcRtcDateTime->u8Minute); + pstcRtcDateTime->u8Second = BCD2DEC(pstcRtcDateTime->u8Second); + } + + /* exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcAlarmTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcAlarmTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcAlarmTime->u8Minute)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcAlarmTime->u8Minute))); + } + DDL_ASSERT(IS_VALID_ALARM_WEEKDAY(pstcRtcAlarmTime->u8Weekday)); + + /* Configure alarm registers */ + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour); + } + M4_RTC->ALMMIN = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Minute); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour; + } + M4_RTC->ALMMIN = pstcRtcAlarmTime->u8Minute; + } + M4_RTC->ALMWEEK = pstcRtcAlarmTime->u8Weekday; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Get RTC date and time register */ + pstcRtcAlarmTime->u8Weekday = (uint8_t)M4_RTC->ALMWEEK; + pstcRtcAlarmTime->u8Minute = (uint8_t)M4_RTC->ALMMIN; + pstcRtcAlarmTime->u8Hour = (uint8_t)M4_RTC->ALMHOUR; + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if ((pstcRtcAlarmTime->u8Hour & RTC_HOUR12_AMPM_MASK) == RTC_HOUR12_AMPM_MASK) + { + pstcRtcAlarmTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcAlarmTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcAlarmTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcAlarmTime->u8Hour = BCD2DEC(pstcRtcAlarmTime->u8Hour); + pstcRtcAlarmTime->u8Minute = BCD2DEC(pstcRtcAlarmTime->u8Minute); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC alarm function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC alarm function + ** \arg Enable Enable RTC alarm function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.ALMIE; + /* Disable alarm interrupt and clear alarm flag when START=1 and ALMIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.ALMIE = 0u; + } + M4_RTC->CR2_f.ALME = enNewSta; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR1_f.ALMFCLR = 0u; + M4_RTC->CR2_f.ALMIE = u8IntSta; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC interrupt request + ** + ** \param [in] enIrq RTC interrupt request type + ** \arg RtcIrqPeriod Period count interrupt request + ** \arg RtcIrqAlarm Alarm interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* enable/disable interrupt */ + switch (enIrq) + { + case RtcIrqPeriod: + M4_RTC->CR2_f.PRDIE = enNewSta; + break; + case RtcIrqAlarm: + M4_RTC->CR2_f.ALMIE = enNewSta; + break; + default: + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t RTC_GetAlarmFlag(void) +{ + return (en_flag_status_t)(M4_RTC->CR2_f.ALMF); +} + +/** + ******************************************************************************* + ** \brief Clear RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClearAlarmFlag(void) +{ + en_result_t enRet = Ok; + + M4_RTC->CR1_f.ALMFCLR = 0u; + + return enRet; +} + +//@} // RtcGroup + +#endif /* DDL_RTC_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c new file mode 100644 index 000000000..4a7025203 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c @@ -0,0 +1,2222 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sdioc.h" +#include "hc32f460_utility.h" + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SDIOC internal data + ** + ******************************************************************************/ +typedef struct stc_sdioc_intern_data +{ + stc_sdioc_normal_irq_cb_t stcNormalIrqCb; ///< Normal irq callback function structure + + stc_sdioc_error_irq_cb_t stcErrorIrqCb; ///< Error irq callback function structure +} stc_sdioc_intern_data_t; + +/** + ******************************************************************************* + ** \brief SDIOC instance data + ** + ******************************************************************************/ +typedef struct stc_sdioc_instance_data +{ + const M4_SDIOC_TypeDef *SDIOCx; ///< pointer to registers of an instance + + stc_sdioc_intern_data_t stcInternData; ///< module internal data of instance +} stc_sdioc_instance_data_t; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SDIOC(__SDIOCx__) \ +( (M4_SDIOC1 == (__SDIOCx__)) || \ + (M4_SDIOC2 == (__SDIOCx__))) + +/*!< Parameter valid check for SDIOC mode. */ +#define IS_VALID_SDIOC_MODE(x) \ +( (SdiocModeSD == (x)) || \ + (SdiocModeMMC == (x))) + +/*!< Parameter valid check for SDIOC Response Register. */ +#define IS_VALID_SDIOC_RESP(x) \ +( (SdiocRegResp01 == (x)) || \ + (SdiocRegResp23 == (x)) || \ + (SdiocRegResp45 == (x)) || \ + (SdiocRegResp67 == (x))) + +/*!< Parameter valid check for SDIOC bus width. */ +#define IS_VALID_SDIOC_BUS_WIDTH(x) \ +( (SdiocBusWidth1Bit == (x)) || \ + (SdiocBusWidth4Bit == (x)) || \ + (SdiocBusWidth8Bit == (x))) + +/*!< Parameter valid check for SDIOC speed mode. */ +#define IS_VALID_SDIOC_SPEED_MODE(x) \ +( (SdiocHighSpeedMode == (x)) || \ + (SdiocNormalSpeedMode == (x))) + +/*!< Parameter valid check for SDIOC Clock division. */ +#define IS_VALID_SDIOC_CLK_DIV(x) \ +( (SdiocClkDiv_1 == (x)) || \ + (SdiocClkDiv_2 == (x)) || \ + (SdiocClkDiv_4 == (x)) || \ + (SdiocClkDiv_8 == (x)) || \ + (SdiocClkDiv_16 == (x)) || \ + (SdiocClkDiv_32 == (x)) || \ + (SdiocClkDiv_64 == (x)) || \ + (SdiocClkDiv_128 == (x)) || \ + (SdiocClkDiv_256 == (x))) + +/*!< Parameter valid check for SDIOC command type. */ +#define IS_VALID_SDIOC_CMD_TYPE(x) \ +( (SdiocCmdAbort == (x)) || \ + (SdiocCmdResume == (x)) || \ + (SdiocCmdNormal == (x)) || \ + (SdiocCmdSuspend == (x))) + +/*!< Parameter valid check for SDIOC data transfer direction. */ +#define IS_VALID_SDIOC_TRANSFER_DIR(x) \ +( (SdiocTransferToCard == (x)) || \ + (SdiocTransferToHost == (x))) + +/*!< Parameter valid check for SDIOC software reset type. */ +#define IS_VALID_SDIOC_SWRESETTYPE(x) \ +( (SdiocSwResetAll == (x)) || \ + (SdiocSwResetCmdLine == (x)) || \ + (SdiocSwResetDatLine == (x))) + +/*!< Parameter valid check for SDIOC data transfer mode. */ +#define IS_VALID_SDIOC_TRANSFER_MODE(x) \ +( (SdiocTransferSingle == (x)) || \ + (SdiocTransferInfinite == (x)) || \ + (SdiocTransferMultiple == (x)) || \ + (SdiocTransferStopMultiple == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_DATA_TIMEOUT(x) \ +( (SdiocDtoSdclk_2_13 == (x)) || \ + (SdiocDtoSdclk_2_14 == (x)) || \ + (SdiocDtoSdclk_2_15 == (x)) || \ + (SdiocDtoSdclk_2_16 == (x)) || \ + (SdiocDtoSdclk_2_17 == (x)) || \ + (SdiocDtoSdclk_2_18 == (x)) || \ + (SdiocDtoSdclk_2_19 == (x)) || \ + (SdiocDtoSdclk_2_20 == (x)) || \ + (SdiocDtoSdclk_2_21 == (x)) || \ + (SdiocDtoSdclk_2_22 == (x)) || \ + (SdiocDtoSdclk_2_23 == (x)) || \ + (SdiocDtoSdclk_2_24 == (x)) || \ + (SdiocDtoSdclk_2_25 == (x)) || \ + (SdiocDtoSdclk_2_26 == (x)) || \ + (SdiocDtoSdclk_2_27 == (x))) + +/*!< Parameter valid check for SDIOC Response type name. */ +#define IS_VALID_SDIOC_RESP_TYPE_NAME(x) \ +( (SdiocCmdRspR1 == (x)) || \ + (SdiocCmdRspR1b == (x)) || \ + (SdiocCmdRspR2 == (x)) || \ + (SdiocCmdRspR3 == (x)) || \ + (SdiocCmdRspR4 == (x)) || \ + (SdiocCmdRspR5 == (x)) || \ + (SdiocCmdRspR5b == (x)) || \ + (SdiocCmdRspR6 == (x)) || \ + (SdiocCmdRspR7 == (x)) || \ + (SdiocCmdNoRsp == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_HOST_STATUS(x) \ +( (SdiocCmdPinLvl == (x)) || \ + (SdiocData0PinLvl == (x)) || \ + (SdiocData1PinLvl == (x)) || \ + (SdiocData2PinLvl == (x)) || \ + (SdiocData3PinLvl == (x)) || \ + (SdiocCardInserted == (x)) || \ + (SdiocDataLineActive == (x)) || \ + (SdiocCardStateStable == (x)) || \ + (SdiocBufferReadEnble == (x)) || \ + (SdiocBufferWriteEnble == (x)) || \ + (SdiocCardDetectPinLvl == (x)) || \ + (SdiocCommandInhibitCmd == (x)) || \ + (SdiocWriteProtectPinLvl == (x)) || \ + (SdiocCommandInhibitData == (x)) || \ + (SdiocReadTransferActive == (x)) || \ + (SdiocWriteTransferActive == (x))) + +/*!< Parameter valid check for SDIOC normal interrupt. */ +#define IS_VALID_SDIOC_NOR_INT(x) \ +( (SdiocCardInt == (x)) || \ + (SdiocErrorInt == (x)) || \ + (SdiocCardRemoval == (x)) || \ + (SdiocBlockGapEvent == (x)) || \ + (SdiocCardInsertedInt == (x)) || \ + (SdiocCommandComplete == (x)) || \ + (SdiocBufferReadReady == (x)) || \ + (SdiocBufferWriteReady == (x)) || \ + (SdiocTransferComplete == (x))) + +/*!< Parameter valid check for SDIOC error interrupt. */ +#define IS_VALID_SDIOC_ERR_INT(x) \ +( (SdiocCmdCrcErr == (x)) || \ + (SdiocDataCrcErr == (x)) || \ + (SdiocCmdIndexErr == (x)) || \ + (SdiocCmdEndBitErr == (x)) || \ + (SdiocAutoCmd12Err == (x)) || \ + (SdiocCmdTimeoutErr == (x)) || \ + (SdiocDataEndBitErr == (x)) || \ + (SdiocDataTimeoutErr == (x))) + +/*!< Parameter valid check for SDIOC auto CMD12 error status. */ +#define IS_VALID_SDIOC_AUTOCMD_ERR(x) \ +( (SdiocCmdNotIssuedErr == (x)) || \ + (SdiocAutoCmd12CrcErr == (x)) || \ + (SdiocAutoCmd12Timeout == (x)) || \ + (SdiocAutoCmd12IndexErr == (x)) || \ + (SdiocAutoCmd12EndBitErr == (x)) || \ + (SdiocAutoCmd12NotExecuted == (x))) + +/*!< Parameter valid check for SDIOC detect card signal. */ +#define IS_VALID_SDIOC_DETECT_SIG(x) \ +( (SdiocSdcdPinLevel == (x)) || \ + (SdiocCardDetectTestLevel == (x))) + +/*!< Parameter valid check for SDIOC data block count value. */ +#define IS_VALID_SDIOC_BLKCNT(x) ((x) != 0u) + +/*!< Parameter valid check for SDIOC data block size value. */ +#define IS_VALID_SDIOC_BLKSIZE(x) (!((x) & 0xF000ul)) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_SDIOC_CMD_VAL(x) (!(0xC0u & (x))) + +/*!< Parameter valid check for buffer address. */ +#define IS_VALID_TRANSFER_BUF_ALIGN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_TRANSFER_BUF_LEN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< SDIOC unit max count value. */ +#define SDIOC_UNIT_MAX_CNT (ARRAY_SZ(m_astcSdiocInstanceDataLut)) + +/*!< SDIOC default sdclk frequency. */ +#define SDIOC_SDCLK_400K (400000ul) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->ARG0))) +#define SDIOC_BUF01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->BUF0))) +#define SDIOC_RESPx(__SDIOCx__, RESP_REG) ((uint32_t)(&((__SDIOCx__)->RESP0)) + (uint32_t)(RESP_REG)) + +/* SDIOC buffer align size */ +#define SDIOC_BUF_ALIGN_SIZE (4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32SdiocClkFreq); +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get SDIOC clock division. + ** + ** \param [in] u32Exclk Exclk frequency + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** \retval SdiocClkDiv_256 EXCLK/256 + ** + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32ClkFreq) +{ + uint32_t u32SdClkDiv = 0ul; + en_sdioc_clk_div_t enClockDiv = SdiocClkDiv_256; + + if(0ul != u32ClkFreq) + { + u32SdClkDiv = u32Exclk / u32ClkFreq; + if (u32Exclk % u32ClkFreq) + { + u32SdClkDiv++; + } + + if ((128ul < u32SdClkDiv) && (u32SdClkDiv <= 256ul)) + { + enClockDiv = SdiocClkDiv_256; + } + else if ((64ul < u32SdClkDiv) && (u32SdClkDiv <= 128ul)) + { + enClockDiv = SdiocClkDiv_128; + } + else if ((32ul < u32SdClkDiv) && (u32SdClkDiv <= 64ul)) + { + enClockDiv = SdiocClkDiv_64; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((8ul < u32SdClkDiv) && (u32SdClkDiv <= 16ul)) + { + enClockDiv = SdiocClkDiv_16; + } + else if ((4ul < u32SdClkDiv) && (u32SdClkDiv <= 8ul)) + { + enClockDiv = SdiocClkDiv_8; + } + else if ((2ul < u32SdClkDiv) && (u32SdClkDiv <= 4ul)) + { + enClockDiv = SdiocClkDiv_4; + } + else if ((1ul < u32SdClkDiv) && (u32SdClkDiv <= 2ul)) + { + enClockDiv = SdiocClkDiv_2; + } + else + { + enClockDiv = SdiocClkDiv_1; + } + } + + return enClockDiv; +} + +/** + ******************************************************************************* + ** \brief Return the internal data for a certain SDIOC instance. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx) +{ + uint8_t i; + stc_sdioc_intern_data_t *pstcInternData = NULL; + static stc_sdioc_instance_data_t m_astcSdiocInstanceDataLut[2]; + + m_astcSdiocInstanceDataLut[0].SDIOCx = M4_SDIOC1; + m_astcSdiocInstanceDataLut[1].SDIOCx = M4_SDIOC2; + + if (NULL != SDIOCx) + { + for (i = 0u; i < SDIOC_UNIT_MAX_CNT; i++) + { + if (SDIOCx == m_astcSdiocInstanceDataLut[i].SDIOCx) + { + pstcInternData = &m_astcSdiocInstanceDataLut[i].stcInternData; + break; + } + } + } + + return pstcInternData; +} + +/** + ******************************************************************************* + ** \brief SDIOC instance interrupt service routine + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval None + ** + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx) +{ + stc_sdioc_intern_data_t *pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + + /* Check for NULL pointer */ + if (NULL != pstcSdiocInternData) + { + /**************** Normal interrupt handler ****************/ + if (1u == SDIOCx->NORINTST_f.CC) /* Command complete */ + { + SDIOCx->NORINTST_f.CC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.TC) /* Transfer complete */ + { + SDIOCx->NORINTST_f.TC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BGE) /* Block gap event */ + { + SDIOCx->NORINTST_f.BGE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BWR) /* Buffer write ready */ + { + SDIOCx->NORINTST_f.BWR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BRR) /* Buffer read ready */ + { + SDIOCx->NORINTST_f.BRR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CIST) /* Card insertion */ + { + SDIOCx->NORINTST_f.CIST = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CRM) /* Card removal */ + { + SDIOCx->NORINTST_f.CRM = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CINT) /* Card interrupt */ + { + SDIOCx->NORINTST_f.CINT = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb(); + } + } + + /**************** Error interrupt handler ****************/ + if (1u == SDIOCx->ERRINTST_f.CTOE) /* Command timeout error */ + { + SDIOCx->ERRINTST_f.CTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CCE) /* Command CRC error */ + { + SDIOCx->ERRINTST_f.CCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CEBE) /* Command end bit error */ + { + SDIOCx->ERRINTST_f.CEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CIE) /* Command index error */ + { + SDIOCx->ERRINTST_f.CIE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DTOE) /* Data timeout error */ + { + SDIOCx->ERRINTST_f.DTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DEBE) /* Data end bit error */ + { + SDIOCx->ERRINTST_f.DEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DCE) /* Data CRC error */ + { + SDIOCx->ERRINTST_f.DCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.ACE) /* Auto CMD12 error */ + { + SDIOCx->ERRINTST_f.ACE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb(); + } + } + } +} + +/** + ******************************************************************************* + ** \brief Initializes a SDIOC. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcInitCfg Pointer to SDIOC configure structure + ** \arg This parameter detail refer @ref stc_sdioc_init_t + ** + ** \retval Ok SDIOC initialized normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg) +{ + __IO uint32_t i = 0ul; + uint32_t u32Exclk = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.FS = SdiocGetClkDiv(u32Exclk, SdiocClk400K); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + SDIOCx->CLKCON_f.ICE = (uint16_t)1u; + SDIOCx->PWRCON_f.PWON = (uint8_t)1u; /* Power on */ + + /* Enable all status */ + SDIOCx->ERRINTST = (uint16_t)0x017Fu; /* Clear Error interrupt status */ + SDIOCx->ERRINTSTEN = (uint16_t)0x017Fu; /* Enable Error interrupt status */ + SDIOCx->NORINTST = (uint16_t)0x00F7u; /* Clear Normal interrupt status */ + SDIOCx->NORINTSTEN = (uint16_t)0x01F7u; /* Enable Normal interrupt status */ + + /* Enable normal interrupt signal */ + if (NULL != pstcInitCfg) + { + if (NULL != pstcInitCfg->pstcNormalIrqEn) + { + SDIOCx->NORINTSGEN = pstcInitCfg->pstcNormalIrqEn->u16NormalIntsgEn; + } + + /* Set normal interrupt callback functions */ + if (NULL != pstcInitCfg->pstcNormalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCommandCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnTransferCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBlockGapIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferWriteReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferReadReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardInsertIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardRemovalIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardIrqCb; + } + + /* Enable error interrupt signal */ + if (NULL != pstcInitCfg->pstcErrorIrqEn) + { + SDIOCx->ERRINTSGEN = pstcInitCfg->pstcErrorIrqEn->u16ErrorIntsgEn; + } + + /* Set error interrupt callback functions */ + if (NULL != pstcInitCfg->pstcErrorIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdIndexErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnAutoCmdErrIrqCb; + } + } + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified SDIOC unit. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorTimeout SDIOCx reset timeout. + ** \retval ErrorInvalidParameter SDIOCx is invalid. + ** + ******************************************************************************/ +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Set normal interrupt callback functions */ + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = NULL; + + /* Set error interrupt callback functions */ + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = NULL; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + * @brief Set SDIOC mode. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enMode SDIOCx mode + * @arg SdiocModeSD: SD mode + * @arg SdiocModeMMC: MMC mode + */ +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_MODE(enMode)); + + if (M4_SDIOC1 == SDIOCx) + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC1 = (uint32_t)enMode; + } + else + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC2 = (uint32_t)enMode; + } +} + +/** + ******************************************************************************* + ** \brief Send SD command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcCmdCfg Pointer to command transfer configuration structure. + ** \arg This parameter detail refer @ref stc_sdioc_cmd_cfg_t + ** + ** \retval Ok Command sent normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcCmdCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg) +{ + uint32_t u32Addr; + stc_sdioc_cmd_field_t stcCmdField; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for NULL pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcCmdCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CMD_VAL(pstcCmdCfg->u8CmdIndex)); + DDL_ASSERT(IS_VALID_SDIOC_CMD_TYPE(pstcCmdCfg->enCmdType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCmdCfg->enDataPresentEnable)); + DDL_ASSERT(IS_VALID_SDIOC_RESP_TYPE_NAME(pstcCmdCfg->enRspIndex)); + + enRet = Ok; + switch (pstcCmdCfg->enRspIndex) + { + case SdiocCmdNoRsp: + stcCmdField.RESTYP = SdiocResponseNoneBit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR2: + stcCmdField.RESTYP = SdiocResponse136Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR3: + case SdiocCmdRspR4: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR1: + case SdiocCmdRspR5: + case SdiocCmdRspR6: + case SdiocCmdRspR7: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + case SdiocCmdRspR1b: + case SdiocCmdRspR5b: + stcCmdField.RESTYP = SdiocResponse48BitCheckBusy; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcCmdField.RESERVED2 = (uint16_t)0u; + stcCmdField.TYP = (uint16_t)pstcCmdCfg->enCmdType; + stcCmdField.IDX = (uint16_t)pstcCmdCfg->u8CmdIndex; + stcCmdField.DAT = (uint16_t)(pstcCmdCfg->enDataPresentEnable); + + u32Addr = SDIOC_ARG01(SDIOCx); + *(__IO uint32_t *)u32Addr = pstcCmdCfg->u32Argument; + + u32Addr = (uint32_t)&stcCmdField; + SDIOCx->CMD = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the response received from the card for the last command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enRespReg Response Specifies the SDIOC response register. + ** \arg SdiocRegResp01 Response0 and Response1 Register + ** \arg SdiocRegResp23 Response2 and Response3 Register + ** \arg SdiocRegResp45 Response4 and Response5 Register + ** \arg SdiocRegResp67 Response6 and Response7 Register + ** + ** \retval The Corresponding response register value + ** + ******************************************************************************/ +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_RESP(enRespReg)); + + return *(__IO uint32_t *)SDIOC_RESPx(SDIOCx, enRespReg) ; +} + +/** + ******************************************************************************* + ** \brief Read data from SDIOCx data buffer + ** + ** This function reads 32-bit data from data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will store SDIOC_BUFFER data + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is read normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu32Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul;; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = *SDIO_BUF_REG; + au8Data[i++] = (uint8_t)((u32Temp >> 0ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 8ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 16ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 24ul) & 0x000000FF); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write data to SDIOCx data buffer + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will be wrote to SDIOC_BUFFER + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is written normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu8Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = (((uint32_t)au8Data[i++]) << 0ul) & 0x000000FFul; + u32Temp += (((uint32_t)au8Data[i++]) << 8ul) & 0x0000FF00ul; + u32Temp += (((uint32_t)au8Data[i++]) << 16ul) & 0x00FF0000ul; + u32Temp += (((uint32_t)au8Data[i++]) << 24ul) & 0xFF000000ul; + + *SDIO_BUF_REG = u32Temp; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure SDIOCx data parameters + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcDataCfg Pointer to SDIOC data transfer configuration structure + ** \arg This parameter detail refer @ref stc_sdioc_data_cfg_t + ** + ** \retval Ok configure normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcDataCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg) +{ + uint16_t u16BlkCnt = (uint16_t)0; + uint32_t u32Addr; + stc_sdioc_transmode_field_t stcTransModeField = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pstcDataCfg pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcDataCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BLKCNT(pstcDataCfg->u16BlkCnt)); + DDL_ASSERT(IS_VALID_SDIOC_BLKSIZE(pstcDataCfg->u16BlkSize)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDataCfg->enAutoCmd12Enable)); + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(pstcDataCfg->enDataTimeOut)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_DIR(pstcDataCfg->enTransferDir)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_MODE(pstcDataCfg->enTransferMode)); + + enRet = Ok; + + switch (pstcDataCfg->enTransferMode) + { + case SdiocTransferSingle: + stcTransModeField.MULB = 0u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferInfinite: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferMultiple: + u16BlkCnt = pstcDataCfg->u16BlkCnt; + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + case SdiocTransferStopMultiple: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcTransModeField.RESERVED0 = (uint16_t)0u; + stcTransModeField.DDIR = (uint16_t)(pstcDataCfg->enTransferDir); + stcTransModeField.ATCEN = (uint16_t)(pstcDataCfg->enAutoCmd12Enable); + + /* Set the SDIOC Data Transfer Timeout value */ + SDIOCx->TOUTCON = (uint8_t)(pstcDataCfg->enDataTimeOut); + /* Set the SDIOC Block Count value */ + SDIOCx->BLKCNT = u16BlkCnt; + /* Set the SDIOC Block Size value */ + SDIOCx->BLKSIZE = pstcDataCfg->u16BlkSize; + /* Set the SDIOC Data Transfer Mode */ + u32Addr = (uint32_t)&stcTransModeField; + SDIOCx->TRANSMODE = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable SDCLK output + ** + ** SD host drives SDCLK line. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd The SDCLK functional state command + ** \arg Enable Enable SDCLK function + ** \arg Disable Disable SDCLK function + ** + ** \retval Ok SDCLK output of SDIOCx enabled normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + SDIOCx->CLKCON_f.CE = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the clock division of SD clock + ** + ** This function changes the SD clock division. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enClkDiv SDIOC clock division value + ** \arg SdiocClkDiv_1 EXCLK/1 + ** \arg SdiocClkDiv_2 EXCLK/2 + ** \arg SdiocClkDiv_4 EXCLK/4 + ** \arg SdiocClkDiv_8 EXCLK/8 + ** \arg SdiocClkDiv_16 EXCLK/16 + ** \arg SdiocClkDiv_32 EXCLK/32 + ** \arg SdiocClkDiv_64 EXCLK/64 + ** \arg SdiocClkDiv_128 EXCLK/128 + ** \arg SdiocClkDiv_256 EXCLK/256 + ** + ** \retval Ok SDIOC clock division is changed normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CLK_DIV(enClkDiv)); + + /* Set clock division */ + SDIOCx->CLKCON_f.FS = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** + ******************************************************************************/ +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((en_sdioc_clk_div_t)SDIOCx->CLKCON_f.FS); +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq) +{ + uint32_t u32Exclk = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.CE = (uint16_t)0u; + SDIOCx->CLKCON_f.FS = (uint16_t)SdiocGetClkDiv(u32Exclk, u32ClkFreq); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the bus width of SD Bus + ** + ** This function changes the SD bus width. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enBusWidth Bus width + ** \arg SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \arg SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \arg SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ** \retval Ok Bus width is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enBusWidth is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BUS_WIDTH(enBusWidth)); + + enRet = Ok; + + switch (enBusWidth) + { + case SdiocBusWidth1Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 0u; + break; + case SdiocBusWidth4Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 1u; + break; + case SdiocBusWidth8Bit: + SDIOCx->HOSTCON_f.EXDW = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus width of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \retval SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \retval SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ******************************************************************************/ +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx) +{ + en_sdioc_bus_width_t enBusWidth = SdiocBusWidth4Bit; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + if (0u == SDIOCx->HOSTCON_f.EXDW) + { + if (0u == SDIOCx->HOSTCON_f.DW) + { + enBusWidth = SdiocBusWidth1Bit; + } + } + else + { + enBusWidth = SdiocBusWidth8Bit; + } + + return enBusWidth; +} + +/** + ******************************************************************************* + ** \brief Set the bus speed mode of SD Bus + ** + ** This function changes the SD bus speed mode. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSpeedMode Speed mode + ** \arg SdiocHighSpeedMode High speed mode + ** \arg SdiocNormalSpeedMode Normal speed mode + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SPEED_MODE(enSpeedMode)); + + /* Set high speed mode */ + SDIOCx->HOSTCON_f.HSEN = ((SdiocHighSpeedMode == enSpeedMode) ? 1u : 0u); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus speed mode of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocHighSpeedMode High speed mode + ** \retval SdiocNormalSpeedMode Normal speed mode + ** + ******************************************************************************/ +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((SDIOCx->HOSTCON_f.HSEN) ? SdiocHighSpeedMode : SdiocNormalSpeedMode); +} + +/** + ******************************************************************************* + ** \brief Set data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enTimeout Data timeout count value + ** \arg SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \arg SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \arg SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \arg SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \arg SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \arg SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \arg SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \arg SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \arg SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \arg SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \arg SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \arg SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \arg SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \arg SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \arg SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(enTimeout)); + + /* Set data timeout */ + SDIOCx->TOUTCON_f.DTO = (uint8_t)enTimeout; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \retval SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \retval SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \retval SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \retval SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \retval SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \retval SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \retval SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \retval SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \retval SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \retval SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \retval SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \retval SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \retval SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \retval SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ******************************************************************************/ +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_sdioc_data_timeout_t)(SDIOCx->TOUTCON_f.DTO); +} + +/** + ******************************************************************************* + ** \brief Set the card detect signal + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enDetectSignal Card detect signal + ** \arg SdiocSdcdPinLevel SDCD# is selected (for normal use) + ** \arg SdiocCardDetectTestLevel The Card Detect Test Level is selected(for test purpose) + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DETECT_SIG(enDetectSignal)); + SDIOCx->HOSTCON_f.CDSS = (uint8_t)enDetectSignal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get card inserted or not. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Set Card Inserted + ** \retval Reset No Card + ** + ** \note This bit is enabled while the Card Detect Signal Selection is set to 1 + ** and it indicates card inserted or not. + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_flag_status_t)(SDIOCx->HOSTCON_f.CDTL); +} + +/** + ******************************************************************************* + ** \brief Power on SD bus power + ** + ** This function starts power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power on normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Power off SD bus power + ** + ** This function stops power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power off normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Stop At Block Gap Request during block gap + ** + ** This function is used to stop data trasnfer of multi-block transfer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Stop At Block Gap Request functional state + ** \arg Enable Enable the function of Stop At Block Gap Request + ** \arg Disable Disable the function of Stop At Block Gap Request + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.SABGR = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Restart data transfer + ** + ** This function is used to restart data transfer when transfer is pending + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->BLKGPCON_f.CR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Read Wait Control + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Read Wait Control functional state + ** \arg Enable Enable the Read Wait Control function + ** \arg Disable Disable the Read Wait Control function + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.RWC = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Interrupt At Block Gap + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Interrupt At Block Gap functional state + ** \arg Enable Enable the function of Interrupt At Block Gap + ** \arg Disable Disable the function of Interrupt At Block Gap + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.IABG = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Generate software reset to SD card + ** + ** This function generates software reset all command to SD card + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSwResetType Software reset type + ** \arg SdiocSwResetAll This reset affects the entire Host Controller except for the card detection circuit. + ** \arg SdiocSwResetCmdLine Only part of command circuit is reset. + ** \arg SdiocSwResetDataLine Only part of data circuit is reset. + ** + ** \retval Ok Software reset is done normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enSwResetType is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SWRESETTYPE(enSwResetType)); + + enRet = Ok; + switch (enSwResetType) + { + case SdiocSwResetAll: + SDIOCx->SFTRST_f.RSTA = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetCmdLine: + SDIOCx->SFTRST_f.RSTC = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTC) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetDatLine: + SDIOCx->SFTRST_f.RSTD = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTD) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (i > u32Cnt) + { + enRet = ErrorTimeout; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of SDIOC host controller + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enHostStatus SDIOC host status + ** \arg SdiocCommandInhibitCmd Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + ** \arg SdiocCommandInhibitData Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + ** \arg SdiocDataLineActive 1: DAT Line Active; 0: DAT Line Inactive + ** \arg SdiocWriteTransferActive Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocReadTransferActive Read Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocBufferWriteEnble 1: Write enable; 0: Write Disable + ** \arg SdiocBufferReadEnble 1: Read enable; 0: Read Disable + ** \arg SdiocCardInserted 1: Card Inserted; 0: Reset or Debouncing or No Card + ** \arg SdiocCardStateStable 1: No Card or Inserted; 0: Reset or Debouncing + ** \arg SdiocCardDetectPinLvl 1: Card present; 0: No card present + ** \arg SdiocWriteProtectPinLvl 1: Write enabled; 0: Write protected + ** \arg SdiocData0PinLvl 1: DAT0 line signal level high; 0: DAT0 line signal level low + ** \arg SdiocData1PinLvl 1: DAT1 line signal level high; 0: DAT1 line signal level low + ** \arg SdiocData2PinLvl 1: DAT2 line signal level high; 0: DAT2 line signal level low + ** \arg SdiocData3PinLvl 1: DAT3 line signal level high; 0: DAT3 line signal level low + ** \arg SdiocCmdPinLvl 1: CMD line signal level high; 0: CMD line signal level low + ** + ** \retval Set The specified status is set + ** \retval Reset The specified status is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_HOST_STATUS(enHostStatus)); + + return ((SDIOCx->PSTAT & ((uint32_t)enHostStatus)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the specified signal of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt signal functional state + ** \arg Enable Enable the specified signal of SD normal interrupt + ** \arg Disable Disable the specified signal of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSGEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSGEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt status functional state + ** \arg Enable Enable the specified status of SD normal interrupt + ** \arg Disable Disable the specified status of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSTEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSTEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + return ((SDIOCx->NORINTST & ((uint16_t)enNorInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + SDIOCx->NORINTST = (uint16_t)enNorInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the signal of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt signal functional state + ** \arg Enable Enable the specified signal of SD error interrupt + ** \arg Disable Disable the specified signal of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSGEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSGEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt status functional state + ** \arg Enable Enable the specified status of SD error interrupt + ** \arg Disable Disable the specified status of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSTEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSTEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + + return ((SDIOCx->ERRINTST & ((uint16_t)enErrInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->ERRINTST = (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Force the specified error interrupt flag + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->FEE |= (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error status selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Set The specified status flag is set + ** \retval Reset The specified status flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + + return ((SDIOCx->ATCERRST & ((uint16_t)enAutoCmdErr)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Force the specified auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + SDIOCx->FEA |= (uint16_t)enAutoCmdErr; + enRet = Ok; + } + + return enRet; +} + +//@} // SdiocGroup + +#endif /* DDL_SDIOC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c new file mode 100644 index 000000000..8d248459f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c @@ -0,0 +1,1132 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.c + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_spi.h" +#include "hc32f460_utility.h" + +#if (DDL_SPI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SpiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for SPI unit */ +#define IS_VALID_SPI_UNIT(x) \ +( (M4_SPI1 == (x)) || \ + (M4_SPI2 == (x)) || \ + (M4_SPI3 == (x)) || \ + (M4_SPI4 == (x))) + +/*!< Parameter valid check for SS setup delay option */ +#define IS_VALID_SS_SETUP_DELAY_OPTION(x) \ +( (SpiSsSetupDelayTypicalSck1 == (x)) || \ + (SpiSsSetupDelayCustomValue == (x))) + +/*!< Parameter valid check for SS setup delay time */ +#define IS_VALID_SS_SETUP_DELAY_TIME(x) \ +( (SpiSsSetupDelaySck1 == (x)) || \ + (SpiSsSetupDelaySck2 == (x)) || \ + (SpiSsSetupDelaySck3 == (x)) || \ + (SpiSsSetupDelaySck4 == (x)) || \ + (SpiSsSetupDelaySck5 == (x)) || \ + (SpiSsSetupDelaySck6 == (x)) || \ + (SpiSsSetupDelaySck7 == (x)) || \ + (SpiSsSetupDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay time */ +#define IS_VALID_SS_HOLD_DELAY_TIME(x) \ +( (SpiSsHoldDelaySck1 == (x)) || \ + (SpiSsHoldDelaySck2 == (x)) || \ + (SpiSsHoldDelaySck3 == (x)) || \ + (SpiSsHoldDelaySck4 == (x)) || \ + (SpiSsHoldDelaySck5 == (x)) || \ + (SpiSsHoldDelaySck6 == (x)) || \ + (SpiSsHoldDelaySck7 == (x)) || \ + (SpiSsHoldDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay option */ +#define IS_VALID_SS_HOLD_DELAY_OPTION(x) \ +( (SpiSsHoldDelayTypicalSck1 == (x)) || \ + (SpiSsHoldDelayCustomValue == (x))) + +/*!< Parameter valid check for SS interval time option */ +#define IS_VALID_SS_INTERVAL_TIME_OPTION(x) \ +( (SpiSsIntervalTypicalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalCustomValue == (x))) + +/*!< Parameter valid check for SS interval time */ +#define IS_VALID_SS_INTERVAL_TIME(x) \ +( (SpiSsIntervalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalSck2PlusPck2 == (x)) || \ + (SpiSsIntervalSck3PlusPck2 == (x)) || \ + (SpiSsIntervalSck4PlusPck2 == (x)) || \ + (SpiSsIntervalSck5PlusPck2 == (x)) || \ + (SpiSsIntervalSck6PlusPck2 == (x)) || \ + (SpiSsIntervalSck7PlusPck2 == (x)) || \ + (SpiSsIntervalSck8PlusPck2 == (x))) + +/*!< Parameter valid check for SS valid channel select */ +#define IS_VALID_SS_VALID_CHANNEL(x) \ +( (SpiSsValidChannel0 == (x)) || \ + (SpiSsValidChannel1 == (x)) || \ + (SpiSsValidChannel2 == (x)) || \ + (SpiSsValidChannel3 == (x))) + +/*!< Parameter valid check for SS polarity */ +#define IS_VALID_SS_POLARITY(x) \ +( (SpiSsLowValid == (x)) || \ + (SpiSsHighValid == (x))) + +/*!< Parameter valid check for read data register object */ +#define IS_VALID_READ_DATA_REG_OBJECT(x) \ +( (SpiReadReceiverBuffer == (x)) || \ + (SpiReadSendBuffer == (x))) + +/*!< Parameter valid check for SCK polarity */ +#define IS_VALID_SCK_POLARITY(x) \ +( (SpiSckIdleLevelLow == (x)) || \ + (SpiSckIdleLevelHigh == (x))) + +/*!< Parameter valid check for SCK phase */ +#define IS_VALID_SCK_PHASE(x) \ +( (SpiSckOddSampleEvenChange == (x)) || \ + (SpiSckOddChangeEvenSample == (x))) + +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( (SpiClkDiv2 == (x)) || \ + (SpiClkDiv4 == (x)) || \ + (SpiClkDiv8 == (x)) || \ + (SpiClkDiv16 == (x)) || \ + (SpiClkDiv32 == (x)) || \ + (SpiClkDiv64 == (x)) || \ + (SpiClkDiv128 == (x)) || \ + (SpiClkDiv256 == (x))) + +/*!< Parameter valid check for data length */ +#define IS_VALID_DATA_LENGTH(x) \ +( (SpiDataLengthBit4 == (x)) || \ + (SpiDataLengthBit5 == (x)) || \ + (SpiDataLengthBit6 == (x)) || \ + (SpiDataLengthBit7 == (x)) || \ + (SpiDataLengthBit8 == (x)) || \ + (SpiDataLengthBit9 == (x)) || \ + (SpiDataLengthBit10 == (x)) || \ + (SpiDataLengthBit11 == (x)) || \ + (SpiDataLengthBit12 == (x)) || \ + (SpiDataLengthBit13 == (x)) || \ + (SpiDataLengthBit14 == (x)) || \ + (SpiDataLengthBit15 == (x)) || \ + (SpiDataLengthBit16 == (x)) || \ + (SpiDataLengthBit20 == (x)) || \ + (SpiDataLengthBit24 == (x)) || \ + (SpiDataLengthBit32 == (x))) + +/*!< Parameter valid check for first bit position */ +#define IS_VALID_FIRST_BIT_POSITION(x) \ +( (SpiFirstBitPositionMSB == (x)) || \ + (SpiFirstBitPositionLSB == (x))) + +/*!< Parameter valid check for frame number */ +#define IS_VALID_FRAME_NUMBER(x) \ +( (SpiFrameNumber1 == (x)) || \ + (SpiFrameNumber2 == (x)) || \ + (SpiFrameNumber3 == (x)) || \ + (SpiFrameNumber4 == (x))) + +/*!< Parameter valid check for work mode */ +#define IS_VALID_WORK_MODE(x) \ +( (SpiWorkMode4Line == (x)) || \ + (SpiWorkMode3Line == (x))) + +/*!< Parameter valid check for transmission mode */ +#define IS_VALID_COMM_MODE(x) \ +( (SpiTransFullDuplex == (x)) || \ + (SpiTransOnlySend == (x))) + +/*!< Parameter valid check for master slave mode */ +#define IS_VALID_MASTER_SLAVE_MODE(x) \ +( (SpiModeSlave == (x)) || \ + (SpiModeMaster == (x))) + +/*!< Parameter valid check for parity mode */ +#define IS_VALID_PARITY_MODE(x) \ +( (SpiParityEven == (x)) || \ + (SpiParityOdd == (x))) + +/*!< Parameter valid check for SS channel */ +#define IS_VALID_SS_CHANNEL(x) \ +( (SpiSsChannel0 == (x)) || \ + (SpiSsChannel1 == (x)) || \ + (SpiSsChannel2 == (x)) || \ + (SpiSsChannel3 == (x))) + +/*!< Parameter valid check for irq type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (SpiIrqIdle == (x)) || \ + (SpiIrqReceive == (x)) || \ + (SpiIrqSend == (x)) || \ + (SpiIrqError == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SpiFlagReceiveBufferFull == (x)) || \ + (SpiFlagSendBufferEmpty == (x)) || \ + (SpiFlagUnderloadError == (x)) || \ + (SpiFlagParityError == (x)) || \ + (SpiFlagModeFaultError == (x)) || \ + (SpiFlagSpiIdle == (x)) || \ + (SpiFlagOverloadError == (x))) + +/*!< SPI registers reset value */ +#define SPI_REG_DR_RESET_VALUE 0x00000000ul +#define SPI_REG_CR1_RESET_VALUE 0x00000000ul +#define SPI_REG_CFG1_RESET_VALUE 0x00000010ul +#define SPI_REG_SR_RESET_VALUE 0x00000020ul +#define SPI_REG_CFG2_RESET_VALUE 0x0000031Dul + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t regTemp = 0ul; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + regTemp = SPIx->SR; + if (SPI_REG_SR_RESET_VALUE != regTemp) + { + SPIx->SR = SPI_REG_SR_RESET_VALUE; + } + SPIx->CR1 = SPI_REG_CR1_RESET_VALUE; + SPIx->DR = SPI_REG_DR_RESET_VALUE; + SPIx->CFG1 = SPI_REG_CFG1_RESET_VALUE; + SPIx->CFG2 = SPI_REG_CFG2_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] pstcSpiInitCfg Pointer to SPI init configuration + ** \arg See the struct #stc_spi_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** - pstcSpiInitCfg == NULL + ** + ******************************************************************************/ +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if((IS_VALID_SPI_UNIT(SPIx)) && (NULL != pstcSpiInitCfg)) + { + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption)); + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime)); + DDL_ASSERT(IS_VALID_SS_VALID_CHANNEL(pstcSpiInitCfg->stcSsConfig.enSsValidBit)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs0Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs1Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs2Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs3Polarity)); + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(pstcSpiInitCfg->enReadBufferObject)); + DDL_ASSERT(IS_VALID_SCK_POLARITY(pstcSpiInitCfg->enSckPolarity)); + DDL_ASSERT(IS_VALID_SCK_PHASE(pstcSpiInitCfg->enSckPhase)); + DDL_ASSERT(IS_VALID_CLK_DIV(pstcSpiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_DATA_LENGTH(pstcSpiInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(pstcSpiInitCfg->enFirstBitPosition)); + DDL_ASSERT(IS_VALID_FRAME_NUMBER(pstcSpiInitCfg->enFrameNumber)); + DDL_ASSERT(IS_VALID_WORK_MODE(pstcSpiInitCfg->enWorkMode)); + DDL_ASSERT(IS_VALID_COMM_MODE(pstcSpiInitCfg->enTransMode)); + DDL_ASSERT(IS_VALID_MASTER_SLAVE_MODE(pstcSpiInitCfg->enMasterSlaveMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enCommAutoSuspendEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enModeFaultErrorDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParitySelfDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParityEn)); + DDL_ASSERT(IS_VALID_PARITY_MODE(pstcSpiInitCfg->enParity)); + + /* Master mode */ + if (SpiModeMaster == pstcSpiInitCfg->enMasterSlaveMode) + { + SPIx->CFG2_f.MSSIE = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption; + SPIx->CFG2_f.MSSDLE = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption; + SPIx->CFG2_f.MIDIE = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption; + SPIx->CFG1_f.MSSI = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime; + SPIx->CFG1_f.MSSDL = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime; + SPIx->CFG1_f.MIDI = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime; + } + else + { + SPIx->CFG2_f.MSSIE = SpiSsSetupDelayTypicalSck1; + SPIx->CFG2_f.MSSDLE = SpiSsHoldDelayTypicalSck1; + SPIx->CFG2_f.MIDIE = SpiSsIntervalTypicalSck1PlusPck2; + SPIx->CFG1_f.MSSI = SpiSsSetupDelaySck1; + SPIx->CFG1_f.MSSDL = SpiSsHoldDelaySck1; + SPIx->CFG1_f.MIDI = SpiSsIntervalSck1PlusPck2; + } + + /* 4 lines spi mode */ + if (SpiWorkMode4Line == pstcSpiInitCfg->enWorkMode) + { + SPIx->CFG2_f.SSA = pstcSpiInitCfg->stcSsConfig.enSsValidBit; + SPIx->CFG1_f.SS0PV = pstcSpiInitCfg->stcSsConfig.enSs0Polarity; + SPIx->CFG1_f.SS1PV = pstcSpiInitCfg->stcSsConfig.enSs1Polarity; + SPIx->CFG1_f.SS2PV = pstcSpiInitCfg->stcSsConfig.enSs2Polarity; + SPIx->CFG1_f.SS3PV = pstcSpiInitCfg->stcSsConfig.enSs3Polarity; + } + else + { + SPIx->CFG2_f.SSA = SpiSsValidChannel0; + SPIx->CFG1_f.SS0PV = SpiSsLowValid; + SPIx->CFG1_f.SS1PV = SpiSsLowValid; + SPIx->CFG1_f.SS2PV = SpiSsLowValid; + SPIx->CFG1_f.SS3PV = SpiSsLowValid; + } + + /* Configure communication config register 1 */ + SPIx->CFG1_f.SPRDTD = pstcSpiInitCfg->enReadBufferObject; + SPIx->CFG1_f.FTHLV = pstcSpiInitCfg->enFrameNumber; + + /* Configure communication config register 2 */ + SPIx->CFG2_f.LSBF = pstcSpiInitCfg->enFirstBitPosition; + SPIx->CFG2_f.DSIZE = pstcSpiInitCfg->enDataLength; + SPIx->CFG2_f.MBR = pstcSpiInitCfg->enClkDiv; + SPIx->CFG2_f.CPOL = pstcSpiInitCfg->enSckPolarity; + SPIx->CFG2_f.CPHA = pstcSpiInitCfg->enSckPhase; + + /* Configure control register */ + SPIx->CR1_f.SPIMDS = pstcSpiInitCfg->enWorkMode; + SPIx->CR1_f.TXMDS = pstcSpiInitCfg->enTransMode; + SPIx->CR1_f.MSTR = pstcSpiInitCfg->enMasterSlaveMode; + SPIx->CR1_f.CSUSPE = pstcSpiInitCfg->enCommAutoSuspendEn; + SPIx->CR1_f.MODFE = pstcSpiInitCfg->enModeFaultErrorDetectEn; + SPIx->CR1_f.PATE = pstcSpiInitCfg->enParitySelfDetectEn; + SPIx->CR1_f.PAE = pstcSpiInitCfg->enParityEn; + SPIx->CR1_f.PAOE = pstcSpiInitCfg->enParity; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI general loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable general loopback + ** \arg Enable Enable general loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK2 = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI reverse loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable reverse loopback + ** \arg Enable Enable reverse loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI working + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable SPI working + ** \arg Enable Enable SPI working + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPE = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u8Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u16Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u32Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI receive 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint8_t Receive data value + ** + ******************************************************************************/ +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint8_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint16_t Receive data value + ** + ******************************************************************************/ +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint16_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint32_t Receive data value + ** + ******************************************************************************/ +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint32_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI set SS channel valid level polarity + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \param [in] enPolarity SS channel valid level polarity + ** \arg SpiSsLowValid SS0~3 signal low level valid + ** \arg SpiSsHighValid SS0~3 signal high level valid + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SS_POLARITY(enPolarity)); + + switch (enChannel) + { + case SpiSsChannel0: + SPIx->CFG1_f.SS0PV = enPolarity; + break; + case SpiSsChannel1: + SPIx->CFG1_f.SS1PV = enPolarity; + break; + case SpiSsChannel2: + SPIx->CFG1_f.SS2PV = enPolarity; + break; + case SpiSsChannel3: + SPIx->CFG1_f.SS3PV = enPolarity; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set SS valid channel + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + + SPIx->CFG2_f.SSA = enChannel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set read data register object + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enObject Read data register object + ** \arg SpiReadReceiverBuffer Read receive buffer + ** \arg SpiReadSendBuffer Read send buffer(must be read when TDEF=1) + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(enObject)); + + SPIx->CFG1_f.SPRDTD = enObject; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set frame number + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFrameNum Once read or write frame number + ** \arg SpiFrameNumber1 1 frame data + ** \arg SpiFrameNumber2 2 frame data + ** \arg SpiFrameNumber3 3 frame data + ** \arg SpiFrameNumber4 4 frame data + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FRAME_NUMBER(enFrameNum)); + + SPIx->CFG1_f.FTHLV = enFrameNum; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set data length + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enDataLength Read or write data length + ** \arg SpiDataLengthBit4 4 bits + ** \arg SpiDataLengthBit5 5 bits + ** \arg SpiDataLengthBit6 6 bits + ** \arg SpiDataLengthBit7 7 bits + ** \arg SpiDataLengthBit8 8 bits + ** \arg SpiDataLengthBit9 9 bits + ** \arg SpiDataLengthBit10 10 bits + ** \arg SpiDataLengthBit11 11 bits + ** \arg SpiDataLengthBit12 12 bits + ** \arg SpiDataLengthBit13 13 bits + ** \arg SpiDataLengthBit14 14 bits + ** \arg SpiDataLengthBit15 15 bits + ** \arg SpiDataLengthBit16 16 bits + ** \arg SpiDataLengthBit20 20 bits + ** \arg SpiDataLengthBit24 24 bits + ** \arg SpiDataLengthBit32 32 bits + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_DATA_LENGTH(enDataLength)); + + SPIx->CFG2_f.DSIZE = enDataLength; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set first bit position + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enPosition First bit position + ** \arg SpiFirstBitPositionMSB Spi first bit to MSB + ** \arg SpiFirstBitPositionLSB Spi first bit to LSB + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(enPosition)); + + SPIx->CFG2_f.LSBF = enPosition; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set clock division + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enClkDiv Clock division + ** \arg SpiClkDiv2 Spi pclk1 division 2 + ** \arg SpiClkDiv4 Spi pclk1 division 4 + ** \arg SpiClkDiv8 Spi pclk1 division 8 + ** \arg SpiClkDiv16 Spi pclk1 division 16 + ** \arg SpiClkDiv32 Spi pclk1 division 32 + ** \arg SpiClkDiv64 Spi pclk1 division 64 + ** \arg SpiClkDiv128 Spi pclk1 division 128 + ** \arg SpiClkDiv256 Spi pclk1 division 256 + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + SPIx->CFG2_f.MBR = enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI interrupt request + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enIrq SPI interrupt request type + ** \arg SpiIrqIdle Spi idle interrupt request + ** \arg SpiIrqReceive Spi receive interrupt request + ** \arg SpiIrqSend Spi send interrupt request + ** \arg SpiIrqError Spi error interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case SpiIrqIdle: + SPIx->CR1_f.IDIE = enNewSta; + break; + case SpiIrqReceive: + SPIx->CR1_f.RXIE = enNewSta; + break; + case SpiIrqSend: + SPIx->CR1_f.TXIE = enNewSta; + break; + case SpiIrqError: + SPIx->CR1_f.EIE = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI idle flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if (IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + enFlagSta = (en_flag_status_t)SPIx->SR_f.RDFF; + break; + case SpiFlagSendBufferEmpty: + enFlagSta = (en_flag_status_t)SPIx->SR_f.TDEF; + break; + case SpiFlagUnderloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.UDRERF; + break; + case SpiFlagParityError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.PERF; + break; + case SpiFlagModeFaultError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.MODFERF; + break; + case SpiFlagSpiIdle: + enFlagSta = (en_flag_status_t)(bool)(!SPIx->SR_f.IDLNF); + break; + case SpiFlagOverloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.OVRERF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI empty flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + SPIx->SR_f.RDFF = 0u; + break; + case SpiFlagSendBufferEmpty: + SPIx->SR_f.TDEF = 0u; + break; + case SpiFlagUnderloadError: + SPIx->SR_f.UDRERF = 0u; + break; + case SpiFlagParityError: + SPIx->SR_f.PERF = 0u; + break; + case SpiFlagModeFaultError: + SPIx->SR_f.MODFERF = 0u; + break; + case SpiFlagSpiIdle: + SPIx->SR_f.IDLNF = 0u; + break; + case SpiFlagOverloadError: + SPIx->SR_f.OVRERF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +//@} // SpiGroup + +#endif /* DDL_SPI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c new file mode 100644 index 000000000..a7f8828d5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c @@ -0,0 +1,286 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.c + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sram.h" +#include "hc32f460_utility.h" + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SramGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ECC/Parity error handling. */ +#define IS_VALID_ERR_OP(x) \ +( ((x) == SramNmi) || \ + ((x) == SramReset)) + +/*! Parameter validity check for SRAM ECC mode */ +#define IS_VALID_ECC_MD(x) \ +( ((x) == EccMode0) || \ + ((x) == EccMode1) || \ + ((x) == EccMode2) || \ + ((x) == EccMode3)) + +/*! Parameter validity check for SRAM Index */ +#define IS_VALID_INDEX(x) \ +( ((x) == Sram12Idx) || \ + ((x) == Sram3Idx) || \ + ((x) == SramHsIdx) || \ + ((x) == SramRetIdx)) + +/*! Parameter validity check for SRAM R/W wait cycle */ +#define IS_VALID_WAIT_CYCLE(x) \ +( ((x) == SramCycle1) || \ + ((x) == SramCycle2) || \ + ((x) == SramCycle3) || \ + ((x) == SramCycle4) || \ + ((x) == SramCycle5) || \ + ((x) == SramCycle6) || \ + ((x) == SramCycle7) || \ + ((x) == SramCycle8)) + +/*! Parameter validity check for SRAM error status */ +#define IS_VALID_ERR(x) \ +( ((x) == Sram3EccErr1) || \ + ((x) == Sram3EccErr2) || \ + ((x) == Sram12ParityErr) || \ + ((x) == SramHSParityErr) || \ + ((x) == SramRetParityErr)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register disable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register disabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Disable(void) +{ + M4_SRAMC->WTPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register enable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register enabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Enable(void) +{ + M4_SRAMC->WTPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register disable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register disabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Disable(void) +{ + M4_SRAMC->CKPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register enable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register enabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Enable(void) +{ + M4_SRAMC->CKPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Set Corresponding error occurs + ** Reset Corresponding error not occurs + ** + ******************************************************************************/ +en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + if (true == !!(enSramErrStatus & M4_SRAMC->CKSR)) + { + return Set; + } + else + { + return Reset; + } +} + +/** + ******************************************************************************* + ** \brief Clear SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Ok Corresponding error flag be cleared + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + M4_SRAMC->CKSR |= enSramErrStatus; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM initialization + ** + ** \param [in] pstcSramConfig SRAM configure structure + ** + ** \retval Ok SRAM initialized + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig) +{ + uint8_t i = 0u; + uint8_t u8TmpIdx; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramRC)); + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramWC)); + DDL_ASSERT(IS_VALID_ECC_MD(pstcSramConfig->enSramEccMode)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramEccOp)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramPyOp)); + + u8TmpIdx = pstcSramConfig->u8SramIdx; + + if (0u == u8TmpIdx) + { + enRet = ErrorInvalidParameter; + } + else + { + SRAM_WT_Enable(); + SRAM_CK_Enable(); + for (i = 0u; i < 4u; i++) + { + if (true == (u8TmpIdx & 0x01u)) + { + M4_SRAMC->WTCR |= (pstcSramConfig->enSramRC | \ + (pstcSramConfig->enSramWC << 4ul)) << (i * 8ul); + } + u8TmpIdx >>= 1u; + } + /* SRAM3 ECC config */ + if (pstcSramConfig->u8SramIdx & Sram3Idx) + { + M4_SRAMC->CKCR_f.ECCMOD = pstcSramConfig->enSramEccMode; + M4_SRAMC->CKCR_f.ECCOAD = pstcSramConfig->enSramEccOp; + } + /* SRAM1/2/HS/Ret parity config */ + else + { + M4_SRAMC->CKCR_f.PYOAD = pstcSramConfig->enSramPyOp; + } + + SRAM_WT_Disable(); + SRAM_CK_Disable(); + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief SRAM de-initialization + ** + ** \param None + ** + ** \retval Ok SRAM de-initialized + ** + ******************************************************************************/ +en_result_t SRAM_DeInit(void) +{ + /* SRAM R/W wait register */ + M4_SRAMC->WTPR = 0x77ul; + M4_SRAMC->WTCR = 0ul; + M4_SRAMC->WTPR = 0x76ul; + + /* SRAM check register */ + M4_SRAMC->CKPR = 0x77ul; + M4_SRAMC->CKCR = 0ul; + M4_SRAMC->CKPR = 0x76ul; + + /* SRAM status register */ + M4_SRAMC->CKSR = 0x1Ful; + + return Ok; +} + +//@} // SramGroup + +#endif /* DDL_SRAM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c new file mode 100644 index 000000000..57d5766fa --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c @@ -0,0 +1,170 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.c + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_swdt.h" +#include "hc32f460_utility.h" + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SwdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SwdtFlagCountUnderflow == (x)) || \ + (SwdtFlagRefreshError == (x))) + +/*!< SWDT_RR register refresh key */ +#define SWDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define SWDT_REFRESH_END_KEY_ ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT refresh counter + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_SWDT->RR = SWDT_REFRESH_START_KEY; + M4_SWDT->RR = SWDT_REFRESH_END_KEY_; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SWDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t SWDT counter current count value + ** + ******************************************************************************/ +uint16_t SWDT_GetCountValue(void) +{ + return ((uint16_t)M4_SWDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.UDF; + break; + case SwdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + M4_SWDT->SR_f.UDF = 0u; + break; + case SwdtFlagRefreshError: + M4_SWDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // SwdtGroup + +#endif /* DDL_SWDT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c new file mode 100644 index 000000000..497f5d97f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c @@ -0,0 +1,967 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.c + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer0.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER0_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer0Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_TMR01) || \ + ((x) == M4_TMR02)) + +/* Parameter validity check for channel. */ +#define IS_VALID_CHANNEL(x) \ +( ((x) == Tim0_ChannelA) || \ + ((x) == Tim0_ChannelB)) + +/* Parameter validity check for command. */ +#define IS_VALID_COMMAND(x) \ +( ((x) == Disable) || \ + ((x) == Enable)) + +/* Parameter validity check for timer0 function mode. */ +#define IS_VALID_FUNCTION(x) \ +( ((x) == Tim0_OutputCapare) || \ + ((x) == Tim0_InputCaptrue)) + +/* Parameter validity check for clock division. */ +#define IS_VALID_CLK_DIVISION(x) \ +( ((x) == Tim0_ClkDiv0) || \ + ((x) == Tim0_ClkDiv2) || \ + ((x) == Tim0_ClkDiv4) || \ + ((x) == Tim0_ClkDiv8) || \ + ((x) == Tim0_ClkDiv16) || \ + ((x) == Tim0_ClkDiv32) || \ + ((x) == Tim0_ClkDiv64) || \ + ((x) == Tim0_ClkDiv128) || \ + ((x) == Tim0_ClkDiv256) || \ + ((x) == Tim0_ClkDiv512) || \ + ((x) == Tim0_ClkDiv1024)) + +/* Parameter validity check for synchronous clock source. */ +#define IS_VALID_CLK_SYN_SRC(x) \ +( ((x) == Tim0_Pclk1) || \ + ((x) == Tim0_InsideHardTrig)) + +/* Parameter validity check for asynchronous clock source. */ +#define IS_VALID_CLK_ASYN_SRC(x) \ +( ((x) == Tim0_LRC) || \ + ((x) == Tim0_XTAL32)) + +/* Parameter validity check for counter clock mode. */ +#define IS_VALID_CLK_MODE(x) \ +( ((x) == Tim0_Sync) || \ + ((x) == Tim0_Async)) + +/* Parameter validity check for counter clock mode for M4_TMR01. */ +#define IS_VALID_CLK_MODE_UNIT01(x) \ +( (x) == Tim0_Async) + +/* Parameter validity check for external trigger event. */ +#define IS_VALID_TRIG_SRC_EVENT(x) \ +( ((x) <= EVT_PORT_EIRQ15) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW))) + +/* Parameter validity check for common trigger. */ +#define IS_VALID_TIM0_COM_TRIGGER(x) \ +( ((x) == Tim0ComTrigger_1) || \ + ((x) == Tim0ComTrigger_2) || \ + ((x) == Tim0ComTrigger_1_2)) + +/* Delay count for time out */ +#define TIMER0_TMOUT (0x5000ul) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get clock mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Tim0_Sync: Synchronous clock + ** \retval Tim0_Async: Asynchronous clock + ** + ******************************************************************************/ +static en_tim0_counter_mode_t TIMER0_GetClkMode(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_tim0_counter_mode_t enMode = Tim0_Sync; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSA; + break; + case Tim0_ChannelB: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSB; + break; + default: + break; + } + return enMode; +} + +/** + ******************************************************************************* + ** \brief Time delay for register write in asynchronous mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enIsPublicReg Enable for BCONR and STFLR register delay + ** + ** \retval None + ** + ******************************************************************************/ +static void AsyncDelay(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enIsPublicReg) +{ + en_functional_state_t enDelayEn = Disable; + en_tim0_counter_mode_t enModeA = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelA); + en_tim0_counter_mode_t enModeB = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelB); + + if(Enable == enIsPublicReg) + { + if((Tim0_Async == enModeA) || (Tim0_Async == enModeB)) + { + enDelayEn = Enable; + } + } + else + { + if(Tim0_Async == TIMER0_GetClkMode(pstcTim0Reg, enCh)) + { + enDelayEn = Enable; + } + } + + if(Enable == enDelayEn) + { + for(uint32_t i=0ul; iSTFLR_f.CMAF; + break; + case Tim0_ChannelB: + enFlag = (en_flag_status_t)pstcTim0Reg->STFLR_f.CMBF; + break; + default: + break; + } + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer0 status flag + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->STFLR_f.CMAF =0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMAF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->STFLR_f.CMBF = 0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMBF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Command the timer0 function + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CSTA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CSTB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select the timer0 function mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enFunc Timer0 function,Tim0_OutputCapare or Tim0_InputCapture + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_tim0_function_t enFunc) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(enFunc)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CAPMDA = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CAPMDB = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 interrupt function command + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.INTENA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.INTENB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CNTAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CNTBR)&0xFFFFu); + } + + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Write Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CNTAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CNTBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Base compare count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CMPAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CMPBR)&0xFFFFu); + } + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Wirte Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CMPAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CMPBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initialize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pstcBaseInit Timer0 function base parameter structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_base_init_t* pstcBaseInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + if (NULL != pstcBaseInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_CLK_DIVISION(pstcBaseInit->Tim0_ClockDivision)); + DDL_ASSERT(IS_VALID_CLK_SYN_SRC(pstcBaseInit->Tim0_SyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_ASYN_SRC(pstcBaseInit->Tim0_AsyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_MODE(pstcBaseInit->Tim0_CounterMode)); + + if((M4_TMR01 == pstcTim0Reg)&&(Tim0_ChannelA == enCh)) + { + DDL_ASSERT(IS_VALID_CLK_MODE_UNIT01(pstcBaseInit->Tim0_CounterMode)); + } + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + /* Clear current configurate CH */ + if(Tim0_ChannelA == enCh) + { + *(uint32_t *)&stcBconrTmp &= 0xFFFF0000ul; + } + else + { + *(uint32_t *)&stcBconrTmp &= 0x0000FFFFul; + } + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(*(uint32_t *)&stcBconrTmp != *(uint32_t *)&(pstcTim0Reg->BCONR_f)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + switch(enCh) + { + case Tim0_ChannelA: + + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKA = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKA = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVA = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPAR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSA = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + break; + + case Tim0_ChannelB: + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKB = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKB = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVB = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPBR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSB = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + + default: + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Ok Process finished. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR &= 0xFFFF0000ul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0x0000FFFFul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPAR = 0x0000FFFFul; + pstcTim0Reg->CNTAR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMAF =0u; + break; + + case Tim0_ChannelB: + pstcTim0Reg->BCONR &= 0x0000FFFFul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0xFFFF0000ul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPBR = 0x0000FFFFul; + pstcTim0Reg->CNTBR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMBF =0u; + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set external trigger source for Timer0 + ** + ** \param [in] enEvent External event source + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_SetTriggerSrc(en_event_src_t enEvent) +{ + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(enEvent)); + + M4_AOS->TMR0_HTSSR_f.TRGSEL = enEvent; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer0 common trigger. + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_tim0_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIM0_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR0_HTSSR |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR0_HTSSR &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Timer0 hardware trigger function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pStcInit Timer0 hareware trigger function structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_trigger_init_t* pStcInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + + if(NULL != pStcInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(pStcInit->Tim0_OCMode)); + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(pStcInit->Tim0_SelTrigSrc)); + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + + switch(enCh) + { + case Tim0_ChannelA: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDA = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPA = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEA = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAA = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPA = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + case Tim0_ChannelB: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDB = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPB = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEB = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAB = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPB = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + default: + break; + } + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /* Set trigger source*/ + M4_AOS->TMR0_HTSSR_f.TRGSEL = pStcInit->Tim0_SelTrigSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; + +} + +//@} // Timer0Group + +#endif /* DDL_TIMER0_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c new file mode 100644 index 000000000..1b655b490 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c @@ -0,0 +1,842 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_cnt.c + ** + ** A detailed description is available at + ** @link Timer4CntGroup Timer4CNT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_cnt.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_CNT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4CntGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for CNT pclk division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( (Timer4CntPclkDiv1 == (x)) || \ + (Timer4CntPclkDiv2 == (x)) || \ + (Timer4CntPclkDiv4 == (x)) || \ + (Timer4CntPclkDiv8 == (x)) || \ + (Timer4CntPclkDiv16 == (x)) || \ + (Timer4CntPclkDiv32 == (x)) || \ + (Timer4CntPclkDiv64 == (x)) || \ + (Timer4CntPclkDiv128 == (x)) || \ + (Timer4CntPclkDiv256 == (x)) || \ + (Timer4CntPclkDiv512 == (x)) || \ + (Timer4CntPclkDiv1024 == (x))) + +/*!< Parameter validity check for CNT mode */ +#define IS_VALID_CNT_MODE(x) \ +( (Timer4CntSawtoothWave == (x)) || \ + (Timer4CntTriangularWave == (x))) + +/*!< Parameter validity check for CNT interrupt mask */ +#define IS_VALID_CNT_INT_MSK(x) \ +( (Timer4CntIntMask0 == (x)) || \ + (Timer4CntIntMask1 == (x)) || \ + (Timer4CntIntMask2 == (x)) || \ + (Timer4CntIntMask3 == (x)) || \ + (Timer4CntIntMask4 == (x)) || \ + (Timer4CntIntMask5 == (x)) || \ + (Timer4CntIntMask6 == (x)) || \ + (Timer4CntIntMask7 == (x)) || \ + (Timer4CntIntMask8 == (x)) || \ + (Timer4CntIntMask9 == (x)) || \ + (Timer4CntIntMask10 == (x)) || \ + (Timer4CntIntMask11 == (x)) || \ + (Timer4CntIntMask12 == (x)) || \ + (Timer4CntIntMask13 == (x)) || \ + (Timer4CntIntMask14 == (x)) || \ + (Timer4CntIntMask15 == (x))) + +/*!< Parameter validity check for CNT match interrupt type */ +#define IS_VALID_CNT_INT_TYPE(x) \ +( (Timer4CntZeroMatchInt == (x)) || \ + (Timer4CntPeakMatchInt == (x))) + +/*!< Parameter validity check for CNT clock source */ +#define IS_VALID_CNT_CLK(x) \ +( (Timer4CntPclk == (x)) || \ + (Timer4CntExtclk == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CNT initialization configuration structure + ** \arg This parameter detail refer @ref stc_timer4_cnt_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_cnt_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_tmr4_ccsr_field_t CCSR_f = {0}; + stc_tmr4_cvpr_field_t CVPR_f = {0}; + + /* Check for TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(pstcInitCfg->enClk)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcInitCfg->enCntMode)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enBufferCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enZeroIntCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enPeakIntCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enZeroIntMsk)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enPeakIntMsk)); + + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + + /* stop count of CNT */ + CCSR_f.STOP = 1u; + + /* set count clock div of CNT */ + CCSR_f.CKDIV = pstcInitCfg->enClkDiv; + + /* set cnt mode */ + CCSR_f.MODE = pstcInitCfg->enCntMode; + + /* set buffer enable bit */ + CCSR_f.BUFEN = (uint16_t)(pstcInitCfg->enBufferCmd); + + /* set external clock enable bit */ + CCSR_f.ECKEN = (Timer4CntExtclk == pstcInitCfg->enClk) ? ((uint16_t)1u) : ((uint16_t)0u); + + /* Set interrupt enable */ + CCSR_f.IRQZEN = (uint16_t)(pstcInitCfg->enZeroIntCmd); + CCSR_f.IRQPEN = (uint16_t)(pstcInitCfg->enPeakIntCmd); + + /* set intterrupt mask times */ + CVPR_f.ZIM = (uint16_t)(pstcInitCfg->enZeroIntMsk); + CVPR_f.PIM = (uint16_t)(pstcInitCfg->enPeakIntMsk); + + /* Set Timer4 register */ + TMR4x->CVPR_f = CVPR_f; + TMR4x->CCSR_f = CCSR_f; + TMR4x->CPSR = pstcInitCfg->u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCntClk Timer4 CNT clock source + ** \arg Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \arg Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_t enCntClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(enCntClk)); + /* set external clock enable bit */ + TMR4x->CCSR_f.ECKEN = (uint16_t)(enCntClk); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \retval Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ******************************************************************************/ +en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_t)(TMR4x->CCSR_f.ECKEN); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enClkDiv Timer4 CNT clock division + ** \arg Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \arg Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \arg Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \arg Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \arg Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \arg Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \arg Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \arg Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \arg Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \arg Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \arg Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(enClkDiv)); + TMR4x->CCSR_f.CKDIV = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \retval Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \retval Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \retval Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \retval Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \retval Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \retval Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \retval Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \retval Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \retval Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \retval Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ******************************************************************************/ +en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_div_t)(TMR4x->CCSR_f.CKDIV); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enMode Timer4 CNT mode + ** \arg Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \arg Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_MODE(enMode)); + TMR4x->CCSR_f.MODE = (uint16_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \retval Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ******************************************************************************/ +en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_mode_t)(TMR4x->CCSR_f.MODE); +} + +/** + ******************************************************************************* + ** \brief Start Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Start successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Stop successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType The specified type of Timer4 CNT interrupt + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified Timer4 CNT interrupt function + ** \arg Disable Disable the specified Timer4 CNT interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZEN = (uint16_t)enCmd; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPEN = (uint16_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Reset None interrupt request on Timer4 CNT + ** \retval Set Detection interrupt request on Timer4 CNT + ** + ******************************************************************************/ +en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16Flag = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16Flag = TMR4x->CCSR_f.IRQZF; + break; + case Timer4CntPeakMatchInt: + u16Flag = TMR4x->CCSR_f.IRQPF; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZF = (uint16_t)0u; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPF = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Cycle The Timer4 CNT cycle value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CPSR = u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The cycle value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CPSR; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT register CNTR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.CLEAR = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the current count value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Count The Timer4 CNT current count value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CNTR = u16Count; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT current count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The current count value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CNTR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enMaskTimes Timer4 CNT interrupt mask times + ** \arg Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \arg Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \arg Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \arg Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \arg Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \arg Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \arg Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \arg Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \arg Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \arg Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \arg Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \arg Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \arg Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \arg Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \arg Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \arg Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_timer4_cnt_int_mask_t enMaskTimes) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(enMaskTimes)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CVPR_f.ZIM = (uint16_t)enMaskTimes; + break; + case Timer4CntPeakMatchInt: + TMR4x->CVPR_f.PIM = (uint16_t)enMaskTimes; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \retval Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \retval Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \retval Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \retval Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \retval Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \retval Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \retval Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \retval Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \retval Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \retval Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \retval Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \retval Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \retval Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \retval Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \retval Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ******************************************************************************/ +en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16MaskTimes = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16MaskTimes = TMR4x->CVPR_f.ZIM; + break; + case Timer4CntPeakMatchInt: + u16MaskTimes = TMR4x->CVPR_f.PIM; + break; + default: + break; + } + + return (en_timer4_cnt_int_mask_t)u16MaskTimes; +} + +//@} // Timer4CntGroup + +#endif /* DDL_TIMER4_CNT_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c new file mode 100644 index 000000000..b47a0f026 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c @@ -0,0 +1,278 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_emb.c + ** + ** A detailed description is available at + ** @link Timer4EmbGroup Timer4EMB description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_emb.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_EMB_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4EmbGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter valid check for EMB HOLD mode. */ +#define IS_VALID_EMB_HOLD_MODE(x) \ +( (EmbHoldPwm == (x)) || \ + (EmbChangePwm == (x))) + +/*!< Parameter valid check for EMB state. */ +#define IS_VALID_EMB_STATE(x) \ +( (EmbTrigPwmOutputHiz == (x)) || \ + (EmbTrigPwmOutputNormal == (x)) || \ + (EmbTrigPwmOutputLowLevel == (x)) || \ + (EmbTrigPwmOutputHighLevel == (x))) + +/*!< Timer4x ECER register address. */ +#define TMR4_ECERx(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) ? &M4_TMR4_CR->ECER1 : \ + ((M4_TMR42 == (__TMRx__)) ? &M4_TMR4_CR->ECER2 : &M4_TMR4_CR->ECER3)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg The pointer of EMB configure structure + ** \arg This parameter detail refer @ref stc_timer4_emb_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_emb_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(pstcInitCfg->enEmbState)); + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(pstcInitCfg->enPwmHold)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)(pstcInitCfg->enPwmHold); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)(pstcInitCfg->enEmbState); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set reset value(0x0000) to register ESCR */ + TMR4x->ECSR = 0u; + + /* Set reset value(0x0000) to register ECER */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)0ul; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enHoldMode EMB HOLD mode + ** \arg EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \arg EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetHoldMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_hold_mode_t enHoldMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(enHoldMode)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)enHoldMode; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \retval EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ******************************************************************************/ +en_timer4_emb_hold_mode_t TIMER4_EMB_GetHoldMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_emb_hold_mode_t)(TMR4x->ECSR_f.HOLD); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enEmbState EMB state + ** \arg EmbTrigPwmOutputNormal PWM output signal normally. + ** \arg EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \arg EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \arg EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetState(const M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_state_t enEmbState) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(enEmbState)); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)enEmbState; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbTrigPwmOutputNormal PWM output signal normally. + ** \retval EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \retval EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \retval EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ******************************************************************************/ +en_timer4_emb_state_t TIMER4_EMB_GetState(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return *(__IO en_timer4_emb_state_t *)TMR4_ECERx(TMR4x); +} + +//@} // Timer4EmbGroup + +#endif /* DDL_TIMER4_EMB_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c new file mode 100644 index 000000000..25281dfb2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c @@ -0,0 +1,1295 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_oco.c + ** + ** A detailed description is available at + ** @link Timer4OcoGroup Timer4OCO description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4OCO. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_oco.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_OCO_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4OcoGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for oco channel */ +#define IS_VALID_OCO_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOul == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwh == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for oco low channel */ +#define IS_VALID_OCO_LOW_CH(x) \ +( (Timer4OcoOul == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for even high channel */ +#define IS_VALID_OCO_HIGH_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOwh == (x))) + +/*!< Parameter validity check for occr buffer mode */ +#define IS_VALID_OCCR_BUF_MODE(x) \ +( (OccrBufDisable == (x)) || \ + (OccrBufTrsfByCntZero == (x)) || \ + (OccrBufTrsfByCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroZicZero == (x)) || \ + (OccrBufTrsfByCntPeakPicZero == (x)) || \ + (OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for ocmr buffer mode */ +#define IS_VALID_OCMR_BUF_MODE(x) \ +( (OcmrBufDisable == (x)) || \ + (OcmrBufTrsfByCntZero == (x)) || \ + (OcmrBufTrsfByCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroZicZero == (x)) || \ + (OcmrBufTrsfByCntPeakPicZero == (x)) || \ + (OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for output level type */ +#define IS_VALID_OP_PORT_LEVEL(x) \ +( (OcPortLevelLow == (x)) || \ + (OcPortLevelHigh == (x))) + +/*!< Parameter validity check for oco OP state */ +#define IS_VALID_OP_STATE(x) \ +( (OcoOpOutputLow == (x)) || \ + (OcoOpOutputHigh == (x)) || \ + (OcoOpOutputHold == (x)) || \ + (OcoOpOutputReverse == (x))) + +/*!< Parameter validity check for oco OCF state */ +#define IS_VALID_OCF_STATE(x) \ +( (OcoOcfSet == (x)) || \ + (OcoOcfHold == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_OCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCMRHUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCERx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCERU + (((uint32_t)(__CH__))/2ul)*4ul) +#define TMR4_OCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCSRU + (((uint32_t)(__CH__))/2ul)*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcInitCfg The pointer of OCO configure structure + ** \arg This parameter detail refer @ref stc_timer4_oco_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_timer4_oco_init_t* pstcInitCfg) +{ + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enOcoIntCmd)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(pstcInitCfg->enPortLevel)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(pstcInitCfg->enOcmrBufMode)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(pstcInitCfg->enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x,enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x,enCh); + + /* Set OCMR and OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPH = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEH = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPL = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEL = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + __IO uint32_t u32OCMR = 0ul; + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + u32OCMR = TMR4_OCMRx(TMR4x, enCh); + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set default value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + pstcOCSR->OCIEH = (uint16_t)0u; + pstcOCSR->OCPH = (uint16_t)0u; + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + pstcOCER->MCECH = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint16_t*)u32OCMR = (uint16_t)0u; + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + pstcOCSR->OCIEL = (uint16_t)0u; + pstcOCSR->OCPL = (uint16_t)0u; + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + pstcOCER->MCECL = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint32_t*)u32OCMR = (uint32_t)0ul; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOccrBufMode Occr buffer mode + ** \arg OccrBufDisable Disable the register buffer function + ** \arg OccrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OccrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OccrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OccrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OccrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** \retval Ok OCO occr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOccrBufMode is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_occr_buf_t enOccrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOcmrBufMode Occr buffer mode + ** \arg OcmrBufDisable Disable the register buffer function + ** \arg OcmrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OcmrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OcmrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OcmrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OcmrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** + ** \retval Ok OCO ocmr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOcmrBufMode is invalid. + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_ocmr_buf_t enOcmrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(enOcmrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCMR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Extend the matching determination conditions of OCO channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd Extend the match conditions functional state + ** \arg Enable Extend the match conditions function + ** \arg Disable Don't extend the match conditions function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ExtMatchCondCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCER->MCECH = (uint16_t)enCmd) : (pstcOCER->MCECL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO high channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref stc_oco_high_ch_compare_mode_t + ** + ** \retval Ok OCO high channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_high_ch_compare_mode_t *pstcMode) +{ + uint16_t u16OCMR = 0u; + __IO uint16_t *pu16OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_HIGH_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownCntMatchOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu16OCMR = (__IO uint16_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + pstcOCER->MCECH = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOpState << 10u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroNotMatchOpState << 14u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOpState << 8u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOpState << 6u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakNotMatchOpState << 12u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOpState << 4u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOcfState << 3u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOcfState << 1u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu16OCMR = u16OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO low channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref TIMER4_OCO_SetLowChCompareMode + ** + ** \retval Ok OCO low channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_low_ch_compare_mode_t *pstcMode) +{ + uint32_t u32OCMR = 0ul; + __IO uint32_t *pu32OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer and pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_LOW_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu32OCMR = (__IO uint32_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh);; + + pstcOCER->MCECL = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighMatchLowChOpState << 26u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState << 10u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState << 30u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState << 14u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighMatchLowChOpState << 24u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState << 8u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState << 18u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighMatchLowChOpState << 22u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState << 6u) ; + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState << 28u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState << 12u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighMatchLowChOpState << 20u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighNotMatchLowChOpState << 4u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowNotMatchHighMatchLowChOpState << 16u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroMatchOcfState << 3u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakMatchOcfState << 1u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu32OCMR = u32OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set output function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The output functional state + ** \arg Enable Enable output function + ** \arg Disable Disable output function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_OutputCompareCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCEH = (uint16_t)enCmd) : (pstcOCSR->OCEL = (uint16_t)enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OCO interrupt function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The interrupt functional state + ** \arg Enable Enable interrupt function + ** \arg Disable Disable interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCIEH = (uint16_t)enCmd) : (pstcOCSR->OCIEL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Reset None interrupt request on Timer4 OCO + ** \retval Set Detection interrupt request on Timer4 OCO + ** + ******************************************************************************/ +en_flag_status_t TIMER4_OCO_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + en_flag_status_t enFlag = Reset; + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set return value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set return value */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = 0u) : (pstcOCSR->OCFL = 0u); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enLevel OP port level of OCO + ** \arg OcPortLevelLow Output low level to OC port + ** \arg OcPortLevelHigh Output high level to OC port + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOpPortLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_port_level_t enLevel) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(enLevel)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = (uint16_t)enLevel) : (pstcOCSR->OCFL = (uint16_t)enLevel); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OcPortLevelLow Output low level to OC port + ** \retval OcPortLevelHigh Output high level to OC port + ** + ******************************************************************************/ +en_timer4_oco_port_level_t TIMER4_OCO_GetOpPinLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_timer4_oco_port_level_t enLevel = OcPortLevelLow; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enLevel; +} + +/** + ******************************************************************************* + ** \brief Write OCCR register + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] u16Occr The value of occr + ** \arg 16bit value + ** + ** \retval Ok OCCR written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_WriteOccr(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + uint16_t u16Occr) +{ + __IO uint16_t *pu16OCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + /* set register */ + *pu16OCCR = u16Occr; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCCR register value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OCCR register value + ** + ******************************************************************************/ +uint16_t TIMER4_OCO_ReadOccr(const M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + + return (*pu16OCCR); +} + +//@} // Timer4OcoGroup + +#endif /* DDL_TIMER4_OCO_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c new file mode 100644 index 000000000..0a1c9836e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c @@ -0,0 +1,600 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_pwm.c + ** + ** A detailed description is available at + ** @link Timer4PwmGroup Timer4PWM description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4PWM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_pwm.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_PWM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4PwmGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for PWM channel */ +#define IS_VALID_PWM_CH(x) \ +( (Timer4PwmU == (x)) || \ + (Timer4PwmV == (x)) || \ + (Timer4PwmW == (x))) + +/*!< Parameter validity check for PWM mode */ +#define IS_VALID_PWM_MODE(x) \ +( (PwmThroughMode == (x)) || \ + (PwmDeadTimerMode == (x)) || \ + (PwmDeadTimerFilterMode == (x))) + +/*!< Parameter valid check for PWM output state. */ +#define IS_VALID_PWM_OUTPUT_STATE(x) \ +( (PwmHPwmLHold == (x)) || \ + (PwmHPwmLReverse == (x)) || \ + (PwmHReversePwmLHold == (x)) || \ + (PwmHHoldPwmLReverse == (x))) + +/*!< Parameter valid check for PWM clock division. */ +#define IS_VALID_PWM_CLK_DIV(x) \ +( (PwmPlckDiv1 == (x)) || \ + (PwmPlckDiv2 == (x)) || \ + (PwmPlckDiv4 == (x)) || \ + (PwmPlckDiv8 == (x)) || \ + (PwmPlckDiv16 == (x)) || \ + (PwmPlckDiv32 == (x)) || \ + (PwmPlckDiv64 == (x)) || \ + (PwmPlckDiv128 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_RCSRx(__TMR4x__) ((uint32_t)&(__TMR4x__)->RCSR) +#define TMR4_POCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->POCRU + ((uint32_t)(__CH__))*4ul) +#define TMR4_PDARx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDARU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PDBRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDBRU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PFSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PFSRU + ((uint32_t)(__CH__))*8ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] pstcInitCfg The pointer of PWM configure structure + ** \arg This parameter detail refer @ref stc_timer4_pwm_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + const stc_timer4_pwm_init_t *pstcInitCfg) +{ + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + en_result_t enRet = Ok; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_PWM_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enRtIntMaskCmd)); + DDL_ASSERT(IS_VALID_PWM_OUTPUT_STATE(pstcInitCfg->enOutputState)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + /* Configure PWM mode */ + pstcPOCR_f->PWMMD = (uint16_t)(pstcInitCfg->enMode); + + /* Configure PWM mode */ + pstcPOCR_f->LVLS = (uint16_t)(pstcInitCfg->enOutputState); + + /* Set timer clock division */ + pstcPOCR_f->DIVCK = (uint16_t)(pstcInitCfg->enClkDiv); + + /* Set interrupt mask */ + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = Ok; + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + __IO uint16_t *pu16PFSR = NULL; + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t*)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t*)TMR4_PDBRx(TMR4x, enCh); + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + *pu16PDAR = (uint16_t)0u; + *pu16PDBR = (uint16_t)0u; + *pu16PFSR = (uint16_t)0u; + pstcPOCR_f->DIVCK = (uint16_t)0u; + pstcPOCR_f->LVLS = (uint16_t)0u; + pstcPOCR_f->PWMMD = (uint16_t)0u; + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)0u; + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)0u; + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Start timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StartTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTEU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTEV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTEW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Stop timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StopTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTSU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTSV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTSW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Reset None interrupt request on PWM reload-timer + ** \retval Set Detection interrupt request on PWM reload-timer + ** + ******************************************************************************/ +en_flag_status_t TIMER4_PWM_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + uint16_t u16Flag = 0u; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + u16Flag = pstcRCSR_f->RTIFU; + break; + case Timer4PwmV: + u16Flag = pstcRCSR_f->RTIFV; + break; + case Timer4PwmW: + u16Flag = pstcRCSR_f->RTIFW; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok PWM reload-timer interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTICU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTICV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTICW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write timer count cycle + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16PDAR PDAR value + ** \arg 0~65535 + ** \param [in] u16PDBR PDBR value + ** \arg 0~65535 + ** + ** \retval Ok Timer count cycle is written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_WriteDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16PDAR, + uint16_t u16PDBR) +{ + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + /* set the register */ + *pu16PDAR = u16PDAR; + *pu16PDBR = u16PDBR; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read dead region count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [out] u16PDAR Pointer of uint16_t type + ** \arg 0~65535 + ** \param [out] u16PDBR Pointer of uint16_t type + ** \arg 0~65535 + ** + ** \retval Ok Read successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ReadDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t *u16PDAR, + uint16_t *u16PDBR) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + *u16PDAR = *(__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + *u16PDBR = *(__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set cycle of PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16Count PWM pulse counter value + ** \arg 0~65535 + ** + ** \retval Ok Cycle of PWM timer is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16Count) +{ + __IO uint16_t *pu16PFSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + *pu16PFSR =u16Count; + + enRet = Ok; + } + + return enRet; +} + +//@} // Timer4PwmGroup + +#endif /* DDL_TIMER4_PWM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c new file mode 100644 index 000000000..e2724a225 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c @@ -0,0 +1,593 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_sevt.c + ** + ** A detailed description is available at + ** @link Timer4SevtGroup Timer4SEVT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4SEVT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_sevt.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4SevtGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for SEVT channel */ +#define IS_VALID_SEVT_CH(x) \ +( (Timer4SevtCh0 == (x)) || \ + (Timer4SevtCh1 == (x)) || \ + (Timer4SevtCh2 == (x)) || \ + (Timer4SevtCh3 == (x)) || \ + (Timer4SevtCh4 == (x)) || \ + (Timer4SevtCh5 == (x))) + +/*!< Parameter validity check for adct buffer mode */ +#define IS_VALID_SEVT_BUF_MODE(x) \ +( (SevtBufDisable == (x)) || \ + (SevtBufCntZero == (x)) || \ + (SevtBufCntPeak == (x)) || \ + (SevtBufCntZeroOrCntPeak == (x)) || \ + (SevtBufCntZeroZicZero == (x)) || \ + (SevtBufCntPeakPicZero == (x)) || \ + (SevtBufCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for SEVT trigger event */ +#define IS_VALID_SEVT_TRG_EVT(x) \ +( (SevtTrgEvtSCMUH == (x)) || \ + (SevtTrgEvtSCMUL == (x)) || \ + (SevtTrgEvtSCMVH == (x)) || \ + (SevtTrgEvtSCMVL == (x)) || \ + (SevtTrgEvtSCMWH == (x)) || \ + (SevtTrgEvtSCMWL == (x))) + +/*!< Parameter validity check for SEVT OCCR selection */ +#define IS_VALID_SEVT_OCCR_SEL(x) \ +( (SevtSelOCCRxh == (x)) || \ + (SevtSelOCCRxl == (x))) + +/*!< Parameter validity check for SEVT running mode */ +#define IS_VALID_SEVT_MODE(x) \ +( (SevtDelayTrigMode == (x)) || \ + (SevtCompareTrigMode == (x))) + +/*!< Parameter validity check for SEVT mask time */ +#define IS_VALID_SEVT_MSK(x) \ +( (Timer4SevtMask0 == (x)) || \ + (Timer4SevtMask1 == (x)) || \ + (Timer4SevtMask2 == (x)) || \ + (Timer4SevtMask3 == (x)) || \ + (Timer4SevtMask4 == (x)) || \ + (Timer4SevtMask5 == (x)) || \ + (Timer4SevtMask6 == (x)) || \ + (Timer4SevtMask7 == (x)) || \ + (Timer4SevtMask8 == (x)) || \ + (Timer4SevtMask9 == (x)) || \ + (Timer4SevtMask10 == (x)) || \ + (Timer4SevtMask11 == (x)) || \ + (Timer4SevtMask12 == (x)) || \ + (Timer4SevtMask13 == (x)) || \ + (Timer4SevtMask14 == (x)) || \ + (Timer4SevtMask15 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_SCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCSRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCMRUH + ((uint32_t)(__CH__))*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a Special-Event channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcInitCfg The pointer of SEVT configure structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_init_t *pstcInitCfg) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t stcSCSR_f; + __IO stc_tmr4_scmr_field_t stcSCMR_f; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_SEVT_BUF_MODE(pstcInitCfg->enBuf)); + DDL_ASSERT(IS_VALID_SEVT_MSK(pstcInitCfg->enMaskTimes)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(pstcInitCfg->enTrigEvt)); + DDL_ASSERT(IS_VALID_SEVT_OCCR_SEL(pstcInitCfg->enOccrSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcZicCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcPicCmd)); + + enRet = Ok; + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = (uint16_t)0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + switch (pstcInitCfg->enBuf) + { + case SevtBufDisable: + stcSCSR_f.BUFEN = (uint16_t)0u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntPeak: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroOrCntPeak: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroZicZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntZeroZicZeroOrCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (Ok == enRet) + { + /* Configure start trigger output channel number */ + stcSCSR_f.EVTOS = (uint16_t)(pstcInitCfg->enTrigEvt); + + /* Select SEVT running mode */ + stcSCSR_f.EVTMS = (uint16_t)(pstcInitCfg->enMode); + + /* select OCO OCCR register: OCCR(x) */ + stcSCSR_f.EVTDS = (uint16_t)(pstcInitCfg->enOccrSel); + + /* Set the comparison with CNT interrupt mask counter */ + stcSCMR_f.AMC = (uint16_t)(pstcInitCfg->enMaskTimes); + stcSCMR_f.MZCE = (uint16_t)(pstcInitCfg->enCmpAmcZicCmd); + stcSCMR_f.MPCE = (uint16_t)(pstcInitCfg->enCmpAmcPicCmd); + + *pstcSCSR_f = stcSCSR_f; + *pstcSCMR_f = stcSCMR_f; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a SEVT channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = 0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enTrgEvt Timer4 Special-EVT Event + ** \arg SevtTrgEvtSCMUH Timer4 Special-EVT Event: TMR4_Ux_SCMUH + ** \arg SevtTrgEvtSCMUL Timer4 Special-EVT Event: TMR4_Ux_SCMUL + ** \arg SevtTrgEvtSCMVH Timer4 Special-EVT Event: TMR4_Ux_SCMVH + ** \arg SevtTrgEvtSCMVL Timer4 Special-EVT Event: TMR4_Ux_SCMVL + ** \arg SevtTrgEvtSCMWH Timer4 Special-EVT Event: TMR4_Ux_SCMWH + ** \arg SevtTrgEvtSCMWL Timer4 Special-EVT Event: TMR4_Ux_SCMWL + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerEvent(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_trigger_evt_t enTrgEvt) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(enTrgEvt)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->EVTOS = (uint16_t)(enTrgEvt); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger condition. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcTrigCond The pointer of SEVT trigger condition structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_trigger_cond_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerCond(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_trigger_cond_t *pstcTrigCond) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enUpMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enZeroMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enDownMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enPeakMatchCmd)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->PEN = (uint16_t)(pstcTrigCond->enPeakMatchCmd); + pstcSCSR_f->ZEN = (uint16_t)(pstcTrigCond->enZeroMatchCmd); + pstcSCSR_f->UEN = (uint16_t)(pstcTrigCond->enUpMatchCmd); + pstcSCSR_f->DEN = (uint16_t)(pstcTrigCond->enDownMatchCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write compare or delay value to Timer4 SEVT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] u16SccrVal Timer4 SEVT compare value + ** + ** \retval Ok Compare or delay value to Timer4 SEVT is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_WriteSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + uint16_t u16SccrVal) +{ + __IO uint16_t *pu16SCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + *pu16SCCR = u16SccrVal; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read compare value or delay value of ATVR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Value of register SCCR + ** + ******************************************************************************/ +uint16_t TIMER4_SEVT_ReadSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + + /* check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + + return *pu16SCCR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enMaskTimes Timer4 Special-EVT event mask times + ** \arg Timer4SevtMask0 Mask 0 time. + ** \arg Timer4SevtMask1 Mask 1 times. + ** \arg Timer4SevtMask2 Mask 2 times. + ** \arg Timer4SevtMask3 Mask 3 times. + ** \arg Timer4SevtMask4 Mask 4 times. + ** \arg Timer4SevtMask5 Mask 5 times. + ** \arg Timer4SevtMask6 Mask 6 times. + ** \arg Timer4SevtMask7 Mask 7 times. + ** \arg Timer4SevtMask8 Mask 8 times. + ** \arg Timer4SevtMask9 Mask 9 times. + ** \arg Timer4SevtMask10 Mask 10 times + ** \arg Timer4SevtMask11 Mask 11 times + ** \arg Timer4SevtMask12 Mask 12 times + ** \arg Timer4SevtMask13 Mask 13 times + ** \arg Timer4SevtMask14 Mask 14 times + ** \arg Timer4SevtMask15 Mask 15 times + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_mask_t enMaskTimes) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MSK(enMaskTimes)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + pstcSCMR_f->AMC = (uint16_t)(enMaskTimes); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 SEVT mask count. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Timer4SevtMask0 Mask 0 time. + ** \retval Timer4SevtMask1 Mask 1 times. + ** \retval Timer4SevtMask2 Mask 2 times. + ** \retval Timer4SevtMask3 Mask 3 times. + ** \retval Timer4SevtMask4 Mask 4 times. + ** \retval Timer4SevtMask5 Mask 5 times. + ** \retval Timer4SevtMask6 Mask 6 times. + ** \retval Timer4SevtMask7 Mask 7 times. + ** \retval Timer4SevtMask8 Mask 8 times. + ** \retval Timer4SevtMask9 Mask 9 times. + ** \retval Timer4SevtMask10 Mask 10 times + ** \retval Timer4SevtMask11 Mask 11 times + ** \retval Timer4SevtMask12 Mask 12 times + ** \retval Timer4SevtMask13 Mask 13 times + ** \retval Timer4SevtMask14 Mask 14 times + ** \retval Timer4SevtMask15 Mask 15 times + ** + ******************************************************************************/ +en_timer4_sevt_mask_t TIMER4_SEVT_GetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + return (en_timer4_sevt_mask_t)pstcSCMR_f->AMC; +} + +//@} // Timer4SevtGroup + +#endif /* DDL_TIMER4_SEVT_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c new file mode 100644 index 000000000..461c25b22 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c @@ -0,0 +1,1786 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer6.c + ** + ** A detailed description is available at + ** @link Timer6Group Timer6 description @endlink + ** + ** - 2018-11-23 CDT First version for Device Driver Library of Timer6. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer6.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER6_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer6Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timer6 unit */ +#define IS_VALID_NORMAL_TIMER6_UNIT(__TMR6x__) \ +( (M4_TMR61 == (__TMR6x__)) || \ + (M4_TMR62 == (__TMR6x__)) || \ + (M4_TMR63 == (__TMR6x__))) + +/*!< Parameter valid check for period register*/ +#define IS_VALID_PERIOD_TYPE(x) \ +( (Timer6PeriodA == (x)) || \ + (Timer6PeriodB == (x)) || \ + (Timer6PeriodC == (x))) +/*!< Parameter valid check for General compare register*/ +#define IS_VALID_GEN_CMP_TYPE(x) \ +( (Timer6GenCompareA == (x)) || \ + (Timer6GenCompareB == (x)) || \ + (Timer6GenCompareC == (x)) || \ + (Timer6GenCompareD == (x)) || \ + (Timer6GenCompareE == (x)) || \ + (Timer6GenCompareF == (x))) + +/*!< Parameter valid check for Special compare register*/ +#define IS_VALID_SPECIAL_CMP_TYPE(x) \ +( (Timer6SpclCompA == (x)) || \ + (Timer6SpclCompB == (x)) || \ + (Timer6SpclCompC == (x)) || \ + (Timer6SpclCompD == (x)) || \ + (Timer6SpclCompE == (x)) || \ + (Timer6SpclCompF == (x))) +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (Timer6PclkDiv1 == (x)) || \ + (Timer6PclkDiv2 == (x)) || \ + (Timer6PclkDiv4 == (x)) || \ + (Timer6PclkDiv8 == (x)) || \ + (Timer6PclkDiv16 == (x)) || \ + (Timer6PclkDiv64 == (x)) || \ + (Timer6PclkDiv256 == (x)) || \ + (Timer6PclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (Timer6CntSawtoothMode == (x)) || \ + (Timer6CntTriangularModeA == (x)) || \ + (Timer6CntTriangularModeB == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (Timer6CntDirDown == (x)) || \ + (Timer6CntDirUp == (x))) + +/*!< Parameter valid check for timer6 output port */ +#define IS_VALID_TIMER6_OUTPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x))) + +/*!< Parameter valid check for timer6 input port */ +#define IS_VALID_TIMER6_INPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for start/stop count output status */ +#define IS_VALID_STA_STP_OUTPUT_STATUS(x) \ +( (Timer6PWMxPortOutLow == (x)) || \ + (Timer6PWMxPortOutHigh == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (Timer6FltClkPclk0Div1 == (x)) || \ + (Timer6FltClkPclk0Div4 == (x)) || \ + (Timer6FltClkPclk0Div16 == (x)) || \ + (Timer6FltClkPclk0Div64 == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_NUM(x) \ +( (Timer6PeriodCnts0 == (x)) || \ + (Timer6PeriodCnts1 == (x)) || \ + (Timer6PeriodCnts2 == (x)) || \ + (Timer6PeriodCnts3 == (x)) || \ + (Timer6PeriodCnts4 == (x)) || \ + (Timer6PeriodCnts5 == (x)) || \ + (Timer6PeriodCnts6 == (x)) || \ + (Timer6PeriodCnts7 == (x))) +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_EN_SOURCE(x) \ +( (Timer6PeriodCnteDisable == (x)) || \ + (Timer6PeriodCnteMin == (x)) || \ + (Timer6PeriodCnteMax == (x)) || \ + (Timer6PeriodCnteBoth == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (Timer6INTENA == (x)) || \ + (Timer6INTENB == (x)) || \ + (Timer6INTENC == (x)) || \ + (Timer6INTEND == (x)) || \ + (Timer6INTENE == (x)) || \ + (Timer6INTENF == (x)) || \ + (Timer6INTENOVF == (x)) || \ + (Timer6INTENUDF == (x)) || \ + (Timer6INTENDTE == (x)) || \ + (Timer6INTENSAU == (x)) || \ + (Timer6INTENSAD == (x)) || \ + (Timer6INTENSBU == (x)) || \ + (Timer6INTENSBD == (x))) + +/*!< Parameter valid check for status type */ +#define IS_VALID_STATUS_TYPE(x) \ +( (Timer6CMAF == (x)) || \ + (Timer6CMBF == (x)) || \ + (Timer6CMCF == (x)) || \ + (Timer6CMDF == (x)) || \ + (Timer6CMEF == (x)) || \ + (Timer6CMFF == (x)) || \ + (Timer6OVFF == (x)) || \ + (Timer6UDFF == (x)) || \ + (Timer6DTEF == (x)) || \ + (Timer6CMSAUF == (x)) || \ + (Timer6CMSADF == (x)) || \ + (Timer6CMSBUF == (x)) || \ + (Timer6CMSBDF == (x)) || \ + (Timer6VPERNUM == (x)) || \ + (Timer6DIRF == (x))) + +/*!< Parameter valid check for hardware up count/down count event type */ +#define IS_VALID_HW_COUNT_TYPE(x) \ +( (Timer6HwCntPWMALowPWMBRise == (x)) || \ + (Timer6HwCntPWMALowPWMBFall == (x)) || \ + (Timer6HwCntPWMAHighPWMBRise == (x)) || \ + (Timer6HwCntPWMAHighPWMBFall == (x)) || \ + (Timer6HwCntPWMBLowPWMARise == (x)) || \ + (Timer6HwCntPWMBLowPWMAFall == (x)) || \ + (Timer6HwCntPWMBHighPWMARise == (x)) || \ + (Timer6HwCntPWMBHighPWMAFall == (x)) || \ + (Timer6HwCntTRIGARise == (x)) || \ + (Timer6HwCntTRIGAFall == (x)) || \ + (Timer6HwCntTRIGBRise == (x)) || \ + (Timer6HwCntTRIGBFall == (x)) || \ + (Timer6HwCntAos0 == (x)) || \ + (Timer6HwCntAos1 == (x))) + +/*!< Parameter valid check for hardware up start/stop/clear/capture event type */ +#define IS_VALID_HW_STA_STP_CLR_CAP_TYPE(x) \ +( (Timer6HwTrigAos0 == (x)) || \ + (Timer6HwTrigAos1 == (x)) || \ + (Timer6HwTrigPWMARise == (x)) || \ + (Timer6HwTrigPWMAFall == (x)) || \ + (Timer6HwTrigPWMBRise == (x)) || \ + (Timer6HwTrigPWMBFall == (x)) || \ + (Timer6HwTrigTimTriARise == (x)) || \ + (Timer6HwTrigTimTriAFall == (x)) || \ + (Timer6HwTrigTimTriBRise == (x)) || \ + (Timer6HwTrigTimTriBFall == (x)) || \ + (Timer6HwTrigEnd == (x))) + +/*!< Parameter valid check for timer6 input port type */ +#define IS_VALID_INPUT_PORT_TYPE(x) \ +( (Timer6xCHA == (x)) || \ + (Timer6xCHB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for GenCMP and period register buffer transfer type*/ +#define IS_VALID_GCMP_PRD_BUF_TYPE(x) \ +( (Timer6GcmpPrdSingleBuf == (x)) || \ + (Timer6GcmpPrdDoubleBuf == (x))) + +/*!< Parameter valid check for special compare register buffer transfer type */ +#define IS_VALID_SPCL_BUF_TYPE(x) \ +( (Timer6SpclSingleBuf == (x)) || \ + (Timer6SpclDoubleBuf == (x))) + +/*!< Parameter valid check for spcl register transfer opportunity type */ +#define IS_VALID_SPCL_TRANS_OPT_TYPE(x) \ +( (Timer6SplcOptNone == (x)) || \ + (Timer6SplcOptOverFlow == (x)) || \ + (Timer6SplcOptUnderFlow == (x)) || \ + (Timer6SplcOptBoth == (x))) + +/*!< Parameter valid check for dead time register type */ +#define IS_VALID_DEAD_TIME_TYPE(x) \ +( (Timer6DeadTimUpAR == (x)) || \ + (Timer6DeadTimUpBR == (x)) || \ + (Timer6DeadTimDwnAR == (x)) || \ + (Timer6DeadTimDwnBR == (x))) + +/*!< Parameter valid check for Z Phase input mask periods */ +#define IS_VALID_ZPHASE_MASK_PRD(x) \ +( (Timer6ZMaskDis == (x)) || \ + (Timer6ZMask4Cyl == (x)) || \ + (Timer6ZMask8Cyl == (x)) || \ + (Tiemr6ZMask16Cyl == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511) + +/*!< Parameter validity check for common trigger. */ +#define IS_VALID_TIMER6_COM_TRIGGER(x) \ +( (Timer6ComTrigger_1 == (x)) || \ + (Timer6ComTrigger_2 == (x)) || \ + (Timer6ComTrigger_1_2 == (x))) + +/*! TimerA registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_GCONR_RESET_VALUE (0x00000100ul) +#define TIMERA_REG_ICONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_PCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_BCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_DCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_FCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_VPERR_RESET_VALUE (0x00000000ul) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief Timer6 interrupt request enable or disable + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Irq Irq type + * \param [in] bEn true/false + * + * \retval Ok: config successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enTimer6Irq)); + + switch (enTimer6Irq) + { + case Timer6INTENA: + TMR6x->ICONR_f.INTENA = bEn; + break; + case Timer6INTENB: + TMR6x->ICONR_f.INTENB = bEn; + break; + case Timer6INTENC: + TMR6x->ICONR_f.INTENC = bEn; + break; + case Timer6INTEND: + TMR6x->ICONR_f.INTEND = bEn; + break; + case Timer6INTENE: + TMR6x->ICONR_f.INTENE = bEn; + break; + case Timer6INTENF: + TMR6x->ICONR_f.INTENF = bEn; + break; + case Timer6INTENOVF: + TMR6x->ICONR_f.INTENOVF = bEn; + break; + case Timer6INTENUDF: + TMR6x->ICONR_f.INTENUDF = bEn; + break; + case Timer6INTENDTE: + TMR6x->ICONR_f.INTENDTE = bEn; + break; + case Timer6INTENSAU: + TMR6x->ICONR_f.INTENSAU = bEn; + break; + case Timer6INTENSAD: + TMR6x->ICONR_f.INTENSAD = bEn; + break; + case Timer6INTENSBU: + TMR6x->ICONR_f.INTENSBU = bEn; + break; + case Timer6INTENSBD: + TMR6x->ICONR_f.INTENSBD = bEn; + break; + default: + break; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Timer6 status flag + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \param [in] enStatus Timer6 status type + ** + ** \retval Timer6 status + ** + ******************************************************************************/ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus) +{ + uint8_t status = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case Timer6CMAF: + status = (uint8_t)TMR6x->STFLR_f.CMAF; + break; + case Timer6CMBF: + status = (uint8_t)TMR6x->STFLR_f.CMBF; + break; + case Timer6CMCF: + status = (uint8_t)TMR6x->STFLR_f.CMCF; + break; + case Timer6CMDF: + status = (uint8_t)TMR6x->STFLR_f.CMDF; + break; + case Timer6CMEF: + status = (uint8_t)TMR6x->STFLR_f.CMEF; + break; + case Timer6CMFF: + status = (uint8_t)TMR6x->STFLR_f.CMFF; + break; + case Timer6OVFF: + status = (uint8_t)TMR6x->STFLR_f.OVFF; + break; + case Timer6UDFF: + status = (uint8_t)TMR6x->STFLR_f.UDFF; + break; + case Timer6DTEF: + status = (uint8_t)TMR6x->STFLR_f.DTEF; + break; + case Timer6CMSAUF: + status = (uint8_t)TMR6x->STFLR_f.CMSAUF; + break; + case Timer6CMSADF: + status = (uint8_t)TMR6x->STFLR_f.CMSADF; + break; + case Timer6CMSBUF: + status = (uint8_t)TMR6x->STFLR_f.CMSBUF; + break; + case Timer6CMSBDF: + status = (uint8_t)TMR6x->STFLR_f.CMSBDF; + break; + case Timer6VPERNUM: + status = (uint8_t)TMR6x->STFLR_f.VPERNUM; + break; + case Timer6DIRF: + status = (uint8_t)TMR6x->STFLR_f.DIRF; + break; + default: + break; + } + + return status; +} + + + +/** + ******************************************************************************* + ** \brief De-Initialize Timer6 unit + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TMR6x->GCONR = TIMERA_REG_GCONR_RESET_VALUE; + TMR6x->PCONR = TIMERA_REG_PCONR_RESET_VALUE; + TMR6x->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TMR6x->BCONR = TIMERA_REG_BCONR_RESET_VALUE; + TMR6x->DCONR = TIMERA_REG_DCONR_RESET_VALUE; + TMR6x->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TMR6x->VPERR = TIMERA_REG_VPERR_RESET_VALUE; + TMR6x->HSTAR = 0x00000000ul; + TMR6x->HSTPR = 0x00000000ul; + TMR6x->HCLRR = 0x00000000ul; + TMR6x->HCPAR = 0x00000000ul; + TMR6x->HCPBR = 0x00000000ul; + TMR6x->HCUPR = 0x00000000ul; + TMR6x->HCDOR = 0x00000000ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Base Config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6BaseCntCfg Bsee Config Pointer + * + * \retval Ok: Config Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6BaseCntCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcTimer6BaseCntCfg->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcTimer6BaseCntCfg->enCntDir)); + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcTimer6BaseCntCfg->enCntClkDiv)); + + + TMR6x->GCONR_f.MODE = pstcTimer6BaseCntCfg->enCntMode; + TMR6x->GCONR_f.DIR = pstcTimer6BaseCntCfg->enCntDir; + TMR6x->GCONR_f.CKDIV = pstcTimer6BaseCntCfg->enCntClkDiv; + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Unit Start Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 1ul; + + return Ok; +} + +/******************************************************************************* + * \brief TImer6 Unit Stop Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Set Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = u16Value; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Get Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x) +{ + uint16_t u16Value; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u16Value = (uint16_t)TMR6x->CNTER_f.CNT; + + return u16Value; +} + +/******************************************************************************* + * \brief Timer6 Unit Clear Count Value + * + * + * \param [in] TMR6x Timer6 unit + * + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit set count period and buffer value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Periodx Period register name + * \param [in] u16Period Count period value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_TYPE(enTimer6Periodx)); + + switch (enTimer6Periodx) + { + case Timer6PeriodA: + TMR6x->PERAR = u16Period; + break; + case Timer6PeriodB: + TMR6x->PERBR = u16Period; + break; + case Timer6PeriodC: + TMR6x->PERCR = u16Period; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * \param [in] u16Compare General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + TMR6x->GCMAR = u16Compare; + break; + case Timer6GenCompareB: + TMR6x->GCMBR = u16Compare; + break; + case Timer6GenCompareC: + TMR6x->GCMCR = u16Compare; + break; + case Timer6GenCompareD: + TMR6x->GCMDR = u16Compare; + break; + case Timer6GenCompareE: + TMR6x->GCMER = u16Compare; + break; + case Timer6GenCompareF: + TMR6x->GCMFR = u16Compare; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set Special Compare Register Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp General Compare Register name + * \param [in] u16SpclCmp General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->SCMAR = u16SpclCmp; + break; + case Timer6SpclCompB: + TMR6x->SCMBR = u16SpclCmp; + break; + case Timer6SpclCompC: + TMR6x->SCMCR = u16SpclCmp; + break; + case Timer6SpclCompD: + TMR6x->SCMDR = u16SpclCmp; + break; + case Timer6SpclCompE: + TMR6x->SCMER = u16SpclCmp; + break; + case Timer6SpclCompF: + TMR6x->SCMFR = u16SpclCmp; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config general compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort PWM channel of timer6 + * \param [in] pstcTimer6GenBufCfg General Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6GenBufCfg->enGcmpBufTransType)); + + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->BCONR_f.BENA = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEA = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + case Timer6PWMB: + TMR6x->BCONR_f.BENB = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEB = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config special compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp Special Compare Register nameunit + * \param [in] pstcTimer6SpclBufCfg Special Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + DDL_ASSERT(IS_VALID_SPCL_BUF_TYPE(pstcTimer6SpclBufCfg->enSpclBufTransType)); + DDL_ASSERT(IS_VALID_SPCL_TRANS_OPT_TYPE(pstcTimer6SpclBufCfg->enSpclBufOptType)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->BCONR_f.BENSPA = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPA = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPA = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + case Timer6SpclCompB: + TMR6x->BCONR_f.BENSPB = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPB = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPB = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config period buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PrdBufCfg Period Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6PrdBufCfg->enPeriodBufTransType)); + + TMR6x->BCONR_f.BENP = pstcTimer6PrdBufCfg->bEnPeriodTransBuf; + TMR6x->BCONR_f.BSEP = pstcTimer6PrdBufCfg->enPeriodBufTransType; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit get General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * + * + * \retval u16TempValue: General Compare Register value + * + ******************************************************************************/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare) +{ + uint16_t u16TempValue = 0u; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + u16TempValue = (uint16_t)TMR6x->GCMAR; + break; + case Timer6GenCompareB: + u16TempValue = (uint16_t)TMR6x->GCMBR; + break; + case Timer6GenCompareC: + u16TempValue = (uint16_t)TMR6x->GCMCR; + break; + case Timer6GenCompareD: + u16TempValue = (uint16_t)TMR6x->GCMDR; + break; + case Timer6GenCompareE: + u16TempValue = (uint16_t)TMR6x->GCMER; + break; + case Timer6GenCompareF: + u16TempValue = (uint16_t)TMR6x->GCMFR; + break; + default: + break; + } + + return u16TempValue; +} + +/*********************************************************************** + * \brief Timer6 Config valid count period + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ValidPerCfg Valid Count Period Pointer + * + * \retval Ok: Config successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ***********************************************************************/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6ValidPerCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_EN_SOURCE(pstcTimer6ValidPerCfg->enValidCdtEn)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_NUM(pstcTimer6ValidPerCfg->enValidCntNum)); + + TMR6x->VPERR_f.PCNTS = pstcTimer6ValidPerCfg->enValidCntNum; + TMR6x->VPERR_f.PCNTE = pstcTimer6ValidPerCfg->enValidCdtEn; + TMR6x->VPERR_f.SPPERIA = pstcTimer6ValidPerCfg->bPeriodSCMA; + TMR6x->VPERR_f.SPPERIB = pstcTimer6ValidPerCfg->bPeriodSCMB; + } + return enRet; +} + +/******************************************************************************* + * \brief Port input config(Trig) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PortInputCfg Point Input Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6PortInputCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (pstcTimer6PortInputCfg->enPortSel) + { + case Timer6xCHA: + TMR6x->PCONR_f.CAPMDA = pstcTimer6PortInputCfg->enPortMode; + TMR6x->FCONR_f.NOFIENGA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6xCHB: + TMR6x->PCONR_f.CAPMDB = pstcTimer6PortInputCfg->enPortMode; + TMR6x->FCONR_f.NOFIENGB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGB = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigA: + TMR6x->FCONR_f.NOFIENTA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKTA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigB: + TMR6x->FCONR_f.NOFIENTB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKTB = pstcTimer6PortInputCfg->enFltClk; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Output Port config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort Timer6 Port(PWMA/PWMB) + * \param [in] pstcTimer6PortOutCfg timer6 Port Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, + en_timer6_chx_port_t enTimer6PWMPort, + const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + + if (NULL == pstcTimer6PortOutCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->PCONR_f.CAPMDA = pstcTimer6PortOutCfg->enPortMode; + TMR6x->PCONR_f.STACA = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCA = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSA = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCA = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCA = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENA = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALA = pstcTimer6PortOutCfg->enDisVal; + break; + + case Timer6PWMB: + TMR6x->PCONR_f.CAPMDB = pstcTimer6PortOutCfg->enPortMode; + TMR6x->PCONR_f.STACB = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCB = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSB = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCB = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCB = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENB = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALB = pstcTimer6PortOutCfg->enDisVal; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + + +/******************************************************************************* + * \brief Timer6 unit Set DeadTime Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6DTReg DeadTime Register name + * \param [in] u16DTValue DeadTime Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEAD_TIME_TYPE(enTimer6DTReg)); + + switch (enTimer6DTReg) + { + case Timer6DeadTimUpAR: + TMR6x->DTUAR = u16DTValue; + break; + case Timer6DeadTimUpBR: + TMR6x->DTUBR = u16DTValue; + break; + case Timer6DeadTimDwnAR: + TMR6x->DTDAR = u16DTValue; + break; + case Timer6DeadTimDwnBR: + TMR6x->DTDBR = u16DTValue; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Config DeadTime function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6DTCfg Timer6 dead time config pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6DTCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + TMR6x->DCONR_f.SEPA = pstcTimer6DTCfg->bEnDtEqualUpDwn; + TMR6x->DCONR_f.DTBENU = pstcTimer6DTCfg->bEnDtBufUp; + TMR6x->DCONR_f.DTBEND = pstcTimer6DTCfg->bEnDtBufDwn; + TMR6x->DCONR_f.DTCEN = pstcTimer6DTCfg->bEnDeadtime; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Start + * + * + * \param [in] pstcTimer6SwSyncStart Software Synchrony Start Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStart) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStart->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStart->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStart->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTAR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Stop + * + * + * \param [in] pstcTimer6SwSyncStop Software Synchrony Stop Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStop) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStop->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStop->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStop->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTPR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Clear + * + * + * \param [in] pstcTimer6SwSyncClear Software Synchrony Clear Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncClear) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncClear->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncClear->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncClear->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SCLRR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Get Software Synchrony status + * + * + * \param [in] pstcTimer6SwSyncState Software Synchrony State Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6SwSyncState) + { + enRet = ErrorInvalidParameter; + } + else + { + if (M4_TMR6_CR->SSTAR & 0x1ul) + { + pstcTimer6SwSyncState->bTimer61 = true; + } + else + { + pstcTimer6SwSyncState->bTimer61 = false; + } + if (M4_TMR6_CR->SSTAR & 0x2ul) + { + pstcTimer6SwSyncState->bTimer62 = true; + } + else + { + pstcTimer6SwSyncState->bTimer62 = false; + } + if (M4_TMR6_CR->SSTAR & 0x4ul) + { + pstcTimer6SwSyncState->bTimer63 = true; + } + else + { + pstcTimer6SwSyncState->bTimer63 = false; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Hardware UpCount Event config + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntUp Hardware UpCount Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntUp)); + + u32Val = TMR6x->HCUPR; + TMR6x->HCUPR = u32Val | (1ul << enTimer6HwCntUp); + + return Ok; +} + +/************************************************************** + * \brief Clear Timer6 Hardware UpCount Event + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ************************************************************/ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCUPR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Set Timer6 Hardware DownCount Event + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntDwn Hardware DownCount Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntDwn)); + + u32Val = TMR6x->HCDOR; + TMR6x->HCDOR = u32Val | (1ul << enTimer6HwCntDwn); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Timer6 Hardware DownCount Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCDOR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStart Hardware Start Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStart)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << enTimer6HwStart); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStop Hardware Stop Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStop)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << enTimer6HwStop); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTPR = 0ul; + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << 31u); + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwClear Hardware Clear Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwClear)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << enTimer6HwClear); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCLRR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureA Hardware capture event A selection + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureA)); + + u32Val = TMR6x->HCPAR; + TMR6x->HCPAR = u32Val | (1ul << enTimer6HwCaptureA); + //TMR6x->PCONR_f.CAPMDA = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureB Hardware capture event B selection + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureB)); + + u32Val = TMR6x->HCPBR; + TMR6x->HCPBR = u32Val | (1ul << enTimer6HwCaptureB); + //TMR6x->PCONR_f.CAPMDB = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPBR = 0ul; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 0 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 1 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR2_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 0 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR1 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR1 &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 1 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR2 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR2 &= ~(u32ComTrig << 30u); + } +} + +/******************************************************************************* + * \brief Z phase input mask config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ZMaskCfg Z phase input mask config pointer + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_ZPHASE_MASK_PRD(pstcTimer6ZMaskCfg->enZMaskCycle)); + + TMR6x->GCONR_f.ZMSKVAL = pstcTimer6ZMaskCfg->enZMaskCycle; + TMR6x->GCONR_f.ZMSKPOS = pstcTimer6ZMaskCfg->bFltPosCntMaksEn; + TMR6x->GCONR_f.ZMSKREV = pstcTimer6ZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + + +//@} // Timer6Group + +#endif /* DDL_TIMER6_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c new file mode 100644 index 000000000..d45888621 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c @@ -0,0 +1,1972 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.c + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timera.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMERA_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup TimeraGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timera unit */ +#define IS_VALID_NORMAL_TIMERA_UNIT(x) \ +( (M4_TMRA1 == (x)) || \ + (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for sync startup timera unit */ +#define IS_VALID_SYNC_STARTUP_TIMERA_UNIT(x) \ +( (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (TimeraPclkDiv1 == (x)) || \ + (TimeraPclkDiv2 == (x)) || \ + (TimeraPclkDiv4 == (x)) || \ + (TimeraPclkDiv8 == (x)) || \ + (TimeraPclkDiv16 == (x)) || \ + (TimeraPclkDiv32 == (x)) || \ + (TimeraPclkDiv64 == (x)) || \ + (TimeraPclkDiv128 == (x)) || \ + (TimeraPclkDiv256 == (x)) || \ + (TimeraPclkDiv512 == (x)) || \ + (TimeraPclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (TimeraCountModeSawtoothWave == (x)) || \ + (TimeraCountModeTriangularWave == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (TimeraCountDirUp == (x)) || \ + (TimeraCountDirDown == (x))) + +/*!< Parameter valid check for normal timera channel */ +#define IS_VALID_NORMAL_TIMERA_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh2 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh4 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh6 == (x)) || \ + (TimeraCh7 == (x)) || \ + (TimeraCh8 == (x))) + +/*!< Parameter valid check for set cache channel */ +#define IS_VALID_SET_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for enable cache channel */ +#define IS_VALID_ENABLE_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for timera count start output status */ +#define IS_VALID_COUNT_START_OUTPUT(x) \ +( (TimeraCountStartOutputLow == (x)) || \ + (TimeraCountStartOutputHigh == (x)) || \ + (TimeraCountStartOutputKeep == (x))) + +/*!< Parameter valid check for timera count stop output status */ +#define IS_VALID_COUNT_STOP_OUTPUT(x) \ +( (TimeraCountStopOutputLow == (x)) || \ + (TimeraCountStopOutputHigh == (x)) || \ + (TimeraCountStopOutputKeep == (x))) + +/*!< Parameter valid check for compare match output status */ +#define IS_VALID_COMPARE_MATCH_OUTPUT(x) \ +( (TimeraCompareMatchOutputLow == (x)) || \ + (TimeraCompareMatchOutputHigh == (x)) || \ + (TimeraCompareMatchOutputKeep == (x)) || \ + (TimeraCompareMatchOutputReverse == (x))) + +/*!< Parameter valid check for period match output status */ +#define IS_VALID_PERIOD_MATCH_OUTPUT(x) \ +( (TimeraPeriodMatchOutputLow == (x)) || \ + (TimeraPeriodMatchOutputHigh == (x)) || \ + (TimeraPeriodMatchOutputKeep == (x)) || \ + (TimeraPeriodMatchOutputReverse == (x))) + +/*!< Parameter valid check for specify output status */ +#define IS_VALID_SPECIFY_OUTPUT_STATUS(x) \ +( (TimeraSpecifyOutputInvalid == (x)) || \ + (TimeraSpecifyOutputLow == (x)) || \ + (TimeraSpecifyOutputHigh == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (TimeraFilterPclkDiv1 == (x)) || \ + (TimeraFilterPclkDiv4 == (x)) || \ + (TimeraFilterPclkDiv16 == (x)) || \ + (TimeraFilterPclkDiv64 == (x))) + +/*!< Parameter valid check for capture filter port source */ +#define IS_VALID_CAPTURE_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceCh1 == (x)) || \ + (TimeraFilterSourceCh2 == (x)) || \ + (TimeraFilterSourceCh3 == (x)) || \ + (TimeraFilterSourceCh4 == (x)) || \ + (TimeraFilterSourceCh5 == (x)) || \ + (TimeraFilterSourceCh6 == (x)) || \ + (TimeraFilterSourceCh7 == (x)) || \ + (TimeraFilterSourceCh8 == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for coding filter port source */ +#define IS_VALID_CODING_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceClkA == (x)) || \ + (TimeraFilterSourceClkB == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (TimeraIrqCaptureOrCompareCh1 == (x)) || \ + (TimeraIrqCaptureOrCompareCh2 == (x)) || \ + (TimeraIrqCaptureOrCompareCh3 == (x)) || \ + (TimeraIrqCaptureOrCompareCh4 == (x)) || \ + (TimeraIrqCaptureOrCompareCh5 == (x)) || \ + (TimeraIrqCaptureOrCompareCh6 == (x)) || \ + (TimeraIrqCaptureOrCompareCh7 == (x)) || \ + (TimeraIrqCaptureOrCompareCh8 == (x)) || \ + (TimeraIrqOverflow == (x)) || \ + (TimeraIrqUnderflow == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (TimeraFlagCaptureOrCompareCh1 == (x)) || \ + (TimeraFlagCaptureOrCompareCh2 == (x)) || \ + (TimeraFlagCaptureOrCompareCh3 == (x)) || \ + (TimeraFlagCaptureOrCompareCh4 == (x)) || \ + (TimeraFlagCaptureOrCompareCh5 == (x)) || \ + (TimeraFlagCaptureOrCompareCh6 == (x)) || \ + (TimeraFlagCaptureOrCompareCh7 == (x)) || \ + (TimeraFlagCaptureOrCompareCh8 == (x)) || \ + (TimeraFlagOverflow == (x)) || \ + (TimeraFlagUnderflow == (x))) + +/*! Parameter valid check for common trigger. */ +#define IS_VALID_COM_TRIGGER(x) \ +( (TimeraComTrigger_1 == (x)) || \ + (TimeraComTrigger_2 == (x)) || \ + (TimeraComTrigger_1_2 == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511u) + +/*!< Timera registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_PERAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_CMPAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_BCSTR_RESET_VALUE (0x0002u) +#define TIMERA_REG_ICONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_ECONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_FCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_STFLR_RESET_VALUE (0x0000u) +#define TIMERA_REG_BCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_CCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_PCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCUPR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCDOR_RESET_VALUE (0x0000u) + +#define TIMERA_REG_HTSSR0_RESET_VALUE (0x000001FFul) +#define TIMERA_REG_HTSSR1_RESET_VALUE (0x000001FFul) + +/*!< Timera calculate register address of channel */ +#define TIMERA_CALC_REG_ADDR(reg, chl) ((uint32_t)(&(reg)) + (chl)*0x4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize Timera unit + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Cnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TIMERAx->PERAR = TIMERA_REG_PERAR_RESET_VALUE; + TIMERAx->BCSTR = TIMERA_REG_BCSTR_RESET_VALUE; + TIMERAx->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TIMERAx->ECONR = TIMERA_REG_ECONR_RESET_VALUE; + TIMERAx->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TIMERAx->STFLR = TIMERA_REG_STFLR_RESET_VALUE; + TIMERAx->HCONR = TIMERA_REG_HCONR_RESET_VALUE; + TIMERAx->HCUPR = TIMERA_REG_HCUPR_RESET_VALUE; + TIMERAx->HCDOR = TIMERA_REG_HCDOR_RESET_VALUE; + + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, u32Cnt) = TIMERA_REG_CMPAR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 4u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, u32Cnt * 2u) = TIMERA_REG_BCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, u32Cnt) = TIMERA_REG_CCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, u32Cnt) = TIMERA_REG_PCONR_RESET_VALUE; + } + + M4_AOS->TMRA_HTSSR0 = TIMERA_REG_HTSSR0_RESET_VALUE; + M4_AOS->TMRA_HTSSR1 = TIMERA_REG_HTSSR1_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit base function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcBaseInit Pointer to timera base init configuration + ** \arg See the struct #stc_timera_base_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode Unit 1 sync startup invalid + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcBaseInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcBaseInit)) + { + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcBaseInit->enClkDiv)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcBaseInit->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcBaseInit->enCntDir)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcBaseInit->enSyncStartupEn)); + + /* Configure control status register */ + TIMERAx->BCSTR_f.CKDIV = pstcBaseInit->enClkDiv; + TIMERAx->BCSTR_f.MODE = pstcBaseInit->enCntMode; + TIMERAx->BCSTR_f.DIR = pstcBaseInit->enCntDir; + + /* Unit 1 sync startup invalid */ + if ((M4_TMRA1 == TIMERAx) && (Enable == pstcBaseInit->enSyncStartupEn)) + { + enRet = ErrorInvalidMode; + } + else + { + TIMERAx->BCSTR_f.SYNST = pstcBaseInit->enSyncStartupEn; + enRet = Ok; + } + + /* Configure period value register */ + TIMERAx->PERAR = pstcBaseInit->u16PeriodVal; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Cnt Timera current count value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16Cnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current count value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CurrCntVal = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CurrCntVal = (uint16_t)TIMERAx->CNTER; + } + + return u16CurrCntVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera period value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Period Timera period value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->PERAR = u16Period; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera period count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current period value + ** + ******************************************************************************/ +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16PeriodVal = 0u; + + /* Check parameters */ + if (IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16PeriodVal = (uint16_t)TIMERAx->PERAR; + } + + return u16PeriodVal; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera software synchronous startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable synchronous startup + ** \arg Enable Enable synchronous startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SYNC_STARTUP_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.SYNST = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera startup + ** \arg Enable Enable timera startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.START = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCompareInit Pointer to timera compare init configuration + ** \arg See the struct #stc_timera_compare_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCompareInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCompareInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_COUNT_START_OUTPUT(pstcCompareInit->enStartCountOutput)); + DDL_ASSERT(IS_VALID_COUNT_STOP_OUTPUT(pstcCompareInit->enStopCountOutput)); + DDL_ASSERT(IS_VALID_COMPARE_MATCH_OUTPUT(pstcCompareInit->enCompareMatchOutput)); + DDL_ASSERT(IS_VALID_PERIOD_MATCH_OUTPUT(pstcCompareInit->enPeriodMatchOutput)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(pstcCompareInit->enSpecifyOutput)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enCacheEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularCrestTransEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularTroughTransEn)); + + /* Configure port control register */ + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->STAC = pstcCompareInit->enStartCountOutput; + pstcTimeraPort->STPC = pstcCompareInit->enStopCountOutput; + pstcTimeraPort->CMPC = pstcCompareInit->enCompareMatchOutput; + pstcTimeraPort->PERC = pstcCompareInit->enPeriodMatchOutput; + pstcTimeraPort->FORC = pstcCompareInit->enSpecifyOutput; + + /* Configure cache control register */ + if ((TimeraCh1 == enChannel) || (TimeraCh3 == enChannel) || + (TimeraCh5 == enChannel) || (TimeraCh7 == enChannel)) + { + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BSE0 = pstcCompareInit->enTriangularCrestTransEn; + pstcTimeraCache->BSE1 = pstcCompareInit->enTriangularTroughTransEn; + pstcTimeraCache->BEN = pstcCompareInit->enCacheEn; + /* Configure compare cache value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareCacheVal; + } + + /* Configure compare value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareVal; + + /* Set compare output function */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->CAPMD = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] u16CompareVal Timera campare value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = u16CompareVal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera compare value + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CompareVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CompareVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CompareVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare cache value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] u16CompareCache Timera compare cache value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_SET_CACHE_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = u16CompareCache; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare cache + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare cache + ** \arg Enable Enable timera compare cache + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_ENABLE_CACHE_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* Configure cache control register */ + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Specify Timera port output status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enOutputSta Timera port output status + ** \arg TimeraSpecifyOutputInvalid Port output invalid + ** \arg TimeraSpecifyOutputLow Port output low level from next period + ** \arg TimeraSpecifyOutputHigh Port output high level from next period + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(enOutputSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->FORC = enOutputSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare function + ** \arg Enable Enable timera compare function + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->OUTEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit capture function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCapInit Pointer to timera capture init configuration + ** \arg See the struct #stc_timera_capture_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCapInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCapInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureSpecifyEventEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enPwmFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enTrigFilterEn)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enPwmClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enTrigClkDiv)); + + /* Configure capture control register */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->HICP0 = pstcCapInit->enCapturePwmRisingEn; + pstcTimeraCapture->HICP1 = pstcCapInit->enCapturePwmFallingEn; + pstcTimeraCapture->HICP2 = pstcCapInit->enCaptureSpecifyEventEn; + pstcTimeraCapture->NOFICKCP = pstcCapInit->enPwmClkDiv; + pstcTimeraCapture->NOFIENCP = pstcCapInit->enPwmFilterEn; + + /* TIMA__TRIG port capture function only valid for TimeraCh3 */ + if (TimeraCh3 == enChannel) + { + pstcTimeraCapture->HICP3 = pstcCapInit->enCaptureTrigRisingEn; + pstcTimeraCapture->HICP4 = pstcCapInit->enCaptureTrigFallingEn; + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCapInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCapInit->enTrigFilterEn; + } + + /* Set capture input function */ + pstcTimeraCapture->CAPMD = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera capture filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera capture filter input port + ** \arg TimeraFilterSourceCh1 TIMA__PWM1 input port + ** \arg TimeraFilterSourceCh2 TIMA__PWM2 input port + ** \arg TimeraFilterSourceCh3 TIMA__PWM3 input port + ** \arg TimeraFilterSourceCh4 TIMA__PWM4 input port + ** \arg TimeraFilterSourceCh5 TIMA__PWM5 input port + ** \arg TimeraFilterSourceCh6 TIMA__PWM6 input port + ** \arg TimeraFilterSourceCh7 TIMA__PWM7 input port + ** \arg TimeraFilterSourceCh8 TIMA__PWM8 input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera capture filter + ** \arg Enable Enable timera capture filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CAPTURE_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (TimeraFilterSourceTrig == enFilterPort) + { + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + } + else + { + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enFilterPort); + pstcTimeraCapture->NOFIENCP = enNewSta; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera capture value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera capture value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CapVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CapVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CapVal; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit orthogonal coding function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcCodingInit Pointer to timera orthogonal coding configuration + ** \arg See the struct #stc_timera_orthogonal_coding_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCodingInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCodingInit)) + { + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enTrigClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkBClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkAClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enTrigFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkBFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkAFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitUnderflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitUnderflowEn)); + + /* Configure hardware increase event register */ + TIMERAx->HCUPR_f.HCUP0 = pstcCodingInit->enIncClkALowAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP1 = pstcCodingInit->enIncClkALowAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP2 = pstcCodingInit->enIncClkAHighAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP3 = pstcCodingInit->enIncClkAHighAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP4 = pstcCodingInit->enIncClkBLowAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP5 = pstcCodingInit->enIncClkBLowAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP6 = pstcCodingInit->enIncClkBHighAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP7 = pstcCodingInit->enIncClkBHighAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP8 = pstcCodingInit->enIncTrigRisingEn; + TIMERAx->HCUPR_f.HCUP9 = pstcCodingInit->enIncTrigFallingEn; + TIMERAx->HCUPR_f.HCUP10 = pstcCodingInit->enIncSpecifyEventTriggerEn; + TIMERAx->HCUPR_f.HCUP11 = pstcCodingInit->enIncAnotherUnitOverflowEn; + TIMERAx->HCUPR_f.HCUP12 = pstcCodingInit->enIncAnotherUnitUnderflowEn; + + /* Configure hardware decrease event register */ + TIMERAx->HCDOR_f.HCDO0 = pstcCodingInit->enDecClkALowAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO1 = pstcCodingInit->enDecClkALowAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO2 = pstcCodingInit->enDecClkAHighAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO3 = pstcCodingInit->enDecClkAHighAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO4 = pstcCodingInit->enDecClkBLowAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO5 = pstcCodingInit->enDecClkBLowAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO6 = pstcCodingInit->enDecClkBHighAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO7 = pstcCodingInit->enDecClkBHighAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO8 = pstcCodingInit->enDecTrigRisingEn; + TIMERAx->HCDOR_f.HCDO9 = pstcCodingInit->enDecTrigFallingEn; + TIMERAx->HCDOR_f.HCDO10 = pstcCodingInit->enDecSpecifyEventTriggerEn; + TIMERAx->HCDOR_f.HCDO11 = pstcCodingInit->enDecAnotherUnitOverflowEn; + TIMERAx->HCDOR_f.HCDO12 = pstcCodingInit->enDecAnotherUnitUnderflowEn; + + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCodingInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCodingInit->enTrigFilterEn; + TIMERAx->FCONR_f.NOFICKCB = pstcCodingInit->enClkBClkDiv; + TIMERAx->FCONR_f.NOFIENCB = pstcCodingInit->enClkBFilterEn; + TIMERAx->FCONR_f.NOFICKCA = pstcCodingInit->enClkAClkDiv; + TIMERAx->FCONR_f.NOFIENCA = pstcCodingInit->enClkAFilterEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16CodingCnt Timera orthogonal coding value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16CodingCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera orthogonal coding value + ** + ******************************************************************************/ +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CodingCnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CodingCnt = (uint16_t)TIMERAx->CNTER; + } + + return u16CodingCnt; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera orthogonal coding filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera orthogonal coding filter input port + ** \arg TimeraFilterSourceClkA TIMA__CLKA input port + ** \arg TimeraFilterSourceClkB TIMA__CLKB input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera orthogonal coding filter + ** \arg Enable Enable timera orthogonal coding filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CODING_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enFilterPort) + { + case TimeraFilterSourceClkA: + TIMERAx->FCONR_f.NOFIENCA = enNewSta; + break; + case TimeraFilterSourceClkB: + TIMERAx->FCONR_f.NOFIENCB = enNewSta; + break; + case TimeraFilterSourceTrig: + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit hardware trigger event function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwTriggerInit Pointer to timera hardware trigger event configuration + ** \arg See the struct #stc_timera_hw_trigger_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwTriggerInit == NULL + ** + ** \note If sync startup(BCSTR.SYNST) bit set 1 trigger hardware sync startup when HCONR.HSTA1~0 bit set + ** + ******************************************************************************/ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwTriggerInit)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn)); + + /* Configure hardware startup conditions */ + TIMERAx->HCONR_f.HSTA0 = pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn; + + /* Configure hardware stop conditions */ + TIMERAx->HCONR_f.HSTP0 = pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn; + + /* Configure hardware clear conditions */ + TIMERAx->HCONR_f.HCLE0 = pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware startup Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStartup Pointer to timera hardware startup configuration + ** \arg See the struct #stc_timera_hw_startup_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStartup == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStartup)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enSpecifyEventStartupEn)); + + TIMERAx->HCONR_f.HSTA0 = pstcHwStartup->enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwStartup->enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwStartup->enSpecifyEventStartupEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware stop Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStop Pointer to timera hardware stop configuration + ** \arg See the struct #stc_timera_hw_stop_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStop == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStop)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enSpecifyEventStopEn)); + + TIMERAx->HCONR_f.HSTP0 = pstcHwStop->enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwStop->enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwStop->enSpecifyEventStopEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware clear Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwClear Pointer to timera hardware clear configuration + ** \arg See the struct #stc_timera_hw_clear_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwClear == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwClear)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3FallingClearEn)); + + TIMERAx->HCONR_f.HCLE0 = pstcHwClear->enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwClear->enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwClear->enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwClear->enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwClear->enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwClear->enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwClear->enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera interrupt request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enIrq Timera interrupt request + ** \arg TimeraIrqCaptureOrCompareCh1 Channel 1 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh2 Channel 2 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh3 Channel 3 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh4 Channel 4 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh5 Channel 5 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh6 Channel 6 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh7 Channel 7 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh8 Channel 8 interrupt request + ** \arg TimeraIrqOverflow Count overflow interrupt request + ** \arg TimeraIrqUnderflow Count underflow interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera interrupt request + ** \arg Enable Enable timera interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case TimeraIrqCaptureOrCompareCh1: + TIMERAx->ICONR_f.ITEN1 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh2: + TIMERAx->ICONR_f.ITEN2 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh3: + TIMERAx->ICONR_f.ITEN3 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh4: + TIMERAx->ICONR_f.ITEN4 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh5: + TIMERAx->ICONR_f.ITEN5 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh6: + TIMERAx->ICONR_f.ITEN6 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh7: + TIMERAx->ICONR_f.ITEN7 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh8: + TIMERAx->ICONR_f.ITEN8 = enNewSta; + break; + case TimeraIrqOverflow: + TIMERAx->BCSTR_f.ITENOVF = enNewSta; + break; + case TimeraIrqUnderflow: + TIMERAx->BCSTR_f.ITENUDF = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera event request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera event request channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera event request + ** \arg Enable Enable timera event request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + switch (enChannel) + { + case TimeraCh1: + TIMERAx->ECONR_f.ETEN1 = enNewSta; + break; + case TimeraCh2: + TIMERAx->ECONR_f.ETEN2 = enNewSta; + break; + case TimeraCh3: + TIMERAx->ECONR_f.ETEN3 = enNewSta; + break; + case TimeraCh4: + TIMERAx->ECONR_f.ETEN4 = enNewSta; + break; + case TimeraCh5: + TIMERAx->ECONR_f.ETEN5 = enNewSta; + break; + case TimeraCh6: + TIMERAx->ECONR_f.ETEN6 = enNewSta; + break; + case TimeraCh7: + TIMERAx->ECONR_f.ETEN7 = enNewSta; + break; + case TimeraCh8: + TIMERAx->ECONR_f.ETEN8 = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF1; + break; + case TimeraFlagCaptureOrCompareCh2: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF2; + break; + case TimeraFlagCaptureOrCompareCh3: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF3; + break; + case TimeraFlagCaptureOrCompareCh4: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF4; + break; + case TimeraFlagCaptureOrCompareCh5: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF5; + break; + case TimeraFlagCaptureOrCompareCh6: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF6; + break; + case TimeraFlagCaptureOrCompareCh7: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF7; + break; + case TimeraFlagCaptureOrCompareCh8: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF8; + break; + case TimeraFlagOverflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.OVFF; + break; + case TimeraFlagUnderflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.UDFF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + TIMERAx->STFLR_f.CMPF1 = 0u; + break; + case TimeraFlagCaptureOrCompareCh2: + TIMERAx->STFLR_f.CMPF2 = 0u; + break; + case TimeraFlagCaptureOrCompareCh3: + TIMERAx->STFLR_f.CMPF3 = 0u; + break; + case TimeraFlagCaptureOrCompareCh4: + TIMERAx->STFLR_f.CMPF4 = 0u; + break; + case TimeraFlagCaptureOrCompareCh5: + TIMERAx->STFLR_f.CMPF5 = 0u; + break; + case TimeraFlagCaptureOrCompareCh6: + TIMERAx->STFLR_f.CMPF6 = 0u; + break; + case TimeraFlagCaptureOrCompareCh7: + TIMERAx->STFLR_f.CMPF7 = 0u; + break; + case TimeraFlagCaptureOrCompareCh8: + TIMERAx->STFLR_f.CMPF8 = 0u; + break; + case TimeraFlagOverflow: + TIMERAx->BCSTR_f.OVFF = 0u; + break; + case TimeraFlagUnderflow: + TIMERAx->BCSTR_f.UDFF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set counter event trigger source + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR0_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set capture event trigger source + ** + ** \param [in] enTriggerSrc Capture event trigger source + ** \arg 0-511 Used to trigger the capture function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA counter common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR0 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR0 &= ~u32ComTrig; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA capture common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR1 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR1 &= ~u32ComTrig; + } + + return enRet; +} + +//@} // TimeraGroup + +#endif /* DDL_TIMERA_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c new file mode 100644 index 000000000..95a994abe --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c @@ -0,0 +1,263 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.c + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_trng.h" +#include "hc32f460_utility.h" + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup TrngGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for TRNG load control. */ +#define IS_TRNG_LOAD_CTRL(CTRL) \ +( ((CTRL) == TrngLoadNewInitValue_Enable) || \ + ((CTRL) == TrngLoadNewInitValue_Disable)) + +/*! Parameter validity check for TRNG shift count. */ +#define IS_TRNG_SHIFT_COUNT(COUNT) \ +( ((COUNT) == TrngShiftCount_32) || \ + ((COUNT) == TrngShiftCount_64) || \ + ((COUNT) == TrngShiftCount_128) || \ + ((COUNT) == TrngShiftCount_256)) + + +#define RANDOM_NUM_LENGTH (2u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the TRNG. + ** + ** \param [in] pstcInit Pointer to TRNG initialization structure. + ** \arg enLoadCtrl + ** \- TrngLoadNewInitValue_Enable Data register load new initial value before + ** random number is generated. + ** \- TrngLoadNewInitValue_Disable Data register do not load new initial value + ** before random number is generated. + ** + ** \arg enShiftCount Shift count control bit when capturing random noise. + ** \- TrngShiftCount_32 Shift 32 times. + ** \- TrngShiftCount_64 Shift 64 times. + ** \- TrngShiftCount_128 Shift 128 times. + ** \- TrngShiftCount_256 Shift 256 times. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + /* Parameter validity check */ + DDL_ASSERT(IS_TRNG_LOAD_CTRL(pstcInit->enLoadCtrl)); + DDL_ASSERT(IS_TRNG_SHIFT_COUNT(pstcInit->enShiftCount)); + + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + M4_TRNG->MR_f.LOAD = pstcInit->enLoadCtrl; + M4_TRNG->MR_f.CNT = pstcInit->enShiftCount; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_DeInit(void) +{ + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + /* Set the value of all registers to the reset value. */ + M4_TRNG->CR = 0u; + M4_TRNG->MR = 0x12ul; + M4_TRNG->DR0 = 0x08000000ul; + M4_TRNG->DR0 = 0x08000200ul; +} + +/** + ******************************************************************************* + ** \brief Start TRNG and generate random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout TRNG works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TrngTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu32Random) && (0u != u32Timeout) && (0u != u8Length)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32TrngTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; + + /* wait generation done and check if timeout. */ + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32TrngTimeout) + { + if (bM4_TRNG_CR_RUN == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (Ok == enRet) + { + /* read the random number. */ + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + } + + /* Stop TRNG generating. */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit. */ + bM4_TRNG_CR_EN = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start TRNG only. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_StartIT(void) +{ + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; +} + +/** + ******************************************************************************* + ** \brief Get random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length) +{ + if ((NULL != pu32Random) && (0u != u8Length)) + { + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + + /* Stop TRNG generating */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + } +} + +//@} // TrngGroup + +#endif /* DDL_TRNG_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c new file mode 100644 index 000000000..8ad561449 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c @@ -0,0 +1,1640 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.c + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_usart.h" +#include "hc32f460_utility.h" + +#if (DDL_USART_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup UsartGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_USART(__USARTx__) \ +( (M4_USART1 == (__USARTx__)) || \ + (M4_USART2 == (__USARTx__)) || \ + (M4_USART3 == (__USARTx__)) || \ + (M4_USART4 == (__USARTx__))) + +/*!< Parameter valid check for USART clock prescale. */ +#define IS_VALID_USART_CLK_DIV(x) \ +( (UsartClkDiv_1 == (x)) || \ + (UsartClkDiv_4 == (x)) || \ + (UsartClkDiv_16 == (x)) || \ + (UsartClkDiv_64 == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_FUNC(x) \ +( (UsartRx == (x)) || \ + (UsartTx == (x)) || \ + (UsartCts == (x)) || \ + (UsartRxInt == (x)) || \ + (UsartTimeOut == (x)) || \ + (UsartSmartCard == (x)) || \ + (UsartSilentMode == (x)) || \ + (UsartTxEmptyInt == (x)) || \ + (UsartTimeOutInt == (x)) || \ + (UsartTxCmpltInt == (x)) || \ + (UsartParityCheck == (x)) || \ + (UsartNoiseFilter == (x)) || \ + (UsartFracBaudrate == (x)) || \ + (UsartMulProcessor == (x)) || \ + (UsartTxAndTxEmptyInt == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_STATUS(x) \ +( (UsartRxMpb == (x)) || \ + (UsartTxEmpty == (x)) || \ + (UsartFrameErr == (x)) || \ + (UsartRxNoEmpty == (x)) || \ + (UsartRxTimeOut == (x)) || \ + (UsartParityErr == (x)) || \ + (UsartOverrunErr == (x)) || \ + (UsartTxComplete == (x))) + +/*!< Parameter valid check for USART clock mode. */ +#define IS_VALID_USART_CLK_MODE(x) \ +( (UsartExtClk == (x)) || \ + (UsartIntClkCkOutput == (x)) || \ + (UsartIntClkCkNoOutput == (x))) + +/*!< Parameter valid check for USART stop bit. */ +#define IS_VALID_USART_STOP_BIT(x) \ +( (UsartOneStopBit == (x)) || \ + (UsartTwoStopBit == (x))) + +/*!< Parameter valid check for USART parity bit. */ +#define IS_VALID_USART_PARITY_BIT(x) \ +( (UsartParityOdd == (x)) || \ + (UsartParityEven == (x)) || \ + (UsartParityNone == (x))) + +/*!< Parameter valid check for USART data length. */ +#define IS_VALID_USART_DATA_LEN(x) \ +( (UsartDataBits8 == (x)) || \ + (UsartDataBits9 == (x))) + +/*!< Parameter valid check for USART data direction. */ +#define IS_VALID_USART_DATA_DIR(x) \ +( (UsartDataLsbFirst == (x)) || \ + (UsartDataMsbFirst == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_SAMPLE_MODE(x) \ +( (UsartSampleBit8 == (x)) || \ + (UsartSampleBit16 == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_HW_FLOW_MODE(x) \ +( (UsartRtsEnable == (x)) || \ + (UsartCtsEnable == (x))) + +/*!< Parameter valid check for USART detect mode. */ +#define IS_VALID_USART_SB_DETECT_MODE(x) \ +( (UsartStartBitLowLvl == (x)) || \ + (UsartStartBitFallEdge == (x))) + +/*!< Parameter valid check for USART mode. */ +#define IS_VALID_USART_MODE(x) \ +( (UsartUartMode == (x)) || \ + (UsartClkSyncMode == (x)) || \ + (UsartSmartCardMode == (x))) + +/*!< Parameter valid check for USART ETU clocks number. */ +#define IS_VALID_USART_ETU_CLK(x) \ +( (UsartScEtuClk32 == (x)) || \ + (UsartScEtuClk64 == (x)) || \ + (UsartScEtuClk128 == (x)) || \ + (UsartScEtuClk256 == (x)) || \ + (UsartScEtuClk372 == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx); +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize UART mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to USART mode configure structure + ** \arg This parameter detail refer @ref stc_usart_uart_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_STOP_BIT(pstcInitCfg->enStopBit)); + DDL_ASSERT(IS_VALID_USART_PARITY_BIT(pstcInitCfg->enParity)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_DATA_LEN(pstcInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(pstcInitCfg->enSampleMode)); + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(pstcInitCfg->enDetectMode)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set USART mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)0ul; + + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR1_f.M = (uint32_t)(pstcInitCfg->enDataLength); + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.STOP = (uint32_t)(pstcInitCfg->enStopBit); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + + switch(pstcInitCfg->enParity) + { + case UsartParityNone: + CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + CR1_f.PS = (uint32_t)0ul; + CR1_f.PCE = (uint32_t)1ul; + break; + case UsartParityOdd: + CR1_f.PS = (uint32_t)1ul; + CR1_f.PCE = (uint32_t)1ul; + break; + default: + break; + } + + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + CR1_f.SBS = (uint32_t)(pstcInitCfg->enDetectMode); + CR1_f.OVER8 = (uint32_t)(pstcInitCfg->enSampleMode); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Initialize clock sync mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to clock sync mode configure structure + ** \arg This parameter detail refer @ref stc_usart_clksync_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set Clock Sync mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize smart card mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to smart card mode configure structure + ** \arg This parameter detail refer @ref stc_usart_sc_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + CR1_f.PCE = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.SCEN = (uint32_t)1ul; /* Set USART mode */ + CR3_f.BCN = (uint32_t)UsartScEtuClk372; /* ETU = 372 * CK */ + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Ok USART is de-initialized normally + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus Choose need get status's flag + ** \arg UsartParityError Parity check error + ** \arg UsartFrameError Frame error + ** \arg UsartOverRunError Overrun error + ** \arg UsartRxRegNoEmpty Rx register is no empty + ** \arg UsartTxComplete Transfer completely + ** \arg UsartTxRegNoEmpty Tx register is no empty + ** \arg UsartRxTimeOut Data receive timeout + ** \arg UsartRxDataType Data is multiple processor id or normal data. + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + DDL_ASSERT(IS_VALID_USART_STATUS(enStatus)); + + return ((USARTx->SR & enStatus) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified USART status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus The specified status + ** \arg UsartParityErr Parity check error + ** \arg UsartFrameErr Frame error + ** \arg UsartOverRunErr Overrun error + ** \arg UsartRxTimeOut Data receive timeout + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enStatus is invalid + ** + ******************************************************************************/ +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch (enStatus) + { + case UsartParityErr: + USARTx->CR1_f.CPE = 1ul; + break; + case UsartFrameErr: + USARTx->CR1_f.CFE = 1ul; + break; + case UsartOverrunErr: + USARTx->CR1_f.CORE = 1ul; + break; + case UsartRxTimeOut: + USARTx->CR1_f.CRTOF = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure USART function. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enFunc USART function selection + ** \arg UsartTimeOut UART RX timeout function + ** \arg UsartTimeOutInt UART RX timeout interrupt function + ** \arg UsartRx UART RX function + ** \arg UsartTx UART TX function + ** \arg UsartSilentMode USART silent function + ** \arg UsartRxInt USART RX interrupt function + ** \arg UsartTxCmpltInt USART TX complete interrupt function + ** \arg UsartTxEmptyInt USART TX empty interrupt function + ** \arg UsartParityCheck USART Parity check function + ** \arg UsartFracBaudrate USART fractional baudrate function + ** \arg UsartNoiseFilter USART noise filter function + ** \param [in] enCmd USART functional state + ** \arg Enable Enable the specified USART function + ** \arg Disable Disable the specified USART function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx == NULL + ** + ******************************************************************************/ +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd) +{ + uint32_t u32Addr; + __IO stc_usart_cr1_field_t CR1_f; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enFunc) + { + case UsartRx: + USARTx->CR1_f.RE = (uint32_t)enCmd; + break; + case UsartRxInt: + USARTx->CR1_f.RIE = (uint32_t)enCmd; + break; + case UsartTx: + USARTx->CR1_f.TE = (uint32_t)enCmd; + break; + case UsartTxEmptyInt: + USARTx->CR1_f.TXEIE = (uint32_t)enCmd; + break; + case UsartTimeOut: + USARTx->CR1_f.RTOE = (uint32_t)enCmd; + break; + case UsartTimeOutInt: + USARTx->CR1_f.RTOIE = (uint32_t)enCmd; + break; + case UsartSilentMode: + USARTx->CR1_f.SLME = (uint32_t)enCmd; + break; + case UsartParityCheck: + USARTx->CR1_f.PCE = (uint32_t)enCmd; + break; + case UsartNoiseFilter: + USARTx->CR1_f.NFE = (uint32_t)enCmd; + break; + case UsartTxCmpltInt: + USARTx->CR1_f.TCIE = (uint32_t)enCmd; + break; + case UsartTxAndTxEmptyInt: + CR1_f = USARTx->CR1_f; + CR1_f.TE = (uint32_t)enCmd; + CR1_f.TXEIE = (uint32_t)enCmd; + u32Addr = (uint32_t)&CR1_f; + USARTx->CR1 = *(__IO uint32_t *)u32Addr; + break; + case UsartFracBaudrate: + USARTx->CR1_f.FBME = (uint32_t)enCmd; + break; + case UsartMulProcessor: + USARTx->CR2_f.MPE = (uint32_t)enCmd; + break; + case UsartSmartCard: + USARTx->CR3_f.SCEN = (uint32_t)enCmd; + break; + case UsartCts: + USARTx->CR3_f.CTSE = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enParity USART parity selection + ** \arg UsartParityNone USART none parity + ** \arg UsartParityEven USART even parity + ** \arg UsartParityOdd USART odd parity + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enParity is invalid + ** + ******************************************************************************/ +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enParity) + { + case UsartParityNone: + USARTx->CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + USARTx->CR1_f.PS = (uint32_t)0ul; + USARTx->CR1_f.PCE = (uint32_t)1u; + break; + case UsartParityOdd: + USARTx->CR1_f.PS = (uint32_t)1ul; + USARTx->CR1_f.PCE = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartParityNone USART none parity + ** \retval UsartParityEven USART even parity + ** \retval UsartParityOdd USART odd parity + ** + ******************************************************************************/ +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx) +{ + en_usart_parity_t enParity = UsartParityNone; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if(0ul == USARTx->CR1_f.PCE) + { + enParity = UsartParityNone; + } + else if(0ul == USARTx->CR1_f.PS) + { + enParity = UsartParityEven; + } + else + { + enParity = UsartParityOdd; + } + + return enParity; +} + +/** + ******************************************************************************* + ** \brief Set USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enSampleMode USART parity selection + ** \arg UsartSampleBit16 16 Bit + ** \arg UsartSampleBit8 8 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(enSampleMode)); + + USARTx->CR1_f.OVER8 = (uint32_t)enSampleMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartSampleBit16 16 Bit + ** \retval UsartSampleBit8 8 Bit + ** + ******************************************************************************/ +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sample_mode_t)USARTx->CR1_f.OVER8; +} + +/** + ******************************************************************************* + ** \brief Set USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDir USART data direction selection + ** \arg UsartDataLsbFirst USART data LSB first + ** \arg UsartDataMsbFirst USART data MSB first + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetTransferDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_DIR(enDir)); + + USARTx->CR1_f.ML = (uint32_t)enDir; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataLsbFirst USART data LSB first + ** \retval UsartDataMsbFirst USART data MSB first + ** + ******************************************************************************/ +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_dir_t)(USARTx->CR1_f.ML); +} + +/** + ******************************************************************************* + ** \brief Set USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDataLen USART data bit length + ** \arg UsartDataBits8 8 Bit + ** \arg UsartDataBits8 9 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_LEN(enDataLen)); + + USARTx->CR1_f.M = (uint32_t)enDataLen; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataBits8 Data bit length:8 Bits + ** \retval UsartDataBits8 Data bit length:9 Bits + ** + ******************************************************************************/ +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_len_t)(USARTx->CR1_f.M); +} + +/** + ******************************************************************************* + ** \brief Set USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkMode USART clock mode selection + ** \arg UsartExtClk Select external clock source + ** \arg UsartIntClkCkOutput Select internal clock source and output clock + ** \arg UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_MODE(enClkMode)); + + USARTx->CR2_f.CLKC = (uint32_t)enClkMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartExtClk Select external clock source + ** \retval UsartIntClkCkOutput Select internal clock source and output clock + ** \retval UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ******************************************************************************/ +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_mode_t)(USARTx->CR2_f.CLKC); +} + +/** + ******************************************************************************* + ** \brief Set USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enMode USART clock mode selection + ** \arg UsartUartMode UART mode + ** \arg UsartClkSyncMode Clock sync mode + ** \arg UsartSmartCardMode Smart card mode + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enMode is invalid + ** + ******************************************************************************/ +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enMode) + { + case UsartUartMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)0ul; + break; + case UsartClkSyncMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)1ul; + break; + case UsartSmartCardMode: + USARTx->CR3_f.SCEN = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartUartMode UART mode + ** \retval UsartClkSyncMode Clock sync mode + ** \retval UsartSmartCardMode Smart card mode + ** + ******************************************************************************/ +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx) +{ + en_usart_mode_t enMode; + + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if (1ul == USARTx->CR3_f.SCEN) + { + enMode = UsartSmartCardMode; + } + else if (1ul == USARTx->CR1_f.MS) + { + enMode = UsartClkSyncMode; + } + else + { + enMode = UsartUartMode; + } + + return enMode; +} + +/** + ******************************************************************************* + ** \brief Set USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStopBit USART stop bit selection + ** \arg UsartOneStopBit 1 Stop Bit + ** \arg UsartTwoStopBits 2 Stop Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_STOP_BIT(enStopBit)); + + USARTx->CR2_f.STOP = (uint32_t)enStopBit; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartOneStopBit 1 Stop Bit + ** \retval UsartTwoStopBits 2 Stop Bit + ** + ******************************************************************************/ +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_stop_bit_t)(USARTx->CR2_f.STOP); +} + +/** + ******************************************************************************* + ** \brief Set USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDetectMode USART start bit detect mode + ** \arg UsartStartBitLowLvl Start bit: RD pin low level + ** \arg UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(enDetectMode)); + + USARTx->CR1_f.SBS = (uint32_t)enDetectMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartStartBitLowLvl Start bit: RD pin low level + ** \retval UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ******************************************************************************/ +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sb_detect_mode_t)(USARTx->CR1_f.SBS); +} + + +/** + ******************************************************************************* + ** \brief Set USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enHwFlowCtrl Hardware flow control + ** \arg UsartRtsEnable Enable RTS + ** \arg UsartCtsEnable Enable CTS + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(enHwFlowCtrl)); + + USARTx->CR3_f.CTSE = (uint32_t)enHwFlowCtrl; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartRtsEnable Enable RTS + ** \retval UsartCtsEnable Enable CTS + ** + ******************************************************************************/ +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_hw_flow_ctrl_t)(USARTx->CR3_f.CTSE); +} + +/** + ******************************************************************************* + ** \brief Set USART clock prescale. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkPrescale USART clock prescale + ** \arg UsartClkDiv_0 PCLK/1 + ** \arg UsartClkDiv_4 PCLK/4 + ** \arg UsartClkDiv_16 PCLK/16 + ** \arg UsartClkDiv_64 PCLK/64 + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(enClkPrescale)); + + USARTx->PR_f.PSC = (uint32_t)enClkPrescale; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock division. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartClkDiv_0 PCLK/1 + ** \retval UsartClkDiv_4 PCLK/4 + ** \retval UsartClkDiv_16 PCLK/16 + ** \retval UsartClkDiv_64 PCLK/64 + ** + ******************************************************************************/ +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_div_t)(USARTx->PR_f.PSC); +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enEtuClk ETU clocks of smart card + ** \arg UsartScEtuClk32 1 etu = 32/f + ** \arg UsartScEtuClk64 1 etu = 64/f + ** \arg UsartScEtuClk93 1 etu = 93/f + ** \arg UsartScEtuClk128 1 etu = 128/f + ** \arg UsartScEtuClk186 1 etu = 186/f + ** \arg UsartScEtuClk256 1 etu = 256/f + ** \arg UsartScEtuClk372 1 etu = 372/f + ** \arg UsartScEtuClk512 1 etu = 512/f + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_ETU_CLK(enEtuClk)); + + USARTx->CR3_f.BCN = (uint32_t)enEtuClk; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartScEtuClk32 1 etu = 32/f + ** \retval UsartScEtuClk64 1 etu = 64/f + ** \retval UsartScEtuClk93 1 etu = 93/f + ** \retval UsartScEtuClk128 1 etu = 128/f + ** \retval UsartScEtuClk186 1 etu = 186/f + ** \retval UsartScEtuClk256 1 etu = 256/f + ** \retval UsartScEtuClk372 1 etu = 372/f + ** \retval UsartScEtuClk512 1 etu = 512/f + ** + ******************************************************************************/ +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sc_etu_clk_t)(USARTx->CR3_f.BCN); +} + +/** + ****************************************************************************** + ** \brief Write UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** + ******************************************************************************/ +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + USARTx->DR_f.TDR = (uint32_t)u16Data; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Read UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t USART_RecData(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return ((uint16_t)(USARTx->DR_f.RDR)); +} + +/** + ******************************************************************************* + ** \brief Set USART baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + if(1ul == USARTx->CR3_f.SCEN) + { + enRet = SetScBaudrate(USARTx, u32Baudrate); + } + else if(1ul == USARTx->CR1_f.MS) + { + enRet = SetClkSyncBaudrate(USARTx, u32Baudrate); + } + else + { + enRet = SetUartBaudrate(USARTx, u32Baudrate); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set UART mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t OVER8 = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + OVER8 = USARTx->CR1_f.OVER8; + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)2ul - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(2048ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set smart card mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t S = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + const uint16_t au16EtuClkCnts[] = {32u, 64u, 93u, 128u, 186u, 256u, 372u, 512u}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + S = au16EtuClkCnts[USARTx->CR3_f.BCN]; + + /* FBME = 0 Calculation formula */ + /* B = C / (2 * S * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * S)) - 1 */ + DIV = ((float)C / ((float)B * (float)S * 2.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / ((2 * S) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((2 * S) * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * S * 512 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * B * S); + DIV_Fraction = (uint32_t)(512ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t C = 0ul; + uint32_t B = 0ul; + uint64_t u64Tmp = 0u; + float32_t DIV = 0.0f; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + if (C > 0ul) + { + B = u32Baudrate; + + /* FBME = 0 Calculation formula */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV = ((float)C / ((float)B * 4.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (4 * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * 1024 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(1024ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval USART clock frequency + ** + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx) +{ + uint32_t u32PClk1 = 0ul; + uint32_t u32UartClk = 0ul; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + u32PClk1 = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.PCLK1S); + u32UartClk = u32PClk1 / (1ul << (2ul * USARTx->PR_f.PSC)); + + return u32UartClk; +} + +//@} // UsartGroup + +#endif /* DDL_USART_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c new file mode 100644 index 000000000..e619d64f5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c @@ -0,0 +1,531 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.c + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_utility.h" + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DdlUtilityGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#if (DDL_PRINT_ENABLE == DDL_ON) +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_UART(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x))) + +#define UART_EnableClk(x) \ +do { \ + if (M4_USART1 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART1 = 0ul; \ + } \ + else if (M4_USART2 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART2 = 0ul; \ + } \ + else if (M4_USART3 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART3 = 0ul; \ + } \ + else \ + { \ + M4_MSTP->FCG1_f.USART4 = 0ul; \ + } \ +} while (0) +#endif + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (DDL_PRINT_ENABLE == DDL_ON) +static M4_USART_TypeDef *m_PrintfDevice; +static uint32_t m_u32PrintfTimeout; +#endif + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +#if (DDL_PRINT_ENABLE == DDL_ON) +/** + ******************************************************************************* + ** \brief UART transmit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] cData The data for transmitting + ** + ** \retval An en_result_t enumeration value: + ** - Ok: Send successfully + ** - ErrorTimeout: Send timeout + ** - ErrorInvalidParameter: The parameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData) +{ + uint32_t u32TxEmpty; + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32Timeout = m_u32PrintfTimeout; + + if (NULL != USARTx) + { + /* Wait TX data register empty */ + do + { + u32Timeout--; + u32TxEmpty = USARTx->SR_f.TXE; + } while ((u32Timeout > 0ul) && (0ul == u32TxEmpty)); + + if (u32TxEmpty > 0ul) + { + USARTx->DR = (uint32_t)cData; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, uint32_t u32Baudrate) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t DIV; + uint64_t u64Tmp; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + uint32_t u32PClk1; + uint32_t u32UartClk; + en_result_t enRet = ErrorInvalidParameter; + + u32PClk1 = SystemCoreClock / (1ul << (M4_SYSREG->CMU_SCFGR_f.PCLK1S)); + u32UartClk = u32PClk1 / (1ul << (2ul * (USARTx->PR_f.PSC))); + + B = u32Baudrate; + C = u32UartClk; + DIV_Fraction = 0ul; + + if ((0ul != C) && (0ul != B)) + { + OVER8 = USARTx->CR1_f.OVER8; + + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if ((DIV < 0.0f) || (DIV_Integer > 0xFFul)) + { + enRet = ErrorInvalidParameter; + } + else + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (2u - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1u) * (uint64_t)B; + DIV_Fraction = (uint32_t)(2048ul * u64Tmp/C - 128ul); + } + + USARTx->CR1_f.FBME = (DIV_Fraction > 0UL) ? 1ul : 0ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + enRet = Ok; + } + } + + return enRet; +} + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + ******************************************************************************* + ** \brief Re-target _write function. + ** + ** \param [in] fd + ** \param [in] data + ** \param [in] size + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) + { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) + { + if (Ok != UartPutChar(m_PrintfDevice, data[i])) + { + break; + } + } + } + + return i ? i : -1; +} + +#else +/** + ******************************************************************************* + ** \brief Re-target fputc function. + ** + ** \param [in] ch + ** \param [in] f + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (Ok == UartPutChar(m_PrintfDevice, (char)ch)) ? ch: -1; +} +#endif + +/** + ******************************************************************************* + ** \brief Debug printf initialization function + ** + ** \param [in] UARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** \param [in] PortInit The pointer of printf port initialization function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_UART(UARTx) && (0ul != u32Baudrate) && (NULL != PortInit)) + { + /* Initialize port */ + PortInit(); + + /* Enable clock */ + UART_EnableClk(UARTx); + + /* Initialize USART */ + UARTx->CR1_f.ML = 0ul; /* LSB */ + UARTx->CR1_f.MS = 0ul; /* UART mode */ + UARTx->CR1_f.OVER8 = 1ul; /* 8bit sampling mode */ + UARTx->CR1_f.M = 0ul; /* 8 bit data length */ + UARTx->CR1_f.PCE = 0ul; /* no parity bit */ + + /* Set baudrate */ + if(Ok != SetUartBaudrate(UARTx, u32Baudrate)) + { + enRet = Error; + } + else + { + UARTx->CR2 = 0ul; /* 1 stop bit, single uart mode */ + UARTx->CR3 = 0ul; /* CTS disable, Smart Card mode disable */ + UARTx->CR1_f.TE = 1ul; /* TX enable */ + + m_PrintfDevice = UARTx; + m_u32PrintfTimeout = (SystemCoreClock / u32Baudrate); + } + } + + return enRet; +} +#endif /* DDL_PRINT_ENABLE */ + +/** + ******************************************************************************* + ** \brief Delay function, delay 1ms approximately + ** + ** \param [in] u32Cnt ms + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1ms(uint32_t u32Cnt) +{ + volatile uint32_t i; + uint32_t u32Cyc; + + u32Cyc = SystemCoreClock; + u32Cyc = u32Cyc / 10000ul; + while (u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief Delay function, delay 1us approximately + ** + ** \param [in] u32Cnt us + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1us(uint32_t u32Cnt) +{ + uint32_t u32Cyc; + volatile uint32_t i; + + if(SystemCoreClock > 10000000ul) + { + u32Cyc = SystemCoreClock / 10000000ul; + while(u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } + } + else + { + while(u32Cnt-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief This function Initializes the interrupt frequency of the SysTick. + ** + ** \param [in] u32Freq SysTick interrupt frequency (1 to 1000). + ** + ** \retval Ok SysTick Initializes succeed + ** \retval Error SysTick Initializes failed + ** + ******************************************************************************/ +__WEAKDEF en_result_t SysTick_Init(uint32_t u32Freq) +{ + en_result_t enRet = Error; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) + { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(SystemCoreClock / u32Freq)) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief This function provides minimum delay (in milliseconds). + ** + ** \param [in] u32Delay Delay specifies the delay time. + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) + { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) + { + tickEnd = tickMax; + } + else + { + tickEnd = u32Delay + m_u32TickStep; + } + + while ((SysTick_GetTick() - tickStart) < tickEnd) + { + } + } +} + +/** + ******************************************************************************* + ** \brief This function is called to increment a global variable "u32TickCount". + ** \note This variable is incremented in SysTick ISR. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + ******************************************************************************* + ** \brief Provides a tick value in millisecond. + ** + ** \param None + ** + ** \retval Tick value + ** + ******************************************************************************/ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + ******************************************************************************* + ** \brief Suspend SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief Resume SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief ddl assert error handle function + ** + ** \param [in] file Point to the current assert the wrong file + ** \param [in] line Point line assert the wrong file in the current + ** + ******************************************************************************/ +#ifdef __DEBUG +__WEAKDEF void Ddl_AssertHandler(uint8_t *file, int16_t line) +{ + /* Users can re-implement this function to print information */ +#if (DDL_PRINT_ENABLE == DDL_ON) + printf("Wrong parameters value: file %s on line %d\r\n", file, line); +#else + (void)file; + (void)line; +#endif + for (;;) + { + ; + } +} +#endif /* __DEBUG */ + +//@} // DdlUtilityGroup + +#endif /* DDL_UTILITY_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c new file mode 100644 index 000000000..c4c56d947 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c @@ -0,0 +1,254 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.c + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_wdt.h" +#include "hc32f460_utility.h" + +#if (DDL_WDT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup WdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter validity check for count cycle */ +#define IS_VALID_COUNT_CYCLE(x) \ +( (WdtCountCycle256 == (x)) || \ + (WdtCountCycle4096 == (x)) || \ + (WdtCountCycle16384 == (x)) || \ + (WdtCountCycle65536 == (x))) + +/*!< Parameter validity check for clock division */ +#define IS_VALID_CLOCK_DIV(x) \ +( (WdtPclk3Div4 == (x)) || \ + (WdtPclk3Div64 == (x)) || \ + (WdtPclk3Div128 == (x)) || \ + (WdtPclk3Div256 == (x)) || \ + (WdtPclk3Div512 == (x)) || \ + (WdtPclk3Div1024 == (x)) || \ + (WdtPclk3Div2048 == (x)) || \ + (WdtPclk3Div8192 == (x))) + +/*!< Parameter validity check for allow refresh percent range */ +#define IS_VALID_ALLOW_REFRESH_RANGE(x) \ +( (WdtRefresh100Pct == (x)) || \ + (WdtRefresh0To25Pct == (x)) || \ + (WdtRefresh25To50Pct == (x)) || \ + (WdtRefresh0To50Pct == (x)) || \ + (WdtRefresh50To75Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To75Pct == (x)) || \ + (WdtRefresh25To75Pct == (x)) || \ + (WdtRefresh0To75Pct == (x)) || \ + (WdtRefresh75To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd75To100Pct == (x)) || \ + (WdtRefresh25To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh0To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh50To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To100Pct == (x)) || \ + (WdtRefresh25To100Pct == (x)) || \ + (WdtRefresh0To100Pct == (x))) + +/*!< Parameter validity check for event request type */ +#define IS_VALID_EVENT_REQUEST_TYPE(x) \ +( (WdtTriggerInterruptRequest == (x)) || \ + (WdtTriggerResetRequest == (x))) + +/*!< Parameter validity check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (WdtFlagCountUnderflow == (x)) || \ + (WdtFlagRefreshError == (x))) + +/*!< WDT_RR register refresh key */ +#define WDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define WDT_REFRESH_END_KEY ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize WDT function + ** + ** \param [in] pstcWdtInit Pointer to WDT init configuration + ** \arg See the struct #stc_wdt_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + en_result_t enRet = Ok; + uint32_t regTemp; + + if (NULL == pstcWdtInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_COUNT_CYCLE(pstcWdtInit->enCountCycle)); + DDL_ASSERT(IS_VALID_CLOCK_DIV(pstcWdtInit->enClkDiv)); + DDL_ASSERT(IS_VALID_ALLOW_REFRESH_RANGE(pstcWdtInit->enRefreshRange)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWdtInit->enSleepModeCountEn)); + DDL_ASSERT(IS_VALID_EVENT_REQUEST_TYPE(pstcWdtInit->enRequestType)); + + /* software start mode */ + regTemp = ((((uint32_t)pstcWdtInit->enRequestType) << 31) | \ + (((uint32_t)(bool)(!pstcWdtInit->enSleepModeCountEn)) << 16) | \ + (((uint32_t)pstcWdtInit->enRefreshRange) << 8) | \ + (((uint32_t)pstcWdtInit->enClkDiv) << 4) | \ + ((uint32_t)pstcWdtInit->enCountCycle)); + /* store the new value */ + M4_WDT->CR = regTemp; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief WDT refresh counter(First refresh start count when software start) + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_WDT->RR = WDT_REFRESH_START_KEY; + M4_WDT->RR = WDT_REFRESH_END_KEY; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get WDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t WDT counter current count value + ** + ******************************************************************************/ +uint16_t WDT_GetCountValue(void) +{ + return ((uint16_t)M4_WDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.UDF; + break; + case WdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + M4_WDT->SR_f.UDF = 0u; + break; + case WdtFlagRefreshError: + M4_WDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // WdtGroup + +#endif /* DDL_WDT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/LICENSE b/bsp/hc32f460/Libraries/LICENSE new file mode 100644 index 000000000..72823826b --- /dev/null +++ b/bsp/hc32f460/Libraries/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2020, Huada Semiconductor Co., Ltd ("HDSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32f460/Libraries/SConscript b/bsp/hc32f460/Libraries/SConscript new file mode 100644 index 000000000..d34278922 --- /dev/null +++ b/bsp/hc32f460/Libraries/SConscript @@ -0,0 +1,47 @@ +# RT-Thread building script for bridge + +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c +HC32F460_StdPeriph_Driver/src/hc32f460_clk.c +HC32F460_StdPeriph_Driver/src/hc32f460_efm.c +HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c +HC32F460_StdPeriph_Driver/src/hc32f460_icg.c +HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c +HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c +HC32F460_StdPeriph_Driver/src/hc32f460_sram.c +HC32F460_StdPeriph_Driver/src/hc32f460_utility.c +HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c +""") + +#src += Glob('HC32F460_StdPeriph_Driver/src/*.c') + +if GetDepend(['RT_USING_SERIAL']): + src += ['HC32F460_StdPeriph_Driver/src/hc32f460_usart.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/HDSC/HC32F460/Source/IAR/startup_hc32f460.s'] + +#add headfile script +path = [cwd + '/CMSIS/Include', + cwd + '/CMSIS/Device/HDSC/HC32F460/Include', + cwd + '/HC32F460_StdPeriph_Driver/inc'] + + +CPPDEFINES = ['USE_DEVICE_DRIVER_LIB', rtconfig.MCU_TYPE, '__DEBUG'] + +group = DefineGroup('HC32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32f460/README.md b/bsp/hc32f460/README.md new file mode 100644 index 000000000..cd49bd5ea --- /dev/null +++ b/bsp/hc32f460/README.md @@ -0,0 +1,59 @@ +# HC32F460PETB# + +## 1. 简介 + +[HC32F460](http://www.hdsc.com.cn/Category83-1487)系列是基于 ARM® Cortex®-M4 32-bit RISC CPU，最高工作频率 200MHz 的高性能MCU。 Cortex-M4 内核集成了浮点运算单元（ FPU） 和 DSP，实现单精度浮点算术运算，支持所有 ARM 单精度数据处理指令和数据类型，支持完整 DSP 指令集。HC32F460 系列集成了高速片上存储器，包括最大 512KB 的 Flash，最大 192KB 的 SRAM。 +主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M4| +|主频| 100MHz | +|SRAM| 192KB | +|Flash| 512KB | + +## 2. 编译说明 + +目前仅支持支持 MDK5，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5(ARM Compiler 5) | MDK5.31 | + +## 3. 烧写及仿真 + +下载程序：使用板载 J-Link 工具。 + +## 4. 驱动支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | USART1/2/3/4 | +| GPIO | 支持 | | +##5.运行结果 +下载程序成功之后，系统会自动运行，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Sep 3 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +6.进阶使用 +默认只开启了 GPIO 输出、中断和 串口4的功能，更多接口需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 5. 联系人信息 + +维护人： + +- [lizhengyang](https://github.com/GoldBr1987) + diff --git a/bsp/hc32f460/SConscript b/bsp/hc32f460/SConscript new file mode 100644 index 000000000..24bb4646a --- /dev/null +++ b/bsp/hc32f460/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32f460/SConstruct b/bsp/hc32f460/SConstruct new file mode 100644 index 000000000..bb318fb96 --- /dev/null +++ b/bsp/hc32f460/SConstruct @@ -0,0 +1,45 @@ +import os +import sys +import rtconfig + +print "############sconstruct##############" +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +print "RTT_ROOT: " + RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'hc32f460.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +print "######################env:" +print env +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32f460/applications/SConscript b/bsp/hc32f460/applications/SConscript new file mode 100644 index 000000000..6f66f7ab7 --- /dev/null +++ b/bsp/hc32f460/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f460/applications/main.c b/bsp/hc32f460/applications/main.c new file mode 100644 index 000000000..dfe9725fd --- /dev/null +++ b/bsp/hc32f460/applications/main.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#include "hc32_ddl.h" +#include +#include +#include "drv_gpio.h" + +/* defined the LED1 pin: PE0 */ +#define LED1_PIN GET_PIN(E,0) +/* defined the LED2 pin: PE0 */ +#define LED2_PIN GET_PIN(E,1) +/* defined the KEY pin: PE13 */ +#define KEY_PIN GET_PIN(E,13) + +#define DELAY_MS (RT_TICK_PER_SECOND) /* 1s */ + +void LED2_Toggle(void *args) +{ + static uint8_t i; + if (i % 2 == 1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + } + else + { + rt_pin_write(LED2_PIN, PIN_LOW); + } + i++; +} + +int32_t main(void) +{ + /* set LED1_PIN output*/ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set LED2_PIN output*/ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + /*set KEY_PIN intput pullup*/ + rt_pin_mode(KEY_PIN, PIN_MODE_INPUT_PULLUP); + /*attach KEY_PIN irq*/ + rt_pin_attach_irq(KEY_PIN, PIN_IRQ_MODE_FALLING, LED2_Toggle, RT_NULL); + /*enable KEY_PIN irq*/ + rt_pin_irq_enable(KEY_PIN, PIN_IRQ_ENABLE); + + + rt_pin_write(LED1_PIN, PIN_HIGH); + while (1) + { + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_delay(DELAY_MS); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_delay(DELAY_MS); + } +} + diff --git a/bsp/hc32f460/board/Kconfig b/bsp/hc32f460/board/Kconfig new file mode 100644 index 000000000..dec846f03 --- /dev/null +++ b/bsp/hc32f460/board/Kconfig @@ -0,0 +1,41 @@ +menu "Hardware Drivers Config" + +config MCU_HC32F460 + bool + select ARCH_ARM_CORTEX_M4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default y + endif + +endmenu + + +endmenu diff --git a/bsp/hc32f460/board/SConscript b/bsp/hc32f460/board/SConscript new file mode 100644 index 000000000..402340a1f --- /dev/null +++ b/bsp/hc32f460/board/SConscript @@ -0,0 +1,16 @@ + +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f460/board/board.c b/bsp/hc32f460/board/board.c new file mode 100644 index 000000000..0d4c61953 --- /dev/null +++ b/bsp/hc32f460/board/board.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#include +#include +#include "board.h" + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} +void SysClkConfig(void) +{ + stc_clk_sysclk_cfg_t stcSysClkCfg; + stc_clk_xtal_cfg_t stcXtalCfg; + stc_clk_mpll_cfg_t stcMpllCfg; + stc_sram_config_t stcSramConfig; + + MEM_ZERO_STRUCT(stcSysClkCfg); + MEM_ZERO_STRUCT(stcXtalCfg); + MEM_ZERO_STRUCT(stcMpllCfg); + + /* Set bus clk div. */ + stcSysClkCfg.enHclkDiv = ClkSysclkDiv1; + stcSysClkCfg.enExclkDiv = ClkSysclkDiv2; + stcSysClkCfg.enPclk0Div = ClkSysclkDiv1; + stcSysClkCfg.enPclk1Div = ClkSysclkDiv2; + stcSysClkCfg.enPclk2Div = ClkSysclkDiv4; + stcSysClkCfg.enPclk3Div = ClkSysclkDiv4; + stcSysClkCfg.enPclk4Div = ClkSysclkDiv2; + CLK_SysClkConfig(&stcSysClkCfg); + + /* Switch system clock source to MPLL. */ + /* Use Xtal as MPLL source. */ + stcXtalCfg.enMode = ClkXtalModeOsc; + stcXtalCfg.enDrv = ClkXtalLowDrv; + + stcXtalCfg.enFastStartup = Enable; + CLK_XtalConfig(&stcXtalCfg); + CLK_XtalCmd(Enable); + + while (Set != CLK_GetFlagStatus(ClkFlagXTALRdy)) + { + ; + } + + /* MPLL config. */ + stcMpllCfg.pllmDiv = 1ul; + stcMpllCfg.plln = 50ul; + stcMpllCfg.PllpDiv = 4ul; + stcMpllCfg.PllqDiv = 4ul; + stcMpllCfg.PllrDiv = 4ul; + CLK_SetPllSource(ClkPllSrcXTAL); + CLK_MpllConfig(&stcMpllCfg); + + /* flash read wait cycle setting */ + EFM_Unlock(); + EFM_SetLatency(5ul); + EFM_Lock(); + + /* sram init include read/write wait cycle setting */ + stcSramConfig.u8SramIdx = Sram12Idx | Sram3Idx | SramHsIdx | SramRetIdx; + stcSramConfig.enSramRC = SramCycle2; + stcSramConfig.enSramWC = SramCycle2; + stcSramConfig.enSramEccMode = EccMode3; + stcSramConfig.enSramEccOp = SramNmi; + stcSramConfig.enSramPyOp = SramNmi; + SRAM_Init(&stcSramConfig); + + /* Enable MPLL. */ + CLK_MpllCmd(Enable); + + /* Wait MPLL ready. */ + while (Set != CLK_GetFlagStatus(ClkFlagMPLLRdy)) + { + ; + } + /* Switch system clock source to MPLL. */ + CLK_SetSysClkSource(CLKSysSrcMPLL); +} +void SysTick_Handler(void) +{ + rt_os_tick_callback(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ + SysClkConfig(); + SysTick_Init(RT_TICK_PER_SECOND); + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/hc32f460/board/board.h b/bsp/hc32f460/board/board.h new file mode 100644 index 000000000..c686b7e37 --- /dev/null +++ b/bsp/hc32f460/board/board.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ddl.h" +#include "drv_gpio.h" + +/* board configuration */ +#define SRAM_BASE 0x1FFF8000 +#define SRAM_SIZE 32*1024 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +/* High speed sram. */ +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN (&__bss_end) +#endif + +#ifdef __ICCARM__ + /* Use *.icf ram symbal, to avoid hardcode.*/ + extern char __ICFEDIT_region_RAM_end__; + #define HEAP_END (&__ICFEDIT_region_RAM_end__) +#else + #define HEAP_END SRAM_END +#endif + +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#endif diff --git a/bsp/hc32f460/board/board_config.c b/bsp/hc32f460/board/board_config.c new file mode 100644 index 000000000..022f8ec78 --- /dev/null +++ b/bsp/hc32f460/board/board_config.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#include +#include "board_config.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(M4_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)M4_USART1: + /* Configure USART1 RX/TX pin. */ + PORT_SetFunc(USART1_RX_PORT, USART1_RX_PIN, Func_Usart1_Rx, Disable); + PORT_SetFunc(USART1_TX_PORT, USART1_TX_PIN, Func_Usart1_Tx, Disable); + break; +#endif +#if defined(BSP_USING_UART2) + case (rt_uint32_t)M4_USART2: + /* Configure USART2 RX/TX pin. */ + PORT_SetFunc(USART2_RX_PORT, USART2_RX_PIN, Func_Usart2_Rx, Disable); + PORT_SetFunc(USART2_TX_PORT, USART2_TX_PIN, Func_Usart2_Tx, Disable); + break; +#endif +#if defined(BSP_USING_UART3) + case (rt_uint32_t)M4_USART3: + /* Configure USART3 RX/TX pin. */ + PORT_SetFunc(USART3_RX_PORT, USART3_RX_PIN, Func_Usart3_Rx, Disable); + PORT_SetFunc(USART3_TX_PORT, USART3_TX_PIN, Func_Usart3_Tx, Disable); + break; +#endif +#if defined(BSP_USING_UART4) + case (rt_uint32_t)M4_USART4: + /* Configure USART4 RX/TX pin. */ + PORT_SetFunc(USART4_RX_PORT, USART4_RX_PIN, Func_Usart4_Rx, Disable); + PORT_SetFunc(USART4_TX_PORT, USART4_TX_PIN, Func_Usart4_Tx, Disable); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + diff --git a/bsp/hc32f460/board/board_config.h b/bsp/hc32f460/board/board_config.h new file mode 100644 index 000000000..54556aba4 --- /dev/null +++ b/bsp/hc32f460/board/board_config.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ddl.h" + +/*********** Port configure *********/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (PortD) + #define USART1_RX_PIN (Pin00) + + #define USART1_TX_PORT (PortD) + #define USART1_TX_PIN (Pin01) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RX_PORT (PortC) + #define USART2_RX_PIN (Pin11) + + #define USART2_TX_PORT (PortC) + #define USART2_TX_PIN (Pin12) +#endif + +#if defined(BSP_USING_UART3) + #define USART3_RX_PORT (PortB) + #define USART3_RX_PIN (Pin08) + + #define USART3_TX_PORT (PortB) + #define USART3_TX_PIN (Pin09) +#endif + +#if defined(BSP_USING_UART4) + #define USART4_RX_PORT (PortC) + #define USART4_RX_PIN (Pin07) + + #define USART4_TX_PORT (PortC) + #define USART4_TX_PIN (Pin06) +#endif + +/*********** USART configure *********/ +#if defined(BSP_USING_UART1) + #define USART1_RXERR_INT_IRQn (Int001_IRQn) + #define USART1_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART1_RX_INT_IRQn (Int002_IRQn) + #define USART1_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RXERR_INT_IRQn (Int003_IRQn) + #define USART2_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART2_RX_INT_IRQn (Int004_IRQn) + #define USART2_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + +#if defined(BSP_USING_UART3) + #define USART3_RXERR_INT_IRQn (Int005_IRQn) + #define USART3_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART3_RX_INT_IRQn (Int006_IRQn) + #define USART3_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + +#if defined(BSP_USING_UART4) + #define USART4_RXERR_INT_IRQn (Int007_IRQn) + #define USART4_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART4_RX_INT_IRQn (Int008_IRQn) + #define USART4_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + + + +/*********** Pin configure *********/ +#if defined(RT_USING_PIN) + + #define EXINT0_INT_IRQn (Int016_IRQn) + #define EXINT0_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT1_INT_IRQn (Int017_IRQn) + #define EXINT1_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT2_INT_IRQn (Int018_IRQn) + #define EXINT2_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT3_INT_IRQn (Int019_IRQn) + #define EXINT3_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT4_INT_IRQn (Int020_IRQn) + #define EXINT4_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT5_INT_IRQn (Int021_IRQn) + #define EXINT5_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT6_INT_IRQn (Int022_IRQn) + #define EXINT6_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT7_INT_IRQn (Int023_IRQn) + #define EXINT7_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT8_INT_IRQn (Int024_IRQn) + #define EXINT8_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT9_INT_IRQn (Int025_IRQn) + #define EXINT9_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT10_INT_IRQn (Int026_IRQn) + #define EXINT10_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT11_INT_IRQn (Int027_IRQn) + #define EXINT11_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT12_INT_IRQn (Int028_IRQn) + #define EXINT12_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT13_INT_IRQn (Int029_IRQn) + #define EXINT13_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT14_INT_IRQn (Int030_IRQn) + #define EXINT14_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT15_INT_IRQn (Int031_IRQn) + #define EXINT15_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#endif + +#endif diff --git a/bsp/hc32f460/board/linker_scripts/link.icf b/bsp/hc32f460/board/linker_scripts/link.icf new file mode 100644 index 000000000..397ec88b5 --- /dev/null +++ b/bsp/hc32f460/board/linker_scripts/link.icf @@ -0,0 +1,59 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x2000FFFF; +define symbol __ICFEDIT_region_IRAM3_start__ = 0x20010000; +define symbol __ICFEDIT_region_IRAM3_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_IRAM4_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM4_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM5_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM5_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__] + | mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__] + | mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__] + | mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32f460/board/linker_scripts/link.lds b/bsp/hc32f460/board/linker_scripts/link.lds new file mode 100644 index 000000000..ab289f41d --- /dev/null +++ b/bsp/hc32f460/board/linker_scripts/link.lds @@ -0,0 +1,200 @@ +/* +;******************************************************************************* +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +*/ +/*****************************************************************************/ +/* File hc32f460xe_flash.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 512KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2019-03-13 */ +/*****************************************************************************/ + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K + OTP (rx): ORIGIN = 0x03000C00, LENGTH = 1020 + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_sec : + { + KEEP(*(.otp_sec)) + } >OTP + + .otp_lock_sec 0x03000FC0 : + { + KEEP(*(.otp_lock_sec)) + } >OTP + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32f460/board/linker_scripts/link.sct b/bsp/hc32f460/board/linker_scripts/link.sct new file mode 100644 index 000000000..e5fbcf64b --- /dev/null +++ b/bsp/hc32f460/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } +RW_IRAM1 0x1FFF8000 0x0002F000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32f460/drivers/SConscript b/bsp/hc32f460/drivers/SConscript new file mode 100644 index 000000000..9325fb936 --- /dev/null +++ b/bsp/hc32f460/drivers/SConscript @@ -0,0 +1,21 @@ + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +drv_irq.c +''') + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f460/drivers/drv_gpio.c b/bsp/hc32f460/drivers/drv_gpio.c new file mode 100644 index 000000000..6ab3c25ad --- /dev/null +++ b/bsp/hc32f460/drivers/drv_gpio.c @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ + +#include +#include "rthw.h" + +#ifdef RT_USING_PIN +#include "drv_gpio.h" +#include "drv_irq.h" + +#define GPIO_PCR_INTE (0x1000U) +#define PIN_EXINT_OFF (0U) +#define PIN_EXINT_ON (GPIO_PCR_INTE) + +#define GPIO_PIN_INDEX(pin) ((en_pin_t)((pin) & 0x0F)) +#define GPIO_PORT(pin) ((en_port_t)(((pin) >> 4) & 0x0F)) +#define GPIO_PIN(pin) ((en_pin_t)(0x01U << GPIO_PIN_INDEX(pin))) + +#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F))) +#define PIN_MAX_NUM ((PortH * 16) + (__CLZ(__RBIT(Pin13))) + 1) + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static void exint0_irq_handler(void); +static void exint1_irq_handler(void); +static void exint2_irq_handler(void); +static void exint3_irq_handler(void); +static void exint4_irq_handler(void); +static void exint5_irq_handler(void); +static void exint6_irq_handler(void); +static void exint7_irq_handler(void); +static void exint8_irq_handler(void); +static void exint9_irq_handler(void); +static void exint10_irq_handler(void); +static void exint11_irq_handler(void); +static void exint12_irq_handler(void); +static void exint13_irq_handler(void); +static void exint14_irq_handler(void); +static void exint15_irq_handler(void); + +struct hc32_pin_irq_map +{ + rt_uint16_t pinbit; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +#ifndef HC32_PIN_CONFIG +#define HC32_PIN_CONFIG(pin, irq, src, irq_info) \ + { \ + .pinbit = pin, \ + .irq_callback = irq, \ + .irq_config = irq_info, \ + .irq_config.int_src = src, \ + } +#endif /* HC32_PIN_CONFIG */ + +static struct hc32_pin_irq_map pin_irq_map[] = +{ + HC32_PIN_CONFIG(Pin00, exint0_irq_handler, INT_PORT_EIRQ0, EXINT0_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin01, exint1_irq_handler, INT_PORT_EIRQ1, EXINT1_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin02, exint2_irq_handler, INT_PORT_EIRQ2, EXINT2_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin03, exint3_irq_handler, INT_PORT_EIRQ3, EXINT3_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin04, exint4_irq_handler, INT_PORT_EIRQ4, EXINT4_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin05, exint5_irq_handler, INT_PORT_EIRQ5, EXINT5_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin06, exint6_irq_handler, INT_PORT_EIRQ6, EXINT6_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin07, exint7_irq_handler, INT_PORT_EIRQ7, EXINT7_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin08, exint8_irq_handler, INT_PORT_EIRQ8, EXINT8_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin09, exint9_irq_handler, INT_PORT_EIRQ9, EXINT9_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin10, exint10_irq_handler, INT_PORT_EIRQ10, EXINT10_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin11, exint11_irq_handler, INT_PORT_EIRQ11, EXINT11_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin12, exint12_irq_handler, INT_PORT_EIRQ12, EXINT12_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin13, exint13_irq_handler, INT_PORT_EIRQ13, EXINT13_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin14, exint14_irq_handler, INT_PORT_EIRQ14, EXINT14_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin15, exint15_irq_handler, INT_PORT_EIRQ15, EXINT15_IRQ_CONFIG), +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void pin_irq_handler(rt_uint16_t pinbit) +{ + rt_int32_t irqindex = -1; + + if (Set == EXINT_GetExIntSrc(pinbit)) + { + EXINT_ClrExIntSrc(pinbit); + irqindex = __CLZ(__RBIT(pinbit)); + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } +} + +static void exint0_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[0].pinbit); + rt_interrupt_leave(); +} + +static void exint1_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[1].pinbit); + rt_interrupt_leave(); +} + +static void exint2_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[2].pinbit); + rt_interrupt_leave(); +} + +static void exint3_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[3].pinbit); + rt_interrupt_leave(); +} + +static void exint4_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[4].pinbit); + rt_interrupt_leave(); +} + +static void exint5_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[5].pinbit); + rt_interrupt_leave(); +} + +static void exint6_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[6].pinbit); + rt_interrupt_leave(); +} + +static void exint7_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[7].pinbit); + rt_interrupt_leave(); +} + +static void exint8_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[8].pinbit); + rt_interrupt_leave(); +} + +static void exint9_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[9].pinbit); + rt_interrupt_leave(); +} + +static void exint10_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[10].pinbit); + rt_interrupt_leave(); +} + +static void exint11_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[11].pinbit); + rt_interrupt_leave(); +} + +static void exint12_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[12].pinbit); + rt_interrupt_leave(); +} + +static void exint13_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[13].pinbit); + rt_interrupt_leave(); +} + +static void exint14_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[14].pinbit); + rt_interrupt_leave(); +} + +static void exint15_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[15].pinbit); + rt_interrupt_leave(); +} + +static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + en_port_t gpio_port; + en_pin_t gpio_pin; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_LOW == value) + { + PORT_ResetBits(gpio_port, gpio_pin); + } + else + { + PORT_SetBits(gpio_port, gpio_pin); + } + } +} + +static int hc32_pin_read(rt_device_t dev, rt_base_t pin) +{ + en_port_t gpio_port; + en_pin_t gpio_pin; + int value = PIN_LOW; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (Reset == PORT_GetBit(gpio_port, gpio_pin)) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + } + + return value; +} + +static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + en_port_t gpio_port; + en_pin_t gpio_pin; + stc_port_init_t stcGpioInit; + + if (pin >= PIN_MAX_NUM) + { + return; + } + + MEM_ZERO_STRUCT(stcGpioInit); + switch (mode) + { + case PIN_MODE_OUTPUT: + stcGpioInit.enPinMode = Pin_Mode_Out; + stcGpioInit.enPinOType = Pin_OType_Cmos; + break; + case PIN_MODE_INPUT: + stcGpioInit.enPinMode = Pin_Mode_In; + break; + case PIN_MODE_INPUT_PULLUP: + stcGpioInit.enPinMode = Pin_Mode_In; + stcGpioInit.enPullUp = Enable; + break; + case PIN_MODE_INPUT_PULLDOWN: + stcGpioInit.enPinMode = Pin_Mode_In; + stcGpioInit.enPullUp = Disable; + break; + case PIN_MODE_OUTPUT_OD: + stcGpioInit.enPinMode = Pin_Mode_Out; + stcGpioInit.enPinOType = Pin_OType_Od; + break; + default: + break; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + PORT_Init(gpio_port, gpio_pin, &stcGpioInit); +} + +static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt) +{ + __IO uint16_t *PCRx; + uint16_t pin_num; + pin_num = __CLZ(__RBIT(u16Pin)); + PCRx = (__IO uint16_t *)((uint32_t)(&M4_PORT->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL)); + + PORT_Unlock(); + MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt); + PORT_Lock(); +} +static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) + +{ + struct hc32_pin_irq_map *irq_map; + rt_base_t level; + rt_int32_t irqindex = -1; + en_pin_t gpio_pin; + stc_exint_config_t stcExintInit; + + if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + irq_map = &pin_irq_map[irqindex]; + gpio_pin = GPIO_PIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Exint config */ + MEM_ZERO_STRUCT(stcExintInit); + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + stcExintInit.enExtiLvl = ExIntRisingEdge; + break; + case PIN_IRQ_MODE_FALLING: + stcExintInit.enExtiLvl = ExIntFallingEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + stcExintInit.enExtiLvl = ExIntBothEdge; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + stcExintInit.enExtiLvl = ExIntLowLevel; + break; + } + stcExintInit.enExitCh = (en_exti_ch_t)irqindex;//gpio_pin; + stcExintInit.enFilterEn = Enable; + stcExintInit.enFltClk = Pclk3Div8; + EXINT_Init(&stcExintInit); + /* IRQ sign-in */ + hc32_install_irq_handler(&irq_map->irq_config, irq_map->irq_callback, RT_FALSE); + NVIC_EnableIRQ(irq_map->irq_config.irq); + gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_ON); + + rt_hw_interrupt_enable(level); + } + else + { + level = rt_hw_interrupt_disable(); + gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_OFF); + NVIC_DisableIRQ(irq_map->irq_config.irq); + + rt_hw_interrupt_enable(level); + } + + return RT_EOK; +} + +static const struct rt_pin_ops pin_ops = +{ + hc32_pin_mode, + hc32_pin_write, + hc32_pin_read, + hc32_pin_attach_irq, + hc32_pin_detach_irq, + hc32_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ +#include "drv_gpio.h" + diff --git a/bsp/hc32f460/drivers/drv_gpio.h b/bsp/hc32f460/drivers/drv_gpio.h new file mode 100644 index 000000000..ee13fb719 --- /dev/null +++ b/bsp/hc32f460/drivers/drv_gpio.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ +#include +#include "board_config.h" + +#ifdef RT_USING_PIN + +#define __HC_PORT(port) Port##port +#define GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN) + +#ifndef EXINT0_IRQ_CONFIG +#define EXINT0_IRQ_CONFIG \ + { \ + .irq = EXINT0_INT_IRQn, \ + .irq_prio = EXINT0_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT1_IRQ_CONFIG +#define EXINT1_IRQ_CONFIG \ + { \ + .irq = EXINT1_INT_IRQn, \ + .irq_prio = EXINT1_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT2_IRQ_CONFIG +#define EXINT2_IRQ_CONFIG \ + { \ + .irq = EXINT2_INT_IRQn, \ + .irq_prio = EXINT2_INT_PRIO, \ + } +#endif /* EXINT2_IRQ_CONFIG */ + +#ifndef EXINT3_IRQ_CONFIG +#define EXINT3_IRQ_CONFIG \ + { \ + .irq = EXINT3_INT_IRQn, \ + .irq_prio = EXINT3_INT_PRIO, \ + } +#endif /* EXINT3_IRQ_CONFIG */ + +#ifndef EXINT4_IRQ_CONFIG +#define EXINT4_IRQ_CONFIG \ + { \ + .irq = EXINT4_INT_IRQn, \ + .irq_prio = EXINT4_INT_PRIO, \ + } +#endif /* EXINT4_IRQ_CONFIG */ + +#ifndef EXINT5_IRQ_CONFIG +#define EXINT5_IRQ_CONFIG \ + { \ + .irq = EXINT5_INT_IRQn, \ + .irq_prio = EXINT5_INT_PRIO, \ + } +#endif /* EXINT5_IRQ_CONFIG */ + +#ifndef EXINT6_IRQ_CONFIG +#define EXINT6_IRQ_CONFIG \ + { \ + .irq = EXINT6_INT_IRQn, \ + .irq_prio = EXINT6_INT_PRIO, \ + } +#endif /* EXINT6_IRQ_CONFIG */ + +#ifndef EXINT7_IRQ_CONFIG +#define EXINT7_IRQ_CONFIG \ + { \ + .irq = EXINT7_INT_IRQn, \ + .irq_prio = EXINT7_INT_PRIO, \ + } +#endif /* EXINT7_IRQ_CONFIG */ + +#ifndef EXINT8_IRQ_CONFIG +#define EXINT8_IRQ_CONFIG \ + { \ + .irq = EXINT8_INT_IRQn, \ + .irq_prio = EXINT8_INT_PRIO, \ + } +#endif /* EXINT8_IRQ_CONFIG */ + +#ifndef EXINT9_IRQ_CONFIG +#define EXINT9_IRQ_CONFIG \ + { \ + .irq = EXINT9_INT_IRQn, \ + .irq_prio = EXINT9_INT_PRIO, \ + } +#endif /* EXINT9_IRQ_CONFIG */ + +#ifndef EXINT10_IRQ_CONFIG +#define EXINT10_IRQ_CONFIG \ + { \ + .irq = EXINT10_INT_IRQn, \ + .irq_prio = EXINT10_INT_PRIO, \ + } +#endif /* EXINT10_IRQ_CONFIG */ + +#ifndef EXINT11_IRQ_CONFIG +#define EXINT11_IRQ_CONFIG \ + { \ + .irq = EXINT11_INT_IRQn, \ + .irq_prio = EXINT11_INT_PRIO, \ + } +#endif /* EXINT11_IRQ_CONFIG */ + +#ifndef EXINT12_IRQ_CONFIG +#define EXINT12_IRQ_CONFIG \ + { \ + .irq = EXINT12_INT_IRQn, \ + .irq_prio = EXINT12_INT_PRIO, \ + } +#endif /* EXINT12_IRQ_CONFIG */ + +#ifndef EXINT13_IRQ_CONFIG +#define EXINT13_IRQ_CONFIG \ + { \ + .irq = EXINT13_INT_IRQn, \ + .irq_prio = EXINT13_INT_PRIO, \ + } +#endif /* EXINT13_IRQ_CONFIG */ + +#ifndef EXINT14_IRQ_CONFIG +#define EXINT14_IRQ_CONFIG \ + { \ + .irq = EXINT14_INT_IRQn, \ + .irq_prio = EXINT14_INT_PRIO, \ + } +#endif /* EXINT14_IRQ_CONFIG */ + +#ifndef EXINT15_IRQ_CONFIG +#define EXINT15_IRQ_CONFIG \ + { \ + .irq = EXINT15_INT_IRQn, \ + .irq_prio = EXINT15_INT_PRIO, \ + } +#endif /* EXINT15_IRQ_CONFIG */ + +#endif + +extern void Led_Init(void); +#endif diff --git a/bsp/hc32f460/drivers/drv_irq.c b/bsp/hc32f460/drivers/drv_irq.c new file mode 100644 index 000000000..c873ab61e --- /dev/null +++ b/bsp/hc32f460/drivers/drv_irq.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#include +#include "drv_irq.h" + +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable) +{ + rt_err_t result = -RT_ERROR; + stc_irq_regi_conf_t irq_signin; + + RT_ASSERT(RT_NULL != irq_config); + RT_ASSERT(RT_NULL != irq_hdr); + + irq_signin.enIRQn = irq_config->irq; + irq_signin.enIntSrc = irq_config->int_src; + irq_signin.pfnCallback = irq_hdr; + if (Ok == enIrqRegistration(&irq_signin)) + { + NVIC_ClearPendingIRQ(irq_signin.enIRQn); + NVIC_SetPriority(irq_signin.enIRQn, irq_config->irq_prio); + + if (RT_TRUE == irq_enable) + { + NVIC_EnableIRQ(irq_signin.enIRQn); + } + else + { + NVIC_DisableIRQ(irq_signin.enIRQn); + } + + result = RT_EOK; + } + + RT_ASSERT(RT_EOK == result); + + return result; +} diff --git a/bsp/hc32f460/drivers/drv_irq.h b/bsp/hc32f460/drivers/drv_irq.h new file mode 100644 index 000000000..f8e0bb851 --- /dev/null +++ b/bsp/hc32f460/drivers/drv_irq.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ + +#ifndef __DRV_IRQ_H__ +#define __DRV_IRQ_H__ + +#include +#include "hc32_ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +struct hc32_irq_config +{ + IRQn_Type irq; + uint32_t irq_prio; + en_int_src_t int_src; +}; + +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32f460/drivers/drv_usart.c b/bsp/hc32f460/drivers/drv_usart.c new file mode 100644 index 000000000..176aa6a7c --- /dev/null +++ b/bsp/hc32f460/drivers/drv_usart.c @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#include +#include +#include "drv_usart.h" +#include "board_config.h" + + +#ifdef RT_USING_SERIAL +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) + #error "Please define at least one BSP_USING_UARTx" + /* UART instance can be selected at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */ +#endif + +/* HC32 config uart class */ +struct hc32_uart_config +{ + struct hc32_irq_config rxerr_irq_config; + struct hc32_irq_config rx_irq_config; +}; +/* HC32 UART index */ +struct uart_index +{ + rt_uint32_t index; + M4_USART_TypeDef *Instance; +}; + +/* HC32 UART irq handler */ +struct uart_irq_handler +{ + void (*rxerr_irq_handler)(void); + void (*rx_irq_handler)(void); +}; + +/* HC32 uart dirver class */ +struct hc32_uart +{ + const char *name; + M4_USART_TypeDef *Instance; + struct hc32_uart_config config; + struct rt_serial_device serial; +}; +#ifndef UART_CONFIG +#define UART_CONFIG(uart_name, USART) \ + { \ + .name = uart_name, \ + .Instance = M4_##USART, \ + .config = { \ + .rxerr_irq_config = { \ + .irq = USART##_RXERR_INT_IRQn, \ + .irq_prio = USART##_RXERR_INT_PRIO, \ + .int_src = INT_##USART##_EI, \ + }, \ + .rx_irq_config = { \ + .irq = USART##_RX_INT_IRQn, \ + .irq_prio = USART##_RX_INT_PRIO, \ + .int_src = INT_##USART##_RI, \ + }, \ + }, \ + } +#endif /* UART_CONFIG */ + + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + UART_INDEX_MAX, +}; + +static const struct uart_index uart_map[] = +{ +#ifdef BSP_USING_UART1 + {UART1_INDEX, M4_USART1}, +#endif +#ifdef BSP_USING_UART2 + {UART2_INDEX, M4_USART2}, +#endif +#ifdef BSP_USING_UART3 + {UART3_INDEX, M4_USART3}, +#endif +#ifdef BSP_USING_UART4 + {UART4_INDEX, M4_USART4}, +#endif +}; +static const struct uart_index uart_clock_map[] = +{ +#ifdef BSP_USING_UART1 + {0, M4_USART1}, +#endif +#ifdef BSP_USING_UART2 + {1, M4_USART2}, +#endif +#ifdef BSP_USING_UART3 + {2, M4_USART3}, +#endif +#ifdef BSP_USING_UART4 + {3, M4_USART4}, +#endif +}; + +static struct hc32_uart uart_obj[] = +{ +#ifdef BSP_USING_UART1 + UART_CONFIG("uart1", USART1), +#endif +#ifdef BSP_USING_UART2 + UART_CONFIG("uart2", USART2), +#endif +#ifdef BSP_USING_UART3 + UART_CONFIG("uart3", USART3), +#endif +#ifdef BSP_USING_UART4 + UART_CONFIG("uart4", USART4), +#endif +}; + +static const struct uart_irq_handler uart_irq_handlers[sizeof(uart_obj) / sizeof(uart_obj[0])]; + +static uint32_t hc32_get_uart_index(M4_USART_TypeDef *Instance) +{ + uint32_t index = UART_INDEX_MAX; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_map); i++) + { + if (uart_map[i].Instance == Instance) + { + index = uart_map[i].index; + RT_ASSERT(index < UART_INDEX_MAX) + break; + } + } + + return index; +} +static uint32_t hc32_get_uart_clock_index(M4_USART_TypeDef *Instance) +{ + uint32_t index = 4; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_clock_map); i++) + { + if (uart_clock_map[i].Instance == Instance) + { + index = uart_clock_map[i].index; + RT_ASSERT(index < 4) + break; + } + } + + return index; +} +static uint32_t hc32_get_usart_fcg(M4_USART_TypeDef *Instance) +{ + return (PWC_FCG1_PERIPH_USART1 << hc32_get_uart_clock_index(Instance)); +} + +static rt_err_t hc32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct hc32_uart *uart; + stc_usart_uart_init_t uart_init; + + RT_ASSERT(RT_NULL != cfg); + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + /* Configure USART initialization structure */ + MEM_ZERO_STRUCT(uart_init); + uart_init.enSampleMode = UsartSampleBit8; + uart_init.enSampleMode = UsartSampleBit8; + uart_init.enDetectMode = UsartStartBitFallEdge; + uart_init.enHwFlow = UsartRtsEnable; + uart_init.enClkMode = UsartIntClkCkNoOutput; + uart_init.enClkDiv = UsartClkDiv_1; + if (BIT_ORDER_LSB == cfg->bit_order) + { + uart_init.enDirection = UsartDataLsbFirst; + } + else + { + uart_init.enDirection = UsartDataMsbFirst; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart_init.enStopBit = UsartOneStopBit; + break; + case STOP_BITS_2: + uart_init.enStopBit = UsartTwoStopBit; + break; + default: + uart_init.enStopBit = UsartOneStopBit; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart_init.enParity = UsartParityNone; + break; + case PARITY_EVEN: + uart_init.enParity = UsartParityEven; + break; + case PARITY_ODD: + uart_init.enParity = UsartParityOdd; + break; + default: + uart_init.enParity = UsartParityNone; + break; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + uart_init.enDataLength = UsartDataBits8; + break; + default: + return -RT_ERROR; + } + + /* Enable USART clock */ + PWC_Fcg1PeriphClockCmd(hc32_get_usart_fcg(uart->Instance), Enable); + + rt_err_t rt_hw_board_uart_init(M4_USART_TypeDef * USARTx); + if (RT_EOK != rt_hw_board_uart_init(uart->Instance)) + { + return -RT_ERROR; + } + + USART_DeInit(uart->Instance); + if (Error == USART_UART_Init(uart->Instance, &uart_init)) + { + return -RT_ERROR; + } + USART_SetBaudrate(uart->Instance, cfg->baud_rate); + if (RT_EOK != USART_SetBaudrate(uart->Instance, cfg->baud_rate)) + { + return -RT_ERROR; + } + /* Register RX error interrupt */ + hc32_install_irq_handler(&uart->config.rxerr_irq_config, + uart_irq_handlers[hc32_get_uart_index(uart->Instance)].rxerr_irq_handler, + RT_TRUE); + + USART_FuncCmd(uart->Instance, UsartRxInt, Enable); + + if ((serial->parent.flag & RT_DEVICE_FLAG_RDWR) || \ + (serial->parent.flag & RT_DEVICE_FLAG_RDONLY)) + { + USART_FuncCmd(uart->Instance, UsartRx, Enable); + } + + if ((serial->parent.flag & RT_DEVICE_FLAG_RDWR) || \ + (serial->parent.flag & RT_DEVICE_FLAG_WRONLY)) + { + USART_FuncCmd(uart->Instance, UsartTx, Enable); + } + + return RT_EOK; +} + + +static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hc32_uart *uart; + uint32_t uart_index; + RT_ASSERT(RT_NULL != serial); + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + switch (cmd) + { + /* Disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* Disable RX irq */ + NVIC_DisableIRQ(uart->config.rx_irq_config.irq); + enIrqResign(uart->config.rx_irq_config.irq); + break; + + /* Enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + uart_index = hc32_get_uart_index(uart->Instance); + /* Install RX irq handler */ + hc32_install_irq_handler(&uart->config.rx_irq_config, + uart_irq_handlers[uart_index].rx_irq_handler, + RT_TRUE); + break; + } + return RT_EOK; +} + +static int hc32_putc(struct rt_serial_device *serial, char c) +{ + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + USART_SendData(uart->Instance, c); + /* Polling mode. */ + while (USART_GetStatus(uart->Instance, UsartTxEmpty) != Set); + return 1; +} + +static int hc32_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + if (Set == USART_GetStatus(uart->Instance, UsartRxNoEmpty)) + { + ch = (rt_uint8_t)USART_RecData(uart->Instance); + } + + return ch; +} + +static void hc32_uart_rx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +} + +static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->Instance); + + if (Set == USART_GetStatus(uart->Instance, UsartParityErr) || \ + Set == USART_GetStatus(uart->Instance, UsartFrameErr)) + { + USART_RecData(uart->Instance); + } + USART_ClearStatus(uart->Instance, UsartParityErr); + USART_ClearStatus(uart->Instance, UsartFrameErr); + USART_ClearStatus(uart->Instance, UsartOverrunErr); +} +#if defined(BSP_USING_UART1) +static void hc32_uart1_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +static void hc32_uart2_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +static void hc32_uart2_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +static void hc32_uart3_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart3_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +static void hc32_uart4_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +static void hc32_uart4_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +static const struct uart_irq_handler uart_irq_handlers[] = +{ +#ifdef BSP_USING_UART1 + {hc32_uart1_rxerr_irq_handler, hc32_uart1_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART2 + {hc32_uart2_rxerr_irq_handler, hc32_uart2_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART3 + {hc32_uart3_rxerr_irq_handler, hc32_uart3_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART4 + {hc32_uart4_rxerr_irq_handler, hc32_uart4_rx_irq_handler}, +#endif +}; +static const struct rt_uart_ops hc32_uart_ops = +{ + .configure = hc32_configure, + .control = hc32_control, + .putc = hc32_putc, + .getc = hc32_getc, +}; + +int hc32_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].name, + (RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX), + &uart_obj[i]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(hc32_hw_uart_init); + +#endif + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32f460/drivers/drv_usart.h b/bsp/hc32f460/drivers/drv_usart.h new file mode 100644 index 000000000..1bb200b8e --- /dev/null +++ b/bsp/hc32f460/drivers/drv_usart.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-2 lizhengyang first version + */ +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ +#include +#include "rtdevice.h" + +#include "hc32_ddl.h" +#include "drv_irq.h" + +extern int hc32_hw_uart_init(void); +#endif diff --git a/bsp/hc32f460/project.uvoptx b/bsp/hc32f460/project.uvoptx new file mode 100644 index 000000000..6be8fd8b7 --- /dev/null +++ b/bsp/hc32f460/project.uvoptx @@ -0,0 +1,1149 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 9 + 70 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 9 + 71 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\delay.c + delay.c + 0 + 0 + + + 9 + 72 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\stdlib.c + stdlib.c + 0 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\unistd.c + unistd.c + 0 + 0 + + + + diff --git a/bsp/hc32f460/project.uvprojx b/bsp/hc32f460/project.uvprojx new file mode 100644 index 000000000..857c8b9c1 --- /dev/null +++ b/bsp/hc32f460/project.uvprojx @@ -0,0 +1,823 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F460PETB + HDSC + HDSC.HC32F460.1.0.7 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h + + + + + + + + + + $$Device:HC32F460PETB$SVD\HDSC_HC32F460PETB.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x3000c00 + 0x3fc + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + USE_DEVICE_DRIVER_LIB, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, __RTTHREAD__, __DEBUG, RT_USING_ARM_LIBC + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;board;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\finsh;Libraries\CMSIS\Include;Libraries\CMSIS\Device\HDSC\HC32F460\Include;Libraries\HC32F460_StdPeriph_Driver\inc;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + + + Drivers + + + board_config.c + 1 + board\board_config.c + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_irq.c + 1 + drivers\drv_irq.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + HC32_StdPeriph + + + system_hc32f460.c + 1 + Libraries\CMSIS\Device\HDSC\HC32F460\Source\system_hc32f460.c + + + hc32f460_usart.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_usart.c + + + hc32f460_gpio.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_gpio.c + + + hc32f460_clk.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_clk.c + + + hc32f460_efm.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_efm.c + + + hc32f460_sram.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_sram.c + + + hc32f460_utility.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_utility.c + + + hc32f460_exint_nmi_swi.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_exint_nmi_swi.c + + + hc32f460_icg.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_icg.c + + + startup_hc32f460.s + 2 + Libraries\CMSIS\Device\HDSC\HC32F460\Source\ARM\startup_hc32f460.s + + + hc32f460_interrupts.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_interrupts.c + + + hc32f460_pwc.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_pwc.c + + + + + Kernel + + + irq.c + 1 + ..\..\src\irq.c + + + device.c + 1 + ..\..\src\device.c + + + mem.c + 1 + ..\..\src\mem.c + + + components.c + 1 + ..\..\src\components.c + + + clock.c + 1 + ..\..\src\clock.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + timer.c + 1 + ..\..\src\timer.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + object.c + 1 + ..\..\src\object.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + thread.c + 1 + ..\..\src\thread.c + + + + + libc + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + delay.c + 1 + ..\..\components\libc\compilers\common\delay.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + unistd.c + 1 + ..\..\components\libc\compilers\common\unistd.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/hc32f460/rtconfig.h b/bsp/hc32f460/rtconfig.h new file mode 100644 index 000000000..cf1179edd --- /dev/null +++ b/bsp/hc32f460/rtconfig.h @@ -0,0 +1,188 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define MCU_HC32F460 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART4 + +#endif diff --git a/bsp/hc32f460/rtconfig.py b/bsp/hc32f460/rtconfig.py new file mode 100644 index 000000000..462c2009f --- /dev/null +++ b/bsp/hc32f460/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='iar' + +print "############rtconfig##############" + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +print "CROSS_TOOL: " + CROSS_TOOL + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:\03_software\Program Files\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:\03_software\Program Files\IAR Systems\Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +MCU_TYPE = 'HC32F460' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall -DHC32F460 -D__DEBUG -USE_DEVICE_DRIVER_LIB -D__ASSEMBLY__' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork -USE_DEVICE_DRIVER_LIB -DHC32F460 -D__DEBUG' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link.sct"' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D __DEBUG' + ' -D USE_DEVICE_DRIVER_LIB' + ' -D HC32F460' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/hc32f460/template.uvopt b/bsp/hc32f460/template.uvopt new file mode 100644 index 000000000..33eee51f0 --- /dev/null +++ b/bsp/hc32f460/template.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U788529815 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0AT32F403A_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC800 -FD20000000 -FF0AT32F403A_1024 -FL0100000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + diff --git a/bsp/hc32f460/template.uvoptx b/bsp/hc32f460/template.uvoptx new file mode 100644 index 000000000..a8bf21a9e --- /dev/null +++ b/bsp/hc32f460/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U4294967295 -O78 -S5 -ZTIFSpeedSel1000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F460_512K.FLM -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0AT32F403A_1024 -FL0100000 -FS08000000 -FP0($$Device:AT32F403AVGT7$Flash\AT32F403A_1024.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF495056867767222250 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32f460/template.uvprojx b/bsp/hc32f460/template.uvprojx new file mode 100644 index 000000000..d289d4ffb --- /dev/null +++ b/bsp/hc32f460/template.uvprojx @@ -0,0 +1,406 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F460PETB + HDSC + HDSC.HC32F460.1.0.7 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h + + + + + + + + + + $$Device:HC32F460PETB$SVD\HDSC_HC32F460PETB.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x3000c00 + 0x3fc + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + __DEBUG,HC32F460,USE_DEVICE_DRIVER_LIB + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + --keep=*Handler + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + -- GitLab