diff --git a/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s b/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s
new file mode 100644
index 0000000000000000000000000000000000000000..ca5ee3073335c164a587fd0b16059f1b7ada0570
--- /dev/null
+++ b/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s
@@ -0,0 +1,277 @@
+;/*****************************************************************************
+; * @file: startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC17xx Device Series
+; * @version: V1.02
+; * @date: 27. July 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPI_IRQHandler ; 29: SPI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+RIT_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s b/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s
new file mode 100644
index 0000000000000000000000000000000000000000..bd01a3ad00e2ca31131686178565f908e9ddbcb7
--- /dev/null
+++ b/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s
@@ -0,0 +1,239 @@
+/*****************************************************************************/
+/* startup_LPC17xx.s: Startup file for LPC17xx device series */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
+/*****************************************************************************/
+
+
+/*
+//*** <<< Use Configuration Wizard in Context Menu >>> ***
+*/
+
+
+/*
+// Stack Configuration
+// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//
+*/
+
+ .equ Stack_Size, 0x00000100
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// Heap Configuration
+// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//
+*/
+
+ .equ Heap_Size, 0x00001000
+
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack /* Top of Stack */
+ .long __cs3_reset /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long WDT_IRQHandler /* 16: Watchdog Timer */
+ .long TIMER0_IRQHandler /* 17: Timer0 */
+ .long TIMER1_IRQHandler /* 18: Timer1 */
+ .long TIMER2_IRQHandler /* 19: Timer2 */
+ .long TIMER3_IRQHandler /* 20: Timer3 */
+ .long UART0_IRQHandler /* 21: UART0 */
+ .long UART1_IRQHandler /* 22: UART1 */
+ .long UART2_IRQHandler /* 23: UART2 */
+ .long UART3_IRQHandler /* 24: UART3 */
+ .long PWM1_IRQHandler /* 25: PWM1 */
+ .long I2C0_IRQHandler /* 26: I2C0 */
+ .long I2C1_IRQHandler /* 27: I2C1 */
+ .long I2C2_IRQHandler /* 28: I2C2 */
+ .long SPI_IRQHandler /* 29: SPI */
+ .long SSP0_IRQHandler /* 30: SSP0 */
+ .long SSP1_IRQHandler /* 31: SSP1 */
+ .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
+ .long RTC_IRQHandler /* 33: Real Time Clock */
+ .long EINT0_IRQHandler /* 34: External Interrupt 0 */
+ .long EINT1_IRQHandler /* 35: External Interrupt 1 */
+ .long EINT2_IRQHandler /* 36: External Interrupt 2 */
+ .long EINT3_IRQHandler /* 37: External Interrupt 3 */
+ .long ADC_IRQHandler /* 38: A/D Converter */
+ .long BOD_IRQHandler /* 39: Brown-Out Detect */
+ .long USB_IRQHandler /* 40: USB */
+ .long CAN_IRQHandler /* 41: CAN */
+ .long DMA_IRQHandler /* 42: General Purpose DMA */
+ .long I2S_IRQHandler /* 43: I2S */
+ .long ENET_IRQHandler /* 44: Ethernet */
+ .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */
+ .long MCPWM_IRQHandler /* 46: Motor Control PWM */
+ .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
+ .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+ .thumb
+
+
+/* Reset Handler */
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=_start
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+/* Exception Handlers */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak MemManage_Handler
+ .type MemManage_Handler, %function
+MemManage_Handler:
+ B .
+ .size MemManage_Handler, . - MemManage_Handler
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ B .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ WDT_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ UART0_IRQHandler
+ IRQ UART1_IRQHandler
+ IRQ UART2_IRQHandler
+ IRQ UART3_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ I2C0_IRQHandler
+ IRQ I2C1_IRQHandler
+ IRQ I2C2_IRQHandler
+ IRQ SPI_IRQHandler
+ IRQ SSP0_IRQHandler
+ IRQ SSP1_IRQHandler
+ IRQ PLL0_IRQHandler
+ IRQ RTC_IRQHandler
+ IRQ EINT0_IRQHandler
+ IRQ EINT1_IRQHandler
+ IRQ EINT2_IRQHandler
+ IRQ EINT3_IRQHandler
+ IRQ ADC_IRQHandler
+ IRQ BOD_IRQHandler
+ IRQ USB_IRQHandler
+ IRQ CAN_IRQHandler
+ IRQ DMA_IRQHandler
+ IRQ I2S_IRQHandler
+ IRQ ENET_IRQHandler
+ IRQ RIT_IRQHandler
+ IRQ MCPWM_IRQHandler
+ IRQ QEI_IRQHandler
+ IRQ PLL1_IRQHandler
+
+ .end
diff --git a/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s b/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s
new file mode 100644
index 0000000000000000000000000000000000000000..eae20ede947722cd3122b8c3d8f78c4facc2bde0
--- /dev/null
+++ b/bsp/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s
@@ -0,0 +1,341 @@
+;/*****************************************************************************
+; * @file: startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC17xx Device Series
+; * @version: V1.02
+; * @date: 31. July 2009
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPI_IRQHandler ; 29: SPI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER0_IRQHandler
+ B TIMER0_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK PWM1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PWM1_IRQHandler
+ B PWM1_IRQHandler
+
+ PUBWEAK I2C0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C0_IRQHandler
+ B I2C0_IRQHandler
+
+ PUBWEAK I2C1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_IRQHandler
+ B I2C1_IRQHandler
+
+ PUBWEAK I2C2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_IRQHandler
+ B I2C2_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ PUBWEAK SSP0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SSP0_IRQHandler
+ B SSP0_IRQHandler
+
+ PUBWEAK SSP1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SSP1_IRQHandler
+ B SSP1_IRQHandler
+
+ PUBWEAK PLL0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PLL0_IRQHandler
+ B PLL0_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK EINT0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT0_IRQHandler
+ B EINT0_IRQHandler
+
+ PUBWEAK EINT1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT1_IRQHandler
+ B EINT1_IRQHandler
+
+ PUBWEAK EINT2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT2_IRQHandler
+ B EINT2_IRQHandler
+
+ PUBWEAK EINT3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT3_IRQHandler
+ B EINT3_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK BOD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+BOD_IRQHandler
+ B BOD_IRQHandler
+
+ PUBWEAK USB_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_IRQHandler
+ B USB_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK DMA_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA_IRQHandler
+ B DMA_IRQHandler
+
+ PUBWEAK I2S_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2S_IRQHandler
+ B I2S_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK RIT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RIT_IRQHandler
+ B RIT_IRQHandler
+
+ PUBWEAK MCPWM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCPWM_IRQHandler
+ B MCPWM_IRQHandler
+
+ PUBWEAK QEI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+QEI_IRQHandler
+ B QEI_IRQHandler
+
+ PUBWEAK PLL1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PLL1_IRQHandler
+ B PLL1_IRQHandler
+
+ END