未验证 提交 7f8642e7 编写于 作者: B Bernard Xiong 提交者: GitHub

Merge pull request #3080 from gavin-liugang/master

imxrt: Update for imxrt UART, SDRAM, ENET, PHY modules
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
int main(void) int main(void)
{ {
#ifndef PHY_USING_KSZ8081
/* set LED0 pin mode to output */ /* set LED0 pin mode to output */
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
...@@ -28,5 +29,6 @@ int main(void) ...@@ -28,5 +29,6 @@ int main(void)
rt_pin_write(LED0_PIN, PIN_LOW); rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500); rt_thread_mdelay(500);
} }
#endif
} }
/*
* Copyright (c) 2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-09-19 Gavin first version
*
*/
#include <rtthread.h>
#ifdef RT_USING_DFS_RAMFS
#include <dfs_fs.h>
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
int mnt_init(void)
{
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8*1024*1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
return 0;
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
rt_kprintf("RAM file system initializated!\n");
else
rt_kprintf("RAM file system initializate failed!\n");
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
...@@ -56,12 +56,60 @@ menu "On-chip Peripheral Drivers" ...@@ -56,12 +56,60 @@ menu "On-chip Peripheral Drivers"
depends on BSP_LPUART1_TX_USING_DMA depends on BSP_LPUART1_TX_USING_DMA
int "Set LPUART1 TX DMA channel (0-32)" int "Set LPUART1 TX DMA channel (0-32)"
default 1 default 1
config BSP_USING_LPUART3
bool "Enable LPUART3"
default n
config BSP_LPUART3_RX_USING_DMA
bool "Enable LPUART3 RX DMA"
depends on BSP_USING_LPUART3
select BSP_USING_DMA
select RT_SERIAL_USING_DMA
default n
config BSP_LPUART3_RX_DMA_CHANNEL
depends on BSP_LPUART3_RX_USING_DMA
int "Set LPUART3 RX DMA channel (0-32)"
default 0
config BSP_LPUART3_TX_USING_DMA
bool "Enable LPUART3 TX DMA"
depends on BSP_USING_LPUART3
select BSP_USING_DMA
select RT_SERIAL_USING_DMA
default n
config BSP_LPUART3_TX_DMA_CHANNEL
depends on BSP_LPUART3_TX_USING_DMA
int "Set LPUART3 TX DMA channel (0-32)"
default 1
endif endif
endmenu endmenu
menu "Onboard Peripheral Drivers" menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select PHY_USING_KSZ8081
select RT_USING_NETDEV
default n
if BSP_USING_ETH
config PHY_USING_KSZ8081
bool "i.MX RT1050EVKB uses ksz8081 phy"
default y
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
endif
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"
......
...@@ -12,6 +12,10 @@ MCUX_Config/pin_mux.c ...@@ -12,6 +12,10 @@ MCUX_Config/pin_mux.c
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1'] CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1']
if GetDepend(['PHY_USING_KSZ8081']):
src += Glob('ports/phyksz8081/fsl_phy.c')
CPPPATH += [cwd + '/ports/phyksz8081']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
Return('group') Return('group')
...@@ -12,6 +12,8 @@ ...@@ -12,6 +12,8 @@
#include <rtthread.h> #include <rtthread.h>
#include "board.h" #include "board.h"
#include "pin_mux.h" #include "pin_mux.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#ifdef BSP_USING_DMA #ifdef BSP_USING_DMA
#include "fsl_dmamux.h" #include "fsl_dmamux.h"
...@@ -109,6 +111,325 @@ void imxrt_dma_init(void) ...@@ -109,6 +111,325 @@ void imxrt_dma_init(void)
EDMA_Init(DMA0, &config); EDMA_Init(DMA0, &config);
} }
#endif #endif
#ifdef BSP_USING_LPUART
void imxrt_uart_pins_init(void)
{
#ifdef BSP_USING_LPUART1
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef BSP_USING_LPUART2
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART3
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART4
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_00_LPUART4_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_01_LPUART4_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_00_LPUART4_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_01_LPUART4_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART5
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_12_LPUART5_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_13_LPUART5_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_12_LPUART5_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_13_LPUART5_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART6
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART7
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_31_LPUART7_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_32_LPUART7_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_31_LPUART7_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_32_LPUART7_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART8
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
0x10B0u);
#endif
}
#endif /* BSP_USING_LPUART */
#ifdef BSP_USING_ETH
void imxrt_enet_pins_init(void)
{
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0xB0A9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
0xB0A9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
0x31u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/6
Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Disabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
0xB829u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Enabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
}
void imxrt_enet_phy_reset_by_gpio(void)
{
gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
GPIO_PinInit(GPIO1, 9, &gpio_config);
GPIO_PinInit(GPIO1, 10, &gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
GPIO_WritePinOutput(GPIO1, 9, 0);
rt_thread_delay(100);
GPIO_WritePinOutput(GPIO1, 9, 1);
}
#endif /* BSP_USING_ETH */
/** /**
* This function will initial rt1050 board. * This function will initial rt1050 board.
*/ */
...@@ -121,6 +442,14 @@ void rt_hw_board_init() ...@@ -121,6 +442,14 @@ void rt_hw_board_init()
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
#ifdef BSP_USING_LPUART
imxrt_uart_pins_init();
#endif
#ifdef BSP_USING_ETH
imxrt_enet_pins_init();
#endif
#ifdef BSP_USING_DMA #ifdef BSP_USING_DMA
imxrt_dma_init(); imxrt_dma_init();
#endif #endif
......
...@@ -38,5 +38,11 @@ extern int heap_end; ...@@ -38,5 +38,11 @@ extern int heap_end;
void rt_hw_board_init(void); void rt_hw_board_init(void);
#ifdef BSP_USING_ETH
void imxrt_enet_pins_init(void);
void imxrt_enet_phy_reset_by_gpio(void);
#define PHY_ADDRESS 0x02u
#endif
#endif #endif
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_phy.h"
#include <rtthread.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern uint32_t ENET_GetInstance(ENET_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT;
uint32_t idReg = 0;
status_t result = kStatus_Success;
uint32_t instance = ENET_GetInstance(base);
uint32_t timeDelay;
uint32_t ctlReg = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI(base, srcClock_Hz, false);
/* Initialization after PHY stars to work. */
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
}
if (!counter)
{
return kStatus_Fail;
}
/* Reset PHY. */
counter = PHY_TIMEOUT_COUNT;
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (result == kStatus_Success)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
uint32_t data = 0;
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if ( result != kStatus_Success)
{
return result;
}
result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
if (result != kStatus_Success)
{
return result;
}
#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success)
{
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
if (result == kStatus_Success)
{
/* Check auto negotiation complete. */
while (counter --)
{
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
if ( result == kStatus_Success)
{
PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
{
/* Wait a moment for Phy status stable. */
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
{
__ASM("nop");
}
break;
}
}
if (!counter)
{
return kStatus_PHY_AutoNegotiateFail;
}
}
}
}
}
return result;
}
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
{
uint32_t counter;
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI write command. */
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
/* Wait for SMI complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
{
assert(dataPtr);
uint32_t counter;
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI read command operation. */
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
/* Wait for MII complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Get data from MII register. */
*dataPtr = ENET_ReadSMIData(base);
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
{
status_t result;
uint32_t data = 0;
/* Set the loop mode. */
if (enable)
{
if (mode == kPHY_LocalLoop)
{
if (speed == kPHY_Speed100M)
{
data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
else
{
data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
}
else
{
/* First read the current status in control register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
}
}
}
else
{
/* Disable the loop mode. */
if (mode == kPHY_LocalLoop)
{
/* First read the current status in control register. */
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
if (result == kStatus_Success)
{
data &= ~PHY_BCTL_LOOP_MASK;
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
}
}
else
{
/* First read the current status in control one register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
}
}
}
return result;
}
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
{
assert(status);
status_t result = kStatus_Success;
uint32_t data;
/* Read the basic status register. */
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
if (result == kStatus_Success)
{
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
{
/* link down. */
*status = false;
}
else
{
/* link up. */
*status = true;
}
}
return result;
}
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
{
assert(duplex);
status_t result = kStatus_Success;
uint32_t data, ctlReg;
/* Read the control two register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (result == kStatus_Success)
{
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* Full duplex. */
*duplex = kPHY_FullDuplex;
}
else
{
/* Half duplex. */
*duplex = kPHY_HalfDuplex;
}
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* 100M speed. */
*speed = kPHY_Speed100M;
}
else
{ /* 10M speed. */
*speed = kPHY_Speed10M;
}
}
return result;
}
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_enet.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
/*! @brief Defines the PHY status. */
enum _phy_status
{
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
};
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
typedef enum _phy_speed
{
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
kPHY_Speed100M /*!< ENET PHY 100M speed. */
} phy_speed_t;
/*! @brief Defines the PHY link duplex. */
typedef enum _phy_duplex
{
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
kPHY_FullDuplex /*!< ENET PHY full duplex. */
} phy_duplex_t;
/*! @brief Defines the PHY loopback mode. */
typedef enum _phy_loop
{
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
} phy_loop_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
/*!
* @brief Enables/disables PHY loopback.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* the two loopback mode should not be both set. when one loopback mode is set
* the other one should be disabled.
* @param speed PHY speed for loopback mode.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY loopback success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
/*!
* @brief Gets the PHY link status.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PHY_H_ */
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx
* 2019-4-25 misonyo port to IMXRT
*/
#ifndef SDRAM_PORT_H__
#define SDRAM_PORT_H__
/* parameters for sdram peripheral */
#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
#define SDRAM_REGION kSEMC_SDRAM_CS0
/* CS pin: kSEMC_MUXCSX0/1/2/3 */
#define SDRAM_CS_PIN kSEMC_MUXCSX0
/* size(kbyte):32MB = 32*1024*1KBytes */
#define SDRAM_SIZE ((uint32_t)0x8000)
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
/* Timing configuration for W9825G6KH */
/* TRP:precharge to active command time (ns) */
#define SDRAM_TRP 18
/* TRCD:active to read/write command delay time (ns) */
#define SDRAM_TRCD 18
/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
#define SDRAM_REFRESH_RECOVERY 67
/* TWR:write recovery time (ns). */
#define SDRAM_TWR 12
/* TRAS:active to precharge command time (ns). */
#define SDRAM_TRAS 42
/* TRC time (ns). */
#define SDRAM_TRC 60
/* active to active time (ns). */
#define SDRAM_ACT2ACT 60
/* refresh time (ns). 64ms */
#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
#endif /* SDRAM_PORT_H__ */
...@@ -40,6 +40,9 @@ if GetDepend('BSP_USING_SDRAM'): ...@@ -40,6 +40,9 @@ if GetDepend('BSP_USING_SDRAM'):
if GetDepend('BSP_USING_LCD'): if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c'] src += ['drv_lcd.c']
if GetDepend('BSP_USING_ETH'):
src += ['drv_eth.c']
path = [cwd,cwd + '/config'] path = [cwd,cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
......
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-10-10 Tanek the first version
* 2019-5-10 misonyo add DMA TX and RX function
*/
#include <rtthread.h>
#include "board.h"
#include <rtdevice.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
#include "fsl_enet.h"
#include "fsl_gpio.h"
#include "fsl_phy.h"
#include "fsl_cache.h"
#include "fsl_iomuxc.h"
#ifdef RT_USING_LWIP
#include <netif/ethernetif.h>
#include "lwipopts.h"
#define ENET_RXBD_NUM (4)
#define ENET_TXBD_NUM (4)
#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
/* debug option */
#undef ETH_RX_DUMP
#undef ETH_TX_DUMP
#define DBG_ENABLE
#define DBG_SECTION_NAME "[ETH]"
#define DBG_COLOR
#define DBG_LEVEL DBG_INFO
#include <rtdbg.h>
#define MAX_ADDR_LEN 6
struct rt_imxrt_eth
{
/* inherit from ethernet device */
struct eth_device parent;
enet_handle_t enet_handle;
ENET_Type *enet_base;
enet_data_error_stats_t error_statistic;
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
rt_bool_t tx_is_waiting;
struct rt_semaphore tx_wait;
enet_mii_speed_t speed;
enet_mii_duplex_t duplex;
};
ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable");
ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)];
ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable");
ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)];
static struct rt_imxrt_eth imxrt_eth_device;
void _enet_rx_callback(struct rt_imxrt_eth *eth)
{
rt_err_t result;
ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt);
result = eth_device_ready(&(eth->parent));
if (result != RT_EOK)
rt_kprintf("RX err =%d\n", result);
}
void _enet_tx_callback(struct rt_imxrt_eth *eth)
{
if (eth->tx_is_waiting == RT_TRUE)
{
eth->tx_is_waiting = RT_FALSE;
rt_sem_release(&eth->tx_wait);
}
}
void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData)
{
switch (event)
{
case kENET_RxEvent:
_enet_rx_callback((struct rt_imxrt_eth *)userData);
break;
case kENET_TxEvent:
_enet_tx_callback((struct rt_imxrt_eth *)userData);
break;
case kENET_ErrEvent:
dbg_log(DBG_LOG, "kENET_ErrEvent\n");
break;
case kENET_WakeUpEvent:
dbg_log(DBG_LOG, "kENET_WakeUpEvent\n");
break;
case kENET_TimeStampEvent:
dbg_log(DBG_LOG, "kENET_TimeStampEvent\n");
break;
case kENET_TimeStampAvailEvent:
dbg_log(DBG_LOG, "kENET_TimeStampAvailEvent \n");
break;
default:
dbg_log(DBG_LOG, "unknow error\n");
break;
}
}
static void _enet_clk_init(void)
{
const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1};
CLOCK_InitEnetPll(&config);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
IOMUXC_GPR->GPR1|=1<<23;
}
static void _enet_config(void)
{
enet_config_t config;
uint32_t sysClock;
/* prepare the buffer configuration. */
enet_buffer_config_t buffConfig =
{
ENET_RXBD_NUM,
ENET_TXBD_NUM,
SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
&g_rxBuffDescrip[0],
&g_txBuffDescrip[0],
&g_rxDataBuff[0][0],
&g_txDataBuff[0][0],
};
/* Get default configuration. */
/*
* config.miiMode = kENET_RmiiMode;
* config.miiSpeed = kENET_MiiSpeed100M;
* config.miiDuplex = kENET_MiiFullDuplex;
* config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN;
*/
ENET_GetDefaultConfig(&config);
config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt;
config.miiSpeed = imxrt_eth_device.speed;
config.miiDuplex = imxrt_eth_device.duplex;
/* Set SMI to get PHY link status. */
sysClock = CLOCK_GetFreq(kCLOCK_AhbClk);
dbg_log(DBG_LOG, "deinit\n");
ENET_Deinit(imxrt_eth_device.enet_base);
dbg_log(DBG_LOG, "init\n");
ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock);
dbg_log(DBG_LOG, "set call back\n");
ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device);
dbg_log(DBG_LOG, "active read\n");
ENET_ActiveRead(imxrt_eth_device.enet_base);
}
#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
static void packet_dump(const char *msg, const struct pbuf *p)
{
const struct pbuf *q;
rt_uint32_t i, j;
rt_uint8_t *ptr;
rt_kprintf("%s %d byte\n", msg, p->tot_len);
i = 0;
for (q = p; q != RT_NULL; q = q->next)
{
ptr = q->payload;
for (j = 0; j < q->len; j++)
{
if ((i % 8) == 0)
{
rt_kprintf(" ");
}
if ((i % 16) == 0)
{
rt_kprintf("\r\n");
}
rt_kprintf("%02x ", *ptr);
i++;
ptr++;
}
}
rt_kprintf("\n\n");
}
#else
#define packet_dump(...)
#endif /* dump */
/* initialize the interface */
static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
{
dbg_log(DBG_LOG, "rt_imxrt_eth_init...\n");
_enet_config();
return RT_EOK;
}
static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n");
return RT_EOK;
}
static rt_err_t rt_imxrt_eth_close(rt_device_t dev)
{
dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n");
return RT_EOK;
}
static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
{
dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n");
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
}
static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
{
assert(ringId < FSL_FEATURE_ENET_QUEUE);
switch (ringId)
{
case 0:
base->TDAR = ENET_TDAR_TDAR_MASK;
break;
#if FSL_FEATURE_ENET_QUEUE > 1
case kENET_Ring1:
base->TDAR1 = ENET_TDAR1_TDAR_MASK;
break;
case kENET_Ring2:
base->TDAR2 = ENET_TDAR2_TDAR_MASK;
break;
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
default:
base->TDAR = ENET_TDAR_TDAR_MASK;
break;
}
}
static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length)
{
assert(handle);
assert(data);
volatile enet_tx_bd_struct_t *curBuffDescrip;
uint32_t len = 0;
uint32_t sizeleft = 0;
uint32_t address;
/* Check the frame length. */
if (length > ENET_FRAME_MAX_FRAMELEN)
{
return kStatus_ENET_TxFrameOverLen;
}
/* Check if the transmit buffer is ready. */
curBuffDescrip = handle->txBdCurrent[0];
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
{
return kStatus_ENET_TxFrameBusy;
}
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
bool isPtpEventMessage = false;
/* Check PTP message with the PTP header. */
isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/* One transmit buffer is enough for one frame. */
if (handle->txBuffSizeAlign[0] >= length)
{
/* Copy data to the buffer for uDMA transfer. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0);
/* Set data length. */
curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* For enable the timestamp. */
if (isPtpEventMessage)
{
curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
else
{
curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK);
/* Increase the buffer descriptor address. */
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
{
handle->txBdCurrent[0] = handle->txBdBase[0];
}
else
{
handle->txBdCurrent[0]++;
}
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, length);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
_ENET_ActiveSend(base, 0);
return kStatus_Success;
}
else
{
/* One frame requires more than one transmit buffers. */
do
{
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* For enable the timestamp. */
if (isPtpEventMessage)
{
curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
else
{
curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
}
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/* Increase the buffer descriptor address. */
if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
{
handle->txBdCurrent[0] = handle->txBdBase[0];
}
else
{
handle->txBdCurrent[0]++;
}
/* update the size left to be transmit. */
sizeleft = length - len;
if (sizeleft > handle->txBuffSizeAlign[0])
{
/* Data copy. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
/* Data length update. */
curBuffDescrip->length = handle->txBuffSizeAlign[0];
len += handle->txBuffSizeAlign[0];
/* Sets the control flag. */
curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
/* Active the transmit buffer descriptor*/
_ENET_ActiveSend(base, 0);
}
else
{
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, sizeleft);
curBuffDescrip->length = sizeleft;
/* Set Last buffer wrap flag. */
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
/* Add the cache clean maintain. */
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
_ENET_ActiveSend(base, 0);
return kStatus_Success;
}
/* Get the current buffer descriptor address. */
curBuffDescrip = handle->txBdCurrent[0];
} while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
return kStatus_ENET_TxFrameBusy;
}
}
/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
{
rt_err_t result = RT_EOK;
enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
RT_ASSERT(p != NULL);
RT_ASSERT(enet_handle != RT_NULL);
dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len);
#ifdef ETH_TX_DUMP
packet_dump("send", p);
#endif
do
{
result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
if (result == kStatus_ENET_TxFrameBusy)
{
imxrt_eth_device.tx_is_waiting = RT_TRUE;
rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER);
}
}
while (result == kStatus_ENET_TxFrameBusy);
return RT_EOK;
}
/* reception packet. */
struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
{
uint32_t length = 0;
status_t status;
struct pbuf *p = RT_NULL;
enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle;
ENET_Type *enet_base = imxrt_eth_device.enet_base;
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
/* Get the Frame size */
status = ENET_GetRxFrameSize(enet_handle, &length);
/* Call ENET_ReadFrame when there is a received frame. */
if (length != 0)
{
/* Received valid frame. Deliver the rx buffer with the size equal to length. */
p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
if (p != NULL)
{
status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length);
if (status == kStatus_Success)
{
#ifdef ETH_RX_DUMP
packet_dump("recv", p);
#endif
return p;
}
else
{
dbg_log(DBG_LOG, " A frame read failed\n");
pbuf_free(p);
}
}
else
{
dbg_log(DBG_LOG, " pbuf_alloc faild\n");
}
}
else if (status == kStatus_ENET_RxFrameError)
{
dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
/* Update the received buffer when error happened. */
/* Get the error information of the received g_frame. */
ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
/* update the receive buffer. */
ENET_ReadFrame(enet_base, enet_handle, NULL, 0);
}
ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt);
return NULL;
}
static void phy_monitor_thread_entry(void *parameter)
{
phy_speed_t speed;
phy_duplex_t duplex;
bool link = false;
imxrt_enet_phy_reset_by_gpio();
PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk));
while (1)
{
bool new_link = false;
status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link);
if ((status == kStatus_Success) && (link != new_link))
{
link = new_link;
if (link) // link up
{
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base,
PHY_ADDRESS, &speed, &duplex);
if (kPHY_Speed10M == speed)
{
dbg_log(DBG_LOG, "10M\n");
}
else
{
dbg_log(DBG_LOG, "100M\n");
}
if (kPHY_HalfDuplex == duplex)
{
dbg_log(DBG_LOG, "half dumplex\n");
}
else
{
dbg_log(DBG_LOG, "full dumplex\n");
}
if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed)
|| (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
{
imxrt_eth_device.speed = (enet_mii_speed_t)speed;
imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex;
dbg_log(DBG_LOG, "link up, and update eth mode.\n");
rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device);
}
else
{
dbg_log(DBG_LOG, "link up, eth not need re-config.\n");
}
dbg_log(DBG_LOG, "link up.\n");
eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE);
}
else
{
dbg_log(DBG_LOG, "link down.\n");
eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE);
}
}
rt_thread_delay(RT_TICK_PER_SECOND * 2);
}
}
static int rt_hw_imxrt_eth_init(void)
{
rt_err_t state;
_enet_clk_init();
/* NXP (Freescale) MAC OUI */
imxrt_eth_device.dev_addr[0] = 0x00;
imxrt_eth_device.dev_addr[1] = 0x04;
imxrt_eth_device.dev_addr[2] = 0x9F;
/* generate MAC addr from 96bit unique ID (only for test). */
imxrt_eth_device.dev_addr[3] = 0x05;
imxrt_eth_device.dev_addr[4] = 0x44;
imxrt_eth_device.dev_addr[5] = 0xE5;
imxrt_eth_device.speed = kENET_MiiSpeed100M;
imxrt_eth_device.duplex = kENET_MiiFullDuplex;
imxrt_eth_device.enet_base = ENET;
imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init;
imxrt_eth_device.parent.parent.open = rt_imxrt_eth_open;
imxrt_eth_device.parent.parent.close = rt_imxrt_eth_close;
imxrt_eth_device.parent.parent.read = rt_imxrt_eth_read;
imxrt_eth_device.parent.parent.write = rt_imxrt_eth_write;
imxrt_eth_device.parent.parent.control = rt_imxrt_eth_control;
imxrt_eth_device.parent.parent.user_data = RT_NULL;
imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx;
imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx;
dbg_log(DBG_LOG, "sem init: tx_wait\r\n");
/* init tx semaphore */
rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
/* register eth device */
dbg_log(DBG_LOG, "eth_device_init start\r\n");
state = eth_device_init(&(imxrt_eth_device.parent), "e0");
if (RT_EOK == state)
{
dbg_log(DBG_LOG, "eth_device_init success\r\n");
}
else
{
dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state);
}
eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE);
/* start phy monitor */
{
rt_thread_t tid;
tid = rt_thread_create("phy",
phy_monitor_thread_entry,
RT_NULL,
512,
RT_THREAD_PRIORITY_MAX - 2,
2);
if (tid != RT_NULL)
rt_thread_startup(tid);
}
return state;
}
INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
#endif
#ifdef RT_USING_FINSH
#include <finsh.h>
void phy_read(uint32_t phyReg)
{
uint32_t data;
status_t status;
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data);
if (kStatus_Success == status)
{
rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data);
}
else
{
rt_kprintf("PHY_Read: %02X --> faild", phyReg);
}
}
void phy_write(uint32_t phyReg, uint32_t data)
{
status_t status;
status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data);
if (kStatus_Success == status)
{
rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data);
}
else
{
rt_kprintf("PHY_Write: %02X --> faild\n", phyReg);
}
}
void phy_dump(void)
{
uint32_t data;
status_t status;
int i;
for (i = 0; i < 32; i++)
{
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data);
if (kStatus_Success != status)
{
rt_kprintf("phy_dump: %02X --> faild", i);
break;
}
if (i % 8 == 7)
{
rt_kprintf("%02X --> %08X ", i, data);
}
else
{
rt_kprintf("%02X --> %08X\n", i, data);
}
}
}
void enet_reg_dump(void)
{
ENET_Type *enet_base = imxrt_eth_device.enet_base;
#define DUMP_REG(__REG) \
rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG)
DUMP_REG(EIR);
DUMP_REG(EIMR);
DUMP_REG(RDAR);
DUMP_REG(TDAR);
DUMP_REG(ECR);
DUMP_REG(MMFR);
DUMP_REG(MSCR);
DUMP_REG(MIBC);
DUMP_REG(RCR);
DUMP_REG(TCR);
DUMP_REG(PALR);
DUMP_REG(PAUR);
DUMP_REG(OPD);
DUMP_REG(TXIC);
DUMP_REG(RXIC);
DUMP_REG(IAUR);
DUMP_REG(IALR);
DUMP_REG(GAUR);
DUMP_REG(GALR);
DUMP_REG(TFWR);
DUMP_REG(RDSR);
DUMP_REG(TDSR);
DUMP_REG(MRBR);
DUMP_REG(RSFL);
DUMP_REG(RSEM);
DUMP_REG(RAEM);
DUMP_REG(RAFL);
DUMP_REG(TSEM);
DUMP_REG(TAEM);
DUMP_REG(TAFL);
DUMP_REG(TIPG);
DUMP_REG(FTRL);
DUMP_REG(TACC);
DUMP_REG(RACC);
DUMP_REG(RMON_T_DROP);
DUMP_REG(RMON_T_PACKETS);
DUMP_REG(RMON_T_BC_PKT);
DUMP_REG(RMON_T_MC_PKT);
DUMP_REG(RMON_T_CRC_ALIGN);
DUMP_REG(RMON_T_UNDERSIZE);
DUMP_REG(RMON_T_OVERSIZE);
DUMP_REG(RMON_T_FRAG);
DUMP_REG(RMON_T_JAB);
DUMP_REG(RMON_T_COL);
DUMP_REG(RMON_T_P64);
DUMP_REG(RMON_T_P65TO127);
DUMP_REG(RMON_T_P128TO255);
DUMP_REG(RMON_T_P256TO511);
DUMP_REG(RMON_T_P512TO1023);
DUMP_REG(RMON_T_P1024TO2047);
DUMP_REG(RMON_T_P_GTE2048);
DUMP_REG(RMON_T_OCTETS);
DUMP_REG(IEEE_T_DROP);
DUMP_REG(IEEE_T_FRAME_OK);
DUMP_REG(IEEE_T_1COL);
DUMP_REG(IEEE_T_MCOL);
DUMP_REG(IEEE_T_DEF);
DUMP_REG(IEEE_T_LCOL);
DUMP_REG(IEEE_T_EXCOL);
DUMP_REG(IEEE_T_MACERR);
DUMP_REG(IEEE_T_CSERR);
DUMP_REG(IEEE_T_SQE);
DUMP_REG(IEEE_T_FDXFC);
DUMP_REG(IEEE_T_OCTETS_OK);
DUMP_REG(RMON_R_PACKETS);
DUMP_REG(RMON_R_BC_PKT);
DUMP_REG(RMON_R_MC_PKT);
DUMP_REG(RMON_R_CRC_ALIGN);
DUMP_REG(RMON_R_UNDERSIZE);
DUMP_REG(RMON_R_OVERSIZE);
DUMP_REG(RMON_R_FRAG);
DUMP_REG(RMON_R_JAB);
DUMP_REG(RMON_R_RESVD_0);
DUMP_REG(RMON_R_P64);
DUMP_REG(RMON_R_P65TO127);
DUMP_REG(RMON_R_P128TO255);
DUMP_REG(RMON_R_P256TO511);
DUMP_REG(RMON_R_P512TO1023);
DUMP_REG(RMON_R_P1024TO2047);
DUMP_REG(RMON_R_P_GTE2048);
DUMP_REG(RMON_R_OCTETS);
DUMP_REG(IEEE_R_DROP);
DUMP_REG(IEEE_R_FRAME_OK);
DUMP_REG(IEEE_R_CRC);
DUMP_REG(IEEE_R_ALIGN);
DUMP_REG(IEEE_R_MACERR);
DUMP_REG(IEEE_R_FDXFC);
DUMP_REG(IEEE_R_OCTETS_OK);
DUMP_REG(ATCR);
DUMP_REG(ATVR);
DUMP_REG(ATOFF);
DUMP_REG(ATPER);
DUMP_REG(ATCOR);
DUMP_REG(ATINC);
DUMP_REG(ATSTMP);
DUMP_REG(TGSR);
}
void enet_nvic_tog(void)
{
NVIC_SetPendingIRQ(ENET_IRQn);
}
void enet_rx_stat(void)
{
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
#define DUMP_STAT(__VAR) \
rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR);
DUMP_STAT(statsRxLenGreaterErr);
DUMP_STAT(statsRxAlignErr);
DUMP_STAT(statsRxFcsErr);
DUMP_STAT(statsRxOverRunErr);
DUMP_STAT(statsRxTruncateErr);
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
DUMP_STAT(statsRxProtocolChecksumErr);
DUMP_STAT(statsRxIpHeadChecksumErr);
DUMP_STAT(statsRxMacErr);
DUMP_STAT(statsRxPhyErr);
DUMP_STAT(statsRxCollisionErr);
DUMP_STAT(statsTxErr);
DUMP_STAT(statsTxFrameErr);
DUMP_STAT(statsTxOverFlowErr);
DUMP_STAT(statsTxLateCollisionErr);
DUMP_STAT(statsTxExcessCollisionErr);
DUMP_STAT(statsTxUnderFlowErr);
DUMP_STAT(statsTxTsErr);
#endif
}
void enet_buf_info(void)
{
int i = 0;
for (i = 0; i < ENET_RXBD_NUM; i++)
{
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
i,
g_rxBuffDescrip[i].length,
g_rxBuffDescrip[i].control,
g_rxBuffDescrip[i].buffer);
}
for (i = 0; i < ENET_TXBD_NUM; i++)
{
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
i,
g_txBuffDescrip[i].length,
g_txBuffDescrip[i].control,
g_txBuffDescrip[i].buffer);
}
}
FINSH_FUNCTION_EXPORT(phy_read, read phy register);
FINSH_FUNCTION_EXPORT(phy_write, write phy register);
FINSH_FUNCTION_EXPORT(phy_dump, dump phy registers);
FINSH_FUNCTION_EXPORT(enet_reg_dump, dump enet registers);
FINSH_FUNCTION_EXPORT(enet_nvic_tog, toggle enet nvic pendding bit);
FINSH_FUNCTION_EXPORT(enet_rx_stat, dump enet rx statistic);
FINSH_FUNCTION_EXPORT(enet_buf_info, dump enet tx and tx buffer descripter);
#endif
...@@ -66,10 +66,17 @@ int rt_hw_sdram_Init(void) ...@@ -66,10 +66,17 @@ int rt_hw_sdram_Init(void)
} }
else else
{ {
LOG_D("sdram init success, mapped at 0x%X, size is %d bytes.", SDRAM_BANK_ADDR, SDRAM_SIZE); LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE);
#ifdef RT_USING_MEMHEAP_AS_HEAP #ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */ /*
rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE); * If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap.
* The heap start address is (base + half size), and the size is (half size - 2M).
* The reasons are:
* 1. Reserve the half space for SDRAM link case
* 2. Reserve the 2M for non-cache space
*/
rt_memheap_init(&system_heap, "sdram", (void *)(SDRAM_BANK_ADDR + (SDRAM_SIZE * 1024)/2),
(SDRAM_SIZE * 1024)/2 - (2 * 1024 * 1024));
#endif #endif
} }
......
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