From 5f0102865d3fc4eaa6d68e9393c3481c50340e71 Mon Sep 17 00:00:00 2001 From: xuzhuoyi Date: Mon, 22 Aug 2016 15:59:53 +0800 Subject: [PATCH] [bsp][stm32f429-disco] Fix assertion failed at function:rt_malloc --- bsp/stm32f429-disco/Libraries/SConscript | 4 +- bsp/stm32f429-disco/drivers/board.c | 5 + bsp/stm32f429-disco/drivers/board.h | 2 + bsp/stm32f429-disco/drivers/drv_sdram.c | 245 ++++++++++++++++++++--- bsp/stm32f429-disco/drivers/drv_sdram.h | 56 +----- bsp/stm32f429-disco/rtconfig.py | 6 +- 6 files changed, 240 insertions(+), 78 deletions(-) diff --git a/bsp/stm32f429-disco/Libraries/SConscript b/bsp/stm32f429-disco/Libraries/SConscript index 8bc01cafeb..41cea2d657 100644 --- a/bsp/stm32f429-disco/Libraries/SConscript +++ b/bsp/stm32f429-disco/Libraries/SConscript @@ -17,9 +17,9 @@ src += Glob('STM32F4xx_HAL_Driver/Src/*.c') if rtconfig.CROSS_TOOL == 'gcc': src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s'] elif rtconfig.CROSS_TOOL == 'keil': - src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s'] + src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s'] elif rtconfig.CROSS_TOOL == 'iar': - src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s'] + src = src + ['CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s'] path = [cwd + '/STM32F4xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32F4xx/Include', diff --git a/bsp/stm32f429-disco/drivers/board.c b/bsp/stm32f429-disco/drivers/board.c index 144948e812..da089d20ec 100644 --- a/bsp/stm32f429-disco/drivers/board.c +++ b/bsp/stm32f429-disco/drivers/board.c @@ -20,6 +20,11 @@ #include "usart.h" #include "stm32f4xx_hal.h" +void _init(void) +{ + +} + /** * @brief This function is executed in case of error occurrence. * @param None diff --git a/bsp/stm32f429-disco/drivers/board.h b/bsp/stm32f429-disco/drivers/board.h index 4388ef242f..5774ab94a3 100644 --- a/bsp/stm32f429-disco/drivers/board.h +++ b/bsp/stm32f429-disco/drivers/board.h @@ -76,6 +76,8 @@ void rt_hw_board_init(void); #define FINSH_DEVICE_NAME CONSOLE_DEVICE +void Error_Handler(void); + #endif // <<< Use Configuration Wizard in Context Menu >>> diff --git a/bsp/stm32f429-disco/drivers/drv_sdram.c b/bsp/stm32f429-disco/drivers/drv_sdram.c index eea0be065c..529cfb51b8 100644 --- a/bsp/stm32f429-disco/drivers/drv_sdram.c +++ b/bsp/stm32f429-disco/drivers/drv_sdram.c @@ -26,13 +26,193 @@ #include "drv_sdram.h" #include "stm32f4xx_ll_fmc.h" #include +#include "board.h" SDRAM_HandleTypeDef hsdram1; +FMC_SDRAM_CommandTypeDef command; +/** + * @brief SDRAM MSP Initialization + * This function configures the hardware resources used in this example: + * - Peripheral's clock enable + * - Peripheral's GPIO Configuration + * @param hsdram: SDRAM handle pointer + * @retval None + */ +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) +{ + GPIO_InitTypeDef GPIO_Init_Structure; + + /*##-1- Enable peripherals and GPIO Clocks #################################*/ + /* Enable GPIO clocks */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /*##-2- Configure peripheral GPIO ##########################################*/ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+--------------------+--------------------+ + + SDRAM pins assignment + + +-------------------+--------------------+--------------------+--------------------+ + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ + | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | + | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | + +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | + | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | + | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | + | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | + +-------------------+--------------------+--------------------+ + | PB5 <-> FMC_SDCKE1| + | PB6 <-> FMC_SDNE1 | + | PC0 <-> FMC_SDNWE | + +-------------------+ + +*/ + + /* Common GPIO configuration */ + GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP; + GPIO_Init_Structure.Speed = GPIO_SPEED_FAST; + GPIO_Init_Structure.Pull = GPIO_NOPULL; + GPIO_Init_Structure.Alternate = GPIO_AF12_FMC; + + /* GPIOB configuration */ + GPIO_Init_Structure.Pin = GPIO_PIN_5 | GPIO_PIN_6; + HAL_GPIO_Init(GPIOB, &GPIO_Init_Structure); + + /* GPIOC configuration */ + GPIO_Init_Structure.Pin = GPIO_PIN_0; + HAL_GPIO_Init(GPIOC, &GPIO_Init_Structure); + + /* GPIOD configuration */ + GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | + GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | + GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure); -#ifndef USE_Delay -static void delay(__IO uint32_t nCount); -#endif /* USE_Delay*/ + /* GPIOE configuration */ + GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | + GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | + GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure); + + /* GPIOF configuration */ + GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | + GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | + GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | + GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure); + + /* GPIOG configuration */ + GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | + GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure); +} + +/** + * @brief SDRAM MSP De-Initialization + * This function frees the hardware resources used in this example: + * - Disable the Peripheral's clock + * - Revert GPIO configuration to their default state + * @param hsdram: SDRAM handle pointer + * @retval None + */ +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) +{ + /*## Disable peripherals and GPIO Clocks ###################################*/ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5 | GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 |\ + GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 |\ + GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 |\ + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |\ + GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\ + GPIO_PIN_14 | GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |\ + GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 |\ + GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\ + GPIO_PIN_14 | GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); +} + +/** + * @brief Perform the SDRAM exernal memory inialization sequence + * @param hsdram: SDRAM handle + * @param Command: Pointer to SDRAM command structure + * @retval None + */ +static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command) +{ + __IO uint32_t tmpmrd =0; + /* Step 3: Configure a clock configuration enable command */ + Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; + Command->AutoRefreshNumber = 1; + Command->ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); + + /* Step 4: Insert 100 ms delay */ + /* interrupt is not enable, just to delay some time. */ + for (tmpmrd = 0; tmpmrd < 0xfffff; tmpmrd ++) + ; + + /* Step 5: Configure a PALL (precharge all) command */ + Command->CommandMode = FMC_SDRAM_CMD_PALL; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; + Command->AutoRefreshNumber = 1; + Command->ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); + + /* Step 6 : Configure a Auto-Refresh command */ + Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; + Command->AutoRefreshNumber = 4; + Command->ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); + + /* Step 7: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; + Command->AutoRefreshNumber = 1; + Command->ModeRegisterDefinition = tmpmrd; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); + + /* Step 8: Set the refresh rate counter */ + /* (15.62 us x Freq) - 20 */ + /* Set the device refresh counter */ + HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT); +} /** * @brief Configures the FMC and GPIOs to interface with the SDRAM memory. @@ -43,36 +223,49 @@ static void delay(__IO uint32_t nCount); */ void SDRAM_Init(void) { - FMC_SDRAM_TimingTypeDef SdramTiming; + FMC_SDRAM_TimingTypeDef SDRAM_Timing; - /** Perform the SDRAM1 memory initialization sequence - */ + /*##-1- Configure the SDRAM device #########################################*/ + /* SDRAM device configuration */ hsdram1.Instance = FMC_SDRAM_DEVICE; - /* hsdram1.Init */ - hsdram1.Init.SDBank = FMC_SDRAM_BANK2; - hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; - hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_11; - hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; + + /* Timing configuration for 90 MHz of SD clock frequency (180MHz/2) */ + /* TMRD: 2 Clock cycles */ + SDRAM_Timing.LoadToActiveDelay = 2; + /* TXSR: min=70ns (6x11.90ns) */ + SDRAM_Timing.ExitSelfRefreshDelay = 7; + /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ + SDRAM_Timing.SelfRefreshTime = 4; + /* TRC: min=63 (6x11.90ns) */ + SDRAM_Timing.RowCycleDelay = 7; + /* TWR: 2 Clock cycles */ + SDRAM_Timing.WriteRecoveryTime = 2; + /* TRP: 15ns => 2x11.90ns */ + SDRAM_Timing.RPDelay = 2; + /* TRCD: 15ns => 2x11.90ns */ + SDRAM_Timing.RCDDelay = 2; + + hsdram1.Init.SDBank = FMC_SDRAM_BANK2; + hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + hsdram1.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; - hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; - hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; - hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; - hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; - hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; - /* SdramTiming */ - SdramTiming.LoadToActiveDelay = 16; - SdramTiming.ExitSelfRefreshDelay = 16; - SdramTiming.SelfRefreshTime = 16; - SdramTiming.RowCycleDelay = 16; - SdramTiming.WriteRecoveryTime = 16; - SdramTiming.RPDelay = 16; - SdramTiming.RCDDelay = 16; - - if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) + hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; + hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + hsdram1.Init.SDClockPeriod = SDCLOCK_PERIOD; + hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; + hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; + + /* Initialize the SDRAM controller */ + if(HAL_SDRAM_Init(&hsdram1, &SDRAM_Timing) != HAL_OK) { + /* Initialization Error */ Error_Handler(); } + /* Program the SDRAM external device */ + SDRAM_Initialization_Sequence(&hsdram1, &command); + } rt_err_t sdram_hw_init(void) diff --git a/bsp/stm32f429-disco/drivers/drv_sdram.h b/bsp/stm32f429-disco/drivers/drv_sdram.h index 87fcd097e8..67825f602d 100644 --- a/bsp/stm32f429-disco/drivers/drv_sdram.h +++ b/bsp/stm32f429-disco/drivers/drv_sdram.h @@ -25,57 +25,16 @@ #include -#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) +#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) -/** - * @brief FMC SDRAM Memory Width - */ -/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */ -#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b - -/** - * @brief FMC SDRAM CAS Latency - */ -/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */ -#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 - -/** - * @brief FMC SDRAM Memory clock period - */ -#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */ -/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */ - -/** - * @brief FMC SDRAM Memory Read Burst feature - */ -#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */ -/* #define SDRAM_READBURST FMC_Read_Burst_Enable */ - -/** - * @brief FMC SDRAM Bank Remap - */ -/* #define SDRAM_BANK_REMAP */ +/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 +/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 */ +#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ - -/* #define USE_Delay */ - -#ifdef USE_Delay - #define __Delay Delay /* User can provide more timing precise __Delay function - (with 10ms time base), using SysTick for example */ -#else - #define __Delay delay /* Default __Delay function with less precise timing */ -#endif - -/** - * @brief FMC SDRAM Mode definition register defines - */ #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) @@ -88,6 +47,9 @@ #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +#define BUFFER_SIZE ((uint32_t)0x0100) +#define WRITE_READ_ADDR ((uint32_t)0x0800) +#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90MHz SD clock) */ /** * @} */ diff --git a/bsp/stm32f429-disco/rtconfig.py b/bsp/stm32f429-disco/rtconfig.py index 7af669802c..e056e87d67 100644 --- a/bsp/stm32f429-disco/rtconfig.py +++ b/bsp/stm32f429-disco/rtconfig.py @@ -41,9 +41,9 @@ if PLATFORM == 'gcc': OBJCPY = PREFIX + 'objcopy' DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -g -Wall -DSTM32F429ZI -DSTM32F429_439xx -DUSE_STDPERIPH_DRIVER -D__ASSEMBLY__' + CFLAGS = DEVICE + ' -g -Wall -DSTM32F429ZI -DSTM32F429_439xx -D__ASSEMBLY__' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld' CPATH = '' LPATH = '' @@ -65,7 +65,7 @@ elif PLATFORM == 'armcc': TARGET_EXT = 'axf' DEVICE = ' --cpu=cortex-m4.fp' - CFLAGS = DEVICE + ' --apcs=interwork -DUSE_STDPERIPH_DRIVER -DSTM32F429_439xx' + CFLAGS = DEVICE + ' --apcs=interwork -DSTM32F429_439xx' AFLAGS = DEVICE LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct' -- GitLab