From 467aa3fe4c5f24e8c967b5450f23804d9fc1bb7c Mon Sep 17 00:00:00 2001 From: "bernard.xiong" Date: Thu, 2 Jul 2009 23:30:53 +0000 Subject: [PATCH] import lm3s, lpc2148/lpc2478, x86/qemu, AT91SAM7S/7X, s3c44b0, STM32F103ZE bsp git-svn-id: https://rt-thread.googlecode.com/svn/trunk@6 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- bsp/lm3s/application.c | 56 + bsp/lm3s/board.c | 112 + bsp/lm3s/board.h | 24 + bsp/lm3s/driverlib/adc.c | 979 + bsp/lm3s/driverlib/adc.h | 149 + bsp/lm3s/driverlib/can.c | 2203 +++ bsp/lm3s/driverlib/can.h | 458 + bsp/lm3s/driverlib/comp.c | 439 + bsp/lm3s/driverlib/comp.h | 133 + bsp/lm3s/driverlib/cpu.c | 189 + bsp/lm3s/driverlib/cpu.h | 60 + bsp/lm3s/driverlib/cr_project.xml | 66 + bsp/lm3s/driverlib/debug.h | 56 + bsp/lm3s/driverlib/driverlib.Opt | 59 + bsp/lm3s/driverlib/driverlib.Uv2 | 124 + bsp/lm3s/driverlib/driverlib.ewp | 839 + bsp/lm3s/driverlib/driverlib.sgxx | Bin 0 -> 3442 bytes bsp/lm3s/driverlib/epi.c | 1039 + bsp/lm3s/driverlib/epi.h | 229 + bsp/lm3s/driverlib/ethernet.c | 1280 ++ bsp/lm3s/driverlib/ethernet.h | 172 + bsp/lm3s/driverlib/flash.c | 915 + bsp/lm3s/driverlib/flash.h | 89 + bsp/lm3s/driverlib/gpio.c | 1512 ++ bsp/lm3s/driverlib/gpio.h | 768 + bsp/lm3s/driverlib/hibernate.c | 965 + bsp/lm3s/driverlib/hibernate.h | 130 + bsp/lm3s/driverlib/i2c.c | 1109 ++ bsp/lm3s/driverlib/i2c.h | 170 + bsp/lm3s/driverlib/i2s.c | 1139 ++ bsp/lm3s/driverlib/i2s.h | 157 + bsp/lm3s/driverlib/interrupt.c | 550 + bsp/lm3s/driverlib/interrupt.h | 76 + bsp/lm3s/driverlib/mpu.c | 449 + bsp/lm3s/driverlib/mpu.h | 150 + bsp/lm3s/driverlib/pin_map.h | 20416 ++++++++++++++++++++ bsp/lm3s/driverlib/pwm.c | 1728 ++ bsp/lm3s/driverlib/pwm.h | 277 + bsp/lm3s/driverlib/qei.c | 619 + bsp/lm3s/driverlib/qei.h | 115 + bsp/lm3s/driverlib/readme.txt | 24 + bsp/lm3s/driverlib/rom.h | 2252 +++ bsp/lm3s/driverlib/rom_map.h | 2763 +++ bsp/lm3s/driverlib/ssi.c | 680 + bsp/lm3s/driverlib/ssi.h | 127 + bsp/lm3s/driverlib/sysctl.c | 2319 +++ bsp/lm3s/driverlib/sysctl.h | 469 + bsp/lm3s/driverlib/systick.c | 262 + bsp/lm3s/driverlib/systick.h | 66 + bsp/lm3s/driverlib/timer.c | 1007 + bsp/lm3s/driverlib/timer.h | 153 + bsp/lm3s/driverlib/uart.c | 1621 ++ bsp/lm3s/driverlib/uart.h | 246 + bsp/lm3s/driverlib/udma.c | 1247 ++ bsp/lm3s/driverlib/udma.h | 338 + bsp/lm3s/driverlib/usb.c | 3434 ++++ bsp/lm3s/driverlib/usb.h | 433 + bsp/lm3s/driverlib/watchdog.c | 567 + bsp/lm3s/driverlib/watchdog.h | 74 + bsp/lm3s/inc/asmdefs.h | 215 + bsp/lm3s/inc/cr_project.xml | 29 + bsp/lm3s/inc/hw_adc.h | 1159 ++ bsp/lm3s/inc/hw_can.h | 756 + bsp/lm3s/inc/hw_comp.h | 277 + bsp/lm3s/inc/hw_epi.h | 428 + bsp/lm3s/inc/hw_ethernet.h | 683 + bsp/lm3s/inc/hw_flash.h | 328 + bsp/lm3s/inc/hw_gpio.h | 593 + bsp/lm3s/inc/hw_hibernate.h | 245 + bsp/lm3s/inc/hw_i2c.h | 412 + bsp/lm3s/inc/hw_i2s.h | 233 + bsp/lm3s/inc/hw_ints.h | 140 + bsp/lm3s/inc/hw_memmap.h | 118 + bsp/lm3s/inc/hw_nvic.h | 1027 + bsp/lm3s/inc/hw_pwm.h | 716 + bsp/lm3s/inc/hw_qei.h | 201 + bsp/lm3s/inc/hw_ssi.h | 220 + bsp/lm3s/inc/hw_sysctl.h | 1625 ++ bsp/lm3s/inc/hw_timer.h | 452 + bsp/lm3s/inc/hw_types.h | 176 + bsp/lm3s/inc/hw_uart.h | 436 + bsp/lm3s/inc/hw_udma.h | 320 + bsp/lm3s/inc/hw_usb.h | 4638 +++++ bsp/lm3s/inc/hw_watchdog.h | 178 + bsp/lm3s/inc/inc.sgxx | Bin 0 -> 1247 bytes bsp/lm3s/project.Opt | 80 + bsp/lm3s/project.Uv2 | 140 + bsp/lm3s/rtconfig.h | 135 + bsp/lm3s/startup.c | 139 + bsp/stm32/application.c | 303 + bsp/stm32/board.c | 405 + bsp/stm32/board.h | 25 + bsp/stm32/cortexm3_macro.s | 279 + bsp/stm32/enc28j60.c | 727 + bsp/stm32/enc28j60.h | 256 + bsp/stm32/kbd.c | 91 + bsp/stm32/kbd.h | 7 + bsp/stm32/lcd.c | 487 + bsp/stm32/lcd.h | 148 + bsp/stm32/library/inc/cortexm3_macro.h | 53 + bsp/stm32/library/inc/stm32f10x_adc.h | 300 + bsp/stm32/library/inc/stm32f10x_bkp.h | 122 + bsp/stm32/library/inc/stm32f10x_can.h | 263 + bsp/stm32/library/inc/stm32f10x_crc.h | 37 + bsp/stm32/library/inc/stm32f10x_dac.h | 167 + bsp/stm32/library/inc/stm32f10x_dbgmcu.h | 55 + bsp/stm32/library/inc/stm32f10x_dma.h | 297 + bsp/stm32/library/inc/stm32f10x_exti.h | 107 + bsp/stm32/library/inc/stm32f10x_flash.h | 208 + bsp/stm32/library/inc/stm32f10x_fsmc.h | 337 + bsp/stm32/library/inc/stm32f10x_gpio.h | 237 + bsp/stm32/library/inc/stm32f10x_i2c.h | 285 + bsp/stm32/library/inc/stm32f10x_iwdg.h | 69 + bsp/stm32/library/inc/stm32f10x_lib.h | 124 + bsp/stm32/library/inc/stm32f10x_map.h | 7603 ++++++++ bsp/stm32/library/inc/stm32f10x_nvic.h | 287 + bsp/stm32/library/inc/stm32f10x_pwr.h | 77 + bsp/stm32/library/inc/stm32f10x_rcc.h | 288 + bsp/stm32/library/inc/stm32f10x_rtc.h | 70 + bsp/stm32/library/inc/stm32f10x_sdio.h | 337 + bsp/stm32/library/inc/stm32f10x_spi.h | 289 + bsp/stm32/library/inc/stm32f10x_systick.h | 64 + bsp/stm32/library/inc/stm32f10x_tim.h | 778 + bsp/stm32/library/inc/stm32f10x_type.h | 80 + bsp/stm32/library/inc/stm32f10x_usart.h | 253 + bsp/stm32/library/inc/stm32f10x_wwdg.h | 54 + bsp/stm32/library/src/stm32f10x_adc.c | 1402 ++ bsp/stm32/library/src/stm32f10x_bkp.c | 272 + bsp/stm32/library/src/stm32f10x_can.c | 907 + bsp/stm32/library/src/stm32f10x_crc.c | 114 + bsp/stm32/library/src/stm32f10x_dac.c | 389 + bsp/stm32/library/src/stm32f10x_dbgmcu.c | 97 + bsp/stm32/library/src/stm32f10x_dma.c | 678 + bsp/stm32/library/src/stm32f10x_exti.c | 219 + bsp/stm32/library/src/stm32f10x_flash.c | 919 + bsp/stm32/library/src/stm32f10x_fsmc.c | 851 + bsp/stm32/library/src/stm32f10x_gpio.c | 583 + bsp/stm32/library/src/stm32f10x_i2c.c | 1216 ++ bsp/stm32/library/src/stm32f10x_iwdg.c | 148 + bsp/stm32/library/src/stm32f10x_lib.c | 303 + bsp/stm32/library/src/stm32f10x_nvic.c | 751 + bsp/stm32/library/src/stm32f10x_pwr.c | 280 + bsp/stm32/library/src/stm32f10x_rcc.c | 1105 ++ bsp/stm32/library/src/stm32f10x_rtc.c | 320 + bsp/stm32/library/src/stm32f10x_sdio.c | 832 + bsp/stm32/library/src/stm32f10x_spi.c | 863 + bsp/stm32/library/src/stm32f10x_systick.c | 181 + bsp/stm32/library/src/stm32f10x_tim.c | 3219 +++ bsp/stm32/library/src/stm32f10x_usart.c | 1001 + bsp/stm32/library/src/stm32f10x_wwdg.c | 185 + bsp/stm32/project.Opt | 197 + bsp/stm32/project.Uv2 | 277 + bsp/stm32/project.ewd | 1299 ++ bsp/stm32/project.ewp | 1805 ++ bsp/stm32/project.eww | 10 + bsp/stm32/rtc.c | 217 + bsp/stm32/rtc.h | 6 + bsp/stm32/rtconfig.h | 158 + bsp/stm32/sdcard.c | 3108 +++ bsp/stm32/sdcard.h | 264 + bsp/stm32/startup.c | 150 + bsp/stm32/stm32f10x_conf.h | 174 + bsp/stm32/stm32f10x_flash.icf | 32 + bsp/stm32/stm32f10x_it.c | 919 + bsp/stm32/stm32f10x_it.h | 100 + bsp/stm32/usart.c | 341 + bsp/stm32/usart.h | 9 + 167 files changed, 115651 insertions(+) create mode 100644 bsp/lm3s/application.c create mode 100644 bsp/lm3s/board.c create mode 100644 bsp/lm3s/board.h create mode 100644 bsp/lm3s/driverlib/adc.c create mode 100644 bsp/lm3s/driverlib/adc.h create mode 100644 bsp/lm3s/driverlib/can.c create mode 100644 bsp/lm3s/driverlib/can.h create mode 100644 bsp/lm3s/driverlib/comp.c create mode 100644 bsp/lm3s/driverlib/comp.h create mode 100644 bsp/lm3s/driverlib/cpu.c create mode 100644 bsp/lm3s/driverlib/cpu.h create mode 100644 bsp/lm3s/driverlib/cr_project.xml create mode 100644 bsp/lm3s/driverlib/debug.h create mode 100644 bsp/lm3s/driverlib/driverlib.Opt create mode 100644 bsp/lm3s/driverlib/driverlib.Uv2 create mode 100644 bsp/lm3s/driverlib/driverlib.ewp create mode 100644 bsp/lm3s/driverlib/driverlib.sgxx create mode 100644 bsp/lm3s/driverlib/epi.c create mode 100644 bsp/lm3s/driverlib/epi.h create mode 100644 bsp/lm3s/driverlib/ethernet.c create mode 100644 bsp/lm3s/driverlib/ethernet.h create mode 100644 bsp/lm3s/driverlib/flash.c create mode 100644 bsp/lm3s/driverlib/flash.h create mode 100644 bsp/lm3s/driverlib/gpio.c create mode 100644 bsp/lm3s/driverlib/gpio.h create mode 100644 bsp/lm3s/driverlib/hibernate.c create mode 100644 bsp/lm3s/driverlib/hibernate.h create mode 100644 bsp/lm3s/driverlib/i2c.c create mode 100644 bsp/lm3s/driverlib/i2c.h create mode 100644 bsp/lm3s/driverlib/i2s.c create mode 100644 bsp/lm3s/driverlib/i2s.h create mode 100644 bsp/lm3s/driverlib/interrupt.c create mode 100644 bsp/lm3s/driverlib/interrupt.h create mode 100644 bsp/lm3s/driverlib/mpu.c create mode 100644 bsp/lm3s/driverlib/mpu.h create mode 100644 bsp/lm3s/driverlib/pin_map.h create mode 100644 bsp/lm3s/driverlib/pwm.c create mode 100644 bsp/lm3s/driverlib/pwm.h create mode 100644 bsp/lm3s/driverlib/qei.c create mode 100644 bsp/lm3s/driverlib/qei.h create mode 100644 bsp/lm3s/driverlib/readme.txt create mode 100644 bsp/lm3s/driverlib/rom.h create mode 100644 bsp/lm3s/driverlib/rom_map.h create mode 100644 bsp/lm3s/driverlib/ssi.c create mode 100644 bsp/lm3s/driverlib/ssi.h create mode 100644 bsp/lm3s/driverlib/sysctl.c create mode 100644 bsp/lm3s/driverlib/sysctl.h create mode 100644 bsp/lm3s/driverlib/systick.c create mode 100644 bsp/lm3s/driverlib/systick.h create mode 100644 bsp/lm3s/driverlib/timer.c create mode 100644 bsp/lm3s/driverlib/timer.h create mode 100644 bsp/lm3s/driverlib/uart.c create mode 100644 bsp/lm3s/driverlib/uart.h create mode 100644 bsp/lm3s/driverlib/udma.c create mode 100644 bsp/lm3s/driverlib/udma.h create mode 100644 bsp/lm3s/driverlib/usb.c create mode 100644 bsp/lm3s/driverlib/usb.h create mode 100644 bsp/lm3s/driverlib/watchdog.c create mode 100644 bsp/lm3s/driverlib/watchdog.h create mode 100644 bsp/lm3s/inc/asmdefs.h create mode 100644 bsp/lm3s/inc/cr_project.xml create mode 100644 bsp/lm3s/inc/hw_adc.h create mode 100644 bsp/lm3s/inc/hw_can.h create mode 100644 bsp/lm3s/inc/hw_comp.h create mode 100644 bsp/lm3s/inc/hw_epi.h create mode 100644 bsp/lm3s/inc/hw_ethernet.h create mode 100644 bsp/lm3s/inc/hw_flash.h create mode 100644 bsp/lm3s/inc/hw_gpio.h create mode 100644 bsp/lm3s/inc/hw_hibernate.h create mode 100644 bsp/lm3s/inc/hw_i2c.h create mode 100644 bsp/lm3s/inc/hw_i2s.h create mode 100644 bsp/lm3s/inc/hw_ints.h create mode 100644 bsp/lm3s/inc/hw_memmap.h create mode 100644 bsp/lm3s/inc/hw_nvic.h create mode 100644 bsp/lm3s/inc/hw_pwm.h create mode 100644 bsp/lm3s/inc/hw_qei.h create mode 100644 bsp/lm3s/inc/hw_ssi.h create mode 100644 bsp/lm3s/inc/hw_sysctl.h create mode 100644 bsp/lm3s/inc/hw_timer.h create mode 100644 bsp/lm3s/inc/hw_types.h create mode 100644 bsp/lm3s/inc/hw_uart.h create mode 100644 bsp/lm3s/inc/hw_udma.h create mode 100644 bsp/lm3s/inc/hw_usb.h create mode 100644 bsp/lm3s/inc/hw_watchdog.h create mode 100644 bsp/lm3s/inc/inc.sgxx create mode 100644 bsp/lm3s/project.Opt create mode 100644 bsp/lm3s/project.Uv2 create mode 100644 bsp/lm3s/rtconfig.h create mode 100644 bsp/lm3s/startup.c create mode 100644 bsp/stm32/application.c create mode 100644 bsp/stm32/board.c create mode 100644 bsp/stm32/board.h create mode 100644 bsp/stm32/cortexm3_macro.s create mode 100644 bsp/stm32/enc28j60.c create mode 100644 bsp/stm32/enc28j60.h create mode 100644 bsp/stm32/kbd.c create mode 100644 bsp/stm32/kbd.h create mode 100644 bsp/stm32/lcd.c create mode 100644 bsp/stm32/lcd.h create mode 100644 bsp/stm32/library/inc/cortexm3_macro.h create mode 100644 bsp/stm32/library/inc/stm32f10x_adc.h create mode 100644 bsp/stm32/library/inc/stm32f10x_bkp.h create mode 100644 bsp/stm32/library/inc/stm32f10x_can.h create mode 100644 bsp/stm32/library/inc/stm32f10x_crc.h create mode 100644 bsp/stm32/library/inc/stm32f10x_dac.h create mode 100644 bsp/stm32/library/inc/stm32f10x_dbgmcu.h create mode 100644 bsp/stm32/library/inc/stm32f10x_dma.h create mode 100644 bsp/stm32/library/inc/stm32f10x_exti.h create mode 100644 bsp/stm32/library/inc/stm32f10x_flash.h create mode 100644 bsp/stm32/library/inc/stm32f10x_fsmc.h create mode 100644 bsp/stm32/library/inc/stm32f10x_gpio.h create mode 100644 bsp/stm32/library/inc/stm32f10x_i2c.h create mode 100644 bsp/stm32/library/inc/stm32f10x_iwdg.h create mode 100644 bsp/stm32/library/inc/stm32f10x_lib.h create mode 100644 bsp/stm32/library/inc/stm32f10x_map.h create mode 100644 bsp/stm32/library/inc/stm32f10x_nvic.h create mode 100644 bsp/stm32/library/inc/stm32f10x_pwr.h create mode 100644 bsp/stm32/library/inc/stm32f10x_rcc.h create mode 100644 bsp/stm32/library/inc/stm32f10x_rtc.h create mode 100644 bsp/stm32/library/inc/stm32f10x_sdio.h create mode 100644 bsp/stm32/library/inc/stm32f10x_spi.h create mode 100644 bsp/stm32/library/inc/stm32f10x_systick.h create mode 100644 bsp/stm32/library/inc/stm32f10x_tim.h create mode 100644 bsp/stm32/library/inc/stm32f10x_type.h create mode 100644 bsp/stm32/library/inc/stm32f10x_usart.h create mode 100644 bsp/stm32/library/inc/stm32f10x_wwdg.h create mode 100644 bsp/stm32/library/src/stm32f10x_adc.c create mode 100644 bsp/stm32/library/src/stm32f10x_bkp.c create mode 100644 bsp/stm32/library/src/stm32f10x_can.c create mode 100644 bsp/stm32/library/src/stm32f10x_crc.c create mode 100644 bsp/stm32/library/src/stm32f10x_dac.c create mode 100644 bsp/stm32/library/src/stm32f10x_dbgmcu.c create mode 100644 bsp/stm32/library/src/stm32f10x_dma.c create mode 100644 bsp/stm32/library/src/stm32f10x_exti.c create mode 100644 bsp/stm32/library/src/stm32f10x_flash.c create mode 100644 bsp/stm32/library/src/stm32f10x_fsmc.c create mode 100644 bsp/stm32/library/src/stm32f10x_gpio.c create mode 100644 bsp/stm32/library/src/stm32f10x_i2c.c create mode 100644 bsp/stm32/library/src/stm32f10x_iwdg.c create mode 100644 bsp/stm32/library/src/stm32f10x_lib.c create mode 100644 bsp/stm32/library/src/stm32f10x_nvic.c create mode 100644 bsp/stm32/library/src/stm32f10x_pwr.c create mode 100644 bsp/stm32/library/src/stm32f10x_rcc.c create mode 100644 bsp/stm32/library/src/stm32f10x_rtc.c create mode 100644 bsp/stm32/library/src/stm32f10x_sdio.c create mode 100644 bsp/stm32/library/src/stm32f10x_spi.c create mode 100644 bsp/stm32/library/src/stm32f10x_systick.c create mode 100644 bsp/stm32/library/src/stm32f10x_tim.c create mode 100644 bsp/stm32/library/src/stm32f10x_usart.c create mode 100644 bsp/stm32/library/src/stm32f10x_wwdg.c create mode 100644 bsp/stm32/project.Opt create mode 100644 bsp/stm32/project.Uv2 create mode 100644 bsp/stm32/project.ewd create mode 100644 bsp/stm32/project.ewp create mode 100644 bsp/stm32/project.eww create mode 100644 bsp/stm32/rtc.c create mode 100644 bsp/stm32/rtc.h create mode 100644 bsp/stm32/rtconfig.h create mode 100644 bsp/stm32/sdcard.c create mode 100644 bsp/stm32/sdcard.h create mode 100644 bsp/stm32/startup.c create mode 100644 bsp/stm32/stm32f10x_conf.h create mode 100644 bsp/stm32/stm32f10x_flash.icf create mode 100644 bsp/stm32/stm32f10x_it.c create mode 100644 bsp/stm32/stm32f10x_it.h create mode 100644 bsp/stm32/usart.c create mode 100644 bsp/stm32/usart.h diff --git a/bsp/lm3s/application.c b/bsp/lm3s/application.c new file mode 100644 index 0000000000..b574fc4d48 --- /dev/null +++ b/bsp/lm3s/application.c @@ -0,0 +1,56 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +/** + * @addtogroup LM3S + */ +/*@{*/ + +#include +#include + +char thread1_stack[0x120]; +struct rt_thread thread1; + +void thread1_entry(void* parameter) +{ + rt_uint32_t i = 0; + + while (1) + { + rt_kprintf("thread1 --> %d\n", ++i); + rt_thread_delay(100); + } +} + +void thread_test() +{ + rt_thread_init(&thread1, + "thread1", + thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), + 20, 15); + + rt_thread_startup(&thread1); +} +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT(thread_test, test a basic thread) +#endif + +int rt_application_init() +{ + return 0; +} +/*@}*/ diff --git a/bsp/lm3s/board.c b/bsp/lm3s/board.c new file mode 100644 index 0000000000..87e3bf178b --- /dev/null +++ b/bsp/lm3s/board.c @@ -0,0 +1,112 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-05-16 Bernard first implementation + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static void rt_hw_console_init(void); + +/** + * @addtogroup LM3S + */ + +/*@{*/ + +extern void rt_hw_interrupt_thread_switch(void); +/** + * This is the timer interrupt service routine. + * + */ +void rt_hw_timer_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} + +/** + * This function will initial STM32 board. + */ +void rt_hw_board_init() +{ + /* set clock */ + SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | + SYSCTL_XTAL_6MHZ); + + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); + + /* init console */ + rt_hw_console_init(); + + /* enable interrupt */ + IntMasterEnable(); +} + +/* init console to support rt_kprintf */ +static void rt_hw_console_init() +{ + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); +} + +/* write one character to serial, must not trigger interrupt */ +static void rt_hw_console_putc(const char c) +{ + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); +} + +/** + * This function is used by rt_kprintf to display a string on console. + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + rt_hw_console_putc (*str++); + } +} + +/*@}*/ diff --git a/bsp/lm3s/board.h b/bsp/lm3s/board.h new file mode 100644 index 0000000000..3c796846d4 --- /dev/null +++ b/bsp/lm3s/board.h @@ -0,0 +1,24 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +void rt_hw_board_led_on(int n); +void rt_hw_board_led_off(int n); +void rt_hw_board_init(void); + +void rt_hw_usart_init(void); + +#endif diff --git a/bsp/lm3s/driverlib/adc.c b/bsp/lm3s/driverlib/adc.c new file mode 100644 index 0000000000..792fdbc697 --- /dev/null +++ b/bsp/lm3s/driverlib/adc.c @@ -0,0 +1,979 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_adc.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/adc.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// These defines are used by the ADC driver to simplify access to the ADC +// sequencer's registers. +// +//***************************************************************************** +#define ADC_SEQ (ADC_O_SSMUX0) +#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0) +#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0) +#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0) +#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0) +#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0) + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +static unsigned char g_pucOversampleFactor[3]; + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This will enable the global interrupt in the interrupt +//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It +//! is the interrupt handler's responsibility to clear the interrupt source via +//! ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This will disable the +//! global interrupt in the interrupt controller; the sequence interrupt must +//! be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); +} + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified sample sequence. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +unsigned long +ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); + } + else + { + return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); + } +} + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence should be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); +} + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulTrigger is the trigger source that initiates the sample sequence; +//! must be one of the \b ADC_TRIGGER_* values. +//! \param ulPriority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequences range from zero to three; sequence zero will capture +//! up to eight samples, sequences one and two will capture up to four samples, +//! and sequence three will capture a single sample. The trigger condition and +//! priority (with respect to other sample sequence execution) is set. +//! +//! The \e ulTrigger parameter can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! Note that not all trigger sources are available on all Stellaris family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents +//! the highest priority and 3 the lowest. Note that when programming the +//! priority among a set of sample sequences, each must have unique priority; +//! it is up to the caller to guarantee the uniqueness of the priorities. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulTrigger, unsigned long ulPriority) +{ + // + // Check the arugments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || + (ulTrigger == ADC_TRIGGER_COMP0) || + (ulTrigger == ADC_TRIGGER_COMP1) || + (ulTrigger == ADC_TRIGGER_COMP2) || + (ulTrigger == ADC_TRIGGER_EXTERNAL) || + (ulTrigger == ADC_TRIGGER_TIMER) || + (ulTrigger == ADC_TRIGGER_PWM0) || + (ulTrigger == ADC_TRIGGER_PWM1) || + (ulTrigger == ADC_TRIGGER_PWM2) || + (ulTrigger == ADC_TRIGGER_ALWAYS)); + ASSERT(ulPriority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ulSequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & + ~(0xf << ulSequenceNum)) | + ((ulTrigger & 0xf) << ulSequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & + ~(0xf << ulSequenceNum)) | + ((ulPriority & 0x3) << ulSequenceNum)); +} + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step; must be a logical OR of +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). +//! +//! This function will set the configuration of the ADC for one step of a +//! sample sequence. The ADC can be configured for single-ended or +//! differential operation (the \b ADC_CTL_D bit selects differential +//! operation when set), the channel to be sampled can be chosen (the +//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature +//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step +//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it +//! can be configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the +//! appropriate time when the trigger for this sequence occurs. +//! +//! The \e ulStep parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequence, from zero to three for the second and +//! third sample sequence, and can only be zero for the fourth sample sequence. +//! +//! Differential mode only works with adjacent channel pairs (for example, 0 +//! and 1). The channel select must be the number of the channel pair to +//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 +//! and 3) or undefined results will be returned by the ADC. Additionally, if +//! differential mode is selected when the temperature sensor is being sampled, +//! undefined results will be returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulStep, unsigned long ulConfig) +{ + // + // Check the arugments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || + ((ulSequenceNum == 1) && (ulStep < 4)) || + ((ulSequenceNum == 2) && (ulStep < 4)) || + ((ulSequenceNum == 3) && (ulStep < 1))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); +} + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence overflow has occurred. This will +//! happen if the captured samples are not read from the FIFO before the next +//! trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +long +ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); +} + +//***************************************************************************** +// +//! Clears the overflow condition on a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This will clear an overflow condition on one of the sample sequences. The +//! overflow condition must be cleared in order to detect a subsequent overflow +//! condition (it otherwise causes no harm). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear the overflow condition for this sequence. + // + HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence underflow has occurred. This will +//! happen if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +long +ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); +} + +//***************************************************************************** +// +//! Clears the underflow condition on a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This will clear an underflow condition on one of the sample sequences. The +//! underflow condition must be cleared in order to detect a subsequent +//! underflow condition (it otherwise causes no harm). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Clear the underflow condition for this sequence. + // + HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer. The number of samples available in the hardware +//! FIFO are copied into the buffer, which is assumed to be large enough to +//! hold that many samples. This will only return the samples that are +//! presently available, which may not be the entire sample sequence if it is +//! in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +long +ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer) +{ + unsigned long ulCount; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ulCount = 0; + while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO); + + // + // Increment the count of samples read. + // + ulCount++; + } + + // + // Return the number of samples read. + // + return(ulCount); +} + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. +//! +//! \return None. +// +//***************************************************************************** +void +ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; +} + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (that is, the fourth sample sequencer is not +//! supported). Oversampling by 2x (for example) divides the depth of the +//! sample sequencer by two; so 2x oversampling on the first sample sequencer +//! can only provide four samples per trigger. This also means that 8x +//! oversampling is only available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && + ((ulSequenceNum == 0) || (ulFactor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Save the sfiht factor. + // + g_pucOversampleFactor[ulSequenceNum] = ulValue; +} + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; + ulSequenceNum; ulSequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + if(ulSequenceNum != 1) + { + HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 | + ADC_SSCTL0_END0) << ulStep); + } + + // + // Go to the next hardware step. + // + ulStep += 4; + } +} + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! \param ulCount is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items +//! then incorrect results will be returned. It is the caller's responsibility +//! to read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer, unsigned long ulCount) +{ + unsigned long ulIdx, ulAccum; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ulCount--) + { + // + // Compute the sum of the samples. + // + ulAccum = 0; + for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ulAccum += HWREG(ulBase + ADC_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; + } +} + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero will disable hardware +//! oversampling. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 Ksps ADC to 62.5 Ksps. +//! +//! \note Hardware oversampling is available beginning with Rev C0 of the +//! Stellaris microcontroller. +//! +//! \return None. +// +//***************************************************************************** +void +ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); + ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || + (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || + (ulFactor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ulBase + ADC_O_SAC) = ulValue; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/adc.h b/bsp/lm3s/driverlib/adc.h new file mode 100644 index 0000000000..6a008ce7ce --- /dev/null +++ b/bsp/lm3s/driverlib/adc.h @@ -0,0 +1,149 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 +#define ADC_CTL_CH8 0x00000008 // Input channel 8 +#define ADC_CTL_CH9 0x00000009 // Input channel 9 +#define ADC_CTL_CH10 0x0000000A // Input channel 10 +#define ADC_CTL_CH11 0x0000000B // Input channel 11 +#define ADC_CTL_CH12 0x0000000C // Input channel 12 +#define ADC_CTL_CH13 0x0000000D // Input channel 13 +#define ADC_CTL_CH14 0x0000000E // Input channel 14 +#define ADC_CTL_CH15 0x0000000F // Input channel 15 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceOverflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceUnderflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/bsp/lm3s/driverlib/can.c b/bsp/lm3s/driverlib/can.c new file mode 100644 index 0000000000..4bd4c0e105 --- /dev/null +++ b/bsp/lm3s/driverlib/can.c @@ -0,0 +1,2203 @@ +//***************************************************************************** +// +// can.c - Driver for the CAN module. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_can.h" +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/can.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// This is the maximum number that can be stored as an 11bit Message +// identifier. +// +//***************************************************************************** +#define CAN_MAX_11BIT_MSG_ID (0x7ff) + +//***************************************************************************** +// +// This is used as the loop delay for accessing the CAN controller registers. +// +//***************************************************************************** +#define CAN_RW_DELAY (5) + +// +// The maximum CAN bit timing divisor is 13. +// +#define CAN_MAX_BIT_DIVISOR (13) + +// +// The minimum CAN bit timing divisor is 5. +// +#define CAN_MIN_BIT_DIVISOR (5) + +// +// The maximum CAN pre-divisor is 1024. +// +#define CAN_MAX_PRE_DIVISOR (1024) + +// +// The minimum CAN pre-divisor is 1024. +// +#define CAN_MIN_PRE_DIVISOR (1024) + +//***************************************************************************** +// +// This table is used by the CANBitRateSet() API as the register defaults for +// the bit timing values. +// +//***************************************************************************** +static const unsigned short g_usCANBitValues[] = +{ + 0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5 + 0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6 + 0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7 + 0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8 + 0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9 + 0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10 + 0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11 + 0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12 + 0x3740 // TSEG2 4, TSEG1 8, SJW 2, Divide 13 +}; + +//***************************************************************************** +// +//! \internal +//! Checks a CAN base address. +//! +//! \param ulBase is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +CANBaseValid(unsigned long ulBase) +{ + return((ulBase == CAN0_BASE) || (ulBase == CAN1_BASE) || + (ulBase == CAN2_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Returns the CAN controller interrupt number. +//! +//! \param ulBase is the base address of the selected CAN controller +//! +//! Given a CAN controller base address, returns the corresponding interrupt +//! number. +//! +//! This function replaces the original CANGetIntNumber() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return Returns a CAN interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +static long +CANIntNumberGet(unsigned long ulBase) +{ + long lIntNumber; + + // + // Return the interrupt number for the given CAN controller. + // + switch(ulBase) + { + // + // Return the interrupt number for CAN 0 + // + case CAN0_BASE: + { + lIntNumber = INT_CAN0; + break; + } + + // + // Return the interrupt number for CAN 1 + // + case CAN1_BASE: + { + lIntNumber = INT_CAN1; + break; + } + + // + // Return the interrupt number for CAN 2 + // + case CAN2_BASE: + { + lIntNumber = INT_CAN2; + break; + } + + // + // Return -1 to indicate a bad address was passed in. + // + default: + { + lIntNumber = -1; + } + } + return(lIntNumber); +} + +//***************************************************************************** +// +//! \internal +//! +//! Reads a CAN controller register. +//! +//! \param ulRegAddress is the full address of the CAN register to be read. +//! +//! This function performs the necessary synchronization to read from a CAN +//! controller register. +//! +//! This function replaces the original CANReadReg() API and performs the same +//! actions. A macro is provided in can.h to map the original API to +//! this API. +//! +//! \note This function provides the delay required to access CAN registers. +//! This delay is required when accessing CAN registers directly. +//! +//! \return Returns the value read from the register. +// +//***************************************************************************** +static unsigned long +CANRegRead(unsigned long ulRegAddress) +{ + volatile int iDelay; + unsigned long ulRetVal; + unsigned long ulIntNumber; + unsigned long ulReenableInts; + + // + // Get the CAN interrupt number from the register base address. + // + ulIntNumber = CANIntNumberGet(ulRegAddress & 0xfffff000); + + // + // Make sure that the CAN base address was valid. + // + ASSERT(ulIntNumber != (unsigned long)-1); + + // + // Remember current state so that CAN interrupts are only re-enabled if + // they were already enabled. + // + ulReenableInts = HWREG(NVIC_EN1) & (1 << (ulIntNumber - 48)); + + // + // If the CAN interrupt was enabled then disable it. + // + if(ulReenableInts) + { + IntDisable(ulIntNumber); + } + + // + // Trigger the inital read to the CAN controller. The value returned at + // this point is not valid. + // + HWREG(ulRegAddress); + + // + // This delay is necessary for the CAN have the correct data on the bus. + // + for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++) + { + } + + // + // Do the final read that has the valid value of the register. + // + ulRetVal = HWREG(ulRegAddress); + + // + // Reenable CAN interrupts if they were enabled before this call. + // + if(ulReenableInts) + { + IntEnable(ulIntNumber); + } + + return(ulRetVal); +} + +//***************************************************************************** +// +//! \internal +//! +//! Writes a CAN controller register. +//! +//! \param ulRegAddress is the full address of the CAN register to be written. +//! \param ulRegValue is the value to write into the register specified by +//! \e ulRegAddress. +//! +//! This function takes care of the synchronization necessary to write to a +//! CAN controller register. +//! +//! This function replaces the original CANWriteReg() API and performs the same +//! actions. A macro is provided in can.h to map the original API to +//! this API. +//! +//! \note The delays in this function are required when accessing CAN registers +//! directly. +//! +//! \return None. +// +//***************************************************************************** +static void +CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue) +{ + volatile int iDelay; + + // + // Trigger the inital write to the CAN controller. The value will not make + // it out to the CAN controller for CAN_RW_DELAY cycles. + // + HWREG(ulRegAddress) = ulRegValue; + + // + // Delay to allow the CAN controller to receive the new data. + // + for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++) + { + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pucData is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param pulRegister is an unsigned long pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b + +//! \b CAN_O_IF1DA1. +//! \param iSize is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageSet() +//! function. +//! +//! This function replaces the original CANWriteDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +static void +CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize) +{ + int iIdx; + unsigned long ulValue; + + // + // Loop always copies 1 or 2 bytes per iteration. + // + for(iIdx = 0; iIdx < iSize; ) + { + + // + // Write out the data 16 bits at a time since this is how the registers + // are aligned in memory. + // + ulValue = pucData[iIdx++]; + + // + // Only write the second byte if needed otherwise it will be zero. + // + if(iIdx < iSize) + { + ulValue |= (pucData[iIdx++] << 8); + } + CANRegWrite((unsigned long)(pulRegister++), ulValue); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pucData is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param pulRegister is an unsigned long pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b + +//! \b CAN_O_IF1DA1. +//! \param iSize is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageGet() +//! function. +//! +//! This function replaces the original CANReadDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +static void +CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize) +{ + int iIdx; + unsigned long ulValue; + + // + // Loop always copies 1 or 2 bytes per iteration. + // + for(iIdx = 0; iIdx < iSize; ) + { + // + // Read out the data 16 bits at a time since this is how the registers + // are aligned in memory. + // + ulValue = CANRegRead((unsigned long)(pulRegister++)); + + // + // Store the first byte. + // + pucData[iIdx++] = (unsigned char)ulValue; + + // + // Only read the second byte if needed. + // + if(iIdx < iSize) + { + pucData[iIdx++] = (unsigned char)(ulValue >> 8); + } + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller after reset. +//! +//! \param ulBase is the base address of the CAN controller. +//! +//! After reset, the CAN controller is left in the disabled state. However, +//! the memory used for message objects contains undefined values and must be +//! cleared prior to enabling the CAN controller the first time. This prevents +//! unwanted transmission or reception of data before the message objects are +//! configured. This function must be called before enabling the controller +//! the first time. +//! +//! \return None. +// +//***************************************************************************** +void +CANInit(unsigned long ulBase) +{ + int iMsg; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + CANRegWrite(ulBase + CAN_O_CTL, CAN_CTL_INIT); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB | + CAN_IF1CMSK_CONTROL); + CANRegWrite(ulBase + CAN_O_IF1ARB2, 0); + CANRegWrite(ulBase + CAN_O_IF1MCTL, 0); + + // + // Loop through to program all 32 message objects + // + for(iMsg = 1; iMsg <= 32; iMsg++) + { + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Initiate programming the message object + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg); + } + + // + // Make sure that the interrupt and new data flags are updated for the + // message objects. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_NEWDAT | + CAN_IF1CMSK_CLRINTPND); + + // + // Loop through to program all 32 message objects + // + for(iMsg = 1; iMsg <= 32; iMsg++) + { + // + // Wait for busy bit to clear. + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Initiate programming the message object + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg); + } + + // + // Acknowledge any pending status interrupts. + // + CANRegRead(ulBase + CAN_O_STS); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller will automatically transmit any pending frames, and process any +//! received frames. The controller can be stopped by calling CANDisable(). +//! Prior to calling CANEnable(), CANInit() should have been called to +//! initialize the controller and the CAN bus clock should be configured by +//! calling CANBitTimingSet(). +//! +//! \return None. +// +//***************************************************************************** +void +CANEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Clear the init bit in the control register. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) & ~CAN_CTL_INIT); +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller will no longer automatically process data on the CAN bus. The +//! controller can be restarted by calling CANEnable(). The state of the CAN +//! controller and the message objects in the controller are left as they were +//! before this call was made. +//! +//! \return None. +// +//***************************************************************************** +void +CANDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Set the init bit in the control register. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) | CAN_CTL_INIT); +} + +//***************************************************************************** +// +//! Reads the current settings for the CAN controller bit timing. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pClkParms is a pointer to a structure to hold the timing parameters. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing, and stores the resulting information in the structure +//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the +//! values that are returned in the structure pointed to by \e pClkParms. +//! +//! This function replaces the original CANGetBitTiming() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms) +{ + unsigned int uBitReg; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT(pClkParms != 0); + + // + // Read out all the bit timing values from the CAN controller registers. + // + uBitReg = CANRegRead(ulBase + CAN_O_BIT); + + // + // Set the phase 2 segment. + // + pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2_M) >> 12) + 1; + + // + // Set the phase 1 segment. + // + pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1_M) >> 8) + 1; + + // + // Set the sychronous jump width. + // + pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> 6) + 1; + + // + // Set the pre-divider for the CAN bus bit clock. + // + pClkParms->uQuantumPrescaler = + ((uBitReg & CAN_BIT_BRP_M) | + ((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1; +} + +//***************************************************************************** +// +//! This function is used to set the CAN bit timing values to a nominal setting +//! based on a desired bit rate. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulSourceClock is the system clock for the device in Hz. +//! \param ulBitRate is the desired bit rate. +//! +//! This function will set the CAN bit timing for the bit rate passed in the +//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Since the +//! CAN clock is based off of the system clock the calling function should pass +//! in the source clock rate either by retrieving it from SysCtlClockGet() or +//! using a specific value in Hz. The CAN bit clock is calculated to be an +//! average timing value that should work for most systems. If tighter timing +//! requirements are needed, then the CANBitTimingSet() function is available +//! for full customization of all of the CAN bit timing values. Since not all +//! bit rates can be matched exactly, the bit rate is set to the value closest +//! to the desired bit rate without being higher than the \e ulBitRate value. +//! +//! \note On some devices the source clock is fixed at 8MHz so the +//! \e ulSourceClock should be set to 8000000. +//! +//! \return This function returns the bit rate that the CAN controller was +//! configured to use or it returns 0 to indicate that the bit rate was not +//! changed because the requested bit rate was not valid. +//! +//***************************************************************************** +unsigned long +CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock, + unsigned long ulBitRate) +{ + unsigned long ulDesiredRatio; + unsigned long ulCANBits; + unsigned long ulPreDivide; + unsigned long ulRegValue; + unsigned short usCANCTL; + + ASSERT(ulBitRate != 0); + + // + // Caclulate the desired clock rate. + // + ulDesiredRatio = ulSourceClock / ulBitRate; + + // + // If the ratio of CAN bit rate to processor clock is too small or too + // large then return 0 indicating that no bit rate was set. + // + if((ulDesiredRatio > (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)) || + (ulDesiredRatio < CAN_MIN_BIT_DIVISOR)) + { + return(0); + } + + // + // Make sure that the Desired Ratio is not too large. This enforces the + // requirement that the bit rate is larger than requested. + // + if((ulSourceClock / ulDesiredRatio) > ulBitRate) + { + ulDesiredRatio += 1; + } + + // + // Check all possible values to find a matching value. + // + while(ulDesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR) + { + // + // Loop through all possible CAN bit divisors. + // + for(ulCANBits = CAN_MAX_BIT_DIVISOR; ulCANBits >= CAN_MIN_BIT_DIVISOR; + ulCANBits--) + { + // + // For a given CAN bit divisor save the pre divisor. + // + ulPreDivide = ulDesiredRatio / ulCANBits; + + // + // If the caculated divisors match the desired clock ratio then + // return these bit rate and set the CAN bit timing. + // + if((ulPreDivide * ulCANBits) == ulDesiredRatio) + { + // + // Start building the bit timing value by adding the bit timing + // in time quanta. + // + ulRegValue = g_usCANBitValues[ulCANBits - CAN_MIN_BIT_DIVISOR]; + + // + // To set the bit timing register, the controller must be placed + // in init mode (if not already), and also configuration change + // bit enabled. The stat of the register should be saved + // so it can be restored. + // + usCANCTL = CANRegRead(ulBase + CAN_O_CTL); + CANRegWrite(ulBase + CAN_O_CTL, usCANCTL | CAN_CTL_INIT | + CAN_CTL_CCE); + + // + // Now add in the pre-scalar on the bit rate. + // + ulRegValue |= ((ulPreDivide - 1)& CAN_BIT_BRP_M); + + // + // Set the clock bits in the and the lower bits of the + // pre-scalar. + // + CANRegWrite(ulBase + CAN_O_BIT, ulRegValue); + + // + // Set the divider upper bits in the extension register. + // + CANRegWrite(ulBase + CAN_O_BRPE, + ((ulPreDivide - 1) >> 6) & CAN_BRPE_BRPE_M); + + // + // Restore the saved CAN Control register. + // + CANRegWrite(ulBase + CAN_O_CTL, usCANCTL); + + // + // Return the computed bit rate. + // + return(ulSourceClock / ( ulPreDivide * ulCANBits)); + } + } + + // + // Move the divisor up one and look again. Only in rare cases are + // more than 2 loops required to find the value. + // + ulDesiredRatio++; + } + return(0); +} + +//***************************************************************************** +// +//! Configures the CAN controller bit timing. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pClkParms points to the structure with the clock parameters. +//! +//! Configures the various timing parameters for the CAN bus bit timing: +//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and +//! the Synchronization Jump Width. The values for Propagation and Phase +//! Buffer 1 segments are derived from the combination +//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined +//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along +//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual +//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value, +//! which specifies the divisor for the CAN module clock. +//! +//! The total bit time, in quanta, will be the sum of the two Seg parameters, +//! as follows: +//! +//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1 +//! +//! Note that the Sync_Seg is always one quantum in duration, and will be added +//! to derive the correct duration of Prop_Seg and Phase1_Seg. +//! +//! The equation to determine the actual bit rate is as follows: +//! +//! CAN Clock / +//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler)) +//! +//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1, +//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be +//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. +//! +//! This function replaces the original CANSetBitTiming() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms) +{ + unsigned int uBitReg; + unsigned int uSavedInit; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT(pClkParms != 0); + + // + // The phase 1 segment must be in the range from 2 to 16. + // + ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) && + (pClkParms->uSyncPropPhase1Seg <= 16)); + + // + // The phase 2 segment must be in the range from 1 to 8. + // + ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8)); + + // + // The synchronous jump windows must be in the range from 1 to 4. + // + ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4)); + + // + // The CAN clock pre-divider must be in the range from 1 to 1024. + // + ASSERT((pClkParms->uQuantumPrescaler <= 1024) && + (pClkParms->uQuantumPrescaler >= 1)); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. State + // of the init bit should be saved so it can be restored at the end. + // + uSavedInit = CANRegRead(ulBase + CAN_O_CTL); + CANRegWrite(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE); + + // + // Set the bit fields of the bit timing register according to the parms. + // + uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2_M; + uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1_M; + uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW_M; + uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M; + CANRegWrite(ulBase + CAN_O_BIT, uBitReg); + + // + // Set the divider upper bits in the extension register. + // + CANRegWrite(ulBase + CAN_O_BRPE, + ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M); + // + // Clear the config change bit, and restore the init bit. + // + uSavedInit &= ~CAN_CTL_CCE; + + // + // If Init was not set before, then clear it. + // + if(uSavedInit & CAN_CTL_INIT) + { + uSavedInit &= ~CAN_CTL_INIT; + } + CANRegWrite(ulBase + CAN_O_CTL, uSavedInit); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled CAN interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables CAN interrupts on the interrupt controller; specific CAN +//! interrupt sources must be enabled using CANIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! CANIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable CAN interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulIntNumber; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Get the actual interrupt number for this CAN controller. + // + ulIntNumber = CANIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntRegister(ulIntNumber, pfnHandler); + + // + // Enable the Ethernet interrupt. + // + IntEnable(ulIntNumber); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the CAN controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt on the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntUnregister(unsigned long ulBase) +{ + unsigned long ulIntNumber; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Get the actual interrupt number for this CAN controller. + // + ulIntNumber = CANIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntUnregister(ulIntNumber); + + // + // Disable the CAN interrupt. + // + IntDisable(ulIntNumber); +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts +//! +//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled. +//! Further, for any particular transaction from a message object to generate +//! an interrupt, that message object must have interrupts enabled (see +//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the +//! controller enters the ``bus off'' condition, or if the error counters reach +//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few +//! status conditions and may provide more interrupts than the application +//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine +//! the cause. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + + // + // Enable the specified interrupts. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) | ulIntFlags); +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e ulIntFlags parameter has the same definition as in the +//! CANIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + + // + // Disable the specified interrupts. + // + CANRegWrite(ulBase + CAN_O_CTL, + CANRegRead(ulBase + CAN_O_CTL) & ~(ulIntFlags)); +} + +//***************************************************************************** +// +//! Returns the current CAN controller interrupt status. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param eIntStsReg indicates which interrupt status register to read +//! +//! Returns the value of one of two interrupt status registers. The interrupt +//! status register read is determined by the \e eIntStsReg parameter, which +//! can have one of the following values: +//! +//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt +//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message +//! objects +//! +//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register +//! and indicates the cause of the interrupt. It will be a value of +//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, +//! the status register should be read with the CANStatusGet() function. +//! Calling this function to read the status will also clear the status +//! interrupt. If the value of the interrupt register is in the range 1-32, +//! then this indicates the number of the highest priority message object that +//! has an interrupt pending. The message object interrupt can be cleared by +//! using the CANIntClear() function, or by reading the message using +//! CANMessageGet() in the case of a received message. The interrupt handler +//! can read the interrupt status again to make sure all pending interrupts are +//! cleared before returning from the interrupt. +//! +//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects +//! have pending interrupts. This can be used to discover all of the pending +//! interrupts at once, as opposed to repeatedly reading the interrupt register +//! by using \b CAN_INT_STS_CAUSE. +//! +//! \return Returns the value of one of the interrupt status registers. +// +//***************************************************************************** +unsigned long +CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // See which status the caller is looking for. + // + switch(eIntStsReg) + { + // + // The caller wants the global interrupt status for the CAN controller + // specified by ulBase. + // + case CAN_INT_STS_CAUSE: + { + ulStatus = CANRegRead(ulBase + CAN_O_INT); + break; + } + + // + // The caller wants the current message status interrupt for all + // messages. + // + case CAN_INT_STS_OBJECT: + { + // + // Read and combine both 16 bit values into one 32bit status. + // + ulStatus = (CANRegRead(ulBase + CAN_O_MSG1INT) & + CAN_MSG1INT_INTPND_M); + ulStatus |= (CANRegRead(ulBase + CAN_O_MSG2INT) << 16); + break; + } + + // + // Request was for unknown status so just return 0. + // + default: + { + ulStatus = 0; + break; + } + } + // + // Return the interrupt status value + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulIntClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e ulIntClr parameter should be one of the following values: +//! +//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt. +//! - 1-32 - Clears the specified message object interrupt +//! +//! It is not necessary to use this function to clear an interrupt. This +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. +//! +//! Normally, the status interrupt is cleared by reading the controller status +//! using CANStatusGet(). A specific message object interrupt is normally +//! cleared by reading the message object using CANMessageGet(). +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +CANIntClear(unsigned long ulBase, unsigned long ulIntClr) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulIntClr == CAN_INT_INTID_STATUS) || + ((ulIntClr>=1) && (ulIntClr <=32))); + + if(ulIntClr == CAN_INT_INTID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + CANRegRead(ulBase + CAN_O_STS); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMSK_CLRINTPND bit. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_CLRINTPND); + + // + // Send the clear pending interrupt command to the CAN controller. + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IF1CRQ_MNUM_M); + + // + // Wait to be sure that this interface is not busy. + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + } +} + +//***************************************************************************** +// +//! Sets the CAN controller automatic retransmission behavior. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param bAutoRetry enables automatic retransmission. +//! +//! Enables or disables automatic retransmission of messages with detected +//! errors. If \e bAutoRetry is \b true, then automatic retransmission is +//! enabled, otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry) +{ + unsigned long ulCtlReg; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + ulCtlReg = CANRegRead(ulBase + CAN_O_CTL); + + // + // Conditionally set the DAR bit to enable/disable auto-retry. + // + if(bAutoRetry) + { + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + ulCtlReg &= ~CAN_CTL_DAR; + } + else + { + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + ulCtlReg |= CAN_CTL_DAR; + } + + CANRegWrite(ulBase + CAN_O_CTL, ulCtlReg); +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param ulBase is the base address of the CAN controller. +//! +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +tBoolean +CANRetryGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + if(CANRegRead(ulBase + CAN_O_CTL) & CAN_CTL_DAR) + { + // + // Automatic data retransmission is not enabled. + // + return(false); + } + + // + // Automatic data retransmission is enabled. + // + return(true); +} + +//***************************************************************************** +// +//! Reads one of the controller status registers. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param eStatusReg is the status register to read. +//! +//! Reads a status register of the CAN controller and returns it to the caller. +//! The different status registers are: +//! +//! - \b CAN_STS_CONTROL - the main controller status +//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission +//! - \b CAN_STS_NEWDAT - bit mask of objects with new data +//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration +//! +//! When reading the main controller status register, a pending status +//! interrupt will be cleared. This should be used in the interrupt handler +//! for the CAN controller if the cause is a status interrupt. The controller +//! status register fields are as follows: +//! +//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition +//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 +//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state +//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of +//! any message filtering). +//! - \b CAN_STATUS_TXOK - a message was successfully transmitted +//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits) +//! - \b CAN_STATUS_LEC_NONE - no error +//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected +//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part +//! of a message +//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged +//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in +//! recessive mode +//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in +//! dominant mode +//! - \b CAN_STATUS_LEC_CRC - CRC error in received message +//! +//! The remaining status registers are 32-bit bit maps to the message objects. +//! They can be used to quickly obtain information about the status of all the +//! message objects without needing to query each one. They contain the +//! following information: +//! +//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that +//! means that a transmission is pending on that object. The application can +//! use this to determine which objects are still waiting to send a message. +//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means +//! that a new message has been received in that object, and has not yet been +//! picked up by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means +//! it has a valid configuration programmed. The host application can use this +//! to determine which message objects are empty/unused. +//! +//! \return Returns the value of the status register. +// +//***************************************************************************** +unsigned long +CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + switch(eStatusReg) + { + // + // Just return the global CAN status register since that is what was + // requested. + // + case CAN_STS_CONTROL: + { + ulStatus = CANRegRead(ulBase + CAN_O_STS); + CANRegWrite(ulBase + CAN_O_STS, + ~(CAN_STS_RXOK | CAN_STS_TXOK | CAN_STS_LEC_M)); + break; + } + + // + // Combine the Transmit status bits into one 32bit value. + // + case CAN_STS_TXREQUEST: + { + ulStatus = CANRegRead(ulBase + CAN_O_TXRQ1); + ulStatus |= CANRegRead(ulBase + CAN_O_TXRQ2) << 16; + break; + } + + // + // Combine the New Data status bits into one 32bit value. + // + case CAN_STS_NEWDAT: + { + ulStatus = CANRegRead(ulBase + CAN_O_NWDA1); + ulStatus |= CANRegRead(ulBase + CAN_O_NWDA2) << 16; + break; + } + + // + // Combine the Message valid status bits into one 32bit value. + // + case CAN_STS_MSGVAL: + { + ulStatus = CANRegRead(ulBase + CAN_O_MSG1VAL); + ulStatus |= CANRegRead(ulBase + CAN_O_MSG2VAL) << 16; + break; + } + + // + // Unknown CAN status requested so return 0. + // + default: + { + ulStatus = 0; + break; + } + } + return(ulStatus); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param pulRxCount is a pointer to storage for the receive error counter. +//! \param pulTxCount is a pointer to storage for the transmit error counter. +//! +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. +//! +//! After this call, \e *pulRxCount will hold the current receive error count +//! and \e *pulTxCount will hold the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +tBoolean +CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, + unsigned long *pulTxCount) +{ + unsigned long ulCANError; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + + // + // Read the current count of transmit/receive errors. + // + ulCANError = CANRegRead(ulBase + CAN_O_ERR); + + // + // Extract the error numbers from the register value. + // + *pulRxCount = (ulCANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S; + *pulTxCount = (ulCANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S; + + if(ulCANError & CAN_ERR_RP) + { + return(true); + } + return(false); +} + +//***************************************************************************** +// +//! Configures a message object in the CAN controller. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulObjID is the object number to configure (1-32). +//! \param pMsgObject is a pointer to a structure containing message object +//! settings. +//! \param eMsgType indicates the type of message for this object. +//! +//! This function is used to configure any one of the 32 message objects in the +//! CAN controller. A message object can be configured as any type of CAN +//! message object as well as several options for automatic transmission and +//! reception. This call also allows the message object to be configured to +//! generate interrupts on completion of message receipt or transmission. The +//! message object can also be configured with a filter/mask so that actions +//! are only taken when a message that meets certain parameters is seen on the +//! CAN bus. +//! +//! The \e eMsgType parameter must be one of the following values: +//! +//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object. +//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object. +//! - \b MSG_OBJ_TYPE_RX - CAN receive message object. +//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object. +//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then +//! transmit message object. +//! +//! The message object pointed to by \e pMsgObject must be populated by the +//! caller, as follows: +//! +//! - \e ulMsgID - contains the message ID, either 11 or 29 bits. +//! - \e ulMsgIDMask - mask of bits from \e ulMsgID that must match if +//! identifier filtering is enabled. +//! - \e ulFlags +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission. +//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the +//! identifier mask specified by \e ulMsgIDMask. +//! - \e ulMsgLen - the number of bytes in the message data. This should be +//! non-zero even for a remote frame; it should match the expected bytes of the +//! data responding data frame. +//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a +//! data frame. +//! +//! \b Example: To send a data frame or remote frame(in response to a remote +//! request), take the following steps: +//! +//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. +//! -# Set \e pMsgObject->ulMsgID to the message ID. +//! -# Set \e pMsgObject->ulFlags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to +//! allow an interrupt to be generated when the message is sent. +//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the data frame. +//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes +//! to send in the message. +//! -# Call this function with \e ulObjID set to one of the 32 object buffers. +//! +//! \b Example: To receive a specific data frame, take the following steps: +//! +//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX. +//! -# Set \e pMsgObject->ulMsgID to the full message ID, or a partial mask to +//! use partial ID matching. +//! -# Set \e pMsgObject->ulMsgIDMask bits that should be used for masking +//! during comparison. +//! -# Set \e pMsgObject->ulFlags as follows: +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame +//! is received. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering. +//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data +//! frame. +//! -# The buffer pointed to by \e pMsgObject->pucMsgData and +//! \e pMsgObject->ulMsgLen are not used by this call as no data is present at +//! the time of the call. +//! -# Call this function with \e ulObjID set to one of the 32 object buffers. +//! +//! If you specify a message object buffer that already contains a message +//! definition, it will be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageSet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType) +{ + unsigned short usCmdMaskReg; + unsigned short usMaskReg[2]; + unsigned short usArbReg[2]; + unsigned short usMsgCtrl; + tBoolean bTransferData; + tBoolean bUseExtendedID; + + bTransferData = 0; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulObjID <= 32) && (ulObjID != 0)); + ASSERT((eMsgType == MSG_OBJ_TYPE_TX) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RX) || + (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE)); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // See if we need to use an extended identifier or not. + // + if((pMsgObject->ulMsgID > CAN_MAX_11BIT_MSG_ID) || + (pMsgObject->ulFlags & MSG_OBJ_EXTENDED_ID)) + { + bUseExtendedID = 1; + } + else + { + bUseExtendedID = 0; + } + + // + // This is always a write to the Message object as this call is setting a + // message object. This call will also always set all size bits so it sets + // both data bits. The call will use the CONTROL register to set control + // bits so this bit needs to be set as well. + // + usCmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | + CAN_IF1CMSK_CONTROL); + + // + // Initialize the values to a known state before filling them in based on + // the type of message object that is being configured. + // + usArbReg[0] = 0; + usMsgCtrl = 0; + usMaskReg[0] = 0; + usMaskReg[1] = 0; + + switch(eMsgType) + { + // + // Transmit message object. + // + case MSG_OBJ_TYPE_TX: + { + // + // Set the TXRQST bit and the reset the rest of the register. + // + usMsgCtrl |= CAN_IF1MCTL_TXRQST; + usArbReg[1] = CAN_IF1ARB2_DIR; + bTransferData = 1; + break; + } + + // + // Transmit remote request message object + // + case MSG_OBJ_TYPE_TX_REMOTE: + { + // + // Set the TXRQST bit and the reset the rest of the register. + // + usMsgCtrl |= CAN_IF1MCTL_TXRQST; + usArbReg[1] = 0; + break; + } + + // + // Receive message object. + // + case MSG_OBJ_TYPE_RX: + { + // + // This clears the DIR bit along with everthing else. The TXRQST + // bit was cleard by defaulting usMsgCtrl to 0. + // + usArbReg[1] = 0; + break; + } + + // + // Receive remote request message object. + // + case MSG_OBJ_TYPE_RX_REMOTE: + { + // + // The DIR bit is set to one for remote receivers. The TXRQST bit + // was cleard by defaulting usMsgCtrl to 0. + // + usArbReg[1] = CAN_IF1ARB2_DIR; + + // + // Set this object so that it only indicates that a remote frame + // was received and allow for software to handle it by sending back + // a data frame. + // + usMsgCtrl = CAN_IF1MCTL_UMASK; + + // + // Use the full Identifier by default. + // + usMaskReg[0] = 0xffff; + usMaskReg[1] = 0x1fff; + + // + // Make sure to send the mask to the message object. + // + usCmdMaskReg |= CAN_IF1CMSK_MASK; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Oddly the DIR bit is set to one for remote receivers. + // + usArbReg[1] = CAN_IF1ARB2_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + usMsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; + + // + // The data to be returned needs to be filled in. + // + bTransferData = 1; + break; + } + + // + // This case should never happen due to the ASSERT statement at the + // beginning of this function. + // + default: + { + return; + } + } + + // + // Configure the Mask Registers. + // + if(pMsgObject->ulFlags & MSG_OBJ_USE_ID_FILTER) + { + if(bUseExtendedID) + { + // + // Set the 29 bits of Identifier mask that were requested. + // + usMaskReg[0] = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M; + usMaskReg[1] = ((pMsgObject->ulMsgIDMask >> 16) & + CAN_IF1MSK2_IDMSK_M); + } + else + { + // + // Lower 16 bit are unused so set them to zero. + // + usMaskReg[0] = 0; + + // + // Put the 11 bit Mask Identifier into the upper bits of the field + // in the register. + // + usMaskReg[1] = ((pMsgObject->ulMsgIDMask << 2) & + CAN_IF1MSK2_IDMSK_M); + } + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + if((pMsgObject->ulFlags & MSG_OBJ_USE_EXT_FILTER) == + MSG_OBJ_USE_EXT_FILTER) + { + usMaskReg[1] |= CAN_IF1MSK2_MXTD; + } + + // + // The caller wants to filter on the message direction field. + // + if((pMsgObject->ulFlags & MSG_OBJ_USE_DIR_FILTER) == + MSG_OBJ_USE_DIR_FILTER) + { + usMaskReg[1] |= CAN_IF1MSK2_MDIR; + } + + if(pMsgObject->ulFlags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | + MSG_OBJ_USE_EXT_FILTER)) + { + // + // Set the UMASK bit to enable using the mask register. + // + usMsgCtrl |= CAN_IF1MCTL_UMASK; + + // + // Set the MASK bit so that this gets trasferred to the Message Object. + // + usCmdMaskReg |= CAN_IF1CMSK_MASK; + } + + // + // Set the Arb bit so that this gets transferred to the Message object. + // + usCmdMaskReg |= CAN_IF1CMSK_ARB; + + // + // Configure the Arbitration registers. + // + if(bUseExtendedID) + { + // + // Set the 29 bit version of the Identifier for this message object. + // + usArbReg[0] |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M; + usArbReg[1] |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M; + + // + // Mark the message as valid and set the extended ID bit. + // + usArbReg[1] |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD; + } + else + { + // + // Set the 11 bit version of the Identifier for this message object. + // The lower 18 bits are set to zero. + // + usArbReg[1] |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M; + + // + // Mark the message as valid. + // + usArbReg[1] |= CAN_IF1ARB2_MSGVAL; + } + + // + // Set the data length since this is set for all transfers. This is also a + // single transfer and not a FIFO transfer so set EOB bit. + // + usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M) | CAN_IF1MCTL_EOB; + + // + // Enable transmit interrupts if they should be enabled. + // + if(pMsgObject->ulFlags & MSG_OBJ_TX_INT_ENABLE) + { + usMsgCtrl |= CAN_IF1MCTL_TXIE; + } + + // + // Enable receive interrupts if they should be enabled. + // + if(pMsgObject->ulFlags & MSG_OBJ_RX_INT_ENABLE) + { + usMsgCtrl |= CAN_IF1MCTL_RXIE; + } + + // + // Write the data out to the CAN Data registers if needed. + // + if(bTransferData) + { + CANDataRegWrite(pMsgObject->pucMsgData, + (unsigned long *)(ulBase + CAN_O_IF1DA1), + pMsgObject->ulMsgLen); + } + + // + // Write out the registers to program the message object. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, usCmdMaskReg); + CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg[0]); + CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg[1]); + CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg[0]); + CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg[1]); + CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl); + + // + // Transfer the message object to the message object specifiec by ulObjID. + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); + + return; +} + +//***************************************************************************** +// +//! Reads a CAN message from one of the message object buffers. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulObjID is the object number to read (1-32). +//! \param pMsgObject points to a structure containing message object fields. +//! \param bClrPendingInt indicates whether an associated interrupt should be +//! cleared. +//! +//! This function is used to read the contents of one of the 32 message objects +//! in the CAN controller, and return it to the caller. The data returned is +//! stored in the fields of the caller-supplied structure pointed to by +//! \e pMsgObject. The data consists of all of the parts of a CAN message, +//! plus some control and status information. +//! +//! Normally this is used to read a message object that has received and stored +//! a CAN message with a certain identifier. However, this could also be used +//! to read the contents of a message object in order to load the fields of the +//! structure in case only part of the structure needs to be changed from a +//! previous setting. +//! +//! When using CANMessageGet, all of the same fields of the structure are +//! populated in the same way as when the CANMessageSet() function is used, +//! with the following exceptions: +//! +//! \e pMsgObject->ulFlags: +//! +//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it +//! was read +//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on +//! this message object, and not read by the host before being overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageGet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tBoolean bClrPendingInt) +{ + unsigned short usCmdMaskReg; + unsigned short usMaskReg[2]; + unsigned short usArbReg[2]; + unsigned short usMsgCtrl; + + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulObjID <= 32) && (ulObjID != 0)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + usCmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | + CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | CAN_IF1CMSK_ARB); + + // + // Clear a pending interrupt and new data in a message object. + // + if(bClrPendingInt) + { + usCmdMaskReg |= CAN_IF1CMSK_CLRINTPND; + } + + // + // Set up the request for data from the message object. + // + CANRegWrite(ulBase + CAN_O_IF2CMSK, usCmdMaskReg); + + // + // Transfer the message object to the message object specifiec by ulObjID. + // + CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Read out the IF Registers. + // + usMaskReg[0] = CANRegRead(ulBase + CAN_O_IF2MSK1); + usMaskReg[1] = CANRegRead(ulBase + CAN_O_IF2MSK2); + usArbReg[0] = CANRegRead(ulBase + CAN_O_IF2ARB1); + usArbReg[1] = CANRegRead(ulBase + CAN_O_IF2ARB2); + usMsgCtrl = CANRegRead(ulBase + CAN_O_IF2MCTL); + + pMsgObject->ulFlags = MSG_OBJ_NO_FLAGS; + + // + // Determine if this is a remote frame by checking the TXRQST and DIR bits. + // + if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) && + (usArbReg[1] & CAN_IF1ARB2_DIR)) || + ((usMsgCtrl & CAN_IF1MCTL_TXRQST) && + (!(usArbReg[1] & CAN_IF1ARB2_DIR)))) + { + pMsgObject->ulFlags |= MSG_OBJ_REMOTE_FRAME; + } + + // + // Get the identifier out of the register, the format depends on size of + // the mask. + // + if(usArbReg[1] & CAN_IF1ARB2_XTD) + { + // + // Set the 29 bit version of the Identifier for this message object. + // + pMsgObject->ulMsgID = ((usArbReg[1] & CAN_IF1ARB2_ID_M) << 16) | + usArbReg[0]; + + pMsgObject->ulFlags |= MSG_OBJ_EXTENDED_ID; + } + else + { + // + // The Identifier is an 11 bit value. + // + pMsgObject->ulMsgID = (usArbReg[1] & CAN_IF1ARB2_ID_M) >> 2; + } + + // + // Indicate that we lost some data. + // + if(usMsgCtrl & CAN_IF1MCTL_MSGLST) + { + pMsgObject->ulFlags |= MSG_OBJ_DATA_LOST; + } + + // + // Set the flag to indicate if ID masking was used. + // + if(usMsgCtrl & CAN_IF1MCTL_UMASK) + { + if(usArbReg[1] & CAN_IF1ARB2_XTD) + { + // + // The Identifier Mask is assumed to also be a 29 bit value. + // + pMsgObject->ulMsgIDMask = + ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg[0]; + // + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + // + if((pMsgObject->ulMsgIDMask != 0x1fffffff) || + ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER; + } + } + else + { + // + // The Identifier Mask is assumed to also be an 11 bit value. + // + pMsgObject->ulMsgIDMask = ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) >> + 2); + + // + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + // + if((pMsgObject->ulMsgIDMask != 0x7ff) || + ((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_ID_FILTER; + } + } + + // + // Indicate if the extended bit was used in filtering. + // + if(usMaskReg[1] & CAN_IF1MSK2_MXTD) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_EXT_FILTER; + } + + // + // Indicate if direction filtering was enabled. + // + if(usMaskReg[1] & CAN_IF1MSK2_MDIR) + { + pMsgObject->ulFlags |= MSG_OBJ_USE_DIR_FILTER; + } + } + + // + // Set the interupt flags. + // + if(usMsgCtrl & CAN_IF1MCTL_TXIE) + { + pMsgObject->ulFlags |= MSG_OBJ_TX_INT_ENABLE; + } + if(usMsgCtrl & CAN_IF1MCTL_RXIE) + { + pMsgObject->ulFlags |= MSG_OBJ_RX_INT_ENABLE; + } + + // + // See if there is new data available. + // + if(usMsgCtrl & CAN_IF1MCTL_NEWDAT) + { + // + // Get the amount of data needed to be read. + // + pMsgObject->ulMsgLen = (usMsgCtrl & CAN_IF1MCTL_DLC_M); + + // + // Don't read any data for a remote frame, there is nothing valid in + // that buffer anyway. + // + if((pMsgObject->ulFlags & MSG_OBJ_REMOTE_FRAME) == 0) + { + // + // Read out the data from the CAN registers. + // + CANDataRegRead(pMsgObject->pucMsgData, + (unsigned long *)(ulBase + CAN_O_IF2DA1), + pMsgObject->ulMsgLen); + } + + // + // Now clear out the new data flag. + // + CANRegWrite(ulBase + CAN_O_IF2CMSK, CAN_IF1CMSK_NEWDAT); + + // + // Transfer the message object to the message object specifiec by + // ulObjID. + // + CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Indicate that there is new data in this message. + // + pMsgObject->ulFlags |= MSG_OBJ_NEW_DATA; + } + else + { + // + // Along with the MSG_OBJ_NEW_DATA not being set the amount of data + // needs to be set to zero if none was available. + // + pMsgObject->ulMsgLen = 0; + } +} + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param ulBase is the base address of the CAN controller. +//! \param ulObjID is the message object number to disable (1-32). +//! +//! This function frees the specified message object from use. Once a message +//! object has been ``cleared,'' it will no longer automatically send or +//! receive messages, or generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageClear(unsigned long ulBase, unsigned long ulObjID) +{ + // + // Check the arguments. + // + ASSERT(CANBaseValid(ulBase)); + ASSERT((ulObjID >= 1) && (ulObjID <= 32)); + + // + // Wait for busy bit to clear + // + while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid. + // + CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB); + CANRegWrite(ulBase + CAN_O_IF1ARB1, 0); + CANRegWrite(ulBase + CAN_O_IF1ARB2, 0); + + // + // Initiate programming the message object + // + CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/can.h b/bsp/lm3s/driverlib/can.h new file mode 100644 index 0000000000..51df810346 --- /dev/null +++ b/bsp/lm3s/driverlib/can.h @@ -0,0 +1,458 @@ +//***************************************************************************** +// +// can.h - Defines and Macros for the CAN controller. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CAN_H__ +#define __CAN_H__ + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** + +//***************************************************************************** +// +//! These are the flags used by the tCANMsgObject variable when calling the +//! CANMessageSet() and CANMessageGet() functions. +// +//***************************************************************************** +typedef enum +{ + // + //! This indicates that transmit interrupts should be enabled, or are + //! enabled. + // + MSG_OBJ_TX_INT_ENABLE = 0x00000001, + + // + //! This indicates that receive interrupts should be enabled, or are + //! enabled. + // + MSG_OBJ_RX_INT_ENABLE = 0x00000002, + + // + //! This indicates that a message object will use or is using an extended + //! identifier. + // + MSG_OBJ_EXTENDED_ID = 0x00000004, + + // + //! This indicates that a message object will use or is using filtering + //! based on the object's message identifier. + // + MSG_OBJ_USE_ID_FILTER = 0x00000008, + + // + //! This indicates that new data was available in the message object. + // + MSG_OBJ_NEW_DATA = 0x00000080, + + // + //! This indicates that data was lost since this message object was last + //! read. + // + MSG_OBJ_DATA_LOST = 0x00000100, + + // + //! This indicates that a message object will use or is using filtering + //! based on the direction of the transfer. If the direction filtering is + //! used, then ID filtering must also be enabled. + // + MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), + + // + //! This indicates that a message object will use or is using message + //! identifier filtering based on the extended identifier. If the extended + //! identifier filtering is used, then ID filtering must also be enabled. + // + MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), + + // + //! This indicates that a message object is a remote frame. + // + MSG_OBJ_REMOTE_FRAME = 0x00000040, + + // + //! This indicates that a message object has no flags set. + // + MSG_OBJ_NO_FLAGS = 0x00000000 +} +tCANObjFlags; + +//***************************************************************************** +// +//! This define is used with the #tCANObjFlags enumerated values to allow +//! checking only status flags and not configuration flags. +// +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +// +//! The structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +// +//***************************************************************************** +typedef struct +{ + // + //! The CAN message identifier used for 11 or 29 bit identifiers. + // + unsigned long ulMsgID; + + // + //! The message identifier mask used when identifier filtering is enabled. + // + unsigned long ulMsgIDMask; + + // + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + // + unsigned long ulFlags; + + // + //! This value is the number of bytes of data in the message object. + // + unsigned long ulMsgLen; + + // + //! This is a pointer to the message object's data. + // + unsigned char *pucMsgData; +} +tCANMsgObject; + +//***************************************************************************** +// +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +// +//***************************************************************************** +typedef struct +{ + // + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + // + unsigned int uSyncPropPhase1Seg; + + // + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + // + unsigned int uPhase2Seg; + + // + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + // + unsigned int uSJW; + + // + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + // + unsigned int uQuantumPrescaler; +} +tCANBitClkParms; + +//***************************************************************************** +// +//! This data type is used to identify the interrupt status register. This is +//! used when calling the CANIntStatus() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the CAN interrupt status information. + // + CAN_INT_STS_CAUSE, + + // + //! Read a message object's interrupt status. + // + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +// +//! This data type is used to identify which of several status registers to +//! read when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the full CAN controller status. + // + CAN_STS_CONTROL, + + // + //! Read the full 32-bit mask of message objects with a transmit request + //! set. + // + CAN_STS_TXREQUEST, + + // + //! Read the full 32-bit mask of message objects with new data available. + // + CAN_STS_NEWDAT, + + // + //! Read the full 32-bit mask of message objects that are enabled. + // + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// +//! These definitions are used to specify interrupt sources to CANIntEnable() +//! and CANIntDisable(). +// +//***************************************************************************** +typedef enum +{ + // + //! This flag is used to allow a CAN controller to generate error + //! interrupts. + // + CAN_INT_ERROR = 0x00000008, + + // + //! This flag is used to allow a CAN controller to generate status + //! interrupts. + // + CAN_INT_STATUS = 0x00000004, + + // + //! This flag is used to allow a CAN controller to generate any CAN + //! interrupts. If this is not set, then no interrupts will be generated + //! by the CAN controller. + // + CAN_INT_MASTER = 0x00000002 +} +tCANIntFlags; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CANMessageSet() API. +// +//***************************************************************************** +typedef enum +{ + // + //! Transmit message object. + // + MSG_OBJ_TYPE_TX, + + // + //! Transmit remote request message object + // + MSG_OBJ_TYPE_TX_REMOTE, + + // + //! Receive message object. + // + MSG_OBJ_TYPE_RX, + + // + //! Receive remote request message object. + // + MSG_OBJ_TYPE_RX_REMOTE, + + // + //! Remote frame receive remote, with auto-transmit message object. + // + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// +//! The following enumeration contains all error or status indicators that can +//! be returned when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! CAN controller has entered a Bus Off state. + // + CAN_STATUS_BUS_OFF = 0x00000080, + + // + //! CAN controller error level has reached warning level. + // + CAN_STATUS_EWARN = 0x00000040, + + // + //! CAN controller error level has reached error passive level. + // + CAN_STATUS_EPASS = 0x00000020, + + // + //! A message was received successfully since the last read of this status. + // + CAN_STATUS_RXOK = 0x00000010, + + // + //! A message was transmitted successfully since the last read of this + //! status. + // + CAN_STATUS_TXOK = 0x00000008, + + // + //! This is the mask for the last error code field. + // + CAN_STATUS_LEC_MSK = 0x00000007, + + // + //! There was no error. + // + CAN_STATUS_LEC_NONE = 0x00000000, + + // + //! A bit stuffing error has occurred. + // + CAN_STATUS_LEC_STUFF = 0x00000001, + + // + //! A formatting error has occurred. + // + CAN_STATUS_LEC_FORM = 0x00000002, + + // + //! An acknowledge error has occurred. + // + CAN_STATUS_LEC_ACK = 0x00000003, + + // + //! The bus remained a bit level of 1 for longer than is allowed. + // + CAN_STATUS_LEC_BIT1 = 0x00000004, + + // + //! The bus remained a bit level of 0 for longer than is allowed. + // + CAN_STATUS_LEC_BIT0 = 0x00000005, + + // + //! A CRC error has occurred. + // + CAN_STATUS_LEC_CRC = 0x00000006, + + // + //! This is the mask for the CAN Last Error Code (LEC). + // + CAN_STATUS_LEC_MASK = 0x00000007 +} +tCANStatusCtrl; + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern unsigned long CANBitRateSet(unsigned long ulBase, + unsigned long ulSourceClock, + unsigned long ulBitRate); +extern void CANDisable(unsigned long ulBase); +extern void CANEnable(unsigned long ulBase); +extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, + unsigned long *pulTxCount); +extern void CANInit(unsigned long ulBase); +extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); +extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern unsigned long CANIntStatus(unsigned long ulBase, + tCANIntStsReg eIntStsReg); +extern void CANIntUnregister(unsigned long ulBase); +extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); +extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); +extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType); +extern tBoolean CANRetryGet(unsigned long ulBase); +extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); +extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); + +//***************************************************************************** +// +// Several CAN APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#define CANSetBitTiming(a, b) CANBitTimingSet(a, b) +#define CANGetBitTiming(a, b) CANBitTimingGet(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // __CAN_H__ diff --git a/bsp/lm3s/driverlib/comp.c b/bsp/lm3s/driverlib/comp.c new file mode 100644 index 0000000000..b7cba55413 --- /dev/null +++ b/bsp/lm3s/driverlib/comp.c @@ -0,0 +1,439 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_comp.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/comp.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function will configure a comparator. The \e ulConfig parameter is +//! the result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! - \b COMP_OUTPUT_NONE is deprecated and behaves the same as +//! \b COMP_OUTPUT_NORMAL. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Configure this comparator. + // + HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulRef is the desired reference voltage. +//! +//! This function will set the internal reference voltage value. The voltage +//! is specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ulBase + COMP_O_ACREFCTL) = ulRef; +} + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +tBoolean +ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT0_OVAL) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This sets the handler to be called when the comparator interrupt occurs. +//! This will enable the interrupt in the interrupt controller; it is the +//! interrupt-handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0 + ulComp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0 + ulComp); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp; +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function will clear the handler to be called when a comparator +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0 + ulComp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0 + ulComp); +} + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp; +} + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the comparator. Either the raw or +//! the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +tBoolean +ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ulBase + COMP_O_ACMIS) >> ulComp) & 1) ? true : false); + } + else + { + return(((HWREG(ulBase + COMP_O_ACRIS) >> ulComp) & 1) ? true : false); + } +} + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! must be done in the interrupt handler to keep it from being called again +//! immediately upon exit. Note that for a level triggered interrupt, the +//! interrupt cannot be cleared until it stops asserting. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Clear the interrupt. + // + HWREG(ulBase + COMP_O_ACMIS) = 1 << ulComp; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/comp.h b/bsp/lm3s/driverlib/comp.h new file mode 100644 index 0000000000..6c6bf8fcc1 --- /dev/null +++ b/bsp/lm3s/driverlib/comp.h @@ -0,0 +1,133 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and combined together with values from the other +// groups via a logical OR. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#ifndef DEPRECATED +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#endif +#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/bsp/lm3s/driverlib/cpu.c b/bsp/lm3s/driverlib/cpu.c new file mode 100644 index 0000000000..fbe243647f --- /dev/null +++ b/bsp/lm3s/driverlib/cpu.c @@ -0,0 +1,189 @@ +//***************************************************************************** +// +// cpu.c - Instruction wrappers for special CPU instructions needed by the +// drivers. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "driverlib/cpu.h" + +//***************************************************************************** +// +// Wrapper function for the CPSID instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +unsigned long __attribute__((naked)) +CPUcpsid(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#endif + +//***************************************************************************** +// +// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +unsigned long __attribute__((naked)) +CPUcpsie(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#endif + +//***************************************************************************** +// +// Wrapper function for the WFI instruction. +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" wfi\n"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + wfi; + bx lr +} +#endif diff --git a/bsp/lm3s/driverlib/cpu.h b/bsp/lm3s/driverlib/cpu.h new file mode 100644 index 0000000000..8939ecd45a --- /dev/null +++ b/bsp/lm3s/driverlib/cpu.h @@ -0,0 +1,60 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern unsigned long CPUcpsid(void); +extern unsigned long CPUcpsie(void); +extern void CPUwfi(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ diff --git a/bsp/lm3s/driverlib/cr_project.xml b/bsp/lm3s/driverlib/cr_project.xml new file mode 100644 index 0000000000..835b3c172f --- /dev/null +++ b/bsp/lm3s/driverlib/cr_project.xml @@ -0,0 +1,66 @@ + + + + + {(Makefile|codered|ewarm|gcc|rvmdk|sourcerygxx)} + {.*\.(ewd|ewp|eww|icf|Opt|sct|Uv2|xml|ld)} + + + inc + + + codered + + + DEBUG + + + NDEBUG + + + __CODE_RED + codered + PART_LM3S101 + + + -O2 + + + -O2 + + + ${workspace_loc:/} + + diff --git a/bsp/lm3s/driverlib/debug.h b/bsp/lm3s/driverlib/debug.h new file mode 100644 index 0000000000..ed8c8aa05e --- /dev/null +++ b/bsp/lm3s/driverlib/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/bsp/lm3s/driverlib/driverlib.Opt b/bsp/lm3s/driverlib/driverlib.Opt new file mode 100644 index 0000000000..6d0a5fa294 --- /dev/null +++ b/bsp/lm3s/driverlib/driverlib.Opt @@ -0,0 +1,59 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (driverlib), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Source),1,0,0 +GRPOPT 2,(Documentation),0,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<.\adc.c> +OPTFFF 1,2,1,0,0,0,0,0,<.\can.c> +OPTFFF 1,3,1,0,0,0,0,0,<.\comp.c> +OPTFFF 1,4,1,0,0,0,0,0,<.\cpu.c> +OPTFFF 1,5,1,0,0,0,0,0,<.\epi.c> +OPTFFF 1,6,1,0,0,0,0,0,<.\ethernet.c> +OPTFFF 1,7,1,0,0,0,0,0,<.\flash.c> +OPTFFF 1,8,1,0,0,0,0,0,<.\gpio.c> +OPTFFF 1,9,1,0,0,0,0,0,<.\hibernate.c> +OPTFFF 1,10,1,0,0,0,0,0,<.\i2c.c> +OPTFFF 1,11,1,0,0,0,0,0,<.\i2s.c> +OPTFFF 1,12,1,0,0,0,0,0,<.\interrupt.c> +OPTFFF 1,13,1,0,0,0,0,0,<.\mpu.c> +OPTFFF 1,14,1,0,0,0,0,0,<.\pwm.c> +OPTFFF 1,15,1,0,0,0,0,0,<.\qei.c> +OPTFFF 1,16,1,0,0,0,0,0,<.\ssi.c> +OPTFFF 1,17,1,0,0,0,0,0,<.\sysctl.c> +OPTFFF 1,18,1,0,0,0,0,0,<.\systick.c> +OPTFFF 1,19,1,0,0,0,0,0,<.\timer.c> +OPTFFF 1,20,1,83886082,0,1124,1143,0,<.\uart.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,182,2,0,0,196,0,0,0 } +OPTFFF 1,21,1,0,0,0,0,0,<.\udma.c> +OPTFFF 1,22,1,0,0,0,0,0,<.\usb.c> +OPTFFF 1,23,1,0,0,0,0,0,<.\watchdog.c> +OPTFFF 2,24,5,0,0,0,0,0,<.\readme.txt> + + +TARGOPT 1, (driverlib) + ADSCLK=6000000 + OPTTT 0,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\rvmdk\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 0 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965) + OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + OPTDF 0x0 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/bsp/lm3s/driverlib/driverlib.Uv2 b/bsp/lm3s/driverlib/driverlib.Uv2 new file mode 100644 index 0000000000..c81ec86ede --- /dev/null +++ b/bsp/lm3s/driverlib/driverlib.Uv2 @@ -0,0 +1,124 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (driverlib), 0x0004 // Tools: 'ARM-ADS' + +Group (Source) +Group (Documentation) + +File 1,1,<.\adc.c> +File 1,1,<.\can.c> +File 1,1,<.\comp.c> +File 1,1,<.\cpu.c> +File 1,1,<.\epi.c> +File 1,1,<.\ethernet.c> +File 1,1,<.\flash.c> +File 1,1,<.\gpio.c> +File 1,1,<.\hibernate.c> +File 1,1,<.\i2c.c> +File 1,1,<.\i2s.c> +File 1,1,<.\interrupt.c> +File 1,1,<.\mpu.c> +File 1,1,<.\pwm.c> +File 1,1,<.\qei.c> +File 1,1,<.\ssi.c> +File 1,1,<.\sysctl.c> +File 1,1,<.\systick.c> +File 1,1,<.\timer.c> +File 1,1,<.\uart.c> +File 1,1,<.\udma.c> +File 1,1,<.\usb.c> +File 1,1,<.\watchdog.c> +File 2,5,<.\readme.txt> + + +Options 1,0,0 // Target 'driverlib' + Device (LM3S6965) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) + DevID (4337) + Rgf (LM3Sxxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\rvmdk\) + OutName (driverlib) + GenApp=0 + GenLib=1 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\rvmdk\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } + OCMADSIROM { 1,0,0,0,0,0,0,4,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 12,34,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (rvmdk) + ADSCUDEF () + ADSCINCD (..;) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC () + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965) + OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2CM3.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/bsp/lm3s/driverlib/driverlib.ewp b/bsp/lm3s/driverlib/driverlib.ewp new file mode 100644 index 0000000000..fbce106a60 --- /dev/null +++ b/bsp/lm3s/driverlib/driverlib.ewp @@ -0,0 +1,839 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Source + + $PROJ_DIR$\adc.c + + + $PROJ_DIR$\can.c + + + $PROJ_DIR$\comp.c + + + $PROJ_DIR$\cpu.c + + + $PROJ_DIR$\epi.c + + + $PROJ_DIR$\ethernet.c + + + $PROJ_DIR$\flash.c + + + $PROJ_DIR$\gpio.c + + + $PROJ_DIR$\hibernate.c + + + $PROJ_DIR$\i2c.c + + + $PROJ_DIR$\i2s.c + + + $PROJ_DIR$\interrupt.c + + + $PROJ_DIR$\mpu.c + + + $PROJ_DIR$\pwm.c + + + $PROJ_DIR$\qei.c + + + $PROJ_DIR$\ssi.c + + + $PROJ_DIR$\sysctl.c + + + $PROJ_DIR$\systick.c + + + $PROJ_DIR$\timer.c + + + $PROJ_DIR$\uart.c + + + $PROJ_DIR$\udma.c + + + $PROJ_DIR$\usb.c + + + $PROJ_DIR$\watchdog.c + + + diff --git a/bsp/lm3s/driverlib/driverlib.sgxx b/bsp/lm3s/driverlib/driverlib.sgxx new file mode 100644 index 0000000000000000000000000000000000000000..2f10fd87cd1d60cd6bb25a4317ad2c8f21ecada8 GIT binary patch literal 3442 zcmZ`+cQD-F9$h7bMU<$~WA)xkqHb8-MhT)Mi(pw+qHKs3ZHbcTJwXyJh-lHGvqU6% zS+aU3dRyT!Z|42-e!utTJLhxn{r+)g?woUH&N0#@BEAj)0ImXVm^LVS(3B5N69535 zS1^hh5LID8;#9=}J05OdK08nKLbsrR`4sZ+TFxfVT zp)@d0s=U_8g27$8^NJ~$Aq6eRdU38ZCGP=y{jVh4YsR7nOTX}&&#I4iv=E}+ss{HP zGMm2Pdc^=qBGP6lyJbE#Ww>uC+;f!U?r%;h+30#Ba%CR4S}y zLoo6fh%awR<+C=GFwUWXSS7Zk-lt~R~)}YVt&x!O$!t#`mQ}*$2wQ=L+rt~xEU?-K4MgP{eaPSxh`!UYwKMvu# za0p!|^(Wm6hY(x=04OdU^28B^`qL$`7Y@0^-(2D~^zCklICb;3-|O5qYa>H;C*NJN zz4cIgVDWq#&)C6+{sWygx5lKv0NvC_yc=isog3Fe(S4gm`6uNQ&rJ>THhhNh*tIs@ zD#nZv(nB)A$PpbPb<*COH@y*3D(;q)>>pyEt5(86-|B`wDAoz^QzL?)?@tY&qlgOS z`B4~#PBim;>L}>u)k4!Ox%5EX+Zp$}19wenP5V%tI(dDD(F@?jaJN-w;yBMro}vLj zi#lv?AW|h-lIptHE6mTlJfvGY<=8@&Jz-QC(4O%1xLRVn$-JPX16`>2(*sf~Moj38 z7VPL1s**$V)9#*@MuaZ+>W#7fB(MpfkaB1x5#qBRrZ9z1XBt-qLA_!HV<<$Eu%WAK zRM}GfWR%446v#Xeky1`AG(X0^RC*QGWo`gwbGRGgefynD)5+o@t+Oa&pD*)o!oLLJ zybwgb!|0yR#dDR0003l{g4q43#)}IjF7Y=tHdtMZ=j33s@2K+tk>gh>Y&%GPrk!A&mzKXb&5A+tCnye*PPUm= z$GtIE^J-`6sI;ZQ?($=tit=#XV%M3W7Drcr>X}}1bh5+!YL*Tf$3Qw^yq3CTEbqM3 z?racK&e`X^Sp7~uhL&IsGT1{y%Tx~-88>K}@zMEJJI$^$o<)dYud;B9FtK>tRfZ>e zM<^+hD*CPn_7`>PnPc6`HX!QBd~`ia$mGrU4u#nPj+?^YrS5j| zO78ZbJEgw)N*K-7(nKXfs7E#c?ph@EgWrX?E}GJ z3-r4G``%+cCor0ho{T=8D1}|BO2%qH0-Gmn#;Z3ajf(O^&x@FU4&-45lGI>u59dty zKdP6vYgF{Z$K1Xk;tS*O`So9K%8kK^N5$JhZ5UMv4pd zgc`L%AI$KRlxNzsc}y9I(E(`*dDX?g)B-?Y&hs2j-g*fgW{^NG&l(L>$;-zNB|< ztj>@m4DF{QF%|3L!=_~1TgXzTDUe4z91GWGa@a9jh+F!h2T>>a(c|b_?c$@D1}|kA zQL>Pk(8ieb;zj6++6Q~<^|8+0Qj6zVy(VpVM7XOK_R)H$iT}-?EF{TjLo_Q1L|u|R zreANSwg@$)d=KucD04@kKP-C1bJ7O8A-bum*=a{F@K}aUM`hP{h2vdBYUOEvMpykW z9MicVcWAeM^OpPm+X+JOe&SLW{CX1G8;1QMSLwRgjFpw=o#BF-(SyVdmbdA*-V7yD z@nM(UlnQu59wL}p6rMsS%<_ie<81jz4mPF`Pt!a2C32hh^#!C!a8`^;LaM%5LE(>c zttA;DP9L6+q374MPalK@k@e&*z;!()5cOCL_*|06-b&!j)503AigB|o=__&3v)$l@ zT&pO9GAuH4GRTn}rgXsga>-fBq86eEK2*|9q1_jtg2kEBw0|+88u#|gG7w5xl1!7^ zYuMJ^*cnZN(Lc}C>;9qkt`OsY`fhhIrKV#vF_&ME6&86`GS zhS%YfOr#K*>g5Vov z8kBrf>R!?P{NxN2w`6EGjV;QPbOFECEZ>}WHDOvl&60ibqJ|*mp0;z1l1R;* zTg^(Dwia0;Fqd58Wkua%z9=1FwrnQ%4BFaitKhYN;w{i=>em4C&f_AT_rq>#$cd>K z!L%5%Z=*yNUv-NsV!np(rCN#xTC(L&Iajl+C8=cOh%ut-Eek9;NDCqIf=Hx%)92VJ zQO~UeS7_2tYfSeim$(Plh{rxw?mWq849B{;-90X8e_DX2^1}7#2lo4UYUkf7AFjY6 zi+XNJ#HD}AEu-$QoDeEq%jO?u@IIEw6~i@Qz3*3bF~Xi%Q}|7#(R9@aq8JjAv741y znt5+2J>pA?q+RHdu*KPtT|DqexlupZcF_$u+7u?dek@}1G(%|?NS)OVpybwqt{UE- z-F0qFr^hoK6?0REhxUl!_-ESY5gkjRJ-n{KXnsznUO}4VJafrwecI~=%vnano68Qv z;+YK7qgy_-YRiDe-D78h>b8%=gvP5N$o7lKGM*-hhGeua+OMckuGc~Po)B~~b%o6?nFWLu}#~IGDtZB`+7WyIP z*gWvi`eq%}RVAIIZ}T}HQ>;Qcr=xbDdk@0Eg)*2Nb#E{dE>tu8K>l>*+q?dP9q$p7 zU$`bk<3@Uo##8jk*Zc_LBVXESx<$qL=6en$HLzkv`g=D_QdFuvY}{6bkJDkG~=& zldkGlW#uRHu5scC>6o%`okh+ziR%dkJ;q8!vk9rgPH8-yF+2bJ)Q0_9;Mics{Ki)4 zxe*+3dVjLU>?bMK_~&g;Ou&%f$`3BTsr{i-BNDiD;e-~_WMepsSD4?_?m~tya`>=N;~gk1XVdQB^1_D#sl{( zM*L;>1C4YE2-%7LU)^B3s38}@@&a#zFL!^Hk1PK!AAbumf3p2En*PbgO?bifUqSVP s@qdKWKN-`mL2-Hd7xRN0nE(I) literal 0 HcmV?d00001 diff --git a/bsp/lm3s/driverlib/epi.c b/bsp/lm3s/driverlib/epi.c new file mode 100644 index 0000000000..61a2c7718c --- /dev/null +++ b/bsp/lm3s/driverlib/epi.c @@ -0,0 +1,1039 @@ +//***************************************************************************** +// +// epi.c - Driver for the EPI module. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#include "inc/hw_epi.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/epi.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! \addtogroup epi_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sets the usage mode of the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! \param ulMode is the usage mode of the EPI module. +//! +//! This functions sets the operating mode of the EPI module. The parameter +//! \e ulMode must be one of the following: +//! +//! - \b EPI_MODE_NONE - non-moded operation +//! - \b EPI_MODE_SDRAM - use with SDRAM device +//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface +//! - \b EPI_MODE_DISABLE - disable the EPI module +//! +//! Selection of any of the above modes will enable the EPI module, except +//! for \b EPI_MODE_DISABLE which should be used to disable the module. +//! +//! \return None. +// +//***************************************************************************** +void +EPIModeSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT((ulMode == EPI_MODE_NONE) || + (ulMode == EPI_MODE_SDRAM) || + (ulMode == EPI_MODE_HB8) || + (ulMode == EPI_MODE_DISABLE)); + + // + // Write the mode word to the register. + // + HWREG(ulBase + EPI_O_CFG) = ulMode; +} + +//***************************************************************************** +// +//! Sets the clock divider for the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! \param ulDivider is the value of the clock divider to be applied to +//! the external interface (0-65535). +//! +//! This functions sets the clock divider that will be used to determine the +//! clock rate of the external interface. The value is the number of high +//! and low ticks of the system clock per external bus clock. A value of 0 +//! means that the system clock is used without any reduction. The system +//! clock will be divided by the value of \e ulDivider multiplied by 2. A +//! value of 1 gives a divider of 2, and value of 2 gives a divider of 4, a +//! value of 3 gives a divider of 6, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +EPIDividerSet(unsigned long ulBase, unsigned long ulDivider) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Write the divider value to the register. + // + HWREG(ulBase + EPI_O_BAUD) = ulDivider; +} + +//***************************************************************************** +// +//! Configures the SDRAM mode of operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the SDRAM interface configuration. +//! \param ulRefresh is the refresh count in core clocks (0-2047). +//! +//! This function is used to configure the SDRAM interface, when the SDRAM +//! mode is chosen with the function EPIModeSet(). The parameter \e ulConfig +//! is the logical OR of several sets of choices: +//! +//! The processor core frequency must be specified with one of the following: +//! +//! - \b EPI_SDRAM_CORE_FREQ_0_15 - core clock is 0 MHz < clk <= 15 MHz +//! - \b EPI_SDRAM_CORE_FREQ_15_30 - core clock is 15 MHz < clk <= 30 MHz +//! - \b EPI_SDRAM_CORE_FREQ_30_50 - core clock is 30 MHz < clk <= 50 MHz +//! - \b EPI_SDRAM_CORE_FREQ_50_100 - core clock is 50 MHz < clk <= 100 MHz +//! +//! The low power mode is specified with one of the following: +//! +//! - \b EPI_SDRAM_LOW_POWER - enter low power, self-refresh state +//! - \b EPI_SDRAM_FULL_POWER - normal operating state +//! +//! The SDRAM device size is specified with one of the following: +//! +//! - \b EPI_SDRAM_SIZE_64MBIT - 64 Mbit device (8 MB) +//! - \b EPI_SDRAM_SIZE_128MBIT - 128 Mbit device (16 MB) +//! - \b EPI_SDRAM_SIZE_256MBIT - 256 Mbit device (32 MB) +//! - \b EPI_SDRAM_SIZE_512MBIT - 512 Mbit device (64 MB) +//! +//! The parameter \e ulRefresh sets the refresh counter in units of core +//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulRefresh) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulRefresh < 2048); + + // + // Fill in the refresh count field of the configuration word. + // + ulConfig &= ~EPI_SDRAMCFG_RFSH_M; + ulConfig |= ulRefresh << EPI_SDRAMCFG_RFSH_S; + + // + // Write the SDRAM configuration register. + // + HWREG(ulBase + EPI_O_SDRAMCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the interface for Host-bus 8 operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the interface configuration. +//! \param ulMaxWait is the maximum number of external clocks to wait +//! if a FIFO ready signal is holding off the transaction. +//! +//! This function is used to configure the interface when used in Host-bus 8 +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ulConfig is the logical OR of any of the following: +//! +//! - one of \b EPI_HB8_MODE_ADMUX, \b EPI_HB8_MODE_ADDEMUX, +//! \b EPI_HB8_MODE_SRAM, or \b EPI_HB8_MODE_FIFO to select the HB8 mode +//! - \b EPI_HB8_USE_TXEMPTY - enable TXEMPTY signal with FIFO +//! - \b EPI_HB8_USE_RXFULL - enable RXFULL signal with FIFO +//! - \b EPI_HB8_WRHIGH - use active high write strobe, otherwise it is +//! active low +//! - \b EPI_HB8_RDHIGH - use active high read strobe, otherwise it is +//! active low +//! - one of \b EPI_HB8_WRWAIT_0, \b EPI_HB8_WRWAIT_1, \b EPI_HB8_WRWAIT_2, +//! or \b EPI_HB8_WRWAIT_3 to select the number of write wait states (default +//! is 0 wait states) +//! - one of \b EPI_HB8_RDWAIT_0, \b EPI_HB8_RDWAIT_1, \b EPI_HB8_RDWAIT_2, +//! or \b EPI_HB8_RDWAIT_3 to select the number of read wait states (default +//! is 0 wait states) +//! +//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a +//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this +//! parameter determines the maximum number of clocks to wait when the +//! transaction is being held off by by the FIFO using one of these ready +//! signals. A value of 0 means to wait forever. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulMaxWait < 256); + + // + // Fill in the max wait field of the configuration word. + // + ulConfig &= ~EPI_HB8CFG_MAXWAIT_M; + ulConfig |= ulMaxWait << EPI_HB8CFG_MAXWAIT_S; + + // + // Write the non-moded configuration register. + // + HWREG(ulBase + EPI_O_HB8CFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the interface for non-moded operation. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the interface configuration. +//! \param ulFrameCount is the frame size in clocks, if the frame signal +//! is used (0-15). +//! \param ulMaxWait is the maximum number of external clocks to wait +//! when the external clock enable is holding off the transaction (0-255). +//! +//! This function is used to configure the interface when used in non-moded +//! operation as chosen with the function EPIModeSet(). The parameter +//! \e ulConfig is the logical OR of any of the following: +//! +//! - \b EPI_NONMODE_CLKPIN - interface clock is output on a pin +//! - \b EPI_NONMODE_CLKSTOP - clock is stopped when there is no transaction, +//! otherwise it is free-running +//! - \b EPI_NONMODE_CLKENA - enable the clock enable input from the device +//! - \b EPI_NONMODE_FRAMEPIN - framing signal is emitted on a pin +//! - \b EPI_NONMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it +//! is a pulse +//! - \b EPI_NONMODE_READWRITE - read and write strobes are emitted on pins +//! - \b EPI_NONMODE_WRITE2CYCLE - a two cycle write is used, otherwise a +//! single-cycle write is used +//! - \b EPI_NONMODE_READ2CYCLE - a two cycle read is used, otherwise a +//! single-cycle read is used +//! - \b EPI_NONMODE_ASIZE_NONE, \b EPI_NONMODE_ASIZE_4, +//! \b EPI_NONMODE_ASIZE_12, or \b EPI_NONMODE_ASIZE_20 to choose no address +//! bus, or and address bus size of 4, 12, or 20 bits +//! - \b EPI_NONMODE_DSIZE_8, \b EPI_NONMODE_DSIZE_16, +//! \b EPI_NONMODE_DSIZE_24, or \b EPI_NONMODE_DSIZE_32 to select a data bus +//! size of 8, 16, 24, or 32 bits +//! +//! The parameter \e ulFrameCount is the number of clocks used to form the +//! framing signal, if the framing signal is used. The behavior depends on +//! whether the frame signal is a pulse or a 50/50 duty cycle. This value +//! is not used if the framing signal is not enabled with the option +//! \b EPI_NONMMODE_FRAMEPIN. +//! +//! The parameter \e ulMaxWait is used if the external clock enable is turned +//! on with the \b EPI_NONMODE_CLKENA option is used. In the case that +//! external clock enable is used, this parameter determines the maximum +//! number of clocks to wait when the external clock enable signal is holding +//! off a transaction. A value of 0 means to wait forever. If a non-zero +//! value is used and exceeded, an interrupt will occur and the transaction +//! aborted. +//! +//! \return None. +// +//***************************************************************************** +void +EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulFrameCount, unsigned long ulMaxWait) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulFrameCount < 16); + ASSERT(ulMaxWait < 256); + + // + // Fill in the frame count field of the configuration word. + // + ulConfig &= ~EPI_GPCFG_FRMCNT_M; + ulConfig |= ulFrameCount << EPI_GPCFG_FRMCNT_S; + + // + // Fill in the max wait field of the configuration word. + // + ulConfig &= ~EPI_GPCFG_MAXWAIT_M; + ulConfig |= ulMaxWait << EPI_GPCFG_MAXWAIT_S; + + // + // Write the non-moded configuration register. + // + HWREG(ulBase + EPI_O_GPCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Configures the address map for the external interface. +//! +//! \param ulBase is the EPI module base address. +//! \param ulMap is the address mapping configuration. +//! +//! This function is used to configure the address mapping for the external +//! interface. This determines the base address of the external memory or +//! device within the processor peripheral and/or memory space. +//! +//! The parameter \e ulMap is the logical OR of the following: +//! +//! - \b EPI_ADDR_PER_SIZE_256B, \b EPI_ADDR_PER_SIZE_64KB, +//! \b EPI_ADDR_PER_SIZE_16MB, or \b EPI_ADDR_PER_SIZE_512MB to choose a +//! peripheral address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes +//! - \b EPI_ADDR_PER_BASE_NONE, \b EPI_ADDR_PER_BASE_A, or +//! \b EPI_ADDR_PER_BASE_C to choose the base address of the peripheral +//! space as none, 0xA0000000, or 0xC0000000 +//! - \b EPI_ADDR_RAM_SIZE_256B, \b EPI_ADDR_RAM_SIZE_64KB, +//! \b EPI_ADDR_RAM_SIZE_16MB, or \b EPI_ADDR_RAM_SIZE_512MB to choose a +//! RAM address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes +//! - \b EPI_ADDR_RAM_BASE_NONE, \b EPI_ADDR_RAM_BASE_6, or +//! \b EPI_ADDR_RAM_BASE_8 to choose the base address of the RAM space +//! as none, 0x60000000, or 0x80000000 +//! +//! \return None. +// +//***************************************************************************** +void +EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulMap < 0x100); + + // + // Set the value of the address mapping register. + // + HWREG(ulBase + EPI_O_ADDRMAP) = ulMap; +} + +//***************************************************************************** +// +//! Configures a non-blocking read transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! \param ulDataSize is the size of the data items to read. +//! \param ulAddress is the starting address to read. +//! +//! This function is used to configure a non-blocking read channel for a +//! transaction. Two channels are available which can be used in a ping-pong +//! method for continuous reading. It is not necessary to use both channels +//! to perform a non-blocking read. +//! +//! The parameter \e ulDataSize is one of \b EPI_NBCONFIG_SIZE_8, +//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit, +//! or 32-bit sized data transfers. +//! +//! The parameter \e ulAddress is the starting address for the read, relative +//! to the external device. The start of the device is address 0. +//! +//! Once configured, the non-blocking read is started by calling +//! EPINonBlockingReadStart(). If the addresses to be read from the device +//! are in a sequence, it is not necessary to call this function multiple +//! times. Until it is changed, the EPI module will remember the last address +//! that was used for a non-blocking read (per channel). +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDataSize, unsigned long ulAddress) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + ASSERT(ulDataSize < 4); + ASSERT(ulAddress < 0x20000000); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RSIZE1 - EPI_O_RSIZE0); + + // + // Write the data size register for the channel. + // + HWREG(ulBase + EPI_O_RSIZE0 + ulOffset) = ulDataSize; + + // + // Write the starting address register for the channel. + // + HWREG(ulBase + EPI_O_RADDR0 + ulOffset) = ulAddress; +} + +//***************************************************************************** +// +//! Starts a non-blocking read transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! \param ulCount is the number of items to read (1-4095). +//! +//! This function starts a non-blocking read that was previously configured +//! with the function EPINonBlockingReadConfigure(). Once this function is +//! called, the EPI module will begin reading data from the external device +//! into the read FIFO. The EPI will stop reading when the FIFO fills up +//! and resume reading when the application drains the FIFO, until the +//! total specified count of data items has been read. +//! +//! Once a read transaction is completed and the FIFO drained, another +//! transaction can be started from the next address by calling this +//! function again. +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulCount) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + ASSERT(ulCount < 4096); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Write to the read count register. + // + HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = ulCount; +} + +//***************************************************************************** +// +//! Stops a non-blocking read transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! +//! This function cancels a non-blocking read transaction that is already +//! in progress. +//! +//! \return None. +// +//***************************************************************************** +void +EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Write a 0 to the read count register, which will cancel the transaction. + // + HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0; +} + +//***************************************************************************** +// +//! Get the count remaining for a non-blocking transaction. +//! +//! \param ulBase is the EPI module base address. +//! \param ulChannel is the read channel (0 or 1). +//! +//! This function gets the remaining count of items for a non-blocking read +//! transaction. +//! +//! \return The number of items remaining in the non-blocking read transaction. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadCount(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulChannel < 2); + + // + // Compute the offset needed to select the correct channel regs. + // + ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); + + // + // Read the count remaining and return the value to the caller. + // + return(HWREG(ulBase + EPI_O_RPSTD0 + ulOffset)); +} + +//***************************************************************************** +// +//! Get the count of items available in the read FIFO. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function gets the number of items that are available to read in +//! the read FIFO. The read FIFO is filled by a non-blocking read transaction +//! which is configured by the functions EPINonBlockingReadConfigure() and +//! EPINonBlockingReadStart(). +//! +//! \return The number of items available to read in the read FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Read the FIFO count and return it to the caller. + // + return(HWREG(ulBase + EPI_O_RFIFOCNT)); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 32-bit data items. +//! +//! \param ulBase is the EPI module base address. +//! \param ulCount is the maximum count of items to read. +//! \param pulBuf is the caller supplied buffer where the read data should +//! be stored. +//! +//! This function reads 32-bit data items from the read FIFO and stores +//! the values in a caller supplied buffer. The function will read and store +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ulCount. The actual +//! count of items will be returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount, + unsigned long *pulBuf) +{ + unsigned long ulCountRead = 0; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulCount < 4096); + ASSERT(pulBuf); + + // + // Read from the FIFO while there are any items to read, and + // the callers specified count is not exceeded. + // + while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pulBuf = HWREG(ulBase + EPI_O_READFIFO); + + // + // Update the caller's buffer pointer and the count of items read. + // + pulBuf++; + ulCountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ulCountRead); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 16-bit data items. +//! +//! \param ulBase is the EPI module base address. +//! \param ulCount is the maximum count of items to read. +//! \param pusBuf is the caller supplied buffer where the read data should +//! be stored. +//! +//! This function reads 16-bit data items from the read FIFO and stores +//! the values in a caller supplied buffer. The function will read and store +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ulCount. The actual +//! count of items will be returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount, + unsigned short *pusBuf) +{ + unsigned long ulCountRead = 0; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulCount < 4096); + ASSERT(pusBuf); + + // + // Read from the FIFO while there are any items to read, and + // the callers specified count is not exceeded. + // + while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO); + + // + // Update the caller's buffer pointer and the count of items read. + // + pusBuf++; + ulCountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ulCountRead); +} + +//***************************************************************************** +// +//! Read available data from the read FIFO, as 8-bit data items. +//! +//! \param ulBase is the EPI module base address. +//! \param ulCount is the maximum count of items to read. +//! \param pucBuf is the caller supplied buffer where the read data should +//! be stored. +//! +//! This function reads 8-bit data items from the read FIFO and stores +//! the values in a caller supplied buffer. The function will read and store +//! data from the FIFO until there is no more data in the FIFO or the maximum +//! count is reached as specified in the parameter \e ulCount. The actual +//! count of items will be returned. +//! +//! \return The number of items read from the FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount, + unsigned char *pucBuf) +{ + unsigned long ulCountRead = 0; + + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulCount < 4096); + ASSERT(pucBuf); + + // + // Read from the FIFO while there are any items to read, and + // the callers specified count is not exceeded. + // + while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--) + { + // + // Read from the FIFO and store in the caller supplied buffer. + // + *pucBuf = (unsigned char)HWREG(ulBase + EPI_O_READFIFO); + + // + // Update the caller's buffer pointer and the count of items read. + // + pucBuf++; + ulCountRead++; + } + + // + // Return the count of items read to the caller. + // + return(ulCountRead); +} + +//***************************************************************************** +// +//! Configures the read FIFO. +//! +//! \param ulBase is the EPI module base address. +//! \param ulConfig is the FIFO configuration. +//! +//! This function configures the FIFO trigger levels and error +//! generation. The parameter \e ulConfig is the logical OR of the +//! following: +//! +//! - \b EPI_FIFO_CONFIG_WTFULLERR - enables an error interrupt when a write is +//! attempted and the write FIFO is full +//! - \b EPI_FIFO_CONFIG_RSTALLERR - enables an error interrupt when a read is +//! stalled due to an interleaved write or other reason +//! - \b EPI_FIFO_CONFIG_TX_EMPTY, \b EPI_FIFO_CONFIG_TX_1_4, +//! \b EPI_FIFO_CONFIG_TX_1_2, or \b EPI_FIFO_CONFIG_TX_3_4 to set the +//! TX FIFO trigger level to empty, 1/4, 1/2, or 3/4 level +//! - \b EPI_FIFO_CONFIG_RX_1_8, \b EPI_FIFO_CONFIG_RX_1_4, +//! \b EPI_FIFO_CONFIG_RX_1_2, \b EPI_FIFO_CONFIG_RX_3_4, +//! \b EPI_FIFO_CONFIG_RX_7_8, or \b EPI_FIFO_CONFIG_RX_FULL to set the +//! RX FIFO trigger level to 1/8, 1/4, 1/2, 3/4, 7/8 or full level +//! +//! \return None. +// +//***************************************************************************** +void +EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulConfig == (ulConfig & 0x00030077)); + + // + // Load the configuration into the FIFO config reg. + // + HWREG(ulBase + EPI_O_FIFOLVL) = ulConfig; +} + +//***************************************************************************** +// +//! Reads the number of empty slots in the write transaction FIFO. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function returns the number of slots available in the transaction +//! FIFO. It can be used in a polling method to avoid attempting a write +//! that would stall. +//! +//! \return The number of empty slots in the transaction FIFO. +// +//***************************************************************************** +unsigned long +EPINonBlockingWriteCount(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Read the FIFO count and return it to the caller. + // + return(HWREG(ulBase + EPI_O_WFIFOCNT)); +} + +//***************************************************************************** +// +//! Enables EPI interrupt sources. +//! +//! \param ulBase is the EPI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the specified EPI sources to generate interrupts. +//! The \e ulIntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b EPI_INT_TXREQ - transmit FIFO is below the trigger level +//! - \b EPI_INT_RXREQ - read FIFO is above the trigger level +//! - \b EPI_INT_ERR - an error condition occurred +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulIntFlags < 16); + + // + // Write the interrupt flags mask to the mask register. + // + HWREG(ulBase + EPI_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables EPI interrupt sources. +//! +//! \param ulBase is the EPI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the specified EPI sources for interrupt +//! generation. The \e ulIntFlags parameter can be the logical OR +//! of any of the following values: \b EPI_INT_RXREQ, \b EPI_INT_TXREQ, or +//! \b I2S_INT_ERR. +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulIntFlags < 16); + + // + // Write the interrupt flags mask to the mask register. + // + HWREG(ulBase + EPI_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the EPI interrupt status. +//! +//! \param ulBase is the EPI module base address. +//! \param bMasked is set \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the EPI interrupt status. It can return either +//! the raw or masked interrupt status. +//! +//! \return Returns the masked or raw EPI interrupt status, as a bit field +//! of any of the following values: \b EPI_INT_TXREQ, \b EPI_INT_RXREQ, +//! or \b EPI_INT_ERR +// +//***************************************************************************** +unsigned long +EPIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + EPI_O_MIS)); + } + else + { + return(HWREG(ulBase + EPI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Gets the EPI error interrupt status. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function returns the error status of the EPI. If the return value of +//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this +//! function can be used to determine the cause of the error. +//! +//! This function returns a bit mask of error flags, which can be the logical +//! OR of any of the following: +//! +//! - \b EPI_INT_ERR_WTFULL - occurs when a write stalled when the transaction +//! FIFO was full +//! - \b EPI_INT_ERR_RSTALL - occurs when a read stalled +//! - \b EPI_INT_ERR_TIMEOUT - occurs when the external clock enable held +//! off a transaction longer than the configured maximum wait time +//! +//! \return Returns the interrupt error flags as the logical OR of any of +//! the following: \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or +//! \b EPI_INT_ERR_TIMEOUT. +// +//***************************************************************************** +unsigned long +EPIIntErrorStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Read the error status and return to caller. + // + return(HWREG(ulBase + EPI_O_EISC)); +} + +//***************************************************************************** +// +//! Clears pending EPI error sources. +//! +//! \param ulBase is the EPI module base address. +//! \param ulErrFlags is a bit mask of the error sources to be cleared. +//! +//! This function clears the specified pending EPI errors. The \e ulErrFlags +//! parameter can be the logical OR of any of the following values: +//! \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or \b EPI_INT_ERR_TIMEOUT. +//! +//! \return Returns None. +// +//***************************************************************************** +void +EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(ulErrFlags < 16); + + // + // Write the error flags to the register to clear the pending errors. + // + HWREG(ulBase + EPI_O_EISC) = ulErrFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This sets and enables the handler to be called when the EPI module +//! generates an interrupt. Specific EPI interrupts must still be enabled +//! with the EPIIntEnable() function. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_EPI0, pfnHandler); + + // + // Enable the EPI interface interrupt. + // + IntEnable(INT_EPI0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the EPI module. +//! +//! \param ulBase is the EPI module base address. +//! +//! This function will disable and clear the handler to be called when the +//! EPI interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EPIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == EPI0_BASE); + + // + // Disable the EPI interface interrupt. + // + IntDisable(INT_EPI0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_EPI0); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/epi.h b/bsp/lm3s/driverlib/epi.h new file mode 100644 index 0000000000..4cd478e39f --- /dev/null +++ b/bsp/lm3s/driverlib/epi.h @@ -0,0 +1,229 @@ +//***************************************************************************** +// +// epi.h - Prototypes and macros for the EPI module. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __EPI_H__ +#define __EPI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EPIModeSet() +// +//***************************************************************************** +#define EPI_MODE_NONE 0x00000010 +#define EPI_MODE_SDRAM 0x00000011 +#define EPI_MODE_HB8 0x00000012 +#define EPI_MODE_DISABLE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigSDRAMSet() +// +//***************************************************************************** +#define EPI_SDRAM_CORE_FREQ_0_15 0x00000000 +#define EPI_SDRAM_CORE_FREQ_15_30 0x40000000 +#define EPI_SDRAM_CORE_FREQ_30_50 0x80000000 +#define EPI_SDRAM_CORE_FREQ_50_100 0xC0000000 +#define EPI_SDRAM_LOW_POWER 0x00000200 +#define EPI_SDRAM_FULL_POWER 0x00000000 +#define EPI_SDRAM_SIZE_64MBIT 0x00000000 +#define EPI_SDRAM_SIZE_128MBIT 0x00000001 +#define EPI_SDRAM_SIZE_256MBIT 0x00000002 +#define EPI_SDRAM_SIZE_512MBIT 0x00000003 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigNoModeSet() +// +//***************************************************************************** +#define EPI_NONMODE_CLKPIN 0x80000000 +#define EPI_NONMODE_CLKSTOP 0x40000000 +#define EPI_NONMODE_CLKENA 0x10000000 +#define EPI_NONMODE_FRAMEPIN 0x08000000 +#define EPI_NONMODE_FRAME50 0x04000000 +#define EPI_NONMODE_READWRITE 0x00200000 +#define EPI_NONMODE_WRITE2CYCLE 0x00080000 +#define EPI_NONMODE_READ2CYCLE 0x00040000 +#define EPI_NONMODE_ASIZE_NONE 0x00000000 +#define EPI_NONMODE_ASIZE_4 0x00000010 +#define EPI_NONMODE_ASIZE_12 0x00000020 +#define EPI_NONMODE_ASIZE_20 0x00000030 +#define EPI_NONMODE_DSIZE_8 0x00000000 +#define EPI_NONMODE_DSIZE_16 0x00000001 +#define EPI_NONMODE_DSIZE_24 0x00000002 +#define EPI_NONMODE_DSIZE_32 0x00000003 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB8ModeSet() +// +//***************************************************************************** +#define EPI_HB8_USE_TXEMPTY 0x00800000 +#define EPI_HB8_USE_RXFULL 0x00400000 +#define EPI_HB8_WRHIGH 0x00200000 +#define EPI_HB8_RDHIGH 0x00100000 +#define EPI_HB8_WRWAIT_0 0x00000000 +#define EPI_HB8_WRWAIT_1 0x00000040 +#define EPI_HB8_WRWAIT_2 0x00000080 +#define EPI_HB8_WRWAIT_3 0x000000C0 +#define EPI_HB8_RDWAIT_0 0x00000000 +#define EPI_HB8_RDWAIT_1 0x00000010 +#define EPI_HB8_RDWAIT_2 0x00000020 +#define EPI_HB8_RDWAIT_3 0x00000030 +#define EPI_HB8_MODE_ADMUX 0x00000000 +#define EPI_HB8_MODE_ADDEMUX 0x00000001 +#define EPI_HB8_MODE_SRAM 0x00000002 +#define EPI_HB8_MODE_FIFO 0x00000003 + +//***************************************************************************** +// +// Values that can be passed to EPIConfigSDRAMSet() +// +//***************************************************************************** +#define EPI_ADDR_PER_SIZE_256B 0x00000000 +#define EPI_ADDR_PER_SIZE_64KB 0x00000040 +#define EPI_ADDR_PER_SIZE_16MB 0x00000080 +#define EPI_ADDR_PER_SIZE_512MB 0x000000C0 +#define EPI_ADDR_PER_BASE_NONE 0x00000000 +#define EPI_ADDR_PER_BASE_A 0x00000010 +#define EPI_ADDR_PER_BASE_C 0x00000020 +#define EPI_ADDR_RAM_SIZE_256B 0x00000000 +#define EPI_ADDR_RAM_SIZE_64KB 0x00000004 +#define EPI_ADDR_RAM_SIZE_16MB 0x00000008 +#define EPI_ADDR_RAM_SIZE_512MB 0x0000000C +#define EPI_ADDR_RAM_BASE_NONE 0x00000000 +#define EPI_ADDR_RAM_BASE_6 0x00000001 +#define EPI_ADDR_RAM_BASE_8 0x00000002 + +//***************************************************************************** +// +// Values that can be passed to EPINonBlockingReadConfigure() +// +//***************************************************************************** +#define EPI_NBCONFIG_SIZE_8 1 +#define EPI_NBCONFIG_SIZE_16 2 +#define EPI_NBCONFIG_SIZE_32 3 + +//***************************************************************************** +// +// Values that can be passed to EPIFIFOConfig() +// +//***************************************************************************** +#define EPI_FIFO_CONFIG_WTFULLERR 0x00020000 +#define EPI_FIFO_CONFIG_RSTALLERR 0x00010000 +#define EPI_FIFO_CONFIG_TX_EMPTY 0x00000000 +#define EPI_FIFO_CONFIG_TX_1_4 0x00000020 +#define EPI_FIFO_CONFIG_TX_1_2 0x00000030 +#define EPI_FIFO_CONFIG_TX_3_4 0x00000040 +#define EPI_FIFO_CONFIG_RX_1_8 0x00000001 +#define EPI_FIFO_CONFIG_RX_1_4 0x00000002 +#define EPI_FIFO_CONFIG_RX_1_2 0x00000003 +#define EPI_FIFO_CONFIG_RX_3_4 0x00000004 +#define EPI_FIFO_CONFIG_RX_7_8 0x00000005 +#define EPI_FIFO_CONFIG_RX_FULL 0x00000006 + +//***************************************************************************** +// +// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned +// as flags from EPIIntStatus() +// +//***************************************************************************** +#define EPI_INT_TXREQ 0x00000004 +#define EPI_INT_RXREQ 0x00000002 +#define EPI_INT_ERR 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to EPIIntErrorClear(), or returned as flags from +// EPIIntErrorStatus() +// +//***************************************************************************** +#define EPI_INT_ERR_WTFULL 0x00000004 +#define EPI_INT_ERR_RSTALL 0x00000002 +#define EPI_INT_ERR_TIMEOUT 0x00000001 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +void EPIModeSet(unsigned long ulBase, unsigned long ulMode); +void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider); +void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulRefresh); +void EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulFrameCount, unsigned long ulMaxWait); +void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxWait); +void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap); +void EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulDataSize, unsigned long ulAddress); +void EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulCount); +void EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel); +unsigned long EPINonBlockingReadCount(unsigned long ulBase, + unsigned long ulChannel); +unsigned long EPINonBlockingReadAvail(unsigned long ulBase); +unsigned long EPINonBlockingReadGet32(unsigned long ulBase, + unsigned long ulCount, + unsigned long *pulBuf); +unsigned long EPINonBlockingReadGet16(unsigned long ulBase, + unsigned long ulCount, + unsigned short *pusBuf); +unsigned long EPINonBlockingReadGet8(unsigned long ulBase, + unsigned long ulCount, + unsigned char *pucBuf); +void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig); +unsigned long EPINonBlockingWriteCount(unsigned long ulBase); +void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked); +unsigned long EPIIntErrorStatus(unsigned long ulBase); +void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags); +void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +void EPIIntUnregister(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EPI_H__ diff --git a/bsp/lm3s/driverlib/ethernet.c b/bsp/lm3s/driverlib/ethernet.c new file mode 100644 index 0000000000..df65dee309 --- /dev/null +++ b/bsp/lm3s/driverlib/ethernet.c @@ -0,0 +1,1280 @@ +//***************************************************************************** +// +// ethernet.c - Driver for the Integrated Ethernet Controller +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ethernet_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ethernet.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/ethernet.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Initializes the Ethernet controller for operation. +//! +//! \param ulBase is the base address of the controller. +//! \param ulEthClk is the rate of the clock supplied to the Ethernet module. +//! +//! This function will prepare the Ethernet controller for first time use in +//! a given hardware/software configuration. This function should be called +//! before any other Ethernet API functions are called. +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original EthernetInit() API and performs the +//! same actions. A macro is provided in ethernet.h to map the +//! original API to this API. +//! +//! \note If the device configuration is changed (for example, the system clock +//! is reprogrammed to a different speed), then the Ethernet controller must be +//! disabled by calling the EthernetDisable() function and the controller must +//! be reinitialized by calling the EthernetInitExpClk() function again. After +//! the controller has been reinitialized, the controller should be +//! reconfigured using the appropriate Ethernet API calls. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk) +{ + unsigned long ulDiv; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Set the Management Clock Divider register for access to the PHY + // register set (via EthernetPHYRead/Write). + // + // The MDC clock divided down from the system clock using the following + // formula. A maximum of 2.5MHz is allowed for F(mdc). + // + // F(mdc) = F(sys) / (2 * (div + 1)) + // div = (F(sys) / (2 * F(mdc))) - 1 + // div = (F(sys) / 2 / F(mdc)) - 1 + // + // Note: Because we should round up, to ensure we don't violate the + // maximum clock speed, we can simplify this as follows: + // + // div = F(sys) / 2 / F(mdc) + // + // For example, given a system clock of 6.0MHz, and a div value of 1, + // the mdc clock would be programmed as 1.5 MHz. + // + ulDiv = (ulEthClk / 2) / 2500000; + HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M); +} + +//***************************************************************************** +// +//! Sets the configuration of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param ulConfig is the configuration for the controller. +//! +//! After the EthernetInitExpClk() function has been called, this API function +//! can be used to configure the various features of the Ethernet controller. +//! +//! The Ethernet controller provides three control registers that are used +//! to configure the controller's operation. The transmit control register +//! provides settings to enable full duplex operation, to auto-generate the +//! frame check sequence, and to pad the transmit packets to the minimum +//! length as required by the IEEE standard. The receive control register +//! provides settings to enable reception of packets with bad frame check +//! sequence values and to enable multi-cast or promiscuous modes. The +//! timestamp control register provides settings that enable support logic in +//! the controller that allow the use of the General Purpose Timer 3 to capture +//! timestamps for the transmitted and received packets. +//! +//! The \e ulConfig parameter is the logical OR of the following values: +//! +//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer +//! inputs +//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC +//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets) +//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets +//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode +//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation +//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size +//! +//! These bit-mapped values are programmed into the transmit, receive, and/or +//! timestamp control register. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | + ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS | + ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN | + ETH_CFG_TS_TSEN)) == 0); + + // + // Setup the Transmit Control Register. + // + ulTemp = HWREG(ulBase + MAC_O_TCTL); + ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN); + ulTemp |= ulConfig & 0x0FF; + HWREG(ulBase + MAC_O_TCTL) = ulTemp; + + // + // Setup the Receive Control Register. + // + ulTemp = HWREG(ulBase + MAC_O_RCTL); + ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL); + ulTemp |= (ulConfig >> 8) & 0x0FF; + HWREG(ulBase + MAC_O_RCTL) = ulTemp; + + // + // Setup the Time Stamp Configuration register. + // + ulTemp = HWREG(ulBase + MAC_O_TS); + ulTemp &= ~(MAC_TS_TSEN); + ulTemp |= (ulConfig >> 16) & 0x0FF; + HWREG(ulBase + MAC_O_TS) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the current configuration of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function will query the control registers of the Ethernet controller +//! and return a bit-mapped configuration value. +//! +//! \sa The description of the EthernetConfigSet() function provides detailed +//! information for the bit-mapped configuration values that will be returned. +//! +//! \return Returns the bit-mapped Ethernet controller configuration value. +// +//***************************************************************************** +unsigned long +EthernetConfigGet(unsigned long ulBase) +{ + unsigned long ulConfig; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Read and return the Ethernet controller configuration parameters, + // properly shifted into the appropriate bit field positions. + // + ulConfig = HWREG(ulBase + MAC_O_TS) << 16; + ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8; + ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN); + return(ulConfig); +} + +//***************************************************************************** +// +//! Sets the MAC address of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucMACAddr is the pointer to the array of MAC-48 address octets. +//! +//! This function will program the IEEE-defined MAC-48 address specified in +//! \e pucMACAddr into the Ethernet controller. This address is used by the +//! Ethernet controller for hardware-level filtering of incoming Ethernet +//! packets (when promiscuous mode is not enabled). +//! +//! The MAC-48 address is defined as 6 octets, illustrated by the following +//! example address. The numbers are shown in hexadecimal format. +//! +//! AC-DE-48-00-00-80 +//! +//! In this representation, the first three octets (AC-DE-48) are the +//! Organizationally Unique Identifier (OUI). This is a number assigned by +//! the IEEE to an organization that requests a block of MAC addresses. The +//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner +//! to uniquely identify a piece of hardware within that organization that is +//! to be connected to the Ethernet. +//! +//! In this representation, the octets are transmitted from left to right, +//! with the ``AC'' octet being transmitted first and the ``80'' octet being +//! transmitted last. Within an octet, the bits are transmitted LSB to MSB. +//! For this address, the first bit to be transmitted would be ``0'', the LSB +//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of +//! ``80''. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr) +{ + unsigned long ulTemp; + unsigned char *pucTemp = (unsigned char *)&ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucMACAddr != 0); + + // + // Program the MAC Address into the device. The first four bytes of the + // MAC Address are placed into the IA0 register. The remaining two bytes + // of the MAC address are placed into the IA1 register. + // + pucTemp[0] = pucMACAddr[0]; + pucTemp[1] = pucMACAddr[1]; + pucTemp[2] = pucMACAddr[2]; + pucTemp[3] = pucMACAddr[3]; + HWREG(ulBase + MAC_O_IA0) = ulTemp; + ulTemp = 0; + pucTemp[0] = pucMACAddr[4]; + pucTemp[1] = pucMACAddr[5]; + HWREG(ulBase + MAC_O_IA1) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the MAC address of the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucMACAddr is the pointer to the location in which to store the +//! array of MAC-48 address octets. +//! +//! This function will read the currently programmed MAC address into the +//! \e pucMACAddr buffer. +//! +//! \sa Refer to EthernetMACAddrSet() API description for more details about +//! the MAC address format. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr) +{ + unsigned long ulTemp; + unsigned char *pucTemp = (unsigned char *)&ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucMACAddr != 0); + + // + // Read the MAC address from the device. The first four bytes of the + // MAC address are read from the IA0 register. The remaining two bytes + // of the MAC addres + // + ulTemp = HWREG(ulBase + MAC_O_IA0); + pucMACAddr[0] = pucTemp[0]; + pucMACAddr[1] = pucTemp[1]; + pucMACAddr[2] = pucTemp[2]; + pucMACAddr[3] = pucTemp[3]; + ulTemp = HWREG(ulBase + MAC_O_IA1); + pucMACAddr[4] = pucTemp[0]; + pucMACAddr[5] = pucTemp[1]; +} + +//***************************************************************************** +// +//! Enables the Ethernet controller for normal operation. +//! +//! \param ulBase is the base address of the controller. +//! +//! Once the Ethernet controller has been configured using the +//! EthernetConfigSet() function and the MAC address has been programmed using +//! the EthernetMACAddrSet() function, this API function can be called to +//! enable the controller for normal operation. +//! +//! This function will enable the controller's transmitter and receiver, and +//! will reset the receive FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Reset the receive FIFO. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; + + // + // Enable the Ethernet receiver. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN; + + // + // Enable Ethernet transmitter. + // + HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN; + + // + // Reset the receive FIFO again, after the receiver has been enabled. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; +} + +//***************************************************************************** +// +//! Disables the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! When terminating operations on the Ethernet interface, this function should +//! be called. This function will disable the transmitter and receiver, and +//! will clear out the receive FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Reset the receive FIFO. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; + + // + // Disable the Ethernet transmitter. + // + HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN); + + // + // Disable the Ethernet receiver. + // + HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN); + + // + // Reset the receive FIFO again, after the receiver has been disabled. + // + HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO; +} + +//***************************************************************************** +// +//! Check for packet available from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! The Ethernet controller provides a register that contains the number of +//! packets available in the receive FIFO. When the last bytes of a packet are +//! successfully received (that is, the frame check sequence bytes), the packet +//! count is incremented. Once the packet has been fully read (including the +//! frame check sequence bytes) from the FIFO, the packet count will be +//! decremented. +//! +//! \return Returns \b true if there are one or more packets available in the +//! receive FIFO, including the current packet being read, and \b false +//! otherwise. +// +//***************************************************************************** +tBoolean +EthernetPacketAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Return the availability of packets. + // + return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false); +} + +//***************************************************************************** +// +//! Checks for packet space available in the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! +//! The Ethernet controller's transmit FIFO is designed to support a single +//! packet at a time. After the packet has been written into the FIFO, the +//! transmit request bit must be set to enable the transmission of the packet. +//! Only after the packet has been transmitted can a new packet be written +//! into the FIFO. This function will simply check to see if a packet is +//! in progress. If so, there is no space available in the transmit FIFO. +//! +//! \return Returns \b true if a space is available in the transmit FIFO, and +//! \b false otherwise. +// +//***************************************************************************** +tBoolean +EthernetSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Return the availability of space. + // + return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true); +} + +//***************************************************************************** +// +//! \internal +//! +//! Internal function for reading a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is the maximum number of bytes to be read into the buffer. +//! +//! Based on the following table of how the receive frame is stored in the +//! receive FIFO, this function will extract a packet from the FIFO and store +//! it in the packet buffer that was passed in. +//! +//! Format of the data in the RX FIFO is as follows: +//! +//! \verbatim +//! +---------+----------+----------+----------+----------+ +//! | | 31:24 | 23:16 | 15:8 | 7:0 | +//! +---------+----------+----------+----------+----------+ +//! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB | +//! +---------+----------+----------+----------+----------+ +//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 | +//! +---------+----------+----------+----------+----------+ +//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 | +//! +---------+----------+----------+----------+----------+ +//! | ... | | | | | +//! +---------+----------+----------+----------+----------+ +//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 | +//! +---------+----------+----------+----------+----------+ +//! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 | +//! +---------+----------+----------+----------+----------+ +//! \endverbatim +//! +//! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes. +//! Where DA is Destination (MAC) Address. +//! Where SA is Source (MAC) Address. +//! Where FT is Frame Type (or Frame Length for Ethernet). +//! Where DATA is Payload Data for the Ethernet Frame. +//! Where FCS is the Frame Check Sequence. +//! +//! \return Returns the negated packet length \b -n if the packet is too large +//! for \e pucBuf, and returns the packet length \b n otherwise. +// +//***************************************************************************** +static long +EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + unsigned long ulTemp; + long lFrameLen, lTempLen; + long i = 0; + + // + // Read WORD 0 (see format above) from the FIFO, set the receive + // Frame Length and store the first two bytes of the destination + // address in the receive buffer. + // + ulTemp = HWREG(ulBase + MAC_O_DATA); + lFrameLen = (long)(ulTemp & 0xFFFF); + pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff); + pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff); + + // + // Read all but the last WORD into the receive buffer. + // + lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6); + while(i <= (lTempLen - 4)) + { + *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA); + i += 4; + } + + // + // Read the last 1, 2, or 3 BYTES into the buffer + // + if(i < lTempLen) + { + ulTemp = HWREG(ulBase + MAC_O_DATA); + if(i == lTempLen - 3) + { + pucBuf[i++] = ((ulTemp >> 0) & 0xff); + pucBuf[i++] = ((ulTemp >> 8) & 0xff); + pucBuf[i++] = ((ulTemp >> 16) & 0xff); + i += 1; + } + else if(i == lTempLen - 2) + { + pucBuf[i++] = ((ulTemp >> 0) & 0xff); + pucBuf[i++] = ((ulTemp >> 8) & 0xff); + i += 2; + } + else if(i == lTempLen - 1) + { + pucBuf[i++] = ((ulTemp >> 0) & 0xff); + i += 3; + } + } + + // + // Read any remaining WORDS (that did not fit into the buffer). + // + while(i < (lFrameLen - 2)) + { + ulTemp = HWREG(ulBase + MAC_O_DATA); + i += 4; + } + + // + // If frame was larger than the buffer, return the "negative" frame length + // + lFrameLen -= 6; + if(lFrameLen > lBufLen) + { + return(-lFrameLen); + } + + // + // Return the Frame Length + // + return(lFrameLen); +} + +//***************************************************************************** +// +//! Receives a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is the maximum number of bytes to be read into the buffer. +//! +//! This function reads a packet from the receive FIFO of the controller and +//! places it into \e pucBuf. If no packet is available the function will +//! return immediately. Otherwise, the function will read the entire packet +//! from the receive FIFO. If there are more bytes in the packet than will fit +//! into \e pucBuf (as specified by \e lBufLen), the function will return the +//! negated length of the packet and the buffer will contain \e lBufLen bytes +//! of the packet. Otherwise, the function will return the length of the +//! packet that was read and \e pucBuf will contain the entire packet +//! (excluding the frame check sequence bytes). +//! +//! This function replaces the original EthernetPacketNonBlockingGet() API and +//! performs the same actions. A macro is provided in ethernet.h to +//! map the original API to this API. +//! +//! \note This function will return immediately if no packet is available. +//! +//! \return Returns \b 0 if no packet is available, the negated packet length +//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n +//! otherwise. +// +//***************************************************************************** +long +EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Check to see if any packets are available. + // + if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0) + { + return(0); + } + + // + // Read the packet, and return. + // + return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! Waits for a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is the maximum number of bytes to be read into the buffer. +//! +//! This function reads a packet from the receive FIFO of the controller and +//! places it into \e pucBuf. The function will wait until a packet is +//! available in the FIFO. Then the function will read the entire packet +//! from the receive FIFO. If there are more bytes in the packet than will +//! fit into \e pucBuf (as specified by \e lBufLen), the function will return +//! the negated length of the packet and the buffer will contain \e lBufLen +//! bytes of the packet. Otherwise, the function will return the length of +//! the packet that was read and \e pucBuf will contain the entire packet +//! (excluding the frame check sequence bytes). +//! +//! \note This function is blocking and will not return until a packet arrives. +//! +//! \return Returns the negated packet length \b -n if the packet is too large +//! for \e pucBuf, and returns the packet length \b n otherwise. +// +//***************************************************************************** +long +EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Wait for a packet to become available + // + while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0) + { + } + + // + // Read the packet + // + return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! \internal +//! +//! Internal function for sending a packet to the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is number of bytes in the packet to be transmitted. +//! +//! Puts a packet into the transmit FIFO of the controller. +//! +//! Format of the data in the TX FIFO is as follows: +//! +//! \verbatim +//! +---------+----------+----------+----------+----------+ +//! | | 31:24 | 23:16 | 15:8 | 7:0 | +//! +---------+----------+----------+----------+----------+ +//! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB | +//! +---------+----------+----------+----------+----------+ +//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 | +//! +---------+----------+----------+----------+----------+ +//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 | +//! +---------+----------+----------+----------+----------+ +//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 | +//! +---------+----------+----------+----------+----------+ +//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 | +//! +---------+----------+----------+----------+----------+ +//! | ... | | | | | +//! +---------+----------+----------+----------+----------+ +//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 | +//! +---------+----------+----------+----------+----------+ +//! \endverbatim +//! +//! Where PL is Payload Length, (DATA) only +//! Where DA is Destination (MAC) Address +//! Where SA is Source (MAC) Address +//! Where FT is Frame Type (or Frame Length for Ethernet) +//! Where DATA is Payload Data for the Ethernet Frame +//! +//! \return Returns the negated packet length \b -lBufLen if the packet is too +//! large for FIFO, and the packet length \b lBufLen otherwise. +// +//***************************************************************************** +static long +EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + unsigned long ulTemp; + long i = 0; + + // + // If the packet is too large, return the negative packet length as + // an error code. + // + if(lBufLen > (2048 - 2)) + { + return(-lBufLen); + } + + // + // Build and write WORD 0 (see format above) to the transmit FIFO. + // + ulTemp = (unsigned long)(lBufLen - 14); + ulTemp |= (pucBuf[i++] << 16); + ulTemp |= (pucBuf[i++] << 24); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + + // + // Write each subsequent WORD n to the transmit FIFO, except for the last + // WORD (if the word does not contain 4 bytes). + // + while(i <= (lBufLen - 4)) + { + HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i]; + i += 4; + } + + // + // Build the last word of the remaining 1, 2, or 3 bytes, and store + // the WORD into the transmit FIFO. + // + if(i != lBufLen) + { + if(i == (lBufLen - 3)) + { + ulTemp = (pucBuf[i++] << 0); + ulTemp |= (pucBuf[i++] << 8); + ulTemp |= (pucBuf[i++] << 16); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + } + else if(i == (lBufLen - 2)) + { + ulTemp = (pucBuf[i++] << 0); + ulTemp |= (pucBuf[i++] << 8); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + } + else if(i == (lBufLen - 1)) + { + ulTemp = (pucBuf[i++] << 0); + HWREG(ulBase + MAC_O_DATA) = ulTemp; + } + } + + // + // Activate the transmitter + // + HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX; + + // + // Return the Buffer Length transmitted. + // + return(lBufLen); +} + +//***************************************************************************** +// +//! Sends a packet to the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is number of bytes in the packet to be transmitted. +//! +//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf +//! into the transmit FIFO of the controller and then activates the +//! transmitter for this packet. If no space is available in the FIFO, the +//! function will return immediately. If space is available, the +//! function will return once \e lBufLen bytes of the packet have been placed +//! into the FIFO and the transmitter has been started. The function will not +//! wait for the transmission to complete. The function will return the +//! negated \e lBufLen if the length is larger than the space available in +//! the transmit FIFO. +//! +//! This function replaces the original EthernetPacketNonBlockingPut() API and +//! performs the same actions. A macro is provided in ethernet.h to +//! map the original API to this API. +//! +//! \note This function does not block and will return immediately if no space +//! is available for the transmit packet. +//! +//! \return Returns \b 0 if no space is available in the transmit FIFO, the +//! negated packet length \b -lBufLen if the packet is too large for FIFO, and +//! the packet length \b lBufLen otherwise. +// +//***************************************************************************** +long +EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Check if the transmit FIFO is in use and return the appropriate code. + // + if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) + { + return(0); + } + + // + // Send the packet and return. + // + return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! Waits to send a packet from the Ethernet controller. +//! +//! \param ulBase is the base address of the controller. +//! \param pucBuf is the pointer to the packet buffer. +//! \param lBufLen is number of bytes in the packet to be transmitted. +//! +//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf +//! into the transmit FIFO of the controller and then activates the transmitter +//! for this packet. This function will wait until the transmit FIFO is empty. +//! Once space is available, the function will return once \e lBufLen bytes of +//! the packet have been placed into the FIFO and the transmitter has been +//! started. The function will not wait for the transmission to complete. The +//! function will return the negated \e lBufLen if the length is larger than +//! the space available in the transmit FIFO. +//! +//! \note This function blocks and will wait until space is available for the +//! transmit packet before returning. +//! +//! \return Returns the negated packet length \b -lBufLen if the packet is too +//! large for FIFO, and the packet length \b lBufLen otherwise. +// +//***************************************************************************** +long +EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pucBuf != 0); + ASSERT(lBufLen > 0); + + // + // Wait for current packet (if any) to complete. + // + while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) + { + } + + // + // Send the packet and return. + // + return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for an Ethernet interrupt. +//! +//! \param ulBase is the base address of the controller. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled Ethernet interrupts occur. +//! +//! This function sets the handler to be called when the Ethernet interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It +//! is the interrupt handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(pfnHandler != 0); + + // + // Register the interrupt handler. + // + IntRegister(INT_ETH, pfnHandler); + + // + // Enable the Ethernet interrupt. + // + IntEnable(INT_ETH); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for an Ethernet interrupt. +//! +//! \param ulBase is the base address of the controller. +//! +//! This function unregisters the interrupt handler. This will disable the +//! global interrupt in the interrupt controller so that the interrupt handler +//! no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_ETH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_ETH); +} + +//***************************************************************************** +// +//! Enables individual Ethernet interrupt sources. +//! +//! \param ulBase is the base address of the controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated Ethernet interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated +//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17, +//! must be read to determine which PHY interrupt has occurred. This register +//! can be read using the EthernetPHYRead() API function. +//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the +//! management interface has completed successfully. +//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred +//! during reception of a frame. This error can indicate a length mismatch, a +//! CRC failure, or an error indication from the PHY. +//! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received +//! that exceeds the available space in the RX FIFO. +//! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX +//! FIFO has been successfully transmitted. +//! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred +//! during the transmission of a packet. This error can be either a retry +//! failure during the back-off process, or an invalid length stored in the TX +//! FIFO. +//! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are +//! available in the RX FIFO for processing. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX))); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + MAC_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual Ethernet interrupt sources. +//! +//! \param ulBase is the base address of the controller. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated Ethernet interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to EthernetIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX))); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current Ethernet interrupt status. +//! +//! \param ulBase is the base address of the controller. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This returns the interrupt status for the Ethernet controller. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in EthernetIntEnable(). +// +//***************************************************************************** +unsigned long +EthernetIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Read the unmasked status. + // + ulStatus = HWREG(ulBase + MAC_O_RIS); + + // + // If masked status is requested, mask it off. + // + if(bMasked) + { + ulStatus &= HWREG(ulBase + MAC_O_IM); + } + + // + // Return the interrupt status value. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Clears Ethernet interrupt sources. +//! +//! \param ulBase is the base address of the controller. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified Ethernet interrupt sources are cleared so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to EthernetIntEnable(). +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX))); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + MAC_O_IACK) = ulIntFlags; +} + +//***************************************************************************** +// +//! Writes to the PHY register. +//! +//! \param ulBase is the base address of the controller. +//! \param ucRegAddr is the address of the PHY register to be accessed. +//! \param ulData is the data to be written to the PHY register. +//! +//! This function will write the \e ulData to the PHY register specified by +//! \e ucRegAddr. +//! +//! \return None. +// +//***************************************************************************** +void +EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, + unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Wait for any pending transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Program the DATA to be written. + // + HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M; + + // + // Program the PHY register address and initiate the transaction. + // + HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) | + MAC_MCTL_WRITE | MAC_MCTL_START); + + // + // Wait for the write transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } +} + +//***************************************************************************** +// +//! Reads from a PHY register. +//! +//! \param ulBase is the base address of the controller. +//! \param ucRegAddr is the address of the PHY register to be accessed. +//! +//! This function will return the contents of the PHY register specified by +//! \e ucRegAddr. +//! +//! \return Returns the 16-bit value read from the PHY. +// +//***************************************************************************** +unsigned long +EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ETH_BASE); + + // + // Wait for any pending transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Program the PHY register address and initiate the transaction. + // + HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) | + MAC_MCTL_START); + + // + // Wait for the transaction to complete. + // + while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START) + { + } + + // + // Return the PHY data that was read. + // + return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/ethernet.h b/bsp/lm3s/driverlib/ethernet.h new file mode 100644 index 0000000000..16db1fe03f --- /dev/null +++ b/bsp/lm3s/driverlib/ethernet.h @@ -0,0 +1,172 @@ +//***************************************************************************** +// +// ethernet.h - Defines and Macros for the ethernet module. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ETHERNET_H__ +#define __ETHERNET_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EthernetConfigSet as the ulConfig value, and +// returned from EthernetConfigGet. +// +//***************************************************************************** +#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP) +#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets +#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous +#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast +#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode +#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation +#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding + +//***************************************************************************** +// +// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and +// EthernetIntClear as the ulIntFlags parameter, and returned from +// EthernetIntStatus. +// +//***************************************************************************** +#define ETH_INT_PHY 0x040 // PHY Event/Interrupt +#define ETH_INT_MDIO 0x020 // Management Transaction +#define ETH_INT_RXER 0x010 // RX Error +#define ETH_INT_RXOF 0x008 // RX FIFO Overrun +#define ETH_INT_TX 0x004 // TX Complete +#define ETH_INT_TXER 0x002 // TX Error +#define ETH_INT_RX 0x001 // RX Complete + +//***************************************************************************** +// +// Helper Macros for Ethernet Processing +// +//***************************************************************************** +// +// htonl/ntohl - big endian/little endian byte swapping macros for +// 32-bit (long) values +// +//***************************************************************************** +#ifndef htonl + #define htonl(a) \ + ((((a) >> 24) & 0x000000ff) | \ + (((a) >> 8) & 0x0000ff00) | \ + (((a) << 8) & 0x00ff0000) | \ + (((a) << 24) & 0xff000000)) +#endif + +#ifndef ntohl + #define ntohl(a) htonl((a)) +#endif + +//***************************************************************************** +// +// htons/ntohs - big endian/little endian byte swapping macros for +// 16-bit (short) values +// +//***************************************************************************** +#ifndef htons + #define htons(a) \ + ((((a) >> 8) & 0x00ff) | \ + (((a) << 8) & 0xff00)) +#endif + +#ifndef ntohs + #define ntohs(a) htons((a)) +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk); +extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long EthernetConfigGet(unsigned long ulBase); +extern void EthernetMACAddrSet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetMACAddrGet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetEnable(unsigned long ulBase); +extern void EthernetDisable(unsigned long ulBase); +extern tBoolean EthernetPacketAvail(unsigned long ulBase); +extern tBoolean EthernetSpaceAvail(unsigned long ulBase); +extern long EthernetPacketGetNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPutNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern void EthernetIntRegister(unsigned long ulBase, + void (*pfnHandler)(void)); +extern void EthernetIntUnregister(unsigned long ulBase); +extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, + unsigned long ulData); +extern unsigned long EthernetPHYRead(unsigned long ulBase, + unsigned char ucRegAddr); + +//***************************************************************************** +// +// Several Ethernet APIs have been renamed, with the original function name +// being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define EthernetInit(a) \ + EthernetInitExpClk(a, SysCtlClockGet()) +#define EthernetPacketNonBlockingGet(a, b, c) \ + EthernetPacketGetNonBlocking(a, b, c) +#define EthernetPacketNonBlockingPut(a, b, c) \ + EthernetPacketPutNonBlocking(a, b, c) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ETHERNET_H__ diff --git a/bsp/lm3s/driverlib/flash.c b/bsp/lm3s/driverlib/flash.c new file mode 100644 index 0000000000..56eaa9ade2 --- /dev/null +++ b/bsp/lm3s/driverlib/flash.c @@ -0,0 +1,915 @@ +//***************************************************************************** +// +// flash.c - Driver for programming the on-chip flash. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_flash.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/flash.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Program Enable (FMPPE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPPERegs[] = +{ + FLASH_FMPPE, + FLASH_FMPPE1, + FLASH_FMPPE2, + FLASH_FMPPE3 +}; + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Read Enable (FMPRE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPRERegs[] = +{ + FLASH_FMPRE, + FLASH_FMPRE1, + FLASH_FMPRE2, + FLASH_FMPRE3 +}; + +//***************************************************************************** +// +//! Gets the number of processor clocks per micro-second. +//! +//! This function returns the number of clocks per micro-second, as presently +//! known by the flash controller. +//! +//! \return Returns the number of processor clocks per micro-second. +// +//***************************************************************************** +unsigned long +FlashUsecGet(void) +{ + // + // Return the number of clocks per micro-second. + // + return(HWREG(FLASH_USECRL) + 1); +} + +//***************************************************************************** +// +//! Sets the number of processor clocks per micro-second. +//! +//! \param ulClocks is the number of processor clocks per micro-second. +//! +//! This function is used to tell the flash controller the number of processor +//! clocks per micro-second. This value must be programmed correctly or the +//! flash most likely will not program correctly; it has no affect on reading +//! flash. +//! +//! \return None. +// +//***************************************************************************** +void +FlashUsecSet(unsigned long ulClocks) +{ + // + // Set the number of clocks per micro-second. + // + HWREG(FLASH_USECRL) = ulClocks - 1; +} + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 1 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +long +FlashErase(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); + + // + // Clear the flash access interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC; + + // + // Erase the block. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; + + // + // Wait until the block has been erased. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) + { + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS) + { + return(-1); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will program a sequence of words into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a word can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +long +FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access interrupt. + // + HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC; + + // + // See if this device has a write buffer. + // + if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB) + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Set the address of this block of words. + // + HWREG(FLASH_FMA) = ulAddress & ~(0x7f); + + // + // Loop over the words in this 32-word block. + // + while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) && + (ulCount != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF; + + // + // Wait until the write buffer has been programmed. + // + while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF) + { + } + } + } + else + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Program the next word. + // + HWREG(FLASH_FMA) = ulAddress; + HWREG(FLASH_FMD) = *pulData; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE) + { + } + + // + // Increment to the next word. + // + pulData++; + ulAddress += 4; + ulCount -= 4; + } + } + + // + // Return an error if an access violation occurred. + // + if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS) + { + return(-1); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be queried. +//! +//! This function will get the current protection for the specified 2 kB block +//! of flash. Each block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +tFlashProtection +FlashProtectGet(unsigned long ulAddress) +{ + unsigned long ulFMPRE, ulFMPPE; + unsigned long ulBank; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + + // + // Calculate the Flash Bank from Base Address, and mask off the Bank + // from ulAddress for subsequent reference. + // + ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4); + ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1); + + // + // Read the appropriate flash protection registers for the specified + // flash bank. + // + ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]); + ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]); + + // + // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper + // bits of the FMPPE register are used for JTAG protect options, and are + // not available for the FLASH protection scheme. When Querying Block + // Protection, assume these bits are 1. + // + if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2)) + { + ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30); + } + + // + // Check the appropriate protection bits for the block of memory that + // is specified by the address. + // + switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (that is, it can not be erased + // or programmed, and the only reads allowed are via the instruction + // fetch interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (that is, it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function will set the protection for the specified 2 kB block of +//! flash. Blocks which are read/write can be made read-only or execute-only. +//! Blocks which are read-only can be made execute-only. Blocks which are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (that is, read-only to read/write) will +//! result in a failure (and be prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This allows the application to be executed in the desired flash protection +//! environment to check for inappropriate flash access (via the flash +//! interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +long +FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) +{ + unsigned long ulProtectRE, ulProtectPE; + unsigned long ulBank; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ulAddress /= FLASH_PROTECT_SIZE; + + // + // ulAddress contains a "raw" block number. Derive the Flash Bank from + // the "raw" block number, and convert ulAddress to a "relative" + // block number. + // + ulBank = ((ulAddress / 32) % 4); + ulAddress %= 32; + + // + // Get the current protection for the specified flash bank. + // + ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]); + ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]); + + // + // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper + // bits of the FMPPE register are used for JTAG protect options, and are + // not available for the FLASH protection scheme. When setting protection, + // check to see if block 30 or 31 and protection is FlashExecuteOnly. If + // so, return an error condition. + // + if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2)) + { + if((ulAddress >= 30) && (eProtect == FlashExecuteOnly)) + { + return(-1); + } + } + + // + // Set the protection based on the requested proection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) + { + return(-1); + } + + // + // Make this block read only. + // + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) || + (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper + // bits of the FMPPE register are used for JTAG options, and are not + // available for the FLASH protection scheme. When setting block + // protection, ensure that these bits are not altered. + // + if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2)) + { + ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30); + ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) & + (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30)); + } + + // + // Set the new protection for the specified flash bank. + // + HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE; + HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function will make the currently programmed flash protection settings +//! permanent. This is a non-reversible operation; a chip reset or power cycle +//! will not change the flash protection. +//! +//! This function will not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashProtectSave(void) +{ + int ulTemp, ulLimit; + + // + // If running on a Sandstorm-class device, only trigger a save of the first + // two protection registers (FMPRE and FMPPE). Otherwise, save the + // entire bank of flash protection registers. + // + ulLimit = CLASS_IS_SANDSTORM ? 2 : 8; + for(ulTemp = 0; ulTemp < ulLimit; ulTemp++) + { + // + // Tell the flash controller to write the flash protection register. + // + HWREG(FLASH_FMA) = ulTemp; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Gets the user registers. +//! +//! \param pulUser0 is a pointer to the location to store USER Register 0. +//! \param pulUser1 is a pointer to the location to store USER Register 1. +//! +//! This function will read the contents of user registers (0 and 1), and +//! store them in the specified locations. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1) +{ + // + // Verify that the pointers are valid. + // + ASSERT(pulUser0 != 0); + ASSERT(pulUser1 != 0); + + // + // Verify that hardware supports user registers. + // + if(CLASS_IS_SANDSTORM) + { + return(-1); + } + + // + // Get and store the current value of the user registers. + // + *pulUser0 = HWREG(FLASH_USERREG0); + *pulUser1 = HWREG(FLASH_USERREG1); + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the user registers. +//! +//! \param ulUser0 is the value to store in USER Register 0. +//! \param ulUser1 is the value to store in USER Register 1. +//! +//! This function will set the contents of the user registers (0 and 1) to +//! the specified values. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashUserSet(unsigned long ulUser0, unsigned long ulUser1) +{ + // + // Verify that hardware supports user registers. + // + if(CLASS_IS_SANDSTORM) + { + return(-1); + } + + // + // Save the new values into the user registers. + // + HWREG(FLASH_USERREG0) = ulUser0; + HWREG(FLASH_USERREG1) = ulUser1; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the user registers. +//! +//! This function will make the currently programmed user register settings +//! permanent. This is a non-reversible operation; a chip reset or power cycle +//! will not change this setting. +//! +//! This function will not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +long +FlashUserSave(void) +{ + // + // Verify that hardware supports user registers. + // + if(CLASS_IS_SANDSTORM) + { + return(-1); + } + + // + // Setting the MSB of FMA will trigger a permanent save of a USER + // register. Bit 0 will indicate User 0 (0) or User 1 (1). + // + HWREG(FLASH_FMA) = 0x80000000; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the USER1 Register. + // + HWREG(FLASH_FMA) = 0x80000001; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC. +// +//***************************************************************************** +unsigned long +FlashIntGetStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/flash.h b/bsp/lm3s/driverlib/flash.h new file mode 100644 index 0000000000..0d1f7d4fd5 --- /dev/null +++ b/bsp/lm3s/driverlib/flash.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); +extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); +extern long FlashUserSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/bsp/lm3s/driverlib/gpio.c b/bsp/lm3s/driverlib/gpio.c new file mode 100644 index 0000000000..9936d44373 --- /dev/null +++ b/bsp/lm3s/driverlib/gpio.c @@ -0,0 +1,1512 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_gpio.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// The base addresses of all the GPIO modules. Both the APB and AHB apertures +// are provided. +// +//***************************************************************************** +static const unsigned long g_pulGPIOBaseAddrs[] = +{ + GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE, + GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE, + GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE, + GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE, + GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE, + GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE, + GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE, + GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE, + GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a GPIO base address. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function determines if a GPIO port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +GPIOBaseValid(unsigned long ulPort) +{ + return((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTA_AHB_BASE) || + (ulPort == GPIO_PORTB_BASE) || (ulPort == GPIO_PORTB_AHB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTC_AHB_BASE) || + (ulPort == GPIO_PORTD_BASE) || (ulPort == GPIO_PORTD_AHB_BASE) || + (ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) || + (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) || + (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) || + (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) || + (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the GPIO interrupt number. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +static long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIO_PORTA_BASE: + case GPIO_PORTA_AHB_BASE: + { + ulInt = INT_GPIOA; + break; + } + + case GPIO_PORTB_BASE: + case GPIO_PORTB_AHB_BASE: + { + ulInt = INT_GPIOB; + break; + } + + case GPIO_PORTC_BASE: + case GPIO_PORTC_AHB_BASE: + { + ulInt = INT_GPIOC; + break; + } + + case GPIO_PORTD_BASE: + case GPIO_PORTD_AHB_BASE: + { + ulInt = INT_GPIOD; + break; + } + + case GPIO_PORTE_BASE: + case GPIO_PORTE_AHB_BASE: + { + ulInt = INT_GPIOE; + break; + } + + case GPIO_PORTF_BASE: + case GPIO_PORTF_AHB_BASE: + { + ulInt = INT_GPIOF; + break; + } + + case GPIO_PORTG_BASE: + case GPIO_PORTG_AHB_BASE: + { + ulInt = INT_GPIOG; + break; + } + + case GPIO_PORTH_BASE: + case GPIO_PORTH_AHB_BASE: + { + ulInt = INT_GPIOH; + break; + } + + case GPIO_PORTJ_BASE: + case GPIO_PORTJ_AHB_BASE: + { + ulInt = INT_GPIOJ; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulPinIO is the pin direction and/or mode. +//! +//! This function will set the specified pin(s) on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output, and +//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under +//! hardware control. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || + (ulPinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? + (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AFSEL) & + ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the direction and mode of a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir, ulAFSEL; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_DIR); + ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); + return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); +} + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulIntType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin(s) on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! where the different values describe the interrupt detection mechanism +//! (edge or level) and the particular triggering event (falling, rising, +//! or both edges for edge detect, low or high for level detect). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_IBE); + ulIS = HWREG(ulPort + GPIO_O_IS); + ulIEV = HWREG(ulPort + GPIO_O_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulStrength specifies the output drive strength. +//! \param ulPinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pin(s) +//! on the selected GPIO port. For pin(s) configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ulStrength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! The parameter \e ulPinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_OD_WPU +//! - \b GPIO_PIN_TYPE_OD_WPD +//! - \b GPIO_PIN_TYPE_ANALOG +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an +//! analog input (for the comparators). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, unsigned long ulPinType) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulStrength == GPIO_STRENGTH_2MA) || + (ulStrength == GPIO_STRENGTH_4MA) || + (ulStrength == GPIO_STRENGTH_8MA) || + (ulStrength == GPIO_STRENGTH_8MA_SC)); + ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || + (ulPinType == GPIO_PIN_TYPE_STD_WPU) || + (ulPinType == GPIO_PIN_TYPE_STD_WPD) || + (ulPinType == GPIO_PIN_TYPE_OD) || + (ulPinType == GPIO_PIN_TYPE_OD_WPU) || + (ulPinType == GPIO_PIN_TYPE_OD_WPD) || + (ulPinType == GPIO_PIN_TYPE_ANALOG)) + + // + // Set the output drive strength. + // + HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? + (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? + (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? + (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? + (HWREG(ulPort + GPIO_O_SLR) | ucPins) : + (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); + + // + // Set the pin type. + // + HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? + (HWREG(ulPort + GPIO_O_ODR) | ucPins) : + (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? + (HWREG(ulPort + GPIO_O_PUR) | ucPins) : + (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? + (HWREG(ulPort + GPIO_O_PDR) | ucPins) : + (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? + (HWREG(ulPort + GPIO_O_DEN) | ucPins) : + (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); + + // + // Set the analog mode select register. This register only appears in + // DustDevil-class (and later) devices, but is a harmless write on + // Sandstorm- and Fury-class devices. + // + HWREG(ulPort + GPIO_O_AMSEL) = + ((ulPinType == GPIO_PIN_TYPE_ANALOG) ? + (HWREG(ulPort + GPIO_O_AMSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AMSEL) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! \param pulStrength is a pointer to storage for the output drive strength. +//! \param pulPinType is a pointer to storage for the output drive type. +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e pulStrength and +//! \e pulPinType correspond to the values used in GPIOPadConfigSet(). This +//! function also works for pin(s) configured as input pin(s); however, the +//! only meaningful data returned is whether the pin is terminated with a +//! pull-up or down resistor. +//! +//! \return None +// +//***************************************************************************** +void +GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, unsigned long *pulPinType) +{ + unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = (1 << ucPin); + + // + // Get the drive strength for this pin. + // + ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); + ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); + ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); + ulTemp4 = HWREG(ulPort + GPIO_O_SLR); + *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); + + // + // Get the pin type. + // + ulTemp1 = HWREG(ulPort + GPIO_O_ODR); + ulTemp2 = HWREG(ulPort + GPIO_O_PUR); + ulTemp3 = HWREG(ulPort + GPIO_O_PDR); + ulTemp4 = HWREG(ulPort + GPIO_O_DEN); + *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); +} + +//***************************************************************************** +// +//! Enables interrupts for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Unmasks the interrupt for the specified pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) |= ucPins; +} + +//***************************************************************************** +// +//! Disables interrupts for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Masks the interrupt for the specified pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns a bit-packed byte, where each bit that is set identifies +//! an active masked or raw interrupt, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! Bits 31:8 should be ignored. +// +//***************************************************************************** +long +GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the interrupt for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Clears the interrupt for the specified pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_ICR) = ucPins; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO interrupt +//! in the interrupt controller; individual pin interrupts and interrupt +//! sources must be enabled with GPIOPinIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfnIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOPinIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPortIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} + +//***************************************************************************** +// +//! Reads the values present of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The values at the specified pin(s) are read, as specified by \e ucPins. +//! Values are returned for both input and output pin(s), and the value +//! for pin(s) that are not specified by \e ucPins are set to 0. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); +} + +//***************************************************************************** +// +//! Writes a value to the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ucVal is the value to write to the pin(s). +//! +//! Writes the corresponding bit values to the output pin(s) specified by +//! \e ucPins. Writing to a pin configured as an input pin has no effect. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; +} + +//***************************************************************************** +// +//! Configures pin(s) for use as analog-to-digital converter inputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The analog-to-digital converter input pins must be properly configured +//! to function correctly on DustDevil-class devices. This function provides +//! the proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into an ADC input; it only +//! configures an ADC input pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as a CAN device. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The CAN pins must be properly configured for the CAN peripherals to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a CAN pin; it only +//! configures a CAN pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into an analog comparator input; +//! it only configures an analog comparator pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO inputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO inputs; this is especially true of Fury-class devices where the +//! digital input enable is turned off by default. This function provides the +//! proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO outputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO outputs; this is especially true of Fury-class devices where the +//! digital input enable is turned off by default. This function provides the +//! proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as GPIO open drain outputs. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The GPIO pins must be properly configured in order to function correctly as +//! GPIO outputs; this is especially true of Fury-class devices where the +//! digital input enable is turned off by default. This function provides the +//! proper configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be outputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2C peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for those +//! pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into an I2C pin; it only +//! configures an I2C pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, not using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those +//! pin(s); other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a timer pin; it only +//! configures a timer pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a UART pin; it only +//! configures a UART pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the USB peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some USB digital pins must be properly configured for the USB peripheral to +//! function correctly. This function provides a typical configuration for +//! the digital USB pin(s); other configurations may work as well depending +//! upon the board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the USB peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some USB analog pins must be properly configured for the USB peripheral to +//! function correctly. This function provides the proper configuration for +//! those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a USB pin; it only +//! configures a USB pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2S peripheral. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! Some I2S pins must be properly configured for the I2S peripheral to +//! function correctly. This function provides a typical configuration for +//! the digital I2S pin(s); other configurations may work as well depending +//! upon the board setup (for example, using the on-chip pull-ups). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This cannot be used to turn any pin into a I2S pin; it only +//! configures a I2S pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param ulPinConfig is the pin configuration value, specified as one of the +//! \b GPIO_P??_??? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). +//! +//! \note This function is only valid on Tempest-class devices. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinConfigure(unsigned long ulPinConfig) +{ + unsigned long ulBase, ulShift; + + // + // Check the argument. + // + ASSERT(((ulPinConfig >> 16) & 0xff) < 9); + ASSERT(((ulPinConfig >> 8) & 0xe3) == 0); + + // + // Extract the base address index from the input value. + // + ulBase = (ulPinConfig >> 16) & 0xff; + + // + // Get the base address of the GPIO module, selecting either the APB or the + // AHB aperture as appropriate. + // + if(HWREG(SYSCTL_GPIOHSCTL) & (1 << ulBase)) + { + ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1]; + } + else + { + ulBase = g_pulGPIOBaseAddrs[ulBase << 1]; + } + + // + // Extract the shift from the input value. + // + ulShift = (ulPinConfig >> 8) & 0xff; + + // + // Write the requested pin muxing value for this GPIO pin. + // + HWREG(ulBase + GPIO_O_PCTL) = ((HWREG(ulBase + GPIO_O_PCTL) & + ~(0xf << ulShift)) | + ((ulPinConfig & 0xf) << ulShift)); + +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/gpio.h b/bsp/lm3s/driverlib/gpio.h new file mode 100644 index 0000000000..08b594ff55 --- /dev/null +++ b/bsp/lm3s/driverlib/gpio.h @@ -0,0 +1,768 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter. +// +//***************************************************************************** +// +// GPIO pin A0 +// +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C1SCL 0x00000008 +#define GPIO_PA0_U1RX 0x00000009 + +// +// GPIO pin A1 +// +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C1SDA 0x00000408 +#define GPIO_PA1_U1TX 0x00000409 + +// +// GPIO pin A2 +// +#define GPIO_PA2_SSI0CLK 0x00000801 +#define GPIO_PA2_PWM4 0x00000804 +#define GPIO_PA2_I2S0RXSD 0x00000809 + +// +// GPIO pin A3 +// +#define GPIO_PA3_SSI0FSS 0x00000c01 +#define GPIO_PA3_PWM5 0x00000c04 +#define GPIO_PA3_I2S0RXMCLK 0x00000c09 + +// +// GPIO pin A4 +// +#define GPIO_PA4_SSI0RX 0x00001001 +#define GPIO_PA4_PWM6 0x00001004 +#define GPIO_PA4_CAN0RX 0x00001005 +#define GPIO_PA4_I2S0TXSCK 0x00001009 + +// +// GPIO pin A5 +// +#define GPIO_PA5_SSI0TX 0x00001401 +#define GPIO_PA5_PWM7 0x00001404 +#define GPIO_PA5_CAN0TX 0x00001405 +#define GPIO_PA5_I2S0TXWS 0x00001409 + +// +// GPIO pin A6 +// +#define GPIO_PA6_I2C1SCL 0x00001801 +#define GPIO_PA6_CCP1 0x00001802 +#define GPIO_PA6_PWM0 0x00001804 +#define GPIO_PA6_PWM4 0x00001805 +#define GPIO_PA6_CAN0RX 0x00001806 +#define GPIO_PA6_USB0EPEN 0x00001808 +#define GPIO_PA6_U1CTS 0x00001809 + +// +// GPIO pin A7 +// +#define GPIO_PA7_I2C1SDA 0x00001c01 +#define GPIO_PA7_CCP4 0x00001c02 +#define GPIO_PA7_PWM1 0x00001c04 +#define GPIO_PA7_PWM5 0x00001c05 +#define GPIO_PA7_CAN0TX 0x00001c06 +#define GPIO_PA7_CCP3 0x00001c07 +#define GPIO_PA7_USB0PFLT 0x00001c08 +#define GPIO_PA7_U1DCD 0x00001c09 + +// +// GPIO pin B0 +// +#define GPIO_PB0_CCP0 0x00010001 +#define GPIO_PB0_PWM2 0x00010002 +#define GPIO_PB0_U1RX 0x00010005 + +// +// GPIO pin B1 +// +#define GPIO_PB1_CCP2 0x00010401 +#define GPIO_PB1_PWM3 0x00010402 +#define GPIO_PB1_CCP1 0x00010404 +#define GPIO_PB1_U1TX 0x00010405 + +// +// GPIO pin B2 +// +#define GPIO_PB2_I2C0SCL 0x00010801 +#define GPIO_PB2_IDX0 0x00010802 +#define GPIO_PB2_CCP3 0x00010804 +#define GPIO_PB2_CCP0 0x00010805 +#define GPIO_PB2_USB0EPEN 0x00010808 + +// +// GPIO pin B3 +// +#define GPIO_PB3_I2C0SDA 0x00010c01 +#define GPIO_PB3_FAULT0 0x00010c02 +#define GPIO_PB3_FAULT3 0x00010c04 +#define GPIO_PB3_USB0PFLT 0x00010c08 + +// +// GPIO pin B4 +// +#define GPIO_PB4_U2RX 0x00011004 +#define GPIO_PB4_CAN0RX 0x00011005 +#define GPIO_PB4_IDX0 0x00011006 +#define GPIO_PB4_U1RX 0x00011007 +#define GPIO_PB4_EPI0S23 0x00011008 + +// +// GPIO pin B5 +// +#define GPIO_PB5_C0O 0x00011401 +#define GPIO_PB5_CCP5 0x00011402 +#define GPIO_PB5_CCP6 0x00011403 +#define GPIO_PB5_CCP0 0x00011404 +#define GPIO_PB5_CAN0TX 0x00011405 +#define GPIO_PB5_CCP2 0x00011406 +#define GPIO_PB5_U1TX 0x00011407 +#define GPIO_PB5_EPI0S22 0x00011408 + +// +// GPIO pin B6 +// +#define GPIO_PB6_CCP1 0x00011801 +#define GPIO_PB6_CCP7 0x00011802 +#define GPIO_PB6_C0O 0x00011803 +#define GPIO_PB6_FAULT1 0x00011804 +#define GPIO_PB6_IDX0 0x00011805 +#define GPIO_PB6_CCP5 0x00011806 +#define GPIO_PB6_I2S0TXSCK 0x00011809 + +// +// GPIO pin B7 +// +#define GPIO_PB7_NMI 0x00011c04 + +// +// GPIO pin C0 +// +#define GPIO_PC0_TCK 0x00020003 + +// +// GPIO pin C1 +// +#define GPIO_PC1_TMS 0x00020403 + +// +// GPIO pin C2 +// +#define GPIO_PC2_TDI 0x00020803 + +// +// GPIO pin C3 +// +#define GPIO_PC3_TDO 0x00020c03 + +// +// GPIO pin C4 +// +#define GPIO_PC4_CCP5 0x00021001 +#define GPIO_PC4_PHA0 0x00021002 +#define GPIO_PC4_PWM6 0x00021004 +#define GPIO_PC4_CCP2 0x00021005 +#define GPIO_PC4_CCP4 0x00021006 +#define GPIO_PC4_EPI0S2 0x00021008 +#define GPIO_PC4_CCP1 0x00021009 + +// +// GPIO pin C5 +// +#define GPIO_PC5_CCP1 0x00021401 +#define GPIO_PC5_C1O 0x00021402 +#define GPIO_PC5_C0O 0x00021403 +#define GPIO_PC5_FAULT2 0x00021404 +#define GPIO_PC5_CCP3 0x00021405 +#define GPIO_PC5_USB0EPEN 0x00021406 +#define GPIO_PC5_EPI0S3 0x00021408 + +// +// GPIO pin C6 +// +#define GPIO_PC6_CCP3 0x00021801 +#define GPIO_PC6_PHB0 0x00021802 +#define GPIO_PC6_C2O 0x00021803 +#define GPIO_PC6_PWM7 0x00021804 +#define GPIO_PC6_U1RX 0x00021805 +#define GPIO_PC6_CCP0 0x00021806 +#define GPIO_PC6_USB0PFLT 0x00021807 +#define GPIO_PC6_EPI0S4 0x00021808 + +// +// GPIO pin C7 +// +#define GPIO_PC7_CCP4 0x00021c01 +#define GPIO_PC7_PHB0 0x00021c02 +#define GPIO_PC7_CCP0 0x00021c04 +#define GPIO_PC7_U1TX 0x00021c05 +#define GPIO_PC7_USB0PFLT 0x00021c06 +#define GPIO_PC7_C1O 0x00021c07 +#define GPIO_PC7_EPI0S5 0x00021c08 + +// +// GPIO pin D0 +// +#define GPIO_PD0_PWM0 0x00030001 +#define GPIO_PD0_CAN0RX 0x00030002 +#define GPIO_PD0_IDX0 0x00030003 +#define GPIO_PD0_U2RX 0x00030004 +#define GPIO_PD0_U1RX 0x00030005 +#define GPIO_PD0_CCP6 0x00030006 +#define GPIO_PD0_I2S0RXSCK 0x00030008 +#define GPIO_PD0_U1CTS 0x00030009 + +// +// GPIO pin D1 +// +#define GPIO_PD1_PWM1 0x00030401 +#define GPIO_PD1_CAN0TX 0x00030402 +#define GPIO_PD1_PHA0 0x00030403 +#define GPIO_PD1_U2TX 0x00030404 +#define GPIO_PD1_U1TX 0x00030405 +#define GPIO_PD1_CCP7 0x00030406 +#define GPIO_PD1_I2S0RXWS 0x00030408 +#define GPIO_PD1_U1DCD 0x00030409 +#define GPIO_PD1_CCP2 0x0003040a +#define GPIO_PD1_PHB1 0x0003040b + +// +// GPIO pin D2 +// +#define GPIO_PD2_U1RX 0x00030801 +#define GPIO_PD2_CCP6 0x00030802 +#define GPIO_PD2_PWM2 0x00030803 +#define GPIO_PD2_CCP5 0x00030804 +#define GPIO_PD2_EPI0S20 0x00030808 + +// +// GPIO pin D3 +// +#define GPIO_PD3_U1TX 0x00030c01 +#define GPIO_PD3_CCP7 0x00030c02 +#define GPIO_PD3_PWM3 0x00030c03 +#define GPIO_PD3_CCP0 0x00030c04 +#define GPIO_PD3_EPI0S21 0x00030c08 + +// +// GPIO pin D4 +// +#define GPIO_PD4_CCP0 0x00031001 +#define GPIO_PD4_CCP3 0x00031002 +#define GPIO_PD4_I2S0RXSD 0x00031008 +#define GPIO_PD4_U1RI 0x00031009 +#define GPIO_PD4_EPI0S19 0x0003100a + +// +// GPIO pin D5 +// +#define GPIO_PD5_CCP2 0x00031401 +#define GPIO_PD5_CCP4 0x00031402 +#define GPIO_PD5_I2S0RXMCLK 0x00031408 +#define GPIO_PD5_U2RX 0x00031409 +#define GPIO_PD5_EPI0S28 0x0003140a + +// +// GPIO pin D6 +// +#define GPIO_PD6_FAULT0 0x00031801 +#define GPIO_PD6_I2S0TXSCK 0x00031808 +#define GPIO_PD6_U2TX 0x00031809 +#define GPIO_PD6_EPI0S29 0x0003180a + +// +// GPIO pin D7 +// +#define GPIO_PD7_IDX0 0x00031c01 +#define GPIO_PD7_C0O 0x00031c02 +#define GPIO_PD7_CCP1 0x00031c03 +#define GPIO_PD7_I2S0TXWS 0x00031c08 +#define GPIO_PD7_U1DTR 0x00031c09 +#define GPIO_PD7_EPI0S30 0x00031c0a + +// +// GPIO pin E0 +// +#define GPIO_PE0_PWM4 0x00040001 +#define GPIO_PE0_SSI1CLK 0x00040002 +#define GPIO_PE0_CCP3 0x00040003 +#define GPIO_PE0_EPI0S8 0x00040008 +#define GPIO_PE0_USB0PFLT 0x00040009 + +// +// GPIO pin E1 +// +#define GPIO_PE1_PWM5 0x00040401 +#define GPIO_PE1_SSI1FSS 0x00040402 +#define GPIO_PE1_FAULT0 0x00040403 +#define GPIO_PE1_CCP2 0x00040404 +#define GPIO_PE1_CCP6 0x00040405 +#define GPIO_PE1_EPI0S9 0x00040408 + +// +// GPIO pin E2 +// +#define GPIO_PE2_CCP4 0x00040801 +#define GPIO_PE2_SSI1RX 0x00040802 +#define GPIO_PE2_PHB1 0x00040803 +#define GPIO_PE2_PHA0 0x00040804 +#define GPIO_PE2_CCP2 0x00040805 +#define GPIO_PE2_EPI0S24 0x00040808 + +// +// GPIO pin E3 +// +#define GPIO_PE3_CCP1 0x00040c01 +#define GPIO_PE3_SSI1TX 0x00040c02 +#define GPIO_PE3_PHA1 0x00040c03 +#define GPIO_PE3_PHB0 0x00040c04 +#define GPIO_PE3_CCP7 0x00040c05 +#define GPIO_PE3_EPI0S25 0x00040c08 + +// +// GPIO pin E4 +// +#define GPIO_PE4_CCP3 0x00041001 +#define GPIO_PE4_FAULT0 0x00041004 +#define GPIO_PE4_U2TX 0x00041005 +#define GPIO_PE4_CCP2 0x00041006 +#define GPIO_PE4_I2S0TXWS 0x00041009 + +// +// GPIO pin E5 +// +#define GPIO_PE5_CCP5 0x00041401 +#define GPIO_PE5_I2S0TXSD 0x00041409 + +// +// GPIO pin E6 +// +#define GPIO_PE6_PWM4 0x00041801 +#define GPIO_PE6_C1O 0x00041802 +#define GPIO_PE6_U1CTS 0x00041809 + +// +// GPIO pin E7 +// +#define GPIO_PE7_PWM5 0x00041c01 +#define GPIO_PE7_C2O 0x00041c02 +#define GPIO_PE7_U1DCD 0x00041c09 + +// +// GPIO pin F0 +// +#define GPIO_PF0_CAN1RX 0x00050001 +#define GPIO_PF0_PHB0 0x00050002 +#define GPIO_PF0_PWM0 0x00050003 +#define GPIO_PF0_I2S0TXSD 0x00050008 +#define GPIO_PF0_U1DSR 0x00050009 + +// +// GPIO pin F1 +// +#define GPIO_PF1_CAN1TX 0x00050401 +#define GPIO_PF1_IDX1 0x00050402 +#define GPIO_PF1_PWM1 0x00050403 +#define GPIO_PF1_I2S0TXMCLK 0x00050408 +#define GPIO_PF1_U1RTS 0x00050409 +#define GPIO_PF1_CCP3 0x0005040a + +// +// GPIO pin F2 +// +#define GPIO_PF2_LED1 0x00050801 +#define GPIO_PF2_PWM4 0x00050802 +#define GPIO_PF2_PWM2 0x00050804 +#define GPIO_PF2_SSI1CLK 0x00050809 + +// +// GPIO pin F3 +// +#define GPIO_PF3_LED0 0x00050c01 +#define GPIO_PF3_PWM5 0x00050c02 +#define GPIO_PF3_PWM3 0x00050c04 +#define GPIO_PF3_SSI1FSS 0x00050c09 + +// +// GPIO pin F4 +// +#define GPIO_PF4_CCP0 0x00051001 +#define GPIO_PF4_C0O 0x00051002 +#define GPIO_PF4_FAULT0 0x00051004 +#define GPIO_PF4_EPI0S12 0x00051008 +#define GPIO_PF4_SSI1RX 0x00051009 + +// +// GPIO pin F5 +// +#define GPIO_PF5_CCP2 0x00051401 +#define GPIO_PF5_C1O 0x00051402 +#define GPIO_PF5_EPI0S15 0x00051408 +#define GPIO_PF5_SSI1TX 0x00051409 + +// +// GPIO pin F6 +// +#define GPIO_PF6_CCP1 0x00051801 +#define GPIO_PF6_C2O 0x00051802 +#define GPIO_PF6_PHA0 0x00051804 +#define GPIO_PF6_I2S0TXMCLK 0x00051809 +#define GPIO_PF6_U1RTS 0x0005180a + +// +// GPIO pin F7 +// +#define GPIO_PF7_CCP4 0x00051c01 +#define GPIO_PF7_PHB0 0x00051c04 +#define GPIO_PF7_EPI0S12 0x00051c08 +#define GPIO_PF7_FAULT1 0x00051c09 + +// +// GPIO pin G0 +// +#define GPIO_PG0_U2RX 0x00060001 +#define GPIO_PG0_PWM0 0x00060002 +#define GPIO_PG0_I2C1SCL 0x00060003 +#define GPIO_PG0_PWM4 0x00060004 +#define GPIO_PG0_USB0EPEN 0x00060007 +#define GPIO_PG0_EPI0S13 0x00060008 + +// +// GPIO pin G1 +// +#define GPIO_PG1_U2TX 0x00060401 +#define GPIO_PG1_PWM1 0x00060402 +#define GPIO_PG1_I2C1SDA 0x00060403 +#define GPIO_PG1_PWM5 0x00060404 +#define GPIO_PG1_EPI0S14 0x00060408 + +// +// GPIO pin G2 +// +#define GPIO_PG2_PWM0 0x00060801 +#define GPIO_PG2_FAULT0 0x00060804 +#define GPIO_PG2_IDX1 0x00060808 +#define GPIO_PG2_I2S0RXSD 0x00060809 + +// +// GPIO pin G3 +// +#define GPIO_PG3_PWM1 0x00060c01 +#define GPIO_PG3_FAULT2 0x00060c04 +#define GPIO_PG3_FAULT0 0x00060c08 +#define GPIO_PG3_I2S0RXMCLK 0x00060c09 + +// +// GPIO pin G4 +// +#define GPIO_PG4_CCP3 0x00061001 +#define GPIO_PG4_FAULT1 0x00061004 +#define GPIO_PG4_EPI0S15 0x00061008 +#define GPIO_PG4_PWM6 0x00061009 +#define GPIO_PG4_U1RI 0x0006100a + +// +// GPIO pin G5 +// +#define GPIO_PG5_CCP5 0x00061401 +#define GPIO_PG5_IDX0 0x00061404 +#define GPIO_PG5_FAULT1 0x00061405 +#define GPIO_PG5_PWM7 0x00061408 +#define GPIO_PG5_I2S0RXSCK 0x00061409 +#define GPIO_PG5_U1DTR 0x0006140a + +// +// GPIO pin G6 +// +#define GPIO_PG6_PHA1 0x00061801 +#define GPIO_PG6_PWM6 0x00061804 +#define GPIO_PG6_FAULT1 0x00061808 +#define GPIO_PG6_I2S0RXWS 0x00061809 +#define GPIO_PG6_U1RI 0x0006180a + +// +// GPIO pin G7 +// +#define GPIO_PG7_PHB1 0x00061c01 +#define GPIO_PG7_PWM7 0x00061c04 +#define GPIO_PG7_CCP5 0x00061c08 +#define GPIO_PG7_EPI0S31 0x00061c09 + +// +// GPIO pin H0 +// +#define GPIO_PH0_CCP6 0x00070001 +#define GPIO_PH0_PWM2 0x00070002 +#define GPIO_PH0_EPI0S6 0x00070008 +#define GPIO_PH0_PWM4 0x00070009 + +// +// GPIO pin H1 +// +#define GPIO_PH1_CCP7 0x00070401 +#define GPIO_PH1_PWM3 0x00070402 +#define GPIO_PH1_EPI0S7 0x00070408 +#define GPIO_PH1_PWM5 0x00070409 + +// +// GPIO pin H2 +// +#define GPIO_PH2_IDX1 0x00070801 +#define GPIO_PH2_C1O 0x00070802 +#define GPIO_PH2_FAULT3 0x00070804 +#define GPIO_PH2_EPI0S1 0x00070808 + +// +// GPIO pin H3 +// +#define GPIO_PH3_PHB0 0x00070c01 +#define GPIO_PH3_FAULT0 0x00070c02 +#define GPIO_PH3_USB0EPEN 0x00070c04 +#define GPIO_PH3_EPI0S0 0x00070c08 + +// +// GPIO pin H4 +// +#define GPIO_PH4_USB0PFLT 0x00071004 +#define GPIO_PH4_EPI0S10 0x00071008 +#define GPIO_PH4_SSI1CLK 0x0007100b + +// +// GPIO pin H5 +// +#define GPIO_PH5_EPI0S11 0x00071408 +#define GPIO_PH5_FAULT2 0x0007140a +#define GPIO_PH5_SSI1FSS 0x0007140b + +// +// GPIO pin H6 +// +#define GPIO_PH6_EPI0S26 0x00071808 +#define GPIO_PH6_PWM4 0x0007180a +#define GPIO_PH6_SSI1RX 0x0007180b + +// +// GPIO pin H7 +// +#define GPIO_PH7_EPI0S27 0x00071c08 +#define GPIO_PH7_PWM5 0x00071c0a +#define GPIO_PH7_SSI1TX 0x00071c0b + +// +// GPIO pin J0 +// +#define GPIO_PJ0_EPI0S16 0x00080008 +#define GPIO_PJ0_PWM0 0x0008000a +#define GPIO_PJ0_I2C1SCL 0x0008000b + +// +// GPIO pin J1 +// +#define GPIO_PJ1_EPI0S17 0x00080408 +#define GPIO_PJ1_USB0PFLT 0x00080409 +#define GPIO_PJ1_PWM1 0x0008040a +#define GPIO_PJ1_I2C1SDA 0x0008040b + +// +// GPIO pin J2 +// +#define GPIO_PJ2_EPI0S18 0x00080808 +#define GPIO_PJ2_CCP0 0x00080809 +#define GPIO_PJ2_FAULT0 0x0008080a + +// +// GPIO pin J3 +// +#define GPIO_PJ3_EPI0S19 0x00080c08 +#define GPIO_PJ3_U1CTS 0x00080c09 +#define GPIO_PJ3_CCP6 0x00080c0a + +// +// GPIO pin J4 +// +#define GPIO_PJ4_EPI0S28 0x00081008 +#define GPIO_PJ4_U1DCD 0x00081009 +#define GPIO_PJ4_CCP4 0x0008100a + +// +// GPIO pin J5 +// +#define GPIO_PJ5_EPI0S29 0x00081408 +#define GPIO_PJ5_U1DSR 0x00081409 +#define GPIO_PJ5_CCP2 0x0008140a + +// +// GPIO pin J6 +// +#define GPIO_PJ6_EPI0S30 0x00081808 +#define GPIO_PJ6_U1RTS 0x00081809 +#define GPIO_PJ6_CCP1 0x0008180a + +// +// GPIO pin J7 +// +#define GPIO_PJ7_U1DTR 0x00081c09 +#define GPIO_PJ7_CCP0 0x00081c0a + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfnIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinConfigure(unsigned long ulPinConfig); +extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort, + unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/bsp/lm3s/driverlib/hibernate.c b/bsp/lm3s/driverlib/hibernate.c new file mode 100644 index 0000000000..b2ff21b82e --- /dev/null +++ b/bsp/lm3s/driverlib/hibernate.c @@ -0,0 +1,965 @@ +//***************************************************************************** +// +// hibernate.c - Driver for the Hibernation module +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup hibernate_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_hibernate.h" +#include "inc/hw_ints.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/hibernate.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +// The delay in microseconds for writing to the Hibernation module registers. +// +//***************************************************************************** +#define DELAY_USECS 95 + +//***************************************************************************** +// +// The number of processor cycles to execute one pass of the delay loop. +// +//***************************************************************************** +#define LOOP_CYCLES 3 + +//***************************************************************************** +// +// The calculated number of delay loops to achieve the write delay. +// +//***************************************************************************** +static unsigned long g_ulWriteDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Polls until the write complete (WRC) bit in the hibernate control register +//! is set. +//! +//! \param None. +//! +//! On non-Fury-class devices, the hibernate module provides an indication when +//! any write is completed. This is used to pace writes to the module. This +//! function merely polls this bit and returns as soon as it is set. At this +//! point, it is safe to perform another write to the module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateWriteComplete(void) +{ + // + // Spin until the write complete bit is set. + // + while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) + { + } +} + +//***************************************************************************** +// +//! Enables the Hibernation module for operation. +//! +//! \param ulHibClk is the rate of the clock supplied to the Hibernation +//! module. +//! +//! Enables the Hibernation module for operation. This function should be +//! called before any of the Hibernation module features are used. +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original HibernateEnable() API and performs the +//! same actions. A macro is provided in hibernate.h to map the +//! original API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateEnableExpClk(unsigned long ulHibClk) +{ + // + // Turn on the clock enable bit. + // + HWREG(HIB_CTL) |= HIB_CTL_CLK32EN; + + // + // For Fury-class devices, compute the number of delay loops that must be + // used to achieve the desired delay for writes to the hibernation + // registers. This value will be used in calls to SysCtlDelay(). + // + if(CLASS_IS_FURY) + { + g_ulWriteDelay = (((ulHibClk / 1000) * DELAY_USECS) / + (1000L * LOOP_CYCLES)); + g_ulWriteDelay++; + } +} + +//***************************************************************************** +// +//! Disables the Hibernation module for operation. +//! +//! Disables the Hibernation module for operation. After this function is +//! called, none of the Hibernation module features are available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDisable(void) +{ + // + // Turn off the clock enable bit. + // + HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; +} + +//***************************************************************************** +// +//! Selects the clock input for the Hibernation module. +//! +//! \param ulClockInput specifies the clock input. +//! +//! Configures the clock input for the Hibernation module. The configuration +//! option chosen depends entirely on hardware design. The clock input for the +//! module will either be a 32.768 kHz oscillator or a 4.194304 MHz crystal. +//! The \e ulClockFlags parameter must be one of the following: +//! +//! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz +//! oscillator. +//! - \b HIBERNATE_CLOCK_SEL_DIV128 - use the crystal input, divided by 128. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateClockSelect(unsigned long ulClockInput) +{ + // + // Check the arguments. + // + ASSERT((ulClockInput == HIBERNATE_CLOCK_SEL_RAW) || + (ulClockInput == HIBERNATE_CLOCK_SEL_DIV128)); + + // + // Set the clock selection bit according to the parameter. + // + HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL); +} + +//***************************************************************************** +// +//! Enables the RTC feature of the Hibernation module. +//! +//! Enables the RTC in the Hibernation module. The RTC can be used to wake the +//! processor from hibernation at a certain time, or to generate interrupts at +//! certain times. This function must be called before using any of the RTC +//! features of the Hibernation module. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCEnable(void) +{ + // + // Turn on the RTC enable bit. + // + HWREG(HIB_CTL) |= HIB_CTL_RTCEN; +} + +//***************************************************************************** +// +//! Disables the RTC feature of the Hibernation module. +//! +//! Disables the RTC in the Hibernation module. After calling this function +//! the RTC features of the Hibernation module will not be available. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCDisable(void) +{ + // + // Turn off the RTC enable bit. + // + HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; +} + +//***************************************************************************** +// +//! Configures the wake conditions for the Hibernation module. +//! +//! \param ulWakeFlags specifies which conditions should be used for waking. +//! +//! Enables the conditions under which the Hibernation module will wake. The +//! \e ulWakeFlags parameter is the logical OR of any combination of the +//! following: +//! +//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. +//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateWakeSet(unsigned long ulWakeFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC))); + + // + // Set the specified wake flags in the control register. + // + HWREG(HIB_CTL) = (ulWakeFlags | + (HWREG(HIB_CTL) & + ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC))); +} + +//***************************************************************************** +// +//! Gets the currently configured wake conditions for the Hibernation module. +//! +//! Returns the flags representing the wake configuration for the Hibernation +//! module. The return value will be a combination of the following flags: +//! +//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. +//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. +//! +//! \return Returns flags indicating the configured wake conditions. +// +//***************************************************************************** +unsigned long +HibernateWakeGet(void) +{ + // + // Read the wake bits from the control register and return + // those bits to the caller. + // + return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)); +} + +//***************************************************************************** +// +//! Configures the low battery detection. +//! +//! \param ulLowBatFlags specifies behavior of low battery detection. +//! +//! Enables the low battery detection and whether hibernation is allowed if a +//! low battery is detected. If low battery detection is enabled, then a low +//! battery condition will be indicated in the raw interrupt status register, +//! and can also trigger an interrupt. Optionally, hibernation can be aborted +//! if a low battery is detected. +//! +//! The \e ulLowBatFlags parameter is one of the following values: +//! +//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition. +//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort +//! hibernation if low battery is detected. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateLowBatSet(unsigned long ulLowBatFlags) +{ + // + // Check the arguments. + // + ASSERT((ulLowBatFlags == HIBERNATE_LOW_BAT_DETECT) || + (ulLowBatFlags == HIBERNATE_LOW_BAT_ABORT)); + + // + // Set the low battery detect and abort bits in the control register, + // according to the parameter. + // + HWREG(HIB_CTL) = (ulLowBatFlags | + (HWREG(HIB_CTL) & ~HIBERNATE_LOW_BAT_ABORT)); +} + +//***************************************************************************** +// +//! Gets the currently configured low battery detection behavior. +//! +//! Returns a value representing the currently configured low battery detection +//! behavior. The return value will be one of the following: +//! +//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition. +//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort +//! hibernation if low battery is detected. +//! +//! \return Returns a value indicating the configured low battery detection. +// +//***************************************************************************** +unsigned long +HibernateLowBatGet(void) +{ + // + // Read the low bat bits from the control register and return those bits to + // the caller. + // + return(HWREG(HIB_CTL) & HIBERNATE_LOW_BAT_ABORT); +} + +//***************************************************************************** +// +//! Sets the value of the real time clock (RTC) counter. +//! +//! \param ulRTCValue is the new value for the RTC. +//! +//! Sets the value of the RTC. The RTC will count seconds if the hardware is +//! configured correctly. The RTC must be enabled by calling +//! HibernateRTCEnable() before calling this function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCSet(unsigned long ulRTCValue) +{ + // + // Write the new RTC value to the RTC load register. + // + HWREG(HIB_RTCLD) = ulRTCValue; + + // + // Add a delay here to enforce the required delay between write accesses to + // certain Hibernation module registers. + // + if(CLASS_IS_FURY) + { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Gets the value of the real time clock (RTC) counter. +//! +//! Gets the value of the RTC and returns it to the caller. +//! +//! \return Returns the value of the RTC. +// +//***************************************************************************** +unsigned long +HibernateRTCGet(void) +{ + // + // Return the value of the RTC counter register to the caller. + // + return(HWREG(HIB_RTCC)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC match 0 register. +//! +//! \param ulMatch is the value for the match register. +//! +//! Sets the match 0 register for the RTC. The Hibernation module can be +//! configured to wake from hibernation, and/or generate an interrupt when the +//! value of the RTC counter is the same as the match register. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCMatch0Set(unsigned long ulMatch) +{ + // + // Write the new match value to the match register. + // + HWREG(HIB_RTCM0) = ulMatch; + + // + // Add a delay here to enforce the required delay between write accesses to + // certain Hibernation module registers. + // + if(CLASS_IS_FURY) + { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Gets the value of the RTC match 0 register. +//! +//! Gets the value of the match 0 register for the RTC. +//! +//! \return Returns the value of the match register. +// +//***************************************************************************** +unsigned long +HibernateRTCMatch0Get(void) +{ + // + // Return the value of the match register to the caller. + // + return(HWREG(HIB_RTCM0)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC match 1 register. +//! +//! \param ulMatch is the value for the match register. +//! +//! Sets the match 1 register for the RTC. The Hibernation module can be +//! configured to wake from hibernation, and/or generate an interrupt when the +//! value of the RTC counter is the same as the match register. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCMatch1Set(unsigned long ulMatch) +{ + // + // Write the new match value to the match register. + // + HWREG(HIB_RTCM1) = ulMatch; + + // + // Add a delay here to enforce the required delay between write accesses to + // certain Hibernation module registers. + // + if(CLASS_IS_FURY) + { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Gets the value of the RTC match 1 register. +//! +//! Gets the value of the match 1 register for the RTC. +//! +//! \return Returns the value of the match register. +// +//***************************************************************************** +unsigned long +HibernateRTCMatch1Get(void) +{ + // + // Return the value of the match register to the caller. + // + return(HWREG(HIB_RTCM1)); +} + +//***************************************************************************** +// +//! Sets the value of the RTC predivider trim register. +//! +//! \param ulTrim is the new value for the pre-divider trim register. +//! +//! Sets the value of the pre-divider trim register. The input time source is +//! divided by the pre-divider to achieve a one-second clock rate. Once every +//! 64 seconds, the value of the pre-divider trim register is applied to the +//! predivider to allow fine-tuning of the RTC rate, in order to make +//! corrections to the rate. The software application can make adjustments to +//! the predivider trim register to account for variations in the accuracy of +//! the input time source. The nominal value is 0x7FFF, and it can be adjusted +//! up or down in order to fine-tune the RTC rate. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRTCTrimSet(unsigned long ulTrim) +{ + // + // Check the arguments. + // + ASSERT(ulTrim < 0x10000); + + // + // Write the new trim value to the trim register. + // + HWREG(HIB_RTCT) = ulTrim; + + // + // Add a delay here to enforce the required delay between write accesses to + // certain Hibernation module registers. + // + if(CLASS_IS_FURY) + { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); + } +} + +//***************************************************************************** +// +//! Gets the value of the RTC predivider trim register. +//! +//! Gets the value of the pre-divider trim register. This function can be used +//! to get the current value of the trim register prior to making an adjustment +//! by using the HibernateRTCTrimSet() function. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +HibernateRTCTrimGet(void) +{ + // + // Return the value of the trim register to the caller. + // + return(HWREG(HIB_RTCT)); +} + +//***************************************************************************** +// +//! Stores data in the non-volatile memory of the Hibernation module. +//! +//! \param pulData points to the data that the caller wants to store in the +//! memory of the Hibernation module. +//! \param ulCount is the count of 32-bit words to store. +//! +//! Stores a set of data in the Hibernation module non-volatile memory. This +//! memory will be preserved when the power to the processor is turned off, and +//! can be used to store application state information which will be available +//! when the processor wakes. Up to 64 32-bit words can be stored in the +//! non-volatile memory. The data can be restored by calling the +//! HibernateDataGet() function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDataSet(unsigned long *pulData, unsigned long ulCount) +{ + unsigned int uIdx; + + // + // Check the arguments. + // + ASSERT(ulCount <= 64); + ASSERT(pulData != 0); + + // + // Loop through all the words to be stored, storing one at a time. + // + for(uIdx = 0; uIdx < ulCount; uIdx++) + { + // + // Write a word to the non-volatile storage area. + // + HWREG(HIB_DATA + (uIdx * 4)) = pulData[uIdx]; + + // + // Add a delay between writes to the data area. + // + if(CLASS_IS_FURY) + { + // + // Delay a fixed time on Fury-class devices + // + SysCtlDelay(g_ulWriteDelay); + } + else + { + // + // Wait for write complete to be signaled on later devices. + // + HibernateWriteComplete(); + } + } +} + +//***************************************************************************** +// +//! Reads a set of data from the non-volatile memory of the Hibernation module. +//! +//! \param pulData points to a location where the data that is read from the +//! Hibernation module will be stored. +//! \param ulCount is the count of 32-bit words to read. +//! +//! Retrieves a set of data from the Hibernation module non-volatile memory +//! that was previously stored with the HibernateDataSet() function. The +//! caller must ensure that \e pulData points to a large enough memory block to +//! hold all the data that is read from the non-volatile memory. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateDataGet(unsigned long *pulData, unsigned long ulCount) +{ + unsigned int uIdx; + + // + // Check the arguments. + // + ASSERT(ulCount <= 64); + ASSERT(pulData != 0); + + // + // Loop through all the words to be restored, reading one at a time. + // + for(uIdx = 0; uIdx < ulCount; uIdx++) + { + // + // Read a word from the non-volatile storage area. No delay is + // required between reads. + // + pulData[uIdx] = HWREG(HIB_DATA + (uIdx * 4)); + } +} + +//***************************************************************************** +// +//! Requests hibernation mode. +//! +//! This function requests the Hibernation module to disable the external +//! regulator, thus removing power from the processor and all peripherals. The +//! Hibernation module will remain powered from the battery or auxiliary power +//! supply. +//! +//! The Hibernation module will re-enable the external regulator when one of +//! the configured wake conditions occurs (such as RTC match or external +//! \b WAKE pin). When the power is restored the processor will go through a +//! normal power-on reset. The processor can retrieve saved state information +//! with the HibernateDataGet() function. Prior to calling the function to +//! request hibernation mode, the conditions for waking must have already been +//! set by using the HibernateWakeSet() function. +//! +//! Note that this function may return because some time may elapse before the +//! power is actually removed, or it may not be removed at all. For this +//! reason, the processor will continue to execute instructions for some time +//! and the caller should be prepared for this function to return. There are +//! various reasons why the power may not be removed. For example, if the +//! HibernateLowBatSet() function was used to configure an abort if low +//! battery is detected, then the power will not be removed if the battery +//! voltage is too low. There may be other reasons, related to the external +//! circuit design, that a request for hibernation may not actually occur. +//! +//! For all these reasons, the caller must be prepared for this function to +//! return. The simplest way to handle it is to just enter an infinite loop +//! and wait for the power to be removed. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateRequest(void) +{ + // + // Set the bit in the control register to cut main power to the processor. + // + HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; +} + +//***************************************************************************** +// +//! Enables interrupts for the Hibernation module. +//! +//! \param ulIntFlags is the bit mask of the interrupts to be enabled. +//! +//! Enables the specified interrupt sources from the Hibernation module. +//! +//! The \e ulIntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt +//! - \b HIBERNATE_INT_LOW_BAT - low battery interrupt +//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt +//! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntEnable(unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_RTC_MATCH_1))); + + // + // Set the specified interrupt mask bits. + // + HWREG(HIB_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables interrupts for the Hibernation module. +//! +//! \param ulIntFlags is the bit mask of the interrupts to be disabled. +//! +//! Disables the specified interrupt sources from the Hibernation module. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to the HibernateIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntDisable(unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_RTC_MATCH_1))); + + // + // Clear the specified interrupt mask bits. + // + HWREG(HIB_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the Hibernation module interrupt. +//! +//! \param pfnHandler points to the function to be called when a hibernation +//! interrupt occurs. +//! +//! Registers the interrupt handler in the system interrupt controller. The +//! interrupt is enabled at the global level, but individual interrupt sources +//! must still be enabled with a call to HibernateIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_HIBERNATE, pfnHandler); + + // + // Enable the hibernate module interrupt. + // + IntEnable(INT_HIBERNATE); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the Hibernation module interrupt. +//! +//! Unregisters the interrupt handler in the system interrupt controller. The +//! interrupt is disabled at the global level, and the interrupt handler will +//! no longer be called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntUnregister(void) +{ + // + // Disable the hibernate interrupt. + // + IntDisable(INT_HIBERNATE); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_HIBERNATE); +} + +//***************************************************************************** +// +//! Gets the current interrupt status of the Hibernation module. +//! +//! \param bMasked is false to retrieve the raw interrupt status, and true to +//! retrieve the masked interrupt status. +//! +//! Returns the interrupt status of the Hibernation module. The caller can use +//! this to determine the cause of a hibernation interrupt. Either the masked +//! or raw interrupt status can be returned. +//! +//! \return Returns the interrupt status as a bit field with the values as +//! described in the HibernateIntEnable() function. +// +//***************************************************************************** +unsigned long +HibernateIntStatus(tBoolean bMasked) +{ + // + // Read and return the Hibernation module raw or masked interrupt status. + // + if(bMasked == true) + { + return(HWREG(HIB_MIS) & 0xf); + } + else + { + return(HWREG(HIB_RIS) & 0xf); + } +} + +//***************************************************************************** +// +//! Clears pending interrupts from the Hibernation module. +//! +//! \param ulIntFlags is the bit mask of the interrupts to be cleared. +//! +//! Clears the specified interrupt sources. This must be done from within the +//! interrupt handler or else the handler will be called again upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to the HibernateIntEnable() function. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +HibernateIntClear(unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | + HIBERNATE_INT_RTC_MATCH_0 | + HIBERNATE_INT_RTC_MATCH_1))); + + // + // Write the specified interrupt bits into the interrupt clear register. + // + HWREG(HIB_IC) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Checks to see if the Hibernation module is already powered up. +//! +//! This function queries the control register to determine if the module is +//! already active. This function can be called at a power-on reset to help +//! determine if the reset is due to a wake from hibernation or a cold start. +//! If the Hibernation module is already active, then it does not need to be +//! re-enabled and its status can be queried immediately. +//! +//! The software application should also use the HibernateIntStatus() function +//! to read the raw interrupt status to determine the cause of the wake. The +//! HibernateDataGet() function can be used to restore state. These +//! combinations of functions can be used by the software to determine if the +//! processor is waking from hibernation and the appropriate action to take as +//! a result. +//! +//! \return Returns \b true if the module is already active, and \b false if +//! not. +// +//***************************************************************************** +unsigned int +HibernateIsActive(void) +{ + // + // Read the control register, and return true if the module is enabled. + // + return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/hibernate.h b/bsp/lm3s/driverlib/hibernate.h new file mode 100644 index 0000000000..4be5f81231 --- /dev/null +++ b/bsp/lm3s/driverlib/hibernate.h @@ -0,0 +1,130 @@ +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HIBERNATE_H__ +#define __HIBERNATE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros needed for selecting the clock source for HibernateClockSelect() +// +//***************************************************************************** +#define HIBERNATE_CLOCK_SEL_RAW 0x04 +#define HIBERNATE_CLOCK_SEL_DIV128 0x00 + +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +#define HIBERNATE_WAKE_PIN 0x10 +#define HIBERNATE_WAKE_RTC 0x08 + +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +#define HIBERNATE_LOW_BAT_DETECT 0x20 +#define HIBERNATE_LOW_BAT_ABORT 0xA0 + +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +#define HIBERNATE_INT_PIN_WAKE 0x08 +#define HIBERNATE_INT_LOW_BAT 0x04 +#define HIBERNATE_INT_RTC_MATCH_0 0x01 +#define HIBERNATE_INT_RTC_MATCH_1 0x02 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HibernateEnableExpClk(unsigned long ulHibClk); +extern void HibernateDisable(void); +extern void HibernateClockSelect(unsigned long ulClockInput); +extern void HibernateRTCEnable(void); +extern void HibernateRTCDisable(void); +extern void HibernateWakeSet(unsigned long ulWakeFlags); +extern unsigned long HibernateWakeGet(void); +extern void HibernateLowBatSet(unsigned long ulLowBatFlags); +extern unsigned long HibernateLowBatGet(void); +extern void HibernateRTCSet(unsigned long ulRTCValue); +extern unsigned long HibernateRTCGet(void); +extern void HibernateRTCMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch0Get(void); +extern void HibernateRTCMatch1Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch1Get(void); +extern void HibernateRTCTrimSet(unsigned long ulTrim); +extern unsigned long HibernateRTCTrimGet(void); +extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateRequest(void); +extern void HibernateIntEnable(unsigned long ulIntFlags); +extern void HibernateIntDisable(unsigned long ulIntFlags); +extern void HibernateIntRegister(void (*pfnHandler)(void)); +extern void HibernateIntUnregister(void); +extern unsigned long HibernateIntStatus(tBoolean bMasked); +extern void HibernateIntClear(unsigned long ulIntFlags); +extern unsigned int HibernateIsActive(void); + +//***************************************************************************** +// +// Several Hibernate module APIs have been renamed, with the original function +// name being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define HibernateEnable(a) \ + HibernateEnableExpClk(a, SysCtlClockGet()) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HIBERNATE_H__ diff --git a/bsp/lm3s/driverlib/i2c.c b/bsp/lm3s/driverlib/i2c.c new file mode 100644 index 0000000000..eadeec1c97 --- /dev/null +++ b/bsp/lm3s/driverlib/i2c.c @@ -0,0 +1,1109 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2c.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/i2c.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulI2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master, and will have enabled the I2C Master block. +//! +//! If the parameter \e bFast is \b true, then the master block will be set up +//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data +//! at 100 kbps. +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original I2CMasterInit() API and performs the +//! same actions. A macro is provided in i2c.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast) +{ + unsigned long ulSCLFreq; + unsigned long ulTPR; + + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ulBase); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ulSCLFreq = 400000; + } + else + { + ulSCLFreq = 100000; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ulTPR = ((ulI2CClk + (2 * 10 * ulSCLFreq) - 1) / (2 * 10 * ulSCLFreq)) - 1; + HWREG(ulBase + I2C_O_MTPR) = ulTPR; +} + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address and have enabled the I2C Slave block. +//! +//! The parameter \e ucSlaveAddr is the value that will be compared against the +//! slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ulBase); + + // + // Set up the slave address. + // + HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr; +} + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This will enable operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Enable the master block. + // + HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE; +} + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This will enable operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Enable the clock to the slave block. + // + HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |= + I2C_MCR_SFE; + + // + // Enable the slave. + // + HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This will disable operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Disable the master block. + // + HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE); +} + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This will disable operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Disable the slave. + // + HWREG(ulBase + I2C_O_SCSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &= + ~(I2C_MCR_SFE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! This sets the handler to be called when an I2C interrupt occurs. This will +//! enable the global interrupt in the interrupt controller; specific I2C +//! interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Determine the interrupt number based on the I2C port. + // + ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1; + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function will clear the handler to be called when an I2C interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Determine the interrupt number based on the I2C port. + // + ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! Enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) = 1; +} + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! Enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Enables individual I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt +//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt +//! - \b I2C_SLAVE_INT_DATA - Data interrupt +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! Disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! Disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Disables individual I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CSlaveIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Master module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +tBoolean +I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Slave module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +tBoolean +I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_O_SMIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_O_SRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Slave module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CSlaveIntEnableEx(). +// +//***************************************************************************** +unsigned long +I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + // + // Workaround for I2C slave masked interrupt status register errata + // (7.1) for Dustdevil Rev A0 devices. + // + if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0) + { + ulValue = HWREG(ulBase + I2C_O_SRIS); + return(ulValue & HWREG(ulBase + I2C_O_SIMR)); + } + else + { + return(HWREG(ulBase + I2C_O_SMIS)); + } + } + else + { + return(HWREG(ulBase + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Stellaris + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2CSlaveIntEnableEx(). +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_O_SICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Sets the address that the I2C Master will place on the bus. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucSlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address will indicate that the I2C Master is initiating a +//! read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, + tBoolean bReceive) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +tBoolean +I2CMasterBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Return the busy status. + // + if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +tBoolean +I2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Return the bus busy status. + // + if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ulCmd command to be issued to the I2C Master module +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The \e ucCmd parameter can be one of the following +//! values: +//! +//! - \b I2C_MASTER_CMD_SINGLE_SEND +//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \b I2C_MASTER_CMD_BURST_SEND_START +//! - \b I2C_MASTER_CMD_BURST_SEND_CONT +//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // + // Send the command. + // + HWREG(ulBase + I2C_O_MCS) = ulCmd; +} + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, +//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or +//! \b I2C_MASTER_ERR_ARB_LOST. +// +//***************************************************************************** +unsigned long +I2CMasterErr(unsigned long ulBase) +{ + unsigned long ulErr; + + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Get the raw error state + // + ulErr = HWREG(ulBase + I2C_O_MCS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ulErr & I2C_MCS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ulErr & I2C_MCS_ERROR) + { + return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase is the base address of the I2C Master module. +//! \param ucData data to be transmitted from the I2C Master +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Write the byte. + // + HWREG(ulBase + I2C_O_MDR) = ucData; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase is the base address of the I2C Master module. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +unsigned long +I2CMasterDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE)); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function will return the action requested from a master, if any. +//! Possible values are: +//! +//! - \b I2C_SLAVE_ACT_NONE +//! - \b I2C_SLAVE_ACT_RREQ +//! - \b I2C_SLAVE_ACT_TREQ +//! - \b I2C_SLAVE_ACT_RREQ_FBR +//! +//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been +//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that +//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ +//! to indicate that an I2C master has requested that the I2C Slave module send +//! data, and \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent +//! data to the I2C slave and the first byte following the slave's own address +//! has been received. +// +//***************************************************************************** +unsigned long +I2CSlaveStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Return the slave status. + // + return(HWREG(ulBase + I2C_O_SCSR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! \param ucData data to be transmitted from the I2C Slave +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Write the byte. + // + HWREG(ulBase + I2C_O_SDR) = ucData; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ulBase is the base address of the I2C Slave module. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! unsigned long. +// +//***************************************************************************** +unsigned long +I2CSlaveDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE)); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_O_SDR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/i2c.h b/bsp/lm3s/driverlib/i2c.h new file mode 100644 index 0000000000..d31b190d56 --- /dev/null +++ b/bsp/lm3s/driverlib/i2c.h @@ -0,0 +1,170 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2CSlaveIntDisableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase, + tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +//***************************************************************************** +// +// Several I2C APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define I2CMasterInit(a, b) \ + I2CMasterInitExpClk(a, SysCtlClockGet(), b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/bsp/lm3s/driverlib/i2s.c b/bsp/lm3s/driverlib/i2s.c new file mode 100644 index 0000000000..fd530b3651 --- /dev/null +++ b/bsp/lm3s/driverlib/i2s.c @@ -0,0 +1,1139 @@ +//***************************************************************************** +// +// i2s.c - Driver for the I2S controller. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2s_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2s.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/i2s.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +//! Enables the I2S transmit module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function enables the transmit module for operation. The module +//! should be enabled after configuration. When the module is disabled, +//! no data or clocks will be generated on the I2S signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Enable the tx FIFO service request. + // + HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN; +} + +//***************************************************************************** +// +//! Disables the I2S transmit module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function disables the transmit module for operation. The module +//! should be disabled before configuration. When the module is disabled, +//! no data or clocks will be generated on the I2S signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN; +} + +//***************************************************************************** +// +//! Writes data samples to the I2S transmit FIFO with blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param ulData is the single or dual channel I2S data. +//! +//! This function writes a single channel sample or combined left-right +//! samples to the I2S transmit FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2STxConfigSet(). +//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter +//! contains either the left or right sample. The left and right sample +//! alternate with each write to the FIFO, left sample first. If the transmit +//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the +//! \e ulData parameter contains both the left and right samples. If the +//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter +//! contains the single channel sample. +//! +//! For the compact modes, both the left and right samples are written at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no room in the transmit FIFO, then this function will wait +//! in a polling loop until the data can be written. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Wait until there is space. + // + while(HWREG(ulBase + I2S_O_TXLEV) >= 16) + { + } + + // + // Write the data to the I2S. + // + HWREG(ulBase + I2S_O_TXFIFO) = ulData; +} + +//***************************************************************************** +// +//! Writes data samples to the I2S transmit FIFO without blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param ulData is the single or dual channel I2S data. +//! +//! This function writes a single channel sample or combined left-right +//! samples to the I2S transmit FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2STxConfigSet(). +//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter +//! contains either the left or right sample. The left and right sample +//! alternate with each write to the FIFO, left sample first. If the transmit +//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the +//! \e ulData parameter contains both the left and right samples. If the +//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter +//! contains the single channel sample. +//! +//! For the compact modes, both the left and right samples are written at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no room in the transmit FIFO, then this function will return +//! immediately without writing any data to the FIFO. +//! +//! \return The number of elements written to the I2S transmit FIFO (1 or 0). +// +//***************************************************************************** +long +I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Check for space to write. + // + if(HWREG(ulBase + I2S_O_TXLEV) < 16) + { + HWREG(ulBase + I2S_O_TXFIFO) = ulData; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Configures the I2S transmit module. +//! +//! \param ulBase is the I2S module base address. +//! \param ulConfig is the logical OR of the configuration options. +//! +//! This function is used to configure the options for the I2S transmit +//! channel. The parameter \e ulConfig is the logical OR of the following +//! options: +//! +//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. +//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether +//! the I2S transmitter is the clock master or slave. +//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per sample. +//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per word that are transferred on the data +//! line. +//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether +//! the module transmits zeroes or repeats the last sample when the FIFO is +//! empty. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK | + I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK | + I2S_CONFIG_SAMPLE_SIZE_MASK | + I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig); + + // + // Check to see if a compact mode is used. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8) + { + // + // If compact 8 mode is used, then need to adjust some bits + // before writing the config register. Also set the FIFO + // config register for 8 bit compact samples. + // + ulConfig &= ~I2S_CONFIG_MODE_MONO; + HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS; + } + else + { + // + // If compact 8 mode is not used, then set the FIFO config + // register for 16 bit. This is okay if a compact mode is + // not used. + // + HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; + } + + // + // Write the configuration register. Since all the fields are + // specified by the configuration parameter, it is not necessary + // to do a read-modify-write. + // + HWREG(ulBase + I2S_O_TXCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which a service request is generated. +//! +//! \param ulBase is the I2S module base address. +//! \param ulLevel is the FIFO service request limit. +//! +//! This function is used to set the transmit FIFO fullness level at which +//! a service request will occur. The service request is used to generate +//! an interrupt or a DMA transfer request. The transmit FIFO will +//! generate a service request when the number of items in the FIFO is +//! less than the level specified in the \e ulLevel parameter. For example, +//! if \e ulLevel is 8, then a service request will be generated when +//! there are less than 8 samples remaining in the transmit FIFO. +//! +//! For the purposes of counting the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono +//! mode is used, internally the mono sample is still treated as a sample +//! pair, so a single mono sample counts as 2. Since the FIFO always deals +//! with sample pairs, the level must be an even number from 0 to 16. The +//! maximum value is 16, which will cause a service request when there +//! is any room in the FIFO. The minimum value is 0, which disables the +//! service request. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT(ulLevel <= 16); + + // + // Write the FIFO limit + // + HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel; +} + +//***************************************************************************** +// +//! Gets the current setting of the FIFO service request level. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the value of the transmit FIFO service +//! request level. This value is set using the I2STxFIFOLimitSet() +//! function. +//! +//! \return Returns the current value of the FIFO service request limit. +// +//***************************************************************************** +unsigned long +I2STxFIFOLimitGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the FIFO limit + // + return(HWREG(ulBase + I2S_O_TXLIMIT)); +} + +//***************************************************************************** +// +//! Gets the number of samples in the transmit FIFO. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the number of samples in the transmit +//! FIFO. For the purposes of measuring the FIFO level, a left-right sample +//! pair counts as 2, whether the mode is dual or compact stereo. When mono +//! mode is used, internally the mono sample is still treated as a sample +//! pair, so a single mono sample counts as 2. Since the FIFO always deals +//! with sample pairs, normally the level will be an even number from 0 to +//! 16. If dual stereo mode is used and only the left sample has been +//! written without the matching right sample, then the FIFO level will be an +//! odd value. If the FIFO level is odd, it indicates a left-right sample +//! mismatch. +//! +//! \return Returns the number of samples in the transmit FIFO, which will +//! normally be an even number. +// +//***************************************************************************** +unsigned long +I2STxFIFOLevelGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the transmit FIFO level. + // + return(HWREG(ulBase + I2S_O_TXLEV)); +} + +//***************************************************************************** +// +//! Enables the I2S receive module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function enables the receive module for operation. The module +//! should be enabled after configuration. When the module is disabled, +//! no data will be clocked in regardless of the signals on the I2S interface. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Enable the tx FIFO service request. + // + HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN; +} + +//***************************************************************************** +// +//! Disables the I2S receive module for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function disables the receive module for operation. The module +//! should be disabled before configuration. When the module is disabled, +//! no data will be clocked in regardless of the signals on the I2S interface. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN; +} + +//***************************************************************************** +// +//! Reads data samples from the I2S receive FIFO with blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param pulData points to storage for the returned I2S sample data. +//! +//! This function reads a single channel sample or combined left-right +//! samples from the I2S receive FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2SRxConfigSet(). +//! If the receive mode is I2S_MODE_DUAL_STEREO then the returned value +//! contains either the left or right sample. The left and right sample +//! alternate with each read from the FIFO, left sample first. If the receive +//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the +//! returned data contains both the left and right samples. If the +//! receive mode is I2S_MODE_SINGLE_MONO then the returned data +//! contains the single channel sample. +//! +//! For the compact modes, both the left and right samples are read at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no data in the receive FIFO, then this function will wait +//! in a polling loop until data is available. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Wait until there is data available. + // + while(HWREG(ulBase + I2S_O_RXLEV) == 0) + { + } + + // + // Read data from the I2S receive FIFO. + // + *pulData = HWREG(ulBase + I2S_O_RXFIFO); +} + +//***************************************************************************** +// +//! Reads data samples from the I2S receive FIFO without blocking. +//! +//! \param ulBase is the I2S module base address. +//! \param pulData points to storage for the returned I2S sample data. +//! +//! This function reads a single channel sample or combined left-right +//! samples from the I2S receive FIFO. The format of the sample is determined +//! by the configuration that was used with the function I2SRxConfigSet(). +//! If the receive mode is I2S_MODE_DUAL_STEREO then the received data +//! contains either the left or right sample. The left and right sample +//! alternate with each read from the FIFO, left sample first. If the receive +//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the +//! received data contains both the left and right samples. If the +//! receive mode is I2S_MODE_SINGLE_MONO then the received data +//! contains the single channel sample. +//! +//! For the compact modes, both the left and right samples are read at +//! the same time. If 16-bit compact mode is used, then the least significant +//! 16 bits contain the left sample, and the most significant 16 bits contain +//! the right sample. If 8-bit compact mode is used, then the lower 8 bits +//! contain the left sample, and the next 8 bits contain the right sample, +//! with the upper 16 bits unused. +//! +//! If there is no data in the receive FIFO, then this function will return +//! immediately without reading any data from the FIFO. +//! +//! \return The number of elements read from the I2S receive FIFO (1 or 0). +// +//***************************************************************************** +long +I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Check for available samples. + // + if(HWREG(ulBase + I2S_O_RXLEV) != 0) + { + *pulData = HWREG(ulBase + I2S_O_RXFIFO); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Configures the I2S receive module. +//! +//! \param ulBase is the I2S module base address. +//! \param ulConfig is the logical OR of the configuration options. +//! +//! This function is used to configure the options for the I2S receive +//! channel. The parameter \e ulConfig is the logical OR of the following +//! options: +//! +//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. +//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether +//! the I2S receiver is the clock master or slave. +//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per sample. +//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per word that are transferred on the data +//! line. +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK | + I2S_CONFIG_CLK_MASK | I2S_CONFIG_SAMPLE_SIZE_MASK | + I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig); + + // + // Clear out any prior config of the RX FIFO config register. + // + HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; + + // + // If mono mode is used, then the FMM bit needs to be set. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO) + { + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; + } + + // + // If a compact mode is used, then the CSS bit needs to be set. + // + else if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8) + { + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; + } + + // + // The "mono" bits needs to be removed from the configuration word + // prior to writing to hardware, because the RX configuration register + // does not actually use these bits. + // + ulConfig &= ~I2S_CONFIG_MODE_MONO; + + // + // Write the configuration register. Since all the fields are + // specified by the configuration parameter, it is not necessary + // to do a read-modify-write. + // + HWREG(ulBase + I2S_O_RXCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which a service request is generated. +//! +//! \param ulBase is the I2S module base address. +//! \param ulLevel is the FIFO service request limit. +//! +//! This function is used to set the receive FIFO fullness level at which +//! a service request will occur. The service request is used to generate +//! an interrupt or a DMA transfer request. The receive FIFO will +//! generate a service request when the number of items in the FIFO is +//! greater than the level specified in the \e ulLevel parameter. For example, +//! if \e ulLevel is 4, then a service request will be generated when +//! there are more than 4 samples available in the receive FIFO. +//! +//! For the purposes of counting the FIFO level, a left-right sample pair +//! counts as 2, whether the mode is dual or compact stereo. When mono +//! mode is used, internally the mono sample is still treated as a sample +//! pair, so a single mono sample counts as 2. Since the FIFO always deals +//! with sample pairs, the level must be an even number from 0 to 16. The +//! minimum value is 0, which will cause a service request when there +//! is any data available in the FIFO. The maximum value is 16, which +//! disables the service request (because there cannot be more than 16 +//! items in the FIFO). +//! +//! \return None. +// +//***************************************************************************** +void +I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT(ulLevel <= 16); + + // + // Write the FIFO limit + // + HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel; +} + +//***************************************************************************** +// +//! Gets the current setting of the FIFO service request level. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the value of the receive FIFO service +//! request level. This value is set using the I2SRxFIFOLimitSet() +//! function. +//! +//! \return Returns the current value of the FIFO service request limit. +// +//***************************************************************************** +unsigned long +I2SRxFIFOLimitGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the FIFO limit. The lower bit is masked + // because it always reads as 1, and has no meaning. + // + return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE); +} + +//***************************************************************************** +// +//! Gets the number of samples in the receive FIFO. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function is used to get the number of samples in the receive +//! FIFO. For the purposes of measuring the FIFO level, a left-right sample +//! pair counts as 2, whether the mode is dual or compact stereo. When mono +//! mode is used, internally the mono sample is still treated as a sample +//! pair, so a single mono sample counts as 2. Since the FIFO always deals +//! with sample pairs, normally the level will be an even number from 0 to +//! 16. If dual stereo mode is used and only the left sample has been +//! read without reading the matching right sample, then the FIFO level will +//! be an odd value. If the FIFO level is odd, it indicates a left-right +//! sample mismatch. +//! +//! \return Returns the number of samples in the transmit FIFO, which will +//! normally be an even number. +// +//***************************************************************************** +unsigned long +I2SRxFIFOLevelGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Read and return the receive FIFO level. + // + return(HWREG(ulBase + I2S_O_RXLEV)); +} + +//***************************************************************************** +// +//! Enables the I2S transmit and receive modules for operation. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function simultaneously enables the transmit and receive modules for +//! operation, providing a synchronized SCLK and LRCLK. The module should be +//! enabled after configuration. When the module is disabled, no data or +//! clocks will be generated on the I2S signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxRxEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Enable the Tx FIFO service request. + // + HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM; + + // + // Enable the Rx FIFO service request. + // + HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM; + + // + // Enable the transmit and receive modules. + // + HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN; +} + +//***************************************************************************** +// +//! Disables the I2S transmit and receive modules. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function simultaneously disables the transmit and receive modules. +//! When the module is disabled, no data or clocks will be generated on the I2S +//! signals. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxRxDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Disable the transmit and receive modules. + // + HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN); +} + +//***************************************************************************** +// +//! Configures the I2S transmit and receive modules. +//! +//! \param ulBase is the I2S module base address. +//! \param ulConfig is the logical OR of the configuration options. +//! +//! This function is used to configure the options for the I2S transmit and +//! receive channels with identical parameters. The parameter \e ulConfig is +//! the logical OR of the following options: +//! +//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format, +//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or +//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format. +//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock. +//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo, +//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode, +//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or +//! \b I2S_CONFIG_MODE_MONO for single channel mono format. +//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether +//! the I2S transmitter is the clock master or slave. +//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per sample. +//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8 +//! to select the number of bits per word that are transferred on the data +//! line. +//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether +//! the module transmits zeroes or repeats the last sample when the FIFO is +//! empty. +//! +//! \return None. +// +//***************************************************************************** +void +I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK | + I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK | + I2S_CONFIG_SAMPLE_SIZE_MASK | + I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig); + + // + // Clear out any prior configuration of the FIFO config registers. + // + HWREG(ulBase + I2S_O_TXFIFOCFG) = 0; + HWREG(ulBase + I2S_O_RXFIFOCFG) = 0; + + // + // If mono mode is used, then the FMM bit needs to be set. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO) + { + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM; + ulConfig &= ~(I2S_CONFIG_MODE_MONO); + } + + // + // If a compact mode is used, then the CSS bit needs to be set. + // + if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8) + { + HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS; + HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS; + } + + // + // Write the configuration register. Since all the fields are specified by + // the configuration parameter, it is not necessary to do a + // read-modify-write. + // + HWREG(ulBase + I2S_O_TXCFG) = ulConfig; + HWREG(ulBase + I2S_O_RXCFG) = ulConfig; +} + +//***************************************************************************** +// +//! Selects the source of the master clock, internal or external. +//! +//! \param ulBase is the I2S module base address. +//! \param ulMClock is the logical OR of the master clock configuration +//! choices. +//! +//! This function selects whether the master clock is sourced from the device +//! internal PLL, or comes from an external pin. The I2S serial bit clock +//! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master +//! clock. The transmit and receive modules can be configured independently. +//! The \e ulMClock parameter is chosen from the following: +//! +//! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT +//! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT +//! +//! \return Returns None. +// +//***************************************************************************** +void +I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock) +{ + unsigned long ulConfig; + + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulMClock & (I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT)) == ulMClock); + + // + // Set the clock selection bits in the configuation word. + // + ulConfig = HWREG(ulBase + I2S_O_CFG) & + ~(I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT); + HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock; +} + +//***************************************************************************** +// +//! Enables I2S interrupt sources. +//! +//! \param ulBase is the I2S module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the specified I2S sources to generate interrupts. +//! The \e ulIntFlags parameter can be the logical OR of any of the following +//! values: +//! +//! - \b I2S_INT_RXERR for receive errors +//! - \b I2S_INT_RXREQ for receive FIFO service requests +//! - \b I2S_INT_TXERR for transmit errors +//! - \b I2S_INT_TXREQ for transmit FIFO service requests +//! +//! \return Returns None. +// +//***************************************************************************** +void +I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ | + I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + I2S_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables I2S interrupt sources. +//! +//! \param ulBase is the I2S module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the specified I2S sources for interrupt +//! generation. The \e ulIntFlags parameter can be the logical OR +//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ, +//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. +//! +//! \return Returns None. +// +//***************************************************************************** +void +I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ | + I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags; +} + +//***************************************************************************** +// +//! Gets the I2S interrupt status. +//! +//! \param ulBase is the I2S module base address. +//! \param bMasked is set \b true to get the masked interrupt status, or +//! \b false to get the raw interrupt status. +//! +//! This function returns the I2S interrupt status. It can return either +//! the raw or masked interrupt status. +//! +//! \return Returns the masked or raw I2S interrupt status, as a bit field +//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ, +//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ +// +//***************************************************************************** +unsigned long +I2SIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + I2S_O_MIS)); + } + else + { + return(HWREG(ulBase + I2S_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears pending I2S interrupt sources. +//! +//! \param ulBase is the I2S module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified pending I2S interrupts. This must +//! be done in the interrupt handler to keep the handler from being called +//! again immediately upon exit. The \e ulIntFlags parameter can be the +//! logical OR of any of the following values: \b I2S_INT_RXERR, +//! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return Returns None. +// +//***************************************************************************** +void +I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ | + I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + I2S_O_IC) = ulIntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2S controller. +//! +//! \param ulBase is the I2S module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This sets and enables the handler to be called when the I2S controller +//! generates an interrupt. Specific I2S interrupts must still be enabled +//! with the I2SIntEnable() function. It is the responsibility of the +//! interrupt handler to clear any pending interrupts with I2SIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(INT_I2S0, pfnHandler); + + // + // Enable the I2S interface interrupt. + // + IntEnable(INT_I2S0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2S controller. +//! +//! \param ulBase is the I2S module base address. +//! +//! This function will disable and clear the handler to be called when the +//! I2S interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2SIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2S0_BASE); + + // + // Disable the I2S interface interrupt. + // + IntDisable(INT_I2S0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_I2S0); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/i2s.h b/bsp/lm3s/driverlib/i2s.h new file mode 100644 index 0000000000..93cc2e6fe0 --- /dev/null +++ b/bsp/lm3s/driverlib/i2s.h @@ -0,0 +1,157 @@ +//***************************************************************************** +// +// i2s.h - Prototypes and macros for the I2S controller. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to I2STxConfigSet() and I2SRxConfigSet() +// +//***************************************************************************** +#define I2S_CONFIG_FORMAT_MASK 0x3C000000 // JST, DLY, SCP, LRP +#define I2S_CONFIG_FORMAT_I2S 0x14000000 // !JST, DLY, !SCP, LRP +#define I2S_CONFIG_FORMAT_LEFT_JUST \ + 0x00000000 // !JST, !DLY, !SCP, !LRP +#define I2S_CONFIG_FORMAT_RIGHT_JUST \ + 0x20000000 // JST, !DLY, !SCP, !LRP + +#define I2S_CONFIG_SCLK_INVERT 0x08000000 + +#define I2S_CONFIG_MODE_MASK 0x03000000 +#define I2S_CONFIG_MODE_DUAL 0x00000000 +#define I2S_CONFIG_MODE_COMPACT_16 \ + 0x01000000 +#define I2S_CONFIG_MODE_COMPACT_8 \ + 0x03000000 +#define I2S_CONFIG_MODE_MONO 0x02000000 + +#define I2S_CONFIG_EMPTY_MASK 0x00800000 +#define I2S_CONFIG_EMPTY_ZERO 0x00000000 +#define I2S_CONFIG_EMPTY_REPEAT 0x00800000 + +#define I2S_CONFIG_CLK_MASK 0x00400000 +#define I2S_CONFIG_CLK_MASTER 0x00400000 +#define I2S_CONFIG_CLK_SLAVE 0x00000000 + +#define I2S_CONFIG_SAMPLE_SIZE_MASK \ + 0x0000FC00 +#define I2S_CONFIG_SAMPLE_SIZE_32 \ + 0x00007C00 +#define I2S_CONFIG_SAMPLE_SIZE_24 \ + 0x00005C00 +#define I2S_CONFIG_SAMPLE_SIZE_20 \ + 0x00004C00 +#define I2S_CONFIG_SAMPLE_SIZE_16 \ + 0x00003C00 +#define I2S_CONFIG_SAMPLE_SIZE_8 \ + 0x00001C00 + +#define I2S_CONFIG_WIRE_SIZE_MASK \ + 0x000003F0 +#define I2S_CONFIG_WIRE_SIZE_32 0x000001F0 +#define I2S_CONFIG_WIRE_SIZE_24 0x00000170 +#define I2S_CONFIG_WIRE_SIZE_20 0x00000130 +#define I2S_CONFIG_WIRE_SIZE_16 0x000000F0 +#define I2S_CONFIG_WIRE_SIZE_8 0x00000070 + +//***************************************************************************** +// +// Values that can be passed to I2SMasterClockSelect() +// +//***************************************************************************** +#define I2S_TX_MCLK_EXT 0x00000010 +#define I2S_TX_MCLK_INT 0x00000000 +#define I2S_RX_MCLK_EXT 0x00000020 +#define I2S_RX_MCLK_INT 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to I2SIntEnable(), I2SIntDisable(), and +// I2SIntClear() +// +//***************************************************************************** +#define I2S_INT_RXERR 0x00000020 +#define I2S_INT_RXREQ 0x00000010 +#define I2S_INT_TXERR 0x00000002 +#define I2S_INT_TXREQ 0x00000001 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void I2STxEnable(unsigned long ulBase); +extern void I2STxDisable(unsigned long ulBase); +extern void I2STxDataPut(unsigned long ulBase, unsigned long ulData); +extern long I2STxDataPutNonBlocking(unsigned long ulBase, + unsigned long ulData); +extern void I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern void I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel); +extern unsigned long I2STxFIFOLimitGet(unsigned long ulBase); +extern unsigned long I2STxFIFOLevelGet(unsigned long ulBase); +extern void I2SRxEnable(unsigned long ulBase); +extern void I2SRxDisable(unsigned long ulBase); +extern void I2SRxDataGet(unsigned long ulBase, unsigned long *pulData); +extern long I2SRxDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern void I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel); +extern unsigned long I2SRxFIFOLimitGet(unsigned long ulBase); +extern unsigned long I2SRxFIFOLevelGet(unsigned long ulBase); +extern void I2STxRxEnable(unsigned long ulBase); +extern void I2STxRxDisable(unsigned long ulBase); +extern void I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern void I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock); +extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long I2SIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void I2SIntUnregister(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2S_H__ diff --git a/bsp/lm3s/driverlib/interrupt.c b/bsp/lm3s/driverlib/interrupt.c new file mode 100644 index 0000000000..f1cd137535 --- /dev/null +++ b/bsp/lm3s/driverlib/interrupt.c @@ -0,0 +1,550 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/cpu.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +static const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulRegs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +#if defined(ewarm) +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#elif defined(sourcerygxx) +static __attribute__((section(".cs3.region-head.ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#else +static __attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise NVIC will not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts; +//! some tool chains, such as the evaluation version of RV-MDK, do not support +//! linker scripts and therefore will not produce a valid executable. See the +//! discussion of compile-time versus run-time interrupt handler registration +//! in the introduction to this chapter. +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long ulIdx, ulValue; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + ulValue = HWREG(NVIC_VTABLE); + for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) + { + g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) + + ulValue); + } + + // + // Point NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = pfnHandler; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; +} + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Stellaris family, three bits are available for hardware interrupt +//! prioritization and therefore priority grouping values of three through +//! seven have the same effect. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. The remaining bits can be +//! used to sub-prioritize the interrupt sources, and may be used by the +//! hardware priority mechanism on a future part. This arrangement allows +//! priorities to migrate to different NVIC implementations without changing +//! the gross prioritization of the interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ulInterrupt >= 16) && (ulInterrupt <= 47)) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16); + } + else if(ulInterrupt >= 48) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ulInterrupt >= 16) && (ulInterrupt <= 47)) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16); + } + else if(ulInterrupt >= 48) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48); + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/interrupt.h b/bsp/lm3s/driverlib/interrupt.h new file mode 100644 index 0000000000..53fdfb403c --- /dev/null +++ b/bsp/lm3s/driverlib/interrupt.h @@ -0,0 +1,76 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean IntMasterEnable(void); +extern tBoolean IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/bsp/lm3s/driverlib/mpu.c b/bsp/lm3s/driverlib/mpu.c new file mode 100644 index 0000000000..0500c5eb20 --- /dev/null +++ b/bsp/lm3s/driverlib/mpu.c @@ -0,0 +1,449 @@ +//***************************************************************************** +// +// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpu_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/mpu.h" + +//***************************************************************************** +// +//! Enables and configures the MPU for use. +//! +//! \param ulMPUConfig is the logical OR of the possible configurations. +//! +//! This function enables the Cortex-M3 memory protection unit. It also +//! configures the default behavior when in privileged mode and while +//! handling a hard fault or NMI. Prior to enabling the MPU, at least one +//! region must be set by calling MPURegionSet() or else by enabling the +//! default region for privileged mode by passing the +//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable(). +//! Once the MPU is enabled, a memory management fault will be generated +//! for any memory access violations. +//! +//! The \e ulMPUConfig parameter should be the logical OR of any of the +//! following: +//! +//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in +//! privileged mode and when no other regions are defined. If this option +//! is not enabled, then there must be at least one valid region already +//! defined when the MPU is enabled. +//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI +//! exception handler. If this option is not enabled, then the MPU is +//! disabled while in one of these exception handlers and the default +//! memory map is applied. +//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, +//! no default memory map is provided in privileged mode, and the MPU will +//! not be enabled in the fault handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUEnable(unsigned long ulMPUConfig) +{ + // + // Check the arguments. + // + ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT | + MPU_CONFIG_HARDFLT_NMI))); + + // + // Set the MPU control bits according to the flags passed by the user, + // and also set the enable bit. + // + HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the MPU for use. +//! +//! This function disables the Cortex-M3 memory protection unit. When the +//! MPU is disabled, the default memory map is used and memory management +//! faults are not generated. +//! +//! \return None. +// +//***************************************************************************** +void +MPUDisable(void) +{ + // + // Turn off the MPU enable bit. + // + HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Gets the count of regions supported by the MPU. +//! +//! This function is used to get the number of regions that are supported by +//! the MPU. This is the total number that are supported, including regions +//! that are already programmed. +//! +//! \return The number of memory protection regions that are available +//! for programming using MPURegionSet(). +// +//***************************************************************************** +unsigned long +MPURegionCountGet(void) +{ + // + // Read the DREGION field of the MPU type register, and mask off + // the bits of interest to get the count of regions. + // + return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) + >> NVIC_MPU_TYPE_DREGION_S); +} + +//***************************************************************************** +// +//! Enables a specific region. +//! +//! \param ulRegion is the region number to enable. +//! +//! This function is used to enable a memory protection region. The region +//! should already be set up with the MPURegionSet() function. Once enabled, +//! the memory protection rules of the region will be applied and access +//! violations will cause a memory management fault. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionEnable(unsigned long ulRegion) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + + // + // Select the region to modify. + // + HWREG(NVIC_MPU_NUMBER) = ulRegion; + + // + // Modify the enable bit in the region attributes. + // + HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE; +} + +//***************************************************************************** +// +//! Disables a specific region. +//! +//! \param ulRegion is the region number to disable. +//! +//! This function is used to disable a previously enabled memory protection +//! region. The region will remain configured if it is not overwritten with +//! another call to MPURegionSet(), and can be enabled again by calling +//! MPURegionEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionDisable(unsigned long ulRegion) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + + // + // Select the region to modify. + // + HWREG(NVIC_MPU_NUMBER) = ulRegion; + + // + // Modify the enable bit in the region attributes. + // + HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE; +} + +//***************************************************************************** +// +//! Sets up the access rules for a specific region. +//! +//! \param ulRegion is the region number to set up. +//! \param ulAddr is the base address of the region. It must be aligned +//! according to the size of the region specified in ulFlags. +//! \param ulFlags is a set of flags to define the attributes of the region. +//! +//! This function sets up the protection rules for a region. The region has +//! a base address and a set of attributes including the size, which must +//! be a power of 2. The base address parameter, \e ulAddr, must be aligned +//! according to the size. +//! +//! The \e ulFlags parameter is the logical OR of all of the attributes +//! of the region. It is a combination of choices for region size, +//! execute permission, read/write permissions, disabled sub-regions, +//! and a flag to determine if the region is enabled. +//! +//! The size flag determines the size of a region, and must be one of the +//! following: +//! +//! - \b MPU_RGN_SIZE_32B +//! - \b MPU_RGN_SIZE_64B +//! - \b MPU_RGN_SIZE_128B +//! - \b MPU_RGN_SIZE_256B +//! - \b MPU_RGN_SIZE_512B +//! - \b MPU_RGN_SIZE_1K +//! - \b MPU_RGN_SIZE_2K +//! - \b MPU_RGN_SIZE_4K +//! - \b MPU_RGN_SIZE_8K +//! - \b MPU_RGN_SIZE_16K +//! - \b MPU_RGN_SIZE_32K +//! - \b MPU_RGN_SIZE_64K +//! - \b MPU_RGN_SIZE_128K +//! - \b MPU_RGN_SIZE_256K +//! - \b MPU_RGN_SIZE_512K +//! - \b MPU_RGN_SIZE_1M +//! - \b MPU_RGN_SIZE_2M +//! - \b MPU_RGN_SIZE_4M +//! - \b MPU_RGN_SIZE_8M +//! - \b MPU_RGN_SIZE_16M +//! - \b MPU_RGN_SIZE_32M +//! - \b MPU_RGN_SIZE_64M +//! - \b MPU_RGN_SIZE_128M +//! - \b MPU_RGN_SIZE_256M +//! - \b MPU_RGN_SIZE_512M +//! - \b MPU_RGN_SIZE_1G +//! - \b MPU_RGN_SIZE_2G +//! - \b MPU_RGN_SIZE_4G +//! +//! The execute permission flag must be one of the following: +//! +//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code +//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code +//! +//! The read/write access permissions are applied separately for the +//! privileged and user modes. The read/write access flags must be one +//! of the following: +//! +//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode +//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access +//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only +//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write +//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access +//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only +//! +//! The region is automatically divided into 8 equally-sized sub-regions by +//! the MPU. Sub-regions can only be used in regions of size 256 bytes +//! or larger. Any of these 8 sub-regions can be disabled. This allows +//! for creation of ``holes'' in a region which can be left open, or overlaid +//! by another region with different attributes. Any of the 8 sub-regions +//! can be disabled with a logical OR of any of the following flags: +//! +//! - \b MPU_SUB_RGN_DISABLE_0 +//! - \b MPU_SUB_RGN_DISABLE_1 +//! - \b MPU_SUB_RGN_DISABLE_2 +//! - \b MPU_SUB_RGN_DISABLE_3 +//! - \b MPU_SUB_RGN_DISABLE_4 +//! - \b MPU_SUB_RGN_DISABLE_5 +//! - \b MPU_SUB_RGN_DISABLE_6 +//! - \b MPU_SUB_RGN_DISABLE_7 +//! +//! Finally, the region can be initially enabled or disabled with one of +//! the following flags: +//! +//! - \b MPU_RGN_ENABLE +//! - \b MPU_RGN_DISABLE +//! +//! As an example, to set a region with the following attributes: size of +//! 32 KB, execution enabled, read-only for both privileged and user, one +//! sub-region disabled, and initially enabled; the \e ulFlags parameter would +//! have the following value: +//! +//! +//! (MPU_RG_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO | +//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) +//! +//! +//! \note This function will write to multiple registers and is not protected +//! from interrupts. It is possible that an interrupt which accesses a +//! region may occur while that region is in the process of being changed. +//! The safest way to handle this is to disable a region before changing it. +//! Refer to the discussion of this in the API Detailed Description section. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1)) + == ulAddr); + + // + // Program the base address, use the region field to select the + // region at the same time. + // + HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID; + + // + // Program the region attributes. Set the TEX field and the S, C, + // and B bits to fixed values that are suitable for all Stellaris + // memory. + // + HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M | + NVIC_MPU_ATTR_CACHEABLE)) | + NVIC_MPU_ATTR_SHAREABLE | + NVIC_MPU_ATTR_BUFFRABLE; +} + +//***************************************************************************** +// +//! Gets the current settings for a specific region. +//! +//! \param ulRegion is the region number to get. +//! \param pulAddr points to storage for the base address of the region. +//! \param pulFlags points to the attribute flags for the region. +//! +//! This function retrieves the configuration of a specific region. The +//! meanings and format of the parameters is the same as that of the +//! MPURegionSet() function. +//! +//! This function can be used to save the configuration of a region for +//! later use with the MPURegionSet() function. The region's enable state +//! will be preserved in the attributes that are saved. +//! +//! \return None. +// +//***************************************************************************** +void +MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, + unsigned long *pulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulRegion < 8); + ASSERT(pulAddr); + ASSERT(pulFlags); + + // + // Select the region to get. + // + HWREG(NVIC_MPU_NUMBER) = ulRegion; + + // + // Read and store the base address for the region. + // + *pulAddr = HWREG(NVIC_MPU_BASE); + + // + // Read and store the region attributes. + // + *pulFlags = HWREG(NVIC_MPU_ATTR); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the memory management fault. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! memory management fault occurs. +//! +//! This sets and enables the handler to be called when the MPU generates +//! a memory management fault due to a protection region access violation. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUIntRegister(void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + + // + // Register the interrupt handler. + // + IntRegister(FAULT_MPU, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(FAULT_MPU); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the memory management fault. +//! +//! This function will disable and clear the handler to be called when a +//! memory management fault occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +MPUIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(FAULT_MPU); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_MPU); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/mpu.h b/bsp/lm3s/driverlib/mpu.h new file mode 100644 index 0000000000..8111942726 --- /dev/null +++ b/bsp/lm3s/driverlib/mpu.h @@ -0,0 +1,150 @@ +//***************************************************************************** +// +// mpu.h - Defines and Macros for the memory protection unit. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __MPU_H__ +#define __MPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Flags that can be passed to MPUEnable. +// +//***************************************************************************** +#define MPU_CONFIG_PRIV_DEFAULT 4 +#define MPU_CONFIG_HARDFLT_NMI 2 +#define MPU_CONFIG_NONE 0 + +//***************************************************************************** +// +// Flags for the region size to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_SIZE_32B (4 << 1) +#define MPU_RGN_SIZE_64B (5 << 1) +#define MPU_RGN_SIZE_128B (6 << 1) +#define MPU_RGN_SIZE_256B (7 << 1) +#define MPU_RGN_SIZE_512B (8 << 1) + +#define MPU_RGN_SIZE_1K (9 << 1) +#define MPU_RGN_SIZE_2K (10 << 1) +#define MPU_RGN_SIZE_4K (11 << 1) +#define MPU_RGN_SIZE_8K (12 << 1) +#define MPU_RGN_SIZE_16K (13 << 1) +#define MPU_RGN_SIZE_32K (14 << 1) +#define MPU_RGN_SIZE_64K (15 << 1) +#define MPU_RGN_SIZE_128K (16 << 1) +#define MPU_RGN_SIZE_256K (17 << 1) +#define MPU_RGN_SIZE_512K (18 << 1) + +#define MPU_RGN_SIZE_1M (19 << 1) +#define MPU_RGN_SIZE_2M (20 << 1) +#define MPU_RGN_SIZE_4M (21 << 1) +#define MPU_RGN_SIZE_8M (22 << 1) +#define MPU_RGN_SIZE_16M (23 << 1) +#define MPU_RGN_SIZE_32M (24 << 1) +#define MPU_RGN_SIZE_64M (25 << 1) +#define MPU_RGN_SIZE_128M (26 << 1) +#define MPU_RGN_SIZE_256M (27 << 1) +#define MPU_RGN_SIZE_512M (28 << 1) + +#define MPU_RGN_SIZE_1G (29 << 1) +#define MPU_RGN_SIZE_2G (30 << 1) +#define MPU_RGN_SIZE_4G (31 << 1) + +//***************************************************************************** +// +// Flags for the permissions to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_PERM_EXEC 0x00000000 +#define MPU_RGN_PERM_NOEXEC 0x10000000 +#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 +#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 +#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 +#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 +#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 +#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 + +//***************************************************************************** +// +// Flags for the sub-region to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_SUB_RGN_DISABLE_0 0x00000100 +#define MPU_SUB_RGN_DISABLE_1 0x00000200 +#define MPU_SUB_RGN_DISABLE_2 0x00000400 +#define MPU_SUB_RGN_DISABLE_3 0x00000800 +#define MPU_SUB_RGN_DISABLE_4 0x00001000 +#define MPU_SUB_RGN_DISABLE_5 0x00002000 +#define MPU_SUB_RGN_DISABLE_6 0x00004000 +#define MPU_SUB_RGN_DISABLE_7 0x00008000 + +//***************************************************************************** +// +// Flags to enable or disable a region, to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_ENABLE 1 +#define MPU_RGN_DISABLE 0 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void MPUEnable(unsigned long ulMPUConfig); +extern void MPUDisable(void); +extern unsigned long MPURegionCountGet(void); +extern void MPURegionEnable(unsigned long ulRegion); +extern void MPURegionDisable(unsigned long ulRegion); +extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, + unsigned long ulFlags); +extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, + unsigned long *pulFlags); +extern void MPUIntRegister(void (*pfnHandler)(void)); +extern void MPUIntUnregister(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __MPU_H__ diff --git a/bsp/lm3s/driverlib/pin_map.h b/bsp/lm3s/driverlib/pin_map.h new file mode 100644 index 0000000000..3a226d4ef1 --- /dev/null +++ b/bsp/lm3s/driverlib/pin_map.h @@ -0,0 +1,20416 @@ +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// +// LM3S101 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S101 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB) +#define 32KHZ_PORT (GPIO_PORTB_BASE) +#define 32KHZ_PIN (GPIO_PIN_1) + +#endif // PART_LM3S101 + +//***************************************************************************** +// +// LM3S102 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S102 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB) +#define 32KHZ_PORT (GPIO_PORTB_BASE) +#define 32KHZ_PIN (GPIO_PIN_1) + +#endif // PART_LM3S102 + +//***************************************************************************** +// +// LM3S300 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S300 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S300 + +//***************************************************************************** +// +// LM3S301 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S301 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S301 + +//***************************************************************************** +// +// LM3S308 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S308 + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S308 + +//***************************************************************************** +// +// LM3S310 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S310 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S310 + +//***************************************************************************** +// +// LM3S315 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S315 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S315 + +//***************************************************************************** +// +// LM3S316 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S316 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S316 + +//***************************************************************************** +// +// LM3S317 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S317 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S317 + +//***************************************************************************** +// +// LM3S328 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S328 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S328 + +//***************************************************************************** +// +// LM3S600 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S600 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S600 + +//***************************************************************************** +// +// LM3S601 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S601 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX_PORT (GPIO_PORTD_BASE) +#define IDX_PIN (GPIO_PIN_7) + +#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA_PORT (GPIO_PORTC_BASE) +#define PHA_PIN (GPIO_PIN_4) + +#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB_PORT (GPIO_PORTC_BASE) +#define PHB_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S601 + +//***************************************************************************** +// +// LM3S608 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S608 + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S608 + +//***************************************************************************** +// +// LM3S610 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S610 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S610 + +//***************************************************************************** +// +// LM3S611 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S611 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S611 + +//***************************************************************************** +// +// LM3S612 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S612 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S612 + +//***************************************************************************** +// +// LM3S613 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S613 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S613 + +//***************************************************************************** +// +// LM3S615 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S615 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S615 + +//***************************************************************************** +// +// LM3S617 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S617 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S617 + +//***************************************************************************** +// +// LM3S618 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S618 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define IDX_PORT (GPIO_PORTB_BASE) +#define IDX_PIN (GPIO_PIN_2) + +#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA_PORT (GPIO_PORTC_BASE) +#define PHA_PIN (GPIO_PIN_4) + +#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB_PORT (GPIO_PORTC_BASE) +#define PHB_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S618 + +//***************************************************************************** +// +// LM3S628 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S628 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S628 + +//***************************************************************************** +// +// LM3S800 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S800 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S800 + +//***************************************************************************** +// +// LM3S801 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S801 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX_PORT (GPIO_PORTD_BASE) +#define IDX_PIN (GPIO_PIN_7) + +#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA_PORT (GPIO_PORTC_BASE) +#define PHA_PIN (GPIO_PIN_4) + +#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB_PORT (GPIO_PORTC_BASE) +#define PHB_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S801 + +//***************************************************************************** +// +// LM3S808 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S808 + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S808 + +//***************************************************************************** +// +// LM3S811 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S811 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S811 + +//***************************************************************************** +// +// LM3S812 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S812 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S812 + +//***************************************************************************** +// +// LM3S815 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S815 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S815 + +//***************************************************************************** +// +// LM3S817 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S817 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S817 + +//***************************************************************************** +// +// LM3S818 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S818 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define IDX_PORT (GPIO_PORTB_BASE) +#define IDX_PIN (GPIO_PIN_2) + +#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA_PORT (GPIO_PORTC_BASE) +#define PHA_PIN (GPIO_PIN_4) + +#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB_PORT (GPIO_PORTC_BASE) +#define PHB_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S818 + +//***************************************************************************** +// +// LM3S828 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S828 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSCL_PORT (GPIO_PORTB_BASE) +#define I2CSCL_PIN (GPIO_PIN_2) + +#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2CSDA_PORT (GPIO_PORTB_BASE) +#define I2CSDA_PIN (GPIO_PIN_3) + +#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSICLK_PORT (GPIO_PORTA_BASE) +#define SSICLK_PIN (GPIO_PIN_2) + +#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIFSS_PORT (GPIO_PORTA_BASE) +#define SSIFSS_PIN (GPIO_PIN_3) + +#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSIRX_PORT (GPIO_PORTA_BASE) +#define SSIRX_PIN (GPIO_PIN_4) + +#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSITX_PORT (GPIO_PORTA_BASE) +#define SSITX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S828 + +//***************************************************************************** +// +// LM3S1110 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1110 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1110 + +//***************************************************************************** +// +// LM3S1133 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1133 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1133 + +//***************************************************************************** +// +// LM3S1138 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1138 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP3_PORT (GPIO_PORTG_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP4_PORT (GPIO_PORTF_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1138 + +//***************************************************************************** +// +// LM3S1150 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1150 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1150 + +//***************************************************************************** +// +// LM3S1162 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1162 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1162 + +//***************************************************************************** +// +// LM3S1165 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1165 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP6_PORT (GPIO_PORTB_BASE) +#define CCP6_PIN (GPIO_PIN_5) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1165 + +//***************************************************************************** +// +// LM3S1332 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1332 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1332 + +//***************************************************************************** +// +// LM3S1435 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1435 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1435 + +//***************************************************************************** +// +// LM3S1439 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1439 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1439 + +//***************************************************************************** +// +// LM3S1512 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1512 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C2O_PORT (GPIO_PORTF_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP4_PORT (GPIO_PORTD_BASE) +#define CCP4_PIN (GPIO_PIN_5) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1512 + +//***************************************************************************** +// +// LM3S1538 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1538 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1538 + +//***************************************************************************** +// +// LM3S1601 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1601 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1601 + +//***************************************************************************** +// +// LM3S1608 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1608 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1608 + +//***************************************************************************** +// +// LM3S1620 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1620 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1620 + +//***************************************************************************** +// +// LM3S1635 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1635 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1635 + +//***************************************************************************** +// +// LM3S1637 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1637 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1637 + +//***************************************************************************** +// +// LM3S1751 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1751 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1751 + +//***************************************************************************** +// +// LM3S1850 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1850 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1850 + +//***************************************************************************** +// +// LM3S1911 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1911 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1911 + +//***************************************************************************** +// +// LM3S1918 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1918 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1918 + +//***************************************************************************** +// +// LM3S1937 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1937 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S1937 + +//***************************************************************************** +// +// LM3S1958 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1958 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1958 + +//***************************************************************************** +// +// LM3S1960 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1960 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C2O_PORT (GPIO_PORTF_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP4_PORT (GPIO_PORTF_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH) +#define IDX1_PORT (GPIO_PORTH_BASE) +#define IDX1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PHA1_PORT (GPIO_PORTG_BASE) +#define PHA1_PIN (GPIO_PIN_6) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PHB0_PORT (GPIO_PORTH_BASE) +#define PHB0_PIN (GPIO_PIN_3) + +#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PHB1_PORT (GPIO_PORTG_BASE) +#define PHB1_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1960 + +//***************************************************************************** +// +// LM3S1968 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1968 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP3_PORT (GPIO_PORTG_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOH) +#define FAULT_PORT (GPIO_PORTH_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define IDX1_PORT (GPIO_PORTF_BASE) +#define IDX1_PIN (GPIO_PIN_1) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PHA1_PORT (GPIO_PORTG_BASE) +#define PHA1_PIN (GPIO_PIN_6) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PHB1_PORT (GPIO_PORTG_BASE) +#define PHB1_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM0_PORT (GPIO_PORTG_BASE) +#define PWM0_PIN (GPIO_PIN_2) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1968 + +//***************************************************************************** +// +// LM3S2016 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2016 + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2016 + +//***************************************************************************** +// +// LM3S2110 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2110 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2110 + +//***************************************************************************** +// +// LM3S2139 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2139 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2139 + +//***************************************************************************** +// +// LM3S2410 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2410 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2410 + +//***************************************************************************** +// +// LM3S2412 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2412 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2412 + +//***************************************************************************** +// +// LM3S2432 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2432 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2432 + +//***************************************************************************** +// +// LM3S2533 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2533 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2533 + +//***************************************************************************** +// +// LM3S2601 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2601 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2601 + +//***************************************************************************** +// +// LM3S2608 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2608 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2608 + +//***************************************************************************** +// +// LM3S2620 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2620 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C2O_PORT (GPIO_PORTE_BASE) +#define C2O_PIN (GPIO_PIN_7) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PHB0_PORT (GPIO_PORTH_BASE) +#define PHB0_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM0_PORT (GPIO_PORTG_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM1_PORT (GPIO_PORTG_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM2_PORT (GPIO_PORTD_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM3_PORT (GPIO_PORTD_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2620 + +//***************************************************************************** +// +// LM3S2637 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2637 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2637 + +//***************************************************************************** +// +// LM3S2651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2651 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2651 + +//***************************************************************************** +// +// LM3S2730 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2730 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2730 + +//***************************************************************************** +// +// LM3S2739 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2739 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2739 + +//***************************************************************************** +// +// LM3S2911 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2911 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2911 + +//***************************************************************************** +// +// LM3S2918 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2918 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S2918 + +//***************************************************************************** +// +// LM3S2939 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2939 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PHB0_PORT (GPIO_PORTH_BASE) +#define PHB0_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2939 + +//***************************************************************************** +// +// LM3S2948 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2948 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP3_PORT (GPIO_PORTG_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2948 + +//***************************************************************************** +// +// LM3S2950 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2950 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C2O_PORT (GPIO_PORTF_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP5_PORT (GPIO_PORTE_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PHB0_PORT (GPIO_PORTH_BASE) +#define PHB0_PIN (GPIO_PIN_3) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM0_PORT (GPIO_PORTG_BASE) +#define PWM0_PIN (GPIO_PIN_2) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM1_PORT (GPIO_PORTG_BASE) +#define PWM1_PIN (GPIO_PIN_3) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2950 + +//***************************************************************************** +// +// LM3S2965 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2965 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP4_PORT (GPIO_PORTD_BASE) +#define CCP4_PIN (GPIO_PIN_5) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP5_PORT (GPIO_PORTG_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH) +#define IDX1_PORT (GPIO_PORTH_BASE) +#define IDX1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PHA1_PORT (GPIO_PORTG_BASE) +#define PHA1_PIN (GPIO_PIN_6) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PHB0_PORT (GPIO_PORTH_BASE) +#define PHB0_PIN (GPIO_PIN_3) + +#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PHB1_PORT (GPIO_PORTG_BASE) +#define PHB1_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM0_PORT (GPIO_PORTG_BASE) +#define PWM0_PIN (GPIO_PIN_2) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM1_PORT (GPIO_PORTG_BASE) +#define PWM1_PIN (GPIO_PIN_3) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2965 + +//***************************************************************************** +// +// LM3S6100 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6100 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6100 + +//***************************************************************************** +// +// LM3S6110 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6110 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6110 + +//***************************************************************************** +// +// LM3S6420 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6420 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6420 + +//***************************************************************************** +// +// LM3S6422 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6422 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6422 + +//***************************************************************************** +// +// LM3S6432 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6432 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6432 + +//***************************************************************************** +// +// LM3S6537 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6537 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6537 + +//***************************************************************************** +// +// LM3S6610 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6610 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C2O_PORT (GPIO_PORTE_BASE) +#define C2O_PIN (GPIO_PIN_7) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_0) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6610 + +//***************************************************************************** +// +// LM3S6611 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6611 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6611 + +//***************************************************************************** +// +// LM3S6618 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6618 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) +#define I2C1SCL_PORT (GPIO_PORTG_BASE) +#define I2C1SCL_PIN (GPIO_PIN_0) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6618 + +//***************************************************************************** +// +// LM3S6633 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6633 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6633 + +//***************************************************************************** +// +// LM3S6637 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6637 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6637 + +//***************************************************************************** +// +// LM3S6730 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6730 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6730 + +//***************************************************************************** +// +// LM3S6753 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6753 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6753 + +//***************************************************************************** +// +// LM3S6816 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6816 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT_PORT (GPIO_PORTE_BASE) +#define FAULT_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6816 + +//***************************************************************************** +// +// LM3S6911 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6911 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE) +#define C1O_PORT (GPIO_PORTE_BASE) +#define C1O_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6911 + +//***************************************************************************** +// +// LM3S6916 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6916 + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT_PORT (GPIO_PORTE_BASE) +#define FAULT_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6916 + +//***************************************************************************** +// +// LM3S6918 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6918 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) +#define I2C1SCL_PORT (GPIO_PORTG_BASE) +#define I2C1SCL_PIN (GPIO_PIN_0) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S6918 + +//***************************************************************************** +// +// LM3S6938 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6938 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_0) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6938 + +//***************************************************************************** +// +// LM3S6950 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6950 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6950 + +//***************************************************************************** +// +// LM3S6952 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6952 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_0) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_0) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6952 + +//***************************************************************************** +// +// LM3S6965 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S6965 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP1_PORT (GPIO_PORTD_BASE) +#define CCP1_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP2_PORT (GPIO_PORTD_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define IDX1_PORT (GPIO_PORTF_BASE) +#define IDX1_PIN (GPIO_PIN_1) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PHA1_PORT (GPIO_PORTE_BASE) +#define PHA1_PIN (GPIO_PIN_3) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PHB1_PORT (GPIO_PORTE_BASE) +#define PHB1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S6965 + +//***************************************************************************** +// +// LM3S8530 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8530 + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CAN2RX_PORT (GPIO_PORTE_BASE) +#define CAN2RX_PIN (GPIO_PIN_4) + +#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CAN2TX_PORT (GPIO_PORTE_BASE) +#define CAN2TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S8530 + +//***************************************************************************** +// +// LM3S8538 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8538 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_0) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8538 + +//***************************************************************************** +// +// LM3S8630 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8630 + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8630 + +//***************************************************************************** +// +// LM3S8730 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8730 + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8730 + +//***************************************************************************** +// +// LM3S8733 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8733 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8733 + +//***************************************************************************** +// +// LM3S8738 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8738 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S8738 + +//***************************************************************************** +// +// LM3S8930 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8930 + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S8930 + +//***************************************************************************** +// +// LM3S8933 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8933 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD) +#define C0O_PORT (GPIO_PORTD_BASE) +#define C0O_PIN (GPIO_PIN_7) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP3_PORT (GPIO_PORTD_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8933 + +//***************************************************************************** +// +// LM3S8938 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8938 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_7) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP1_PORT (GPIO_PORTE_BASE) +#define CCP1_PIN (GPIO_PIN_3) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_0) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP4_PORT (GPIO_PORTE_BASE) +#define CCP4_PIN (GPIO_PIN_2) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2RX_PORT (GPIO_PORTG_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG) +#define U2TX_PORT (GPIO_PORTG_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S8938 + +//***************************************************************************** +// +// LM3S8962 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8962 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_4) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD) +#define FAULT_PORT (GPIO_PORTD_BASE) +#define FAULT_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_7) + +#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define IDX1_PORT (GPIO_PORTF_BASE) +#define IDX1_PIN (GPIO_PIN_1) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PHA1_PORT (GPIO_PORTE_BASE) +#define PHA1_PIN (GPIO_PIN_3) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_6) + +#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PHB1_PORT (GPIO_PORTE_BASE) +#define PHB1_PIN (GPIO_PIN_2) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM1_PORT (GPIO_PORTG_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8962 + +//***************************************************************************** +// +// LM3S8970 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8970 + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CAN2RX_PORT (GPIO_PORTE_BASE) +#define CAN2RX_PIN (GPIO_PIN_4) + +#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CAN2TX_PORT (GPIO_PORTE_BASE) +#define CAN2TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#endif // PART_LM3S8970 + +//***************************************************************************** +// +// LM3S8971 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S8971 + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_1) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_5) + +#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT_PORT (GPIO_PORTB_BASE) +#define FAULT_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define IDX0_PORT (GPIO_PORTB_BASE) +#define IDX0_PIN (GPIO_PIN_2) + +#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED0_PORT (GPIO_PORTF_BASE) +#define LED0_PIN (GPIO_PIN_3) + +#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define LED1_PORT (GPIO_PORTF_BASE) +#define LED1_PIN (GPIO_PIN_2) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM2_PORT (GPIO_PORTD_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM3_PORT (GPIO_PORTD_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM4_PORT (GPIO_PORTE_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE) +#define PWM5_PORT (GPIO_PORTE_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB) +#define TRST_PORT (GPIO_PORTB_BASE) +#define TRST_PIN (GPIO_PIN_7) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S8971 + +//***************************************************************************** +// +// LM3S1607 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1607 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_1) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_0) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_5) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP5_PORT (GPIO_PORTB_BASE) +#define CCP5_PIN (GPIO_PIN_6) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U2RX_PORT (GPIO_PORTB_BASE) +#define U2RX_PIN (GPIO_PIN_4) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define U2TX_PORT (GPIO_PORTE_BASE) +#define U2TX_PIN (GPIO_PIN_4) + +#endif // PART_LM3S1607 + +//***************************************************************************** +// +// LM3S1625 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1625 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_7) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1625 + +//***************************************************************************** +// +// LM3S1626 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1626 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_6) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_5) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM0_PORT (GPIO_PORTA_BASE) +#define PWM0_PIN (GPIO_PIN_6) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM1_PORT (GPIO_PORTA_BASE) +#define PWM1_PIN (GPIO_PIN_7) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_4) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_5) + +#endif // PART_LM3S1626 + +//***************************************************************************** +// +// LM3S1627 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1627 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_6) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_5) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define IDX0_PORT (GPIO_PORTB_BASE) +#define IDX0_PIN (GPIO_PIN_4) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM2_PORT (GPIO_PORTD_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM3_PORT (GPIO_PORTD_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1627 + +//***************************************************************************** +// +// LM3S1776 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S1776 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_7) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT1_PORT (GPIO_PORTB_BASE) +#define FAULT1_PIN (GPIO_PIN_6) + +#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define FAULT2_PORT (GPIO_PORTC_BASE) +#define FAULT2_PIN (GPIO_PIN_5) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PWM6_PORT (GPIO_PORTC_BASE) +#define PWM6_PIN (GPIO_PIN_4) + +#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PWM7_PORT (GPIO_PORTC_BASE) +#define PWM7_PIN (GPIO_PIN_6) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S1776 + +//***************************************************************************** +// +// LM3S2276 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2276 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0RX_PORT (GPIO_PORTB_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0TX_PORT (GPIO_PORTB_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_7) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT1_PORT (GPIO_PORTB_BASE) +#define FAULT1_PIN (GPIO_PIN_6) + +#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define FAULT2_PORT (GPIO_PORTC_BASE) +#define FAULT2_PIN (GPIO_PIN_5) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PWM6_PORT (GPIO_PORTC_BASE) +#define PWM6_PIN (GPIO_PIN_4) + +#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PWM7_PORT (GPIO_PORTC_BASE) +#define PWM7_PIN (GPIO_PIN_6) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2276 + +//***************************************************************************** +// +// LM3S2616 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2616 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C0O_PORT (GPIO_PORTC_BASE) +#define C0O_PIN (GPIO_PIN_5) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_7) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_7) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CAN0RX_PORT (GPIO_PORTA_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CAN0TX_PORT (GPIO_PORTA_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM0_PORT (GPIO_PORTA_BASE) +#define PWM0_PIN (GPIO_PIN_6) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM1_PORT (GPIO_PORTA_BASE) +#define PWM1_PIN (GPIO_PIN_7) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2616 + +//***************************************************************************** +// +// LM3S2671 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2671 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_7) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_7) + +#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2O_PORT (GPIO_PORTC_BASE) +#define C2O_PIN (GPIO_PIN_6) + +#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_MINUS_PORT (GPIO_PORTC_BASE) +#define C2_MINUS_PIN (GPIO_PIN_5) + +#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C2_PLUS_PORT (GPIO_PORTC_BASE) +#define C2_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_1) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM0_PORT (GPIO_PORTA_BASE) +#define PWM0_PIN (GPIO_PIN_6) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM1_PORT (GPIO_PORTA_BASE) +#define PWM1_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2671 + +//***************************************************************************** +// +// LM3S2678 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2678 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_1) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_0) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0RX_PORT (GPIO_PORTB_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0TX_PORT (GPIO_PORTB_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_6) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP1_PORT (GPIO_PORTC_BASE) +#define CCP1_PIN (GPIO_PIN_5) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT0_PORT (GPIO_PORTB_BASE) +#define FAULT0_PIN (GPIO_PIN_3) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT1_PORT (GPIO_PORTB_BASE) +#define FAULT1_PIN (GPIO_PIN_6) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define IDX0_PORT (GPIO_PORTB_BASE) +#define IDX0_PIN (GPIO_PIN_2) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHA0_PORT (GPIO_PORTC_BASE) +#define PHA0_PIN (GPIO_PIN_4) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM0_PORT (GPIO_PORTA_BASE) +#define PWM0_PIN (GPIO_PIN_6) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM1_PORT (GPIO_PORTA_BASE) +#define PWM1_PIN (GPIO_PIN_7) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2678 + +//***************************************************************************** +// +// LM3S2776 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S2776 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0RX_PORT (GPIO_PORTB_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0TX_PORT (GPIO_PORTB_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_7) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT1_PORT (GPIO_PORTB_BASE) +#define FAULT1_PIN (GPIO_PIN_6) + +#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define FAULT2_PORT (GPIO_PORTC_BASE) +#define FAULT2_PIN (GPIO_PIN_5) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM2_PORT (GPIO_PORTB_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB) +#define PWM3_PORT (GPIO_PORTB_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PWM6_PORT (GPIO_PORTC_BASE) +#define PWM6_PIN (GPIO_PIN_4) + +#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PWM7_PORT (GPIO_PORTC_BASE) +#define PWM7_PIN (GPIO_PIN_6) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#endif // PART_LM3S2776 + +//***************************************************************************** +// +// LM3S3651 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3651 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0O_PORT (GPIO_PORTB_BASE) +#define C0O_PIN (GPIO_PIN_6) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_7) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_3) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP4_PORT (GPIO_PORTA_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP5_PORT (GPIO_PORTD_BASE) +#define CCP5_PIN (GPIO_PIN_2) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP6_PORT (GPIO_PORTD_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP7_PORT (GPIO_PORTD_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0ID_PORT (GPIO_PORTB_BASE) +#define USB0ID_PIN (GPIO_PIN_0) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0VBUS_PORT (GPIO_PORTB_BASE) +#define USB0VBUS_PIN (GPIO_PIN_1) + +#endif // PART_LM3S3651 + +//***************************************************************************** +// +// LM3S3739 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3739 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_6) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP3_PORT (GPIO_PORTG_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP5_PORT (GPIO_PORTD_BASE) +#define CCP5_PIN (GPIO_PIN_2) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP7_PORT (GPIO_PORTD_BASE) +#define CCP7_PIN (GPIO_PIN_3) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U2RX_PORT (GPIO_PORTD_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U2TX_PORT (GPIO_PORTD_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0EPEN_PORT (GPIO_PORTH_BASE) +#define USB0EPEN_PIN (GPIO_PIN_3) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0PFLT_PORT (GPIO_PORTH_BASE) +#define USB0PFLT_PIN (GPIO_PIN_4) + +#endif // PART_LM3S3739 + +//***************************************************************************** +// +// LM3S3748 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3748 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_3) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP2_PORT (GPIO_PORTF_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP3_PORT (GPIO_PORTG_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_4) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP5_PORT (GPIO_PORTD_BASE) +#define CCP5_PIN (GPIO_PIN_2) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP7_PORT (GPIO_PORTH_BASE) +#define CCP7_PIN (GPIO_PIN_1) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define FAULT0_PORT (GPIO_PORTF_BASE) +#define FAULT0_PIN (GPIO_PIN_4) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT1_PORT (GPIO_PORTG_BASE) +#define FAULT1_PIN (GPIO_PIN_5) + +#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT2_PORT (GPIO_PORTG_BASE) +#define FAULT2_PIN (GPIO_PIN_3) + +#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define FAULT3_PORT (GPIO_PORTH_BASE) +#define FAULT3_PIN (GPIO_PIN_2) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define IDX0_PORT (GPIO_PORTD_BASE) +#define IDX0_PIN (GPIO_PIN_0) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PHA0_PORT (GPIO_PORTD_BASE) +#define PHA0_PIN (GPIO_PIN_1) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM2_PORT (GPIO_PORTF_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM3_PORT (GPIO_PORTF_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM4_PORT (GPIO_PORTG_BASE) +#define PWM4_PIN (GPIO_PIN_0) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM5_PORT (GPIO_PORTG_BASE) +#define PWM5_PIN (GPIO_PIN_1) + +#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM6_PORT (GPIO_PORTG_BASE) +#define PWM6_PIN (GPIO_PIN_6) + +#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM7_PORT (GPIO_PORTG_BASE) +#define PWM7_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOC) +#define U1RX_PORT (GPIO_PORTC_BASE) +#define U1RX_PIN (GPIO_PIN_6) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOC) +#define U1TX_PORT (GPIO_PORTC_BASE) +#define U1TX_PIN (GPIO_PIN_7) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0EPEN_PORT (GPIO_PORTH_BASE) +#define USB0EPEN_PIN (GPIO_PIN_3) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0PFLT_PORT (GPIO_PORTH_BASE) +#define USB0PFLT_PIN (GPIO_PIN_4) + +#endif // PART_LM3S3748 + +//***************************************************************************** +// +// LM3S3749 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S3749 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1O_PORT (GPIO_PORTC_BASE) +#define C1O_PIN (GPIO_PIN_7) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP0_PORT (GPIO_PORTD_BASE) +#define CCP0_PIN (GPIO_PIN_3) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP2_PORT (GPIO_PORTF_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP3_PORT (GPIO_PORTA_BASE) +#define CCP3_PIN (GPIO_PIN_7) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP4_PORT (GPIO_PORTF_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP6_PORT (GPIO_PORTD_BASE) +#define CCP6_PIN (GPIO_PIN_2) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT0_PORT (GPIO_PORTG_BASE) +#define FAULT0_PIN (GPIO_PIN_2) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT1_PORT (GPIO_PORTG_BASE) +#define FAULT1_PIN (GPIO_PIN_4) + +#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT2_PORT (GPIO_PORTG_BASE) +#define FAULT2_PIN (GPIO_PIN_3) + +#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define FAULT3_PORT (GPIO_PORTH_BASE) +#define FAULT3_PIN (GPIO_PIN_2) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) +#define I2C1SCL_PORT (GPIO_PORTG_BASE) +#define I2C1SCL_PIN (GPIO_PIN_0) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG) +#define I2C1SDA_PORT (GPIO_PORTG_BASE) +#define I2C1SDA_PIN (GPIO_PIN_1) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define IDX0_PORT (GPIO_PORTG_BASE) +#define IDX0_PIN (GPIO_PIN_5) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHA0_PORT (GPIO_PORTF_BASE) +#define PHA0_PIN (GPIO_PIN_6) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define PHB0_PORT (GPIO_PORTC_BASE) +#define PHB0_PIN (GPIO_PIN_6) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM0_PORT (GPIO_PORTF_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM1_PORT (GPIO_PORTF_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM6_PORT (GPIO_PORTG_BASE) +#define PWM6_PIN (GPIO_PIN_6) + +#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM7_PORT (GPIO_PORTG_BASE) +#define PWM7_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U2RX_PORT (GPIO_PORTD_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U2TX_PORT (GPIO_PORTD_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0EPEN_PORT (GPIO_PORTH_BASE) +#define USB0EPEN_PIN (GPIO_PIN_3) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0PFLT_PORT (GPIO_PORTH_BASE) +#define USB0PFLT_PIN (GPIO_PIN_4) + +#endif // PART_LM3S3749 + +//***************************************************************************** +// +// LM3S5632 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5632 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_5) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#endif // PART_LM3S5632 + +//***************************************************************************** +// +// LM3S5652 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5652 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_5) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP2_PORT (GPIO_PORTE_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP3_PORT (GPIO_PORTA_BASE) +#define CCP3_PIN (GPIO_PIN_7) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0ID_PORT (GPIO_PORTB_BASE) +#define USB0ID_PIN (GPIO_PIN_0) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0VBUS_PORT (GPIO_PORTB_BASE) +#define USB0VBUS_PIN (GPIO_PIN_1) + +#endif // PART_LM3S5652 + +//***************************************************************************** +// +// LM3S5662 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5662 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0RX_PORT (GPIO_PORTB_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0TX_PORT (GPIO_PORTB_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_2) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT0_PORT (GPIO_PORTB_BASE) +#define FAULT0_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM2_PORT (GPIO_PORTD_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM3_PORT (GPIO_PORTD_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0ID_PORT (GPIO_PORTB_BASE) +#define USB0ID_PIN (GPIO_PIN_0) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0VBUS_PORT (GPIO_PORTB_BASE) +#define USB0VBUS_PIN (GPIO_PIN_1) + +#endif // PART_LM3S5662 + +//***************************************************************************** +// +// LM3S5732 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5732 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_5) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#endif // PART_LM3S5732 + +//***************************************************************************** +// +// LM3S5737 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5737 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_1) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP2_PORT (GPIO_PORTB_BASE) +#define CCP2_PIN (GPIO_PIN_5) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#endif // PART_LM3S5737 + +//***************************************************************************** +// +// LM3S5739 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5739 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CAN0RX_PORT (GPIO_PORTA_BASE) +#define CAN0RX_PIN (GPIO_PIN_6) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CAN0TX_PORT (GPIO_PORTA_BASE) +#define CAN0TX_PIN (GPIO_PIN_7) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP0_PORT (GPIO_PORTC_BASE) +#define CCP0_PIN (GPIO_PIN_6) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CCP1_PORT (GPIO_PORTF_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG) +#define CCP3_PORT (GPIO_PORTG_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP5_PORT (GPIO_PORTD_BASE) +#define CCP5_PIN (GPIO_PIN_2) + +#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH) +#define CCP6_PORT (GPIO_PORTH_BASE) +#define CCP6_PIN (GPIO_PIN_0) + +#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CCP7_PORT (GPIO_PORTD_BASE) +#define CCP7_PIN (GPIO_PIN_3) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG) +#define I2C1SCL_PORT (GPIO_PORTG_BASE) +#define I2C1SCL_PIN (GPIO_PIN_0) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG) +#define I2C1SDA_PORT (GPIO_PORTG_BASE) +#define I2C1SDA_PIN (GPIO_PIN_1) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1RX_PORT (GPIO_PORTB_BASE) +#define U1RX_PIN (GPIO_PIN_0) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define U1TX_PORT (GPIO_PORTB_BASE) +#define U1TX_PIN (GPIO_PIN_1) + +#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U2RX_PORT (GPIO_PORTD_BASE) +#define U2RX_PIN (GPIO_PIN_0) + +#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U2TX_PORT (GPIO_PORTD_BASE) +#define U2TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0EPEN_PORT (GPIO_PORTH_BASE) +#define USB0EPEN_PIN (GPIO_PIN_3) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0PFLT_PORT (GPIO_PORTH_BASE) +#define USB0PFLT_PIN (GPIO_PIN_4) + +#endif // PART_LM3S5739 + +//***************************************************************************** +// +// LM3S5747 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5747 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0RX_PORT (GPIO_PORTB_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0TX_PORT (GPIO_PORTB_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define FAULT0_PORT (GPIO_PORTE_BASE) +#define FAULT0_PIN (GPIO_PIN_1) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM2_PORT (GPIO_PORTD_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM3_PORT (GPIO_PORTD_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#endif // PART_LM3S5747 + +//***************************************************************************** +// +// LM3S5749 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5749 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_7) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_6) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_5) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_4) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_7) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_6) + +#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC6_PORT (GPIO_PORTD_BASE) +#define ADC6_PIN (GPIO_PIN_5) + +#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC7_PORT (GPIO_PORTD_BASE) +#define ADC7_PIN (GPIO_PIN_4) + +#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C0O_PORT (GPIO_PORTF_BASE) +#define C0O_PIN (GPIO_PIN_4) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF) +#define C1O_PORT (GPIO_PORTF_BASE) +#define C1O_PIN (GPIO_PIN_5) + +#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C1_MINUS_PORT (GPIO_PORTB_BASE) +#define C1_MINUS_PIN (GPIO_PIN_5) + +#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define C1_PLUS_PORT (GPIO_PORTC_BASE) +#define C1_PLUS_PIN (GPIO_PIN_5) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1RX_PORT (GPIO_PORTF_BASE) +#define CAN1RX_PIN (GPIO_PIN_0) + +#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF) +#define CAN1TX_PORT (GPIO_PORTF_BASE) +#define CAN1TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_0) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_1) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP3_PORT (GPIO_PORTC_BASE) +#define CCP3_PIN (GPIO_PIN_6) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT0_PORT (GPIO_PORTG_BASE) +#define FAULT0_PIN (GPIO_PIN_2) + +#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT1_PORT (GPIO_PORTG_BASE) +#define FAULT1_PIN (GPIO_PIN_4) + +#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG) +#define FAULT2_PORT (GPIO_PORTG_BASE) +#define FAULT2_PIN (GPIO_PIN_3) + +#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define FAULT3_PORT (GPIO_PORTH_BASE) +#define FAULT3_PIN (GPIO_PIN_2) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SCL_PORT (GPIO_PORTA_BASE) +#define I2C1SCL_PIN (GPIO_PIN_6) + +#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA) +#define I2C1SDA_PORT (GPIO_PORTA_BASE) +#define I2C1SDA_PIN (GPIO_PIN_7) + +#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define IDX0_PORT (GPIO_PORTG_BASE) +#define IDX0_PIN (GPIO_PIN_5) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHA0_PORT (GPIO_PORTF_BASE) +#define PHA0_PIN (GPIO_PIN_6) + +#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PHB0_PORT (GPIO_PORTF_BASE) +#define PHB0_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM0_PORT (GPIO_PORTG_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM1_PORT (GPIO_PORTG_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM2_PORT (GPIO_PORTH_BASE) +#define PWM2_PIN (GPIO_PIN_0) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH) +#define PWM3_PORT (GPIO_PORTH_BASE) +#define PWM3_PIN (GPIO_PIN_1) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM4_PORT (GPIO_PORTF_BASE) +#define PWM4_PIN (GPIO_PIN_2) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF) +#define PWM5_PORT (GPIO_PORTF_BASE) +#define PWM5_PIN (GPIO_PIN_3) + +#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM6_PORT (GPIO_PORTG_BASE) +#define PWM6_PIN (GPIO_PIN_6) + +#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG) +#define PWM7_PORT (GPIO_PORTG_BASE) +#define PWM7_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1CLK_PORT (GPIO_PORTE_BASE) +#define SSI1CLK_PIN (GPIO_PIN_0) + +#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1FSS_PORT (GPIO_PORTE_BASE) +#define SSI1FSS_PIN (GPIO_PIN_1) + +#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1RX_PORT (GPIO_PORTE_BASE) +#define SSI1RX_PIN (GPIO_PIN_2) + +#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE) +#define SSI1TX_PORT (GPIO_PORTE_BASE) +#define SSI1TX_PIN (GPIO_PIN_3) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1RX_PORT (GPIO_PORTD_BASE) +#define U1RX_PIN (GPIO_PIN_2) + +#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define U1TX_PORT (GPIO_PORTD_BASE) +#define U1TX_PIN (GPIO_PIN_3) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0EPEN_PORT (GPIO_PORTH_BASE) +#define USB0EPEN_PIN (GPIO_PIN_3) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH) +#define USB0PFLT_PORT (GPIO_PORTH_BASE) +#define USB0PFLT_PIN (GPIO_PIN_4) + +#endif // PART_LM3S5749 + +//***************************************************************************** +// +// LM3S5752 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5752 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC4_PORT (GPIO_PORTD_BASE) +#define ADC4_PIN (GPIO_PIN_3) + +#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD) +#define ADC5_PORT (GPIO_PORTD_BASE) +#define ADC5_PIN (GPIO_PIN_2) + +#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_MINUS_PORT (GPIO_PORTB_BASE) +#define C0_MINUS_PIN (GPIO_PIN_4) + +#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define C0_PLUS_PORT (GPIO_PORTB_BASE) +#define C0_PLUS_PIN (GPIO_PIN_6) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0RX_PORT (GPIO_PORTD_BASE) +#define CAN0RX_PIN (GPIO_PIN_0) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD) +#define CAN0TX_PORT (GPIO_PORTD_BASE) +#define CAN0TX_PIN (GPIO_PIN_1) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_5) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP1_PORT (GPIO_PORTA_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP2_PORT (GPIO_PORTE_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA) +#define CCP3_PORT (GPIO_PORTA_BASE) +#define CCP3_PIN (GPIO_PIN_7) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP5_PORT (GPIO_PORTC_BASE) +#define CCP5_PIN (GPIO_PIN_4) + +#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SCL_PORT (GPIO_PORTB_BASE) +#define I2C0SCL_PIN (GPIO_PIN_2) + +#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB) +#define I2C0SDA_PORT (GPIO_PORTB_BASE) +#define I2C0SDA_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0ID_PORT (GPIO_PORTB_BASE) +#define USB0ID_PIN (GPIO_PIN_0) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0VBUS_PORT (GPIO_PORTB_BASE) +#define USB0VBUS_PIN (GPIO_PIN_1) + +#endif // PART_LM3S5752 + +//***************************************************************************** +// +// LM3S5762 Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM3S5762 + +#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC0_PORT (GPIO_PORTE_BASE) +#define ADC0_PIN (GPIO_PIN_3) + +#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC1_PORT (GPIO_PORTE_BASE) +#define ADC1_PIN (GPIO_PIN_2) + +#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC2_PORT (GPIO_PORTE_BASE) +#define ADC2_PIN (GPIO_PIN_1) + +#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define ADC3_PORT (GPIO_PORTE_BASE) +#define ADC3_PIN (GPIO_PIN_0) + +#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0RX_PORT (GPIO_PORTB_BASE) +#define CAN0RX_PIN (GPIO_PIN_4) + +#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CAN0TX_PORT (GPIO_PORTB_BASE) +#define CAN0TX_PIN (GPIO_PIN_5) + +#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP0_PORT (GPIO_PORTB_BASE) +#define CCP0_PIN (GPIO_PIN_2) + +#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB) +#define CCP1_PORT (GPIO_PORTB_BASE) +#define CCP1_PIN (GPIO_PIN_6) + +#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP2_PORT (GPIO_PORTC_BASE) +#define CCP2_PIN (GPIO_PIN_4) + +#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE) +#define CCP3_PORT (GPIO_PORTE_BASE) +#define CCP3_PIN (GPIO_PIN_4) + +#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC) +#define CCP4_PORT (GPIO_PORTC_BASE) +#define CCP4_PIN (GPIO_PIN_7) + +#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB) +#define FAULT0_PORT (GPIO_PORTB_BASE) +#define FAULT0_PIN (GPIO_PIN_3) + +#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB) +#define NMI_PORT (GPIO_PORTB_BASE) +#define NMI_PIN (GPIO_PIN_7) + +#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM0_PORT (GPIO_PORTD_BASE) +#define PWM0_PIN (GPIO_PIN_0) + +#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM1_PORT (GPIO_PORTD_BASE) +#define PWM1_PIN (GPIO_PIN_1) + +#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM2_PORT (GPIO_PORTD_BASE) +#define PWM2_PIN (GPIO_PIN_2) + +#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD) +#define PWM3_PORT (GPIO_PORTD_BASE) +#define PWM3_PIN (GPIO_PIN_3) + +#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM4_PORT (GPIO_PORTA_BASE) +#define PWM4_PIN (GPIO_PIN_6) + +#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA) +#define PWM5_PORT (GPIO_PORTA_BASE) +#define PWM5_PIN (GPIO_PIN_7) + +#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0CLK_PORT (GPIO_PORTA_BASE) +#define SSI0CLK_PIN (GPIO_PIN_2) + +#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0FSS_PORT (GPIO_PORTA_BASE) +#define SSI0FSS_PIN (GPIO_PIN_3) + +#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0RX_PORT (GPIO_PORTA_BASE) +#define SSI0RX_PIN (GPIO_PIN_4) + +#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define SSI0TX_PORT (GPIO_PORTA_BASE) +#define SSI0TX_PIN (GPIO_PIN_5) + +#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWCLK_PORT (GPIO_PORTC_BASE) +#define SWCLK_PIN (GPIO_PIN_0) + +#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWDIO_PORT (GPIO_PORTC_BASE) +#define SWDIO_PIN (GPIO_PIN_1) + +#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define SWO_PORT (GPIO_PORTC_BASE) +#define SWO_PIN (GPIO_PIN_3) + +#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TCK_PORT (GPIO_PORTC_BASE) +#define TCK_PIN (GPIO_PIN_0) + +#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDI_PORT (GPIO_PORTC_BASE) +#define TDI_PIN (GPIO_PIN_2) + +#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TDO_PORT (GPIO_PORTC_BASE) +#define TDO_PIN (GPIO_PIN_3) + +#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC) +#define TMS_PORT (GPIO_PORTC_BASE) +#define TMS_PIN (GPIO_PIN_1) + +#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0RX_PORT (GPIO_PORTA_BASE) +#define U0RX_PIN (GPIO_PIN_0) + +#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA) +#define U0TX_PORT (GPIO_PORTA_BASE) +#define U0TX_PIN (GPIO_PIN_1) + +#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0EPEN_PORT (GPIO_PORTC_BASE) +#define USB0EPEN_PIN (GPIO_PIN_5) + +#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0ID_PORT (GPIO_PORTB_BASE) +#define USB0ID_PIN (GPIO_PIN_0) + +#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC) +#define USB0PFLT_PORT (GPIO_PORTC_BASE) +#define USB0PFLT_PIN (GPIO_PIN_6) + +#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB) +#define USB0VBUS_PORT (GPIO_PORTB_BASE) +#define USB0VBUS_PIN (GPIO_PIN_1) + +#endif // PART_LM3S5762 + +//***************************************************************************** +// +// Pin Mapping Functions +// +// This section describes the code that is responsible for handling the +// mapping of peripheral functions to their physical location on the pins of +// a device. +// +//***************************************************************************** + +//***************************************************************************** +// +// Definitions to support mapping GPIO Ports and Pins to their function. +// +//***************************************************************************** + +//***************************************************************************** +// +// Configures the specified ADC pin to function as an ADC pin. +// +// \param ulName is one of the valid names for the ADC pins. +// +// This function takes on of the valid names for an ADC pin and configures +// the pin for its ADC functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2, +// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7. +// +// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeADC(ulName) GPIOPinTypeADC(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified CAN pin to function as a CAN pin. +// +// \param ulName is one of the valid names for the CAN pins. +// +// This function takes one of the valid names for a CAN pin and configures +// the pin for its CAN functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX, +// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX. +// +// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeCAN(ulName) GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified comparator pin to function as a comparator pin. +// +// \param ulName is one of the valid names for the Comparator pins. +// +// This function takes one of the valid names for a comparator pin and +// configures the pin for its comparator functionality depending on the part +// that is defined. +// +// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS, +// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS. +// +// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins +// at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeComparator(ulName) \ + GPIOPinTypeComparator(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified I2C pin to function as an I2C pin. +// +// \param ulName is one of the valid names for the I2C pins. +// +// This function takes one of the valid names for an I2C pin and configures +// the pin for its I2C functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA, +// \b I2C1SCL, or \b I2C1SDA. +// +// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified PWM pin to function as a PWM pin. +// +// \param ulName is one of the valid names for the PWM pins. +// +// This function takes one of the valid names for a PWM pin and configures +// the pin for its PWM functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2, +// \b PWM3, \b PWM4, \b PWM5, or \b FAULT. +// +// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypePWM(ulName) GPIOPinTypePWM(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified QEI pin to function as a QEI pin. +// +// \param ulName is one of the valid names for the QEI pins. +// +// This function takes one of the valid names for a QEI pin and configures +// the pin for its QEI functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0, +// \b PHA1, \b PHB1, or \b IDX1. +// +// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeQEI(ulName) GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified SSI pin to function as an SSI pin. +// +// \param ulName is one of the valid names for the SSI pins. +// +// This function takes one of the valid names for an SSI pin and configures +// the pin for its SSI functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS, +// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX. +// +// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeSSI(ulName) GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified Timer pin to function as a Timer pin. +// +// \param ulName is one of the valid names for the Timer pins. +// +// This function takes one of the valid names for a Timer pin and configures +// the pin for its Timer functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2, +// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7. +// +// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeTimer(ulName) GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified UART pin to function as a UART pin. +// +// \param ulName is one of the valid names for the UART pins. +// +// This function takes one of the valid names for a UART pin and configures +// the pin for its UART functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX, +// \b U1TX, \b U2RX, or \b U2TX. +// +// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeUART(ulName) GPIOPinTypeUART(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +//! Configures the specified USB digital pin to function as a USB pin. +//! +//! \param ulName is one of the valid names for a USB digital pin. +//! +//! This function takes one of the valid names for a USB digital pin and +//! configures the pin for its USB functionality depending on the part that is +//! defined. +//! +//! The valid names for the pins are as follows: \b EPEN or \b PFAULT. +//! +//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at +//! once. +//! +//! \return None. +// +//***************************************************************************** +#define PinTypeUSBDigital(ulName) \ + GPIOPinTypeUSBDigital(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +//! Enables the peripheral port used by the given pin. +//! +//! \param ulName is one of the valid names for a pin. +//! +//! This function takes one of the valid names for a pin function and +//! enables the peripheral port for that pin depending on the part that is +//! defined. +//! +//! Any valid pin name can be used. +//! +//! \sa SysCtlPeripheralEnable() in order to enable a single port when +//! multiple pins are on the same port. +//! +//! \return None. +// +//***************************************************************************** +#define PeripheralEnable(ulName) \ + SysCtlPeripheralEnable(ulName##_PERIPH) + +#endif // __PIN_MAP_H__ diff --git a/bsp/lm3s/driverlib/pwm.c b/bsp/lm3s/driverlib/pwm.c new file mode 100644 index 0000000000..1bbc52620d --- /dev/null +++ b/bsp/lm3s/driverlib/pwm.c @@ -0,0 +1,1728 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pwm.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \ + ((_mod_) + PWM_GEN_EXT_0 + \ + ((_gen_) - PWM_GEN_0) * 2) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! \internal +//! Checks a PWM generator number. +//! +//! \param ulGen is the generator number. +//! +//! This function determines if a PWM generator number is valid. +//! +//! \return Returnes \b true if the generator number is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +PWMGenValid(unsigned long ulGen) +{ + return((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2) || (ulGen == PWM_GEN_3)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a PWM output number. +//! +//! \param ulPWMOut is the output number. +//! +//! This function determines if a PWM output number is valid. +//! +//! \return Returns \b true if the output number is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +PWMOutValid(unsigned long ulPWMOut) +{ + return((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5) || + (ulPWMOut == PWM_OUT_6) || (ulPWMOut == PWM_OUT_7)); +} +#endif + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to configure. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulConfig is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it will count from a value down to zero, +//! and then reset to the preset value. This will produce left-aligned PWM +//! signals (that is the rising edge of the two PWM signals produced by the +//! generator will occur at the same time). In count up/down mode, it will +//! count up from zero to the preset value, count back down to zero, and then +//! repeat the process. This will produce center-aligned PWM signals (that is, +//! the middle of the high/low period of the PWM signals produced by the +//! generator will occur at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their affect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This allows multiple parameters to be modified and take affect +//! simultaneously, instead of one at a time. Additionally, parameters to +//! multiple PWM generators in synchronous mode can be updated simultaneously, +//! allowing them to be treated as if they were a unified generator. In +//! non-synchronous mode, the parameter updates are not delayed until a +//! synchronization event. In either mode, the parameter updates only occur +//! when the counter is at zero to help prevent oddly formed PWM signals during +//! the update (that is, a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it will continue to +//! count until it reaches zero, at which point it will pause until the +//! processor is restarted. If configured to continue running, it will keep +//! counting as if nothing had happened. +//! +//! The \e ulConfig parameter contains the desired configuration. It is the +//! logical OR of the following: +//! +//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting +//! mode +//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter +//! load and comparator update synchronization mode +//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior +//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or +//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization +//! mode for generator counting mode changes +//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or +//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter +//! synchronization mode +//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to +//! specify whether fault conditions are latched or not +//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to +//! specify whether minimum fault period support is required +//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify +//! whether extended fault source selection support is enabled or not +//! +//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the +//! minimum duration of a PWM fault signal. Fault will be signaled for at +//! least this time even if the external fault pin deasserts earlier. Care +//! should be taken when using this mode since during the fault signal period, +//! the fault interrupt from the PWM generator will remain asserted. The fault +//! interrupt handler may, therefore, reenter immediately if it exits prior to +//! expiration of the fault timer. +//! +//! \note Changes to the counter mode will affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Change the global configuration of the generator. + // + HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER | + PWM_X_CTL_FLTSRC | PWM_X_CTL_DBFALLUPD_M | + PWM_X_CTL_DBRISEUPD_M | + PWM_X_CTL_DBCTLUPD_M | + PWM_X_CTL_GENBUPD_M | + PWM_X_CTL_GENAUPD_M | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ulConfig); + + // + // Set the individual PWM generator controls. + // + if(ulConfig & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (that is, center align the + // signals). + // + HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE | + PWM_X_GENA_ACTCMPAD_ZERO); + HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE | + PWM_X_GENB_ACTCMPBD_ZERO); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (that is, left align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE | + PWM_X_GENA_ACTCMPAD_ZERO); + HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE | + PWM_X_GENB_ACTCMPBD_ZERO); + } +} + +//***************************************************************************** +// +//! Set the period of a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be modified. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulPeriod specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of PWM clock +//! ticks between pulses on the generator block zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ulPeriod / 2) < 65536); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; + } +} + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of PWM clock ticks +//! between pulses on the generator block zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in PWM clock ticks. +// +//***************************************************************************** +unsigned long +PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Figure out the counter mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ulGen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ulGen + PWM_O_X_LOAD) + 1); + } +} + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be enabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function allows the PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenEnable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be disabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function blocks the PWM clock from driving the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); +} + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5, +//! \b PWM_OUT_6, or \b PWM_OUT_7. +//! \param ulWidth specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth) +{ + unsigned long ulGenBase, ulReg; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMOutValid(ulPWMOut)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulWidth /= 2; + } + + // + // Get the period. + // + ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ulWidth < ulReg); + + // + // Compute the compare value. + // + ulReg = ulReg - ulWidth; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; + } + else + { + HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; + } +} + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5, +//! \b PWM_OUT_6, or \b PWM_OUT_7. +//! +//! This function gets the currently programmed pulse width for the specified +//! PWM output. If the update of the comparator for the specified output has +//! yet to be completed, the value returned may not be the active pulse width. +//! The value returned is the programmed pulse width, measured in PWM clock +//! ticks. +//! +//! \return Returns the width of the pulse in PWM clock ticks. +// +//***************************************************************************** +unsigned long +PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) +{ + unsigned long ulGenBase, ulReg, ulLoad; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMOutValid(ulPWMOut)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load - compare) * 2. Otherwise, set width = load - compare. + // + ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); + } + else + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); + } + ulReg = ulLoad - ulReg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulReg = ulReg * 2; + } + + // + // Return the pulse width. + // + return(ulReg); +} + +//***************************************************************************** +// +//! Enables the PWM dead band output, and sets the dead band delays. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param usRise specifies the width of delay from the rising edge. +//! \param usFall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, +//! where the dead bands are defined as the number of \b PWM clock ticks +//! from the rising or falling edge of the generator's \b OutA signal. +//! Note that this function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//***************************************************************************** +void +PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT(usRise < 4096); + ASSERT(usFall < 4096); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Write the dead band delay values. + // + HWREG(ulGen + PWM_O_X_DBRISE) = usRise; + HWREG(ulGen + PWM_O_X_DBFALL) = usFall; + + // + // Enable the deadband functionality. + // + HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +void +PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= + ~(PWM_X_DBCTL_ENABLE); +} + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be updated. Must be the +//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, +//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +void +PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | + PWM_GEN_3_BIT))); + + // + // Synchronize pending PWM register changes. + // + HWREG(ulBase + PWM_O_CTL) = ulGenBits; +} + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be +//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, +//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base +//! of the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +void +PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | + PWM_GEN_3_BIT))); + + // + // Synchronize the counters in the specified generators by writing to the + // module's synchronization register. + // + HWREG(ulBase + PWM_O_SYNC) = ulGenBits; +} + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, +//! or \b PWM_OUT_7_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function is used to enable or disable the selected PWM outputs. The +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's ENABLE output control register, and set or clear the + // requested bits. + // + if(bEnable == true) + { + HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or +//! \b PWM_OUT_7_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function will cause the specified +//! PWM output signals to be inverted, or made active low. If \e bInvert is +//! \b false, the specified output will be passed through as is, or be made +//! active high. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's INVERT output control register, and set or clear the + // requested bits. + // + if(bInvert == true) + { + HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Specifies the level of PWM outputs suppressed in response to a fault +//! condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or +//! \b PWM_OUT_7_BIT. +//! \param bDriveHigh determines if the signal is driven high or low during an +//! active fault condition. +//! +//! This function determines whether a PWM output pin that is suppressed in +//! response to a fault condition will be driven high or low. The affected +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bDriveHigh determines the output level for the pins identified by +//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs +//! will be driven high when a fault is detected. If it is \e false, the pins +//! will be driven low. +//! +//! In a fault condition, pins which have not been configured to be suppressed +//! via a call to PWMOutputFault() are unaffected by this function. +//! +//! \note This function is available only on devices which support extended +//! PWM fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bDriveHigh) +{ + // + // Check the arguments. + // + ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's FAULT output control register, and set or clear the + // requested bits. + // + if(bDriveHigh == true) + { + HWREG(ulBase + PWM_O_FAULTVAL) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULTVAL) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or +//! \b PWM_OUT_7_BIT. +//! \param bFaultSuppress determines if the signal is suppressed or passed +//! through during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bFaultSuppress determines the fault handling +//! characteristics for the selected outputs. If \e bFaultSuppress is \b true, +//! then the selected outputs will be made inactive. If \e bFaultSuppress is +//! \b false, then the selected outputs are unaffected by the detected fault. +//! +//! On devices supporting extended PWM fault handling, the state the affected +//! output pins are driven to can be configured with PWMOutputFaultLevel(). If +//! not configured, or if the device does not support extended PWM fault +//! handling, affected outputs will be driven low on a fault condition. +//! +//! \return None. +// +//***************************************************************************** +void +PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultSuppress) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | + PWM_OUT_6_BIT | PWM_OUT_7_BIT))); + + // + // Read the module's FAULT output control register, and set or clear the + // requested bits. + // + if(bFaultSuppress == true) + { + HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function will also enable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Get the interrupt number associated with the specified generator. + // + if(ulGen == PWM_GEN_3) + { + ulInt = INT_PWM3; + } + else + { + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + } + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! +//! This function will unregister the interrupt handler for the specified +//! PWM generator block. This function will also disable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Get the interrupt number associated with the specified generator. + // + if(ulGen == PWM_GEN_3) + { + ulInt = INT_PWM3; + } + else + { + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + } + + // + // Disable the PWMx interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function will also enable the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(INT_PWM_FAULT, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(INT_PWM_FAULT); +} + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function will remove the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function will also disable the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Disable the PWM fault interrupt. + // + IntDisable(INT_PWM_FAULT); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(INT_PWM_FAULT); +} + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers enabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulIntTrig specifies the interrupts and triggers to be enabled. +//! +//! Unmasks the specified interrupt(s) and trigger(s) by setting the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The \e ulIntTrig parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, +//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, +//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | + PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | + PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD | + PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU | + PWM_TR_CNT_BD)) == 0); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; +} + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers disabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulIntTrig specifies the interrupts and triggers to be disabled. +//! +//! Masks the specified interrupt(s) and trigger(s) by clearing the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The \e ulIntTrig parameter is the logical OR of +//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, +//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, +//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, +//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | + PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | + PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD | + PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU | + PWM_TR_CNT_BD)) == 0); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the contents of the interrupt status register, or the +//! contents of the raw interrupt status register, for the specified +//! PWM generator. +// +//***************************************************************************** +unsigned long +PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ulGen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ulGen + PWM_O_X_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulInts specifies the interrupts to be cleared. +//! +//! Clears the specified interrupt(s) by writing a 1 to the specified bits +//! of the interrupt status register for the specified PWM generator. The +//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO, +//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD, +//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | + PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == + 0); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; +} + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be enabled. Must be a logical +//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, +//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, +//! or \b PWM_INT_FAULT3. +//! +//! Unmasks the specified interrupt(s) by setting the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | + PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Read the module's interrupt enable register, and enable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; +} + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be disabled. Must be a +//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, +//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, +//! or \b PWM_INT_FAULT3. +//! +//! Masks the specified interrupt(s) by clearing the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +void +PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | + PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Read the module's interrupt enable register, and disable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); +} + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! Clears the fault interrupt by writing to the appropriate bit of the +//! interrupt status register for the selected PWM module. +//! +//! This function clears only the FAULT0 interrupt and is retained for +//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be +//! used instead since it supports all fault interrupts supported on devices +//! with and without extended PWM fault handling support. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0; +} + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, +//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and +//! \b PWM_INT_FAULT3. +//! +//***************************************************************************** +unsigned long +PWMIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ulBase + PWM_O_ISC)); + } + else + { + return(HWREG(ulBase + PWM_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulFaultInts specifies the fault interrupts to clear. +//! +//! Clears one or more fault interrupts by writing to the appropriate bit of +//! the PWM interrupt status register. The parameter \e ulFaultInts must be +//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, +//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. +//! +//! When running on a device supporting extended PWM fault handling, the fault +//! interrupts are derived by performing a logical OR of each of the configured +//! fault trigger signals for a given generator. Therefore, these interrupts +//! are not directly related to the four possible FAULTn inputs to the device +//! but indicate that a fault has been signaled to one of the four possible PWM +//! generators. On a device without extended PWM fault handling, the interrupt +//! is directly related to the state of the single FAULT pin. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several cycles before the interrupt source is actually cleared. Therefore, +//! it is recommended that the interrupt source be cleared early in the +//! interrupt handler (as opposed to the very last action) to avoid returning +//! from the interrupt handler before the interrupt source is actually cleared. +//! Failure to do so may result in the interrupt handler being immediately +//! reentered (since NVIC still sees the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 | + PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); + + // + // Clear the supplied fault bits. + // + HWREG(ulBase + PWM_O_ISC) = ulFaultInts; +} + +//***************************************************************************** +// +//! Configures the minimum fault period and fault pin senses for a given +//! PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator whose fault configuration is being set. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulMinFaultPeriod is the minimum fault active period expressed in +//! PWM clock cycles. +//! \param ulFaultSenses indicates which sense of each FAULT input should be +//! considered the ``asserted'' state. Valid values are logical OR +//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. +//! +//! This function sets the minimum fault period for a given generator along +//! with the sense of each of the 4 possible fault inputs. The minimum fault +//! period is expressed in PWM clock cycles and takes effect only if +//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the +//! \e ulConfig parameter. When a fault input is asserted, the minimum fault +//! period timer ensures that it remains asserted for at least the number of +//! clock cycles specified. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulMinFaultPeriod, + unsigned long ulFaultSenses) +{ + // + // Check the arguments. + // + ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M); + ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW | + PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW | + PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW | + PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) == + 0); + + // + // Write the minimum fault period. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod; + + // + // Write the fault senses. + // + HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses; +} + +//***************************************************************************** +// +//! Configures the set of fault triggers for a given PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator whose fault triggers are being set. Must +//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGroup indicates the subset of possible faults that are to be +//! configured. This must be \b PWM_FAULT_GROUP_0. +//! \param ulFaultTriggers defines the set of inputs that are to contribute +//! towards generation of the fault signal to the given PWM generator. For +//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0, +//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. +//! +//! This function allows selection of the set of fault inputs that will be +//! combined to generate a fault condition to a given PWM generator. By +//! default, all generators use only FAULT0 (for backwards compatibility) but +//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the +//! \e ulConfig parameter, extended fault handling is enabled and this function +//! must be called to configure the fault triggers. +//! +//! The fault signal to the PWM generator is generated by ORing together each +//! of the signals whose inputs are specified in the \e ulFaultTriggers +//! parameter after having adjusted the sense of each FAULTn input based on the +//! configuration previously set using a call to PWMGenFaultConfigure(). +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, unsigned long ulFaultTriggers) +{ + // + // Check for valid parameters. + // + ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | + PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0); + + // + // Write the fault triggers to the appropriate register. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) = + ulFaultTriggers; + } + else + { + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1) = + ulFaultTriggers; + } +} + +//***************************************************************************** +// +//! Returns the set of fault triggers currently configured for a given PWM +//! generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator whose fault triggers are being queried. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. +//! \param ulGroup indicates the subset of faults that are being queried. This +//! must be \b PWM_FAULT_GROUP_0. +//! +//! This function allows an application to query the current set of inputs that +//! contribute towards the generation of a fault condition to a given PWM +//! generator. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return Returns the current fault triggers configured for the fault group +//! provided. For \b PWM_FAULT_GROUP_0, the returned value will be a logical +//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. +// +//***************************************************************************** +unsigned long +PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup) +{ + // + // Check for valid parameters. + // + ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + + // + // Return the current fault triggers. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0)); + } + else + { + return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1)); + } +} + +//***************************************************************************** +// +//! Returns the current state of the fault triggers for a given PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator whose fault trigger states are being +//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. +//! \param ulGroup indicates the subset of faults that are being queried. This +//! must be \b PWM_FAULT_GROUP_0. +//! +//! This function allows an application to query the current state of each of +//! the fault trigger inputs to a given PWM generator. The current state of +//! each fault trigger input is returned unless PWMGenConfigure() has +//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the +//! \e ulConfig parameter in which case the returned status is the latched +//! fault trigger status. +//! +//! If latched faults are configured, the application must call +//! PWMGenFaultClear() to clear each trigger. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return Returns the current state of the fault triggers for the given PWM +//! generator. A set bit indicates that the associated trigger is active. For +//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of +//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or +//! \b PWM_FAULT_FAULT3. +// +//***************************************************************************** +unsigned long +PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup) +{ + // + // Check for valid parameters. + // + ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + + // + // Return the current fault status. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0)); + } + else + { + return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1)); + } +} + +//***************************************************************************** +// +//! Clears one or more latched fault triggers for a given PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator whose fault trigger states are being +//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or +//! \b PWM_GEN_3. +//! \param ulGroup indicates the subset of faults that are being queried. This +//! must be \b PWM_FAULT_GROUP_0. +//! \param ulFaultTriggers is the set of fault triggers which are to be +//! cleared. +//! +//! This function allows an application to clear the fault triggers for a given +//! PWM generator. This is only required if PWMGenConfigure() has previously +//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig. +//! +//! \note This function is only available on devices supporting extended PWM +//! fault handling. +//! +//! \return None. +// +//***************************************************************************** +void +PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, unsigned long ulFaultTriggers) +{ + // + // Check for valid parameters. + // + ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT); + ASSERT(ulBase == PWM_BASE); + ASSERT(PWMGenValid(ulGen)); + ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1)); + ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | + PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0); + + // + // Clear the given faults. + // + if(ulGroup == PWM_FAULT_GROUP_0) + { + HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) = + ulFaultTriggers; + } + else + { + HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1) = + ulFaultTriggers; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/pwm.h b/bsp/lm3s/driverlib/pwm.h new file mode 100644 index 0000000000..12cdc45b57 --- /dev/null +++ b/bsp/lm3s/driverlib/pwm.h @@ -0,0 +1,277 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#ifndef DEPRECATED +#define PWM_INT_FAULT 0x00010000 // Fault interrupt +#endif +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_1 1 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFaultLevel(unsigned long ulBase, + unsigned long ulPWMOutBits, + tBoolean bDriveHigh); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultSuppress); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void PWMFaultIntClearExt(unsigned long ulBase, + unsigned long ulFaultInts); +extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulMinFaultPeriod, + unsigned long ulFaultSenses); +extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); +extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern unsigned long PWMGenFaultStatus(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/bsp/lm3s/driverlib/qei.c b/bsp/lm3s/driverlib/qei.c new file mode 100644 index 0000000000..36207582c7 --- /dev/null +++ b/bsp/lm3s/driverlib/qei.c @@ -0,0 +1,619 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_qei.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the quadrature encoder module. It must be +//! configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +void +QEIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Enable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Disable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulConfig is the configuration for the quadrature encoder. See below +//! for a description of this parameter. +//! \param ulMaxPosition specifies the maximum position value. +//! +//! This will configure the operation of the quadrature encoder. The +//! \e ulConfig parameter provides the configuration of the encoder and is the +//! logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +void +QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Write the new configuration to the hardware. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ulConfig); + + // + // Set the maximum position. + // + HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current position of the encoder. Depending upon the +//! configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter will not be aligned with the index pulse yet). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +unsigned long +QEIPositionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the current position counter. + // + return(HWREG(ulBase + QEI_O_POS)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPosition is the new position for the encoder. +//! +//! This sets the current position of the encoder; the encoder position will +//! then be measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +void +QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Set the position counter. + // + HWREG(ulBase + QEI_O_POS) = ulPosition; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current direction of rotation. In this case, current +//! means the most recently detected direction of the encoder; it may not be +//! presently moving but this is the direction it last moved before it stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +long +QEIDirectionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the direction of rotation. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the error indicator for the quadrature encoder. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +tBoolean +QEIErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the error indicator. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the velocity capture in the quadrature +//! encoder module. It must be configured before it is enabled. Velocity +//! capture will not occur if the quadrature encoder is not enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Enable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; +} + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Disable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of \b QEI_VELDIV_1, +//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16, +//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128. +//! \param ulPeriod specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This will configure the operation of the velocity capture portion of the +//! quadrature encoder. The position increment signal is predivided as +//! specified by \e ulPreDiv before being accumulated by the velocity capture. +//! The divided signal is accumulated over \e ulPeriod system clock before +//! being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +void +QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ulPeriod != 0); + + // + // Set the velocity predivider. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ulPreDiv); + + // + // Set the timer period. + // + HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; +} + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current speed of the encoder. The value returned is the +//! number of pulses detected in the specified time period; this number can be +//! multiplied by the number of time periods per second and divided by the +//! number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return Returns the number of pulses captured in the given time period. +// +//***************************************************************************** +unsigned long +QEIVelocityGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return the speed capture value. + // + return(HWREG(ulBase + QEI_O_SPEED)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This sets the handler to be called when a quadrature encoder interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). +//! It is the interrupt handler's responsibility to clear the interrupt source +//! via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Determine the interrupt number based on the QEI module. + // + ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1; + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function will clear the handler to be called when a quadrature encoder +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Determine the interrupt number based on the QEI module. + // + ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or +//! \b QEI_INTINDEX values. +//! +//! Enables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or +//! \b QEI_INTINDEX values. +//! +//! Disables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the quadrature encoder module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. +// +//***************************************************************************** +unsigned long +QEIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + QEI_O_ISC)); + } + else + { + return(HWREG(ulBase + QEI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or +//! \b QEI_INTINDEX values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to keep +//! it from being called again immediately upon exit. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + QEI_O_ISC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/qei.h b/bsp/lm3s/driverlib/qei.h new file mode 100644 index 0000000000..4749f02e59 --- /dev/null +++ b/bsp/lm3s/driverlib/qei.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/bsp/lm3s/driverlib/readme.txt b/bsp/lm3s/driverlib/readme.txt new file mode 100644 index 0000000000..505472b922 --- /dev/null +++ b/bsp/lm3s/driverlib/readme.txt @@ -0,0 +1,24 @@ +This project will build the Stellaris Peripheral Driver Library. + +------------------------------------------------------------------------------- + +Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +Software License Agreement + +Luminary Micro, Inc. (LMI) is supplying this software for use solely and +exclusively on LMI's microcontroller products. + +The software is owned by LMI and/or its suppliers, and is protected under +applicable copyright laws. All rights are reserved. You may not combine +this software with "viral" open-source software in order to form a larger +program. Any use in violation of the foregoing restrictions may subject +the user to criminal sanctions under applicable laws, as well as to civil +liability for the breach of the terms and conditions of this license. + +THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + +This is part of revision 4694 of the Stellaris Peripheral Driver Library. diff --git a/bsp/lm3s/driverlib/rom.h b/bsp/lm3s/driverlib/rom.h new file mode 100644 index 0000000000..211743f3bd --- /dev/null +++ b/bsp/lm3s/driverlib/rom.h @@ -0,0 +1,2252 @@ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((unsigned long *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14])) +#define ROM_ETHERNETTABLE ((unsigned long *)(ROM_APITABLE[15])) +#define ROM_USBTABLE ((unsigned long *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((unsigned long *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((unsigned long *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long *pulBuffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + tBoolean bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulTrigger, \ + unsigned long ulPriority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulStep, \ + unsigned long ulConfig))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceOverflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceUnderflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCProcessorTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFactor))ROM_ADCTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAN API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANInit \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANEnable \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANDisable \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANBitTimingSet \ + ((void (*)(unsigned long ulBase, \ + tCANBitClkParms *pClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANBitTimingGet \ + ((void (*)(unsigned long ulBase, \ + tCANBitClkParms *pClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANMessageSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID, \ + tCANMsgObject *pMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANMessageGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID, \ + tCANMsgObject *pMsgObject, \ + tBoolean bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANMessageClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANRetryGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANRetrySet \ + ((void (*)(unsigned long ulBase, \ + tBoolean bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_CANErrCntrGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long *pulRxCount, \ + unsigned long *pulTxCount))ROM_CANTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulConfig))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorRefSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorValueGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_ComparatorIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + tBoolean bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Ethernet API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEthClk))ROM_ETHERNETTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_ETHERNETTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetMACAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetMACAddrGet \ + ((void (*)(unsigned long ulBase, \ + unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetEnable \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetDisable \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPacketAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPacketGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPacketGet \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPacketPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPacketPut \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_ETHERNETTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPHYWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucRegAddr, \ + unsigned long ulData))ROM_ETHERNETTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_EthernetPHYRead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned char ucRegAddr))ROM_ETHERNETTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UpdateEthernet \ + ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashProgram \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashUsecGet \ + ((unsigned long (*)(void))ROM_FLASHTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashUsecSet \ + ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashErase \ + ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashProtectSet \ + ((long (*)(unsigned long ulAddress, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashProtectSave \ + ((long (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashUserGet \ + ((long (*)(unsigned long *pulUser0, \ + unsigned long *pulUser1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashUserSet \ + ((long (*)(unsigned long ulUser0, \ + unsigned long ulUser1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashUserSave \ + ((long (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashIntGetStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_FlashIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinWrite \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned char ucVal))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIODirModeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulPinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIODirModeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOIntTypeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulIntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOIntTypeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPadConfigSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulStrength, \ + unsigned long ulPadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPadConfigGet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPin, \ + unsigned long *pulStrength, \ + unsigned long *pulPadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinIntEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinIntDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinIntStatus \ + ((long (*)(unsigned long ulPort, \ + tBoolean bMasked))ROM_GPIOTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinIntClear \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinRead \ + ((long (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypePWM \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeUART \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeADC \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[24]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Hibernate API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateEnableExpClk \ + ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateClockSelect \ + ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateWakeSet \ + ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateWakeGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateLowBatSet \ + ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateLowBatGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCSet \ + ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCMatch0Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCMatch0Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCMatch1Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCMatch1Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRTCTrimGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateDataSet \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulCount))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateDataGet \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulCount))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_HibernateIsActive \ + ((unsigned int (*)(void))ROM_HIBERNATETABLE[24]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulI2CClk, \ + tBoolean bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveInit \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr, \ + tBoolean bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterBusBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterErr \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CMasterDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_I2CSlaveDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntEnable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntMasterEnable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntMasterDisable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntDisable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntPriorityGroupingGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntPrioritySet \ + ((void (*)(unsigned long ulInterrupt, \ + unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_IntPriorityGet \ + ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the MPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPUEnable \ + ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPURegionCountGet \ + ((unsigned long (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPURegionEnable \ + ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPURegionDisable \ + ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPURegionSet \ + ((void (*)(unsigned long ulRegion, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_MPURegionGet \ + ((void (*)(unsigned long ulRegion, \ + unsigned long *pulAddr, \ + unsigned long *pulFlags))ROM_MPUTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMPulseWidthSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOut, \ + unsigned long ulWidth))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulConfig))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenPeriodSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulPeriod))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenPeriodGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMPulseWidthGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulPWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMDeadBandEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned short usRise, \ + unsigned short usFall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMDeadBandDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMSyncUpdate \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMSyncTimeBase \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMOutputState \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMOutputInvert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMOutputFault \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + tBoolean bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulInts))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMFaultIntClear \ + ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulMinFaultPeriod, \ + unsigned long ulFaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup, \ + unsigned long ulFaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenFaultTriggerGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenFaultStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_PWMGenFaultClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup, \ + unsigned long ulFaultTriggers))ROM_PWMTABLE[28]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIPositionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIPositionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPosition))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIDirectionGet \ + ((long (*)(unsigned long ulBase))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIErrorGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIVelocityEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIVelocityDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIVelocityConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPreDiv, \ + unsigned long ulPeriod))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIVelocityGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_QEIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSSIClk, \ + unsigned long ulProtocol, \ + unsigned long ulMode, \ + unsigned long ulBitRate, \ + unsigned long ulDataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIEnable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDisable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SSIDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_SSITABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlSRAMSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlFlashSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPinPresent \ + ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralPresent \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlIntEnable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlIntDisable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlIntClear \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlLDOSet \ + ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlLDOGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlResetCauseGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlPWMClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlADCSpeedSet \ + ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlADCSpeedGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[28]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlGPIOAHBEnable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlGPIOAHBDisable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickValueGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickPeriodSet \ + ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_SysTickPeriodGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerControlLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerControlTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerControlEvent \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulEvent))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerControlStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerRTCEnable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerRTCDisable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerPrescaleSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerPrescaleGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerLoadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerLoadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_TimerIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_TIMERTABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTCharPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTParityModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulParity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTParityModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long ulBaud, \ + unsigned long ulConfig))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long *pulBaud, \ + unsigned long *pulConfig))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTEnableSIR \ + ((void (*)(unsigned long ulBase, \ + tBoolean bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTDisableSIR \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTCharsAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTCharGetNonBlocking \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTCharGet \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTCharPutNonBlocking \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTBreakCtl \ + ((void (*)(unsigned long ulBase, \ + tBoolean bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_UARTDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(unsigned long ulChannel, \ + unsigned long ulMode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + unsigned long ulTransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAErrorStatusGet \ + ((unsigned long (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelEnable \ + ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelDisable \ + ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelIsEnabled \ + ((tBoolean (*)(unsigned long ulChannel))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelRequest \ + ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(unsigned long ulChannel, \ + unsigned long ulAttr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(unsigned long ulChannel, \ + unsigned long ulAttr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelAttributeGet \ + ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelControlSet \ + ((void (*)(unsigned long ulChannel, \ + unsigned long ulControl))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelSizeGet \ + ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_uDMAChannelModeGet \ + ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the USB API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevAddrGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulAddress))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevConnect \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevDisconnect \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevEndpointConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulMaxPacketSize, \ + unsigned long ulFlags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + tBoolean bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevEndpointStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBEndpointDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned char *pucData, \ + unsigned long *pulSize))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBEndpointDataPut \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned char *pucData, \ + unsigned long ulSize))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBEndpointDataSend \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulTransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBEndpointStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBFIFOAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBFIFOConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long *pulFIFOAddress, \ + unsigned long *pulFIFOSize, \ + unsigned long ulFlags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBFIFOConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFIFOAddress, \ + unsigned long ulFIFOSize, \ + unsigned long ulFlags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBFIFOFlush \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBFrameNumberGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostEndpointConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulMaxPacketSize, \ + unsigned long ulNAKPollInterval, \ + unsigned long ulTargetEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + tBoolean bDataToggle, \ + unsigned long ulFlags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostHubAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostHubAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostPwrDisable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostPwrEnable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostPwrFaultConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostRequestIN \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostRequestStatus \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostReset \ + ((void (*)(unsigned long ulBase, \ + tBoolean bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostResume \ + ((void (*)(unsigned long ulBase, \ + tBoolean bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostSpeedGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBHostSuspend \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[39]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_USBIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[40]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogIntClear \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogRunning \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogResetEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogResetDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogLock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogUnlock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogLockState \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogReloadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogReloadGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogIntEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogStallEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) +#define ROM_WatchdogStallDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Software API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_Crc16Array \ + ((unsigned short (*)(unsigned long ulWordLen, \ + unsigned long *pulData))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_Crc16Array3 \ + ((void (*)(unsigned long ulWordLen, \ + unsigned long *pulData, \ + unsigned short *pusCrc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +#endif // __ROM_H__ diff --git a/bsp/lm3s/driverlib/rom_map.h b/bsp/lm3s/driverlib/rom_map.h new file mode 100644 index 0000000000..2a9d296641 --- /dev/null +++ b/bsp/lm3s/driverlib/rom_map.h @@ -0,0 +1,2763 @@ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available and in flash otherwise. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCSequenceDataGet +#define MAP_ADCSequenceDataGet \ + ROM_ADCSequenceDataGet +#else +#define MAP_ADCSequenceDataGet \ + ADCSequenceDataGet +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCSequenceEnable +#define MAP_ADCSequenceEnable \ + ROM_ADCSequenceEnable +#else +#define MAP_ADCSequenceEnable \ + ADCSequenceEnable +#endif +#ifdef ROM_ADCSequenceDisable +#define MAP_ADCSequenceDisable \ + ROM_ADCSequenceDisable +#else +#define MAP_ADCSequenceDisable \ + ADCSequenceDisable +#endif +#ifdef ROM_ADCSequenceConfigure +#define MAP_ADCSequenceConfigure \ + ROM_ADCSequenceConfigure +#else +#define MAP_ADCSequenceConfigure \ + ADCSequenceConfigure +#endif +#ifdef ROM_ADCSequenceStepConfigure +#define MAP_ADCSequenceStepConfigure \ + ROM_ADCSequenceStepConfigure +#else +#define MAP_ADCSequenceStepConfigure \ + ADCSequenceStepConfigure +#endif +#ifdef ROM_ADCSequenceOverflow +#define MAP_ADCSequenceOverflow \ + ROM_ADCSequenceOverflow +#else +#define MAP_ADCSequenceOverflow \ + ADCSequenceOverflow +#endif +#ifdef ROM_ADCSequenceOverflowClear +#define MAP_ADCSequenceOverflowClear \ + ROM_ADCSequenceOverflowClear +#else +#define MAP_ADCSequenceOverflowClear \ + ADCSequenceOverflowClear +#endif +#ifdef ROM_ADCSequenceUnderflow +#define MAP_ADCSequenceUnderflow \ + ROM_ADCSequenceUnderflow +#else +#define MAP_ADCSequenceUnderflow \ + ADCSequenceUnderflow +#endif +#ifdef ROM_ADCSequenceUnderflowClear +#define MAP_ADCSequenceUnderflowClear \ + ROM_ADCSequenceUnderflowClear +#else +#define MAP_ADCSequenceUnderflowClear \ + ADCSequenceUnderflowClear +#endif +#ifdef ROM_ADCProcessorTrigger +#define MAP_ADCProcessorTrigger \ + ROM_ADCProcessorTrigger +#else +#define MAP_ADCProcessorTrigger \ + ADCProcessorTrigger +#endif +#ifdef ROM_ADCHardwareOversampleConfigure +#define MAP_ADCHardwareOversampleConfigure \ + ROM_ADCHardwareOversampleConfigure +#else +#define MAP_ADCHardwareOversampleConfigure \ + ADCHardwareOversampleConfigure +#endif + +//***************************************************************************** +// +// Macros for the CAN API. +// +//***************************************************************************** +#ifdef ROM_CANIntClear +#define MAP_CANIntClear \ + ROM_CANIntClear +#else +#define MAP_CANIntClear \ + CANIntClear +#endif +#ifdef ROM_CANInit +#define MAP_CANInit \ + ROM_CANInit +#else +#define MAP_CANInit \ + CANInit +#endif +#ifdef ROM_CANEnable +#define MAP_CANEnable \ + ROM_CANEnable +#else +#define MAP_CANEnable \ + CANEnable +#endif +#ifdef ROM_CANDisable +#define MAP_CANDisable \ + ROM_CANDisable +#else +#define MAP_CANDisable \ + CANDisable +#endif +#ifdef ROM_CANBitTimingSet +#define MAP_CANBitTimingSet \ + ROM_CANBitTimingSet +#else +#define MAP_CANBitTimingSet \ + CANBitTimingSet +#endif +#ifdef ROM_CANBitTimingGet +#define MAP_CANBitTimingGet \ + ROM_CANBitTimingGet +#else +#define MAP_CANBitTimingGet \ + CANBitTimingGet +#endif +#ifdef ROM_CANMessageSet +#define MAP_CANMessageSet \ + ROM_CANMessageSet +#else +#define MAP_CANMessageSet \ + CANMessageSet +#endif +#ifdef ROM_CANMessageGet +#define MAP_CANMessageGet \ + ROM_CANMessageGet +#else +#define MAP_CANMessageGet \ + CANMessageGet +#endif +#ifdef ROM_CANStatusGet +#define MAP_CANStatusGet \ + ROM_CANStatusGet +#else +#define MAP_CANStatusGet \ + CANStatusGet +#endif +#ifdef ROM_CANMessageClear +#define MAP_CANMessageClear \ + ROM_CANMessageClear +#else +#define MAP_CANMessageClear \ + CANMessageClear +#endif +#ifdef ROM_CANIntEnable +#define MAP_CANIntEnable \ + ROM_CANIntEnable +#else +#define MAP_CANIntEnable \ + CANIntEnable +#endif +#ifdef ROM_CANIntDisable +#define MAP_CANIntDisable \ + ROM_CANIntDisable +#else +#define MAP_CANIntDisable \ + CANIntDisable +#endif +#ifdef ROM_CANIntStatus +#define MAP_CANIntStatus \ + ROM_CANIntStatus +#else +#define MAP_CANIntStatus \ + CANIntStatus +#endif +#ifdef ROM_CANRetryGet +#define MAP_CANRetryGet \ + ROM_CANRetryGet +#else +#define MAP_CANRetryGet \ + CANRetryGet +#endif +#ifdef ROM_CANRetrySet +#define MAP_CANRetrySet \ + ROM_CANRetrySet +#else +#define MAP_CANRetrySet \ + CANRetrySet +#endif +#ifdef ROM_CANErrCntrGet +#define MAP_CANErrCntrGet \ + ROM_CANErrCntrGet +#else +#define MAP_CANErrCntrGet \ + CANErrCntrGet +#endif + +//***************************************************************************** +// +// Macros for the Comparator API. +// +//***************************************************************************** +#ifdef ROM_ComparatorIntClear +#define MAP_ComparatorIntClear \ + ROM_ComparatorIntClear +#else +#define MAP_ComparatorIntClear \ + ComparatorIntClear +#endif +#ifdef ROM_ComparatorConfigure +#define MAP_ComparatorConfigure \ + ROM_ComparatorConfigure +#else +#define MAP_ComparatorConfigure \ + ComparatorConfigure +#endif +#ifdef ROM_ComparatorRefSet +#define MAP_ComparatorRefSet \ + ROM_ComparatorRefSet +#else +#define MAP_ComparatorRefSet \ + ComparatorRefSet +#endif +#ifdef ROM_ComparatorValueGet +#define MAP_ComparatorValueGet \ + ROM_ComparatorValueGet +#else +#define MAP_ComparatorValueGet \ + ComparatorValueGet +#endif +#ifdef ROM_ComparatorIntEnable +#define MAP_ComparatorIntEnable \ + ROM_ComparatorIntEnable +#else +#define MAP_ComparatorIntEnable \ + ComparatorIntEnable +#endif +#ifdef ROM_ComparatorIntDisable +#define MAP_ComparatorIntDisable \ + ROM_ComparatorIntDisable +#else +#define MAP_ComparatorIntDisable \ + ComparatorIntDisable +#endif +#ifdef ROM_ComparatorIntStatus +#define MAP_ComparatorIntStatus \ + ROM_ComparatorIntStatus +#else +#define MAP_ComparatorIntStatus \ + ComparatorIntStatus +#endif + +//***************************************************************************** +// +// Macros for the Ethernet API. +// +//***************************************************************************** +#ifdef ROM_EthernetIntClear +#define MAP_EthernetIntClear \ + ROM_EthernetIntClear +#else +#define MAP_EthernetIntClear \ + EthernetIntClear +#endif +#ifdef ROM_EthernetInitExpClk +#define MAP_EthernetInitExpClk \ + ROM_EthernetInitExpClk +#else +#define MAP_EthernetInitExpClk \ + EthernetInitExpClk +#endif +#ifdef ROM_EthernetConfigSet +#define MAP_EthernetConfigSet \ + ROM_EthernetConfigSet +#else +#define MAP_EthernetConfigSet \ + EthernetConfigSet +#endif +#ifdef ROM_EthernetConfigGet +#define MAP_EthernetConfigGet \ + ROM_EthernetConfigGet +#else +#define MAP_EthernetConfigGet \ + EthernetConfigGet +#endif +#ifdef ROM_EthernetMACAddrSet +#define MAP_EthernetMACAddrSet \ + ROM_EthernetMACAddrSet +#else +#define MAP_EthernetMACAddrSet \ + EthernetMACAddrSet +#endif +#ifdef ROM_EthernetMACAddrGet +#define MAP_EthernetMACAddrGet \ + ROM_EthernetMACAddrGet +#else +#define MAP_EthernetMACAddrGet \ + EthernetMACAddrGet +#endif +#ifdef ROM_EthernetEnable +#define MAP_EthernetEnable \ + ROM_EthernetEnable +#else +#define MAP_EthernetEnable \ + EthernetEnable +#endif +#ifdef ROM_EthernetDisable +#define MAP_EthernetDisable \ + ROM_EthernetDisable +#else +#define MAP_EthernetDisable \ + EthernetDisable +#endif +#ifdef ROM_EthernetPacketAvail +#define MAP_EthernetPacketAvail \ + ROM_EthernetPacketAvail +#else +#define MAP_EthernetPacketAvail \ + EthernetPacketAvail +#endif +#ifdef ROM_EthernetSpaceAvail +#define MAP_EthernetSpaceAvail \ + ROM_EthernetSpaceAvail +#else +#define MAP_EthernetSpaceAvail \ + EthernetSpaceAvail +#endif +#ifdef ROM_EthernetPacketGetNonBlocking +#define MAP_EthernetPacketGetNonBlocking \ + ROM_EthernetPacketGetNonBlocking +#else +#define MAP_EthernetPacketGetNonBlocking \ + EthernetPacketGetNonBlocking +#endif +#ifdef ROM_EthernetPacketGet +#define MAP_EthernetPacketGet \ + ROM_EthernetPacketGet +#else +#define MAP_EthernetPacketGet \ + EthernetPacketGet +#endif +#ifdef ROM_EthernetPacketPutNonBlocking +#define MAP_EthernetPacketPutNonBlocking \ + ROM_EthernetPacketPutNonBlocking +#else +#define MAP_EthernetPacketPutNonBlocking \ + EthernetPacketPutNonBlocking +#endif +#ifdef ROM_EthernetPacketPut +#define MAP_EthernetPacketPut \ + ROM_EthernetPacketPut +#else +#define MAP_EthernetPacketPut \ + EthernetPacketPut +#endif +#ifdef ROM_EthernetIntEnable +#define MAP_EthernetIntEnable \ + ROM_EthernetIntEnable +#else +#define MAP_EthernetIntEnable \ + EthernetIntEnable +#endif +#ifdef ROM_EthernetIntDisable +#define MAP_EthernetIntDisable \ + ROM_EthernetIntDisable +#else +#define MAP_EthernetIntDisable \ + EthernetIntDisable +#endif +#ifdef ROM_EthernetIntStatus +#define MAP_EthernetIntStatus \ + ROM_EthernetIntStatus +#else +#define MAP_EthernetIntStatus \ + EthernetIntStatus +#endif +#ifdef ROM_EthernetPHYWrite +#define MAP_EthernetPHYWrite \ + ROM_EthernetPHYWrite +#else +#define MAP_EthernetPHYWrite \ + EthernetPHYWrite +#endif +#ifdef ROM_EthernetPHYRead +#define MAP_EthernetPHYRead \ + ROM_EthernetPHYRead +#else +#define MAP_EthernetPHYRead \ + EthernetPHYRead +#endif + +//***************************************************************************** +// +// Macros for the Flash API. +// +//***************************************************************************** +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashUsecGet +#define MAP_FlashUsecGet \ + ROM_FlashUsecGet +#else +#define MAP_FlashUsecGet \ + FlashUsecGet +#endif +#ifdef ROM_FlashUsecSet +#define MAP_FlashUsecSet \ + ROM_FlashUsecSet +#else +#define MAP_FlashUsecSet \ + FlashUsecSet +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif +#ifdef ROM_FlashProtectSet +#define MAP_FlashProtectSet \ + ROM_FlashProtectSet +#else +#define MAP_FlashProtectSet \ + FlashProtectSet +#endif +#ifdef ROM_FlashProtectSave +#define MAP_FlashProtectSave \ + ROM_FlashProtectSave +#else +#define MAP_FlashProtectSave \ + FlashProtectSave +#endif +#ifdef ROM_FlashUserGet +#define MAP_FlashUserGet \ + ROM_FlashUserGet +#else +#define MAP_FlashUserGet \ + FlashUserGet +#endif +#ifdef ROM_FlashUserSet +#define MAP_FlashUserSet \ + ROM_FlashUserSet +#else +#define MAP_FlashUserSet \ + FlashUserSet +#endif +#ifdef ROM_FlashUserSave +#define MAP_FlashUserSave \ + ROM_FlashUserSave +#else +#define MAP_FlashUserSave \ + FlashUserSave +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntGetStatus +#define MAP_FlashIntGetStatus \ + ROM_FlashIntGetStatus +#else +#define MAP_FlashIntGetStatus \ + FlashIntGetStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOPadConfigSet +#define MAP_GPIOPadConfigSet \ + ROM_GPIOPadConfigSet +#else +#define MAP_GPIOPadConfigSet \ + GPIOPadConfigSet +#endif +#ifdef ROM_GPIOPadConfigGet +#define MAP_GPIOPadConfigGet \ + ROM_GPIOPadConfigGet +#else +#define MAP_GPIOPadConfigGet \ + GPIOPadConfigGet +#endif +#ifdef ROM_GPIOPinIntEnable +#define MAP_GPIOPinIntEnable \ + ROM_GPIOPinIntEnable +#else +#define MAP_GPIOPinIntEnable \ + GPIOPinIntEnable +#endif +#ifdef ROM_GPIOPinIntDisable +#define MAP_GPIOPinIntDisable \ + ROM_GPIOPinIntDisable +#else +#define MAP_GPIOPinIntDisable \ + GPIOPinIntDisable +#endif +#ifdef ROM_GPIOPinIntStatus +#define MAP_GPIOPinIntStatus \ + ROM_GPIOPinIntStatus +#else +#define MAP_GPIOPinIntStatus \ + GPIOPinIntStatus +#endif +#ifdef ROM_GPIOPinIntClear +#define MAP_GPIOPinIntClear \ + ROM_GPIOPinIntClear +#else +#define MAP_GPIOPinIntClear \ + GPIOPinIntClear +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinTypeCAN +#define MAP_GPIOPinTypeCAN \ + ROM_GPIOPinTypeCAN +#else +#define MAP_GPIOPinTypeCAN \ + GPIOPinTypeCAN +#endif +#ifdef ROM_GPIOPinTypeComparator +#define MAP_GPIOPinTypeComparator \ + ROM_GPIOPinTypeComparator +#else +#define MAP_GPIOPinTypeComparator \ + GPIOPinTypeComparator +#endif +#ifdef ROM_GPIOPinTypeGPIOInput +#define MAP_GPIOPinTypeGPIOInput \ + ROM_GPIOPinTypeGPIOInput +#else +#define MAP_GPIOPinTypeGPIOInput \ + GPIOPinTypeGPIOInput +#endif +#ifdef ROM_GPIOPinTypeGPIOOutput +#define MAP_GPIOPinTypeGPIOOutput \ + ROM_GPIOPinTypeGPIOOutput +#else +#define MAP_GPIOPinTypeGPIOOutput \ + GPIOPinTypeGPIOOutput +#endif +#ifdef ROM_GPIOPinTypeI2C +#define MAP_GPIOPinTypeI2C \ + ROM_GPIOPinTypeI2C +#else +#define MAP_GPIOPinTypeI2C \ + GPIOPinTypeI2C +#endif +#ifdef ROM_GPIOPinTypePWM +#define MAP_GPIOPinTypePWM \ + ROM_GPIOPinTypePWM +#else +#define MAP_GPIOPinTypePWM \ + GPIOPinTypePWM +#endif +#ifdef ROM_GPIOPinTypeQEI +#define MAP_GPIOPinTypeQEI \ + ROM_GPIOPinTypeQEI +#else +#define MAP_GPIOPinTypeQEI \ + GPIOPinTypeQEI +#endif +#ifdef ROM_GPIOPinTypeSSI +#define MAP_GPIOPinTypeSSI \ + ROM_GPIOPinTypeSSI +#else +#define MAP_GPIOPinTypeSSI \ + GPIOPinTypeSSI +#endif +#ifdef ROM_GPIOPinTypeTimer +#define MAP_GPIOPinTypeTimer \ + ROM_GPIOPinTypeTimer +#else +#define MAP_GPIOPinTypeTimer \ + GPIOPinTypeTimer +#endif +#ifdef ROM_GPIOPinTypeUART +#define MAP_GPIOPinTypeUART \ + ROM_GPIOPinTypeUART +#else +#define MAP_GPIOPinTypeUART \ + GPIOPinTypeUART +#endif +#ifdef ROM_GPIOPinTypeGPIOOutputOD +#define MAP_GPIOPinTypeGPIOOutputOD \ + ROM_GPIOPinTypeGPIOOutputOD +#else +#define MAP_GPIOPinTypeGPIOOutputOD \ + GPIOPinTypeGPIOOutputOD +#endif +#ifdef ROM_GPIOPinTypeADC +#define MAP_GPIOPinTypeADC \ + ROM_GPIOPinTypeADC +#else +#define MAP_GPIOPinTypeADC \ + GPIOPinTypeADC +#endif +#ifdef ROM_GPIOPinTypeUSBDigital +#define MAP_GPIOPinTypeUSBDigital \ + ROM_GPIOPinTypeUSBDigital +#else +#define MAP_GPIOPinTypeUSBDigital \ + GPIOPinTypeUSBDigital +#endif + +//***************************************************************************** +// +// Macros for the Hibernate API. +// +//***************************************************************************** +#ifdef ROM_HibernateIntClear +#define MAP_HibernateIntClear \ + ROM_HibernateIntClear +#else +#define MAP_HibernateIntClear \ + HibernateIntClear +#endif +#ifdef ROM_HibernateEnableExpClk +#define MAP_HibernateEnableExpClk \ + ROM_HibernateEnableExpClk +#else +#define MAP_HibernateEnableExpClk \ + HibernateEnableExpClk +#endif +#ifdef ROM_HibernateDisable +#define MAP_HibernateDisable \ + ROM_HibernateDisable +#else +#define MAP_HibernateDisable \ + HibernateDisable +#endif +#ifdef ROM_HibernateClockSelect +#define MAP_HibernateClockSelect \ + ROM_HibernateClockSelect +#else +#define MAP_HibernateClockSelect \ + HibernateClockSelect +#endif +#ifdef ROM_HibernateRTCEnable +#define MAP_HibernateRTCEnable \ + ROM_HibernateRTCEnable +#else +#define MAP_HibernateRTCEnable \ + HibernateRTCEnable +#endif +#ifdef ROM_HibernateRTCDisable +#define MAP_HibernateRTCDisable \ + ROM_HibernateRTCDisable +#else +#define MAP_HibernateRTCDisable \ + HibernateRTCDisable +#endif +#ifdef ROM_HibernateWakeSet +#define MAP_HibernateWakeSet \ + ROM_HibernateWakeSet +#else +#define MAP_HibernateWakeSet \ + HibernateWakeSet +#endif +#ifdef ROM_HibernateWakeGet +#define MAP_HibernateWakeGet \ + ROM_HibernateWakeGet +#else +#define MAP_HibernateWakeGet \ + HibernateWakeGet +#endif +#ifdef ROM_HibernateLowBatSet +#define MAP_HibernateLowBatSet \ + ROM_HibernateLowBatSet +#else +#define MAP_HibernateLowBatSet \ + HibernateLowBatSet +#endif +#ifdef ROM_HibernateLowBatGet +#define MAP_HibernateLowBatGet \ + ROM_HibernateLowBatGet +#else +#define MAP_HibernateLowBatGet \ + HibernateLowBatGet +#endif +#ifdef ROM_HibernateRTCSet +#define MAP_HibernateRTCSet \ + ROM_HibernateRTCSet +#else +#define MAP_HibernateRTCSet \ + HibernateRTCSet +#endif +#ifdef ROM_HibernateRTCGet +#define MAP_HibernateRTCGet \ + ROM_HibernateRTCGet +#else +#define MAP_HibernateRTCGet \ + HibernateRTCGet +#endif +#ifdef ROM_HibernateRTCMatch0Set +#define MAP_HibernateRTCMatch0Set \ + ROM_HibernateRTCMatch0Set +#else +#define MAP_HibernateRTCMatch0Set \ + HibernateRTCMatch0Set +#endif +#ifdef ROM_HibernateRTCMatch0Get +#define MAP_HibernateRTCMatch0Get \ + ROM_HibernateRTCMatch0Get +#else +#define MAP_HibernateRTCMatch0Get \ + HibernateRTCMatch0Get +#endif +#ifdef ROM_HibernateRTCMatch1Set +#define MAP_HibernateRTCMatch1Set \ + ROM_HibernateRTCMatch1Set +#else +#define MAP_HibernateRTCMatch1Set \ + HibernateRTCMatch1Set +#endif +#ifdef ROM_HibernateRTCMatch1Get +#define MAP_HibernateRTCMatch1Get \ + ROM_HibernateRTCMatch1Get +#else +#define MAP_HibernateRTCMatch1Get \ + HibernateRTCMatch1Get +#endif +#ifdef ROM_HibernateRTCTrimSet +#define MAP_HibernateRTCTrimSet \ + ROM_HibernateRTCTrimSet +#else +#define MAP_HibernateRTCTrimSet \ + HibernateRTCTrimSet +#endif +#ifdef ROM_HibernateRTCTrimGet +#define MAP_HibernateRTCTrimGet \ + ROM_HibernateRTCTrimGet +#else +#define MAP_HibernateRTCTrimGet \ + HibernateRTCTrimGet +#endif +#ifdef ROM_HibernateDataSet +#define MAP_HibernateDataSet \ + ROM_HibernateDataSet +#else +#define MAP_HibernateDataSet \ + HibernateDataSet +#endif +#ifdef ROM_HibernateDataGet +#define MAP_HibernateDataGet \ + ROM_HibernateDataGet +#else +#define MAP_HibernateDataGet \ + HibernateDataGet +#endif +#ifdef ROM_HibernateRequest +#define MAP_HibernateRequest \ + ROM_HibernateRequest +#else +#define MAP_HibernateRequest \ + HibernateRequest +#endif +#ifdef ROM_HibernateIntEnable +#define MAP_HibernateIntEnable \ + ROM_HibernateIntEnable +#else +#define MAP_HibernateIntEnable \ + HibernateIntEnable +#endif +#ifdef ROM_HibernateIntDisable +#define MAP_HibernateIntDisable \ + ROM_HibernateIntDisable +#else +#define MAP_HibernateIntDisable \ + HibernateIntDisable +#endif +#ifdef ROM_HibernateIntStatus +#define MAP_HibernateIntStatus \ + ROM_HibernateIntStatus +#else +#define MAP_HibernateIntStatus \ + HibernateIntStatus +#endif +#ifdef ROM_HibernateIsActive +#define MAP_HibernateIsActive \ + ROM_HibernateIsActive +#else +#define MAP_HibernateIsActive \ + HibernateIsActive +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif + +//***************************************************************************** +// +// Macros for the MPU API. +// +//***************************************************************************** +#ifdef ROM_MPUEnable +#define MAP_MPUEnable \ + ROM_MPUEnable +#else +#define MAP_MPUEnable \ + MPUEnable +#endif +#ifdef ROM_MPUDisable +#define MAP_MPUDisable \ + ROM_MPUDisable +#else +#define MAP_MPUDisable \ + MPUDisable +#endif +#ifdef ROM_MPURegionCountGet +#define MAP_MPURegionCountGet \ + ROM_MPURegionCountGet +#else +#define MAP_MPURegionCountGet \ + MPURegionCountGet +#endif +#ifdef ROM_MPURegionEnable +#define MAP_MPURegionEnable \ + ROM_MPURegionEnable +#else +#define MAP_MPURegionEnable \ + MPURegionEnable +#endif +#ifdef ROM_MPURegionDisable +#define MAP_MPURegionDisable \ + ROM_MPURegionDisable +#else +#define MAP_MPURegionDisable \ + MPURegionDisable +#endif +#ifdef ROM_MPURegionSet +#define MAP_MPURegionSet \ + ROM_MPURegionSet +#else +#define MAP_MPURegionSet \ + MPURegionSet +#endif +#ifdef ROM_MPURegionGet +#define MAP_MPURegionGet \ + ROM_MPURegionGet +#else +#define MAP_MPURegionGet \ + MPURegionGet +#endif + +//***************************************************************************** +// +// Macros for the PWM API. +// +//***************************************************************************** +#ifdef ROM_PWMPulseWidthSet +#define MAP_PWMPulseWidthSet \ + ROM_PWMPulseWidthSet +#else +#define MAP_PWMPulseWidthSet \ + PWMPulseWidthSet +#endif +#ifdef ROM_PWMGenConfigure +#define MAP_PWMGenConfigure \ + ROM_PWMGenConfigure +#else +#define MAP_PWMGenConfigure \ + PWMGenConfigure +#endif +#ifdef ROM_PWMGenPeriodSet +#define MAP_PWMGenPeriodSet \ + ROM_PWMGenPeriodSet +#else +#define MAP_PWMGenPeriodSet \ + PWMGenPeriodSet +#endif +#ifdef ROM_PWMGenPeriodGet +#define MAP_PWMGenPeriodGet \ + ROM_PWMGenPeriodGet +#else +#define MAP_PWMGenPeriodGet \ + PWMGenPeriodGet +#endif +#ifdef ROM_PWMGenEnable +#define MAP_PWMGenEnable \ + ROM_PWMGenEnable +#else +#define MAP_PWMGenEnable \ + PWMGenEnable +#endif +#ifdef ROM_PWMGenDisable +#define MAP_PWMGenDisable \ + ROM_PWMGenDisable +#else +#define MAP_PWMGenDisable \ + PWMGenDisable +#endif +#ifdef ROM_PWMPulseWidthGet +#define MAP_PWMPulseWidthGet \ + ROM_PWMPulseWidthGet +#else +#define MAP_PWMPulseWidthGet \ + PWMPulseWidthGet +#endif +#ifdef ROM_PWMDeadBandEnable +#define MAP_PWMDeadBandEnable \ + ROM_PWMDeadBandEnable +#else +#define MAP_PWMDeadBandEnable \ + PWMDeadBandEnable +#endif +#ifdef ROM_PWMDeadBandDisable +#define MAP_PWMDeadBandDisable \ + ROM_PWMDeadBandDisable +#else +#define MAP_PWMDeadBandDisable \ + PWMDeadBandDisable +#endif +#ifdef ROM_PWMSyncUpdate +#define MAP_PWMSyncUpdate \ + ROM_PWMSyncUpdate +#else +#define MAP_PWMSyncUpdate \ + PWMSyncUpdate +#endif +#ifdef ROM_PWMSyncTimeBase +#define MAP_PWMSyncTimeBase \ + ROM_PWMSyncTimeBase +#else +#define MAP_PWMSyncTimeBase \ + PWMSyncTimeBase +#endif +#ifdef ROM_PWMOutputState +#define MAP_PWMOutputState \ + ROM_PWMOutputState +#else +#define MAP_PWMOutputState \ + PWMOutputState +#endif +#ifdef ROM_PWMOutputInvert +#define MAP_PWMOutputInvert \ + ROM_PWMOutputInvert +#else +#define MAP_PWMOutputInvert \ + PWMOutputInvert +#endif +#ifdef ROM_PWMOutputFault +#define MAP_PWMOutputFault \ + ROM_PWMOutputFault +#else +#define MAP_PWMOutputFault \ + PWMOutputFault +#endif +#ifdef ROM_PWMGenIntTrigEnable +#define MAP_PWMGenIntTrigEnable \ + ROM_PWMGenIntTrigEnable +#else +#define MAP_PWMGenIntTrigEnable \ + PWMGenIntTrigEnable +#endif +#ifdef ROM_PWMGenIntTrigDisable +#define MAP_PWMGenIntTrigDisable \ + ROM_PWMGenIntTrigDisable +#else +#define MAP_PWMGenIntTrigDisable \ + PWMGenIntTrigDisable +#endif +#ifdef ROM_PWMGenIntStatus +#define MAP_PWMGenIntStatus \ + ROM_PWMGenIntStatus +#else +#define MAP_PWMGenIntStatus \ + PWMGenIntStatus +#endif +#ifdef ROM_PWMGenIntClear +#define MAP_PWMGenIntClear \ + ROM_PWMGenIntClear +#else +#define MAP_PWMGenIntClear \ + PWMGenIntClear +#endif +#ifdef ROM_PWMIntEnable +#define MAP_PWMIntEnable \ + ROM_PWMIntEnable +#else +#define MAP_PWMIntEnable \ + PWMIntEnable +#endif +#ifdef ROM_PWMIntDisable +#define MAP_PWMIntDisable \ + ROM_PWMIntDisable +#else +#define MAP_PWMIntDisable \ + PWMIntDisable +#endif +#ifdef ROM_PWMFaultIntClear +#define MAP_PWMFaultIntClear \ + ROM_PWMFaultIntClear +#else +#define MAP_PWMFaultIntClear \ + PWMFaultIntClear +#endif +#ifdef ROM_PWMIntStatus +#define MAP_PWMIntStatus \ + ROM_PWMIntStatus +#else +#define MAP_PWMIntStatus \ + PWMIntStatus +#endif +#ifdef ROM_PWMOutputFaultLevel +#define MAP_PWMOutputFaultLevel \ + ROM_PWMOutputFaultLevel +#else +#define MAP_PWMOutputFaultLevel \ + PWMOutputFaultLevel +#endif +#ifdef ROM_PWMFaultIntClearExt +#define MAP_PWMFaultIntClearExt \ + ROM_PWMFaultIntClearExt +#else +#define MAP_PWMFaultIntClearExt \ + PWMFaultIntClearExt +#endif +#ifdef ROM_PWMGenFaultConfigure +#define MAP_PWMGenFaultConfigure \ + ROM_PWMGenFaultConfigure +#else +#define MAP_PWMGenFaultConfigure \ + PWMGenFaultConfigure +#endif +#ifdef ROM_PWMGenFaultTriggerSet +#define MAP_PWMGenFaultTriggerSet \ + ROM_PWMGenFaultTriggerSet +#else +#define MAP_PWMGenFaultTriggerSet \ + PWMGenFaultTriggerSet +#endif +#ifdef ROM_PWMGenFaultTriggerGet +#define MAP_PWMGenFaultTriggerGet \ + ROM_PWMGenFaultTriggerGet +#else +#define MAP_PWMGenFaultTriggerGet \ + PWMGenFaultTriggerGet +#endif +#ifdef ROM_PWMGenFaultStatus +#define MAP_PWMGenFaultStatus \ + ROM_PWMGenFaultStatus +#else +#define MAP_PWMGenFaultStatus \ + PWMGenFaultStatus +#endif +#ifdef ROM_PWMGenFaultClear +#define MAP_PWMGenFaultClear \ + ROM_PWMGenFaultClear +#else +#define MAP_PWMGenFaultClear \ + PWMGenFaultClear +#endif + +//***************************************************************************** +// +// Macros for the QEI API. +// +//***************************************************************************** +#ifdef ROM_QEIPositionGet +#define MAP_QEIPositionGet \ + ROM_QEIPositionGet +#else +#define MAP_QEIPositionGet \ + QEIPositionGet +#endif +#ifdef ROM_QEIEnable +#define MAP_QEIEnable \ + ROM_QEIEnable +#else +#define MAP_QEIEnable \ + QEIEnable +#endif +#ifdef ROM_QEIDisable +#define MAP_QEIDisable \ + ROM_QEIDisable +#else +#define MAP_QEIDisable \ + QEIDisable +#endif +#ifdef ROM_QEIConfigure +#define MAP_QEIConfigure \ + ROM_QEIConfigure +#else +#define MAP_QEIConfigure \ + QEIConfigure +#endif +#ifdef ROM_QEIPositionSet +#define MAP_QEIPositionSet \ + ROM_QEIPositionSet +#else +#define MAP_QEIPositionSet \ + QEIPositionSet +#endif +#ifdef ROM_QEIDirectionGet +#define MAP_QEIDirectionGet \ + ROM_QEIDirectionGet +#else +#define MAP_QEIDirectionGet \ + QEIDirectionGet +#endif +#ifdef ROM_QEIErrorGet +#define MAP_QEIErrorGet \ + ROM_QEIErrorGet +#else +#define MAP_QEIErrorGet \ + QEIErrorGet +#endif +#ifdef ROM_QEIVelocityEnable +#define MAP_QEIVelocityEnable \ + ROM_QEIVelocityEnable +#else +#define MAP_QEIVelocityEnable \ + QEIVelocityEnable +#endif +#ifdef ROM_QEIVelocityDisable +#define MAP_QEIVelocityDisable \ + ROM_QEIVelocityDisable +#else +#define MAP_QEIVelocityDisable \ + QEIVelocityDisable +#endif +#ifdef ROM_QEIVelocityConfigure +#define MAP_QEIVelocityConfigure \ + ROM_QEIVelocityConfigure +#else +#define MAP_QEIVelocityConfigure \ + QEIVelocityConfigure +#endif +#ifdef ROM_QEIVelocityGet +#define MAP_QEIVelocityGet \ + ROM_QEIVelocityGet +#else +#define MAP_QEIVelocityGet \ + QEIVelocityGet +#endif +#ifdef ROM_QEIIntEnable +#define MAP_QEIIntEnable \ + ROM_QEIIntEnable +#else +#define MAP_QEIIntEnable \ + QEIIntEnable +#endif +#ifdef ROM_QEIIntDisable +#define MAP_QEIIntDisable \ + ROM_QEIIntDisable +#else +#define MAP_QEIIntDisable \ + QEIIntDisable +#endif +#ifdef ROM_QEIIntStatus +#define MAP_QEIIntStatus \ + ROM_QEIIntStatus +#else +#define MAP_QEIIntStatus \ + QEIIntStatus +#endif +#ifdef ROM_QEIIntClear +#define MAP_QEIIntClear \ + ROM_QEIIntClear +#else +#define MAP_QEIIntClear \ + QEIIntClear +#endif + +//***************************************************************************** +// +// Macros for the SSI API. +// +//***************************************************************************** +#ifdef ROM_SSIDataPut +#define MAP_SSIDataPut \ + ROM_SSIDataPut +#else +#define MAP_SSIDataPut \ + SSIDataPut +#endif +#ifdef ROM_SSIConfigSetExpClk +#define MAP_SSIConfigSetExpClk \ + ROM_SSIConfigSetExpClk +#else +#define MAP_SSIConfigSetExpClk \ + SSIConfigSetExpClk +#endif +#ifdef ROM_SSIEnable +#define MAP_SSIEnable \ + ROM_SSIEnable +#else +#define MAP_SSIEnable \ + SSIEnable +#endif +#ifdef ROM_SSIDisable +#define MAP_SSIDisable \ + ROM_SSIDisable +#else +#define MAP_SSIDisable \ + SSIDisable +#endif +#ifdef ROM_SSIIntEnable +#define MAP_SSIIntEnable \ + ROM_SSIIntEnable +#else +#define MAP_SSIIntEnable \ + SSIIntEnable +#endif +#ifdef ROM_SSIIntDisable +#define MAP_SSIIntDisable \ + ROM_SSIIntDisable +#else +#define MAP_SSIIntDisable \ + SSIIntDisable +#endif +#ifdef ROM_SSIIntStatus +#define MAP_SSIIntStatus \ + ROM_SSIIntStatus +#else +#define MAP_SSIIntStatus \ + SSIIntStatus +#endif +#ifdef ROM_SSIIntClear +#define MAP_SSIIntClear \ + ROM_SSIIntClear +#else +#define MAP_SSIIntClear \ + SSIIntClear +#endif +#ifdef ROM_SSIDataPutNonBlocking +#define MAP_SSIDataPutNonBlocking \ + ROM_SSIDataPutNonBlocking +#else +#define MAP_SSIDataPutNonBlocking \ + SSIDataPutNonBlocking +#endif +#ifdef ROM_SSIDataGet +#define MAP_SSIDataGet \ + ROM_SSIDataGet +#else +#define MAP_SSIDataGet \ + SSIDataGet +#endif +#ifdef ROM_SSIDataGetNonBlocking +#define MAP_SSIDataGetNonBlocking \ + ROM_SSIDataGetNonBlocking +#else +#define MAP_SSIDataGetNonBlocking \ + SSIDataGetNonBlocking +#endif +#ifdef ROM_SSIDMAEnable +#define MAP_SSIDMAEnable \ + ROM_SSIDMAEnable +#else +#define MAP_SSIDMAEnable \ + SSIDMAEnable +#endif +#ifdef ROM_SSIDMADisable +#define MAP_SSIDMADisable \ + ROM_SSIDMADisable +#else +#define MAP_SSIDMADisable \ + SSIDMADisable +#endif + +//***************************************************************************** +// +// Macros for the SysCtl API. +// +//***************************************************************************** +#ifdef ROM_SysCtlSleep +#define MAP_SysCtlSleep \ + ROM_SysCtlSleep +#else +#define MAP_SysCtlSleep \ + SysCtlSleep +#endif +#ifdef ROM_SysCtlSRAMSizeGet +#define MAP_SysCtlSRAMSizeGet \ + ROM_SysCtlSRAMSizeGet +#else +#define MAP_SysCtlSRAMSizeGet \ + SysCtlSRAMSizeGet +#endif +#ifdef ROM_SysCtlFlashSizeGet +#define MAP_SysCtlFlashSizeGet \ + ROM_SysCtlFlashSizeGet +#else +#define MAP_SysCtlFlashSizeGet \ + SysCtlFlashSizeGet +#endif +#ifdef ROM_SysCtlPinPresent +#define MAP_SysCtlPinPresent \ + ROM_SysCtlPinPresent +#else +#define MAP_SysCtlPinPresent \ + SysCtlPinPresent +#endif +#ifdef ROM_SysCtlPeripheralPresent +#define MAP_SysCtlPeripheralPresent \ + ROM_SysCtlPeripheralPresent +#else +#define MAP_SysCtlPeripheralPresent \ + SysCtlPeripheralPresent +#endif +#ifdef ROM_SysCtlPeripheralReset +#define MAP_SysCtlPeripheralReset \ + ROM_SysCtlPeripheralReset +#else +#define MAP_SysCtlPeripheralReset \ + SysCtlPeripheralReset +#endif +#ifdef ROM_SysCtlPeripheralEnable +#define MAP_SysCtlPeripheralEnable \ + ROM_SysCtlPeripheralEnable +#else +#define MAP_SysCtlPeripheralEnable \ + SysCtlPeripheralEnable +#endif +#ifdef ROM_SysCtlPeripheralDisable +#define MAP_SysCtlPeripheralDisable \ + ROM_SysCtlPeripheralDisable +#else +#define MAP_SysCtlPeripheralDisable \ + SysCtlPeripheralDisable +#endif +#ifdef ROM_SysCtlPeripheralSleepEnable +#define MAP_SysCtlPeripheralSleepEnable \ + ROM_SysCtlPeripheralSleepEnable +#else +#define MAP_SysCtlPeripheralSleepEnable \ + SysCtlPeripheralSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralSleepDisable +#define MAP_SysCtlPeripheralSleepDisable \ + ROM_SysCtlPeripheralSleepDisable +#else +#define MAP_SysCtlPeripheralSleepDisable \ + SysCtlPeripheralSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepEnable +#define MAP_SysCtlPeripheralDeepSleepEnable \ + ROM_SysCtlPeripheralDeepSleepEnable +#else +#define MAP_SysCtlPeripheralDeepSleepEnable \ + SysCtlPeripheralDeepSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepDisable +#define MAP_SysCtlPeripheralDeepSleepDisable \ + ROM_SysCtlPeripheralDeepSleepDisable +#else +#define MAP_SysCtlPeripheralDeepSleepDisable \ + SysCtlPeripheralDeepSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralClockGating +#define MAP_SysCtlPeripheralClockGating \ + ROM_SysCtlPeripheralClockGating +#else +#define MAP_SysCtlPeripheralClockGating \ + SysCtlPeripheralClockGating +#endif +#ifdef ROM_SysCtlIntEnable +#define MAP_SysCtlIntEnable \ + ROM_SysCtlIntEnable +#else +#define MAP_SysCtlIntEnable \ + SysCtlIntEnable +#endif +#ifdef ROM_SysCtlIntDisable +#define MAP_SysCtlIntDisable \ + ROM_SysCtlIntDisable +#else +#define MAP_SysCtlIntDisable \ + SysCtlIntDisable +#endif +#ifdef ROM_SysCtlIntClear +#define MAP_SysCtlIntClear \ + ROM_SysCtlIntClear +#else +#define MAP_SysCtlIntClear \ + SysCtlIntClear +#endif +#ifdef ROM_SysCtlIntStatus +#define MAP_SysCtlIntStatus \ + ROM_SysCtlIntStatus +#else +#define MAP_SysCtlIntStatus \ + SysCtlIntStatus +#endif +#ifdef ROM_SysCtlLDOSet +#define MAP_SysCtlLDOSet \ + ROM_SysCtlLDOSet +#else +#define MAP_SysCtlLDOSet \ + SysCtlLDOSet +#endif +#ifdef ROM_SysCtlLDOGet +#define MAP_SysCtlLDOGet \ + ROM_SysCtlLDOGet +#else +#define MAP_SysCtlLDOGet \ + SysCtlLDOGet +#endif +#ifdef ROM_SysCtlReset +#define MAP_SysCtlReset \ + ROM_SysCtlReset +#else +#define MAP_SysCtlReset \ + SysCtlReset +#endif +#ifdef ROM_SysCtlDeepSleep +#define MAP_SysCtlDeepSleep \ + ROM_SysCtlDeepSleep +#else +#define MAP_SysCtlDeepSleep \ + SysCtlDeepSleep +#endif +#ifdef ROM_SysCtlResetCauseGet +#define MAP_SysCtlResetCauseGet \ + ROM_SysCtlResetCauseGet +#else +#define MAP_SysCtlResetCauseGet \ + SysCtlResetCauseGet +#endif +#ifdef ROM_SysCtlResetCauseClear +#define MAP_SysCtlResetCauseClear \ + ROM_SysCtlResetCauseClear +#else +#define MAP_SysCtlResetCauseClear \ + SysCtlResetCauseClear +#endif +#ifdef ROM_SysCtlClockSet +#define MAP_SysCtlClockSet \ + ROM_SysCtlClockSet +#else +#define MAP_SysCtlClockSet \ + SysCtlClockSet +#endif +#ifdef ROM_SysCtlClockGet +#define MAP_SysCtlClockGet \ + ROM_SysCtlClockGet +#else +#define MAP_SysCtlClockGet \ + SysCtlClockGet +#endif +#ifdef ROM_SysCtlPWMClockSet +#define MAP_SysCtlPWMClockSet \ + ROM_SysCtlPWMClockSet +#else +#define MAP_SysCtlPWMClockSet \ + SysCtlPWMClockSet +#endif +#ifdef ROM_SysCtlPWMClockGet +#define MAP_SysCtlPWMClockGet \ + ROM_SysCtlPWMClockGet +#else +#define MAP_SysCtlPWMClockGet \ + SysCtlPWMClockGet +#endif +#ifdef ROM_SysCtlADCSpeedSet +#define MAP_SysCtlADCSpeedSet \ + ROM_SysCtlADCSpeedSet +#else +#define MAP_SysCtlADCSpeedSet \ + SysCtlADCSpeedSet +#endif +#ifdef ROM_SysCtlADCSpeedGet +#define MAP_SysCtlADCSpeedGet \ + ROM_SysCtlADCSpeedGet +#else +#define MAP_SysCtlADCSpeedGet \ + SysCtlADCSpeedGet +#endif +#ifdef ROM_SysCtlGPIOAHBEnable +#define MAP_SysCtlGPIOAHBEnable \ + ROM_SysCtlGPIOAHBEnable +#else +#define MAP_SysCtlGPIOAHBEnable \ + SysCtlGPIOAHBEnable +#endif +#ifdef ROM_SysCtlGPIOAHBDisable +#define MAP_SysCtlGPIOAHBDisable \ + ROM_SysCtlGPIOAHBDisable +#else +#define MAP_SysCtlGPIOAHBDisable \ + SysCtlGPIOAHBDisable +#endif +#ifdef ROM_SysCtlUSBPLLEnable +#define MAP_SysCtlUSBPLLEnable \ + ROM_SysCtlUSBPLLEnable +#else +#define MAP_SysCtlUSBPLLEnable \ + SysCtlUSBPLLEnable +#endif +#ifdef ROM_SysCtlUSBPLLDisable +#define MAP_SysCtlUSBPLLDisable \ + ROM_SysCtlUSBPLLDisable +#else +#define MAP_SysCtlUSBPLLDisable \ + SysCtlUSBPLLDisable +#endif + +//***************************************************************************** +// +// Macros for the SysTick API. +// +//***************************************************************************** +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlTrigger +#define MAP_TimerControlTrigger \ + ROM_TimerControlTrigger +#else +#define MAP_TimerControlTrigger \ + TimerControlTrigger +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerRTCEnable +#define MAP_TimerRTCEnable \ + ROM_TimerRTCEnable +#else +#define MAP_TimerRTCEnable \ + TimerRTCEnable +#endif +#ifdef ROM_TimerRTCDisable +#define MAP_TimerRTCDisable \ + ROM_TimerRTCDisable +#else +#define MAP_TimerRTCDisable \ + TimerRTCDisable +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTEnableSIR +#define MAP_UARTEnableSIR \ + ROM_UARTEnableSIR +#else +#define MAP_UARTEnableSIR \ + UARTEnableSIR +#endif +#ifdef ROM_UARTDisableSIR +#define MAP_UARTDisableSIR \ + ROM_UARTDisableSIR +#else +#define MAP_UARTDisableSIR \ + UARTDisableSIR +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif + +//***************************************************************************** +// +// Macros for the USB API. +// +//***************************************************************************** +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBDevAddrGet +#define MAP_USBDevAddrGet \ + ROM_USBDevAddrGet +#else +#define MAP_USBDevAddrGet \ + USBDevAddrGet +#endif +#ifdef ROM_USBDevAddrSet +#define MAP_USBDevAddrSet \ + ROM_USBDevAddrSet +#else +#define MAP_USBDevAddrSet \ + USBDevAddrSet +#endif +#ifdef ROM_USBDevConnect +#define MAP_USBDevConnect \ + ROM_USBDevConnect +#else +#define MAP_USBDevConnect \ + USBDevConnect +#endif +#ifdef ROM_USBDevDisconnect +#define MAP_USBDevDisconnect \ + ROM_USBDevDisconnect +#else +#define MAP_USBDevDisconnect \ + USBDevDisconnect +#endif +#ifdef ROM_USBDevEndpointConfig +#define MAP_USBDevEndpointConfig \ + ROM_USBDevEndpointConfig +#else +#define MAP_USBDevEndpointConfig \ + USBDevEndpointConfig +#endif +#ifdef ROM_USBDevEndpointDataAck +#define MAP_USBDevEndpointDataAck \ + ROM_USBDevEndpointDataAck +#else +#define MAP_USBDevEndpointDataAck \ + USBDevEndpointDataAck +#endif +#ifdef ROM_USBDevEndpointStall +#define MAP_USBDevEndpointStall \ + ROM_USBDevEndpointStall +#else +#define MAP_USBDevEndpointStall \ + USBDevEndpointStall +#endif +#ifdef ROM_USBDevEndpointStallClear +#define MAP_USBDevEndpointStallClear \ + ROM_USBDevEndpointStallClear +#else +#define MAP_USBDevEndpointStallClear \ + USBDevEndpointStallClear +#endif +#ifdef ROM_USBDevEndpointStatusClear +#define MAP_USBDevEndpointStatusClear \ + ROM_USBDevEndpointStatusClear +#else +#define MAP_USBDevEndpointStatusClear \ + USBDevEndpointStatusClear +#endif +#ifdef ROM_USBEndpointDataGet +#define MAP_USBEndpointDataGet \ + ROM_USBEndpointDataGet +#else +#define MAP_USBEndpointDataGet \ + USBEndpointDataGet +#endif +#ifdef ROM_USBEndpointDataPut +#define MAP_USBEndpointDataPut \ + ROM_USBEndpointDataPut +#else +#define MAP_USBEndpointDataPut \ + USBEndpointDataPut +#endif +#ifdef ROM_USBEndpointDataSend +#define MAP_USBEndpointDataSend \ + ROM_USBEndpointDataSend +#else +#define MAP_USBEndpointDataSend \ + USBEndpointDataSend +#endif +#ifdef ROM_USBEndpointDataToggleClear +#define MAP_USBEndpointDataToggleClear \ + ROM_USBEndpointDataToggleClear +#else +#define MAP_USBEndpointDataToggleClear \ + USBEndpointDataToggleClear +#endif +#ifdef ROM_USBEndpointStatus +#define MAP_USBEndpointStatus \ + ROM_USBEndpointStatus +#else +#define MAP_USBEndpointStatus \ + USBEndpointStatus +#endif +#ifdef ROM_USBFIFOAddrGet +#define MAP_USBFIFOAddrGet \ + ROM_USBFIFOAddrGet +#else +#define MAP_USBFIFOAddrGet \ + USBFIFOAddrGet +#endif +#ifdef ROM_USBFIFOConfigGet +#define MAP_USBFIFOConfigGet \ + ROM_USBFIFOConfigGet +#else +#define MAP_USBFIFOConfigGet \ + USBFIFOConfigGet +#endif +#ifdef ROM_USBFIFOConfigSet +#define MAP_USBFIFOConfigSet \ + ROM_USBFIFOConfigSet +#else +#define MAP_USBFIFOConfigSet \ + USBFIFOConfigSet +#endif +#ifdef ROM_USBFIFOFlush +#define MAP_USBFIFOFlush \ + ROM_USBFIFOFlush +#else +#define MAP_USBFIFOFlush \ + USBFIFOFlush +#endif +#ifdef ROM_USBFrameNumberGet +#define MAP_USBFrameNumberGet \ + ROM_USBFrameNumberGet +#else +#define MAP_USBFrameNumberGet \ + USBFrameNumberGet +#endif +#ifdef ROM_USBHostAddrGet +#define MAP_USBHostAddrGet \ + ROM_USBHostAddrGet +#else +#define MAP_USBHostAddrGet \ + USBHostAddrGet +#endif +#ifdef ROM_USBHostAddrSet +#define MAP_USBHostAddrSet \ + ROM_USBHostAddrSet +#else +#define MAP_USBHostAddrSet \ + USBHostAddrSet +#endif +#ifdef ROM_USBHostEndpointConfig +#define MAP_USBHostEndpointConfig \ + ROM_USBHostEndpointConfig +#else +#define MAP_USBHostEndpointConfig \ + USBHostEndpointConfig +#endif +#ifdef ROM_USBHostEndpointDataAck +#define MAP_USBHostEndpointDataAck \ + ROM_USBHostEndpointDataAck +#else +#define MAP_USBHostEndpointDataAck \ + USBHostEndpointDataAck +#endif +#ifdef ROM_USBHostEndpointDataToggle +#define MAP_USBHostEndpointDataToggle \ + ROM_USBHostEndpointDataToggle +#else +#define MAP_USBHostEndpointDataToggle \ + USBHostEndpointDataToggle +#endif +#ifdef ROM_USBHostEndpointStatusClear +#define MAP_USBHostEndpointStatusClear \ + ROM_USBHostEndpointStatusClear +#else +#define MAP_USBHostEndpointStatusClear \ + USBHostEndpointStatusClear +#endif +#ifdef ROM_USBHostHubAddrGet +#define MAP_USBHostHubAddrGet \ + ROM_USBHostHubAddrGet +#else +#define MAP_USBHostHubAddrGet \ + USBHostHubAddrGet +#endif +#ifdef ROM_USBHostHubAddrSet +#define MAP_USBHostHubAddrSet \ + ROM_USBHostHubAddrSet +#else +#define MAP_USBHostHubAddrSet \ + USBHostHubAddrSet +#endif +#ifdef ROM_USBHostPwrDisable +#define MAP_USBHostPwrDisable \ + ROM_USBHostPwrDisable +#else +#define MAP_USBHostPwrDisable \ + USBHostPwrDisable +#endif +#ifdef ROM_USBHostPwrEnable +#define MAP_USBHostPwrEnable \ + ROM_USBHostPwrEnable +#else +#define MAP_USBHostPwrEnable \ + USBHostPwrEnable +#endif +#ifdef ROM_USBHostPwrFaultConfig +#define MAP_USBHostPwrFaultConfig \ + ROM_USBHostPwrFaultConfig +#else +#define MAP_USBHostPwrFaultConfig \ + USBHostPwrFaultConfig +#endif +#ifdef ROM_USBHostPwrFaultDisable +#define MAP_USBHostPwrFaultDisable \ + ROM_USBHostPwrFaultDisable +#else +#define MAP_USBHostPwrFaultDisable \ + USBHostPwrFaultDisable +#endif +#ifdef ROM_USBHostPwrFaultEnable +#define MAP_USBHostPwrFaultEnable \ + ROM_USBHostPwrFaultEnable +#else +#define MAP_USBHostPwrFaultEnable \ + USBHostPwrFaultEnable +#endif +#ifdef ROM_USBHostRequestIN +#define MAP_USBHostRequestIN \ + ROM_USBHostRequestIN +#else +#define MAP_USBHostRequestIN \ + USBHostRequestIN +#endif +#ifdef ROM_USBHostRequestStatus +#define MAP_USBHostRequestStatus \ + ROM_USBHostRequestStatus +#else +#define MAP_USBHostRequestStatus \ + USBHostRequestStatus +#endif +#ifdef ROM_USBHostReset +#define MAP_USBHostReset \ + ROM_USBHostReset +#else +#define MAP_USBHostReset \ + USBHostReset +#endif +#ifdef ROM_USBHostResume +#define MAP_USBHostResume \ + ROM_USBHostResume +#else +#define MAP_USBHostResume \ + USBHostResume +#endif +#ifdef ROM_USBHostSpeedGet +#define MAP_USBHostSpeedGet \ + ROM_USBHostSpeedGet +#else +#define MAP_USBHostSpeedGet \ + USBHostSpeedGet +#endif +#ifdef ROM_USBHostSuspend +#define MAP_USBHostSuspend \ + ROM_USBHostSuspend +#else +#define MAP_USBHostSuspend \ + USBHostSuspend +#endif +#ifdef ROM_USBIntDisable +#define MAP_USBIntDisable \ + ROM_USBIntDisable +#else +#define MAP_USBIntDisable \ + USBIntDisable +#endif +#ifdef ROM_USBIntEnable +#define MAP_USBIntEnable \ + ROM_USBIntEnable +#else +#define MAP_USBIntEnable \ + USBIntEnable +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogResetEnable +#define MAP_WatchdogResetEnable \ + ROM_WatchdogResetEnable +#else +#define MAP_WatchdogResetEnable \ + WatchdogResetEnable +#endif +#ifdef ROM_WatchdogResetDisable +#define MAP_WatchdogResetDisable \ + ROM_WatchdogResetDisable +#else +#define MAP_WatchdogResetDisable \ + WatchdogResetDisable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntEnable +#define MAP_WatchdogIntEnable \ + ROM_WatchdogIntEnable +#else +#define MAP_WatchdogIntEnable \ + WatchdogIntEnable +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif + +#endif // __ROM_MAP_H__ diff --git a/bsp/lm3s/driverlib/ssi.c b/bsp/lm3s/driverlib/ssi.c new file mode 100644 index 0000000000..f9e84ad50c --- /dev/null +++ b/bsp/lm3s/driverlib/ssi.c @@ -0,0 +1,680 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ssi.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/ssi.h" + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulSSIClk is the rate of the clock supplied to the SSI module. +//! \param ulProtocol specifies the data transfer protocol. +//! \param ulMode specifies the mode of operation. +//! \param ulBitRate specifies the clock rate. +//! \param ulDataWidth specifies number of bits transferred per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \e ulProtocol parameter defines the data frame format. The +//! \e ulProtocol parameter can be one of the following values: +//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, +//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola +//! frame formats imply the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \e ulMode parameter defines the operating mode of the SSI module. The +//! SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. The \e ulMode +//! parameter can be one of the following values: \b SSI_MODE_MASTER, +//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. +//! +//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate +//! must satisfy the following clock ratio criteria: +//! +//! - FSSI >= 2 * bit rate (master mode) +//! - FSSI >= 12 * bit rate (slave modes) +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The \e ulDataWidth parameter defines the width of the data transfers, and +//! can be a value between 4 and 16, inclusive. +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original SSIConfig() API and performs the same +//! actions. A macro is provided in ssi.h to map the original API to +//! this API. +//! +//! \return None. +// +//***************************************************************************** +void +SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, unsigned long ulDataWidth) +{ + unsigned long ulMaxBitRate; + unsigned long ulRegVal; + unsigned long ulPreDiv; + unsigned long ulSCR; + unsigned long ulSPH_SPO; + + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || + (ulProtocol == SSI_FRF_MOTO_MODE_1) || + (ulProtocol == SSI_FRF_MOTO_MODE_2) || + (ulProtocol == SSI_FRF_MOTO_MODE_3) || + (ulProtocol == SSI_FRF_TI) || + (ulProtocol == SSI_FRF_NMW)); + ASSERT((ulMode == SSI_MODE_MASTER) || + (ulMode == SSI_MODE_SLAVE) || + (ulMode == SSI_MODE_SLAVE_OD)); + ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) || + ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12)))); + ASSERT((ulSSIClk / ulBitRate) <= (254 * 256)); + ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); + + // + // Set the mode. + // + ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ulBase + SSI_O_CR1) = ulRegVal; + + // + // Set the clock predivider. + // + ulMaxBitRate = ulSSIClk / ulBitRate; + ulPreDiv = 0; + do + { + ulPreDiv += 2; + ulSCR = (ulMaxBitRate / ulPreDiv) - 1; + } + while(ulSCR > 255); + HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; + + // + // Set protocol and clock rate. + // + ulSPH_SPO = ulProtocol << 6; + ulProtocol &= SSI_CR0_FRF_M; + ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); + HWREG(ulBase + SSI_O_CR0) = ulRegVal; +} + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will enable operation of the synchronous serial interface. It must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SSIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will disable operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an SSI interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Determine the interrupt number based on the SSI port. + // + ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1; + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Determine the interrupt number based on the SSI port. + // + ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. The \e ulIntFlags parameter can be any of the +//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter +//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR +//! values. +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the SSI module base address. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the SSI module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR. +// +//***************************************************************************** +unsigned long +SSIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + SSI_O_MIS)); + } + else + { + return(HWREG(ulBase + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SSI interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to +//! keep it from being called again immediately upon exit. +//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO +//! and \b SSI_RXOR values. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + SSI_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \e ulData will be discarded. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ulBase + SSI_O_DR) = ulData; +} + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. If there is no space in the FIFO, then this +//! function will return a zero. +//! +//! This function replaces the original SSIDataNonBlockingPut() API and +//! performs the same actions. A macro is provided in ssi.h to map +//! the original API to this API. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \e ulData will be discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +long +SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Check for space to write. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ulBase + SSI_O_DR) = ulData; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of the specified +//! SSI module, and place that data into the location specified by the +//! \e pulData parameter. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \e pulData +//! will contain valid data. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pulData = HWREG(ulBase + SSI_O_DR); +} + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of +//! the specified SSI module, and place that data into the location specified +//! by the \e ulData parameter. If there is no data in the FIFO, then this +//! function will return a zero. +//! +//! This function replaces the original SSIDataNonBlockingGet() API and +//! performs the same actions. A macro is provided in ssi.h to map +//! the original API to this API. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \e pulData +//! will contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +long +SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Check for data to read. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) + { + *pulData = HWREG(ulBase + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Enable SSI DMA operation. +//! +//! \param ulBase is the base address of the SSI port. +//! \param ulDMAFlags is a bit mask of the DMA features to enable. +//! +//! The specified SSI DMA features are enabled. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! The \e ulDMAFlags parameter is the logical OR of any of the following +//! values: +//! +//! - SSI_DMA_RX - enable DMA for receive +//! - SSI_DMA_TX - enable DMA for transmit +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \return None. +// +//***************************************************************************** +void +SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Set the requested bits in the UART DMA control register. + // + HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags; +} + +//***************************************************************************** +// +//! Disable SSI DMA operation. +//! +//! \param ulBase is the base address of the SSI port. +//! \param ulDMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The +//! \e ulDMAFlags parameter is the logical OR of any of the following values: +//! +//! - SSI_DMA_RX - disable DMA for receive +//! - SSI_DMA_TX - disable DMA for transmit +//! +//! \return None. +// +//***************************************************************************** +void +SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE)); + + // + // Clear the requested bits in the UART DMA control register. + // + HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/ssi.h b/bsp/lm3s/driverlib/ssi.h new file mode 100644 index 0000000000..4f7101b598 --- /dev/null +++ b/bsp/lm3s/driverlib/ssi.h @@ -0,0 +1,127 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); + +//***************************************************************************** +// +// Several SSI APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define SSIConfig(a, b, c, d, e) \ + SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e) +#define SSIDataNonBlockingGet(a, b) \ + SSIDataGetNonBlocking(a, b) +#define SSIDataNonBlockingPut(a, b) \ + SSIDataPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/bsp/lm3s/driverlib/sysctl.c b/bsp/lm3s/driverlib/sysctl.c new file mode 100644 index 0000000000..0bc6ae7d51 --- /dev/null +++ b/bsp/lm3s/driverlib/sysctl.c @@ -0,0 +1,2319 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "driverlib/cpu.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number. +// +//***************************************************************************** +#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf) + +//***************************************************************************** +// +// This macro constructs the peripheral bit mask from the peripheral number. +// +//***************************************************************************** +#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16)) + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that +// contains the peripheral present bit for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulDCRegs[] = +{ + SYSCTL_DC1, + SYSCTL_DC2, + SYSCTL_DC4, + SYSCTL_DC1 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that +// controls the software reset for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulSRCRRegs[] = +{ + SYSCTL_SRCR0, + SYSCTL_SRCR1, + SYSCTL_SRCR2 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that +// controls the run-mode enable for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulRCGCRegs[] = +{ + SYSCTL_RCGC0, + SYSCTL_RCGC1, + SYSCTL_RCGC2 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that +// controls the sleep-mode enable for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulSCGCRegs[] = +{ + SYSCTL_SCGC0, + SYSCTL_SCGC1, + SYSCTL_SCGC2 +}; + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that +// controls the deep-sleep-mode enable for that peripheral. +// +//***************************************************************************** +static const unsigned long g_pulDCGCRegs[] = +{ + SYSCTL_DCGC0, + SYSCTL_DCGC1, + SYSCTL_DCGC2 +}; + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +static const unsigned long g_pulXtals[] = +{ + 1000000, + 1843200, + 2000000, + 2457600, + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000, + 10000000, + 12000000, + 12288000, + 13560000, + 14318180, + 16000000, + 16384000 +}; + +//***************************************************************************** +// +//! \internal +//! Checks a peripheral identifier. +//! +//! \param ulPeripheral is the peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \return Returns \b true if the peripheral identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +SysCtlPeripheralValid(unsigned long ulPeripheral) +{ + return((ulPeripheral == SYSCTL_PERIPH_ADC0) || + (ulPeripheral == SYSCTL_PERIPH_ADC1) || + (ulPeripheral == SYSCTL_PERIPH_CAN0) || + (ulPeripheral == SYSCTL_PERIPH_CAN1) || + (ulPeripheral == SYSCTL_PERIPH_CAN2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_EPI0) || + (ulPeripheral == SYSCTL_PERIPH_ETH) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulPeripheral == SYSCTL_PERIPH_GPIOF) || + (ulPeripheral == SYSCTL_PERIPH_GPIOG) || + (ulPeripheral == SYSCTL_PERIPH_GPIOH) || + (ulPeripheral == SYSCTL_PERIPH_GPIOJ) || + (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) || + (ulPeripheral == SYSCTL_PERIPH_I2C0) || + (ulPeripheral == SYSCTL_PERIPH_I2C1) || + (ulPeripheral == SYSCTL_PERIPH_I2S0) || + (ulPeripheral == SYSCTL_PERIPH_IEEE1588) || + (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_PLL) || + (ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_QEI0) || + (ulPeripheral == SYSCTL_PERIPH_QEI1) || + (ulPeripheral == SYSCTL_PERIPH_SSI0) || + (ulPeripheral == SYSCTL_PERIPH_SSI1) || + (ulPeripheral == SYSCTL_PERIPH_TEMP) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_TIMER3) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_UART2) || + (ulPeripheral == SYSCTL_PERIPH_UDMA) || + (ulPeripheral == SYSCTL_PERIPH_USB0) || + (ulPeripheral == SYSCTL_PERIPH_WDOG0) || + (ulPeripheral == SYSCTL_PERIPH_WDOG1)); +} +#endif + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Stellaris device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +unsigned long +SysCtlSRAMSizeGet(void) +{ + // + // Compute the size of the SRAM. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_M) >> 8) + 0x100); +} + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Stellaris device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +unsigned long +SysCtlFlashSizeGet(void) +{ + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800); +} + +//***************************************************************************** +// +//! Determines if a pin is present. +//! +//! \param ulPin is the pin in question. +//! +//! Determines if a particular pin is present in the device. The PWM, analog +//! comparators, ADC, and timers have a varying number of pins across members +//! of the Stellaris family; this will determine which are present on this +//! device. +//! +//! The \e ulPin argument must be only one of the following values: +//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, +//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, +//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, +//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, +//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, +//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, +//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, +//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, +//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, +//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, \b SYSCTL_PIN_CCP6, +//! \b SYSCTL_PIN_CCP7, \b SYSCTL_PIN_32KHZ, or \b SYSCTL_PIN_MC_FAULT0. +//! +//! \return Returns \b true if the specified pin is present and \b false if it +//! is not. +// +//***************************************************************************** +tBoolean +SysCtlPinPresent(unsigned long ulPin) +{ + // + // Check the arguments. + // + ASSERT((ulPin == SYSCTL_PIN_PWM0) || + (ulPin == SYSCTL_PIN_PWM1) || + (ulPin == SYSCTL_PIN_PWM2) || + (ulPin == SYSCTL_PIN_PWM3) || + (ulPin == SYSCTL_PIN_PWM4) || + (ulPin == SYSCTL_PIN_PWM5) || + (ulPin == SYSCTL_PIN_C0MINUS) || + (ulPin == SYSCTL_PIN_C0PLUS) || + (ulPin == SYSCTL_PIN_C0O) || + (ulPin == SYSCTL_PIN_C1MINUS) || + (ulPin == SYSCTL_PIN_C1PLUS) || + (ulPin == SYSCTL_PIN_C1O) || + (ulPin == SYSCTL_PIN_C2MINUS) || + (ulPin == SYSCTL_PIN_C2PLUS) || + (ulPin == SYSCTL_PIN_C2O) || + (ulPin == SYSCTL_PIN_MC_FAULT0) || + (ulPin == SYSCTL_PIN_ADC0) || + (ulPin == SYSCTL_PIN_ADC1) || + (ulPin == SYSCTL_PIN_ADC2) || + (ulPin == SYSCTL_PIN_ADC3) || + (ulPin == SYSCTL_PIN_ADC4) || + (ulPin == SYSCTL_PIN_ADC5) || + (ulPin == SYSCTL_PIN_ADC6) || + (ulPin == SYSCTL_PIN_ADC7) || + (ulPin == SYSCTL_PIN_CCP0) || + (ulPin == SYSCTL_PIN_CCP1) || + (ulPin == SYSCTL_PIN_CCP2) || + (ulPin == SYSCTL_PIN_CCP3) || + (ulPin == SYSCTL_PIN_CCP4) || + (ulPin == SYSCTL_PIN_CCP5) || + (ulPin == SYSCTL_PIN_32KHZ)); + + // + // Determine if this pin is present. + // + if(HWREG(SYSCTL_DC3) & ulPin) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! Determines if a particular peripheral is present in the device. Each +//! member of the Stellaris family has a different peripheral set; this will +//! determine which are present on this device. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_MPU, +//! \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TEMP, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, +//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, +//! \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, +//! \b SYSCTL_PERIPH_USB0, or \b SYSCTL_PERIPH_WDOG. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +SysCtlPeripheralPresent(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Read the correct DC register and determine if this peripheral exists. + // + if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) & + SYSCTL_PERIPH_MASK(ulPeripheral)) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! deasserted, leaving the peripheral in a operating state but in its reset +//! condition. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ulPeripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \note It takes five clock cycles after the write to enable a peripheral +//! before the the peripheral is actually enabled. During this time, attempts +//! to access the peripheral will result in a bus fault. Care should be taken +//! to ensure that the peripheral is not accessed during this brief time +//! period. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ulPeripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \e ulPeripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. Those that must run at a particular frequency +//! (such as a UART) will not work as expected if the clock changes. It is the +//! responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \e ulPeripheral parameter must be one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |= + SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \e ulPeripheral parameter must be one of the following values: +//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1, +//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1, +//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, +//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, +//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0, +//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, +//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, +//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, +//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or +//! \b SYSCTL_PERIPH_WDOG. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT(SysCtlPeripheralValid(ulPeripheral)); + + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &= + ~SYSCTL_PERIPH_MASK(ulPeripheral); +} + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled they are clocked +//! according to the configuration set by SysCtlPeripheralSleepEnable(), +//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and +//! SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralClockGating(tBoolean bEnable) +{ + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This sets the handler to be called when a system control interrupt occurs. +//! This will enable the global interrupt in the interrupt controller; specific +//! system control interrupts must be enabled via SysCtlIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function will clear the handler to be called when a system control +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL); +} + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Enables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntEnable(unsigned long ulInts) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ulInts; +} + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Disables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntDisable(unsigned long ulInts) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ulInts); +} + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIntClear(unsigned long ulInts) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ulInts; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the system controller. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, +//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and +//! \b SYSCTL_INT_PLL_FAIL. +// +//***************************************************************************** +unsigned long +SysCtlIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} + +//***************************************************************************** +// +//! Sets the output voltage of the LDO. +//! +//! \param ulVoltage is the required output voltage from the LDO. Must be one +//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +//! +//! This function sets the output voltage of the LDO. The default voltage is +//! 2.5 V; it can be adjusted +/- 10%. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlLDOSet(unsigned long ulVoltage) +{ + // + // Check the arguments. + // + ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || + (ulVoltage == SYSCTL_LDO_2_30V) || + (ulVoltage == SYSCTL_LDO_2_35V) || + (ulVoltage == SYSCTL_LDO_2_40V) || + (ulVoltage == SYSCTL_LDO_2_45V) || + (ulVoltage == SYSCTL_LDO_2_50V) || + (ulVoltage == SYSCTL_LDO_2_55V) || + (ulVoltage == SYSCTL_LDO_2_60V) || + (ulVoltage == SYSCTL_LDO_2_65V) || + (ulVoltage == SYSCTL_LDO_2_70V) || + (ulVoltage == SYSCTL_LDO_2_75V)); + + // + // Set the LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOPCTL) = ulVoltage; +} + +//***************************************************************************** +// +//! Gets the output voltage of the LDO. +//! +//! This function determines the output voltage of the LDO, as specified by the +//! control register. +//! +//! \return Returns the current voltage of the LDO; will be one of +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +// +//***************************************************************************** +unsigned long +SysCtlLDOGet(void) +{ + // + // Return the LDO voltage setting. + // + return(HWREG(SYSCTL_LDOPCTL)); +} + +//***************************************************************************** +// +//! Configures the LDO failure control. +//! +//! \param ulConfig is the required LDO failure control setting; can be either +//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. +//! +//! This function allows the LDO to be configured to cause a processor reset +//! when the output voltage becomes unregulated. +//! +//! The LDO failure control is only available on Sandstorm-class devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlLDOConfigSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || + (ulConfig == SYSCTL_LDOCFG_NORST)); + + // + // Set the reset control as requested. + // + HWREG(SYSCTL_LDOARST) = ulConfig; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function will perform a software reset of the entire device. The +//! processor and all peripherals will be reset and all device registers will +//! return to their default values (with the exception of the reset cause +//! register, which will maintain its current value but have the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This will cause the device to reset, + // no further code will be executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +unsigned long +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ulCauses are the reset causes to be cleared; must be a logical OR of +//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, +//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlResetCauseClear(unsigned long ulCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ulCauses); +} + +//***************************************************************************** +// +//! Configures the brown-out control. +//! +//! \param ulConfig is the desired configuration of the brown-out control. +//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or +//! \b SYSCTL_BOR_RESAMPLE. +//! \param ulDelay is the number of internal oscillator cycles to wait before +//! resampling an asserted brown-out signal. This value only has meaning when +//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. +//! +//! This function configures how the brown-out control operates. It can detect +//! a brown-out by looking at only the brown-out output, or it can wait for it +//! to be active for two consecutive samples separated by a configurable time. +//! When it detects a brown-out condition, it can either reset the device or +//! generate a processor interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) +{ + // + // Check the arguments. + // + ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); + ASSERT(ulDelay < 8192); + + // + // Configure the brown-out reset control. + // + HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BORTIM_S) | ulConfig; +} + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! The loop takes 3 cycles/loop. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) || defined(DOXYGEN) +void +SysCtlDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne.n SysCtlDelay\n" + " bx lr"); +} +#endif +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +void __attribute__((naked)) +SysCtlDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne SysCtlDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +SysCtlDelay(unsigned long ulCount) +{ + subs r0, #1; + bne SysCtlDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ulConfig is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e ulConfig parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... +//! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16 +//! are valid on Sandstorm-class devices. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_1MHZ, \b SYSCTL_XTAL_1_84MHZ, \b SYSCTL_XTAL_2MHZ, +//! \b SYSCTL_XTAL_2_45MHZ, \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, +//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, +//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, +//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, +//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below +//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On +//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are +//! not valid. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, +//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. On Sandstorm-class devices, +//! \b SYSCTL_OSC_INT30 and \b SYSCTL_OSC_EXT32 are not valid. +//! \b SYSCTL_OSC_EXT32 is only available on devices with the hibernate module, +//! and then only when the hibernate module has been enabled. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device will be prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (that is, via +//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function will delay until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClockSet(unsigned long ulConfig) +{ + unsigned long ulDelay, ulRCC, ulRCC2; + + // + // See if this is a Sandstorm-class device and clocking features from newer + // devices were requested. + // + if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2)) + { + // + // Return without changing the clocking since the requested + // configuration can not be achieved. + // + return; + } + + // + // Get the current value of the RCC and RCC2 registers. If using a + // Sandstorm-class device, the RCC2 register will read back as zero and the + // writes to it from within this function will be ignored. + // + ulRCC = HWREG(SYSCTL_RCC); + ulRCC2 = HWREG(SYSCTL_RCC2); + + // + // Bypass the PLL and system clock dividers for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USESYSDIV); + ulRCC2 |= SYSCTL_RCC2_BYPASS2; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + + // + // See if either oscillator needs to be enabled. + // + if(((ulRCC & SYSCTL_RCC_IOSCDIS) && !(ulConfig & SYSCTL_RCC_IOSCDIS)) || + ((ulRCC & SYSCTL_RCC_MOSCDIS) && !(ulConfig & SYSCTL_RCC_MOSCDIS))) + { + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | + (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Wait for a bit, giving the oscillator time to stabilize. The number + // of iterations is adjusted based on the current clock source; a + // smaller number of iterations is required for slower clock rates. + // + if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && + (((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) || + ((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_32))) || + (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && + ((ulRCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30))) + { + // + // Delay for 4096 iterations. + // + SysCtlDelay(4096); + } + else + { + // + // Delay for 524,288 iterations. + // + SysCtlDelay(524288); + } + } + + // + // Set the new crystal value, oscillator source, and PLL configuration. + // Since the OSCSRC2 field in RCC2 overlaps the XTAL field in RCC, the + // OSCSRC field has a special encoding within ulConfig to avoid the + // overlap. + // + ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN); + ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M | + SYSCTL_RCC2_PWRDN2); + ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M | + SYSCTL_RCC2_PWRDN2); + ulRCC2 |= (ulConfig & 0x00000008) << 3; + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + // + // Write the new RCC value. + // + if(ulRCC2 & SYSCTL_RCC2_USERCC2) + { + HWREG(SYSCTL_RCC2) = ulRCC2; + HWREG(SYSCTL_RCC) = ulRCC; + } + else + { + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + } + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. + // + SysCtlDelay(16); + + // + // Set the requested system divider and disable the appropriate + // oscillators. This will not get written immediately. + // + ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | + SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | + SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M); + ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M; + if(ulConfig & SYSCTL_RCC2_USEFRACT) + { + ulRCC |= SYSCTL_RCC_USESYSDIV; + ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV); + ulRCC2 |= ulConfig & (SYSCTL_RCC2_USEFRACT | SYSCTL_RCC2_FRACT); + } + else + { + ulRCC2 &= ~(SYSCTL_RCC2_USEFRACT); + } + + // + // See if the PLL output is being used to clock the system. + // + if(!(ulConfig & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ulDelay = 32768; ulDelay > 0; ulDelay--) + { + if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + { + break; + } + } + + // + // Enable use of the PLL. + // + ulRCC &= ~(SYSCTL_RCC_BYPASS); + ulRCC2 &= ~(SYSCTL_RCC2_BYPASS2); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + HWREG(SYSCTL_RCC2) = ulRCC2; + + // + // Delay for a little bit so that the system divider takes effect. + // + SysCtlDelay(16); +} + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. This is +//! also the clock rate of all the peripheral modules (with the exception of +//! PWM, which has its own clock divider). +//! +//! \note This will not return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the later case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +unsigned long +SysCtlClockGet(void) +{ + unsigned long ulRCC, ulRCC2, ulPLL, ulClk; + + // + // Read RCC and RCC2. For Sandstorm-class devices (which do not have + // RCC2), the RCC2 read will return 0, which indicates that RCC2 is + // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear). + // + ulRCC = HWREG(SYSCTL_RCC); + ulRCC2 = HWREG(SYSCTL_RCC2); + + // + // Get the base clock rate. + // + switch((ulRCC2 & SYSCTL_RCC2_USERCC2) ? + (ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) : + (ulRCC & SYSCTL_RCC_OSCSRC_M)) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ulClk = g_pulXtals[(ulRCC & SYSCTL_RCC_XTAL_M) >> + SYSCTL_RCC_XTAL_S]; + break; + } + + // + // The internal oscillator is the source clock. + // + case SYSCTL_RCC_OSCSRC_INT: + { + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // The internal oscillator on a Sandstorm-class device is + // 15 MHz +/- 50%. + // + ulClk = 15000000; + } + else if((CLASS_IS_FURY && REVISION_IS_A2) || + (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) + { + // + // The internal oscillator on a rev A2 Fury-class device and a + // rev A0 Dustdevil-class device is 12 MHz +/- 30%. + // + ulClk = 12000000; + } + else + { + // + // The internal oscillator on all other devices is 16 MHz. + // + ulClk = 16000000; + } + break; + } + + // + // The internal oscillator divided by four is the source clock. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // The internal oscillator on a Sandstorm-class device is + // 15 MHz +/- 50%. + // + ulClk = 15000000 / 4; + } + else if((CLASS_IS_FURY && REVISION_IS_A2) || + (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) + { + // + // The internal oscillator on a rev A2 Fury-class device and a + // rev A0 Dustdevil-class device is 12 MHz +/- 30%. + // + ulClk = 12000000 / 4; + } + else + { + // + // The internal oscillator on a Tempest-class device is 16 MHz. + // + ulClk = 16000000 / 4; + } + break; + } + + // + // The internal 30 KHz oscillator is the source clock. + // + case SYSCTL_RCC_OSCSRC_30: + { + // + // The internal 30 KHz oscillator has an accuracy of +/- 30%. + // + ulClk = 30000; + break; + } + + // + // The 4.19 MHz clock from the hibernate module is the clock source. + // + case SYSCTL_RCC2_OSCSRC2_419: + { + ulClk = 4194304; + break; + } + + // + // The 32 KHz clock from the hibernate module is the source clock. + // + case SYSCTL_RCC2_OSCSRC2_32: + { + ulClk = 32768; + break; + } + + // + // An unknown setting, so return a zero clock (that is, an unknown + // clock rate). + // + default: + { + return(0); + } + } + + // + // See if the PLL is being used. + // + if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) || + (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS))) + { + // + // Get the PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // See if this is a Sandstorm-class or Fury-class device. + // + if(CLASS_IS_SANDSTORM) + { + // + // Compute the PLL output frequency based on its input frequency. + // The formula for a Sandstorm-class devices is + // "(xtal * (f + 2)) / (r + 2)". + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 2)); + } + else + { + // + // Compute the PLL output frequency based on its input frequency. + // The formula for a Fury-class device is + // "(xtal * f) / ((r + 1) * 2)". + // + ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S)) / + ((((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 1) * 2)); + } + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } + } + + // + // See if the system divider is being used. + // + if(ulRCC & SYSCTL_RCC_USESYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + if(ulRCC2 & SYSCTL_RCC2_USERCC2) + { + if((ulRCC2 & SYSCTL_RCC2_USEFRACT) && + (((ulRCC2 & SYSCTL_RCC2_USERCC2) && + !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) || + (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && + !(ulRCC & SYSCTL_RCC_BYPASS)))) + + { + ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M | + SYSCTL_RCC2_FRACT)) >> + (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1)); + } + else + { + ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >> + SYSCTL_RCC2_SYSDIV2_S) + 1); + } + } + else + { + ulClk /= (((ulRCC & SYSCTL_RCC_SYSDIV_M) >> SYSCTL_RCC_SYSDIV_S) + + 1); + } + } + + // + // Return the computed clock rate. + // + return(ulClk); +} + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ulConfig is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function sets the rate of the clock provided to the PWM module as a +//! ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPWMClockSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_PWMDIV_1) || + (ulConfig == SYSCTL_PWMDIV_2) || + (ulConfig == SYSCTL_PWMDIV_4) || + (ulConfig == SYSCTL_PWMDIV_8) || + (ulConfig == SYSCTL_PWMDIV_16) || + (ulConfig == SYSCTL_PWMDIV_32) || + (ulConfig == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) | + ulConfig); +} + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return Returns the current PWM clock configuration; will be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +// +//***************************************************************************** +unsigned long +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Return the current PWM clock configuration. Make sure that + // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled. + // + if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV)) + { + // + // The divider is not active so reflect this in the value we return. + // + return(SYSCTL_PWMDIV_1); + } + else + { + // + // The divider is active so directly return the masked register value. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)); + } +} + +//***************************************************************************** +// +//! Sets the sample rate of the ADC. +//! +//! \param ulSpeed is the desired sample rate of the ADC; must be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +//! +//! This function sets the rate at which the ADC samples are captured by the +//! ADC block. The sampling speed may be limited by the hardware, so the +//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() +//! will return the actual speed in use. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlADCSpeedSet(unsigned long ulSpeed) +{ + // + // Check the arguments. + // + ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || + (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); + + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0); + + // + // Set the ADC speed in run, sleep, and deep-sleep mode. + // + HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) | + ulSpeed); + HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) | + ulSpeed); + HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_DCGC0_ADCSPD_M)) | + ulSpeed); +} + +//***************************************************************************** +// +//! Gets the sample rate of the ADC. +//! +//! This function gets the current sample rate of the ADC. +//! +//! \return Returns the current ADC sample rate; will be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +// +//***************************************************************************** +unsigned long +SysCtlADCSpeedGet(void) +{ + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0); + + // + // Return the current ADC speed. + // + return(HWREG(SYSCTL_RCGC0) & SYSCTL_RCGC0_ADCSPD_M); +} + +//***************************************************************************** +// +//! Configures the internal oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the internal oscillator +//! verification timer should be enabled. +//! +//! This function allows the internal oscillator verification timer to be +//! enabled or disabled. When enabled, an interrupt will be generated if the +//! internal oscillator ceases to operate. +//! +//! The internal oscillator verification timer is only available on +//! Sandstorm-class devices. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the main oscillator will verify the +//! internal oscillator. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlIOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the internal oscillator verification timer as + // requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); + } +} + +//***************************************************************************** +// +//! Configures the main oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the main oscillator +//! verification timer should be enabled. +//! +//! This function allows the main oscillator verification timer to be enabled +//! or disabled. When enabled, an interrupt will be generated if the main +//! oscillator ceases to operate. +//! +//! The main oscillator verification timer is only available on +//! Sandstorm-class devices. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the internal oscillator will verify the +//! main oscillator. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlMOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the main oscillator verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); + } +} + +//***************************************************************************** +// +//! Configures the PLL verification timer. +//! +//! \param bEnable is a boolean that is \b true if the PLL verification timer +//! should be enabled. +//! +//! This function allows the PLL verification timer to be enabled or disabled. +//! When enabled, an interrupt will be generated if the PLL ceases to operate. +//! +//! The PLL verification timer is only available on Sandstorm-class devices. +//! +//! \note The main oscillator must be enabled for this verification timer to +//! operate as it is used to check the PLL. Also, the verification timer +//! should be disabled while the PLL is being reconfigured via +//! SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPLLVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the PLL verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); + } +} + +//***************************************************************************** +// +//! Clears the clock verification status. +//! +//! This function clears the status of the clock verification timers, allowing +//! them to assert another failure if detected. +//! +//! The clock verification timers are only available on Sandstorm-class +//! devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClkVerificationClear(void) +{ + // + // Clear the clock verification. + // + HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_VERCLR; + + // + // The bit does not self-reset, so clear it. + // + HWREG(SYSCTL_CLKVCLR) = 0; +} + +//***************************************************************************** +// +//! Enables a GPIO peripheral for access from the AHB. +//! +//! \param ulGPIOPeripheral is the GPIO peripheral to enable. +//! +//! This function is used to enable the specified GPIO peripheral to be +//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced +//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access, +//! the \b _AHB_BASE form of the base address should be used for GPIO +//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base +//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead. +//! +//! The \e ulGPIOPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); + + // + // Enable this GPIO for AHB access. + // + HWREG(SYSCTL_GPIOHSCTL) |= ulGPIOPeripheral & 0xFFFF; +} + +//***************************************************************************** +// +//! Disables a GPIO peripheral for access from the AHB. +//! +//! \param ulGPIOPeripheral is the GPIO peripheral to disable. +//! +//! This function disables the specified GPIO peripheral for access from the +//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed +//! from the legacy Advanced Peripheral Bus (AHB). +//! +//! The \b ulGPIOPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, +//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, +//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) || + (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); + + // + // Disable this GPIO for AHB access. + // + HWREG(SYSCTL_GPIOHSCTL) &= ~(ulGPIOPeripheral & 0xFFFF); +} + +//***************************************************************************** +// +//! Powers up the USB PLL. +//! +//! This function will enable the USB controller's PLL which is used by it's +//! physical layer. This call is necessary before connecting to any external +//! devices. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLEnable(void) +{ + // + // Turn on the USB PLL. + // + HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN; +} + +//***************************************************************************** +// +//! Powers down the USB PLL. +//! +//! This function will disable the USB controller's PLL which is used by it's +//! physical layer. The USB registers are still accessible, but the physical +//! layer will no longer function. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLDisable(void) +{ + // + // Turn of USB PLL. + // + HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; +} + +//***************************************************************************** +// +//! Sets the MCLK frequency provided to the I2S module. +//! +//! \param ulInputClock is the input clock to the MCLK divider. If this is +//! zero, the value is computed from the current PLL configuration. +//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output +//! is disabled. +//! +//! This function sets the dividers to provide MCLK to the I2S module. A MCLK +//! divider will be chosen that produces the MCLK frequency that is the closest +//! possible to the requested frequency, which may be above or below the +//! requested frequency. +//! +//! The actual MCLK frequency will be returned. It is the responsibility of +//! the application to determine if the selected MCLK is acceptable; in general +//! the human ear can not discern the frequency difference if it is within 0.3% +//! of the desired frequency (though there is a very small percentage of the +//! population that can discern lower frequency deviations). +//! +//! \return Returns the actual MCLK frequency. +// +//***************************************************************************** +unsigned long +SysCtlI2SMClkSet(unsigned long ulInputClock, unsigned long ulMClk) +{ + unsigned long ulDivInt, ulDivFrac, ulPLL; + + // + // See if the I2S MCLK should be disabled. + // + if(ulMClk == 0) + { + // + // Disable the I2S MCLK and return. + // + HWREG(SYSCTL_I2SMCLKCFG) = 0; + return(0); + } + + // + // See if the input clock was specified. + // + if(ulInputClock == 0) + { + // + // The input clock was not specified, so compute the output frequency + // of the PLL. Get the current PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // Get the frequency of the crystal in use. + // + ulInputClock = g_pulXtals[(HWREG(SYSCTL_RCC) & SYSCTL_RCC_XTAL_M) >> + SYSCTL_RCC_XTAL_S]; + + // + // Calculate the PLL output frequency. + // + ulInputClock = ((ulInputClock * ((ulPLL & SYSCTL_PLLCFG_F_M) >> + SYSCTL_PLLCFG_F_S)) / + ((((ulPLL & SYSCTL_PLLCFG_R_M) >> + SYSCTL_PLLCFG_R_S) + 1))); + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulInputClock /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulInputClock /= 4; + } + } + + // + // Verify that the requested MCLK frequency is attainable. + // + ASSERT(ulMClk < ulInputClock); + + // + // Add a rounding factor to the input clock, so that the MCLK frequency + // that is closest to the desire value is selected. + // + ulInputClock += (ulMClk / 32) - 1; + + // + // Compute the integer portion of the MCLK divider. + // + ulDivInt = ulInputClock / ulMClk; + + // + // If the divisor is too large, then simply use the maximum divisor. + // + if(CLASS_IS_TEMPEST && REVISION_IS_B1 && (ulDivInt > 255)) + { + ulDivInt = 255; + ulDivFrac = 15; + } + else if(ulDivInt > 1023) + { + ulDivInt = 1023; + ulDivFrac = 15; + } + else + { + // + // Compute the fractional portion of the MCLK divider. + // + ulDivFrac = ((ulInputClock - (ulDivInt * ulMClk)) * 16) / ulMClk; + } + + // + // Set the divisor for the Tx and Rx MCLK generators and enable the clocks. + // + HWREG(SYSCTL_I2SMCLKCFG) = (SYSCTL_I2SMCLKCFG_RXEN | + (ulDivInt << SYSCTL_I2SMCLKCFG_RXI_S) | + (ulDivFrac << SYSCTL_I2SMCLKCFG_RXF_S) | + SYSCTL_I2SMCLKCFG_TXEN | + (ulDivInt << SYSCTL_I2SMCLKCFG_TXI_S) | + (ulDivFrac << SYSCTL_I2SMCLKCFG_TXF_S)); + + // + // Return the actual MCLK frequency. + // + ulInputClock -= (ulMClk / 32) - 1; + ulDivInt = (ulDivInt * 16) + ulDivFrac; + ulMClk = (ulInputClock / ulDivInt) * 16; + ulMClk += ((ulInputClock - ((ulMClk / 16) * ulDivInt)) * 16) / ulDivInt; + return(ulMClk); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/sysctl.h b/bsp/lm3s/driverlib/sysctl.h new file mode 100644 index 0000000000..3cef7f7621 --- /dev/null +++ b/bsp/lm3s/driverlib/sysctl.h @@ -0,0 +1,469 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#ifndef DEPRECATED +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#endif +#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0 +#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module +#ifndef DEPRECATED +#define SYSCTL_PERIPH_ADC 0x00100001 // ADC +#endif +#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0 +#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1 +#define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 +#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 +#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1 +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#endif +#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#endif +#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#endif +#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 +#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 +#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 +#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0 +#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J +#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA +#define SYSCTL_PERIPH_USB0 0x20100001 // USB0 +#define SYSCTL_PERIPH_ETH 0x20105000 // ETH +#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin +#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc. +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlDelay(unsigned long ulCount); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); +extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock, + unsigned long ulMClk); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/bsp/lm3s/driverlib/systick.c b/bsp/lm3s/driverlib/systick.c new file mode 100644 index 0000000000..4296851443 --- /dev/null +++ b/bsp/lm3s/driverlib/systick.c @@ -0,0 +1,262 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to SysTickPeriodSet(). If +//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This sets the handler to be called when a SysTick interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically by NVIC when the interrupt +//! handler is called. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on +//! the next clock after the SysTick is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/systick.h b/bsp/lm3s/driverlib/systick.h new file mode 100644 index 0000000000..e3d9d58759 --- /dev/null +++ b/bsp/lm3s/driverlib/systick.h @@ -0,0 +1,66 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/bsp/lm3s/driverlib/timer.c b/bsp/lm3s/driverlib/timer.c new file mode 100644 index 0000000000..8065376d1b --- /dev/null +++ b/bsp/lm3s/driverlib/timer.c @@ -0,0 +1,1007 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_timer.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/timer.h" + +//***************************************************************************** +// +//! \internal +//! Checks a timer base address. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function determines if a timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +TimerBaseValid(unsigned long ulBase) +{ + return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE)); +} +#endif + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will enable operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will disable operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured, and is left in the disabled +//! state. The configuration is specified in \e ulConfig as one of the +//! following values: +//! +//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer +//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer +//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer +//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers +//! +//! When configured for a pair of 16-bit timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer +//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer +//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture +//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture +//! - \b TIMER_CFG_A_PWM - 16-bit PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || + (ulConfig == TIMER_CFG_32_BIT_PER) || + (ulConfig == TIMER_CFG_32_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; + HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; +} + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function sets the PWM output level for the specified timer. If the +//! \e bInvert parameter is \b true, then the timer's output will be made +//! active low; otherwise, it will be made active high. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Enables or disables the trigger output. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired trigger state. +//! +//! This function controls the trigger output for the specified timer. If the +//! \e bEnable parameter is \b true, then the timer's output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the trigger output as requested. + // + ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ulBase + TIMER_O_CTL) = (bEnable ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function sets the signal edge(s) that will trigger the timer when in +//! capture mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M); + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & + ~(TIMER_CTL_TAEVENT_M | + TIMER_CTL_TBEVENT_M)) | ulEvent); +} + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer will stop counting if the +//! processor enters debug mode; otherwise the timer will keep running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Enable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this will do nothing. +//! +//! \return None. +// +//***************************************************************************** +void +TimerRTCEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Enable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} + +//***************************************************************************** +// +//! Disable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerRTCDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value; must be between 0 and 255, +//! inclusive. +//! +//! This function sets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the load value. +//! +//! This function sets the timer load value; if the timer is running then the +//! value will be immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : + HWREG(ulBase + TIMER_O_TBR)); +} + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the match value. +//! +//! This function sets the match value for a timer. This is used in capture +//! count mode to determine when to interrupt the processor and in PWM mode to +//! determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This sets the handler to be called when a timer interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific +//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : + ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A))); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function will clear the handler to be called when a timer interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : + ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A))); + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b TIMER_CAPB_EVENT - Capture B event interrupt +//! - \b TIMER_CAPB_MATCH - Capture B match interrupt +//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - \b TIMER_RTC_MATCH - RTC interrupt mask +//! - \b TIMER_CAPA_EVENT - Capture A event interrupt +//! - \b TIMER_CAPA_MATCH - Capture A match interrupt +//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the timer module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +// Puts the timer into its reset state. +// +// \param ulBase is the base address of the timer module. +// +// The specified timer is disabled, and all its interrupts are disabled, +// cleared, and unregistered. Then the timer registers are set to their reset +// value. +// +// \return None. +// +//***************************************************************************** +#ifndef DEPRECATED +void +TimerQuiesce(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable the timer. + // + HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; + + // + // Disable all the timer interrupts. + // + HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; + + // + // Clear all the timer interrupts. + // + HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; + + // + // Unregister the interrupt handler. This also disables interrupts to the + // core. + // + TimerIntUnregister(ulBase, TIMER_BOTH); + + // + // Set all the registers to their reset value. + // + HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; + HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; + HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; + HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; + HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; + HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; + HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; + HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; + HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; + HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; + HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; + HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; + HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; + HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; + HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; +} +#endif // DEPRECATED + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/timer.h b/bsp/lm3s/driverlib/timer.h new file mode 100644 index 0000000000..978f5344db --- /dev/null +++ b/bsp/lm3s/driverlib/timer.h @@ -0,0 +1,153 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used +// instead to return the timer to its reset state. +// +//***************************************************************************** +#ifndef DEPRECATED +extern void TimerQuiesce(unsigned long ulBase); +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/bsp/lm3s/driverlib/uart.c b/bsp/lm3s/driverlib/uart.c new file mode 100644 index 0000000000..648e6abead --- /dev/null +++ b/bsp/lm3s/driverlib/uart.c @@ -0,0 +1,1621 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/uart.h" + +//***************************************************************************** +// +// The system clock divider defining the maximum baud rate supported by the +// UART. +// +//***************************************************************************** +#define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \ + (CLASS_IS_FURY && REVISION_IS_A2) || \ + (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \ + 16 : 8) + +//***************************************************************************** +// +//! \internal +//! Checks a UART base address. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function determines if a UART port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +UARTBaseValid(unsigned long ulBase) +{ + return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it will always be either be one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ulParity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets the type of parity used for transmitting data, and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of +//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, +//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of +//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, +//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! will be generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulTxLevel == UART_FIFO_TX1_8) || + (ulTxLevel == UART_FIFO_TX2_8) || + (ulTxLevel == UART_FIFO_TX4_8) || + (ulTxLevel == UART_FIFO_TX6_8) || + (ulTxLevel == UART_FIFO_TX7_8)); + ASSERT((ulRxLevel == UART_FIFO_RX1_8) || + (ulRxLevel == UART_FIFO_RX2_8) || + (ulRxLevel == UART_FIFO_RX4_8) || + (ulRxLevel == UART_FIFO_RX6_8) || + (ulRxLevel == UART_FIFO_RX7_8)); + + // + // Set the FIFO interrupt levels. + // + HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulTxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8. +//! \param pulRxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! will be generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Read the FIFO level register. + // + ulTemp = HWREG(ulBase + UART_O_IFLS); + + // + // Extract the transmit and receive FIFO levels. + // + *pulTxLevel = ulTemp & UART_IFLS_TX_M; + *pulRxLevel = ulTemp & UART_IFLS_RX_M; +} + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulUARTClk is the rate of the clock supplied to the UART module. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function will configure the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the data +//! format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original UARTConfigSet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig) +{ + unsigned long ulDiv; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT(ulBaud != 0); + ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER)); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Is the required baud rate greater than the maximum rate supported + // without the use of high speed mode? + // + if((ulBaud * 16) > ulUARTClk) + { + // + // Enable high speed mode. + // + HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; + + // + // Half the supplied baud rate to compensate for enabling high speed + // mode. This allows the following code to be common to both cases. + // + ulBaud /= 2; + } + else + { + // + // Disable high speed mode. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); + } + + // + // Compute the fractional baud rate divider. + // + ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2; + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; + HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCRH) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulUARTClk is the rate of the clock supplied to the UART module. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSetExpClk(). +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original UARTConfigGet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, unsigned long *pulConfig) +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac); + + // + // See if high speed mode enabled. + // + if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) + { + // + // High speed mode is enabled so the actual baud rate is actually + // double what was just calculated. + // + *pulBaud *= 2; + } + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFODisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! Enables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param bLowPower indicates if SIR Low Power Mode is to be used. +//! +//! Enables the SIREN control bit for IrDA mode on the UART. If the +//! \e bLowPower flag is set, then SIRLP bit will also be set. +//! +//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable SIR and SIRLP (if appropriate). + // + if(bLowPower) + { + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); + } + else + { + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN); + } +} + +//***************************************************************************** +// +//! Disables SIR (IrDA) mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits. +//! +//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisableSIR(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable SIR and SIRLP (if appropriate). + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); +} + +//***************************************************************************** +// +//! Enables ISO 7816 smart card mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Enables the SMART control bit for ISO 7816 smart card mode on the UART. +//! This call also sets 8 bit word length and even parity as required by ISO +//! 7816. +//! +//! \note The availability of ISO 7816 smart card mode varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTSmartCardEnable(unsigned long ulBase) +{ + unsigned long ulVal; + + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); + + // + // Set 8 bit word length, even parity, 2 stop bits (even though the STP2 + // bit is ignored when in smartcard mode, this lets the caller read back + // the actual setting in use). + // + ulVal = HWREG(ulBase + UART_O_LCRH); + ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | + UART_LCRH_WLEN_M); + ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2; + HWREG(ulBase + UART_O_LCRH) = ulVal; + + // + // Enable SMART mode. + // + HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART; +} + +//***************************************************************************** +// +//! Disables ISO 7816 smart card mode on the specified UART. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the SMART (ISO 7816 smart card) bits in the UART control register. +//! +//! \note The availability of ISO 7816 smart card mode varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTSmartCardDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); + + // + // Disable the SMART bit. + // + HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART; +} + +//***************************************************************************** +// +//! Sets the states of the DTR and/or RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! Sets the states of the DTR or RTS modem handshake outputs from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal +//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); + + // + // Set the appropriate modem control output bits. + // + ulTemp = HWREG(ulBase + UART_O_CTL); + ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); + HWREG(ulBase + UART_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Clears the states of the DTR and/or RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! Clears the states of the DTR or RTS modem handshake outputs from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal +//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); + + // + // Set the appropriate modem control output bits. + // + ulTemp = HWREG(ulBase + UART_O_CTL); + ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); + HWREG(ulBase + UART_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the states of the DTR and RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Returns the current states of each of the two UART modem control signals, +//! DTR and RTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signals. This will be a +//! logical logical OR combination of values \b UART_OUTPUT_RTS and +//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the +//! associated signal is asserted. +// +//***************************************************************************** +unsigned long +UARTModemControlGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + + return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); +} + +//***************************************************************************** +// +//! Gets the states of the RI, DCD, DSR and CTS modem status signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Returns the current states of each of the four UART modem status signals, +//! RI, DCD, DSR and CTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! Stellaris part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signals. This will be a +//! logical logical OR combination of values \b UART_INPUT_RI, \b +//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the +//! presence of each flag indicates that the associated signal is asserted. +// +//***************************************************************************** +unsigned long +UARTModemStatusGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT(ulBase == UART1_BASE); + + return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | + UART_INPUT_CTS | UART_INPUT_DSR)); +} + +//***************************************************************************** +// +//! Sets the UART hardware flow control mode to be used. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode indicates the flow control modes to be used. This is a +//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b +//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) +//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. +//! +//! Sets the required hardware flow control modes. If \e ulMode contains +//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS +//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX, +//! the RTS output is controlled by the hardware and is asserted only when +//! there is space available in the receive FIFO. If no hardware flow control +//! is required, UART_FLOWCONTROL_NONE should be passed. +//! +//! \note The availability of hardware flow control varies with the Stellaris +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); + ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); + + // + // Set the flow control mode as requested. + // + HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & + ~(UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)) | ulMode); +} + +//***************************************************************************** +// +//! Returns the UART hardware flow control mode currently in use. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Returns the current hardware flow control mode. +//! +//! \note The availability of hardware flow control varies with the Stellaris +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns the current flow control mode in use. This is a +//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit +//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) +//! flow control is in use. If hardware flow control is disabled, \b +//! UART_FLOWCONTROL_NONE will be returned. +// +//***************************************************************************** +unsigned long +UARTFlowControlGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL); + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); + + return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)); +} + +//***************************************************************************** +// +//! Sets the operating mode for the UART transmit interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode is the operating mode for the transmit interrupt. It may be +//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle +//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO +//! level. +//! +//! This function allows the mode of the UART transmit interrupt to be set. By +//! default, the transmit interrupt is asserted when the FIFO level falls past +//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this +//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the +//! transmit interrupt will only be asserted once the transmitter is completely +//! idle - the transmit FIFO is empty and all bits, including any stop bits, +//! have cleared the transmitter. +//! +//! \note The availability of end-of-transmission mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); + ASSERT((ulMode == UART_TXINT_MODE_EOT) || + (ulMode == UART_TXINT_MODE_FIFO)); + + // + // Set or clear the EOT bit of the UART control register as appropriate. + // + HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & + ~(UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)) | ulMode); +} + +//***************************************************************************** +// +//! Returns the current operating mode for the UART transmit interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current operating mode for the UART transmit +//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the +//! transmit interrupt is currently set to be asserted once the transmitter is +//! completely idle - the transmit FIFO is empty and all bits, including any +//! stop bits, have cleared the transmitter. The return value will be \b +//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the +//! level of the transmit FIFO. +//! +//! \note The availability of end-of-transmission mode varies with the +//! Stellaris part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. +// +//***************************************************************************** +unsigned long +UARTTxIntModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || + (ulBase == UART2_BASE)); + + // + // Return the current transmit interrupt mode. + // + return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)); +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO, and \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO, +//! and \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! This function replaces the original UARTCharNonBlockingGet() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 will be returned if there are no characters present in +//! the receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +long +UARTCharGetNonBlocking(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function will wait until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as an +//! \e long. +// +//***************************************************************************** +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application will have to retry the function +//! later. +//! +//! This function replaces the original UARTCharNonBlockingPut() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO, and \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +tBoolean +UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function will +//! wait until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true will assert a +//! break condition on the UART. Calling this function with \e bBreakState set +//! to \b false will remove the break condition. For proper transmission of a +//! break command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCRH) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! Determines whether the UART transmitter is busy or not. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \b false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +tBoolean +UARTBusy(unsigned long ulBase) +{ + // + // Check the argument. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine if the UART is busy. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = ((ulBase == UART0_BASE) ? INT_UART0 : + ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2)); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = ((ulBase == UART0_BASE) ? INT_UART0 : + ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2)); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b UART_INT_OE - Overrun Error interrupt +//! - \b UART_INT_BE - Break Error interrupt +//! - \b UART_INT_PE - Parity Error interrupt +//! - \b UART_INT_FE - Framing Error interrupt +//! - \b UART_INT_RT - Receive Timeout interrupt +//! - \b UART_INT_TX - Transmit interrupt +//! - \b UART_INT_RX - Receive interrupt +//! - \b UART_INT_DSR - DSR interrupt +//! - \b UART_INT_DCD - DCD interrupt +//! - \b UART_INT_CTS - CTS interrupt +//! - \b UART_INT_RI - RI interrupt +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Enable UART DMA operation. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulDMAFlags is a bit mask of the DMA features to enable. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. The \e ulDMAFlags parameter is the +//! logical OR of any of the following values: +//! +//! - UART_DMA_RX - enable DMA for receive +//! - UART_DMA_TX - enable DMA for transmit +//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the requested bits in the UART DMA control register. + // + HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; +} + +//***************************************************************************** +// +//! Disable UART DMA operation. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulDMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable UART DMA features that were enabled +//! by UARTDMAEnable(). The specified UART DMA features are disabled. The +//! \e ulDMAFlags parameter is the logical OR of any of the following values: +//! +//! - UART_DMA_RX - disable DMA for receive +//! - UART_DMA_TX - disable DMA for transmit +//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Clear the requested bits in the UART DMA control register. + // + HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; +} + +//***************************************************************************** +// +//! Gets current receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK +//! and \b UART_RXERROR_OVERRUN. +// +//***************************************************************************** +unsigned long +UARTRxErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current value of the receive status register. + // + return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! Clears all reported receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRxErrorClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Any write to the Error Clear Register will clear all bits which are + // currently set. + // + HWREG(ulBase + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/uart.h b/bsp/lm3s/driverlib/uart.h new file mode 100644 index 0000000000..5c8416cc1b --- /dev/null +++ b/bsp/lm3s/driverlib/uart.h @@ -0,0 +1,246 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask +#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask +#define UART_INT_RI 0x001 // RI Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTFIFOEnable(unsigned long ulBase); +extern void UARTFIFODisable(unsigned long ulBase); +extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); +extern void UARTDisableSIR(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern tBoolean UARTBusy(unsigned long ulBase); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern unsigned long UARTRxErrorGet(unsigned long ulBase); +extern void UARTRxErrorClear(unsigned long ulBase); +extern void UARTSmartCardEnable(unsigned long ulBase); +extern void UARTSmartCardDisable(unsigned long ulBase); +extern void UARTModemControlSet(unsigned long ulBase, + unsigned long ulControl); +extern void UARTModemControlClear(unsigned long ulBase, + unsigned long ulControl); +extern unsigned long UARTModemControlGet(unsigned long ulBase); +extern unsigned long UARTModemStatusGet(unsigned long ulBase); +extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTFlowControlGet(unsigned long ulBase); +extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTTxIntModeGet(unsigned long ulBase); + +//***************************************************************************** +// +// Several UART APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define UARTConfigSet(a, b, c) \ + UARTConfigSetExpClk(a, SysCtlClockGet(), b, c) +#define UARTConfigGet(a, b, c) \ + UARTConfigGetExpClk(a, SysCtlClockGet(), b, c) +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/bsp/lm3s/driverlib/udma.c b/bsp/lm3s/driverlib/udma.c new file mode 100644 index 0000000000..3f4729ce45 --- /dev/null +++ b/bsp/lm3s/driverlib/udma.c @@ -0,0 +1,1247 @@ +//***************************************************************************** +// +// udma.c - Driver for the micro-DMA controller. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_udma.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/udma.h" + +//***************************************************************************** +// +//! Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAEnable(void) +{ + // + // Set the master enable bit in the config register. + // + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; +} + +//***************************************************************************** +// +//! Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller will not operate until re-enabled with uDMAEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMADisable(void) +{ + // + // Clear the master enable bit in the config register. + // + HWREG(UDMA_CFG) = 0; +} + +//***************************************************************************** +// +//! Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +unsigned long +uDMAErrorStatusGet(void) +{ + // + // Return the uDMA error status. + // + return(HWREG(UDMA_ERRCLR)); +} + +//***************************************************************************** +// +//! Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. It should be called +//! from within the uDMA error interrupt handler to clear the interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAErrorStatusClear(void) +{ + // + // Clear the uDMA error interrupt. + // + HWREG(UDMA_ERRCLR) = 1; +} + +//***************************************************************************** +// +//! Enables a uDMA channel for operation. +//! +//! \param ulChannel is the channel number to enable. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel will be automatically +//! disabled by the uDMA controller. Therefore, this function should be called +//! prior to starting up any new transfer. +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelEnable(unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + + // + // Set the bit for this channel in the enable set register. + // + HWREG(UDMA_ENASET) = 1 << ulChannel; +} + +//***************************************************************************** +// +//! Disables a uDMA channel for operation. +//! +//! \param ulChannel is the channel number to disable. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! will not respond to uDMA transfer requests until re-enabled via +//! uDMAChannelEnable(). +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelDisable(unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + + // + // Set the bit for this channel in the enable clear register. + // + HWREG(UDMA_ENACLR) = 1 << ulChannel; +} + +//***************************************************************************** +// +//! Checks if a uDMA channel is enabled for operation. +//! +//! \param ulChannel is the channel number to check. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! can be used to check the status of a transfer, since the channel will +//! be automatically disabled at the end of a transfer. +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! \return Returns \b true if the channel is enabled, \b false if disabled. +// +//***************************************************************************** +tBoolean +uDMAChannelIsEnabled(unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + + // + // AND the specified channel bit with the enable register, and return the + // result. + // + return((HWREG(UDMA_ENASET) & (1 << ulChannel)) ? true : false); +} + +//***************************************************************************** +// +//! Sets the base address for the channel control table. +//! +//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! of the uDMA channel control table. +//! +//! This function sets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. The table must be aligned on a 1024 byte boundary. The base +//! address must be set before any of the channel functions can be used. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels, and which transfer modes are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAControlBaseSet(void *pControlTable) +{ + // + // Check the arguments. + // + ASSERT(((unsigned long)pControlTable & ~0x3FF) == + (unsigned long)pControlTable); + ASSERT((unsigned long)pControlTable >= 0x20000000); + + // + // Program the base address into the register. + // + HWREG(UDMA_CTLBASE) = (unsigned long)pControlTable; +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +void * +uDMAControlBaseGet(void) +{ + // + // Read the current value of the control base register, and return it to + // the caller. + // + return((void *)HWREG(UDMA_CTLBASE)); +} + +//***************************************************************************** +// +//! Requests a uDMA channel to start a transfer. +//! +//! \param ulChannel is the channel number on which to request a uDMA transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This could be used for performing a memory to memory transfer, +//! or if for some reason a transfer needs to be initiated by software instead +//! of the peripheral associated with that channel. +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then +//! the completion will be signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion will be signaled on the +//! peripheral's interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelRequest(unsigned long ulChannel) +{ + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + + // + // Set the bit for this channel in the software uDMA request register. + // + HWREG(UDMA_SWREQ) = 1 << ulChannel; +} + +//***************************************************************************** +// +//! Enables attributes of a uDMA channel. +//! +//! \param ulChannel is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // Set the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_USEBURSTSET) = 1 << ulChannel; + } + + // + // Set the alternate control select bit for this channel, + // if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_ALTSET) = 1 << ulChannel; + } + + // + // Set the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_PRIOSET) = 1 << ulChannel; + } + + // + // Set the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_REQMASKSET) = 1 << ulChannel; + } +} + +//***************************************************************************** +// +//! Disables attributes of a uDMA channel. +//! +//! \param ulChannel is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(unsigned long ulChannel, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // Clear the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_USEBURSTCLR) = 1 << ulChannel; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_ALTCLR) = 1 << ulChannel; + } + + // + // Clear the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_PRIOCLR) = 1 << ulChannel; + } + + // + // Clear the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_REQMASKCLR) = 1 << ulChannel; + } +} + +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel. +//! +//! \param ulChannel is the channel to configure. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! The \e ulChannel parameter must be one of the following: +//! +//! - \b UDMA_CHANNEL_UART0RX for UART 0 receive channel +//! - \b UDMA_CHANNEL_UART0TX for UART 0 transmit channel +//! - \b UDMA_CHANNEL_UART1RX for UART 1 receive channel +//! - \b UDMA_CHANNEL_UART1TX for UART 1 transmit channel +//! - \b UDMA_CHANNEL_SSI0RX for SSI 0 receive channel +//! - \b UDMA_CHANNEL_SSI0TX for SSI 0 transmit channel +//! - \b UDMA_CHANNEL_SSI1RX for SSI 1 receive channel +//! - \b UDMA_CHANNEL_SSI1TX for SSI 1 transmit channel +//! - \b UDMA_CHANNEL_SW for the software dedicated uDMA channel +//! +//! And for microcontrollers that have a USB peripheral: +//! +//! - \b UDMA_CHANNEL_USBEP1RX for USB endpoint 1 receive +//! - \b UDMA_CHANNEL_USBEP1TX for USB endpoint 1 transmit +//! - \b UDMA_CHANNEL_USBEP2RX for USB endpoint 2 receive +//! - \b UDMA_CHANNEL_USBEP2TX for USB endpoint 2 transmit +//! - \b UDMA_CHANNEL_USBEP3RX for USB endpoint 3 receive +//! - \b UDMA_CHANNEL_USBEP3TX for USB endpoint 3 transmit +//! +//! \return Returns the logical OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +unsigned long +uDMAChannelAttributeGet(unsigned long ulChannel) +{ + unsigned long ulAttr = 0; + + // + // Check the arguments. + // + ASSERT(ulChannel < 32); + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannel)) + { + ulAttr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(UDMA_ALTSET) & (1 << ulChannel)) + { + ulAttr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(UDMA_PRIOSET) & (1 << ulChannel)) + { + ulAttr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(UDMA_REQMASKSET) & (1 << ulChannel)) + { + ulAttr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ulAttr); +} + +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel. +//! +//! \param ulChannel is the logical OR of the uDMA channel number with +//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulControl is logical OR of several control values to set the control +//! parameters for the channel. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! are typically parameters that are not changed often. +//! +//! The \e ulChannel parameter is one of the choices documented in the +//! uDMAChannelEnable() function. It should be the logical OR of the channel +//! with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether +//! the primary or alternate data structure is used. +//! +//! The \e ulControl parameter is the logical OR of five values: the data size, +//! the source address increment, the destination address increment, the +//! arbitration size, and the use burst flag. The choices available for each +//! of these values is described below. +//! +//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or +//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. +//! +//! Choose the source address increment from one of \b UDMA_SRC_INC_8, +//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or +//! to select non-incrementing. +//! +//! Choose the destination address increment from one of \b UDMA_DST_INC_8, +//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or +//! to select non-incrementing. +//! +//! The arbitration size determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size +//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, +//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 +//! items, in powers of 2. +//! +//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only +//! respond to burst requests at the tail end of a scatter-gather transfer. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelControlSet(unsigned long ulChannel, unsigned long ulControl) +{ + tDMAControlTable *pCtl; + + // + // Check the arguments. + // + ASSERT(ulChannel < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // Get the base address of the control table. + // + pCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + pCtl[ulChannel].ulControl = ((pCtl[ulChannel].ulControl & + ~(UDMA_CHCTL_DSTINC_M | + UDMA_CHCTL_DSTSIZE_M | + UDMA_CHCTL_SRCINC_M | + UDMA_CHCTL_SRCSIZE_M | + UDMA_CHCTL_ARBSIZE_M | + UDMA_CHCTL_NXTUSEBURST)) | + ulControl); +} + +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel. +//! +//! \param ulChannel is the logical or of the uDMA channel number with either +//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulMode is the type of uDMA transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ulTransferSize is the number of data items to transfer. +//! +//! This function is used to set the parameters for a uDMA transfer. These are +//! typically parameters that are changed often. The function +//! uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \e ulChannel parameter is one of the choices documented in the +//! uDMAChannelEnable() function. It should be the logical OR of the channel +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether the +//! primary or alternate data structure is used. +//! +//! The \e ulMode parameter should be one of the following values: +//! +//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. +//! - \b UDMA_MODE_AUTO to perform a transfer that will always complete once +//! started even if request is removed. +//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the +//! primary and alternate control structures for the channel. This allows +//! use of ping-pong buffering for uDMA transfers. +//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather +//! transfer. +//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather +//! transfer. +//! +//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler will take care of this if the +//! pointers are pointing to storage of the appropriate data type. +//! +//! The \e ulTransferSize parameter is the number of data items, not the number +//! of bytes. +//! +//! The two scatter/gather modes, memory and peripheral, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function will look for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and will set the +//! scatter/gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using uDMAChannelEnable() after calling +//! this function. The transfer will not begin until the channel has been set +//! up and enabled. Note that the channel is automatically disabled after the +//! transfer is completed, meaning that uDMAChannelEnable() must be called +//! again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results will be unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The uDMAChannelModeGet() function will return \b UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode, + void *pvSrcAddr, void *pvDstAddr, + unsigned long ulTransferSize) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + unsigned long ulSize; + unsigned long ulInc; + + // + // Check the arguments. + // + ASSERT(ulChannel < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((unsigned long)pvSrcAddr >= 0x20000000); + ASSERT((unsigned long)pvDstAddr >= 0x20000000); + ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ulControl = (pControlTable[ulChannel].ulControl & + ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ulChannel & UDMA_ALT_SELECT) + { + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulMode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but dont write the + // control word yet as it could kick off a transfer). + // + ulControl |= ulMode | ((ulTransferSize - 1) << 4); + + // + // Get the data item size from the control word (set previously). + // + ulSize = (ulControl & UDMA_CHCTL_DSTSIZE_M) >> 28; + + // + // Convert the transfer size to be in units of bytes. Shift (multiply) to + // get the value in bytes, based on the data item size. + // + ulTransferSize = ulTransferSize << ulSize; + + // + // Get the address increment value for the source, from the control word. + // + ulInc = (ulControl & UDMA_CHCTL_SRCINC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ulInc != UDMA_SRC_INC_NONE) + { + pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulTransferSize - 1); + } + + // + // Load the source ending address into the control block. + // + pControlTable[ulChannel].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ulInc = (ulControl & UDMA_CHCTL_DSTINC_M); + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ulInc != UDMA_DST_INC_NONE) + { + pvDstAddr = (void *)((unsigned long)pvDstAddr + ulTransferSize - 1); + } + + // + // Load the destination ending address into the control block. + // + pControlTable[ulChannel].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + pControlTable[ulChannel].ulControl = ulControl; +} + +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel. +//! +//! \param ulChannel is the logical or of the uDMA channel number with either +//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items will be returned. If the transfer is +//! complete, then 0 will be returned. +//! +//! The \e ulChannel parameter is one of the choices documented in the +//! uDMAChannelEnable() function. It should be the logical OR of the channel +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether +//! the primary or alternate data structure is used. +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +unsigned long +uDMAChannelSizeGet(unsigned long ulChannel) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT(ulChannel < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off all but the size field. + // + ulControl = pControlTable[ulChannel].ulControl & UDMA_CHCTL_XFERSIZE_M; + + // + // Shift the size field and add one, then return to user. + // + return((ulControl >> 4) + 1); +} + +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel. +//! +//! \param ulChannel is the logical or of the uDMA channel number with either +//! \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the transfer mode for the uDMA channel. It +//! can be used to query the status of a transfer on a channel. When the +//! transfer is complete the mode will be \b UDMA_MODE_STOP. +//! +//! The \e ulChannel parameter is one of the choices documented in the +//! uDMAChannelEnable() function. It should be the logical OR of the channel +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to choose whether the +//! primary or alternate data structure is used. +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which will be one of the following values: \b UDMA_MODE_STOP, +//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. +// +//***************************************************************************** +unsigned long +uDMAChannelModeGet(unsigned long ulChannel) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT(ulChannel < 64); + ASSERT(HWREG(UDMA_CTLBASE) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); + + // + // Get the current control word value and mask off all but the mode field. + // + ulControl = pControlTable[ulChannel].ulControl & UDMA_CHCTL_XFERMODE_M; + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulControl &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ulControl); +} + +//***************************************************************************** +// +//! Select the secondary peripheral for a set of uDMA channels. +//! +//! \param ulSecPeriphs is the logical or of the uDMA channels for which to +//! use the secondary peripheral, instead of the default peripheral. +//! +//! This function is used to select the secondary peripheral assignment for +//! a set of uDMA channels. By selecting the secondary peripheral assignment +//! for a channel, the default peripheral assignment is no longer available +//! for that channel. +//! +//! The parameter \e ulSecPeriphs can be the logical OR of any of the +//! following macros. If one of the macros below is in the list passed +//! to this function, then the secondary peripheral (marked as \b _SEC_) +//! will be selected. +//! +//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX +//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX +//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A +//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B +//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A +//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B +//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A +//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B +//! - \b UDMA_DEF_UART0RX_SEC_UART1RX +//! - \b UDMA_DEF_UART0TX_SEC_UART1TX +//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX +//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX +//! - \b UDMA_DEF_RESERVED_SEC_UART2RX +//! - \b UDMA_DEF_RESERVED_SEC_UART2TX +//! - \b UDMA_DEF_ADC00_SEC_TMR2A +//! - \b UDMA_DEF_ADC01_SEC_TMR2B +//! - \b UDMA_DEF_ADC02_SEC_RESERVED +//! - \b UDMA_DEF_ADC03_SEC_RESERVED +//! - \b UDMA_DEF_TMR0A_SEC_TMR1A +//! - \b UDMA_DEF_TMR0B_SEC_TMR1B +//! - \b UDMA_DEF_TMR1A_SEC_GPIORX +//! - \b UDMA_DEF_TMR1B_SEC_GPIOTX +//! - \b UDMA_DEF_UART1RX_SEC_RESERVED +//! - \b UDMA_DEF_UART1TX_SEC_RESERVED +//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 +//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 +//! - \b UDMA_DEF_RESERVED_SEC_ADC12 +//! - \b UDMA_DEF_RESERVED_SEC_ADC13 +//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED +//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelSelectSecondary(unsigned long ulSecPeriphs) +{ + // + // Select the secondary peripheral for the specified channels. + // + HWREG(UDMA_CHALT) |= ulSecPeriphs; +} + +//***************************************************************************** +// +//! Select the default peripheral for a set of uDMA channels. +//! +//! \param ulDefPeriphs is the logical or of the uDMA channels for which to +//! use the default peripheral, instead of the secondary peripheral. +//! +//! This function is used to select the default peripheral assignment for +//! a set of uDMA channels. +//! +//! The parameter \e ulDefPeriphs can be the logical OR of any of the +//! following macros. If one of the macros below is in the list passed +//! to this function, then the default peripheral (marked as \b _DEF_) +//! will be selected. +//! +//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX +//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX +//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A +//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B +//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A +//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B +//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A +//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B +//! - \b UDMA_DEF_UART0RX_SEC_UART1RX +//! - \b UDMA_DEF_UART0TX_SEC_UART1TX +//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX +//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX +//! - \b UDMA_DEF_RESERVED_SEC_UART2RX +//! - \b UDMA_DEF_RESERVED_SEC_UART2TX +//! - \b UDMA_DEF_ADC00_SEC_TMR2A +//! - \b UDMA_DEF_ADC01_SEC_TMR2B +//! - \b UDMA_DEF_ADC02_SEC_RESERVED +//! - \b UDMA_DEF_ADC03_SEC_RESERVED +//! - \b UDMA_DEF_TMR0A_SEC_TMR1A +//! - \b UDMA_DEF_TMR0B_SEC_TMR1B +//! - \b UDMA_DEF_TMR1A_SEC_GPIORX +//! - \b UDMA_DEF_TMR1B_SEC_GPIOTX +//! - \b UDMA_DEF_UART1RX_SEC_RESERVED +//! - \b UDMA_DEF_UART1TX_SEC_RESERVED +//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 +//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 +//! - \b UDMA_DEF_RESERVED_SEC_ADC12 +//! - \b UDMA_DEF_RESERVED_SEC_ADC13 +//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED +//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelSelectDefault(unsigned long ulDefPeriphs) +{ + // + // Select the default peripheral for the specified channels. + // + HWREG(UDMA_CHALT) &= ~ulDefPeriphs; +} + +//***************************************************************************** +// +//! Gets the uDMA controller channel interrupt status. +//! +//! This function is used to get the interrupt status of the uDMA controller. +//! The returned value is a 32-bit bit mask that indicates which channels are +//! requesting an interrupt. This function can be used from within an +//! interrupt handler to determine or confirm which uDMA channel has requested +//! an interrupt. +//! +//! \return Returns a 32-bit mask which indicates requesting uDMA channels. +//! There is a bit for each channel, and a 1 in a bit indicates that channel +//! is requesting an interrupt. Multiple bits can be set. +// +//***************************************************************************** +unsigned long +uDMAIntStatus(void) +{ + return(HWREG(UDMA_CHIS)); +} + +//***************************************************************************** +// +//! Clears uDMA interrupt status. +//! +//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! Clears bits in the uDMA interrupt status register according to which bits +//! are set in \e ulChanMask. There is one bit for each channel. If a a bit +//! is set in \e ulChanMask, then that corresponding channel's interrupt +//! status will be cleared (if it was set). +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntClear(unsigned long ulChanMask) +{ + HWREG(UDMA_CHIS) = ulChanMask; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt is to be registered. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This sets and enables the handler to be called when the uDMA controller +//! generates an interrupt. The \e ulIntChannel parameter should be one of the +//! following: +//! +//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts +//! from the uDMA software channel (UDMA_CHANNEL_SW) +//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error +//! interrupts +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The interrupt handler for uDMA is for transfer completion when the +//! channel UDMA_CHANNEL_SW is used, and for error interrupts. The +//! interrupts for each peripheral channel are handled through the individual +//! peripheral interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR)); + + // + // Register the interrupt handler. + // + IntRegister(ulIntChannel, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(ulIntChannel); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt to unregister. +//! +//! This function will disable and clear the handler to be called for the +//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of +//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function +//! uDMAIntRegister(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntUnregister(unsigned long ulIntChannel) +{ + // + // Disable the interrupt. + // + IntDisable(ulIntChannel); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulIntChannel); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/udma.h b/bsp/lm3s/driverlib/udma.h new file mode 100644 index 0000000000..d175947ee4 --- /dev/null +++ b/bsp/lm3s/driverlib/udma.h @@ -0,0 +1,338 @@ +//***************************************************************************** +// +// udma.h - Prototypes and macros for the uDMA controller. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// A structure that defines an entry in the channel control table. These +// fields are used by the uDMA controller and normally it is not necessary for +// software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + // + // The ending source address of the data transfer. + // + volatile void *pvSrcEndAddr; + + // + // The ending destination address of the data transfer. + // + volatile void *pvDstEndAddr; + + // + // The channel control mode. + // + volatile unsigned long ulControl; + + // + // An unused location. + // + volatile unsigned long ulSpare; +} +tDMAControlTable; + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAModeSet() and returned +// uDMAModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xc0000000 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHANNEL_USBEP1RX 0 +#define UDMA_CHANNEL_USBEP1TX 1 +#define UDMA_CHANNEL_USBEP2RX 2 +#define UDMA_CHANNEL_USBEP2TX 3 +#define UDMA_CHANNEL_USBEP3RX 4 +#define UDMA_CHANNEL_USBEP3TX 5 +#define UDMA_CHANNEL_ETH0RX 6 +#define UDMA_CHANNEL_ETH0TX 7 +#define UDMA_CHANNEL_UART0RX 8 +#define UDMA_CHANNEL_UART0TX 9 +#define UDMA_CHANNEL_SSI0RX 10 +#define UDMA_CHANNEL_SSI0TX 11 +#define UDMA_CHANNEL_ADC0 14 +#define UDMA_CHANNEL_ADC1 15 +#define UDMA_CHANNEL_ADC2 16 +#define UDMA_CHANNEL_ADC3 17 +#define UDMA_CHANNEL_TMR0A 18 +#define UDMA_CHANNEL_TMR0B 19 +#define UDMA_CHANNEL_TMR1A 20 +#define UDMA_CHANNEL_TMR1B 21 +#define UDMA_CHANNEL_UART1RX 22 +#define UDMA_CHANNEL_UART1TX 23 +#define UDMA_CHANNEL_SSI1RX 24 +#define UDMA_CHANNEL_SSI1TX 25 +#define UDMA_CHANNEL_I2S0RX 28 +#define UDMA_CHANNEL_I2S0TX 29 +#define UDMA_CHANNEL_SW 30 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// uDMA interrupt sources, to be passed to uDMAIntRegister() and +// uDMAIntUnregister(). +// +//***************************************************************************** +#define UDMA_INT_SW 62 +#define UDMA_INT_ERR 63 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. These are for secondary peripheral assignments. +// +//***************************************************************************** +#define UDMA_SEC_CHANNEL_UART2RX_0 \ + 0 +#define UDMA_SEC_CHANNEL_UART2TX_1 \ + 1 +#define UDMA_SEC_CHANNEL_TMR3A 2 +#define UDMA_SEC_CHANNEL_TMR3B 3 +#define UDMA_SEC_CHANNEL_TMR2A_4 \ + 4 +#define UDMA_SEC_CHANNEL_TMR2B_5 \ + 5 +#define UDMA_SEC_CHANNEL_TMR2A_6 \ + 6 +#define UDMA_SEC_CHANNEL_TMR2B_7 \ + 7 +#define UDMA_SEC_CHANNEL_UART1RX \ + 8 +#define UDMA_SEC_CHANNEL_UART1TX \ + 9 +#define UDMA_SEC_CHANNEL_SSI1RX 10 +#define UDMA_SEC_CHANNEL_SSI1TX 11 +#define UDMA_SEC_CHANNEL_UART2RX_12 \ + 12 +#define UDMA_SEC_CHANNEL_UART2TX_13 \ + 13 +#define UDMA_SEC_CHANNEL_TMR2A_14 \ + 14 +#define UDMA_SEC_CHANNEL_TMR2B_15 \ + 15 +#define UDMA_SEC_CHANNEL_TMR1A 18 +#define UDMA_SEC_CHANNEL_TMR1B 19 +#define UDMA_SEC_CHANNEL_EPI0RX 20 +#define UDMA_SEC_CHANNEL_EPI0TX 21 +#define UDMA_SEC_CHANNEL_ADC10 24 +#define UDMA_SEC_CHANNEL_ADC11 25 +#define UDMA_SEC_CHANNEL_ADC12 26 +#define UDMA_SEC_CHANNEL_ADC13 27 +#define UDMA_SEC_CHANNEL_SW 30 + +//***************************************************************************** +// +// uDMA default/secondary peripheral selections, to be passed to +// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). +// +//***************************************************************************** +#define UDMA_DEF_USBEP1RX_SEC_UART2RX \ + 0x00000001 +#define UDMA_DEF_USBEP1TX_SEC_UART2TX \ + 0x00000002 +#define UDMA_DEF_USBEP2RX_SEC_TMR3A \ + 0x00000004 +#define UDMA_DEF_USBEP2TX_SEC_TMR3B \ + 0x00000008 +#define UDMA_DEF_USBEP3RX_SEC_TMR2A \ + 0x00000010 +#define UDMA_DEF_USBEP3TX_SEC_TMR2B \ + 0x00000020 +#define UDMA_DEF_ETH0RX_SEC_TMR2A \ + 0x00000040 +#define UDMA_DEF_ETH0TX_SEC_TMR2B \ + 0x00000080 +#define UDMA_DEF_UART0RX_SEC_UART1RX \ + 0x00000100 +#define UDMA_DEF_UART0TX_SEC_UART1TX \ + 0x00000200 +#define UDMA_DEF_SSI0RX_SEC_SSI1RX \ + 0x00000400 +#define UDMA_DEF_SSI0TX_SEC_SSI1TX \ + 0x00000800 +#define UDMA_DEF_RESERVED_SEC_UART2RX \ + 0x00001000 +#define UDMA_DEF_RESERVED_SEC_UART2TX \ + 0x00002000 +#define UDMA_DEF_ADC00_SEC_TMR2A \ + 0x00004000 +#define UDMA_DEF_ADC01_SEC_TMR2B \ + 0x00008000 +#define UDMA_DEF_ADC02_SEC_RESERVED \ + 0x00010000 +#define UDMA_DEF_ADC03_SEC_RESERVED \ + 0x00020000 +#define UDMA_DEF_TMR0A_SEC_TMR1A \ + 0x00040000 +#define UDMA_DEF_TMR0B_SEC_TMR1B \ + 0x00080000 +#define UDMA_DEF_TMR1A_SEC_EPI0RX \ + 0x00100000 +#define UDMA_DEF_TMR1B_SEC_EPI0TX \ + 0x00200000 +#define UDMA_DEF_UART1RX_SEC_RESERVED \ + 0x00400000 +#define UDMA_DEF_UART1TX_SEC_RESERVED \ + 0x00800000 +#define UDMA_DEF_SSI1RX_SEC_ADC10 \ + 0x01000000 +#define UDMA_DEF_SSI1TX_SEC_ADC11 \ + 0x02000000 +#define UDMA_DEF_RESERVED_SEC_ADC12 \ + 0x04000000 +#define UDMA_DEF_RESERVED_SEC_ADC13 \ + 0x08000000 +#define UDMA_DEF_I2S0RX_SEC_RESERVED \ + 0x10000000 +#define UDMA_DEF_I2S0TX_SEC_RESERVED \ + 0x20000000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void uDMAEnable(void); +extern void uDMADisable(void); +extern unsigned long uDMAErrorStatusGet(void); +extern void uDMAErrorStatusClear(void); +extern void uDMAChannelEnable(unsigned long ulChannel); +extern void uDMAChannelDisable(unsigned long ulChannel); +extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannel); +extern void uDMAControlBaseSet(void *pControlTable); +extern void *uDMAControlBaseGet(void); +extern void uDMAChannelRequest(unsigned long ulChannel); +extern void uDMAChannelAttributeEnable(unsigned long ulChannel, + unsigned long ulAttr); +extern void uDMAChannelAttributeDisable(unsigned long ulChannel, + unsigned long ulAttr); +extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannel); +extern void uDMAChannelControlSet(unsigned long ulChannel, + unsigned long ulControl); +extern void uDMAChannelTransferSet(unsigned long ulChannel, + unsigned long ulMode, void *pvSrcAddr, + void *pvDstAddr, + unsigned long ulTransferSize); +extern unsigned long uDMAChannelSizeGet(unsigned long ulChannel); +extern unsigned long uDMAChannelModeGet(unsigned long ulChannel); +extern void uDMAIntRegister(unsigned long ulIntChannel, + void (*pfnHandler)(void)); +extern void uDMAIntUnregister(unsigned long ulIntChannel); +extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs); +extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs); +extern unsigned long uDMAIntStatus(void); +extern void uDMAIntClear(unsigned long ulChanMask); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ diff --git a/bsp/lm3s/driverlib/usb.c b/bsp/lm3s/driverlib/usb.c new file mode 100644 index 0000000000..b59be5115f --- /dev/null +++ b/bsp/lm3s/driverlib/usb.c @@ -0,0 +1,3434 @@ +//***************************************************************************** +// +// usb.c - Driver for the USB Interface. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usb_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/udma.h" +#include "driverlib/usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INT_RX_SHIFT 8 + +//***************************************************************************** +// +// Amount to shift the status interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INT_STATUS_SHIFT 24 + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16 + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ulBase specifies the USB module base address. +// \param ulEndpoint is the endpoint index to target for this write. +// \param ulIndexedReg is the indexed register to write to. +// \param ucValue is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulIndexedReg, unsigned long ulValue, + unsigned long ulSize) +{ + unsigned long ulIndex; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) || + (ulEndpoint == 3)); + ASSERT((ulSize == 1) || (ulSize == 2)); + + // + // Save the old index in case it was in use. + // + ulIndex = HWREGB(ulBase + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint; + + // + // Determine the size of the register value. + // + if(ulSize == 1) + { + // + // Set the value. + // + HWREGB(ulBase + ulIndexedReg) = ulValue; + } + else + { + // + // Set the value. + // + HWREGH(ulBase + ulIndexedReg) = ulValue; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ulBase + USB_O_EPIDX) = ulIndex; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ulBase specifies the USB module base address. +// \param ulEndpoint is the endpoint index to target for this write. +// \param ulIndexedReg is the indexed register to write to. +// +// This function is used interally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static unsigned long +USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulIndexedReg, unsigned long ulSize) +{ + unsigned char ulIndex; + unsigned char ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) || + (ulEndpoint == 3)); + ASSERT((ulSize == 1) || (ulSize == 2)); + + // + // Save the old index in case it was in use. + // + ulIndex = HWREGB(ulBase + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint; + + // + // Determine the size of the register value. + // + if(ulSize == 1) + { + // + // Get the value. + // + ulValue = HWREGB(ulBase + ulIndexedReg); + } + else + { + // + // Get the value. + // + ulValue = HWREGH(ulBase + ulIndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ulBase + USB_O_EPIDX) = ulIndex; + + // + // Return the register's value. + // + return(ulValue); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ulBase specifies the USB module base address. +//! +//! When used in host mode, this function will put the USB bus in the suspended +//! state. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ulBase specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function will cause the start of a reset condition on the USB bus. +//! The caller should then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(unsigned long ulBase, tBoolean bStart) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ulBase specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode this function will bring the USB controller out of the +//! suspend state. This call should first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application should +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode this function will signal devices to leave the suspend +//! state. This call should first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application should then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This will cause the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(unsigned long ulBase, tBoolean bStart) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function will return the current speed of the USB bus. +//! +//! \note This function should only be called in host mode. +//! +//! \return Returns either \b USB_LOW_SPEED, \b USB_FULL_SPEED, or +//! \b USB_UNDEF_SPEED. +// +//***************************************************************************** +unsigned long +USBHostSpeedGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Returns the status of the USB interrupts. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function will read the source of the interrupt for the USB controller. +//! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints, +//! and general status changes. This call will return the current status for +//! all of these interrupts. The bit values returned should be compared +//! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0, +//! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values. +//! +//! \note This call will clear the source of all of the general status +//! interrupts. +//! +//! \return Returns the status of the sources for the USB controller's +//! interrupt. +// +//***************************************************************************** +unsigned long +USBIntStatus(unsigned long ulBase) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Get the transmit interrupt status. + // + ulStatus = (HWREGH(ulBase + USB_O_TXIS)); + + // + // Get the receive interrupt status, these bits go into the second byte of + // the returned value. + // + ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ulStatus |= (HWREGB(ulBase + USB_O_IS) << USB_INT_STATUS_SHIFT); + + // + // Add the power fault status. + // + if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ulStatus |= USB_INT_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate a id detection was detected. + // + ulStatus |= USB_INT_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Disables the sources for USB interrupts. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which interrupts to disable. +//! +//! This function will disable the USB controller from generating the +//! interrupts indicated by the \e ulFlags parameter. There are three groups +//! of interrupt sources, IN Endpoints, OUT Endpoints, and general status +//! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT, +//! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS. If +//! \b USB_INT_ALL is specified then all interrupts will be disabled. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_INT_ALL)) == 0); + + // + // If any transmit interrupts were disabled then write the transmit + // interrupt settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) + { + HWREGH(ulBase + USB_O_TXIE) &= + ~(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)); + } + + // + // If any receive interrupts were disabled then write the receive interrupt + // settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) + { + HWREGH(ulBase + USB_O_RXIE) &= + ~((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >> + USB_INT_RX_SHIFT); + } + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ulFlags & USB_INT_STATUS) + { + HWREGB(ulBase + USB_O_IE) &= + ~((ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT); + } + + // + // Disable the power fault interrupt. + // + if(ulFlags & USB_INT_POWER_FAULT) + { + HWREG(ulBase + USB_O_EPCIM) = 0; + } + + // + // Disable the ID pin detect interrupt. + // + if(ulFlags & USB_INT_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = 0; + } +} + +//***************************************************************************** +// +//! Enables the sources for USB interrupts. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies which interrupts to enable. +//! +//! This function will enable the USB controller's ability to generate the +//! interrupts indicated by the \e ulFlags parameter. There are three +//! groups of interrupt sources, IN Endpoints, OUT Endpoints, and +//! general status changes, specified by \b USB_INT_HOST_IN, +//! \b USB_INT_HOST_OUT, \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and +//! \b USB_STATUS. If \b USB_INT_ALL is specified then all interrupts will be +//! enabled. +//! +//! \note A call must be made to enable the interrupt in the main interrupt +//! controller to receive interrupts. The USBIntRegister() API performs this +//! controller level interrupt enable. However if static interrupt handlers +//! are used then then a call to IntEnable() must be made in order to allow any +//! USB interrupts to occur. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & (~USB_INT_ALL)) == 0); + + // + // If any transmit interrupts were enabled then write the transmit + // interrupt settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0)) + { + HWREGH(ulBase + USB_O_TXIE) |= + ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0); + } + + // + // If any receive interrupts were enabled then write the receive interrupt + // settings out to the hardware. + // + if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) + { + HWREGH(ulBase + USB_O_RXIE) |= + ((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >> + USB_INT_RX_SHIFT); + } + + // + // If any general interrupts were enabled then write the general interrupt + // settings out to the hardware. + // + if(ulFlags & USB_INT_STATUS) + { + HWREGB(ulBase + USB_O_IE) |= + (ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT; + } + + // + // Enable the power fault interrupt. + // + if(ulFlags & USB_INT_POWER_FAULT) + { + HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ulFlags & USB_INT_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! \param pfnHandler is a pointer to the function to be called when a USB +//! interrupt occurs. +//! +//! This sets the handler to be called when a USB interrupt occurs. This will +//! also enable the global USB interrupt in the interrupt controller. The +//! specific desired USB interrupts must be enabled via a separate call to +//! USBIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt sources via a call to USBIntStatus(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_USB0, pfnHandler); + + // + // Enable the USB interrupt. + // + IntEnable(INT_USB0); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the USB controller. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function unregister the interrupt handler. This function will also +//! disable the USB interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering or +//! unregistering interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_USB0); + + // + // Disable the CAN interrupt. + // + IntDisable(INT_USB0); +} + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function will return the status of a given endpoint. If any of these +//! status bits need to be cleared, then these these values must be cleared by +//! calling the USBDevEndpointStatusClear() or USBHostEndpointStatusClear() +//! functions. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +unsigned long +USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulStatus; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the TX portion of the endpoint status. + // + ulStatus = HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ulStatus |= ((HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1)) << + USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ulStatus); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags are the status bits that will be cleared. +//! +//! This function will clear the status of any bits that are passed in the +//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned +//! from the USBEndpointStatus() call. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Clear the specified flags for the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + HWREGB(ulBase + USB_O_CSRL0) &= ~ulFlags; + } + else + { + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= ~ulFlags; + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(ulFlags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags are the status bits that will be cleared. +//! +//! This function will clear the status of any bits that are passed in the +//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned +//! from the USBEndpointStatus() call. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // If this is endpoint 0 then the bits have different meaning and map into + // the TX memory location. + // + if(ulEndpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ulFlags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ulFlags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ulFlags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ulBase + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN should be cleared. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(ulFlags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // should be cleared. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~((ulFlags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ulFlags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle will be set to the DATA0 state, and if it is \b true it will be +//! set to the DATA1 state. The \e ulFlags parameter can be \b USB_EP_HOST_IN +//! or \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ulFlags parameter is ignored for endpoint zero. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint, + tBoolean bDataToggle, unsigned long ulFlags) +{ + unsigned long ulDataToggle; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // The data toggle defaults to DATA0. + // + ulDataToggle = 0; + + // + // See if the data toggle should be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulDataToggle = USB_CSRH0_DT; + } + else if(ulFlags == USB_EP_HOST_IN) + { + ulDataToggle = USB_RXCSRH1_DT; + } + else + { + ulDataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ulBase + USB_O_CSRH0) = + ((HWREGB(ulBase + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ulDataToggle | USB_CSRH0_DTWE)); + } + else if(ulFlags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) = + ((HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ulDataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) = + ((HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ulDataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the Data toggle on an endpoint to zero. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies the endpoint to reset the data toggle. +//! \param ulFlags specifies whether to access the IN or OUT endpoint. +//! +//! This function will cause the controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ulFlags parameter should be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive data toggle should be cleared. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies the endpoint to stall. +//! \param ulFlags specifies whether to stall the IN or OUT endpoint. +//! +//! This function will cause to endpoint number passed in to go into a stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall +//! will be issued on the IN portion of this endpoint. If the \e ulFlags +//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT +//! portion of this endpoint. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0) + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Determine how to stall this endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ulBase + USB_O_CSRL0) |= + (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + } + else if(ulFlags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies which endpoint to remove the stall condition. +//! \param ulFlags specifies whether to remove the stall condition from the IN +//! or the OUT portion of this endpoint. +//! +//! This function will cause the endpoint number passed in to exit the stall +//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall +//! will be cleared on the IN portion of this endpoint. If the \e ulFlags +//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0) + + // + // Determine how to clear the stall on this endpoint. + // + if(ulEndpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ulFlags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function will cause the soft connect feature of the USB controller to +//! be enabled. Call USBDisconnect() to remove the USB device from the bus. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function will cause the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulAddress is the address to use for a device. +//! +//! This function will set the device address on the USB bus. This address was +//! likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ulBase + USB_O_FADDR) = (unsigned char)ulAddress; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function will return the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function should only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +unsigned long +USBDevAddrGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Return the function address. + // + return(HWREGB(ulBase + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulMaxPayload is the maximum payload for this endpoint. +//! \param ulNAKPollInterval is the either the NAK timeout limit or the polling +//! interval depending on the type of endpoint. +//! \param ulTargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ulFlags are used to configure other endpoint settings. +//! +//! This function will set the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ulFlags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ulFlags parameter determines whether this is an IN endpoint +//! (USB_EP_HOST_IN or USB_EP_DEV_IN) or an OUT endpoint (USB_EP_HOST_OUT or +//! USB_EP_DEV_OUT), whether this is a Full speed endpoint (USB_EP_SPEED_FULL) +//! or a Low speed endpoint (USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ulNAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints the polling interval is simply the number of +//! frames between polling an interrupt endpoint. For isochronous endpoints +//! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1) +//! frames. When used as a NAK timeout, the \e ulNAKPollInterval value +//! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out. +//! There are two special time out values that can be specified when setting +//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT which is the +//! maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT which indicates that there should be no limit on the +//! number of NAKs. +//! +//! The \b USB_EP_DMA_MODE_ flags enables the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ulMaxPayload have been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ulMaxPayload bytes. The \b USB_EP_AUTO_CLEAR +//! bit can be used to clear the data packet ready flag automatically once the +//! data has been read from the FIFO. If this is not used, this flag must be +//! manually cleared via a call to USBDevEndpointStatusClear() or +//! USBHostEndpointStatusClear(). +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulMaxPayload, + unsigned long ulNAKPollInterval, + unsigned long ulTargetEndpoint, unsigned long ulFlags) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + ASSERT(ulNAKPollInterval <= MAX_NAK_LIMIT); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ulEndpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ulBase + USB_O_NAKLMT) = ulNAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) = + ((ulFlags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ulRegister = ulTargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ulFlags & USB_EP_SPEED_FULL) + { + ulRegister |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ulRegister |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ulFlags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ulRegister |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ulRegister |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ulRegister |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ulRegister |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXTYPE1) = + ulRegister; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXINTERVAL1) = + ulNAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) = + ulMaxPayload; + + // + // Set the transmit control value to zero. + // + ulRegister = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ulFlags & USB_EP_AUTO_SET) + { + ulRegister |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) = + (unsigned char)ulRegister; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXTYPE1) = + ulRegister; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXINTERVAL1) = + ulNAKPollInterval; + + // + // Set the receive control value to zero. + // + ulRegister = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ulFlags & USB_EP_AUTO_CLEAR) + { + ulRegister |= USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA Mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) = + (unsigned char)ulRegister; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulMaxPacketSize is the maximum packet size for this endpoint. +//! \param ulFlags are used to configure other endpoint settings. +//! +//! This function will set the basic configuration for an endpoint in device +//! mode. Endpoint zero does not have a dynamic configuration, so this +//! function should not be called for endpoint zero. The \e ulFlags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determines the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ulMaxPacketSize more bytes of data. Also for +//! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data +//! packet ready flag automatically once the data has been read from the FIFO. +//! If this is not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear(). Both of these settings can be used to remove +//! the need for extra calls when using the controller in DMA mode. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulMaxPacketSize, unsigned long ulFlags) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ulFlags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) = + ulMaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ulRegister = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ulFlags & USB_EP_AUTO_SET) + { + ulRegister |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ulRegister |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) = + (unsigned char)ulRegister; + + // + // Reset the Data toggle to zero. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXMAXP1) = + ulMaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ulRegister = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ulFlags & USB_EP_AUTO_CLEAR) + { + ulRegister = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ulFlags & USB_EP_DMA_MODE_1) + { + ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ulFlags & USB_EP_DMA_MODE_0) + { + ulRegister |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if(USB_EP_MODE_ISOC & (ulFlags & USB_EP_MODE_MASK)) + { + ulRegister |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) = + (unsigned char)ulRegister; + + // + // Reset the Data toggle to zero. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pulMaxPacketSize is a pointer which will be written with the +//! maximum packet size for this endpoint. +//! \param pulFlags is a pointer which will be written with the current +//! endpoint settings. On entry to the function, this pointer must contain +//! either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or +//! OUT endpoint is to be queried. +//! +//! This function will return the basic configuration for an endpoint in device +//! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are +//! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to +//! USBDevEndpointConfig for this endpoint. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long *pulMaxPacketSize, + unsigned long *pulFlags) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT(pulMaxPacketSize && pulFlags); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pulFlags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pulFlags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pulMaxPacketSize = (unsigned long)HWREGB(ulBase + + EP_OFFSET(ulEndpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if(ulRegister & USB_TXCSRH1_AUTOSET) + { + *pulFlags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ulRegister & USB_TXCSRH1_DMAEN) + { + if(ulRegister & USB_TXCSRH1_DMAMOD) + { + *pulFlags |= USB_EP_DMA_MODE_1; + } + else + { + *pulFlags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ulRegister & USB_TXCSRH1_ISO) + { + *pulFlags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This ensures that anyone modifying + // the returned flags in preparation for a call to + // USBDevEndpointConfig will not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pulFlags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pulFlags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pulMaxPacketSize = (unsigned long)HWREGB(ulBase + + EP_OFFSET(ulEndpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if(ulRegister & USB_RXCSRH1_AUTOCL) + { + *pulFlags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ulRegister & USB_RXCSRH1_DMAEN) + { + if(ulRegister & USB_RXCSRH1_DMAMOD) + { + *pulFlags |= USB_EP_DMA_MODE_1; + } + else + { + *pulFlags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ulRegister & USB_RXCSRH1_ISO) + { + *pulFlags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This ensures that anyone modifying + // the returned flags in preparation for a call to + // USBDevEndpointConfig will not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pulFlags |= USB_EP_MODE_BULK; + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFIFOAddress is the starting address for the FIFO. +//! \param ulFIFOSize is the size of the FIFO in bytes. +//! \param ulFlags specifies what information to set in the FIFO configuration. +//! +//! This function will set the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO so this function should not be called for endpoint zero. +//! The \e ulFIFOSize parameter should be one of the values in the +//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering +//! it should use the values with the \b _DB at the end of the value. For +//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16 +//! byte double buffered FIFO. If a double buffered FIFO is used, then the +//! actual size of the FIFO will be twice the size indicated by the +//! \e ulFIFOSize parameter. This means that the \b USB_FIFO_SZ_16_DB value +//! will use 32 bytes of the USB controller's FIFO memory. +//! +//! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO should start 64 bytes into +//! the USB controller's FIFO memory. The \e ulFlags value specifies whether +//! the endpoint's OUT or IN FIFO should be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFIFOAddress, unsigned long ulFIFOSize, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOSZ, ulFIFOSize, 1); + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOADD, + ulFIFOAddress >> 3, 2); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOSZ, ulFIFOSize, 1); + USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOADD, + ulFIFOAddress >> 3, 2); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pulFIFOAddress is the starting address for the FIFO. +//! \param pulFIFOSize is the size of the FIFO in bytes. +//! \param ulFlags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function will return the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO so this function should not be called for endpoint zero. The +//! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should +//! be read. If in host mode, the \e ulFlags parameter should be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode the +//! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long *pulFIFOAddress, unsigned long *pulFIFOSize, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_TXFIFOADD, + 2)) << 3; + *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_TXFIFOSZ, 1); + + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_RXFIFOADD, + 2)) << 3; + *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4, + (unsigned long)USB_O_RXFIFOSZ, 1); + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags specifies which direction and what mode to use when enabling +//! DMA. +//! +//! This function will enable DMA on a given endpoint and set the mode according +//! to the values in the \e ulFlags parameter. The \e ulFlags parameter should +//! have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ulFlags & USB_EP_DEV_IN) + { + // + // Enable DMA on this end point. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + + // + // See if the receive DMA is being enabled. + // + if(ulFlags & USB_EP_DEV_OUT) + { + // + // Enable DMA on this end point. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags specifies which direction to disable. +//! +//! This function will disable DMA on a given end point to allow non-DMA +//! USB transactions to generate interrupts normally. The ulFlags should be +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // If this was a reques to disable DMA on the IN portion of the end point + // then handle it. + // + if(ulFlags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + + // + // If this was a request to disable DMA on the OUT portion of the end point + // then handle it. + // + if(ulFlags & USB_EP_DEV_OUT) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function will return the number of bytes of data currently available +//! in the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call will return the number of bytes available in a given +//! endpoint FIFO. +// +//***************************************************************************** +unsigned long +USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pucData is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pulSize is initially the size of the buffer passed into this call +//! via the \e pucData parameter. It will be set to the amount of data +//! returned in the buffer. +//! +//! This function will return the data from the FIFO for the given endpoint. +//! The \e pulSize parameter should indicate the size of the buffer passed in +//! the \e pulData parameter. The data in the \e pulSize parameter will be +//! changed to match the amount of data returned in the \e pucData parameter. +//! If a zero byte packet was received this call will not return a error but +//! will instead just return a zero in the \e pulSize parameter. The only +//! error case occurs when there is no data packet available. +//! +//! \return This call will return 0, or -1 if no packet was received. +// +//***************************************************************************** +long +USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long *pulSize) +{ + unsigned long ulRegister, ulByteCount, ulFIFO; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pulSize = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ulByteCount = HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint); + + // + // Determine how many bytes we will actually copy. + // + ulByteCount = (ulByteCount < *pulSize) ? ulByteCount : *pulSize; + + // + // Return the number of bytes we are going to read. + // + *pulSize = ulByteCount; + + // + // Calculate the FIFO address. + // + ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ulByteCount > 0; ulByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pucData++ = HWREGB(ulFIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this is the last packet. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function should only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint, + tBoolean bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Determine which endpoint is being acked. + // + if(ulEndpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ulBase + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Clear RxPktRdy. + // + if(ulEndpoint == USB_EP_0) + { + HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param pucData is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ulSize is the amount of data to put into the FIFO. +//! +//! This function will put the data from the \e pucData parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission then +//! this call will not put any of the data into the FIFO and will return -1. +//! Care should be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfig(). +//! +//! \return This call will return 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +long +USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long ulSize) +{ + unsigned long ulFIFO; + unsigned char ucTxPktRdy; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ucTxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ucTxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & ucTxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ulSize > 0; ulSize--) + { + HWREGB(ulFIFO) = *pucData++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulTransType is set to indicate what type of data is being sent. +//! +//! This function will start the transfer of data from the FIFO for a given +//! endpoint. This is necessary if the \b USB_EP_AUTO_SET bit was not enabled +//! for the endpoint. Setting the \e ulTransType parameter will allow the +//! appropriate signaling on the USB bus for the type of transaction being +//! requested. The \e ulTransType parameter should be one of the following: +//! +//! - USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - USB_TRANS_IN_LAST for the last IN transactions on endpoint zero in a +//! sequence of IN transactions. +//! - USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call will return 0 on success, or -1 if a transmission is +//! already in progress. +// +//***************************************************************************** +long +USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulTransType) +{ + unsigned long ulTxPktRdy; + + // + // CHeck the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ulEndpoint == USB_EP_0) + { + ulTxPktRdy = ulTransType & 0xff; + } + else + { + ulTxPktRdy = (ulTransType >> 8) & 0xff; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & USB_CSRL0_TXRDY) + { + return(-1); + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) = ulTxPktRdy; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags specifies if the IN or OUT endpoint should be accessed. +//! +//! This function will force the controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ulEndpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ulBase + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ulBase + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ulFlags & (USB_EP_HOST_IN | USB_EP_DEV_OUT)) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) & + USB_RXCSRL1_RXRDY) == 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + else + { + if((HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) & + USB_TXCSRL1_TXRDY) == 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! +//! This function will schedule a request for an IN transaction. When the USB +//! device being communicated with responds the data, the data can be retrieved +//! by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint) +{ + unsigned long ulRegister; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ulEndpoint == USB_EP_0) + { + ulRegister = USB_O_CSRL0; + } + else + { + ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ulBase + ulRegister) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function is used to cause a request for an status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! is used to complete the last phase of a control transaction to a device and +//! an interrupt will be signaled when the status packet has been received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ulBase + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulAddr is the functional address for the controller to use for this +//! endpoint. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function will set the functional address for a device that is using +//! this endpoint for communication. This \e ulAddr parameter is the address +//! of the target device that this endpoint will be used to communicate with. +//! The \e ulFlags parameter indicates if the IN or OUT endpoint should be set. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive address should be set. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)) = ulAddr; + } + else + { + // + // Set the receive address. + // + HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ulFlags parameter determines if +//! the IN or OUT endpoint's device address is returned. +//! +//! \note This function should only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +unsigned long +USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the transmit or receive address should be returned. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Set the hub address for the device that is connected to an endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulAddr is the hub address for the device using this endpoint. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function will set the hub address for a device that is using this +//! endpoint for communication. The \e ulFlags parameter determines if the +//! device address for the IN or the OUT endpoint is set by this call. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is being set. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address for this endpoint. + // + HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr; + } + else + { + // + // Set the hub receive address for this endpoint. + // + HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr; + } +} + +//***************************************************************************** +// +//! Get the current device hub address for this endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint is the endpoint to access. +//! \param ulFlags determines if this is an IN or an OUT endpoint. +//! +//! This function will return the current hub address that an endpoint is using +//! to communicate with a device. The \e ulFlags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function should only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +unsigned long +USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) || + (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) || + (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) || + (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) || + (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) || + (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) || + (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) || + (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address should be returned. + // + if(ulFlags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulFlags specifies the configuration of the power fault. +//! +//! This function will set the behavior of the USB controller during a power +//! fault and the behavior of the USBPEN pin. The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. One of the following can be selected as the power fault level +//! sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - Power fault is indicated by the pin being driven +//! low. +//! - \b USB_HOST_PWRFLT_HIGH - Power fault is indicated by the pin being +//! driven! high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_LOW - USBEPEN is driven low when power is enabled. +//! - \b USB_HOST_PWREN_HIGH - USBEPEN is driven high when power is enabled. +//! - \b USB_HOST_PWREN_VBLOW - USBEPEN is driven high when VBUS is low. +//! - \b USB_HOST_PWREN_VBHIGH - USBEPEN is driven high when VBUS is high. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulFlags & ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)) == 0); + + // + // Set the power fault configuration as specified. This will not change + // whether fault detection is enabled or not. + // + HWREGH(ulBase + USB_O_EPC) = + (ulFlags | (HWREGH(ulBase + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBPFLT pin is not in use this function should not be used. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ulBase + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function enables the USBEPEN signal to enable an external power supply +//! in host mode operation. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Enable the external power suppply enable signal. + // + HWREGH(ulBase + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function disables the USBEPEN signal to disable an external power +//! supply in host mode operation. +//! +//! \note This function should only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +unsigned long +USBFrameNumberGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ulBase + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ulBase specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! start a session and if it is \b false it will end a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ulBase + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ulBase + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This is +//! needed when the USB is going to be used with the uDMA controller and the +//! source or destination address needs to be set to the physical FIFO address +//! for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +unsigned long +USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint) +{ + // + // Return the FIFO address for this endpoint. + // + return(ulBase + USB_O_FIFO0 + (ulEndpoint >> 2)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function will return on of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If and OTG session request is started with no +//! cable in place this is the default mode for the controller. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function will return on of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +unsigned long +USBModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ulBase + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ulBase specifies the USB module base address. +//! \param ulEndpoint specifies which endpoint's FIFO address to return. +//! \param ulChannel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. This +//! allows the 3 receive and 3 transmit DMA channels to be mapped to any +//! endpoint other than 0. The values that should be passed into the \e +//! ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices will have no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulChannel) +{ + unsigned long ulMask; + + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) || + (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) || + (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) || + (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) || + (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) || + (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) || + (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) || + (ulEndpoint == USB_EP_15)); + ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX); + + // + // The input select mask needs to be shifted into the correct position + // based on the channel. + // + ulMask = 0xf << (ulChannel * 4); + + // + // Clear out the current selection for the channel. + // + ulMask = HWREG(ulBase + USB_O_EPS) & (~ulMask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ulMask |= (USB_EP_TO_INDEX(ulEndpoint)) << (ulChannel * 4); + + // + // Write the value out to the register. + // + HWREG(ulBase + USB_O_EPS) = ulMask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ulBase specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. This +//! is only valid on microcontrollers that have the host and device +//! capabilities and not the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == USB0_BASE); + + // + // Set the USB controller mode to host. + // + HWREGB(ulBase + USB_O_GPCS) &= ~(USB_GPCS_DEVMOD); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/usb.h b/bsp/lm3s/driverlib/usb.h new file mode 100644 index 0000000000..7cc8ec9924 --- /dev/null +++ b/bsp/lm3s/driverlib/usb.h @@ -0,0 +1,433 @@ +//***************************************************************************** +// +// usb.h - Prototypes for the USB Interface Driver. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __USB_H__ +#define __USB_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnable(), +// USBIntDisable(), and USBIntClear() as the ulIntFlags parameter, and which +// are returned from USBIntStatus(). +// +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0F // All Interrupt sources +#define USB_INT_STATUS 0xFF000000 // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error +#define USB_INT_SESSION_START 0x40000000 // Session Start Detected +#define USB_INT_SESSION_END 0x20000000 // Session End Detected +#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected +#define USB_INT_CONNECT 0x10000000 // Device Connect Detected +#define USB_INT_SOF 0x08000000 // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000 // Babble signaled +#define USB_INT_RESET 0x04000000 // Reset signaled +#define USB_INT_RESUME 0x02000000 // Resume detected +#define USB_INT_SUSPEND 0x01000000 // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfig() as the ulFlags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_HOST_EP0 0x00002000 // Host endpoint 0 +#define USB_EP_HOST_IN 0x00001000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_EP0 0x00002000 // Device endpoint 0 +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00001000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrFaultConfig() as +// the ulFlags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_LOW 0x00000000 +#define USB_HOST_PWREN_HIGH 0x00000001 +#define USB_HOST_PWREN_VBLOW 0x00000002 +#define USB_HOST_PWREN_VBHIGH 0x00000003 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ulNAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define USB_EP_8 0x00000080 // Endpoint 8 +#define USB_EP_9 0x00000090 // Endpoint 9 +#define USB_EP_10 0x000000A0 // Endpoint 10 +#define USB_EP_11 0x000000B0 // Endpoint 11 +#define USB_EP_12 0x000000C0 // Endpoint 12 +#define USB_EP_13 0x000000D0 // Endpoint 13 +#define USB_EP_14 0x000000E0 // Endpoint 14 +#define USB_EP_15 0x000000F0 // Endpoint 15 +#define NUM_USB_EP 16 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define INDEX_TO_USB_EP(x) ((x) << 4) +#define USB_EP_TO_INDEX(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ulFIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010 +#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \ + (((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ulTransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long USBDevAddrGet(unsigned long ulBase); +extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress); +extern void USBDevConnect(unsigned long ulBase); +extern void USBDevDisconnect(unsigned long ulBase); +extern void USBDevEndpointConfig(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulMaxPacketSize, + unsigned long ulFlags); +extern void USBDevEndpointConfigGet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long *pulMaxPacketSize, + unsigned long *pulFlags); +extern void USBDevEndpointDataAck(unsigned long ulBase, + unsigned long ulEndpoint, + tBoolean bIsLastPacket); +extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBDevEndpointStallClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBDevEndpointStatusClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBEndpointDataAvail(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBEndpointDMADisable(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long *pulSize); +extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint, + unsigned char *pucData, unsigned long ulSize); +extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulTransType); +extern void USBEndpointDataToggleClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBEndpointStatus(unsigned long ulBase, + unsigned long ulEndpoint); +extern unsigned long USBFIFOAddrGet(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long *pulFIFOAddress, + unsigned long *pulFIFOSize, + unsigned long ulFlags); +extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFIFOAddress, + unsigned long ulFIFOSize, unsigned long ulFlags); +extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBFrameNumberGet(unsigned long ulBase); +extern unsigned long USBHostAddrGet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags); +extern void USBHostEndpointConfig(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulMaxPacketSize, + unsigned long ulNAKPollInterval, + unsigned long ulTargetEndpoint, + unsigned long ulFlags); +extern void USBHostEndpointDataAck(unsigned long ulBase, + unsigned long ulEndpoint); +extern void USBHostEndpointDataToggle(unsigned long ulBase, + unsigned long ulEndpoint, + tBoolean bDataToggle, + unsigned long ulFlags); +extern void USBHostEndpointStatusClear(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern unsigned long USBHostHubAddrGet(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulFlags); +extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint, + unsigned long ulAddr, unsigned long ulFlags); +extern void USBHostPwrDisable(unsigned long ulBase); +extern void USBHostPwrEnable(unsigned long ulBase); +extern void USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags); +extern void USBHostPwrFaultDisable(unsigned long ulBase); +extern void USBHostPwrFaultEnable(unsigned long ulBase); +extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint); +extern void USBHostRequestStatus(unsigned long ulBase); +extern void USBHostReset(unsigned long ulBase, tBoolean bStart); +extern void USBHostResume(unsigned long ulBase, tBoolean bStart); +extern unsigned long USBHostSpeedGet(unsigned long ulBase); +extern void USBHostSuspend(unsigned long ulBase); +extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long USBIntStatus(unsigned long ulBase); +extern void USBIntUnregister(unsigned long ulBase); +extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart); +extern unsigned long USBModeGet(unsigned long ulBase); +extern void USBEndpointDMAChannel(unsigned long ulBase, + unsigned long ulEndpoint, + unsigned long ulChannel); +extern void USBHostMode(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __USB_H__ diff --git a/bsp/lm3s/driverlib/watchdog.c b/bsp/lm3s/driverlib/watchdog.c new file mode 100644 index 0000000000..fdfd5e821d --- /dev/null +++ b/bsp/lm3s/driverlib/watchdog.c @@ -0,0 +1,567 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_watchdog.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will check to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will enable the watchdog timer counter and interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogResetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; +} + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Disables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogResetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Disable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Locks out write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function sets the value to load into the watchdog timer when the count +//! reaches zero for the first time; if the watchdog timer is running when this +//! function is called, then the value will be immediately loaded into the +//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; the watchdog +//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function will clear the handler to be called when a watchdog timer +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG); +} + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the watchdog timer interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable the watchdog interrupt. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the watchdog timer module. Either +//! the raw interrupt status or the status of interrupt that is allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, where a 1 indicates that the +//! watchdog interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Since there is a write buffer in the Cortex-M3 processor, it may take +//! several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (since NVIC still sees the interrupt source +//! asserted). +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog will instead +//! expired after the appropriate number of processor cycles have been executed +//! while debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/bsp/lm3s/driverlib/watchdog.h b/bsp/lm3s/driverlib/watchdog.h new file mode 100644 index 0000000000..50fde76e67 --- /dev/null +++ b/bsp/lm3s/driverlib/watchdog.h @@ -0,0 +1,74 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/bsp/lm3s/inc/asmdefs.h b/bsp/lm3s/inc/asmdefs.h new file mode 100644 index 0000000000..aab1fc0c8f --- /dev/null +++ b/bsp/lm3s/inc/asmdefs.h @@ -0,0 +1,215 @@ +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/bsp/lm3s/inc/cr_project.xml b/bsp/lm3s/inc/cr_project.xml new file mode 100644 index 0000000000..0c13775b34 --- /dev/null +++ b/bsp/lm3s/inc/cr_project.xml @@ -0,0 +1,29 @@ + + + + + + diff --git a/bsp/lm3s/inc/hw_adc.h b/bsp/lm3s/inc/hw_adc.h new file mode 100644 index 0000000000..85e0c5ea54 --- /dev/null +++ b/bsp/lm3s/inc/hw_adc.h @@ -0,0 +1,1159 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt + // Status and Clear +#define ADC_O_CTL 0x00000038 // ADC Control +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation +#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital + // Comparator Select +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation +#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital + // Comparator Select +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation +#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital + // Comparator Select +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation +#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital + // Comparator Select +#define ADC_O_TMLB 0x00000100 // Test mode loopback register +#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset + // Initial Conditions +#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 +#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 +#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 +#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 +#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 +#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 +#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 +#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 +#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 +#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 +#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 +#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 +#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 +#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 +#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 +#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status. +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3. +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2. +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1. +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0. +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3. +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2. +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1. +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0. +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize. +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait. +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control. +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling + +//***************************************************************************** +// +// The following are defines for the the interpretation of the data in the +// SSFIFOx when the ADC TMLB is enabled. +// +//***************************************************************************** +#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter. +#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator. +#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator. +#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator. +#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator. +#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift +#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select. +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select. +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select. +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select. +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select. +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select. +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select. +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select. +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable. +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence. +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select. +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable. +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence. +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select. +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable. +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence. +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select. +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable. +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence. +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select. +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable. +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence. +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select. +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select. +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable. +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence. +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select. +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select. +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable. +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence. +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select. +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select. +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select. +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select. +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select. +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select. +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable. +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence. +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select. +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select. +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable. +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence. +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select. +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select. +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable. +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence. +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select. +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select. +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select. +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select. +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select. +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select. +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable. +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence. +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select. +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select. +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable. +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence. +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select. +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select. +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable. +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence. +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select. +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select. +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select. +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select. +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select. +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select. +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select. +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select. +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select. +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select. +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select. +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select. +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select. +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select. +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select. +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select. +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select. +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select. +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear. +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation. +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation. +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation. +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation. +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation. +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation. +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation. +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 7 Digital Comparator + // Operation. +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation. +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation. +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 7 Digital Comparator + // Operation. +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation. +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation. +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 7 Digital Comparator + // Operation. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7. +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6. +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5. +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4. +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3. +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2. +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1. +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0. +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7. +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6. +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5. +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4. +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3. +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2. +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1. +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL0_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL0_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL0_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL0_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL1_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL1_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL1_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL1_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL2_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL2_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL2_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL2_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL3_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL3_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL3_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL3_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL4_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL4_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL4_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL4_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL5_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL5_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL5_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL5_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL6_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL6_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL6_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL6_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable. +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition. +#define ADC_DCCTL7_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL7_CTC_MID 0x00000400 // COMP0 >= CV < COMP1 +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode. +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable. +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition. +#define ADC_DCCTL7_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1 +#define ADC_DCCTL7_CIC_MID 0x00000004 // COMP0 >= CV < COMP1 +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1 +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode. +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1. +#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0. +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the ADC sequence register offsets. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_EMUX +// register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSPRI +// register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSMUX0, +// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present +// in all registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSCTL0, +// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present +// in all registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSFIFO0, +// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0, +// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following are deprecated defines for the the interpretation of the data +// in the SSFIFOx when the ADC TMLB is enabled. +// +//***************************************************************************** +#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter. +#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator. +#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator. +#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator. +#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator. +#define ADC_TMLB_CNT_S 6 // Sample counter shift +#define ADC_TMLB_MUX_S 0 // Input channel number shift + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the loopback ADC +// data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif + +#endif // __HW_ADC_H__ diff --git a/bsp/lm3s/inc/hw_can.h b/bsp/lm3s/inc/hw_can.h new file mode 100644 index 0000000000..5d98a5a995 --- /dev/null +++ b/bsp/lm3s/inc/hw_can.h @@ -0,0 +1,756 @@ +//***************************************************************************** +// +// hw_can.h - Defines and macros used when accessing the can. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following are defines for the CAN register offsets. +// +//***************************************************************************** +#define CAN_O_CTL 0x00000000 // Control register +#define CAN_O_STS 0x00000004 // Status register +#define CAN_O_ERR 0x00000008 // Error register +#define CAN_O_BIT 0x0000000C // Bit Timing register +#define CAN_O_INT 0x00000010 // Interrupt register +#define CAN_O_TST 0x00000014 // Test register +#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register +#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. +#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. +#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register +#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register +#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. +#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. +#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. +#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register +#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register +#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register +#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register +#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. +#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. +#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register +#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register +#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. +#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. +#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. +#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register +#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register +#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register +#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register +#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register +#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register +#define CAN_O_NWDA1 0x00000120 // New Data 1 register +#define CAN_O_NWDA2 0x00000124 // New Data 2 register +#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending +#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending +#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid +#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test mode enable +#define CAN_CTL_CCE 0x00000040 // Configuration change enable +#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission +#define CAN_CTL_EIE 0x00000008 // Error interrupt enable +#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable +#define CAN_CTL_IE 0x00000002 // Module interrupt enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus Off status +#define CAN_STS_EWARN 0x00000040 // Error Warning status +#define CAN_STS_EPASS 0x00000020 // Error Passive status +#define CAN_STS_RXOK 0x00000010 // Received Message Successful +#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error +#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error +#define CAN_STS_LEC_ACK 0x00000003 // Ack error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error +#define CAN_STS_LEC_CRC 0x00000006 // CRC error +#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Receive error passive status +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter. +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter. +#define CAN_ERR_REC_S 8 // Receive error counter bit pos +#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point. +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample + // Point. +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width. +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar. +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier. +#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // CAN_RX pin status +#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin +#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX +#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX +#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX +#define CAN_TST_LBACK 0x00000010 // Loop back mode +#define CAN_TST_SILENT 0x00000008 // Silent mode +#define CAN_TST_BASIC 0x00000004 // Basic mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension. +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits. +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits. +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits. +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits. +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag. +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number. +#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; + // it is interpreted as 0x20, or + // object 32. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read. +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits. +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits. +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits. +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit. +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data. +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request. +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3. +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask. +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier. +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction. +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask. +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier. +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid. +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier. +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction. +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier. +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data. +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost. +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending. +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask. +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable. +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable. +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable. +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request. +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer. +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code. +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag. +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number. +#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; + // it is interpreted as 0x20, or + // object 32. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read. +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits. +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits. +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits. +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit. +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data. +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request. +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3. +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask. +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier. +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction. +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask. +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier. +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid. +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier. +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction. +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier. +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data. +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost. +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending. +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask. +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable. +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable. +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable. +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request. +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer. +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code. +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits. +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits. +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits. +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits. +#define CAN_MSG2VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the CAN register offsets. +// +//***************************************************************************** +#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. +#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. +#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. +#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the can +// registers. +// +//***************************************************************************** +#define CAN_RV_IF1MSK2 0x0000FFFF +#define CAN_RV_IF1MSK1 0x0000FFFF +#define CAN_RV_IF2MSK1 0x0000FFFF +#define CAN_RV_IF2MSK2 0x0000FFFF +#define CAN_RV_BIT 0x00002301 +#define CAN_RV_CTL 0x00000001 +#define CAN_RV_IF1CRQ 0x00000001 +#define CAN_RV_IF2CRQ 0x00000001 +#define CAN_RV_TXRQ2 0x00000000 +#define CAN_RV_IF2DB1 0x00000000 +#define CAN_RV_INT 0x00000000 +#define CAN_RV_IF1DB2 0x00000000 +#define CAN_RV_BRPE 0x00000000 +#define CAN_RV_IF2DA2 0x00000000 +#define CAN_RV_MSGVAL2 0x00000000 +#define CAN_RV_TXRQ1 0x00000000 +#define CAN_RV_IF1MCTL 0x00000000 +#define CAN_RV_IF1DB1 0x00000000 +#define CAN_RV_STS 0x00000000 +#define CAN_RV_MSGINT1 0x00000000 +#define CAN_RV_IF1DA2 0x00000000 +#define CAN_RV_TST 0x00000000 +#define CAN_RV_IF1ARB1 0x00000000 +#define CAN_RV_IF1ARB2 0x00000000 +#define CAN_RV_NWDA2 0x00000000 +#define CAN_RV_IF2CMSK 0x00000000 +#define CAN_RV_NWDA1 0x00000000 +#define CAN_RV_IF1DA1 0x00000000 +#define CAN_RV_IF2DA1 0x00000000 +#define CAN_RV_IF2MCTL 0x00000000 +#define CAN_RV_MSGVAL1 0x00000000 +#define CAN_RV_IF1CMSK 0x00000000 +#define CAN_RV_ERR 0x00000000 +#define CAN_RV_IF2ARB2 0x00000000 +#define CAN_RV_MSGINT2 0x00000000 +#define CAN_RV_IF2ARB1 0x00000000 +#define CAN_RV_IF2DB2 0x00000000 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_STS +// register. +// +//***************************************************************************** +#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_ERR +// register. +// +//***************************************************************************** +#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status +#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status +#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos +#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_BIT +// register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point +#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point +#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width +#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_INT +// register. +// +//***************************************************************************** +#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_TST +// register. +// +//***************************************************************************** +#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_BRPE +// register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1CRQ +// and CAN_IF1CRQ registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status +#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1CMSK +// and CAN_IF2CMSK registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read +#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit +#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) +#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) +#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 +#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1MSK1 +// and CAN_IF2MSK1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1MSK2 +// and CAN_IF2MSK2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier +#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction +#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1ARB1 +// and CAN_IF2ARB1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFARB1_ID 0x0000FFFF // Identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1ARB2 +// and CAN_IF2ARB2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid +#define CAN_IFARB2_XTD 0x00004000 // Extended identifier +#define CAN_IFARB2_DIR 0x00002000 // Message direction +#define CAN_IFARB2_ID 0x00001FFF // Message identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1MCTL +// and CAN_IF2MCTL registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data +#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost +#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending +#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask +#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable +#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable +#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable +#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request +#define CAN_IFMCTL_EOB 0x00000080 // End of buffer +#define CAN_IFMCTL_DLC 0x0000000F // Data length code + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DA1 +// and CAN_IF2DA1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DA2 +// and CAN_IF2DA2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DB1 +// and CAN_IF2DB1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DB2 +// and CAN_IF2DB2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_TXRQ1 +// register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_TXRQ2 +// register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_NWDA1 +// register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_NWDA2 +// register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGINT1 +// register. +// +//***************************************************************************** +#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGINT2 +// register. +// +//***************************************************************************** +#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGVAL1 +// register. +// +//***************************************************************************** +#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGVAL2 +// register. +// +//***************************************************************************** +#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits + +#endif + +#endif // __HW_CAN_H__ diff --git a/bsp/lm3s/inc/hw_comp.h b/bsp/lm3s/inc/hw_comp.h new file mode 100644 index 0000000000..ebc1f7ee81 --- /dev/null +++ b/bsp/lm3s/inc/hw_comp.h @@ -0,0 +1,277 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following are defines for the comparator register offsets. +// +//***************************************************************************** +#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked + // Interrupt Status +#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt + // Status +#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt + // Enable +#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference + // Voltage Control +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt + // Status. +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status. +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status. +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status. +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable. +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable. +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable. +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range. +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref. +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable. +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive. +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value. +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense. +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value. +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense. +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable. +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive. +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value. +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense. +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value. +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense. +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. +// +//***************************************************************************** +#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL2 register. +// +//***************************************************************************** +#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable. +#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive. +#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value +#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value. +#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense. +#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value. +#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense. +#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the comparator register offsets. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_MIS, +// COMP_RIS, and COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_REFCTL +// register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_ACSTAT0, +// COMP_ACSTAT1, and COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_ACCTL0, +// COMP_ACCTL1, and COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the comparator +// registers. +// +//***************************************************************************** +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. + +#endif + +#endif // __HW_COMP_H__ diff --git a/bsp/lm3s/inc/hw_epi.h b/bsp/lm3s/inc/hw_epi.h new file mode 100644 index 0000000000..cc275aa436 --- /dev/null +++ b/bsp/lm3s/inc/hw_epi.h @@ -0,0 +1,428 @@ +//***************************************************************************** +// +// hw_epi.h - Macros for use in accessing the EPI registers. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EPI_H__ +#define __HW_EPI_H__ + +//***************************************************************************** +// +// The following are defines for the External Peripheral Interface (EPI) +// +//***************************************************************************** +#define EPI_O_CFG 0x00000000 // EPI Configuration +#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate +#define EPI_O_GPCFG 0x00000010 // EPI General Purpose + // Configuration +#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Mode Configuration +#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Mode + // Configuration +#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 +#define EPI_O_SDRAMCFG2 0x00000014 // EPI SDRAM Configuration 2 +#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose + // Configuration 2 +#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map +#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 +#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 +#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 +#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 +#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 +#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 +#define EPI_O_STAT 0x00000060 // EPI Status +#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count +#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO +#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 +#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 +#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 +#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 +#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 +#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 +#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 +#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects +#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count +#define EPI_O_IM 0x00000210 // EPI Interrupt Mask +#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status +#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status +#define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_CFG register. +// +//***************************************************************************** +#define EPI_CFG_BLKEN 0x00000010 // Block Enable. +#define EPI_CFG_MODE_M 0x0000000F // Mode Select. +#define EPI_CFG_MODE_NONE 0x00000000 // None +#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM +#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_BAUD register. +// +//***************************************************************************** +#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter. +#define EPI_BAUD_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. +// +//***************************************************************************** +#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range. +#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 +#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 +#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 +#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50 +#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter. +#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode. +#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM. +#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64Mb (8MB) +#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128Mb (16MB) +#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256Mb (32MB) +#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512Mb (64MB) +#define EPI_SDRAMCFG_RFSH_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_GPCFG register. +// +//***************************************************************************** +#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin. +#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated. +#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable. +#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin. +#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame. +#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count. +#define EPI_GPCFG_RW 0x00200000 // Read and Write. +#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes. +#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads. +#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait. +#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size. +#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address +#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // 4 Bits Wide (EPI24 to EPI27) +#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // 12 Bits Wide (EPI16 to EPI27). + // Cannot be used with 24-bit data +#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // 20 Bits Wide +#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus. +#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 4 Bits Wide (EPI0 to EPI7) +#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0 to EPI15) +#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0 to EPI23) +#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide. May not be used + // with clock (EPI0 to EPI31). This + // value is normally used for + // acquisition input and actuator + // control as well as other general + // purpose uses. +#define EPI_GPCFG_FRMCNT_S 22 +#define EPI_GPCFG_MAXWAIT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG register. +// +//***************************************************************************** +#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable. +#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable. +#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity. +#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity. +#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait. +#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States. +#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states +#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state +#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states +#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states +#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States. +#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states +#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state +#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states +#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states +#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode. +#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] +#define EPI_HB8CFG_MODE_SRAM 0x00000002 // SRAM +#define EPI_HB8CFG_MODE_FIFO 0x00000003 // FIFO - D[7:0] +#define EPI_HB8CFG_MAXWAIT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_ADDRMAP register. +// +//***************************************************************************** +#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size. +#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 0x100 (256) +#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 0x10000 (64 KB) +#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 0x1000000 (16 MB) +#define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 0x20000000 (512 MB) +#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address. +#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA0000000 +#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC0000000 +#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size. +#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 0x100 (256) +#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 0x10000 (64KB) +#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 0x1000000 (16MB) +#define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 0x20000000 (512MB) +#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address. +#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x60000000 +#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x80000000 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RSIZE0 register. +// +//***************************************************************************** +#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size. +#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) +#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) +#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RADDR0 register. +// +//***************************************************************************** +#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address. +#define EPI_RADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RPSTD0 register. +// +//***************************************************************************** +#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count. +#define EPI_RPSTD0_POSTCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RSIZE1 register. +// +//***************************************************************************** +#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size. +#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) +#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) +#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RADDR1 register. +// +//***************************************************************************** +#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address. +#define EPI_RADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RPSTD1 register. +// +//***************************************************************************** +#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count. +#define EPI_RPSTD1_POSTCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. +// +//***************************************************************************** +#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count. +#define EPI_RFIFOCNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO register. +// +//***************************************************************************** +#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO1 +// register. +// +//***************************************************************************** +#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO2 +// register. +// +//***************************************************************************** +#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO3 +// register. +// +//***************************************************************************** +#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO4 +// register. +// +//***************************************************************************** +#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO4_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO5 +// register. +// +//***************************************************************************** +#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO5_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO6 +// register. +// +//***************************************************************************** +#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO6_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO7 +// register. +// +//***************************************************************************** +#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data. +#define EPI_READFIFO7_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_FIFOLVL register. +// +//***************************************************************************** +#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error. +#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error. +#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO. +#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Empty +#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // >= 1/4 full +#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // >= 1/2 full +#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // >= 3/4 full +#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO. +#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty +#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // <= 1/8 full +#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // <= 1/4 full +#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // <= 1/2 full +#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // <= 3/4 full +#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // <= 7/8 full +#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries + // in the NBRFIFO. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_IM register. +// +//***************************************************************************** +#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask. +#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask. +#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RIS register. +// +//***************************************************************************** +#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status. +#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status. +#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_MIS register. +// +//***************************************************************************** +#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status. +#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status. +#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_SDRAMCFG2 +// register. +// +//***************************************************************************** +#define EPI_SDRAMCFG2_RCM 0x80000000 // Read Capture Mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. +// +//***************************************************************************** +#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode. +#define EPI_HB8CFG2_CSCFG 0x01000000 // Chip Select Configuration. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_GPCFG2 register. +// +//***************************************************************************** +#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_STAT register. +// +//***************************************************************************** +#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low. +#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full. +#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty. +#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence. +#define EPI_STAT_WBUSY 0x00000020 // Write Busy. +#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy. +#define EPI_STAT_ACTIVE 0x00000001 // Register Active. + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. +// +//***************************************************************************** +#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions. +#define EPI_WFIFOCNT_WTAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_EISC register. +// +//***************************************************************************** +#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error. +#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error. +#define EPI_EISC_TOUT 0x00000001 // Timeout Error. + +#endif // __HW_EPI_H__ diff --git a/bsp/lm3s/inc/hw_ethernet.h b/bsp/lm3s/inc/hw_ethernet.h new file mode 100644 index 0000000000..312632e4d1 --- /dev/null +++ b/bsp/lm3s/inc/hw_ethernet.h @@ -0,0 +1,683 @@ +//***************************************************************************** +// +// hw_ethernet.h - Macros used when accessing the Ethernet hardware. +// +// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ETHERNET_H__ +#define __HW_ETHERNET_H__ + +//***************************************************************************** +// +// The following are defines for the MAC register offsets in the Ethernet +// Controller. +// +//***************************************************************************** +#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt + // Status +#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register +#define MAC_O_IM 0x00000004 // Interrupt Mask Register +#define MAC_O_RCTL 0x00000008 // Receive Control Register +#define MAC_O_TCTL 0x0000000C // Transmit Control Register +#define MAC_O_DATA 0x00000010 // Data Register +#define MAC_O_IA0 0x00000014 // Individual Address Register 0 +#define MAC_O_IA1 0x00000018 // Individual Address Register 1 +#define MAC_O_THR 0x0000001C // Threshold Register +#define MAC_O_MCTL 0x00000020 // Management Control Register +#define MAC_O_MDV 0x00000024 // Management Divider Register +#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg +#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg +#define MAC_O_NP 0x00000034 // Number of Packets Register +#define MAC_O_TR 0x00000038 // Transmission Request Register +#define MAC_O_TS 0x0000003C // Timer Support Register +#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding +#define MAC_O_MDIX 0x00000044 // MDIX Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IACK register. +// +//***************************************************************************** +#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt +#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete +#define MAC_IACK_RXER 0x00000010 // Clear RX Error +#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun +#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy +#define MAC_IACK_TXER 0x00000002 // Clear TX Error +#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IM register. +// +//***************************************************************************** +#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt +#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete +#define MAC_IM_RXERM 0x00000010 // Mask RX Error +#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun +#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy +#define MAC_IM_TXERM 0x00000002 // Mask TX Error +#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_RCTL register. +// +//***************************************************************************** +#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO +#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC +#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode +#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets +#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TCTL register. +// +//***************************************************************************** +#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode +#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation +#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding +#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IA0 register. +// +//***************************************************************************** +#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4. +#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3. +#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2. +#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1. +#define MAC_IA0_MACOCT4_S 24 +#define MAC_IA0_MACOCT3_S 16 +#define MAC_IA0_MACOCT2_S 8 +#define MAC_IA0_MACOCT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IA1 register. +// +//***************************************************************************** +#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6. +#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5. +#define MAC_IA1_MACOCT6_S 8 +#define MAC_IA1_MACOCT5_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TXTH register. +// +//***************************************************************************** +#define MAC_THR_THRESH_M 0x0000003F // Threshold Value. +#define MAC_THR_THRESH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MCTL register. +// +//***************************************************************************** +#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address. +#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write +#define MAC_MCTL_START 0x00000001 // Start MII Transaction +#define MAC_MCTL_REGADR_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MDV register. +// +//***************************************************************************** +#define MAC_MDV_DIV_M 0x000000FF // Clock Divider. +#define MAC_MDV_DIV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MTXD register. +// +//***************************************************************************** +#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data. +#define MAC_MTXD_MDTX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MRXD register. +// +//***************************************************************************** +#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data. +#define MAC_MRXD_MDRX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_NP register. +// +//***************************************************************************** +#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive + // FIFO. +#define MAC_NP_NPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TXRQ register. +// +//***************************************************************************** +#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TS register. +// +//***************************************************************************** +#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MDIX register. +// +//***************************************************************************** +#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable. + +//***************************************************************************** +// +// The following are defines for the Ethernet Controller PHY registers. +// +//***************************************************************************** +#define PHY_MR0 0x00000000 // Ethernet PHY Management Register + // 0 - Control +#define PHY_MR1 0x00000001 // Ethernet PHY Management Register + // 1 - Status +#define PHY_MR2 0x00000002 // Ethernet PHY Management Register + // 2 - PHY Identifier 1 +#define PHY_MR3 0x00000003 // Ethernet PHY Management Register + // 3 - PHY Identifier 2 +#define PHY_MR4 0x00000004 // Ethernet PHY Management Register + // 4 - Auto-Negotiation + // Advertisement +#define PHY_MR5 0x00000005 // Ethernet PHY Management Register + // 5 - Auto-Negotiation Link + // Partner Base Page Ability +#define PHY_MR6 0x00000006 // Ethernet PHY Management Register + // 6 - Auto-Negotiation Expansion +#define PHY_MR16 0x00000010 // Ethernet PHY Management Register + // 16 - Vendor-Specific +#define PHY_MR17 0x00000011 // Ethernet PHY Management Register + // 17 - Interrupt Control/Status +#define PHY_MR18 0x00000012 // Ethernet PHY Management Register + // 18 - Diagnostic +#define PHY_MR19 0x00000013 // Ethernet PHY Management Register + // 19 - Transceiver Control +#define PHY_MR23 0x00000017 // Ethernet PHY Management Register + // 23 - LED Configuration +#define PHY_MR24 0x00000018 // Ethernet PHY Management Register + // 24 -MDI/MDIX Control +#define PHY_MR27 0x0000001B // Ethernet PHY Management Register + // 27 -Special Control/Status +#define PHY_MR29 0x0000001D // Ethernet PHY Management Register + // 29 - Interrupt Status +#define PHY_MR30 0x0000001E // Ethernet PHY Management Register + // 30 - Interrupt Mask +#define PHY_MR31 0x0000001F // Ethernet PHY Management Register + // 31 - PHY Special Control/Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR0 register. +// +//***************************************************************************** +#define PHY_MR0_RESET 0x00008000 // Reset Registers. +#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode. +#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select. +#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable. +#define PHY_MR0_PWRDN 0x00000800 // Power Down. +#define PHY_MR0_ISO 0x00000400 // Isolate. +#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation. +#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode. +#define PHY_MR0_COLT 0x00000080 // Collision Test. + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_O_RIS register. +// +//***************************************************************************** +#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt. +#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete. +#define MAC_RIS_RXER 0x00000010 // Receive Error. +#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun. +#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty. +#define MAC_RIS_TXER 0x00000002 // Transmit Error. +#define MAC_RIS_RXINT 0x00000001 // Packet Received. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR1 register. +// +//***************************************************************************** +#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode. +#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode. +#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode. +#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode. +#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble + // Suppressed. +#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete. +#define PHY_MR1_RFAULT 0x00000010 // Remote Fault. +#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation. +#define PHY_MR1_LINK 0x00000004 // Link Made. +#define PHY_MR1_JAB 0x00000002 // Jabber Condition. +#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR2 register. +// +//***************************************************************************** +#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique + // Identifier[21:6]. +#define PHY_MR2_OUI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR3 register. +// +//***************************************************************************** +#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique + // Identifier[5:0]. +#define PHY_MR3_MN_M 0x000003F0 // Model Number. +#define PHY_MR3_RN_M 0x0000000F // Revision Number. +#define PHY_MR3_OUI_S 10 +#define PHY_MR3_MN_S 4 +#define PHY_MR3_RN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR4 register. +// +//***************************************************************************** +#define PHY_MR4_NP 0x00008000 // Next Page. +#define PHY_MR4_RF 0x00002000 // Remote Fault. +#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3]. +#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2]. +#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1]. +#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0]. +#define PHY_MR4_S_M 0x0000001F // Selector Field. +#define PHY_MR4_S_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR5 register. +// +//***************************************************************************** +#define PHY_MR5_NP 0x00008000 // Next Page. +#define PHY_MR5_ACK 0x00004000 // Acknowledge. +#define PHY_MR5_RF 0x00002000 // Remote Fault. +#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field. +#define PHY_MR5_S_M 0x0000001F // Selector Field. +#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3 +#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T +#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5 +#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394 +#define PHY_MR5_A_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR6 register. +// +//***************************************************************************** +#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault. +#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able. +#define PHY_MR6_PRX 0x00000002 // New Page Received. +#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation + // Able. + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_O_DATA register. +// +//***************************************************************************** +#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data. +#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data. +#define MAC_DATA_RXDATA_S 0 +#define MAC_DATA_TXDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR16 register. +// +//***************************************************************************** +#define PHY_MR16_RPTR 0x00008000 // Repeater Mode. +#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity. +#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode. +#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing. +#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode. +#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier. +#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable. +#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity. +#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass. +#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control. +#define PHY_MR16_SR_S 6 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR17 register. +// +//***************************************************************************** +#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable. +#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable. +#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable. +#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down. +#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable. +#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault + // Interrupt Enable. +#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable. +#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable. +#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt + // Enable. +#define PHY_MR17_MDPB 0x00000400 // Management Data Preamble Bypass. +#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable. +#define PHY_MR17_FLPBK 0x00000200 // Far Loopback Mode. +#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete + // Interrupt Enable. +#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode. +#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt. +#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt. +#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt. +#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault + // Interrupt. +#define PHY_MR17_REFCE 0x00000010 // Reference Clock Enable. +#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt. +#define PHY_MR17_PADBP 0x00000008 // PHY Address Bypass. +#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt. +#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status. +#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt. +#define PHY_MR17_ENON 0x00000002 // Energy On. +#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete + // Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR18 register. +// +//***************************************************************************** +#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure. +#define PHY_MR18_DPLX 0x00000800 // Duplex Mode. +#define PHY_MR18_RATE 0x00000400 // Rate. +#define PHY_MR18_RXSD 0x00000200 // Receive Detection. +#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR19 register. +// +//***************************************************************************** +#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection. +#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion + // loss +#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion + // loss +#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion + // loss +#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion + // loss + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR23 register. +// +//***************************************************************************** +#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source. +#define PHY_MR23_LED1_LINK 0x00000000 // Link OK +#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1) +#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode +#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode +#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex +#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX + // Activity +#define PHY_MR23_LED0_M 0x0000000F // LED0 Source. +#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0) +#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity +#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode +#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode +#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex +#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX + // Activity + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR24 register. +// +//***************************************************************************** +#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode. +#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable. +#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration. +#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete. +#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed. +#define PHY_MR24_MDIX_SD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR27 register. +// +//***************************************************************************** +#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR29 register. +// +//***************************************************************************** +#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt. +#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete + // Interrupt. +#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt. +#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt. +#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge. +#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault. +#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR30 register. +// +//***************************************************************************** +#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled. +#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete + // Interrupt Enabled. +#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled. +#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled. +#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge + // Enabled. +#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault + // Enabled. +#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received + // Enabled. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR31 register. +// +//***************************************************************************** +#define PHY_MR31_BPRMG 0x00008000 // Bypass Remove Glitch. +#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done. +#define PHY_MR31_EN4B5B 0x00000040 // Enable 4B5B Encoding/Decoding. +#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value. +#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable. +#define PHY_MR31_SPEED_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_O_LED register. +// +//***************************************************************************** +#define MAC_LED_LED1_M 0x000000F0 // LED1 Source. +#define MAC_LED_LED1_LINK 0x00000000 // Link OK +#define MAC_LED_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1) +#define MAC_LED_LED1_100 0x00000050 // 100BASE-TX mode +#define MAC_LED_LED1_10 0x00000060 // 10BASE-T mode +#define MAC_LED_LED1_DUPLEX 0x00000070 // Full-Duplex +#define MAC_LED_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX + // Activity +#define MAC_LED_LED0_M 0x0000000F // LED0 Source. +#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0) +#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity +#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode +#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode +#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex +#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX + // Activity + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the MAC register offsets in the +// Ethernet Controller. +// +//***************************************************************************** +#define MAC_O_IS 0x00000000 // Interrupt Status Register +#define MAC_O_MADD 0x00000028 // Management Address Register + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the MAC +// registers. +// +//***************************************************************************** +#define MAC_RV_MDV 0x00000080 +#define MAC_RV_IM 0x0000007F +#define MAC_RV_THR 0x0000003F +#define MAC_RV_RCTL 0x00000008 +#define MAC_RV_IA0 0x00000000 +#define MAC_RV_TCTL 0x00000000 +#define MAC_RV_DATA 0x00000000 +#define MAC_RV_MRXD 0x00000000 +#define MAC_RV_TR 0x00000000 +#define MAC_RV_IS 0x00000000 +#define MAC_RV_NP 0x00000000 +#define MAC_RV_MCTL 0x00000000 +#define MAC_RV_MTXD 0x00000000 +#define MAC_RV_IA1 0x00000000 +#define MAC_RV_IACK 0x00000000 +#define MAC_RV_MADD 0x00000000 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_IS +// register. +// +//***************************************************************************** +#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt +#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete +#define MAC_IS_RXER 0x00000010 // RX Error +#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun +#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy +#define MAC_IS_TXER 0x00000002 // TX Error +#define MAC_IS_RXINT 0x00000001 // RX Packet Available + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_IA0 +// register. +// +//***************************************************************************** +#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address +#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address +#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address +#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_IA1 +// register. +// +//***************************************************************************** +#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address +#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_TXTH +// register. +// +//***************************************************************************** +#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MCTL +// register. +// +//***************************************************************************** +#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MDV +// register. +// +//***************************************************************************** +#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MTXD +// register. +// +//***************************************************************************** +#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MRXD +// register. +// +//***************************************************************************** +#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_NP +// register. +// +//***************************************************************************** +#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PHY_MR23 +// register. +// +//***************************************************************************** +#define PHY_MR23_LED1_TX 0x00000020 // TX Activity +#define PHY_MR23_LED1_RX 0x00000030 // RX Activity +#define PHY_MR23_LED1_COL 0x00000040 // Collision +#define PHY_MR23_LED0_TX 0x00000002 // TX Activity +#define PHY_MR23_LED0_RX 0x00000003 // RX Activity +#define PHY_MR23_LED0_COL 0x00000004 // Collision + +#endif + +#endif // __HW_ETHERNET_H__ diff --git a/bsp/lm3s/inc/hw_flash.h b/bsp/lm3s/inc/hw_flash.h new file mode 100644 index 0000000000..b17b8ed539 --- /dev/null +++ b/bsp/lm3s/inc/hw_flash.h @@ -0,0 +1,328 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH register offsets. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2 +#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid +#define FLASH_FWBN 0x400FD100 // Flash Write Buffer Register n +#define FLASH_RMCTL 0x400FE0F0 // ROM Control +#define FLASH_RMVER 0x400FE0F4 // ROM Version Register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register +#define FLASH_USERDBG 0x400FE1D0 // User Debug +#define FLASH_USERREG0 0x400FE1E0 // User Register 0 +#define FLASH_USERREG1 0x400FE1E4 // User Register 1 +#define FLASH_USERREG2 0x400FE1E8 // User Register 2 +#define FLASH_USERREG3 0x400FE1EC // User Register 3 +#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 +#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 +#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 +#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 +#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 +#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 +#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 +#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word +#define FLASH_FMC_WRKEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Write. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt + // Status. +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask. +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear. +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE and +// FLASH_FMPPE registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value. +#define FLASH_USECRL_S 0 + +//***************************************************************************** +// +// The following are defines for the erase size of the FLASH block that is +// erased by an erase operation, and the protect size is the size of the FLASH +// block that is protected by each protection register. +// +//***************************************************************************** +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_ERASE_SIZE 0x00000400 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset. +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value. +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERDBG register. +// +//***************************************************************************** +#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written. +#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data. +#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1. +#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0. +#define FLASH_USERDBG_DATA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_NW 0x80000000 // Not Written. +#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_NW 0x80000000 // Not Written. +#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMVER register. +// +//***************************************************************************** +#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents. +#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader & + // DriverLib +#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader & + // DriverLib with AES +#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \ + 0x03000000 // Stellaris Boot Loader & + // DriverLib with AES and SAFERTOS +#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size. +#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size +#define FLASH_RMVER_SIZE_23_75K 0x00020000 // 23.75KB Size +#define FLASH_RMVER_SIZE_28_25K 0x00030000 // 28.25KB Size +#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version. +#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision. +#define FLASH_RMVER_VER_S 8 +#define FLASH_RMVER_REV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_NW 0x80000000 // Not Written. +#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_NW 0x80000000 // Not Written. +#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Write Buffer. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FMC +// register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FCRIS +// register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FCIM +// register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FMIS +// register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_USECRL +// register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +#endif + +#endif // __HW_FLASH_H__ diff --git a/bsp/lm3s/inc/hw_gpio.h b/bsp/lm3s/inc/hw_gpio.h new file mode 100644 index 0000000000..9a55d096b3 --- /dev/null +++ b/bsp/lm3s/inc/hw_gpio.h @@ -0,0 +1,593 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO Register offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Interrupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_LOCK 0x00000520 // Lock register. +#define GPIO_O_CR 0x00000524 // Commit register. +#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select +#define GPIO_O_PCTL 0x0000052C // GPIO Port Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock. +#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked +#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked +#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register +#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on + // DustDevil-class devices and + // later. + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port A. +// +//***************************************************************************** +#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask +#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 +#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0 +#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0 +#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask +#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 +#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1 +#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1 +#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask +#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2 +#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2 +#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2 +#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask +#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3 +#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3 +#define GPIO_PCTL_PA3_I2S0RXMCLK \ + 0x00009000 // I2S0RXMCLK on PA3 +#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask +#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4 +#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4 +#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4 +#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4 +#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask +#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5 +#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5 +#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5 +#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5 +#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask +#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6 +#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6 +#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6 +#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6 +#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6 +#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6 +#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6 +#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask +#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7 +#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7 +#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7 +#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7 +#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7 +#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7 +#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7 +#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port B. +// +//***************************************************************************** +#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask +#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0 +#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0 +#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0 +#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask +#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1 +#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1 +#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1 +#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1 +#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask +#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2 +#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2 +#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2 +#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2 +#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2 +#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask +#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3 +#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3 +#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3 +#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3 +#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask +#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4 +#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4 +#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4 +#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4 +#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4 +#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask +#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5 +#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5 +#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5 +#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5 +#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5 +#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5 +#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5 +#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5 +#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask +#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6 +#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6 +#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6 +#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6 +#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6 +#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6 +#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6 +#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask +#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port C. +// +//***************************************************************************** +#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask +#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0 +#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask +#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1 +#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask +#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2 +#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask +#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3 +#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask +#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4 +#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4 +#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4 +#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4 +#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4 +#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4 +#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4 +#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask +#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5 +#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5 +#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5 +#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5 +#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5 +#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5 +#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5 +#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask +#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6 +#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6 +#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6 +#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6 +#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6 +#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6 +#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6 +#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6 +#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask +#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7 +#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7 +#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7 +#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7 +#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7 +#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7 +#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port D. +// +//***************************************************************************** +#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask +#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0 +#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0 +#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0 +#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0 +#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0 +#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0 +#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0 +#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0 +#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask +#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1 +#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1 +#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1 +#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1 +#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1 +#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1 +#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1 +#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1 +#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1 +#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1 +#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask +#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2 +#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2 +#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2 +#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2 +#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2 +#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask +#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3 +#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3 +#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3 +#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3 +#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3 +#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask +#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4 +#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4 +#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4 +#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4 +#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4 +#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask +#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5 +#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5 +#define GPIO_PCTL_PD5_I2S0RXMCLK \ + 0x00800000 // I2S0RXMCLK on PD5 +#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5 +#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5 +#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask +#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6 +#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6 +#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6 +#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6 +#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask +#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7 +#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7 +#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7 +#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7 +#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7 +#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port E. +// +//***************************************************************************** +#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask +#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0 +#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0 +#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0 +#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0 +#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0 +#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask +#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1 +#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1 +#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1 +#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1 +#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1 +#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1 +#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask +#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2 +#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2 +#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2 +#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2 +#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2 +#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2 +#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask +#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3 +#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3 +#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3 +#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3 +#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3 +#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3 +#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask +#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4 +#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4 +#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4 +#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4 +#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4 +#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask +#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5 +#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5 +#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask +#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6 +#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6 +#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6 +#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask +#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7 +#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7 +#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port F. +// +//***************************************************************************** +#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask +#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0 +#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0 +#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0 +#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0 +#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0 +#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask +#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1 +#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1 +#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1 +#define GPIO_PCTL_PF1_I2S0TXMCLK \ + 0x00000080 // I2S0TXMCLK on PF1 +#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1 +#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1 +#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask +#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2 +#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2 +#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2 +#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2 +#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask +#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3 +#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3 +#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3 +#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3 +#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask +#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4 +#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4 +#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4 +#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4 +#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4 +#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask +#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5 +#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5 +#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5 +#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5 +#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask +#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6 +#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6 +#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6 +#define GPIO_PCTL_PF6_I2S0TXMCLK \ + 0x09000000 // I2S0TXMCLK on PF6 +#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6 +#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask +#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7 +#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7 +#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7 +#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port G. +// +//***************************************************************************** +#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask +#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0 +#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0 +#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0 +#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0 +#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0 +#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0 +#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask +#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1 +#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1 +#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1 +#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1 +#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1 +#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask +#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2 +#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2 +#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2 +#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2 +#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask +#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3 +#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3 +#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3 +#define GPIO_PCTL_PG3_I2S0RXMCLK \ + 0x00009000 // I2S0RXMCLK on PG3 +#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask +#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4 +#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4 +#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4 +#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4 +#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4 +#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask +#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5 +#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5 +#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5 +#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5 +#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5 +#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5 +#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask +#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6 +#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6 +#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6 +#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6 +#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6 +#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask +#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7 +#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7 +#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7 +#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port H. +// +//***************************************************************************** +#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask +#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0 +#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0 +#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0 +#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0 +#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask +#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1 +#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1 +#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1 +#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1 +#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask +#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2 +#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2 +#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2 +#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2 +#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask +#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3 +#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3 +#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3 +#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3 +#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask +#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4 +#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4 +#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4 +#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask +#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5 +#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5 +#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5 +#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask +#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6 +#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6 +#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6 +#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask +#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7 +#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7 +#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port J. +// +//***************************************************************************** +#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask +#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0 +#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0 +#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0 +#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask +#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1 +#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1 +#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1 +#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1 +#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask +#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2 +#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2 +#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2 +#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask +#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3 +#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3 +#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3 +#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask +#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4 +#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4 +#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4 +#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask +#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5 +#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5 +#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5 +#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask +#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6 +#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6 +#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6 +#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask +#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7 +#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the GPIO Register offsets. +// +//***************************************************************************** +#define GPIO_O_PeriphID4 0x00000FD0 +#define GPIO_O_PeriphID5 0x00000FD4 +#define GPIO_O_PeriphID6 0x00000FD8 +#define GPIO_O_PeriphID7 0x00000FDC +#define GPIO_O_PeriphID0 0x00000FE0 +#define GPIO_O_PeriphID1 0x00000FE4 +#define GPIO_O_PeriphID2 0x00000FE8 +#define GPIO_O_PeriphID3 0x00000FEC +#define GPIO_O_PCellID0 0x00000FF0 +#define GPIO_O_PCellID1 0x00000FF4 +#define GPIO_O_PCellID2 0x00000FF8 +#define GPIO_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_PCellID1 0x000000F0 +#define GPIO_RV_PCellID3 0x000000B1 +#define GPIO_RV_PeriphID0 0x00000061 +#define GPIO_RV_PeriphID1 0x00000010 +#define GPIO_RV_PCellID0 0x0000000D +#define GPIO_RV_PCellID2 0x00000005 +#define GPIO_RV_PeriphID2 0x00000004 +#define GPIO_RV_LOCK 0x00000001 // Lock register RV. +#define GPIO_RV_PeriphID7 0x00000000 +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_PeriphID4 0x00000000 +#define GPIO_RV_PeriphID5 0x00000000 +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_PeriphID6 0x00000000 +#define GPIO_RV_PeriphID3 0x00000000 +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. + +#endif + +#endif // __HW_GPIO_H__ diff --git a/bsp/lm3s/inc/hw_hibernate.h b/bsp/lm3s/inc/hw_hibernate.h new file mode 100644 index 0000000000..ccd48af3cf --- /dev/null +++ b/bsp/lm3s/inc/hw_hibernate.h @@ -0,0 +1,245 @@ +//***************************************************************************** +// +// hw_hibernate.h - Defines and Macros for the Hibernation module. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_HIBERNATE_H__ +#define __HW_HIBERNATE_H__ + +//***************************************************************************** +// +// The following are defines for the Hibernation module register addresses. +// +//***************************************************************************** +#define HIB_RTCC 0x400FC000 // Hibernate RTC counter +#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0 +#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1 +#define HIB_RTCLD 0x400FC00C // Hibernate RTC load +#define HIB_CTL 0x400FC010 // Hibernate RTC control +#define HIB_IM 0x400FC014 // Hibernate interrupt mask +#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status +#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat +#define HIB_IC 0x400FC020 // Hibernate interrupt clear +#define HIB_RTCT 0x400FC024 // Hibernate RTC trim +#define HIB_DATA 0x400FC030 // Hibernate data area + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC counter +// register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter. +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC match 0 +// register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0. +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC match 1 +// register. +// +//***************************************************************************** +#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1. +#define HIB_RTCM1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC load +// register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load. +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate control +// register +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable. +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered. +#define HIB_CTL_VABORT 0x00000080 // low bat abort +#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator +#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect +#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin +#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match +#define HIB_CTL_CLKSEL 0x00000004 // clock input selection +#define HIB_CTL_HIBREQ 0x00000002 // request hibernation +#define HIB_CTL_RTCEN 0x00000001 // RTC enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate interrupt mask +// reg. +// +//***************************************************************************** +#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt +#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate raw interrupt +// status. +// +//***************************************************************************** +#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt +#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate masked int +// status. +// +//***************************************************************************** +#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt +#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate interrupt +// clear reg. +// +//***************************************************************************** +#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt +#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC trim +// register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value. +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate data register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV + // Registers[63:0]. +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the Hibernation module register +// addresses. +// +//***************************************************************************** +#define HIB_DATA_END 0x400FC130 // end of data area, exclusive + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// counter register. +// +//***************************************************************************** +#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// match 0 register. +// +//***************************************************************************** +#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// match 1 register. +// +//***************************************************************************** +#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// load register. +// +//***************************************************************************** +#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate raw +// interrupt status. +// +//***************************************************************************** +#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate +// masked int status. +// +//***************************************************************************** +#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// trim register. +// +//***************************************************************************** +#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate +// data register. +// +//***************************************************************************** +#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask + +#endif + +#endif // __HW_HIBERNATE_H__ diff --git a/bsp/lm3s/inc/hw_i2c.h b/bsp/lm3s/inc/hw_i2c.h new file mode 100644 index 0000000000..0a69c2e4d1 --- /dev/null +++ b/bsp/lm3s/inc/hw_i2c.h @@ -0,0 +1,412 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the offsets between the I2C master and slave +// registers. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 // I2C Master Slave Address +#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address +#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status +#define I2C_O_MCS 0x00000004 // I2C Master Control/Status +#define I2C_O_SDR 0x00000008 // I2C Slave Data +#define I2C_O_MDR 0x00000008 // I2C Master Data +#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period +#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask +#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status +#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask +#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status +#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt + // Status +#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear +#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt + // Status +#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear +#define I2C_O_MCR 0x00000020 // I2C Master Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address. +#define I2C_MSA_RS 0x00000001 // Receive not Send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address. +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_FBR 0x00000004 // First Byte Received. +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request. +#define I2C_SCSR_DA 0x00000001 // Device Active. +#define I2C_SCSR_RREQ 0x00000001 // Receive Request. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy. +#define I2C_MCS_IDLE 0x00000020 // I2C Idle. +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost. +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable. +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data. +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address. +#define I2C_MCS_STOP 0x00000004 // Generate STOP. +#define I2C_MCS_START 0x00000002 // Generate START. +#define I2C_MCS_ERROR 0x00000002 // Error. +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable. +#define I2C_MCS_BUSY 0x00000001 // I2C Busy. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer. +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred. +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period. +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask. +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask. +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status. +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status. +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_IM 0x00000001 // Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status. +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status. +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear. +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear. +#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_IC 0x00000001 // Interrupt Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable. +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable. +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the offsets between the I2C master +// and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following are deprecated defines for the I2C master register offsets. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following are deprecated defines for the I2C slave register offsets. +// +//***************************************************************************** +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C master +// slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Control and Status register. +// +//***************************************************************************** +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ERR_MASK 0x0000001C +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run + +//***************************************************************************** +// +// The following are deprecated defines for the values used in determining the +// contents of the I2C Master Timer Period register. +// +//***************************************************************************** +#define I2C_SCL_FAST 400000 // SCL fast frequency +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Interrupt Mask register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Raw Interrupt Status register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Masked Interrupt Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Interrupt Clear register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Configuration register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave Own +// Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Control/Status register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Interrupt Mask register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave Raw +// Interrupt Status register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Masked Interrupt Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Interrupt Clear register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SIMR +// register. +// +//***************************************************************************** +#define I2C_SIMR_IM 0x00000001 // Interrupt Mask. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SRIS +// register. +// +//***************************************************************************** +#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SMIS +// register. +// +//***************************************************************************** +#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SICR +// register. +// +//***************************************************************************** +#define I2C_SICR_IC 0x00000001 // Clear Interrupt. + +#endif + +#endif // __HW_I2C_H__ diff --git a/bsp/lm3s/inc/hw_i2s.h b/bsp/lm3s/inc/hw_i2s.h new file mode 100644 index 0000000000..350d07e568 --- /dev/null +++ b/bsp/lm3s/inc/hw_i2s.h @@ -0,0 +1,233 @@ +//***************************************************************************** +// +// hw_i2s.h - Macros for use in accessing the I2S registers. +// +// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_I2S_H__ +#define __HW_I2S_H__ + +//***************************************************************************** +// +// The following are defines for the Inter-Integrated Circuit Sound (I2S) +// Interface +// +//***************************************************************************** +#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data +#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration +#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module + // Configuration +#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit +#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status + // and Mask +#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level +#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data +#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration +#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration +#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit +#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and + // Mask +#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level +#define I2S_O_CFG 0x00000C00 // I2S Module Configuration +#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask +#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status +#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status +#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_TXFIFO register. +// +//***************************************************************************** +#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data. +#define I2S_TXFIFO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_TXFIFOCFG +// register. +// +//***************************************************************************** +#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size. +#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_TXCFG register. +// +//***************************************************************************** +#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data. +#define I2S_TXCFG_DLY 0x10000000 // Data Delay. +#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity. +#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity. +#define I2S_TXCFG_WM_M 0x03000000 // Write Mode. +#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode +#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode +#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode +#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty. +#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave. +#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size. +#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size. +#define I2S_TXCFG_SSZ_S 10 +#define I2S_TXCFG_SDSZ_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_TXLIMIT register. +// +//***************************************************************************** +#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit. +#define I2S_TXLIMIT_LIMIT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_TXISM register. +// +//***************************************************************************** +#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request + // Interrupt. +#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_TXLEV register. +// +//***************************************************************************** +#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples. +#define I2S_TXLEV_LEVEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RXFIFO register. +// +//***************************************************************************** +#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data. +#define I2S_RXFIFO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RXFIFOCFG +// register. +// +//***************************************************************************** +#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode. +#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size. +#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RXCFG register. +// +//***************************************************************************** +#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data. +#define I2S_RXCFG_DLY 0x10000000 // Data Delay. +#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity. +#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity. +#define I2S_RXCFG_RM 0x01000000 // Read Mode. +#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave. +#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size. +#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size. +#define I2S_RXCFG_SSZ_S 10 +#define I2S_RXCFG_SDSZ_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RXLIMIT register. +// +//***************************************************************************** +#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit. +#define I2S_RXLIMIT_LIMIT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RXISM register. +// +//***************************************************************************** +#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request + // Interrupt. +#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RXLEV register. +// +//***************************************************************************** +#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples. +#define I2S_RXLEV_LEVEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_CFG register. +// +//***************************************************************************** +#define I2S_CFG_RXSLV 0x00000020 // When clear, this bit configures + // the receiver to use the + // externally driven I2S0RXMCLK + // signal. +#define I2S_CFG_TXSLV 0x00000010 // When clear, this bit configures + // the transmitter to use the + // externally driven I2S0TXMCLK + // signal. +#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable. +#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_IM register. +// +//***************************************************************************** +#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error. +#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request. +#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error. +#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_RIS register. +// +//***************************************************************************** +#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error. +#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request. +#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error. +#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_MIS register. +// +//***************************************************************************** +#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error. +#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request. +#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error. +#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2S_O_IC register. +// +//***************************************************************************** +#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error. +#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error. + +#endif // __HW_I2S_H__ diff --git a/bsp/lm3s/inc/hw_ints.h b/bsp/lm3s/inc/hw_ints.h new file mode 100644 index 0000000000..b7acfb9932 --- /dev/null +++ b/bsp/lm3s/inc/hw_ints.h @@ -0,0 +1,140 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI0 23 // SSI0 Rx and Tx +#define INT_I2C0 24 // I2C0 Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI0 29 // Quadrature Encoder 0 +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_GPIOG 47 // GPIO Port G +#define INT_GPIOH 48 // GPIO Port H +#define INT_UART2 49 // UART2 Rx and Tx +#define INT_SSI1 50 // SSI1 Rx and Tx +#define INT_TIMER3A 51 // Timer 3 subtimer A +#define INT_TIMER3B 52 // Timer 3 subtimer B +#define INT_I2C1 53 // I2C1 Master and Slave +#define INT_QEI1 54 // Quadrature Encoder 1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_CAN2 57 // CAN2 +#define INT_ETH 58 // Ethernet +#define INT_HIBERNATE 59 // Hibernation module +#define INT_USB0 60 // USB 0 Controller +#define INT_PWM3 61 // PWM Generator 3 +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error +#define INT_ADC1SS0 64 // ADC1 Sequence 0 +#define INT_ADC1SS1 65 // ADC1 Sequence 1 +#define INT_ADC1SS2 66 // ADC1 Sequence 2 +#define INT_ADC1SS3 67 // ADC1 Sequence 3 +#define INT_I2S0 68 // I2S0 +#define INT_EPI0 69 // EPI0 +#define INT_GPIOJ 70 // GPIO Port J + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 70 + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_QEI 29 // Quadrature Encoder + +#endif + +#endif // __HW_INTS_H__ diff --git a/bsp/lm3s/inc/hw_memmap.h b/bsp/lm3s/inc/hw_memmap.h new file mode 100644 index 0000000000..89b143426d --- /dev/null +++ b/bsp/lm3s/inc/hw_memmap.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG0_BASE 0x40000000 // Watchdog0 +#define WATCHDOG1_BASE 0x40001000 // Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master +#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave +#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master +#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM_BASE 0x40028000 // PWM +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define ADC0_BASE 0x40038000 // ADC0 +#define ADC1_BASE 0x40039000 // ADC1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define CAN2_BASE 0x40042000 // CAN2 +#define ETH_BASE 0x40048000 // Ethernet +#define MAC_BASE 0x40048000 // Ethernet +#define USB0_BASE 0x40050000 // USB 0 Controller +#define I2S0_BASE 0x40054000 // I2S0 +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define EPI0_BASE 0x400D0000 // EPI0 +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the base address of the memories +// and peripherals. +// +//***************************************************************************** +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define SSI_BASE 0x40008000 // SSI +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define QEI_BASE 0x4002C000 // QEI +#define ADC_BASE 0x40038000 // ADC + +#endif + +#endif // __HW_MEMMAP_H__ diff --git a/bsp/lm3s/inc/hw_nvic.h b/bsp/lm3s/inc/hw_nvic.h new file mode 100644 index 0000000000..4cf6aa47c8 --- /dev/null +++ b/bsp/lm3s/inc/hw_nvic.h @@ -0,0 +1,1027 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register +#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register +#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register +#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register +#define NVIC_PRI12 0xE000E430 // IRQ 48 to 51 Priority Register +#define NVIC_PRI13 0xE000E434 // IRQ 52 to 55 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable +#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable +#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable +#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable +#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable +#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable +#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable +#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend +#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend +#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend +#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend +#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend +#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend +#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active +#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active +#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active +#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask +#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask +#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask +#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask +#define NVIC_PRI8_INT35_S 24 +#define NVIC_PRI8_INT34_S 16 +#define NVIC_PRI8_INT33_S 8 +#define NVIC_PRI8_INT32_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask +#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask +#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask +#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask +#define NVIC_PRI9_INT39_S 24 +#define NVIC_PRI9_INT38_S 16 +#define NVIC_PRI9_INT37_S 8 +#define NVIC_PRI9_INT36_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask +#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask +#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask +#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask +#define NVIC_PRI10_INT43_S 24 +#define NVIC_PRI10_INT42_S 16 +#define NVIC_PRI10_INT41_S 8 +#define NVIC_PRI10_INT40_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask +#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/bsp/lm3s/inc/hw_pwm.h b/bsp/lm3s/inc/hw_pwm.h new file mode 100644 index 0000000000..8b9e028fe0 --- /dev/null +++ b/bsp/lm3s/inc/hw_pwm.h @@ -0,0 +1,716 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// The following are defines for the PWM Module Register offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register +#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value +#define PWM_O_0_CTL 0x00000040 // PWM0 Control +#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger + // Enable +#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status +#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear +#define PWM_O_0_LOAD 0x00000050 // PWM0 Load +#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter +#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A +#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B +#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control +#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control +#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control +#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay +#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band + // Falling-Edge-Delay +#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 +#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 +#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period +#define PWM_O_1_CTL 0x00000080 // PWM1 Control +#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable +#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status +#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear +#define PWM_O_1_LOAD 0x00000090 // PWM1 Load +#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter +#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A +#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B +#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control +#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control +#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control +#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay +#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band + // Falling-Edge-Delay +#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 +#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 +#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period +#define PWM_O_2_CTL 0x000000C0 // PWM2 Control +#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable +#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status +#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear +#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load +#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter +#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A +#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B +#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control +#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control +#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control +#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay +#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band + // Falling-Edge-Delay +#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 +#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 +#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period +#define PWM_O_3_CTL 0x00000100 // PWM3 Control +#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger + // Enable +#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status +#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear +#define PWM_O_3_LOAD 0x00000110 // PWM3 Load +#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter +#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A +#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B +#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control +#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control +#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control +#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay +#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band + // Falling-Edge-Delay +#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 +#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 +#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period +#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense +#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 +#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 +#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense +#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 +#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 +#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense +#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 +#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 +#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense +#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 +#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Master Control +// register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3. +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2. +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1. +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Time Base Sync +// register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Output Enable +// register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable +#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert +#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault +#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status. +#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status. +#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status. +#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg +#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition +#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition +#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base +#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base + +//***************************************************************************** +// +// The following are defines for the PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input. +#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled +#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source. +#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for + // the PWMnDBFALL register. +#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode. +#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode. +#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode. +#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode. +#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block + +//***************************************************************************** +// +// The following are defines for the PWM Generator extended offsets. +// +//***************************************************************************** +#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense +#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status +#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status +#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base +#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base +#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base +#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base + +//***************************************************************************** +// +// The following are defines for the PWM_X Interrupt/Trigger Enable Register +// bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPB D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPB U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 + +//***************************************************************************** +// +// The following are defines for the PWM_X Raw Interrupt Status Register bit +// definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3. +#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2. +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1. +#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable. +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0. +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable. +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable. +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable. +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3. +#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2. +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1. +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0. +#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted. +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted. +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted. +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted. +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted. +#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted. +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted. +#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted. +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted. +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status. +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status. +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status. +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_ISC register. +// +//***************************************************************************** +#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt. +#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt. +#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt. +#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt. +#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt. +#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_LOAD register. +// +//***************************************************************************** +#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value. +#define PWM_X_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_COUNT register. +// +//***************************************************************************** +#define PWM_X_COUNT_M 0x0000FFFF // Counter Value. +#define PWM_X_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPA register. +// +//***************************************************************************** +#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value. +#define PWM_X_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPB register. +// +//***************************************************************************** +#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value. +#define PWM_X_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENA register. +// +//***************************************************************************** +#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down. +#define PWM_X_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal. +#define PWM_X_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1. +#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up. +#define PWM_X_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal. +#define PWM_X_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1. +#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down. +#define PWM_X_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal. +#define PWM_X_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1. +#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up. +#define PWM_X_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal. +#define PWM_X_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1. +#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load. +#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal. +#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0. +#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1. +#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0. +#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal. +#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0. +#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENB register. +// +//***************************************************************************** +#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down. +#define PWM_X_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal. +#define PWM_X_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1. +#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up. +#define PWM_X_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal. +#define PWM_X_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1. +#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down. +#define PWM_X_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal. +#define PWM_X_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1. +#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up. +#define PWM_X_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal. +#define PWM_X_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1. +#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load. +#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal. +#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0. +#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1. +#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0. +#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal. +#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0. +#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBCTL register. +// +//***************************************************************************** +#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBRISE register. +// +//***************************************************************************** +#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay. +#define PWM_X_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBFALL register. +// +//***************************************************************************** +#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay. +#define PWM_X_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value. +#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value. +#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value. +#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value. +#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value. +#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value. +#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value. +#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period. +#define PWM_X_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. +// +//***************************************************************************** +#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense. +#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense. +#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense. +#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3. +#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2. +#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1. +#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3. +#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2. +#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1. +#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7. +#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6. +#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5. +#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4. +#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3. +#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2. +#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1. +#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger. +#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger. +#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger. +#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger. +#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger. +#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger. +#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger. +#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PWM Master +// Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following are deprecated defines for the PWM Interrupt Register bit +// definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PWM Status +// register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Interrupt Status Register +// bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Generator A/B Control +// Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Generator A/B Control +// Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one +#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero +#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal +#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Dead Band Control +// Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// The following are deprecated defines for the PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output + // pins +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output + // pins +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_X_COUNT 0x00000000 // The current counter value + +#endif + +#endif // __HW_PWM_H__ diff --git a/bsp/lm3s/inc/hw_qei.h b/bsp/lm3s/inc/hw_qei.h new file mode 100644 index 0000000000..fcb0a46b05 --- /dev/null +++ b/bsp/lm3s/inc/hw_qei.h @@ -0,0 +1,201 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following are defines for the QEI register offsets. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Pre-Scale Count. +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter. +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt. +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt. +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired + // Interrupt. +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the QEI_ISC +// register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the QEI +// registers. +// +//***************************************************************************** +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_TIME 0x00000000 // Velocity timer register + +#endif + +#endif // __HW_QEI_H__ diff --git a/bsp/lm3s/inc/hw_ssi.h b/bsp/lm3s/inc/hw_ssi.h new file mode 100644 index 0000000000..fe64552806 --- /dev/null +++ b/bsp/lm3s/inc/hw_ssi.h @@ -0,0 +1,220 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following are defines for the SSI register offsets. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register +#define SSI_O_DMACTL 0x00000024 // SSI DMA Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate. +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_M 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select. +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_EOT 0x00000010 // End of Transmission. +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI clock prescale +// register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor. +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data. +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt + // Mask. +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask. +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask. +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status. +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status. +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status. +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status. +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status. +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status. +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear. +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable. +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SSI Control +// register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_DSS 0x0000000F // Data size select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SSI clock +// prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following are deprecated defines for the SSI controller's FIFO size. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the interrupt +// mask set and clear, raw interrupt, masked interrupt, and interrupt clear +// registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif + +#endif // __HW_SSI_H__ diff --git a/bsp/lm3s/inc/hw_sysctl.h b/bsp/lm3s/inc/hw_sysctl.h new file mode 100644 index 0000000000..49c561f77a --- /dev/null +++ b/bsp/lm3s/inc/hw_sysctl.h @@ -0,0 +1,1625 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following are defines for the system control register addresses. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400FE000 // Device identification register 0 +#define SYSCTL_DID1 0x400FE004 // Device identification register 1 +#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4 +#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5 +#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6 +#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7 +#define SYSCTL_DC8 0x400FE02C // Device capabilities register 8 +#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register +#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register +#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400FE058 // Interrupt status register +#define SYSCTL_RESC 0x400FE05C // Reset cause register +#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register +#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control +#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO Host-Bus Control +#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2 +#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control +#define SYSCTL_PIOSCCTL 0x400FE088 // Precision internal oscillator + // control register +#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg +#define SYSCTL_DSFLASHCFG 0x400FE14C // Deep Sleep Flash Configuration +#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register +#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator + // Calibration +#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator + // Statistics +#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register +#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration +#define SYSCTL_DC9 0x400FE190 // Device capabilities register 9 +#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volitile Memory Information + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_SANDSTORM \ + 0x00000000 // Sandstorm-class Device +#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device +#define SYSCTL_DID0_CLASS_DUSTDEVIL \ + 0x00030000 // DustDevil-class Device +#define SYSCTL_DID0_CLASS_TEMPEST \ + 0x00040000 // Tempest-class Device +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 +#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 +#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 +#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 +#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version. +#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format + // definition, indicating a + // Stellaris LM3Snnn device. +#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1 + // register format, indicating a + // Stellaris Fury-class device. +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family. +#define SYSCTL_DID1_FAM_STELLARIS \ + 0x00000000 // Stellaris family of + // microcontollers, that is, all + // devices with external part + // numbers starting with LM3S. +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93 +#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91 +#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95 +#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92 +#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96 +#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90 +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 +#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 +#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110 +#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133 +#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138 +#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 +#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 +#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 +#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 +#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 +#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 +#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512 +#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538 +#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601 +#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607 +#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608 +#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 +#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625 +#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626 +#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627 +#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 +#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 +#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 +#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776 +#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850 +#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911 +#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918 +#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937 +#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 +#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 +#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 +#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 +#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 +#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276 +#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 +#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 +#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 +#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 +#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601 +#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608 +#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616 +#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 +#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 +#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 +#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671 +#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678 +#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 +#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 +#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776 +#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793 +#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911 +#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918 +#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 +#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 +#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 +#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 +#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651 +#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739 +#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748 +#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749 +#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632 +#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652 +#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662 +#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732 +#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737 +#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739 +#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747 +#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749 +#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752 +#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762 +#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791 +#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 +#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 +#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 +#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 +#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 +#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537 +#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 +#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611 +#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618 +#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 +#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 +#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 +#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 +#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911 +#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918 +#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 +#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 +#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 +#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 +#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 +#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 +#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 +#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730 +#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733 +#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738 +#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930 +#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933 +#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938 +#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 +#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 +#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971 +#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790 +#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792 +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count. +#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package +#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C + // to 105C) +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type. +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_S 16 // Part number shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash +#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift +#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present. +#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present. +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present. +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider. +#define SYSCTL_DC1_MINSYSDIV_100 \ + 0x00001000 // Specifies a 100-MHz clock with a + // PLL divider of 2. +#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Specifies a 66-MHz clock with a + // PLL divider of 3. +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz clock with a + // PLL divider of 4. +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8. +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10. +#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed. +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed. +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present. +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI0 Present. +#define SYSCTL_DC2_I2S0 0x10000000 // I2S 0 Present. +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present +#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present +#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present. +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // AIN7 Pin Present. +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // AIN6 Pin Present. +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // AIN5 Pin Present. +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // AIN4 Pin Present. +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // AIN3 Pin Present. +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // AIN2 Pin Present. +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // AIN1 Pin Present. +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // AIN0 Pin Present. +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present. +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present. +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present. +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable. +#define SYSCTL_DC4_PICAL 0x00040000 // When set, indicates that the + // USER can calibrate the PIOSC +#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present. +#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present. +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present. +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present. +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present. +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay. +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BORTIM_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage. +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset. +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset. +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset. +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor. +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider. +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor. +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable. +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal +#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal +#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal +#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB) +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB) +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB) +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value. +#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value. +#define SYSCTL_PLLCFG_F_S 5 +#define SYSCTL_PLLCFG_R_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider +#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 +#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 +#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 +#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 +#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 +#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 +#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 +#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 +#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 +#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 +#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 +#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 +#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 +#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 +#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 +#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 +#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 +#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 +#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 +#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 +#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 +#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 +#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 +#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 +#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 +#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 +#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 +#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 +#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 +#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 +#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 +#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 +#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 +#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 +#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 +#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 +#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 +#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 +#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 +#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 +#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 +#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 +#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 +#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 +#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 +#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 +#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 +#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 +#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 +#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 +#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 +#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 +#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 +#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 +#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 +#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 +#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 +#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 +#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 +#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 +#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 +#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 +#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 +#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL. +#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source. +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. +#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // Use the 4.19 MHz external osc. +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. +#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override. +#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 +#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 +#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 +#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 +#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 +#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 +#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 +#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 +#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 +#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 +#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 +#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 +#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 +#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 +#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 +#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 +#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 +#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 +#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 +#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 +#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 +#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 +#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 +#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 +#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 +#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 +#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 +#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 +#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 +#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 +#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 +#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 +#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 +#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 +#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 +#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 +#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 +#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 +#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 +#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 +#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 +#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 +#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 +#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 +#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 +#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 +#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 +#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 +#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 +#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 +#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 +#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 +#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 +#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 +#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 +#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 +#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 +#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 +#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 +#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 +#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 +#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 +#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source. +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. +#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source. +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control. +#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control. +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control. +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control. +#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control. +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control. +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control. +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control. +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control. +#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S 0 Reset Control. +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control. +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control. +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control. +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control. +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control. +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control. +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control. +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control. +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control. +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control. +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control. +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control. +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control. +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control. +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control. +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control. +#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control. +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control. +#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control. +#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control. +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control. +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control. +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control. +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control. +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control. +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control. +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control. +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status. +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status. +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status. +#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt + // Status. +#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw + // Interrupt Status. +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw + // Interrupt Status. +#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw + // Interrupt Status. +#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt + // Status. +#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask. +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask. +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask. +#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask. +#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault + // Interrupt Mask. +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt + // Mask. +#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt + // Mask. +#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask. +#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status. +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status. +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt + // Status. +#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt + // Status. +#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked + // Interrupt Status. +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked + // Interrupt Status. +#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked + // Interrupt Status. +#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control. +#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. +#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control. +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control. +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. +#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed. +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed. +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control. +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating. +#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating Control. +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock + // Gating. +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock + // Gating. +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock + // Gating. +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control. +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control. +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. +#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control. +#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. +#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control. +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control. +#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. +#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control. +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control. +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. +#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed. +#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed. +#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control. +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating. +#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S 0 Clock Gating. +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock + // Gating. +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock + // Gating. +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock + // Gating. +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control. +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control. +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. +#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control. +#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. +#define SYSCTL_SCGC2_GPIOJ 0x00000100 // GPIO Port J Present. +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control. +#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. +#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control. +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control. +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. +#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_DCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed. +#define SYSCTL_DCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed. +#define SYSCTL_DCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control. +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating. +#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S 0 Clock Gating. +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock + // Gating. +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock + // Gating. +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock + // Gating. +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control. +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control. +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. +#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control. +#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. +#define SYSCTL_DCGC2_GPIOJ 0x00000100 // GPIO Port J Present. +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present. +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present. +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present. +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present. +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is + // active. +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is + // active. +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present. +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present. +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present. +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present. +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present. +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present. +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present. +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // This specifies that USB0 PHY is + // present. +#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is + // present and its capability. +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed. +#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed. +#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed. +#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed. +#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed. +#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed. +#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed. +#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // SW. +#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX. +#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX. +#define SYSCTL_DC7_DMACH27 0x08000000 // ADC1_SS3. +#define SYSCTL_DC7_DMACH26 0x04000000 // ADC1_SS2. +#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1. +#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25. +#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24. +#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0. +#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23. +#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX. +#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX. +#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22. +#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_TX. +#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_RX. +#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B. +#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A. +#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3. +#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2. +#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B. +#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A. +#define SYSCTL_DC7_DMACH13 0x00002000 // UART2_TX. +#define SYSCTL_DC7_DMACH12 0x00001000 // UART2_RX. +#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11. +#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / UART1_TX. +#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10. +#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / UART1_RX. +#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9. +#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / SSI1_TX. +#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / SSI1_RX. +#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8. +#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B. +#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A. +#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B. +#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5. +#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4. +#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A. +#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3. +#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B. +#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2. +#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A. +#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1. +#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX. +#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX. +#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present. +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present. +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present. +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present. +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC1 11 Pin Present. +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC1 10 Pin Present. +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC1 9 Pin Present. +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC1 8 Pin Present. +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC1 7 Pin Present. +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC1 6 Pin Present. +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC1 5 Pin Present. +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC1 4 Pin Present. +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC1 3 Pin Present. +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC1 2 Pin Present. +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC1 1 Pin Present. +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC1 0 Pin Present. +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present. +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present. +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present. +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present. +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC0 11 Pin Present. +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC0 10 Pin Present. +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC0 9 Pin Present. +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC0 8 Pin Present. +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC0 7 Pin Present. +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC0 6 Pin Present. +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC0 5 Pin Present. +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC0 4 Pin Present. +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC0 3 Pin Present. +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC0 2 Pin Present. +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC0 1 Pin Present. +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC0 0 Pin Present. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value. +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration. +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim. +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value. +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value. +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result. +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted. +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy. +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy. +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value. +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable. +#define SYSCTL_I2SMCLKCFG_RXI_M 0x0FF00000 // RX Clock Integer Input. +#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input. +#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable. +#define SYSCTL_I2SMCLKCFG_TXI_M 0x00000FF0 // TX Clock Integer Input. +#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input. +#define SYSCTL_I2SMCLKCFG_RXI_S 20 +#define SYSCTL_I2SMCLKCFG_RXF_S 16 +#define SYSCTL_I2SMCLKCFG_TXI_S 4 +#define SYSCTL_I2SMCLKCFG_TXF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 7 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 6 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 5 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 4 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 3 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 2 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 1 Dig Cmp Present. +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 0 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 7 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 6 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 5 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 4 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 3 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 2 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 1 Dig Cmp Present. +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 0 Dig Cmp Present. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_TPSW 0x00000010 // 1: Indicates 3rd party software + // in ROM. +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word flash write buffer + // function available. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSFLASHCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSFLASHCFG_SHDWN 0x00000001 // Flash Shutdown. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced Host Bus. +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced Host Bus. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the system control register +// addresses. +// +//***************************************************************************** +#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0 +#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID0 +// register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID1 +// register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC0 +// register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC1 +// register. +// +//***************************************************************************** +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC2 +// register. +// +//***************************************************************************** +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC3 +// register. +// +//***************************************************************************** +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0, +// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module +#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module +#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1, +// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 +#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 +#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 +#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2, +// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_ETH 0x50000000 // ETH module +#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module +#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module +#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RIS, +// SYSCTL_IMC, and SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RESC +// register. +// +//***************************************************************************** +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCC +// register. +// +//***************************************************************************** +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG +// register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCC2 +// register. +// +//***************************************************************************** +#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider +#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_DSLPCLKCFG register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override +#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0 +// register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control. +#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0 +// register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0 +// register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0 +// register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control. + +#endif + +#endif // __HW_SYSCTL_H__ diff --git a/bsp/lm3s/inc/hw_timer.h b/bsp/lm3s/inc/hw_timer.h new file mode 100644 index 0000000000..2ccc1a65c7 --- /dev/null +++ b/bsp/lm3s/inc/hw_timer.h @@ -0,0 +1,452 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration. +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode. +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode. +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match + // Interrupt Mask. +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match + // Interrupt Mask. +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw + // Interrupt. +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw + // Interrupt. +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match + // Interrupt Clear. +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match + // Interrupt Clear. +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load + // Register High. +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load + // Register Low. +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load + // Register. +#define TIMER_TBILR_TBILRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High. +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low. +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low. +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High. +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low. +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB. +#define TIMER_TBR_TBRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode. +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger. +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable. +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction. +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode + // Select. +#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode. +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode. +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode. +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode. +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode. +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger. +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable. +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction. +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode + // Select. +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode. +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode. +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode. +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode. +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked + // Interrupt. +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked + // Interrupt. +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked + // Interrupt. +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked + // Interrupt. +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked + // Interrupt. +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt. +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked + // Interrupt. +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked + // Interrupt. +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked + // Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale. +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale. +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match. +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match. +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High. +#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low. +#define TIMER_TAV_TAVH_S 16 +#define TIMER_TAV_TAVL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register. +#define TIMER_TBV_TBVL_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_MIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/bsp/lm3s/inc/hw_types.h b/bsp/lm3s/inc/hw_types.h new file mode 100644 index 0000000000..b293c73b4d --- /dev/null +++ b/bsp/lm3s/inc/hw_types.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Stellaris silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_SANDSTORM) +// { +// do some Sandstorm-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Stellaris family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Stellaris silicon. Many compilers will +// then detect the "hard-coded" conditionals, and appropriately optimize the +// code blocks, eliminating any "unreachable" code. This would result in +// a smaller Driverlib, thus producing a smaller final application size, but +// at the cost of limiting the Driverlib binary to a specific Stellaris +// silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_SANDSTORM +#define CLASS_IS_SANDSTORM \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM))) +#endif + +#ifndef CLASS_IS_FURY +#define CLASS_IS_FURY \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY)) +#endif + +#ifndef CLASS_IS_DUSTDEVIL +#define CLASS_IS_DUSTDEVIL \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL)) +#endif + +#ifndef CLASS_IS_TEMPEST +#define CLASS_IS_TEMPEST \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A1 +#define REVISION_IS_A1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_B0 +#define REVISION_IS_B0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_B1 +#define REVISION_IS_B1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C1 +#define REVISION_IS_C1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C2 +#define REVISION_IS_C2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) +#endif + +//***************************************************************************** +// +// Deprecated silicon class and revision detection macros. +// +//***************************************************************************** +#ifndef DEPRECATED +#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM +#define DEVICE_IS_FURY CLASS_IS_FURY +#define DEVICE_IS_REVA2 REVISION_IS_A2 +#define DEVICE_IS_REVC1 REVISION_IS_C1 +#define DEVICE_IS_REVC2 REVISION_IS_C2 +#endif + +#endif // __HW_TYPES_H__ diff --git a/bsp/lm3s/inc/hw_uart.h b/bsp/lm3s/inc/hw_uart.h new file mode 100644 index 0000000000..60f274758a --- /dev/null +++ b/bsp/lm3s/inc/hw_uart.h @@ -0,0 +1,436 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART Register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCRH 0x0000002C // UART Line Control +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_DMACTL 0x00000048 // UART DMA Control +#define UART_O_LCTL 0x00000090 // UART LIN Control +#define UART_O_LSS 0x00000094 // UART LIN Snap Shot +#define UART_O_LTIM 0x00000098 // UART LIN Timer + +//***************************************************************************** +// +// The following are defines for the Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received. +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// The following are defines for the Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator. +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect. +#define UART_FR_DSR 0x00000002 // Data Set Ready. +#define UART_FR_CTS 0x00000001 // Clear To Send. + +//***************************************************************************** +// +// The following are defines for the Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor. +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor. +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send. +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send. +#define UART_CTL_RTS 0x00000800 // Request to Send. +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready. +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable. +#define UART_CTL_HSE 0x00000020 // High-Speed Enable. +#define UART_CTL_EOT 0x00000010 // End of Transmission. +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support. +#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable +#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full +#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// The following are defines for the Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask. +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask. +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask. +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask. +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask. +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask. +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status. +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status. +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status. +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status. +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect odem + // Raw Interrupt Status. +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status. +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status. +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status. +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status. +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status. +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect odem + // Masked Interrupt Status. +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status. +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear. +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear. +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear. +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear. +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect odem + // Interrupt Clear. +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear. +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear. +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select. +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length. +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs. +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select. +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select. +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable. +#define UART_LCRH_BRK 0x00000001 // UART Send Break. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor. +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error. +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable. +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//***************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length. +#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits + // (default) +#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits +#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits +#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//***************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot. +#define UART_LSS_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//***************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value. +#define UART_LTIM_TIMER_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the UART Register offsets. +// +//***************************************************************************** +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_PeriphID4 0x00000FD0 +#define UART_O_PeriphID5 0x00000FD4 +#define UART_O_PeriphID6 0x00000FD8 +#define UART_O_PeriphID7 0x00000FDC +#define UART_O_PeriphID0 0x00000FE0 +#define UART_O_PeriphID1 0x00000FE4 +#define UART_O_PeriphID2 0x00000FE8 +#define UART_O_PeriphID3 0x00000FEC +#define UART_O_PCellID0 0x00000FF0 +#define UART_O_PCellID1 0x00000FF4 +#define UART_O_PCellID2 0x00000FF8 +#define UART_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the Data Register bits +// +//***************************************************************************** +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// The following are deprecated defines for the Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// The following are deprecated defines for the Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// The following are deprecated defines for the Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// The following are deprecated defines for the Interrupt FIFO Level Select +// Register bits +// +//***************************************************************************** +#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask +#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask + +//***************************************************************************** +// +// The following are deprecated defines for the Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// The following are deprecated defines for the Reset Values for UART +// Registers. +// +//***************************************************************************** +#define UART_RV_CTL 0x00000300 +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID3 0x000000B1 +#define UART_RV_FR 0x00000090 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_IM 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_IBRD 0x00000000 + +#endif + +#endif // __HW_UART_H__ diff --git a/bsp/lm3s/inc/hw_udma.h b/bsp/lm3s/inc/hw_udma.h new file mode 100644 index 0000000000..137ecd044d --- /dev/null +++ b/bsp/lm3s/inc/hw_udma.h @@ -0,0 +1,320 @@ +//***************************************************************************** +// +// hw_udma.h - Macros for use in accessing the UDMA registers. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_STAT 0x400FF000 // DMA Status +#define UDMA_CFG 0x400FF004 // DMA Configuration +#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer +#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control + // Base Pointer +#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request + // Status +#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request +#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set +#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear +#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set +#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear +#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set +#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear +#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate + // Set +#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate + // Clear +#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set +#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear +#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear +#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select +#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status + +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer. +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1. +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State. +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable. +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer. +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address. +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment. +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size. +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment. +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size. +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size. +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1). +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst. +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode. +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer. +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHALT register. +// +//***************************************************************************** +#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment + // Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UDMA_ENASET +// register. +// +//***************************************************************************** +#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set. + +#endif + +#endif // __HW_UDMA_H__ diff --git a/bsp/lm3s/inc/hw_usb.h b/bsp/lm3s/inc/hw_usb.h new file mode 100644 index 0000000000..2e30fb977f --- /dev/null +++ b/bsp/lm3s/inc/hw_usb.h @@ -0,0 +1,4638 @@ +//***************************************************************************** +// +// hw_usb.h - Macros for use in accessing the USB registers. +// +// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_USB_H__ +#define __HW_USB_H__ + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus (USB) Controller +// offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_EPS 0x00000450 // USB End-Point Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address. +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // ISO Update. +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect. +#define USB_POWER_RESET 0x00000008 // Reset. +#define USB_POWER_RESUME 0x00000004 // Resume Signaling. +#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode. +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt. +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt. +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt. +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt. +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt. +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt. +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt. +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt. +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt. +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt. +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt. +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt. +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt. +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt. +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt. +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt. +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt. +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt. +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt. +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt. +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt. +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt. +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt. +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt. +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt. +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt. +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt. +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt. +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt. +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable. +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable. +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable. +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable. +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable. +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable. +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable. +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable. +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable. +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable. +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable. +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable. +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable. +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable. +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable. +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable. +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable. +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable. +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable. +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable. +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable. +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable. +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable. +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable. +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable. +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable. +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable. +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable. +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable. +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBus Error. +#define USB_IS_SESREQ 0x00000040 // Session Request. +#define USB_IS_DISCON 0x00000020 // Session Disconnect. +#define USB_IS_CONN 0x00000010 // Session Connect. +#define USB_IS_SOF 0x00000008 // Start of Frame. +#define USB_IS_BABBLE 0x00000004 // Babble Detected. +#define USB_IS_RESET 0x00000004 // Reset Signal Detected. +#define USB_IS_RESUME 0x00000002 // Resume Signal Detected. +#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt. +#define USB_IE_SESREQ 0x00000040 // Enable Session Request + // Interrupt. +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt. +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt. +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt. +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt. +#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt. +#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt. +#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number. +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index. +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode. +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access. +#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode. +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected. +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected. +#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level. +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode. +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request. +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support. +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size. +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support. +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size. +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address. +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address. +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait. +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID. +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap. +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap. +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout. +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear. +#define USB_CSRL0_STATUS 0x00000040 // Status Packet. +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear. +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet. +#define USB_CSRL0_STALL 0x00000020 // Send Stall. +#define USB_CSRL0_SETEND 0x00000010 // Setup End. +#define USB_CSRL0_ERROR 0x00000010 // Error. +#define USB_CSRL0_DATAEND 0x00000008 // Data End. +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet. +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled. +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready. +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_CSRH0_DT 0x00000002 // Data Toggle. +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // Count. +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit. +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier. +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP1_MULT_S 11 +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL1_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL1_ERROR 0x00000004 // Error. +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH1_ISO 0x00000040 // ISO. +#define USB_TXCSRH1_MODE 0x00000020 // Mode. +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier. +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP1_MULT_S 11 +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL1_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL1_OVER 0x00000004 // Overrun. +#define USB_RXCSRL1_ERROR 0x00000004 // Error. +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH1_ISO 0x00000040 // ISO. +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier. +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP2_MULT_S 11 +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL2_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL2_ERROR 0x00000004 // Error. +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH2_ISO 0x00000040 // ISO. +#define USB_TXCSRH2_MODE 0x00000020 // Mode. +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier. +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP2_MULT_S 11 +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL2_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL2_ERROR 0x00000004 // Error. +#define USB_RXCSRL2_OVER 0x00000004 // Overrun. +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH2_ISO 0x00000040 // ISO. +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier. +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP3_MULT_S 11 +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL3_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL3_ERROR 0x00000004 // Error. +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH3_ISO 0x00000040 // ISO. +#define USB_TXCSRH3_MODE 0x00000020 // Mode. +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier. +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP3_MULT_S 11 +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL3_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL3_ERROR 0x00000004 // Error. +#define USB_RXCSRL3_OVER 0x00000004 // Overrun. +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH3_ISO 0x00000040 // ISO. +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action. +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable. +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense. +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable. +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable. +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration. +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and + // Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length. +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO15_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_MULTTRAN \ + 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL4_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL4_ERROR 0x00000004 // Error. +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH4_ISO 0x00000040 // ISO. +#define USB_TXCSRH4_MODE 0x00000020 // Mode. +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL4_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL4_OVER 0x00000004 // Overrun. +#define USB_RXCSRL4_ERROR 0x00000004 // Error. +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH4_ISO 0x00000040 // ISO. +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH4_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL5_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL5_ERROR 0x00000004 // Error. +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH5_ISO 0x00000040 // ISO. +#define USB_TXCSRH5_MODE 0x00000020 // Mode. +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL5_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL5_ERROR 0x00000004 // Error. +#define USB_RXCSRL5_OVER 0x00000004 // Overrun. +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH5_ISO 0x00000040 // ISO. +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH5_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL6_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL6_ERROR 0x00000004 // Error. +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH6_ISO 0x00000040 // ISO. +#define USB_TXCSRH6_MODE 0x00000020 // Mode. +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL6_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL6_ERROR 0x00000004 // Error. +#define USB_RXCSRL6_OVER 0x00000004 // Overrun. +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH6_ISO 0x00000040 // ISO. +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH6_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL7_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL7_ERROR 0x00000004 // Error. +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH7_ISO 0x00000040 // ISO. +#define USB_TXCSRH7_MODE 0x00000020 // Mode. +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL7_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL7_ERROR 0x00000004 // Error. +#define USB_RXCSRL7_OVER 0x00000004 // Overrun. +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH7_ISO 0x00000040 // ISO. +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH7_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. +// +//***************************************************************************** +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. +// +//***************************************************************************** +#define USB_TXCSRL8_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL8_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL8_ERROR 0x00000004 // Error. +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. +// +//***************************************************************************** +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH8_ISO 0x00000040 // ISO. +#define USB_TXCSRH8_MODE 0x00000020 // Mode. +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL8_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL8_OVER 0x00000004 // Overrun. +#define USB_RXCSRL8_ERROR 0x00000004 // Error. +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH8_ISO 0x00000040 // ISO. +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH8_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. +// +//***************************************************************************** +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. +// +//***************************************************************************** +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. +// +//***************************************************************************** +#define USB_TXCSRL9_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL9_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL9_ERROR 0x00000004 // Error. +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH9_ISO 0x00000040 // ISO. +#define USB_TXCSRH9_MODE 0x00000020 // Mode. +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL9_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL9_ERROR 0x00000004 // Error. +#define USB_RXCSRL9_OVER 0x00000004 // Overrun. +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH9_ISO 0x00000040 // ISO. +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH9_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. +// +//***************************************************************************** +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. +// +//***************************************************************************** +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. +// +//***************************************************************************** +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL10_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL10_ERROR 0x00000004 // Error. +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH10_ISO 0x00000040 // ISO. +#define USB_TXCSRH10_MODE 0x00000020 // Mode. +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL10_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL10_OVER 0x00000004 // Overrun. +#define USB_RXCSRL10_ERROR 0x00000004 // Error. +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH10_ISO 0x00000040 // ISO. +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH10_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT10_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. +// +//***************************************************************************** +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. +// +//***************************************************************************** +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. +// +//***************************************************************************** +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. +// +//***************************************************************************** +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL11_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL11_ERROR 0x00000004 // Error. +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH11_ISO 0x00000040 // ISO. +#define USB_TXCSRH11_MODE 0x00000020 // Mode. +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL11_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL11_OVER 0x00000004 // Overrun. +#define USB_RXCSRL11_ERROR 0x00000004 // Error. +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH11_ISO 0x00000040 // ISO. +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH11_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL12_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL12_ERROR 0x00000004 // Error. +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH12_ISO 0x00000040 // ISO. +#define USB_TXCSRH12_MODE 0x00000020 // Mode. +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL12_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL12_ERROR 0x00000004 // Error. +#define USB_RXCSRL12_OVER 0x00000004 // Overrun. +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH12_ISO 0x00000040 // ISO. +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH12_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL13_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL13_ERROR 0x00000004 // Error. +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH13_ISO 0x00000040 // ISO. +#define USB_TXCSRH13_MODE 0x00000020 // Mode. +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL13_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL13_OVER 0x00000004 // Overrun. +#define USB_RXCSRL13_ERROR 0x00000004 // Error. +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH13_ISO 0x00000040 // ISO. +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH13_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL14_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL14_ERROR 0x00000004 // Error. +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH14_ISO 0x00000040 // ISO. +#define USB_TXCSRH14_MODE 0x00000020 // Mode. +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL14_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL14_OVER 0x00000004 // Overrun. +#define USB_RXCSRL14_ERROR 0x00000004 // Error. +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH14_ISO 0x00000040 // ISO. +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH14_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL15_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL15_ERROR 0x00000004 // Error. +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH15_ISO 0x00000040 // ISO. +#define USB_TXCSRH15_MODE 0x00000020 // Mode. +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL15_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL15_ERROR 0x00000004 // Error. +#define USB_RXCSRL15_OVER 0x00000004 // Overrun. +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH15_ISO 0x00000040 // ISO. +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH15_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPS register. +// +//***************************************************************************** +#define USB_EPS_DMAC_M 0x00000F00 // DMA C Select. +#define USB_EPS_DMAB_M 0x000000F0 // DMA B Select. +#define USB_EPS_DMAA_M 0x0000000F // DMA A Select. +#define USB_EPS_DMAC_S 8 +#define USB_EPS_DMAB_S 4 +#define USB_EPS_DMAA_S 0 + +#endif // __HW_USB_H__ diff --git a/bsp/lm3s/inc/hw_watchdog.h b/bsp/lm3s/inc/hw_watchdog.h new file mode 100644 index 0000000000..1fb34e1c65 --- /dev/null +++ b/bsp/lm3s/inc/hw_watchdog.h @@ -0,0 +1,178 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved. +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 4694 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following are defines for the Watchdog Timer register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock. +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value. +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value. +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear. +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt + // Status. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the Watchdog Timer register +// offsets. +// +//***************************************************************************** +#define WDT_O_PeriphID4 0x00000FD0 +#define WDT_O_PeriphID5 0x00000FD4 +#define WDT_O_PeriphID6 0x00000FD8 +#define WDT_O_PeriphID7 0x00000FDC +#define WDT_O_PeriphID0 0x00000FE0 +#define WDT_O_PeriphID1 0x00000FE4 +#define WDT_O_PeriphID2 0x00000FE8 +#define WDT_O_PeriphID3 0x00000FEC +#define WDT_O_PCellID0 0x00000FF0 +#define WDT_O_PCellID1 0x00000FF4 +#define WDT_O_PCellID2 0x00000FF8 +#define WDT_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the WDT_TEST +// register. +// +//***************************************************************************** +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the WDT +// registers. +// +//***************************************************************************** +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_PCellID1 0x000000F0 +#define WDT_RV_PCellID3 0x000000B1 +#define WDT_RV_PeriphID1 0x00000018 +#define WDT_RV_PeriphID2 0x00000018 +#define WDT_RV_PCellID0 0x0000000D +#define WDT_RV_PCellID2 0x00000005 +#define WDT_RV_PeriphID0 0x00000005 +#define WDT_RV_PeriphID3 0x00000001 +#define WDT_RV_PeriphID5 0x00000000 +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_PeriphID4 0x00000000 +#define WDT_RV_PeriphID6 0x00000000 +#define WDT_RV_PeriphID7 0x00000000 +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register + +#endif + +#endif // __HW_WATCHDOG_H__ diff --git a/bsp/lm3s/inc/inc.sgxx b/bsp/lm3s/inc/inc.sgxx new file mode 100644 index 0000000000000000000000000000000000000000..f3dc08d788c7cae3259f335aa7db4b4e2a2ae229 GIT binary patch literal 1247 zcmWIWW@Zs#U|`^2&K zlcvV0^IpDsg`T>8dZ%2q;$@Mo_#IbRZWb{tDu zpwKikWY)~dLNOC&@rbx4Jy)GJMQmx)6s3p=9X5slxV!a%?iQcae`_Wa1A~G90|O5O z(A~x96&1*CUkP+K2&1{ZcKX@8+XezH?<>0we2;n-6f>z|(Vbr`Z+A{mRZC0w8#3wb zv$xtTYXwD&_uiDhe)#FT0^QK_`+t3YYr7&~Gj8*A^!;Tim}Ru+wdPsp zsDqbI?~L?o*zZ@#@?%Q>?4ZqR8>X=?ozE(3%CCK>_SJ8;x!F6?RP63nIn=9#w4^qE zsm;7@91&4GKkdl<Us{UTpd?!jK9*Ayn>@ymRv@*gR$@N`DQ*AV(QAlAD09(>o+BB)+$^2D0hdko`jePa@mr`>C8YA5njgSKvp)8a%LcW52SAaH8C&%09YLChX4Qo literal 0 HcmV?d00001 diff --git a/bsp/lm3s/project.Opt b/bsp/lm3s/project.Opt new file mode 100644 index 0000000000..f200c39ef1 --- /dev/null +++ b/bsp/lm3s/project.Opt @@ -0,0 +1,80 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (RT-Thread/LM3S), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Startup),1,0,0 +GRPOPT 2,(Kernel),0,0,0 +GRPOPT 3,(finsh),1,0,0 +GRPOPT 4,(LM3S),1,0,0 +GRPOPT 5,(driverlib),0,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<.\application.c> +OPTFFF 1,2,1,16777216,0,0,0,0,<.\board.c> +OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c> +OPTFFF 1,4,5,335544320,0,0,0,0,<.\rtconfig.h> +OPTFFF 2,5,1,0,0,0,0,0,<..\..\src\clock.c> +OPTFFF 2,6,1,0,0,0,0,0,<..\..\src\device.c> +OPTFFF 2,7,1,234881024,0,0,0,0,<..\..\src\idle.c> +OPTFFF 2,8,1,0,0,0,0,0,<..\..\src\ipc.c> +OPTFFF 2,9,1,0,0,0,0,0,<..\..\src\irq.c> +OPTFFF 2,10,1,0,0,0,0,0,<..\..\src\mem.c> +OPTFFF 2,11,1,0,0,0,0,0,<..\..\src\mempool.c> +OPTFFF 2,12,1,0,0,0,0,0,<..\..\src\object.c> +OPTFFF 2,13,1,0,0,0,0,0,<..\..\src\scheduler.c> +OPTFFF 2,14,1,0,0,0,0,0,<..\..\src\slab.c> +OPTFFF 2,15,1,0,0,0,0,0,<..\..\src\thread.c> +OPTFFF 2,16,1,0,0,0,0,0,<..\..\src\timer.c> +OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\kservice.c> +OPTFFF 3,18,1,0,0,0,0,0,<..\..\finsh\symbol.c> +OPTFFF 3,19,1,0,0,0,0,0,<..\..\finsh\cmd.c> +OPTFFF 3,20,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c> +OPTFFF 3,21,1,0,0,0,0,0,<..\..\finsh\finsh_error.c> +OPTFFF 3,22,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c> +OPTFFF 3,23,1,0,0,0,0,0,<..\..\finsh\finsh_init.c> +OPTFFF 3,24,1,0,0,0,0,0,<..\..\finsh\finsh_node.c> +OPTFFF 3,25,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c> +OPTFFF 3,26,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c> +OPTFFF 3,27,1,0,0,0,0,0,<..\..\finsh\finsh_token.c> +OPTFFF 3,28,1,0,0,0,0,0,<..\..\finsh\finsh_var.c> +OPTFFF 3,29,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c> +OPTFFF 3,30,1,0,0,0,0,0,<..\..\finsh\shell.c> +OPTFFF 4,31,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\cpu.c> +OPTFFF 4,32,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\interrupt.c> +OPTFFF 4,33,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\stack.c> +OPTFFF 4,34,2,0,0,157,157,0,<..\..\libcpu\arm\lm3s\context_rvds.S> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,88,0,0,0,116,0,0,0,222,2,0,0,106,1,0,0 } +OPTFFF 4,35,2,0,0,0,0,0,<..\..\libcpu\arm\lm3s\start_rvds.S> +OPTFFF 4,36,1,620756994,0,52,65,0,<..\..\libcpu\arm\lm3s\serial.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,196,2,0,0,75,1,0,0 } +OPTFFF 5,37,4,0,0,0,0,0,<.\driverlib\rvmdk\driverlib.lib> + + +TARGOPT 1, (RT-Thread/LM3S) + ADSCLK=6000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 0 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6918)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6918) + OPTDBG 48125,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() + OPTKEY 0,(DLGDARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=165,205,660,637,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)) + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T0) + OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)) + OPTKEY 0,(JL2CM3)(-U20090110 -O206 -S0 -C0 -JU1 -JI127.0.0.1 -JP0 -N00("ARM CoreSight SW-DP") -D00(3BA00477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000) + OPTDF 0x94 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/bsp/lm3s/project.Uv2 b/bsp/lm3s/project.Uv2 new file mode 100644 index 0000000000..d8245d2569 --- /dev/null +++ b/bsp/lm3s/project.Uv2 @@ -0,0 +1,140 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (RT-Thread/LM3S), 0x0004 // Tools: 'ARM-ADS' + +Group (Startup) +Group (Kernel) +Group (finsh) +Group (LM3S) +Group (driverlib) + +File 1,1,<.\application.c> +File 1,1,<.\board.c> +File 1,1,<.\startup.c> +File 1,5,<.\rtconfig.h> +File 2,1,<..\..\src\clock.c> +File 2,1,<..\..\src\device.c> +File 2,1,<..\..\src\idle.c> +File 2,1,<..\..\src\ipc.c> +File 2,1,<..\..\src\irq.c> +File 2,1,<..\..\src\mem.c> +File 2,1,<..\..\src\mempool.c> +File 2,1,<..\..\src\object.c> +File 2,1,<..\..\src\scheduler.c> +File 2,1,<..\..\src\slab.c> +File 2,1,<..\..\src\thread.c> +File 2,1,<..\..\src\timer.c> +File 2,1,<..\..\src\kservice.c> +File 3,1,<..\..\finsh\symbol.c> +File 3,1,<..\..\finsh\cmd.c> +File 3,1,<..\..\finsh\finsh_compiler.c> +File 3,1,<..\..\finsh\finsh_error.c> +File 3,1,<..\..\finsh\finsh_heap.c> +File 3,1,<..\..\finsh\finsh_init.c> +File 3,1,<..\..\finsh\finsh_node.c> +File 3,1,<..\..\finsh\finsh_ops.c> +File 3,1,<..\..\finsh\finsh_parser.c> +File 3,1,<..\..\finsh\finsh_token.c> +File 3,1,<..\..\finsh\finsh_var.c> +File 3,1,<..\..\finsh\finsh_vm.c> +File 3,1,<..\..\finsh\shell.c> +File 4,1,<..\..\libcpu\arm\lm3s\cpu.c> +File 4,1,<..\..\libcpu\arm\lm3s\interrupt.c> +File 4,1,<..\..\libcpu\arm\lm3s\stack.c> +File 4,2,<..\..\libcpu\arm\lm3s\context_rvds.S> +File 4,2,<..\..\libcpu\arm\lm3s\start_rvds.S> +File 4,1,<..\..\libcpu\arm\lm3s\serial.c> +File 5,4,<.\driverlib\rvmdk\driverlib.lib> + + +Options 1,0,0 // Target 'RT-Thread/LM3S' + Device (LM3S6918) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) + DevID (4722) + Rgf (LM3Sxxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\obj\) + OutName (rtthread-lm3s) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } + OCMADSIROM { 1,0,0,0,0,0,0,4,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN () + ADSCUDEF () + ADSCINCD (.;.\inc;..\..\include;..\..\libcpu\arm\lm3s;..\..\finsh) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--keep __fsym_* --keep __vsym_*) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6918)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6918) + OPTDBG 48125,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() + FLASH1 { 9,0,0,0,1,0,0,0,5,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (Segger\JL2CM3.dll) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/bsp/lm3s/rtconfig.h b/bsp/lm3s/rtconfig.h new file mode 100644 index 0000000000..7e91069320 --- /dev/null +++ b/bsp/lm3s/rtconfig.h @@ -0,0 +1,135 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX*/ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second*/ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug*/ +#define RT_DEBUG +/* #define RT_THREAD_DEBUG */ + +/* Using Hook*/ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore*/ +#define RT_USING_SEMAPHORE + +/* Using Mutex*/ +#define RT_USING_MUTEX + +/* Using Event*/ +#define RT_USING_EVENT + +/* Using Faset Event*/ +/* #define RT_USING_FASTEVENT */ + +/* Using MailBox*/ +#define RT_USING_MAILBOX + +/* Using Message Queue*/ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management*/ +#define RT_USING_HEAP + +/* Using Small MM*/ +#define RT_USING_SMALL_MEM + +/* Using SLAB Allocator*/ +/* #define RT_USING_SLAB */ + +/* SECTION: Device System */ +/* Using Device System*/ +#define RT_USING_DEVICE + +#define RT_USING_UART1 +// #define RT_USING_UART2 +// #define RT_USING_UART3 + +/* SECTION: Console options */ +/* the buffer size of console*/ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: FinSH shell options */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION + +/* SECTION: a mini libc */ +/* Using mini libc library*/ +/* #define RT_USING_MINILIBC */ + +/* SECTION: C++ support */ +/* Using C++ support*/ +/* #define RT_USING_CPLUSPLUS */ + +/* SECTION: DFS options */ +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 1 +/* the max number of opened files */ +#define DFS_FD_MAX 2 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +/* Using lighweight TCP/IP protocol stack*/ +/* #define RT_USING_LWIP */ + +/* Trace LwIP protocol*/ +/* #define RT_LWIP_DEBUG */ + +/* Enable ICMP protocol*/ +#define RT_LWIP_ICMP + +/* Enable IGMP protocol*/ +#define RT_LWIP_IGMP + +/* Enable UDP protocol*/ +#define RT_LWIP_UDP + +/* Enable TCP protocol*/ +#define RT_LWIP_TCP + +/* Enable SNMP protocol*/ +/* #define RT_LWIP_SNMP */ + +/* Using DHCP*/ +/* #define RT_LWIP_DHCP */ + +/* ip address of target*/ +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 + +/* gateway address of target*/ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target*/ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +#endif diff --git a/bsp/lm3s/startup.c b/bsp/lm3s/startup.c new file mode 100644 index 0000000000..5a27b553d6 --- /dev/null +++ b/bsp/lm3s/startup.c @@ -0,0 +1,139 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +/** + * @addtogroup LM3S + */ + +extern void rt_hw_serial_init(void); + +/*@{*/ +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +extern void finsh_set_device(char* device); +#endif + +extern int rt_application_init(void); +extern void rt_hw_sdcard_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert error has occurred. +* Input : - file: pointer to the source file name +* - line: assert error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(u8* file, u32 line) +{ + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); + + while (1) ; +} +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP + /* STM32F103VB has 20k SRAM, the end address of SRAM is 0x20005000 */ +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20005000); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)0x20005000); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)0x20005000); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init hardware serial device */ + rt_hw_serial_init(); +#ifdef RT_USING_DFS + /* init sd card device */ + rt_hw_sdcard_init(); +#endif + /* init all device */ + rt_device_init_all(); + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); +#ifdef RT_USING_DEVICE + finsh_set_device("uart1"); +#endif +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + rt_uint32_t level UNUSED; + + /* disable interrupt first */ + level = rt_hw_interrupt_disable(); + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/stm32/application.c b/bsp/stm32/application.c new file mode 100644 index 0000000000..5790d323ac --- /dev/null +++ b/bsp/stm32/application.c @@ -0,0 +1,303 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +/** + * @addtogroup STM32 + */ +/*@{*/ + +#include +#include + +#ifdef RT_USING_DFS +/* dfs init */ +#include +/* dfs filesystem:FAT filesystem init */ +#include +/* dfs filesystem:EFS filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +#ifdef RT_USING_LWIP +#include +#include +#endif + +#ifdef RT_USING_RTGUI +#include +#endif + +#include "lwip/sockets.h" +#define MAX_SERV 5 /* Maximum number of chargen services. Don't need too many */ +#define CHARGEN_THREAD_NAME "chargen" +#define CHARGEN_PRIORITY 200 /* Really low priority */ +#define CHARGEN_THREAD_STACKSIZE 1024 +struct charcb +{ + struct charcb *next; + int socket; + struct sockaddr_in cliaddr; + socklen_t clilen; + char nextchar; +}; + +static struct charcb *charcb_list = 0; +static int do_read(struct charcb *p_charcb); +static void close_chargen(struct charcb *p_charcb); + +/************************************************************** + * void chargen_thread(void *arg) + * + * chargen task. This server will wait for connections on well + * known TCP port number: 19. For every connection, the server will + * write as much data as possible to the tcp port. + **************************************************************/ +static void chargen_thread(void *arg) +{ + int listenfd; + struct sockaddr_in chargen_saddr; + fd_set readset; + fd_set writeset; + int i, maxfdp1; + struct charcb *p_charcb; + + /* First acquire our socket for listening for connections */ + listenfd = lwip_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + + LWIP_ASSERT("chargen_thread(): Socket create failed.", listenfd >= 0); + memset(&chargen_saddr, 0, sizeof(chargen_saddr)); + chargen_saddr.sin_family = AF_INET; + chargen_saddr.sin_addr.s_addr = htonl(INADDR_ANY); + chargen_saddr.sin_port = htons(19); // Chargen server port + + if (lwip_bind(listenfd, (struct sockaddr *) &chargen_saddr, sizeof(chargen_saddr)) == -1) + LWIP_ASSERT("chargen_thread(): Socket bind failed.", 0); + + /* Put socket into listening mode */ + if (lwip_listen(listenfd, MAX_SERV) == -1) + LWIP_ASSERT("chargen_thread(): Listen failed.", 0); + + /* Wait forever for network input: This could be connections or data */ + for (;;) + { + maxfdp1 = listenfd+1; + + /* Determine what sockets need to be in readset */ + FD_ZERO(&readset); + FD_ZERO(&writeset); + FD_SET(listenfd, &readset); + for (p_charcb = charcb_list; p_charcb; p_charcb = p_charcb->next) + { + if (maxfdp1 < p_charcb->socket + 1) + maxfdp1 = p_charcb->socket + 1; + FD_SET(p_charcb->socket, &readset); + FD_SET(p_charcb->socket, &writeset); + } + + /* Wait for data or a new connection */ + i = lwip_select(maxfdp1, &readset, &writeset, 0, 0); + + if (i == 0) continue; + + /* At least one descriptor is ready */ + if (FD_ISSET(listenfd, &readset)) + { + /* We have a new connection request!!! */ + /* Lets create a new control block */ + p_charcb = (struct charcb *)rt_calloc(1, sizeof(struct charcb)); + if (p_charcb) + { + p_charcb->socket = lwip_accept(listenfd, + (struct sockaddr *) &p_charcb->cliaddr, + &p_charcb->clilen); + if (p_charcb->socket < 0) + rt_free(p_charcb); + else + { + /* Keep this tecb in our list */ + p_charcb->next = charcb_list; + charcb_list = p_charcb; + p_charcb->nextchar = 0x21; + } + } + else + { + /* No memory to accept connection. Just accept and then close */ + int sock; + struct sockaddr cliaddr; + socklen_t clilen; + + sock = lwip_accept(listenfd, &cliaddr, &clilen); + if (sock >= 0) + lwip_close(sock); + } + } + /* Go through list of connected clients and process data */ + for (p_charcb = charcb_list; p_charcb; p_charcb = p_charcb->next) + { + if (FD_ISSET(p_charcb->socket, &readset)) + { + /* This socket is ready for reading. This could be because someone typed + * some characters or it could be because the socket is now closed. Try reading + * some data to see. */ + if (do_read(p_charcb) < 0) + break; + } + if (FD_ISSET(p_charcb->socket, &writeset)) + { + char line[80]; + char setchar = p_charcb->nextchar; + + for( i = 0; i < 59; i++) + { + line[i] = setchar; + if (++setchar == 0x7f) + setchar = 0x21; + } + line[i] = 0; + strcat(line, "\n\r"); + if (lwip_write(p_charcb->socket, line, strlen(line)) < 0) + { + close_chargen(p_charcb); + break; + } + if (++p_charcb->nextchar == 0x7f) + p_charcb->nextchar = 0x21; + } + } + } +} + +/************************************************************** + * void close_chargen(struct charcb *p_charcb) + * + * Close the socket and remove this charcb from the list. + **************************************************************/ +static void close_chargen(struct charcb *p_charcb) +{ + struct charcb *p_search_charcb; + + /* Either an error or tcp connection closed on other + * end. Close here */ + lwip_close(p_charcb->socket); + + /* Free charcb */ + if (charcb_list == p_charcb) + charcb_list = p_charcb->next; + else + for (p_search_charcb = charcb_list; p_search_charcb; p_search_charcb = p_search_charcb->next) + { + if (p_search_charcb->next == p_charcb) + { + p_search_charcb->next = p_charcb->next; + break; + } + } + + rt_free(p_charcb); +} + +/************************************************************** + * void do_read(struct charcb *p_charcb) + * + * Socket definitely is ready for reading. Read a buffer from the socket and + * discard the data. If no data is read, then the socket is closed and the + * charcb is removed from the list and freed. + **************************************************************/ +static int do_read(struct charcb *p_charcb) +{ + char buffer[80]; + int readcount; + + /* Read some data */ + readcount = lwip_read(p_charcb->socket, &buffer, 80); + if (readcount <= 0) + { + close_chargen(p_charcb); + return -1; + } + return 0; +} + +void chargen_init(void) +{ + rt_thread_t chargen; + + chargen = rt_thread_create(CHARGEN_THREAD_NAME, + chargen_thread, RT_NULL, + CHARGEN_THREAD_STACKSIZE, + CHARGEN_PRIORITY, 5); + if (chargen != RT_NULL) rt_thread_startup(chargen); +} + +/* thread phase init */ +void rt_init_thread_entry(void *parameter) +{ +/* Filesystem Initialization */ +#ifdef RT_USING_DFS + { + /* init the device filesystem */ + dfs_init(); + /* init the efsl filesystam*/ + efsl_init(); + + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "efs", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } +#endif + +/* LwIP Initialization */ +#ifdef RT_USING_LWIP + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + +#ifdef RT_USING_WEBSERVER + { + extern void thread_webserver(void *parameter); + rt_thread_t webserver; + + webserver = rt_thread_create("twebsrv", + thread_webserver, RT_NULL, + 4096, 140, 20); + rt_thread_startup(webserver); + + chargen_init(); + } +#endif + } +#endif +} + +int rt_application_init() +{ + rt_thread_t init_thread; + + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, 80, 20); + rt_thread_startup(init_thread); + + return 0; +} + +/*@}*/ diff --git a/bsp/stm32/board.c b/bsp/stm32/board.c new file mode 100644 index 0000000000..f166f87631 --- /dev/null +++ b/bsp/stm32/board.c @@ -0,0 +1,405 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first implementation + */ + +#include +#include + +#include "stm32f10x_lib.h" + +static void rt_hw_console_init(void); + +/** + * @addtogroup STM32 + */ + +/*@{*/ + +ErrorStatus HSEStartUpStatus; + +/******************************************************************************* + * Function Name : RCC_Configuration + * Description : Configures the different system clocks. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void RCC_Configuration(void) +{ + /* RCC system reset(for debug purpose) */ + RCC_DeInit(); + + /* Enable HSE */ + RCC_HSEConfig(RCC_HSE_ON); + + /* Wait till HSE is ready */ + HSEStartUpStatus = RCC_WaitForHSEStartUp(); + + if(HSEStartUpStatus == SUCCESS) + { + /* HCLK = SYSCLK */ + RCC_HCLKConfig(RCC_SYSCLK_Div1); + + /* PCLK2 = HCLK */ + RCC_PCLK2Config(RCC_HCLK_Div1); + /* PCLK1 = HCLK/2 */ + RCC_PCLK1Config(RCC_HCLK_Div2); + + /* Flash 2 wait state */ + FLASH_SetLatency(FLASH_Latency_2); + /* Enable Prefetch Buffer */ + FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); + + /* PLLCLK = 8MHz * 9 = 72 MHz */ + RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); + + /* Enable PLL */ + RCC_PLLCmd(ENABLE); + + /* Wait till PLL is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ; + + /* Select PLL as system clock source */ + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + /* Wait till PLL is used as system clock source */ + while(RCC_GetSYSCLKSource() != 0x08) ; + } +} + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x20000000 */ + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); +#endif +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + RCC_ClocksTypeDef rcc_clocks; + rt_uint32_t cnts; + + RCC_GetClocksFreq(&rcc_clocks); + + cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND; + + SysTick_SetReload(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); + SysTick_CounterCmd(SysTick_Counter_Enable); + SysTick_ITConfig(ENABLE); +} + +extern void rt_hw_interrupt_thread_switch(void); +/** + * This is the timer interrupt service routine. + * + */ +void rt_hw_timer_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} + +/******************************************************************************* +* Function Name : FSMC_SRAM_Init +* Description : Configures the FSMC and GPIOs to interface with the SRAM memory. +* This function must be called before any write/read operation +* on the SRAM. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_SRAM_Init(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE | + RCC_APB2Periph_GPIOF, ENABLE); + +/*-- GPIO Configuration ------------------------------------------------------*/ + /* SRAM Data lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | + GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | + GPIO_Pin_15; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* SRAM Address lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* NOE and NWE configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* NE3 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* NBL0, NBL1 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; + GPIO_Init(GPIOE, &GPIO_InitStructure); + +/*-- FSMC Configuration ------------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 2; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /* Enable FSMC Bank1_SRAM Bank */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +} + +/******************************************************************************* +* Function Name : FSMC_NOR_Init +* Description : Configures the FSMC and GPIOs to interface with the NOR memory. +* This function must be called before any write/read operation +* on the NOR. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NOR_Init(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | + RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE); + + /*-- GPIO Configuration ------------------------------------------------------*/ + /* NOR Data lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | + GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* NOR Address lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | + GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* NOE and NWE configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* NE2 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /*-- FSMC Configuration ----------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0x03; + p.FSMC_AddressHoldTime = 0x00; + p.FSMC_DataSetupTime = 0x04; + p.FSMC_BusTurnAroundDuration = 0x00; + p.FSMC_CLKDivision = 0x00; + p.FSMC_DataLatency = 0x00; + p.FSMC_AccessMode = FSMC_AccessMode_B; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /* Enable FSMC Bank1_NOR Bank */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); +} + +/** + * This function will initial STM32 board. + */ +void rt_hw_board_init() +{ + /* Configure the system clocks */ + RCC_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + /* SRAM init */ + FSMC_SRAM_Init(); + + /* Configure the SysTick */ + SysTick_Configuration(); + + rt_hw_console_init(); +} + +/* init console to support rt_kprintf */ +static void rt_hw_console_init() +{ + /* Enable USART1 and GPIOA clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + /* GPIO configuration */ + { + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure USART1 Tx (PA.09) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure USART1 Rx (PA.10) as input floating */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOA, &GPIO_InitStructure); + } + + /* USART configuration */ + { + USART_InitTypeDef USART_InitStructure; + + /* USART1 configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + - USART Clock disabled + - USART CPOL: Clock is active low + - USART CPHA: Data is captured on the middle + - USART LastBit: The clock pulse of the last data bit is not output to + the SCLK pin + */ + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(USART1, &USART_InitStructure); + /* Enable USART1 */ + USART_Cmd(USART1, ENABLE); + } +} + +/* write one character to serial, must not trigger interrupt */ +static void rt_hw_console_putc(const char c) +{ + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n')rt_hw_console_putc('\r'); + + while (!(USART1->SR & USART_FLAG_TXE)); + USART1->DR = (c & 0x1FF); +} + +/** + * This function is used by rt_kprintf to display a string on console. + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + rt_hw_console_putc (*str++); + } +} + +/*@}*/ diff --git a/bsp/stm32/board.h b/bsp/stm32/board.h new file mode 100644 index 0000000000..b1be7c47ac --- /dev/null +++ b/bsp/stm32/board.h @@ -0,0 +1,25 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +void rt_hw_board_led_on(int n); +void rt_hw_board_led_off(int n); +void rt_hw_board_init(void); + +void rt_hw_usart_init(void); +void rt_hw_sdcard_init(void); + +#endif diff --git a/bsp/stm32/cortexm3_macro.s b/bsp/stm32/cortexm3_macro.s new file mode 100644 index 0000000000..5984b58ef0 --- /dev/null +++ b/bsp/stm32/cortexm3_macro.s @@ -0,0 +1,279 @@ +;******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +;* File Name : cortexm3_macro.s +;* Author : MCD Application Team +;* Version : V1.1 +;* Date : 11/26/2007 +;* Description : Instruction wrappers for special Cortex-M3 instructions. +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + + ; Exported functions + EXPORT __WFI + EXPORT __WFE + EXPORT __SEV + EXPORT __ISB + EXPORT __DSB + EXPORT __DMB + EXPORT __SVC + EXPORT __MRS_CONTROL + EXPORT __MSR_CONTROL + EXPORT __MRS_PSP + EXPORT __MSR_PSP + EXPORT __MRS_MSP + EXPORT __MSR_MSP + EXPORT __SETPRIMASK + EXPORT __RESETPRIMASK + EXPORT __SETFAULTMASK + EXPORT __RESETFAULTMASK + EXPORT __BASEPRICONFIG + EXPORT __GetBASEPRI + EXPORT __REV_HalfWord + EXPORT __REV_Word + +;******************************************************************************* +; Function Name : __WFI +; Description : Assembler function for the WFI instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFI + + WFI + BX r14 + +;******************************************************************************* +; Function Name : __WFE +; Description : Assembler function for the WFE instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFE + + WFE + BX r14 + +;******************************************************************************* +; Function Name : __SEV +; Description : Assembler function for the SEV instruction. +; Input : None +; Return : None +;******************************************************************************* +__SEV + + SEV + BX r14 + +;******************************************************************************* +; Function Name : __ISB +; Description : Assembler function for the ISB instruction. +; Input : None +; Return : None +;******************************************************************************* +__ISB + + ISB + BX r14 + +;******************************************************************************* +; Function Name : __DSB +; Description : Assembler function for the DSB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DSB + + DSB + BX r14 + +;******************************************************************************* +; Function Name : __DMB +; Description : Assembler function for the DMB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DMB + + DMB + BX r14 + +;******************************************************************************* +; Function Name : __SVC +; Description : Assembler function for the SVC instruction. +; Input : None +; Return : None +;******************************************************************************* +__SVC + + SVC 0x01 + BX r14 + +;******************************************************************************* +; Function Name : __MRS_CONTROL +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Cortex-M3 CONTROL register value. +;******************************************************************************* +__MRS_CONTROL + + MRS r0, CONTROL + BX r14 + +;******************************************************************************* +; Function Name : __MSR_CONTROL +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Cortex-M3 CONTROL register new value. +; Return : None +;******************************************************************************* +__MSR_CONTROL + + MSR CONTROL, r0 + ISB + BX r14 + +;******************************************************************************* +; Function Name : __MRS_PSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Process Stack value. +;******************************************************************************* +__MRS_PSP + + MRS r0, PSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_PSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Process Stack new value. +; Return : None +;******************************************************************************* +__MSR_PSP + + MSR PSP, r0 ; set Process Stack value + BX r14 + +;******************************************************************************* +; Function Name : __MRS_MSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Main Stack value. +;******************************************************************************* +__MRS_MSP + + MRS r0, MSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_MSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Main Stack new value. +; Return : None +;******************************************************************************* +__MSR_MSP + + MSR MSP, r0 ; set Main Stack value + BX r14 + +;******************************************************************************* +; Function Name : __SETPRIMASK +; Description : Assembler function to set the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETPRIMASK + + CPSID i + BX r14 + +;******************************************************************************* +; Function Name : __RESETPRIMASK +; Description : Assembler function to reset the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETPRIMASK + + CPSIE i + BX r14 + +;******************************************************************************* +; Function Name : __SETFAULTMASK +; Description : Assembler function to set the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETFAULTMASK + + CPSID f + BX r14 + +;******************************************************************************* +; Function Name : __RESETFAULTMASK +; Description : Assembler function to reset the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETFAULTMASK + + CPSIE f + BX r14 + +;******************************************************************************* +; Function Name : __BASEPRICONFIG +; Description : Assembler function to set the Base Priority. +; Input : - r0 : Base Priority new value +; Return : None +;******************************************************************************* +__BASEPRICONFIG + + MSR BASEPRI, r0 + BX r14 + +;******************************************************************************* +; Function Name : __GetBASEPRI +; Description : Assembler function to get the Base Priority value. +; Input : None +; Return : - r0 : Base Priority value +;******************************************************************************* +__GetBASEPRI + + MRS r0, BASEPRI_MAX + BX r14 + +;******************************************************************************* +; Function Name : __REV_HalfWord +; Description : Reverses the byte order in HalfWord(16-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_HalfWord + + REV16 r0, r0 + BX r14 + +;******************************************************************************* +; Function Name : __REV_Word +; Description : Reverses the byte order in Word(32-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_Word + + REV r0, r0 + BX r14 + + END + +;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32/enc28j60.c b/bsp/stm32/enc28j60.c new file mode 100644 index 0000000000..841b740e9b --- /dev/null +++ b/bsp/stm32/enc28j60.c @@ -0,0 +1,727 @@ +#include "enc28j60.h" + +#include +#include "lwipopts.h" +#include "stm32f10x_lib.h" + +#define MAX_ADDR_LEN 6 + +// #define CSACTIVE GPIO_ResetBits(GPIOB, GPIO_Pin_12); +// #define CSPASSIVE GPIO_SetBits(GPIOB, GPIO_Pin_12); +#define CSACTIVE GPIOB->BRR = GPIO_Pin_12; +#define CSPASSIVE GPIOB->BSRR = GPIO_Pin_12; + +struct net_device +{ + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ +}; + +static struct net_device enc28j60_dev_entry; +static struct net_device *enc28j60_dev =&enc28j60_dev_entry; +static rt_uint8_t Enc28j60Bank; +static rt_uint16_t NextPacketPtr; +static struct rt_semaphore tx_sem; + +void _delay_us(rt_uint32_t us) +{ + rt_uint32_t len; + for (;us > 0; us --) + for (len = 0; len < 20; len++ ); +} + +void delay_ms(rt_uint32_t ms) +{ + rt_uint32_t len; + for (;ms > 0; ms --) + for (len = 0; len < 100; len++ ); +} + +rt_uint8_t spi_read_op(rt_uint8_t op, rt_uint8_t address) +{ + int temp=0; + CSACTIVE; + + SPI_I2S_SendData(SPI2, (op | (address & ADDR_MASK))); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + SPI_I2S_ReceiveData(SPI2); + SPI_I2S_SendData(SPI2, 0x00); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + + // do dummy read if needed (for mac and mii, see datasheet page 29) + if(address & 0x80) + { + SPI_I2S_ReceiveData(SPI2); + SPI_I2S_SendData(SPI2, 0x00); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + } + // release CS + + temp=SPI_I2S_ReceiveData(SPI2); + // for(t=0;t<20;t++); + CSPASSIVE; + return (temp); +} + +void spi_write_op(rt_uint8_t op, rt_uint8_t address, rt_uint8_t data) +{ + rt_uint32_t level; + + level = rt_hw_interrupt_disable(); + + CSACTIVE; + SPI_I2S_SendData(SPI2, op | (address & ADDR_MASK)); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + SPI_I2S_SendData(SPI2,data); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + CSPASSIVE; + + rt_hw_interrupt_enable(level); +} + +void enc28j60_set_bank(rt_uint8_t address) +{ + // set the bank (if needed) + if((address & BANK_MASK) != Enc28j60Bank) + { + // set the bank + spi_write_op(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0)); + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5); + Enc28j60Bank = (address & BANK_MASK); + } +} + +rt_uint8_t spi_read(rt_uint8_t address) +{ + // set the bank + enc28j60_set_bank(address); + // do the read + return spi_read_op(ENC28J60_READ_CTRL_REG, address); +} + +void spi_write(rt_uint8_t address, rt_uint8_t data) +{ + // set the bank + enc28j60_set_bank(address); + // do the write + spi_write_op(ENC28J60_WRITE_CTRL_REG, address, data); +} + +void enc28j60_phy_write(rt_uint8_t address, rt_uint16_t data) +{ + // set the PHY register address + spi_write(MIREGADR, address); + + // write the PHY data + spi_write(MIWRL, data); + spi_write(MIWRH, data>>8); + + // wait until the PHY write completes + while(spi_read(MISTAT) & MISTAT_BUSY) + { + _delay_us(15); + } +} + +// read upper 8 bits +rt_uint16_t enc28j60_phy_read(rt_uint8_t address) +{ + // Set the right address and start the register read operation + spi_write(MIREGADR, address); + spi_write(MICMD, MICMD_MIIRD); + + _delay_us(15); + + // wait until the PHY read completes + while(spi_read(MISTAT) & MISTAT_BUSY); + + // reset reading bit + spi_write(MICMD, 0x00); + + return (spi_read(MIRDH)); +} + +void enc28j60_clkout(rt_uint8_t clk) +{ + //setup clkout: 2 is 12.5MHz: + spi_write(ECOCON, clk & 0x7); +} + +/* + * Access the PHY to determine link status + */ +static void enc28j60_check_link_status() +{ + rt_uint16_t reg; + int duplex; + + reg = enc28j60_phy_read(PHSTAT2); + duplex = reg & PHSTAT2_DPXSTAT; + + if (reg & PHSTAT2_LSTAT) + { + /* on */ + } + else + { + /* off */ + } +} + +#ifdef RT_USING_FINSH +#include +/* + * Debug routine to dump useful register contents + */ +static void enc28j60(void) +{ + rt_kprintf("-- enc28j60 registers:\n"); + rt_kprintf("HwRevID: 0x%02x\n", spi_read(EREVID)); + rt_kprintf("Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"); + rt_kprintf(" 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",spi_read(ECON1), spi_read(ECON2), spi_read(ESTAT), spi_read(EIR), spi_read(EIE)); + rt_kprintf("MAC : MACON1 MACON3 MACON4\n"); + rt_kprintf(" 0x%02x 0x%02x 0x%02x\n", spi_read(MACON1), spi_read(MACON3), spi_read(MACON4)); + rt_kprintf("Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"); + rt_kprintf(" 0x%04x 0x%04x 0x%04x 0x%04x ", + (spi_read(ERXSTH) << 8) | spi_read(ERXSTL), + (spi_read(ERXNDH) << 8) | spi_read(ERXNDL), + (spi_read(ERXWRPTH) << 8) | spi_read(ERXWRPTL), + (spi_read(ERXRDPTH) << 8) | spi_read(ERXRDPTL)); + rt_kprintf("0x%02x 0x%02x 0x%04x\n", spi_read(ERXFCON), spi_read(EPKTCNT), + (spi_read(MAMXFLH) << 8) | spi_read(MAMXFLL)); + + rt_kprintf("Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"); + rt_kprintf(" 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n", + (spi_read(ETXSTH) << 8) | spi_read(ETXSTL), + (spi_read(ETXNDH) << 8) | spi_read(ETXNDL), + spi_read(MACLCON1), spi_read(MACLCON2), spi_read(MAPHSUP)); +} +FINSH_FUNCTION_EXPORT(enc28j60, dump enc28j60 registers) +#endif + +/* + * RX handler + * ignore PKTIF because is unreliable! (look at the errata datasheet) + * check EPKTCNT is the suggested workaround. + * We don't need to clear interrupt flag, automatically done when + * enc28j60_hw_rx() decrements the packet counter. + * Returns how many packet processed. + */ +void enc28j60_isr() +{ + /* Variable definitions can be made now. */ + volatile rt_uint32_t eir, pk_counter; + volatile rt_bool_t rx_activiated; + + rx_activiated = RT_FALSE; + + /* get EIR */ + eir = spi_read(EIR); + // rt_kprintf("eir: 0x%08x\n", eir); + + do + { + /* errata #4, PKTIF does not reliable */ + pk_counter = spi_read(EPKTCNT); + if (pk_counter) + { + rt_err_t result; + /* a frame has been received */ + result = eth_device_ready((struct eth_device*)&(enc28j60_dev->parent)); + RT_ASSERT(result == RT_EOK); + + // switch to bank 0 + enc28j60_set_bank(EIE); + // disable rx interrutps + spi_write_op(ENC28J60_BIT_FIELD_CLR, EIE, EIE_PKTIE); + } + + /* clear PKTIF */ + if (eir & EIR_PKTIF) + { + enc28j60_set_bank(EIR); + spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_PKTIF); + + rx_activiated = RT_TRUE; + } + + /* clear DMAIF */ + if (eir & EIR_DMAIF) + { + enc28j60_set_bank(EIR); + spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_DMAIF); + } + + /* LINK changed handler */ + if ( eir & EIR_LINKIF) + { + enc28j60_check_link_status(); + + /* read PHIR to clear the flag */ + enc28j60_phy_read(PHIR); + + enc28j60_set_bank(EIR); + spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_LINKIF); + } + + if (eir & EIR_TXIF) + { + /* A frame has been transmitted. */ + rt_sem_release(&tx_sem); + + enc28j60_set_bank(EIR); + spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXIF); + } + eir = spi_read(EIR); + // rt_kprintf("inner eir: 0x%08x\n", eir); + } while ((rx_activiated != RT_TRUE && eir != 0)); +} + +/* RT-Thread Device Interface */ + +/* initialize the interface */ +rt_err_t enc28j60_init(rt_device_t dev) +{ + CSPASSIVE; + + // perform system reset + spi_write_op(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); + delay_ms(50); + NextPacketPtr = RXSTART_INIT; + + // Rx start + spi_write(ERXSTL, RXSTART_INIT&0xFF); + spi_write(ERXSTH, RXSTART_INIT>>8); + // set receive pointer address + spi_write(ERXRDPTL, RXSTOP_INIT&0xFF); + spi_write(ERXRDPTH, RXSTOP_INIT>>8); + // RX end + spi_write(ERXNDL, RXSTOP_INIT&0xFF); + spi_write(ERXNDH, RXSTOP_INIT>>8); + + // TX start + spi_write(ETXSTL, TXSTART_INIT&0xFF); + spi_write(ETXSTH, TXSTART_INIT>>8); + // set transmission pointer address + spi_write(EWRPTL, TXSTART_INIT&0xFF); + spi_write(EWRPTH, TXSTART_INIT>>8); + // TX end + spi_write(ETXNDL, TXSTOP_INIT&0xFF); + spi_write(ETXNDH, TXSTOP_INIT>>8); + + // do bank 1 stuff, packet filter: + // For broadcast packets we allow only ARP packtets + // All other packets should be unicast only for our mac (MAADR) + // + // The pattern to match on is therefore + // Type ETH.DST + // ARP BROADCAST + // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9 + // in binary these poitions are:11 0000 0011 1111 + // This is hex 303F->EPMM0=0x3f,EPMM1=0x30 + spi_write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_BCEN); + + // do bank 2 stuff + // enable MAC receive + spi_write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS); + // enable automatic padding to 60bytes and CRC operations + // spi_write_op(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN); + spi_write_op(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); + // bring MAC out of reset + + // set inter-frame gap (back-to-back) + // spi_write(MABBIPG, 0x12); + spi_write(MABBIPG, 0x15); + + spi_write(MACON4, MACON4_DEFER); + spi_write(MACLCON2, 63); + + // set inter-frame gap (non-back-to-back) + spi_write(MAIPGL, 0x12); + spi_write(MAIPGH, 0x0C); + + // Set the maximum packet size which the controller will accept + // Do not send packets longer than MAX_FRAMELEN: + spi_write(MAMXFLL, MAX_FRAMELEN&0xFF); + spi_write(MAMXFLH, MAX_FRAMELEN>>8); + + // do bank 3 stuff + // write MAC address + // NOTE: MAC address in ENC28J60 is byte-backward + spi_write(MAADR0, enc28j60_dev->dev_addr[5]); + spi_write(MAADR1, enc28j60_dev->dev_addr[4]); + spi_write(MAADR2, enc28j60_dev->dev_addr[3]); + spi_write(MAADR3, enc28j60_dev->dev_addr[2]); + spi_write(MAADR4, enc28j60_dev->dev_addr[1]); + spi_write(MAADR5, enc28j60_dev->dev_addr[0]); + + /* output off */ + spi_write(ECOCON, 0x00); + + // enc28j60_phy_write(PHCON1, 0x00); + enc28j60_phy_write(PHCON1, PHCON1_PDPXMD); // full duplex + // no loopback of transmitted frames + enc28j60_phy_write(PHCON2, PHCON2_HDLDIS); + + enc28j60_set_bank(ECON2); + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC); + + // switch to bank 0 + enc28j60_set_bank(ECON1); + // enable interrutps + spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE|EIR_TXIF); + // enable packet reception + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); + + /* clock out */ + // enc28j60_clkout(2); + + enc28j60_phy_write(PHLCON, 0xD76); //0x476 + delay_ms(20); + + rt_kprintf("enc28j60 init ok!\n"); + + return RT_EOK; +} + +/* control the interface */ +rt_err_t enc28j60_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, enc28j60_dev_entry.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* Open the ethernet interface */ +rt_err_t enc28j60_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +/* Close the interface */ +rt_err_t enc28j60_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* Read */ +rt_size_t enc28j60_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* Write */ +rt_size_t enc28j60_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* ethernet device interface */ +/* + * Transmit packet. + */ +rt_err_t enc28j60_tx( rt_device_t dev, struct pbuf* p) +{ + struct pbuf* q; + rt_uint32_t len; + rt_uint8_t* ptr; + + // rt_kprintf("tx pbuf: 0x%08x\n", p); + + /* lock tx operation */ + rt_sem_take(&tx_sem, RT_WAITING_FOREVER); + + // Set the write pointer to start of transmit buffer area + spi_write(EWRPTL, TXSTART_INIT&0xFF); + spi_write(EWRPTH, TXSTART_INIT>>8); + // Set the TXND pointer to correspond to the packet size given + spi_write(ETXNDL, (TXSTART_INIT+ p->tot_len + 1)&0xFF); + spi_write(ETXNDH, (TXSTART_INIT+ p->tot_len + 1)>>8); + + // write per-packet control byte (0x00 means use macon3 settings) + spi_write_op(ENC28J60_WRITE_BUF_MEM, 0, 0x00); + + for (q = p; q != NULL; q = q->next) + { + CSACTIVE; + + SPI_I2S_SendData(SPI2, ENC28J60_WRITE_BUF_MEM); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + + len = q->len; + ptr = q->payload; + while(len) + { + SPI_I2S_SendData(SPI2,*ptr) ; + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET);; + ptr++; + + len--; + } + + CSPASSIVE; + } + + // send the contents of the transmit buffer onto the network + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS); + // Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12. + if( (spi_read(EIR) & EIR_TXERIF) ) + { + spi_write_op(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS); + } + + // rt_kprintf("tx ok\n"); + + return RT_EOK; +} + +struct pbuf *enc28j60_rx(rt_device_t dev) +{ + struct pbuf* p; + rt_uint32_t len; + rt_uint16_t rxstat; + rt_uint32_t pk_counter; + + p = RT_NULL; + + pk_counter = spi_read(EPKTCNT); + if (pk_counter) + { + // Set the read pointer to the start of the received packet + spi_write(ERDPTL, (NextPacketPtr)); + spi_write(ERDPTH, (NextPacketPtr)>>8); + + // read the next packet pointer + NextPacketPtr = spi_read_op(ENC28J60_READ_BUF_MEM, 0); + NextPacketPtr |= spi_read_op(ENC28J60_READ_BUF_MEM, 0)<<8; + + // read the packet length (see datasheet page 43) + len = spi_read_op(ENC28J60_READ_BUF_MEM, 0); //0x54 + len |= spi_read_op(ENC28J60_READ_BUF_MEM, 0) <<8; //5554 + + len-=4; //remove the CRC count + + // read the receive status (see datasheet page 43) + rxstat = spi_read_op(ENC28J60_READ_BUF_MEM, 0); + rxstat |= ((rt_uint16_t)spi_read_op(ENC28J60_READ_BUF_MEM, 0))<<8; + + // check CRC and symbol errors (see datasheet page 44, table 7-3): + // The ERXFCON.CRCEN is set by default. Normally we should not + // need to check this. + if ((rxstat & 0x80)==0) + { + // invalid + len=0; + } + else + { + /* allocation pbuf */ + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (p != RT_NULL) + { + rt_uint8_t* data; + struct pbuf* q; + + for (q = p; q != RT_NULL; q= q->next) + { + data = q->payload; + len = q->len; + + CSACTIVE; + + SPI_I2S_SendData(SPI2,ENC28J60_READ_BUF_MEM); + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + + SPI_I2S_ReceiveData(SPI2); + + while(len) + { + len--; + SPI_I2S_SendData(SPI2,0x00) ; + while(SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY)==SET); + + *data= SPI_I2S_ReceiveData(SPI2); + data++; + } + + CSPASSIVE; + } + } + } + + // Move the RX read pointer to the start of the next received packet + // This frees the memory we just read out + spi_write(ERXRDPTL, (NextPacketPtr)); + spi_write(ERXRDPTH, (NextPacketPtr)>>8); + + // decrement the packet counter indicate we are done with this packet + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC); + } + else + { + rt_uint32_t level; + /* lock enc28j60 */ + level = rt_hw_interrupt_disable(); + + // switch to bank 0 + enc28j60_set_bank(EIE); + // enable interrutps + spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE); + // switch to bank 0 + enc28j60_set_bank(ECON1); + // enable packet reception + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + return p; +} + +static void RCC_Configuration(void) +{ + /* enable spi2 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); + + /* enable gpiob port clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); +} + +static void NVIC_Configuration(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Configure one bit for preemption priority */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + + /* Enable the EXTI0 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +static void GPIO_Configuration() +{ + GPIO_InitTypeDef GPIO_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* configure PB0 as external interrupt */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure SPI2 pins: SCK, MISO and MOSI ----------------------------*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect ENC28J60 EXTI Line to GPIOB Pin 0 */ + GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource0); + + /* Configure ENC28J60 EXTI Line to generate an interrupt on falling edge */ + EXTI_InitStructure.EXTI_Line = EXTI_Line0; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(EXTI_Line0); +} + +static void SetupSPI (void) +{ + SPI_InitTypeDef SPI_InitStructure; + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(SPI2, &SPI_InitStructure); + SPI_Cmd(SPI2, ENABLE); +} + +static rt_timer_t enc28j60_timer; +void rt_hw_enc28j60_timeout(void* parameter) +{ + // switch to bank 0 + enc28j60_set_bank(EIE); + // enable interrutps + spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE); + // switch to bank 0 + enc28j60_set_bank(ECON1); + // enable packet reception + spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); + + enc28j60_isr(); +} + +int rt_hw_enc28j60_init() +{ + rt_err_t result; + + /* configuration PB5 as INT */ + RCC_Configuration(); + NVIC_Configuration(); + GPIO_Configuration(); + SetupSPI(); + + /* init rt-thread device interface */ + enc28j60_dev_entry.parent.parent.init = enc28j60_init; + enc28j60_dev_entry.parent.parent.open = enc28j60_open; + enc28j60_dev_entry.parent.parent.close = enc28j60_close; + enc28j60_dev_entry.parent.parent.read = enc28j60_read; + enc28j60_dev_entry.parent.parent.write = enc28j60_write; + enc28j60_dev_entry.parent.parent.control = enc28j60_control; + enc28j60_dev_entry.parent.eth_rx = enc28j60_rx; + enc28j60_dev_entry.parent.eth_tx = enc28j60_tx; + + /* Update MAC address */ + enc28j60_dev_entry.dev_addr[0] = 0x1e; + enc28j60_dev_entry.dev_addr[1] = 0x30; + enc28j60_dev_entry.dev_addr[2] = 0x6c; + enc28j60_dev_entry.dev_addr[3] = 0xa2; + enc28j60_dev_entry.dev_addr[4] = 0x45; + enc28j60_dev_entry.dev_addr[5] = 0x5e; + + rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); + + result = eth_device_init(&(enc28j60_dev->parent), "E0"); + + /* workaround for enc28j60 interrupt */ + enc28j60_timer = rt_timer_create("etimer", + rt_hw_enc28j60_timeout, RT_NULL, + 50, RT_TIMER_FLAG_PERIODIC); + if (enc28j60_timer != RT_NULL) + rt_timer_start(enc28j60_timer); + + return RT_EOK; +} diff --git a/bsp/stm32/enc28j60.h b/bsp/stm32/enc28j60.h new file mode 100644 index 0000000000..c8d27c2a5c --- /dev/null +++ b/bsp/stm32/enc28j60.h @@ -0,0 +1,256 @@ +#ifndef __ENC28J60_H__ +#define __ENC28J60_H__ + +#include + +// ENC28J60 Control Registers +// Control register definitions are a combination of address, +// bank number, and Ethernet/MAC/PHY indicator bits. +// - Register address (bits 0-4) +// - Bank number (bits 5-6) +// - MAC/PHY indicator (bit 7) +#define ADDR_MASK 0x1F +#define BANK_MASK 0x60 +#define SPRD_MASK 0x80 +// All-bank registers +#define EIE 0x1B +#define EIR 0x1C +#define ESTAT 0x1D +#define ECON2 0x1E +#define ECON1 0x1F +// Bank 0 registers +#define ERDPTL (0x00|0x00) +#define ERDPTH (0x01|0x00) +#define EWRPTL (0x02|0x00) +#define EWRPTH (0x03|0x00) +#define ETXSTL (0x04|0x00) +#define ETXSTH (0x05|0x00) +#define ETXNDL (0x06|0x00) +#define ETXNDH (0x07|0x00) +#define ERXSTL (0x08|0x00) +#define ERXSTH (0x09|0x00) +#define ERXNDL (0x0A|0x00) +#define ERXNDH (0x0B|0x00) +#define ERXRDPTL (0x0C|0x00) +#define ERXRDPTH (0x0D|0x00) +#define ERXWRPTL (0x0E|0x00) +#define ERXWRPTH (0x0F|0x00) +#define EDMASTL (0x10|0x00) +#define EDMASTH (0x11|0x00) +#define EDMANDL (0x12|0x00) +#define EDMANDH (0x13|0x00) +#define EDMADSTL (0x14|0x00) +#define EDMADSTH (0x15|0x00) +#define EDMACSL (0x16|0x00) +#define EDMACSH (0x17|0x00) +// Bank 1 registers +#define EHT0 (0x00|0x20) +#define EHT1 (0x01|0x20) +#define EHT2 (0x02|0x20) +#define EHT3 (0x03|0x20) +#define EHT4 (0x04|0x20) +#define EHT5 (0x05|0x20) +#define EHT6 (0x06|0x20) +#define EHT7 (0x07|0x20) +#define EPMM0 (0x08|0x20) +#define EPMM1 (0x09|0x20) +#define EPMM2 (0x0A|0x20) +#define EPMM3 (0x0B|0x20) +#define EPMM4 (0x0C|0x20) +#define EPMM5 (0x0D|0x20) +#define EPMM6 (0x0E|0x20) +#define EPMM7 (0x0F|0x20) +#define EPMCSL (0x10|0x20) +#define EPMCSH (0x11|0x20) +#define EPMOL (0x14|0x20) +#define EPMOH (0x15|0x20) +#define EWOLIE (0x16|0x20) +#define EWOLIR (0x17|0x20) +#define ERXFCON (0x18|0x20) +#define EPKTCNT (0x19|0x20) +// Bank 2 registers +#define MACON1 (0x00|0x40|0x80) +#define MACON2 (0x01|0x40|0x80) +#define MACON3 (0x02|0x40|0x80) +#define MACON4 (0x03|0x40|0x80) +#define MABBIPG (0x04|0x40|0x80) +#define MAIPGL (0x06|0x40|0x80) +#define MAIPGH (0x07|0x40|0x80) +#define MACLCON1 (0x08|0x40|0x80) +#define MACLCON2 (0x09|0x40|0x80) +#define MAMXFLL (0x0A|0x40|0x80) +#define MAMXFLH (0x0B|0x40|0x80) +#define MAPHSUP (0x0D|0x40|0x80) +#define MICON (0x11|0x40|0x80) +#define MICMD (0x12|0x40|0x80) +#define MIREGADR (0x14|0x40|0x80) +#define MIWRL (0x16|0x40|0x80) +#define MIWRH (0x17|0x40|0x80) +#define MIRDL (0x18|0x40|0x80) +#define MIRDH (0x19|0x40|0x80) +// Bank 3 registers +#define MAADR1 (0x00|0x60|0x80) +#define MAADR0 (0x01|0x60|0x80) +#define MAADR3 (0x02|0x60|0x80) +#define MAADR2 (0x03|0x60|0x80) +#define MAADR5 (0x04|0x60|0x80) +#define MAADR4 (0x05|0x60|0x80) +#define EBSTSD (0x06|0x60) +#define EBSTCON (0x07|0x60) +#define EBSTCSL (0x08|0x60) +#define EBSTCSH (0x09|0x60) +#define MISTAT (0x0A|0x60|0x80) +#define EREVID (0x12|0x60) +#define ECOCON (0x15|0x60) +#define EFLOCON (0x17|0x60) +#define EPAUSL (0x18|0x60) +#define EPAUSH (0x19|0x60) +// PHY registers +#define PHCON1 0x00 +#define PHSTAT1 0x01 +#define PHHID1 0x02 +#define PHHID2 0x03 +#define PHCON2 0x10 +#define PHSTAT2 0x11 +#define PHIE 0x12 +#define PHIR 0x13 +#define PHLCON 0x14 + +// ENC28J60 ERXFCON Register Bit Definitions +#define ERXFCON_UCEN 0x80 +#define ERXFCON_ANDOR 0x40 +#define ERXFCON_CRCEN 0x20 +#define ERXFCON_PMEN 0x10 +#define ERXFCON_MPEN 0x08 +#define ERXFCON_HTEN 0x04 +#define ERXFCON_MCEN 0x02 +#define ERXFCON_BCEN 0x01 +// ENC28J60 EIE Register Bit Definitions +#define EIE_INTIE 0x80 +#define EIE_PKTIE 0x40 +#define EIE_DMAIE 0x20 +#define EIE_LINKIE 0x10 +#define EIE_TXIE 0x08 +#define EIE_WOLIE 0x04 +#define EIE_TXERIE 0x02 +#define EIE_RXERIE 0x01 +// ENC28J60 EIR Register Bit Definitions +#define EIR_PKTIF 0x40 +#define EIR_DMAIF 0x20 +#define EIR_LINKIF 0x10 +#define EIR_TXIF 0x08 +#define EIR_WOLIF 0x04 +#define EIR_TXERIF 0x02 +#define EIR_RXERIF 0x01 +// ENC28J60 ESTAT Register Bit Definitions +#define ESTAT_INT 0x80 +#define ESTAT_LATECOL 0x10 +#define ESTAT_RXBUSY 0x04 +#define ESTAT_TXABRT 0x02 +#define ESTAT_CLKRDY 0x01 +// ENC28J60 ECON2 Register Bit Definitions +#define ECON2_AUTOINC 0x80 +#define ECON2_PKTDEC 0x40 +#define ECON2_PWRSV 0x20 +#define ECON2_VRPS 0x08 +// ENC28J60 ECON1 Register Bit Definitions +#define ECON1_TXRST 0x80 +#define ECON1_RXRST 0x40 +#define ECON1_DMAST 0x20 +#define ECON1_CSUMEN 0x10 +#define ECON1_TXRTS 0x08 +#define ECON1_RXEN 0x04 +#define ECON1_BSEL1 0x02 +#define ECON1_BSEL0 0x01 +// ENC28J60 MACON1 Register Bit Definitions +#define MACON1_LOOPBK 0x10 +#define MACON1_TXPAUS 0x08 +#define MACON1_RXPAUS 0x04 +#define MACON1_PASSALL 0x02 +#define MACON1_MARXEN 0x01 +// ENC28J60 MACON2 Register Bit Definitions +#define MACON2_MARST 0x80 +#define MACON2_RNDRST 0x40 +#define MACON2_MARXRST 0x08 +#define MACON2_RFUNRST 0x04 +#define MACON2_MATXRST 0x02 +#define MACON2_TFUNRST 0x01 +// ENC28J60 MACON3 Register Bit Definitions +#define MACON3_PADCFG2 0x80 +#define MACON3_PADCFG1 0x40 +#define MACON3_PADCFG0 0x20 +#define MACON3_TXCRCEN 0x10 +#define MACON3_PHDRLEN 0x08 +#define MACON3_HFRMLEN 0x04 +#define MACON3_FRMLNEN 0x02 +#define MACON3_FULDPX 0x01 +// ENC28J60 MACON4 Register Bit Definitions +#define MACON4_DEFER (1<<6) +#define MACON4_BPEN (1<<5) +#define MACON4_NOBKOFF (1<<4) +// ENC28J60 MICMD Register Bit Definitions +#define MICMD_MIISCAN 0x02 +#define MICMD_MIIRD 0x01 +// ENC28J60 MISTAT Register Bit Definitions +#define MISTAT_NVALID 0x04 +#define MISTAT_SCAN 0x02 +#define MISTAT_BUSY 0x01 +// ENC28J60 PHY PHCON1 Register Bit Definitions +#define PHCON1_PRST 0x8000 +#define PHCON1_PLOOPBK 0x4000 +#define PHCON1_PPWRSV 0x0800 +#define PHCON1_PDPXMD 0x0100 +// ENC28J60 PHY PHSTAT1 Register Bit Definitions +#define PHSTAT1_PFDPX 0x1000 +#define PHSTAT1_PHDPX 0x0800 +#define PHSTAT1_LLSTAT 0x0004 +#define PHSTAT1_JBSTAT 0x0002 +/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */ +#define PHSTAT2_TXSTAT (1 << 13) +#define PHSTAT2_RXSTAT (1 << 12) +#define PHSTAT2_COLSTAT (1 << 11) +#define PHSTAT2_LSTAT (1 << 10) +#define PHSTAT2_DPXSTAT (1 << 9) +#define PHSTAT2_PLRITY (1 << 5) +// ENC28J60 PHY PHCON2 Register Bit Definitions +#define PHCON2_FRCLINK 0x4000 +#define PHCON2_TXDIS 0x2000 +#define PHCON2_JABBER 0x0400 +#define PHCON2_HDLDIS 0x0100 + +// ENC28J60 Packet Control Byte Bit Definitions +#define PKTCTRL_PHUGEEN 0x08 +#define PKTCTRL_PPADEN 0x04 +#define PKTCTRL_PCRCEN 0x02 +#define PKTCTRL_POVERRIDE 0x01 + +// SPI operation codes +#define ENC28J60_READ_CTRL_REG 0x00 +#define ENC28J60_READ_BUF_MEM 0x3A +#define ENC28J60_WRITE_CTRL_REG 0x40 +#define ENC28J60_WRITE_BUF_MEM 0x7A +#define ENC28J60_BIT_FIELD_SET 0x80 +#define ENC28J60_BIT_FIELD_CLR 0xA0 +#define ENC28J60_SOFT_RESET 0xFF + +// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata +// buffer boundaries applied to internal 8K ram +// the entire available packet buffer space is allocated +// + +// start with recbuf at 0/ +#define RXSTART_INIT 0x0 +// receive buffer end +#define RXSTOP_INIT (0x1FFF-0x0600) - 1 +// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) + +#define TXSTART_INIT (0x1FFF-0x0600) +// stp TX buffer at end of mem +#define TXSTOP_INIT 0x1FFF + +// max frame length which the conroller will accept: +#define MAX_FRAMELEN 1518 + +int rt_hw_enc28j60_init(void); + +#endif diff --git a/bsp/stm32/kbd.c b/bsp/stm32/kbd.c new file mode 100644 index 0000000000..ee9aee941f --- /dev/null +++ b/bsp/stm32/kbd.c @@ -0,0 +1,91 @@ +#include "kbd.h" +#include "stm32f10x_lib.h" + +#define GPIO_Pin_KB1 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 +#define GPIO_Pin_KB2 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_9 +#define GPIO_KB1 GPIOA +#define GPIO_KB2 GPIOB + +#define RCC_APB2Periph_GPIO_KB1 RCC_APB2Periph_GPIOA +#define RCC_APB2Periph_GPIO_KB2 RCC_APB2Periph_GPIOB + +#define EXTI_LINE_KB1 EXTI_Line0 | EXTI_Line1 | EXTI_Line2 | EXTI_Line3 +#define GPIO_PORT_SOURCE_KB1 GPIO_PortSourceGPIOA +#define EXTI_LINE_KB2 EXTI_Line0 | EXTI_Line1 | EXTI_Line9 +#define GPIO_PORT_SOURCE_KB2 GPIO_PortSourceGPIOB + +void rt_hw_kbd_init() +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Configure Key Button 1 GPIO Pin as input floating (Key Button EXTI Line) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_KB1; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIO_KB1, &GPIO_InitStructure); + + /* Configure Key Button 2 GPIO Pin as input floating (Key Button EXTI Line) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_KB2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIO_KB2, &GPIO_InitStructure); + + /* Enable Key Button GPIO Port clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_KB1 | RCC_APB2Periph_GPIO_KB2 | + RCC_APB2Periph_AFIO, ENABLE); + + /* Configure one bit for preemption priority */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + + /* Enable the EXTI9_5 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = EXTI2_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = EXTI3_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Connect Key Button EXTI Line to Key Button GPIO Pin */ + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB1, GPIO_PinSource0); + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB1, GPIO_PinSource1); + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB1, GPIO_PinSource2); + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB1, GPIO_PinSource3); + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB2, GPIO_PinSource0); + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB2, GPIO_PinSource1); + GPIO_EXTILineConfig(GPIO_PORT_SOURCE_KB2, GPIO_PinSource9); + + /* Configure Key Button EXTI Line to generate an interrupt on falling edge */ + EXTI_InitStructure.EXTI_Line = EXTI_LINE_KB1 | EXTI_LINE_KB2; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); +} + +void rt_hw_kbd_scan() +{ + /* KBD1 */ + + /* KBD2 */ +} diff --git a/bsp/stm32/kbd.h b/bsp/stm32/kbd.h new file mode 100644 index 0000000000..6bafa90071 --- /dev/null +++ b/bsp/stm32/kbd.h @@ -0,0 +1,7 @@ +#ifndef __KBD_H__ +#define __KBD_H__ + +#include +#include + +#endif diff --git a/bsp/stm32/lcd.c b/bsp/stm32/lcd.c new file mode 100644 index 0000000000..849cc2f160 --- /dev/null +++ b/bsp/stm32/lcd.c @@ -0,0 +1,487 @@ +#include "lcd.h" +#include "finsh.h" +#include "stm32f10x_lib.h" +#include "stm32f10x_rcc.h" + +#ifdef RT_USING_RTGUI + +#include +#include + +/* + * LCD Driver + * RGB mode (5-6-5) + * 240 x 320 pixel LCD + */ +/* convert rtgui color to hardware color, rgb 5-6-5 */ +typedef struct +{ + rt_uint16_t LCD_REG; + rt_uint16_t LCD_RAM; +} LCD_TypeDef; + +/* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */ +#define LCD_BASE ((rt_uint32_t)(0x60000000 | 0x0C000000)) +#define LCD ((LCD_TypeDef *) LCD_BASE) + +#define HW_COLOR_FROM(c) \ + (((RTGUI_RGB_R(c) >> 3) << 11) | \ + ((RTGUI_RGB_B(c) >> 2) << 5) | \ + ((RTGUI_RGB_B(c) >> 3) & 0x1f)) +#define HW_COLOR_TO(c) \ + ((c & 0x1f) * 255 / 31) | \ + (((c >> 5) & 0x3f) * 255 / 63) | \ + (((c >> 11) & 0x1f) * 255 / 31) + +#ifdef RT_USING_FRAMEBUFFER +rt_uint16_t _rt_hw_framebuffer[320 x 240]; +#endif + +/******************************************************************************* +* Function Name : LCD_WriteReg +* Description : Writes to the selected LCD register. +* Input : - LCD_Reg: address of the selected register. +* - LCD_RegValue: value to write to the selected register. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_WriteReg(rt_uint8_t LCD_Reg, rt_uint16_t LCD_RegValue) +{ + /* Write 16-bit Index, then Write Reg */ + LCD->LCD_REG = LCD_Reg; + /* Write 16-bit Reg */ + LCD->LCD_RAM = LCD_RegValue; +} + +/******************************************************************************* +* Function Name : LCD_ReadReg +* Description : Reads the selected LCD Register. +* Input : None +* Output : None +* Return : LCD Register Value. +*******************************************************************************/ +rt_uint16_t LCD_ReadReg(rt_uint8_t LCD_Reg) +{ + /* Write 16-bit Index (then Read Reg) */ + LCD->LCD_REG = LCD_Reg; + /* Read 16-bit Reg */ + return (LCD->LCD_RAM); +} + +/******************************************************************************* +* Function Name : LCD_WriteRAM_Prepare +* Description : Prepare to write to the LCD RAM. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_WriteRAM_Prepare(void) +{ + LCD->LCD_REG = R34; +} + +/******************************************************************************* +* Function Name : LCD_WriteRAM +* Description : Writes to the LCD RAM. +* Input : - RGB_Code: the pixel color in RGB mode (5-6-5). +* Output : None +* Return : None +*******************************************************************************/ +rt_inline void LCD_WriteRAM(rt_uint16_t RGB_Code) +{ + /* Write 16-bit GRAM Reg */ + LCD->LCD_RAM = RGB_Code; +} + +/******************************************************************************* +* Function Name : LCD_ReadRAM +* Description : Reads the LCD RAM. +* Input : None +* Output : None +* Return : LCD RAM Value. +*******************************************************************************/ +rt_inline rt_uint16_t LCD_ReadRAM(void) +{ + /* Write 16-bit Index (then Read Reg) */ + LCD->LCD_REG = R34; /* Select GRAM Reg */ + /* Read 16-bit Reg */ + return LCD->LCD_RAM; +} + +/******************************************************************************* +* Function Name : LCD_DisplayOn +* Description : Enables the Display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayOn(void) +{ + /* Display On */ + LCD_WriteReg(0x26, 0x3C); /* 262K color and display ON */ +} + +/******************************************************************************* +* Function Name : LCD_DisplayOff +* Description : Disables the Display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayOff(void) +{ + /* Display Off */ + LCD_WriteReg(0x26, 0x0); +} + +/******************************************************************************* +* Function Name : LCD_SetCursor +* Description : Sets the cursor position. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetCursor(rt_uint32_t x, rt_uint32_t y) +{ + LCD_WriteReg(0x06, (x & 0xff00) >> 8); + LCD_WriteReg(0x07, (x & 0x00ff)); + + LCD_WriteReg(0x02, (y & 0xff00) >> 8); + LCD_WriteReg(0x03, (y & 0x00ff)); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesConfig +* Description : Configures LCD Control lines (FSMC Pins) in alternate function + Push-Pull mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | + RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | + RCC_APB2Periph_AFIO, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + //±³¹â + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_ResetBits(GPIOA, GPIO_Pin_8); + //·äÃùÆ÷ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_SetBits(GPIOC, GPIO_Pin_6); + + /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14), + PD.10(D15), PD.14(D0), PD.15(D1) as alternate + function push pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | + GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10), + PE.14(D11), PE.15(D12) as alternate function push pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | + GPIO_Pin_15; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + // GPIO_WriteBit(GPIOE, GPIO_Pin_6, Bit_SET); + /* Set PF.00(A0 (RS)) as alternate function push pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_Init(GPIOG, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_FSMCConfig +* Description : Configures the Parallel interface (FSMC) for LCD(Parallel mode) +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_FSMCConfig(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + + /*-- FSMC Configuration ------------------------------------------------------*/ + /*----------------------- SRAM Bank 4 ----------------------------------------*/ + /* FSMC_Bank1_NORSRAM4 configuration */ + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 2; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + /* Color LCD configuration ------------------------------------ + LCD configured as follow: + - Data/Address MUX = Disable + - Memory Type = SRAM + - Data Width = 16bit + - Write Operation = Enable + - Extended Mode = Enable + - Asynchronous Wait = Disable */ + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + // FSMC_NORSRAMInitStructure.FSMC_AsyncWait = FSMC_AsyncWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /* BANK 4 (of NOR/SRAM Bank 1~4) is enabled */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); +} + +void rt_hw_lcd_update(rtgui_rect_t *rect) +{ + /* nothing */ +} + +rt_uint8_t * rt_hw_lcd_get_framebuffer(void) +{ +#ifdef RT_USING_FRAMEBUFFER + return (rt_uint8_t *)_rt_hw_framebuffer; +#else + return RT_NULL; +#endif +} + +void rt_hw_lcd_set_pixel(rtgui_color_t *c, rt_base_t x, rt_base_t y) +{ + LCD_SetCursor(x, 319 - y); + + /* Prepare to write GRAM */ + LCD_WriteRAM_Prepare(); + LCD_WriteRAM(HW_COLOR_FROM(*c)); +} + +void rt_hw_lcd_get_pixel(rtgui_color_t *c, rt_base_t x, rt_base_t y) +{ + rt_uint16_t hc; + + LCD_SetCursor(x, 319 - y); + hc = LCD_ReadRAM(); + *c = HW_COLOR_TO(hc); +} + +void rt_hw_lcd_draw_hline(rtgui_color_t *c, rt_base_t x1, rt_base_t x2, rt_base_t y) +{ + rt_uint32_t index; + rt_uint16_t hc; + + hc = HW_COLOR_FROM(*c); + + for (index = x1; index < x2; index ++) + { + LCD_SetCursor(index, 319 - y); + + /* Prepare to write GRAM */ + LCD_WriteRAM_Prepare(); + LCD_WriteRAM(hc); + } +} + +void rt_hw_lcd_draw_vline(rtgui_color_t *c, rt_base_t x, rt_base_t y1, rt_base_t y2) +{ + rt_uint32_t index; + rt_uint16_t hc; + + hc = HW_COLOR_FROM(*c); + + for (index = y1; index < y2; index ++) + { + LCD_SetCursor(x, 319 - index); + + /* Prepare to write GRAM */ + LCD_WriteRAM_Prepare(); + LCD_WriteRAM(hc); + } +} + +struct rtgui_graphic_driver _rtgui_lcd_driver = +{ + "lcd", + 2, + 240, + 320, + rt_hw_lcd_update, + rt_hw_lcd_get_framebuffer, + rt_hw_lcd_set_pixel, + rt_hw_lcd_get_pixel, + rt_hw_lcd_draw_hline, + rt_hw_lcd_draw_vline +}; + +#define Delay(v) \ + { \ + volatile rt_uint32_t index; \ + for (index = 0; index < v * 100; index ++) \ + ; \ + } + +void rt_hw_lcd_init() +{ + /* Configure the LCD Control pins --------------------------------------------*/ + LCD_CtrlLinesConfig(); + + /* Configure the FSMC Parallel interface -------------------------------------*/ + LCD_FSMCConfig(); + + Delay(5); /* delay 50 ms */ + // Gamma for CMO 3.2¡± + LCD_WriteReg(0x46,0x94); + LCD_WriteReg(0x47,0x41); + LCD_WriteReg(0x48,0x00); + LCD_WriteReg(0x49,0x33); + LCD_WriteReg(0x4a,0x23); + LCD_WriteReg(0x4b,0x45); + LCD_WriteReg(0x4c,0x44); + LCD_WriteReg(0x4d,0x77); + LCD_WriteReg(0x4e,0x12); + LCD_WriteReg(0x4f,0xcc); + LCD_WriteReg(0x50,0x46); + LCD_WriteReg(0x51,0x82); + + //240x320 window setting + LCD_WriteReg(0x02,0x00); + LCD_WriteReg(0x03,0x00); + LCD_WriteReg(0x04,0x01); + LCD_WriteReg(0x05,0x3f); + LCD_WriteReg(0x06,0x00); + LCD_WriteReg(0x07,0x00); + LCD_WriteReg(0x08,0x00); + LCD_WriteReg(0x09,0xef); + + // Display Setting + LCD_WriteReg(0x01,0x06); + LCD_WriteReg(0x16,0x68); + LCD_WriteReg(0x23,0x95); + LCD_WriteReg(0x24,0x95); + LCD_WriteReg(0x25,0xff); + + LCD_WriteReg(0x27,0x02); + LCD_WriteReg(0x28,0x02); + LCD_WriteReg(0x29,0x02); + LCD_WriteReg(0x2a,0x02); + LCD_WriteReg(0x2c,0x02); + LCD_WriteReg(0x2d,0x02); + + LCD_WriteReg(0x3a,0x01);///******************* + LCD_WriteReg(0x3b,0x01); + LCD_WriteReg(0x3c,0xf0); + LCD_WriteReg(0x3d,0x00); + + Delay(2); + + LCD_WriteReg(0x35,0x38); + LCD_WriteReg(0x36,0x78); + + LCD_WriteReg(0x3e,0x38); + + LCD_WriteReg(0x40,0x0f); + LCD_WriteReg(0x41,0xf0); + + // Power Supply Setting + LCD_WriteReg(0x19,0x49);//******** + LCD_WriteReg(0x93,0x0f);//******* + + Delay(1); + + LCD_WriteReg(0x20,0x30); + LCD_WriteReg(0x1d,0x07); + LCD_WriteReg(0x1e,0x00); + LCD_WriteReg(0x1f,0x07); + + // VCOM Setting for CMO 3.2¡± Panel + LCD_WriteReg(0x44,0x4d);//4d***************4f + LCD_WriteReg(0x45,0x13);//0x0a); + Delay(1); + LCD_WriteReg(0x1c,0x04); + Delay(2); + LCD_WriteReg(0x43,0x80); + Delay(5); + LCD_WriteReg(0x1b,0x08); + Delay(4); + LCD_WriteReg(0x1b,0x10); + Delay(4); + + // Display ON Setting + LCD_WriteReg(0x90,0x7f); + LCD_WriteReg(0x26,0x04); + Delay(4); + LCD_WriteReg(0x26,0x24); + LCD_WriteReg(0x26,0x2c); + Delay(4); + LCD_WriteReg(0x26,0x3c); + + // Set internal VDDD voltage + LCD_WriteReg(0x57,0x02); + LCD_WriteReg(0x55,0x00); + LCD_WriteReg(0x57,0x00); + + /* add lcd driver into graphic driver */ + rtgui_list_init(&_rtgui_lcd_driver.list); + rtgui_graphic_driver_add(&_rtgui_lcd_driver); +} + +void hline(rt_uint32_t c, rt_base_t x1, rt_base_t x2, rt_base_t y) +{ + rtgui_color_t color = (rtgui_color_t)c; + rt_hw_lcd_draw_hline(&color, x1, x2, y); +} +FINSH_FUNCTION_EXPORT(hline, Horizontal Line) + +void vline(rt_uint32_t c, rt_base_t x, rt_base_t y1, rt_base_t y2) +{ + rtgui_color_t color = (rtgui_color_t)c; + rt_hw_lcd_draw_vline(&color, x, y1, y2); +} +FINSH_FUNCTION_EXPORT(vline, Vertical Line) +FINSH_FUNCTION_EXPORT(rt_hw_lcd_init, LCD Init) + +void clear() +{ + rt_uint32_t index; +#if 0 + for (index = 0; index < 320; index ++) + { + rt_hw_lcd_draw_hline((rtgui_color_t*)&white, 0, 240, index); + } +#else + for (index = 0; index < 240; index ++) + { + rt_hw_lcd_draw_vline((rtgui_color_t*)&white, index, 0, 320); + } +#endif +} +FINSH_FUNCTION_EXPORT(clear, clear screen) + +#endif diff --git a/bsp/stm32/lcd.h b/bsp/stm32/lcd.h new file mode 100644 index 0000000000..72cc1211a7 --- /dev/null +++ b/bsp/stm32/lcd.h @@ -0,0 +1,148 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include +#include + +/* LCD Registers */ +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R4 0x04 +#define R5 0x05 +#define R6 0x06 +#define R7 0x07 +#define R8 0x08 +#define R9 0x09 +#define R10 0x0A +#define R12 0x0C +#define R13 0x0D +#define R14 0x0E +#define R15 0x0F +#define R16 0x10 +#define R17 0x11 +#define R18 0x12 +#define R19 0x13 +#define R20 0x14 +#define R21 0x15 +#define R22 0x16 +#define R23 0x17 +#define R24 0x18 +#define R25 0x19 +#define R26 0x1A +#define R27 0x1B +#define R28 0x1C +#define R29 0x1D +#define R30 0x1E +#define R31 0x1F +#define R32 0x20 +#define R33 0x21 +#define R34 0x22 +#define R36 0x24 +#define R37 0x25 +#define R40 0x28 +#define R41 0x29 +#define R43 0x2B +#define R45 0x2D +#define R48 0x30 +#define R49 0x31 +#define R50 0x32 +#define R51 0x33 +#define R52 0x34 +#define R53 0x35 +#define R54 0x36 +#define R55 0x37 +#define R56 0x38 +#define R57 0x39 +#define R59 0x3B +#define R60 0x3C +#define R61 0x3D +#define R62 0x3E +#define R63 0x3F +#define R64 0x40 +#define R65 0x41 +#define R66 0x42 +#define R67 0x43 +#define R68 0x44 +#define R69 0x45 +#define R70 0x46 +#define R71 0x47 +#define R72 0x48 +#define R73 0x49 +#define R74 0x4A +#define R75 0x4B +#define R76 0x4C +#define R77 0x4D +#define R78 0x4E +#define R79 0x4F +#define R80 0x50 +#define R81 0x51 +#define R82 0x52 +#define R83 0x53 +#define R96 0x60 +#define R97 0x61 +#define R106 0x6A +#define R118 0x76 +#define R128 0x80 +#define R129 0x81 +#define R130 0x82 +#define R131 0x83 +#define R132 0x84 +#define R133 0x85 +#define R134 0x86 +#define R135 0x87 +#define R136 0x88 +#define R137 0x89 +#define R139 0x8B +#define R140 0x8C +#define R141 0x8D +#define R143 0x8F +#define R144 0x90 +#define R145 0x91 +#define R146 0x92 +#define R147 0x93 +#define R148 0x94 +#define R149 0x95 +#define R150 0x96 +#define R151 0x97 +#define R152 0x98 +#define R153 0x99 +#define R154 0x9A +#define R157 0x9D +#define R192 0xC0 +#define R193 0xC1 +#define R229 0xE5 + +/* LCD Control pins */ +#define CtrlPin_NCS GPIO_Pin_2 /* PB.02 */ +#define CtrlPin_RS GPIO_Pin_7 /* PD.07 */ +#define CtrlPin_NWR GPIO_Pin_15 /* PD.15 */ + +/* LCD color */ +#define White 0xFFFF +#define Black 0x0000 +#define Grey 0xF7DE +#define Blue 0x001F +#define Blue2 0x051F +#define Red 0xF800 +#define Magenta 0xF81F +#define Green 0x07E0 +#define Cyan 0x7FFF +#define Yellow 0xFFE0 + +#define Line0 0 +#define Line1 24 +#define Line2 48 +#define Line3 72 +#define Line4 96 +#define Line5 120 +#define Line6 144 +#define Line7 168 +#define Line8 192 +#define Line9 216 + +#define Horizontal 0x00 +#define Vertical 0x01 + +#endif diff --git a/bsp/stm32/library/inc/cortexm3_macro.h b/bsp/stm32/library/inc/cortexm3_macro.h new file mode 100644 index 0000000000..b26807f924 --- /dev/null +++ b/bsp/stm32/library/inc/cortexm3_macro.h @@ -0,0 +1,53 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +u32 __MRS_PSP(void); +void __MSR_PSP(u32 TopOfProcessStack); +u32 __MRS_MSP(void); +void __MSR_MSP(u32 TopOfMainStack); +void __RESETPRIMASK(void); +void __SETPRIMASK(void); +u32 __READ_PRIMASK(void); +void __RESETFAULTMASK(void); +void __SETFAULTMASK(void); +u32 __READ_FAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_adc.h b/bsp/stm32/library/inc/stm32f10x_adc.h new file mode 100644 index 0000000000..b68716023c --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_adc.h @@ -0,0 +1,300 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_adc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ADC Init structure definition */ +typedef struct +{ + u32 ADC_Mode; + FunctionalState ADC_ScanConvMode; + FunctionalState ADC_ContinuousConvMode; + u32 ADC_ExternalTrigConv; + u32 ADC_DataAlign; + u8 ADC_NbrOfChannel; +}ADC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \ + ((*(u32*)&(PERIPH)) == ADC2_BASE) || \ + ((*(u32*)&(PERIPH)) == ADC3_BASE)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \ + ((*(u32*)&(PERIPH)) == ADC3_BASE)) + +/* ADC dual mode -------------------------------------------------------------*/ +#define ADC_Mode_Independent ((u32)0x00000000) +#define ADC_Mode_RegInjecSimult ((u32)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000) +#define ADC_Mode_InjecSimult ((u32)0x00050000) +#define ADC_Mode_RegSimult ((u32)0x00060000) +#define ADC_Mode_FastInterl ((u32)0x00070000) +#define ADC_Mode_SlowInterl ((u32)0x00080000) +#define ADC_Mode_AlterTrig ((u32)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) + +/* ADC extrenal trigger sources for regular channels conversion --------------*/ +/* for ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000) +/* for ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000) +#define ADC_ExternalTrigConv_None ((u32)0x000E0000) +/* for ADC3 */ +#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000) + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) + +/* ADC data align ------------------------------------------------------------*/ +#define ADC_DataAlign_Right ((u32)0x00000000) +#define ADC_DataAlign_Left ((u32)0x00000800) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) + +/* ADC channels --------------------------------------------------------------*/ +#define ADC_Channel_0 ((u8)0x00) +#define ADC_Channel_1 ((u8)0x01) +#define ADC_Channel_2 ((u8)0x02) +#define ADC_Channel_3 ((u8)0x03) +#define ADC_Channel_4 ((u8)0x04) +#define ADC_Channel_5 ((u8)0x05) +#define ADC_Channel_6 ((u8)0x06) +#define ADC_Channel_7 ((u8)0x07) +#define ADC_Channel_8 ((u8)0x08) +#define ADC_Channel_9 ((u8)0x09) +#define ADC_Channel_10 ((u8)0x0A) +#define ADC_Channel_11 ((u8)0x0B) +#define ADC_Channel_12 ((u8)0x0C) +#define ADC_Channel_13 ((u8)0x0D) +#define ADC_Channel_14 ((u8)0x0E) +#define ADC_Channel_15 ((u8)0x0F) +#define ADC_Channel_16 ((u8)0x10) +#define ADC_Channel_17 ((u8)0x11) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) + +/* ADC sampling times --------------------------------------------------------*/ +#define ADC_SampleTime_1Cycles5 ((u8)0x00) +#define ADC_SampleTime_7Cycles5 ((u8)0x01) +#define ADC_SampleTime_13Cycles5 ((u8)0x02) +#define ADC_SampleTime_28Cycles5 ((u8)0x03) +#define ADC_SampleTime_41Cycles5 ((u8)0x04) +#define ADC_SampleTime_55Cycles5 ((u8)0x05) +#define ADC_SampleTime_71Cycles5 ((u8)0x06) +#define ADC_SampleTime_239Cycles5 ((u8)0x07) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) + +/* ADC extrenal trigger sources for injected channels conversion -------------*/ +/* For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000) +/* For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000) +/* For ADC3 */ +#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000) + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) + +/* ADC injected channel selection --------------------------------------------*/ +#define ADC_InjectedChannel_1 ((u8)0x14) +#define ADC_InjectedChannel_2 ((u8)0x18) +#define ADC_InjectedChannel_3 ((u8)0x1C) +#define ADC_InjectedChannel_4 ((u8)0x20) + +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) + +/* ADC analog watchdog selection ---------------------------------------------*/ +#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000) +#define ADC_AnalogWatchdog_None ((u32)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) + +/* ADC interrupts definition -------------------------------------------------*/ +#define ADC_IT_EOC ((u16)0x0220) +#define ADC_IT_AWD ((u16)0x0140) +#define ADC_IT_JEOC ((u16)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00)) +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) + +/* ADC flags definition ------------------------------------------------------*/ +#define ADC_FLAG_AWD ((u8)0x01) +#define ADC_FLAG_EOC ((u8)0x02) +#define ADC_FLAG_JEOC ((u8)0x04) +#define ADC_FLAG_JSTRT ((u8)0x08) +#define ADC_FLAG_STRT ((u8)0x10) + +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) + +/* ADC thresholds ------------------------------------------------------------*/ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/* ADC injected offset -------------------------------------------------------*/ +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/* ADC injected length -------------------------------------------------------*/ +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/* ADC injected rank ---------------------------------------------------------*/ +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/* ADC regular length --------------------------------------------------------*/ +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) + +/* ADC regular rank ----------------------------------------------------------*/ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/* ADC regular discontinuous mode number -------------------------------------*/ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +u16 ADC_GetConversionValue(ADC_TypeDef* ADCx); +u32 ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset); +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT); + +#endif /*__STM32F10x_ADC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_bkp.h b/bsp/stm32/library/inc/stm32f10x_bkp.h new file mode 100644 index 0000000000..5fe02009ad --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_bkp.h @@ -0,0 +1,122 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_bkp.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Tamper Pin active level */ +#define BKP_TamperPinLevel_High ((u16)0x0000) +#define BKP_TamperPinLevel_Low ((u16)0x0001) + +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) + +/* RTC output source to output on the Tamper pin */ +#define BKP_RTCOutputSource_None ((u16)0x0000) +#define BKP_RTCOutputSource_CalibClock ((u16)0x0080) +#define BKP_RTCOutputSource_Alarm ((u16)0x0100) +#define BKP_RTCOutputSource_Second ((u16)0x0300) + +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) + +/* Data Backup Register */ +#define BKP_DR1 ((u16)0x0004) +#define BKP_DR2 ((u16)0x0008) +#define BKP_DR3 ((u16)0x000C) +#define BKP_DR4 ((u16)0x0010) +#define BKP_DR5 ((u16)0x0014) +#define BKP_DR6 ((u16)0x0018) +#define BKP_DR7 ((u16)0x001C) +#define BKP_DR8 ((u16)0x0020) +#define BKP_DR9 ((u16)0x0024) +#define BKP_DR10 ((u16)0x0028) +#define BKP_DR11 ((u16)0x0040) +#define BKP_DR12 ((u16)0x0044) +#define BKP_DR13 ((u16)0x0048) +#define BKP_DR14 ((u16)0x004C) +#define BKP_DR15 ((u16)0x0050) +#define BKP_DR16 ((u16)0x0054) +#define BKP_DR17 ((u16)0x0058) +#define BKP_DR18 ((u16)0x005C) +#define BKP_DR19 ((u16)0x0060) +#define BKP_DR20 ((u16)0x0064) +#define BKP_DR21 ((u16)0x0068) +#define BKP_DR22 ((u16)0x006C) +#define BKP_DR23 ((u16)0x0070) +#define BKP_DR24 ((u16)0x0074) +#define BKP_DR25 ((u16)0x0078) +#define BKP_DR26 ((u16)0x007C) +#define BKP_DR27 ((u16)0x0080) +#define BKP_DR28 ((u16)0x0084) +#define BKP_DR29 ((u16)0x0088) +#define BKP_DR30 ((u16)0x008C) +#define BKP_DR31 ((u16)0x0090) +#define BKP_DR32 ((u16)0x0094) +#define BKP_DR33 ((u16)0x0098) +#define BKP_DR34 ((u16)0x009C) +#define BKP_DR35 ((u16)0x00A0) +#define BKP_DR36 ((u16)0x00A4) +#define BKP_DR37 ((u16)0x00A8) +#define BKP_DR38 ((u16)0x00AC) +#define BKP_DR39 ((u16)0x00B0) +#define BKP_DR40 ((u16)0x00B4) +#define BKP_DR41 ((u16)0x00B8) +#define BKP_DR42 ((u16)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(u8 CalibrationValue); +void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data); +u16 BKP_ReadBackupRegister(u16 BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#endif /* __STM32F10x_BKP_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_can.h b/bsp/stm32/library/inc/stm32f10x_can.h new file mode 100644 index 0000000000..bb99109ae8 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_can.h @@ -0,0 +1,263 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_can.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* CAN init structure definition */ +typedef struct +{ + FunctionalState CAN_TTCM; + FunctionalState CAN_ABOM; + FunctionalState CAN_AWUM; + FunctionalState CAN_NART; + FunctionalState CAN_RFLM; + FunctionalState CAN_TXFP; + u8 CAN_Mode; + u8 CAN_SJW; + u8 CAN_BS1; + u8 CAN_BS2; + u16 CAN_Prescaler; +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + u8 CAN_FilterNumber; + u8 CAN_FilterMode; + u8 CAN_FilterScale; + u16 CAN_FilterIdHigh; + u16 CAN_FilterIdLow; + u16 CAN_FilterMaskIdHigh; + u16 CAN_FilterMaskIdLow; + u16 CAN_FilterFIFOAssignment; + FunctionalState CAN_FilterActivation; +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + u32 StdId; + u32 ExtId; + u8 IDE; + u8 RTR; + u8 DLC; + u8 Data[8]; +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + u32 StdId; + u32 ExtId; + u8 IDE; + u8 RTR; + u8 DLC; + u8 Data[8]; + u8 FMI; +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/* CAN sleep constants */ +#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */ +#define CANINITOK ((u8)0x01) /* CAN initialization failed */ + +/* CAN operating mode */ +#define CAN_Mode_Normal ((u8)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((u8)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) + +/* CAN synchronisation jump width */ +#define CAN_SJW_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((u8)0x03) /* 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) + +/* time quantum in bit segment 1 */ +#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) + +/* time quantum in bit segment 2 */ +#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/* CAN clock prescaler */ +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/* CAN filter number */ +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) + +/* CAN filter mode */ +#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */ +#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) + +/* CAN filter scale */ +#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */ +#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/* CAN filter FIFO assignation */ +#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */ + +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/* CAN Tx */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((u8)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((u32)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((u32)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((u8)0x08)) + +/* CAN identifier type */ +#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */ +#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */ + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) + +/* CAN remote transmission request */ +#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */ +#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */ + +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +/* CAN transmit constants */ +#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */ +#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */ +#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */ +#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN receive FIFO number constants */ +#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/* CAN sleep constants */ +#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */ +#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */ + +/* CAN wake up constants */ +#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */ + +/* CAN flags */ +#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */ + +#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\ + ((FLAG) == CAN_FLAG_BOF)) + +/* CAN interrupts */ +#define CAN_IT_RQCP0 ((u32)0x00000005) /* Request completed mailbox 0 */ +#define CAN_IT_RQCP1 ((u32)0x00000006) /* Request completed mailbox 1 */ +#define CAN_IT_RQCP2 ((u32)0x00000007) /* Request completed mailbox 2 */ +#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */ +#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */ +#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */ +#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */ +#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */ +#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */ +#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */ +#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */ +#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */ +#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */ +#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */ +#define CAN_IT_ERR ((u32)0x00008000) /* Error */ +#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */ +#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */ + +#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\ + ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported function protypes ----------------------------------------------- */ +void CAN_DeInit(void); +u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState); +u8 CAN_Transmit(CanTxMsg* TxMessage); +u8 CAN_TransmitStatus(u8 TransmitMailbox); +void CAN_CancelTransmit(u8 Mailbox); +void CAN_FIFORelease(u8 FIFONumber); +u8 CAN_MessagePending(u8 FIFONumber); +void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage); +u8 CAN_Sleep(void); +u8 CAN_WakeUp(void); +FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG); +void CAN_ClearFlag(u32 CAN_FLAG); +ITStatus CAN_GetITStatus(u32 CAN_IT); +void CAN_ClearITPendingBit(u32 CAN_IT); + +#endif /* __STM32F10x_CAN_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_crc.h b/bsp/stm32/library/inc/stm32f10x_crc.h new file mode 100644 index 0000000000..14f6ec54c7 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_crc.h @@ -0,0 +1,37 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_crc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* CRC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void CRC_ResetDR(void); +u32 CRC_CalcCRC(u32 Data); +u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength); +u32 CRC_GetCRC(void); +void CRC_SetIDRegister(u8 IDValue); +u8 CRC_GetIDRegister(void); + +#endif /* __STM32F10x_CRC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_dac.h b/bsp/stm32/library/inc/stm32f10x_dac.h new file mode 100644 index 0000000000..8f0f844a3f --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_dac.h @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dac.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* DAC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DAC Init structure definition */ +typedef struct +{ + u32 DAC_Trigger; + u32 DAC_WaveGeneration; + u32 DAC_LFSRUnmask_TriangleAmplitude; + u32 DAC_OutputBuffer; +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DAC trigger selection */ +#define DAC_Trigger_None ((u32)0x00000000) +#define DAC_Trigger_T6_TRGO ((u32)0x00000004) +#define DAC_Trigger_T8_TRGO ((u32)0x0000000C) +#define DAC_Trigger_T7_TRGO ((u32)0x00000014) +#define DAC_Trigger_T5_TRGO ((u32)0x0000001C) +#define DAC_Trigger_T2_TRGO ((u32)0x00000024) +#define DAC_Trigger_T4_TRGO ((u32)0x0000002C) +#define DAC_Trigger_Ext_IT9 ((u32)0x00000034) +#define DAC_Trigger_Software ((u32)0x0000003C) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/* DAC wave generation */ +#define DAC_WaveGeneration_None ((u32)0x00000000) +#define DAC_WaveGeneration_Noise ((u32)0x00000040) +#define DAC_WaveGeneration_Triangle ((u32)0x00000080) + +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) + +/* DAC noise wave generation mask / triangle wave generation max amplitude */ +#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000) +#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100) +#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200) +#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300) +#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400) +#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500) +#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600) +#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700) +#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800) +#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900) +#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00) +#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00) + +#define DAC_TriangleAmplitude_1 ((u32)0x00000000) +#define DAC_TriangleAmplitude_3 ((u32)0x00000100) +#define DAC_TriangleAmplitude_7 ((u32)0x00000200) +#define DAC_TriangleAmplitude_15 ((u32)0x00000300) +#define DAC_TriangleAmplitude_31 ((u32)0x00000400) +#define DAC_TriangleAmplitude_63 ((u32)0x00000500) +#define DAC_TriangleAmplitude_127 ((u32)0x00000600) +#define DAC_TriangleAmplitude_255 ((u32)0x00000700) +#define DAC_TriangleAmplitude_511 ((u32)0x00000800) +#define DAC_TriangleAmplitude_1023 ((u32)0x00000900) +#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00) +#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00) + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) + +/* DAC output buffer */ +#define DAC_OutputBuffer_Enable ((u32)0x00000000) +#define DAC_OutputBuffer_Disable ((u32)0x00000002) + +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) + +/* DAC Channel selection */ +#define DAC_Channel_1 ((u32)0x00000000) +#define DAC_Channel_2 ((u32)0x00000010) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) + +/* DAC data alignement */ +#define DAC_Align_12b_R ((u32)0x00000000) +#define DAC_Align_12b_L ((u32)0x00000004) +#define DAC_Align_8b_R ((u32)0x00000008) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) + +/* DAC wave generation */ +#define DAC_Wave_Noise ((u32)0x00000040) +#define DAC_Wave_Triangle ((u32)0x00000080) + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) + +/* DAC data ------------------------------------------------------------------*/ +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void DAC_DeInit(void); +void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(u32 DAC_Align, u16 Data); +void DAC_SetChannel2Data(u32 DAC_Align, u16 Data); +void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1); +u16 DAC_GetDataOutputValue(u32 DAC_Channel); + +#endif /*__STM32F10x_DAC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_dbgmcu.h b/bsp/stm32/library/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000000..bd74964e3f --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,55 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_dbgmcu.h +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file contains all the functions prototypes for the +* DBGMCU firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define DBGMCU_SLEEP ((u32)0x00000001) +#define DBGMCU_STOP ((u32)0x00000002) +#define DBGMCU_STANDBY ((u32)0x00000004) +#define DBGMCU_IWDG_STOP ((u32)0x00000100) +#define DBGMCU_WWDG_STOP ((u32)0x00000200) +#define DBGMCU_TIM1_STOP ((u32)0x00000400) +#define DBGMCU_TIM2_STOP ((u32)0x00000800) +#define DBGMCU_TIM3_STOP ((u32)0x00001000) +#define DBGMCU_TIM4_STOP ((u32)0x00002000) +#define DBGMCU_CAN_STOP ((u32)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) +#define DBGMCU_TIM8_STOP ((u32)0x00020000) +#define DBGMCU_TIM5_STOP ((u32)0x00040000) +#define DBGMCU_TIM6_STOP ((u32)0x00080000) +#define DBGMCU_TIM7_STOP ((u32)0x00100000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +u32 DBGMCU_GetREVID(void); +u32 DBGMCU_GetDEVID(void); +void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState); + +#endif /* __STM32F10x_DBGMCU_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ + + diff --git a/bsp/stm32/library/inc/stm32f10x_dma.h b/bsp/stm32/library/inc/stm32f10x_dma.h new file mode 100644 index 0000000000..e18b3e9639 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_dma.h @@ -0,0 +1,297 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dma.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_PeripheralBaseAddr; + u32 DMA_MemoryBaseAddr; + u32 DMA_DIR; + u32 DMA_BufferSize; + u32 DMA_PeripheralInc; + u32 DMA_MemoryInc; + u32 DMA_PeripheralDataSize; + u32 DMA_MemoryDataSize; + u32 DMA_Mode; + u32 DMA_Priority; + u32 DMA_M2M; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \ + ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE)) + +/* DMA data transfer direction -----------------------------------------------*/ +#define DMA_DIR_PeripheralDST ((u32)0x00000010) +#define DMA_DIR_PeripheralSRC ((u32)0x00000000) + +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) + +/* DMA peripheral incremented mode -------------------------------------------*/ +#define DMA_PeripheralInc_Enable ((u32)0x00000040) +#define DMA_PeripheralInc_Disable ((u32)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) + +/* DMA memory incremented mode -----------------------------------------------*/ +#define DMA_MemoryInc_Enable ((u32)0x00000080) +#define DMA_MemoryInc_Disable ((u32)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) + +/* DMA peripheral data size --------------------------------------------------*/ +#define DMA_PeripheralDataSize_Byte ((u32)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100) +#define DMA_PeripheralDataSize_Word ((u32)0x00000200) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) + +/* DMA memory data size ------------------------------------------------------*/ +#define DMA_MemoryDataSize_Byte ((u32)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400) +#define DMA_MemoryDataSize_Word ((u32)0x00000800) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) + +/* DMA circular/normal mode --------------------------------------------------*/ +#define DMA_Mode_Circular ((u32)0x00000020) +#define DMA_Mode_Normal ((u32)0x00000000) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) + +/* DMA priority level --------------------------------------------------------*/ +#define DMA_Priority_VeryHigh ((u32)0x00003000) +#define DMA_Priority_High ((u32)0x00002000) +#define DMA_Priority_Medium ((u32)0x00001000) +#define DMA_Priority_Low ((u32)0x00000000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) + +/* DMA memory to memory ------------------------------------------------------*/ +#define DMA_M2M_Enable ((u32)0x00004000) +#define DMA_M2M_Disable ((u32)0x00000000) + +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/* DMA interrupts definition -------------------------------------------------*/ +#define DMA_IT_TC ((u32)0x00000002) +#define DMA_IT_HT ((u32)0x00000004) +#define DMA_IT_TE ((u32)0x00000008) + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +/* For DMA1 */ +#define DMA1_IT_GL1 ((u32)0x00000001) +#define DMA1_IT_TC1 ((u32)0x00000002) +#define DMA1_IT_HT1 ((u32)0x00000004) +#define DMA1_IT_TE1 ((u32)0x00000008) +#define DMA1_IT_GL2 ((u32)0x00000010) +#define DMA1_IT_TC2 ((u32)0x00000020) +#define DMA1_IT_HT2 ((u32)0x00000040) +#define DMA1_IT_TE2 ((u32)0x00000080) +#define DMA1_IT_GL3 ((u32)0x00000100) +#define DMA1_IT_TC3 ((u32)0x00000200) +#define DMA1_IT_HT3 ((u32)0x00000400) +#define DMA1_IT_TE3 ((u32)0x00000800) +#define DMA1_IT_GL4 ((u32)0x00001000) +#define DMA1_IT_TC4 ((u32)0x00002000) +#define DMA1_IT_HT4 ((u32)0x00004000) +#define DMA1_IT_TE4 ((u32)0x00008000) +#define DMA1_IT_GL5 ((u32)0x00010000) +#define DMA1_IT_TC5 ((u32)0x00020000) +#define DMA1_IT_HT5 ((u32)0x00040000) +#define DMA1_IT_TE5 ((u32)0x00080000) +#define DMA1_IT_GL6 ((u32)0x00100000) +#define DMA1_IT_TC6 ((u32)0x00200000) +#define DMA1_IT_HT6 ((u32)0x00400000) +#define DMA1_IT_TE6 ((u32)0x00800000) +#define DMA1_IT_GL7 ((u32)0x01000000) +#define DMA1_IT_TC7 ((u32)0x02000000) +#define DMA1_IT_HT7 ((u32)0x04000000) +#define DMA1_IT_TE7 ((u32)0x08000000) +/* For DMA2 */ +#define DMA2_IT_GL1 ((u32)0x10000001) +#define DMA2_IT_TC1 ((u32)0x10000002) +#define DMA2_IT_HT1 ((u32)0x10000004) +#define DMA2_IT_TE1 ((u32)0x10000008) +#define DMA2_IT_GL2 ((u32)0x10000010) +#define DMA2_IT_TC2 ((u32)0x10000020) +#define DMA2_IT_HT2 ((u32)0x10000040) +#define DMA2_IT_TE2 ((u32)0x10000080) +#define DMA2_IT_GL3 ((u32)0x10000100) +#define DMA2_IT_TC3 ((u32)0x10000200) +#define DMA2_IT_HT3 ((u32)0x10000400) +#define DMA2_IT_TE3 ((u32)0x10000800) +#define DMA2_IT_GL4 ((u32)0x10001000) +#define DMA2_IT_TC4 ((u32)0x10002000) +#define DMA2_IT_HT4 ((u32)0x10004000) +#define DMA2_IT_TE4 ((u32)0x10008000) +#define DMA2_IT_GL5 ((u32)0x10010000) +#define DMA2_IT_TC5 ((u32)0x10020000) +#define DMA2_IT_HT5 ((u32)0x10040000) +#define DMA2_IT_TE5 ((u32)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/* DMA flags definition ------------------------------------------------------*/ +/* For DMA1 */ +#define DMA1_FLAG_GL1 ((u32)0x00000001) +#define DMA1_FLAG_TC1 ((u32)0x00000002) +#define DMA1_FLAG_HT1 ((u32)0x00000004) +#define DMA1_FLAG_TE1 ((u32)0x00000008) +#define DMA1_FLAG_GL2 ((u32)0x00000010) +#define DMA1_FLAG_TC2 ((u32)0x00000020) +#define DMA1_FLAG_HT2 ((u32)0x00000040) +#define DMA1_FLAG_TE2 ((u32)0x00000080) +#define DMA1_FLAG_GL3 ((u32)0x00000100) +#define DMA1_FLAG_TC3 ((u32)0x00000200) +#define DMA1_FLAG_HT3 ((u32)0x00000400) +#define DMA1_FLAG_TE3 ((u32)0x00000800) +#define DMA1_FLAG_GL4 ((u32)0x00001000) +#define DMA1_FLAG_TC4 ((u32)0x00002000) +#define DMA1_FLAG_HT4 ((u32)0x00004000) +#define DMA1_FLAG_TE4 ((u32)0x00008000) +#define DMA1_FLAG_GL5 ((u32)0x00010000) +#define DMA1_FLAG_TC5 ((u32)0x00020000) +#define DMA1_FLAG_HT5 ((u32)0x00040000) +#define DMA1_FLAG_TE5 ((u32)0x00080000) +#define DMA1_FLAG_GL6 ((u32)0x00100000) +#define DMA1_FLAG_TC6 ((u32)0x00200000) +#define DMA1_FLAG_HT6 ((u32)0x00400000) +#define DMA1_FLAG_TE6 ((u32)0x00800000) +#define DMA1_FLAG_GL7 ((u32)0x01000000) +#define DMA1_FLAG_TC7 ((u32)0x02000000) +#define DMA1_FLAG_HT7 ((u32)0x04000000) +#define DMA1_FLAG_TE7 ((u32)0x08000000) +/* For DMA2 */ +#define DMA2_FLAG_GL1 ((u32)0x10000001) +#define DMA2_FLAG_TC1 ((u32)0x10000002) +#define DMA2_FLAG_HT1 ((u32)0x10000004) +#define DMA2_FLAG_TE1 ((u32)0x10000008) +#define DMA2_FLAG_GL2 ((u32)0x10000010) +#define DMA2_FLAG_TC2 ((u32)0x10000020) +#define DMA2_FLAG_HT2 ((u32)0x10000040) +#define DMA2_FLAG_TE2 ((u32)0x10000080) +#define DMA2_FLAG_GL3 ((u32)0x10000100) +#define DMA2_FLAG_TC3 ((u32)0x10000200) +#define DMA2_FLAG_HT3 ((u32)0x10000400) +#define DMA2_FLAG_TE3 ((u32)0x10000800) +#define DMA2_FLAG_GL4 ((u32)0x10001000) +#define DMA2_FLAG_TC4 ((u32)0x10002000) +#define DMA2_FLAG_HT4 ((u32)0x10004000) +#define DMA2_FLAG_TE4 ((u32)0x10008000) +#define DMA2_FLAG_GL5 ((u32)0x10010000) +#define DMA2_FLAG_TC5 ((u32)0x10020000) +#define DMA2_FLAG_HT5 ((u32)0x10040000) +#define DMA2_FLAG_TE5 ((u32)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) + +/* DMA Buffer Size -----------------------------------------------------------*/ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState); +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG); +void DMA_ClearFlag(u32 DMA_FLAG); +ITStatus DMA_GetITStatus(u32 DMA_IT); +void DMA_ClearITPendingBit(u32 DMA_IT); + +#endif /*__STM32F10x_DMA_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_exti.h b/bsp/stm32/library/inc/stm32f10x_exti.h new file mode 100644 index 0000000000..c9bfe59031 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_exti.h @@ -0,0 +1,107 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_exti.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* EXTI mode enumeration -----------------------------------------------------*/ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/* EXTI Trigger enumeration --------------------------------------------------*/ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) + +/* EXTI Init Structure definition --------------------------------------------*/ +typedef struct +{ + u32 EXTI_Line; + EXTIMode_TypeDef EXTI_Mode; + EXTITrigger_TypeDef EXTI_Trigger; + FunctionalState EXTI_LineCmd; +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* EXTI Lines ----------------------------------------------------------------*/ +#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16 + Connected to the PVD Output */ +#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17 + Connected to the RTC Alarm event */ +#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18 + Connected to the USB Wakeup from + suspend event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (u32)0xFFF80000) == 0x00) && ((LINE) != (u16)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(u32 EXTI_Line); +FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line); +void EXTI_ClearFlag(u32 EXTI_Line); +ITStatus EXTI_GetITStatus(u32 EXTI_Line); +void EXTI_ClearITPendingBit(u32 EXTI_Line); + +#endif /* __STM32F10x_EXTI_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_flash.h b/bsp/stm32/library/inc/stm32f10x_flash.h new file mode 100644 index 0000000000..449fca0f93 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_flash.h @@ -0,0 +1,208 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_flash.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* FLASH firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +#ifdef _FLASH_PROG +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; +#endif + +/* Flash Latency -------------------------------------------------------------*/ +#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) + +/* Half Cycle Enable/Disable -------------------------------------------------*/ +#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */ + +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) + + +/* Prefetch Buffer Enable/Disable --------------------------------------------*/ +#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */ + +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) + +#ifdef _FLASH_PROG +/* Option Bytes Write Protection ---------------------------------------------*/ +/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density + ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ +#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */ +#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */ +/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density + ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ +#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/* Option Bytes IWatchdog ----------------------------------------------------*/ +#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */ + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/* Option Bytes nRST_STOP ----------------------------------------------------*/ +#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */ + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/* Option Bytes nRST_STDBY ---------------------------------------------------*/ +#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */ + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/* FLASH Interrupts ----------------------------------------------------------*/ +#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/* FLASH Flags ---------------------------------------------------------------*/ +#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) + +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void FLASH_SetLatency(u32 FLASH_Latency); +void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer); + +#ifdef _FLASH_PROG +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(u32 Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data); +FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data); +FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data); +FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY); +u32 FLASH_GetUserOptionByte(void); +u32 FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG); +void FLASH_ClearFlag(u16 FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(u32 Timeout); +#endif + +#endif /* __STM32F10x_FLASH_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_fsmc.h b/bsp/stm32/library/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000000..699d69fa3b --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_fsmc.h @@ -0,0 +1,337 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_fsmc.h +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file contains all the functions prototypes for the +* FSMC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Timing parameters For NOR/SRAM Banks */ +typedef struct +{ + u32 FSMC_AddressSetupTime; + u32 FSMC_AddressHoldTime; + u32 FSMC_DataSetupTime; + u32 FSMC_BusTurnAroundDuration; + u32 FSMC_CLKDivision; + u32 FSMC_DataLatency; + u32 FSMC_AccessMode; +}FSMC_NORSRAMTimingInitTypeDef; + +/* FSMC NOR/SRAM Init structure definition */ +typedef struct +{ + u32 FSMC_Bank; + u32 FSMC_DataAddressMux; + u32 FSMC_MemoryType; + u32 FSMC_MemoryDataWidth; + u32 FSMC_BurstAccessMode; + u32 FSMC_WaitSignalPolarity; + u32 FSMC_WrapMode; + u32 FSMC_WaitSignalActive; + u32 FSMC_WriteOperation; + u32 FSMC_WaitSignal; + u32 FSMC_ExtendedMode; + u32 FSMC_WriteBurst; + /* Timing Parameters for write and read access if the ExtendedMode is not used*/ + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; + /* Timing Parameters for write access if the ExtendedMode is used*/ + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; +}FSMC_NORSRAMInitTypeDef; + +/* Timing parameters For FSMC NAND and PCCARD Banks */ +typedef struct +{ + u32 FSMC_SetupTime; + u32 FSMC_WaitSetupTime; + u32 FSMC_HoldSetupTime; + u32 FSMC_HiZSetupTime; +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/* FSMC NAND Init structure definition */ +typedef struct +{ + u32 FSMC_Bank; + u32 FSMC_Waitfeature; + u32 FSMC_MemoryDataWidth; + u32 FSMC_ECC; + u32 FSMC_ECCPageSize; + u32 FSMC_TCLRSetupTime; + u32 FSMC_TARSetupTime; + /* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; + /* FSMC Attribute Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; +}FSMC_NANDInitTypeDef; + +/* FSMC PCCARD Init structure definition */ +typedef struct +{ + u32 FSMC_Waitfeature; + u32 FSMC_TCLRSetupTime; + u32 FSMC_TARSetupTime; + /* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; + /* FSMC Attribute Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; + /* FSMC IO Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; +}FSMC_PCCARDInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/*-------------------------------FSMC Banks definitions ----------------------*/ +#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006) +#define FSMC_Bank2_NAND ((u32)0x00000010) +#define FSMC_Bank3_NAND ((u32)0x00000100) +#define FSMC_Bank4_PCCARD ((u32)0x00001000) + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + + +/*------------------------------- NOR/SRAM Banks -----------------------------*/ +/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/ +#define FSMC_DataAddressMux_Disable ((u32)0x00000000) +#define FSMC_DataAddressMux_Enable ((u32)0x00000002) + +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/* FSMC Memory Type ----------------------------------------------------------*/ +#define FSMC_MemoryType_SRAM ((u32)0x00000000) +#define FSMC_MemoryType_PSRAM ((u32)0x00000004) +#define FSMC_MemoryType_NOR ((u32)0x00000008) + +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/* FSMC Data Width ----------------------------------------------------------*/ +#define FSMC_MemoryDataWidth_8b ((u32)0x00000000) +#define FSMC_MemoryDataWidth_16b ((u32)0x00000010) + +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + + +/* FSMC Burst Access Mode ----------------------------------------------------*/ +#define FSMC_BurstAccessMode_Disable ((u32)0x00000000) +#define FSMC_BurstAccessMode_Enable ((u32)0x00000100) + +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) + +/* FSMC Wait Signal Polarity -------------------------------------------------*/ +#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000) +#define FSMC_WaitSignalPolarity_High ((u32)0x00000200) + +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/* FSMC Wrap Mode ------------------------------------------------------------*/ +#define FSMC_WrapMode_Disable ((u32)0x00000000) +#define FSMC_WrapMode_Enable ((u32)0x00000400) + +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/* FSMC Wait Timing ----------------------------------------------------------*/ +#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800) + +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/* FSMC Write Operation ------------------------------------------------------*/ +#define FSMC_WriteOperation_Disable ((u32)0x00000000) +#define FSMC_WriteOperation_Enable ((u32)0x00001000) + +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/* FSMC Wait Signal ----------------------------------------------------------*/ +#define FSMC_WaitSignal_Disable ((u32)0x00000000) +#define FSMC_WaitSignal_Enable ((u32)0x00002000) + +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) + +/* FSMC Extended Mode --------------------------------------------------------*/ +#define FSMC_ExtendedMode_Disable ((u32)0x00000000) +#define FSMC_ExtendedMode_Enable ((u32)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/* FSMC Write Burst ----------------------------------------------------------*/ +#define FSMC_WriteBurst_Disable ((u32)0x00000000) +#define FSMC_WriteBurst_Enable ((u32)0x00080000) + +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) + +/* FSMC Address Setup Time ---------------------------------------------------*/ +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/* FSMC Address Hold Time ----------------------------------------------------*/ +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/* FSMC Data Setup Time ------------------------------------------------------*/ +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/* FSMC Bus Turn around Duration ---------------------------------------------*/ +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/* FSMC CLK Division ---------------------------------------------------------*/ +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/* FSMC Data Latency ---------------------------------------------------------*/ +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/* FSMC Access Mode ----------------------------------------------------------*/ +#define FSMC_AccessMode_A ((u32)0x00000000) +#define FSMC_AccessMode_B ((u32)0x10000000) +#define FSMC_AccessMode_C ((u32)0x20000000) +#define FSMC_AccessMode_D ((u32)0x30000000) + +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/*----------------------------- NAND and PCCARD Banks ------------------------*/ +/* FSMC Wait feature ---------------------------------------------------------*/ +#define FSMC_Waitfeature_Disable ((u32)0x00000000) +#define FSMC_Waitfeature_Enable ((u32)0x00000002) + +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/* FSMC Memory Data Width ----------------------------------------------------*/ +#define FSMC_MemoryDataWidth_8b ((u32)0x00000000) +#define FSMC_MemoryDataWidth_16b ((u32)0x00000010) + +#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/* FSMC ECC ------------------------------------------------------------------*/ +#define FSMC_ECC_Disable ((u32)0x00000000) +#define FSMC_ECC_Enable ((u32)0x00000040) + +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/* FSMC ECC Page Size --------------------------------------------------------*/ +#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000) + +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/* FSMC TCLR Setup Time ------------------------------------------------------*/ +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC TAR Setup Time -------------------------------------------------------*/ +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Setup Time ----------------------------------------------------*/ +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Wait Setup Time -----------------------------------------------*/ +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Hold Setup Time -----------------------------------------------*/ +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC HiZ Setup Time ------------------------------------------------*/ +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/* FSMC Interrupt sources ----------------------------------------------------*/ +#define FSMC_IT_RisingEdge ((u32)0x00000008) +#define FSMC_IT_Level ((u32)0x00000010) +#define FSMC_IT_FallingEdge ((u32)0x00000020) + +#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) + +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) + +/* FSMC Flags ----------------------------------------------------------------*/ +#define FSMC_FLAG_RisingEdge ((u32)0x00000001) +#define FSMC_FLAG_Level ((u32)0x00000002) +#define FSMC_FLAG_FallingEdge ((u32)0x00000004) +#define FSMC_FLAG_FEMPT ((u32)0x00000040) + +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void FSMC_NORSRAMDeInit(u32 FSMC_Bank); +void FSMC_NANDDeInit(u32 FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState); +u32 FSMC_GetECC(u32 FSMC_Bank); +void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG); +void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG); +ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT); +void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT); + +#endif /*__STM32F10x_FSMC_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_gpio.h b/bsp/stm32/library/inc/stm32f10x_gpio.h new file mode 100644 index 0000000000..484584100b --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_gpio.h @@ -0,0 +1,237 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOB_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOC_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOD_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOE_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOF_BASE) || \ + ((*(u32*)&(PERIPH)) == GPIOG_BASE)) + +/* Output Maximum frequency selection ----------------------------------------*/ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/* Configuration Mode enumeration --------------------------------------------*/ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/* GPIO Init structure definition */ +typedef struct +{ + u16 GPIO_Pin; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define ----------------------------------------------------------*/ +#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/* GPIO Remap define ---------------------------------------------------------*/ +#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */ +#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */ +#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ + + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \ + ((REMAP) == GPIO_Remap_SWJ_Disable)) + +/* GPIO Port Sources ---------------------------------------------------------*/ +#define GPIO_PortSourceGPIOA ((u8)0x00) +#define GPIO_PortSourceGPIOB ((u8)0x01) +#define GPIO_PortSourceGPIOC ((u8)0x02) +#define GPIO_PortSourceGPIOD ((u8)0x03) +#define GPIO_PortSourceGPIOE ((u8)0x04) +#define GPIO_PortSourceGPIOF ((u8)0x05) +#define GPIO_PortSourceGPIOG ((u8)0x06) + +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/* GPIO Pin sources ----------------------------------------------------------*/ +#define GPIO_PinSource0 ((u8)0x00) +#define GPIO_PinSource1 ((u8)0x01) +#define GPIO_PinSource2 ((u8)0x02) +#define GPIO_PinSource3 ((u8)0x03) +#define GPIO_PinSource4 ((u8)0x04) +#define GPIO_PinSource5 ((u8)0x05) +#define GPIO_PinSource6 ((u8)0x06) +#define GPIO_PinSource7 ((u8)0x07) +#define GPIO_PinSource8 ((u8)0x08) +#define GPIO_PinSource9 ((u8)0x09) +#define GPIO_PinSource10 ((u8)0x0A) +#define GPIO_PinSource11 ((u8)0x0B) +#define GPIO_PinSource12 ((u8)0x0C) +#define GPIO_PinSource13 ((u8)0x0D) +#define GPIO_PinSource14 ((u8)0x0E) +#define GPIO_PinSource15 ((u8)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); + +#endif /* __STM32F10x_GPIO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_i2c.h b/bsp/stm32/library/inc/stm32f10x_i2c.h new file mode 100644 index 0000000000..52d1960087 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_i2c.h @@ -0,0 +1,285 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_i2c.h +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* I2C Init structure definition */ +typedef struct +{ + u16 I2C_Mode; + u16 I2C_DutyCycle; + u16 I2C_OwnAddress1; + u16 I2C_Ack; + u16 I2C_AcknowledgedAddress; + u32 I2C_ClockSpeed; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define IS_I2C_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == I2C1_BASE) || \ + ((*(u32*)&(PERIPH)) == I2C2_BASE)) + +/* I2C modes */ +#define I2C_Mode_I2C ((u16)0x0000) +#define I2C_Mode_SMBusDevice ((u16)0x0002) +#define I2C_Mode_SMBusHost ((u16)0x000A) + +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/* I2C duty cycle in fast mode */ +#define I2C_DutyCycle_16_9 ((u16)0x4000) +#define I2C_DutyCycle_2 ((u16)0xBFFF) + +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) + +/* I2C cknowledgementy */ +#define I2C_Ack_Enable ((u16)0x0400) +#define I2C_Ack_Disable ((u16)0x0000) + +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) + +/* I2C transfer direction */ +#define I2C_Direction_Transmitter ((u8)0x00) +#define I2C_Direction_Receiver ((u8)0x01) + +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) + +/* I2C acknowledged address defines */ +#define I2C_AcknowledgedAddress_7bit ((u16)0x4000) +#define I2C_AcknowledgedAddress_10bit ((u16)0xC000) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) + +/* I2C registers */ +#define I2C_Register_CR1 ((u8)0x00) +#define I2C_Register_CR2 ((u8)0x04) +#define I2C_Register_OAR1 ((u8)0x08) +#define I2C_Register_OAR2 ((u8)0x0C) +#define I2C_Register_DR ((u8)0x10) +#define I2C_Register_SR1 ((u8)0x14) +#define I2C_Register_SR2 ((u8)0x18) +#define I2C_Register_CCR ((u8)0x1C) +#define I2C_Register_TRISE ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) + +/* I2C SMBus alert pin level */ +#define I2C_SMBusAlert_Low ((u16)0x2000) +#define I2C_SMBusAlert_High ((u16)0xDFFF) + +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) + +/* I2C PEC position */ +#define I2C_PECPosition_Next ((u16)0x0800) +#define I2C_PECPosition_Current ((u16)0xF7FF) + +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) + +/* I2C interrupts definition */ +#define I2C_IT_BUF ((u16)0x0400) +#define I2C_IT_EVT ((u16)0x0200) +#define I2C_IT_ERR ((u16)0x0100) + +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (u16)0xF8FF) == 0x00) && ((IT) != 0x00)) + +/* I2C interrupts definition */ +#define I2C_IT_SMBALERT ((u32)0x01008000) +#define I2C_IT_TIMEOUT ((u32)0x01004000) +#define I2C_IT_PECERR ((u32)0x01001000) +#define I2C_IT_OVR ((u32)0x01000800) +#define I2C_IT_AF ((u32)0x01000400) +#define I2C_IT_ARLO ((u32)0x01000200) +#define I2C_IT_BERR ((u32)0x01000100) +#define I2C_IT_TXE ((u32)0x06000080) +#define I2C_IT_RXNE ((u32)0x06000040) +#define I2C_IT_STOPF ((u32)0x02000010) +#define I2C_IT_ADD10 ((u32)0x02000008) +#define I2C_IT_BTF ((u32)0x02000004) +#define I2C_IT_ADDR ((u32)0x02000002) +#define I2C_IT_SB ((u32)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (u16)0x20FF) == 0x00) && ((IT) != (u16)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) + +/* I2C flags definition */ +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((u32)0x00800000) +#define I2C_FLAG_SMBHOST ((u32)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000) +#define I2C_FLAG_GENCALL ((u32)0x00100000) +#define I2C_FLAG_TRA ((u32)0x00040000) +#define I2C_FLAG_BUSY ((u32)0x00020000) +#define I2C_FLAG_MSL ((u32)0x00010000) +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((u32)0x10008000) +#define I2C_FLAG_TIMEOUT ((u32)0x10004000) +#define I2C_FLAG_PECERR ((u32)0x10001000) +#define I2C_FLAG_OVR ((u32)0x10000800) +#define I2C_FLAG_AF ((u32)0x10000400) +#define I2C_FLAG_ARLO ((u32)0x10000200) +#define I2C_FLAG_BERR ((u32)0x10000100) +#define I2C_FLAG_TXE ((u32)0x10000080) +#define I2C_FLAG_RXNE ((u32)0x10000040) +#define I2C_FLAG_STOPF ((u32)0x10000010) +#define I2C_FLAG_ADD10 ((u32)0x10000008) +#define I2C_FLAG_BTF ((u32)0x10000004) +#define I2C_FLAG_ADDR ((u32)0x10000002) +#define I2C_FLAG_SB ((u32)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0x20FF) == 0x00) && ((FLAG) != (u16)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) + +/* I2C Events */ +/* EV1 */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */ + +/* EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */ + +/* EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */ + +/* EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */ + +/* EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */ + +/* EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */ + +/* EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((u32)0x00070080) /* TRA, BUSY, MSL, TXE flags */ + +/* EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/* EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/* EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) + +/* I2C own address1 -----------------------------------------------------------*/ +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/* I2C clock speed ------------------------------------------------------------*/ +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data); +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction); +u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +u8 I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle); +u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT); + +#endif /*__STM32F10x_I2C_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_iwdg.h b/bsp/stm32/library/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000000..97332f58c7 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_iwdg.h @@ -0,0 +1,69 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_iwdg.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Write access to IWDG_PR and IWDG_RLR registers */ +#define IWDG_WriteAccess_Enable ((u16)0x5555) +#define IWDG_WriteAccess_Disable ((u16)0x0000) + +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) + +/* IWDG prescaler */ +#define IWDG_Prescaler_4 ((u8)0x00) +#define IWDG_Prescaler_8 ((u8)0x01) +#define IWDG_Prescaler_16 ((u8)0x02) +#define IWDG_Prescaler_32 ((u8)0x03) +#define IWDG_Prescaler_64 ((u8)0x04) +#define IWDG_Prescaler_128 ((u8)0x05) +#define IWDG_Prescaler_256 ((u8)0x06) + +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) + +/* IWDG Flag */ +#define IWDG_FLAG_PVU ((u16)0x0001) +#define IWDG_FLAG_RVU ((u16)0x0002) + +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) + +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess); +void IWDG_SetPrescaler(u8 IWDG_Prescaler); +void IWDG_SetReload(u16 Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG); + +#endif /* __STM32F10x_IWDG_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_lib.h b/bsp/stm32/library/inc/stm32f10x_lib.h new file mode 100644 index 0000000000..77aa7274b9 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_lib.h @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_lib.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_LIB_H +#define __STM32F10x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +#ifdef _ADC + #include "stm32f10x_adc.h" +#endif /*_ADC */ + +#ifdef _BKP + #include "stm32f10x_bkp.h" +#endif /*_BKP */ + +#ifdef _CAN + #include "stm32f10x_can.h" +#endif /*_CAN */ + +#ifdef _CRC + #include "stm32f10x_crc.h" +#endif /*_CRC */ + +#ifdef _DAC + #include "stm32f10x_dac.h" +#endif /*_DAC */ + +#ifdef _DBGMCU + #include "stm32f10x_dbgmcu.h" +#endif /*_DBGMCU */ + +#ifdef _DMA + #include "stm32f10x_dma.h" +#endif /*_DMA */ + +#ifdef _EXTI + #include "stm32f10x_exti.h" +#endif /*_EXTI */ + +#ifdef _FLASH + #include "stm32f10x_flash.h" +#endif /*_FLASH */ + +#ifdef _FSMC + #include "stm32f10x_fsmc.h" +#endif /*_FSMC */ + +#ifdef _GPIO + #include "stm32f10x_gpio.h" +#endif /*_GPIO */ + +#ifdef _I2C + #include "stm32f10x_i2c.h" +#endif /*_I2C */ + +#ifdef _IWDG + #include "stm32f10x_iwdg.h" +#endif /*_IWDG */ + +#ifdef _NVIC + #include "stm32f10x_nvic.h" +#endif /*_NVIC */ + +#ifdef _PWR + #include "stm32f10x_pwr.h" +#endif /*_PWR */ + +#ifdef _RCC + #include "stm32f10x_rcc.h" +#endif /*_RCC */ + +#ifdef _RTC + #include "stm32f10x_rtc.h" +#endif /*_RTC */ + +#ifdef _SDIO + #include "stm32f10x_sdio.h" +#endif /*_SDIO */ + +#ifdef _SPI + #include "stm32f10x_spi.h" +#endif /*_SPI */ + +#ifdef _SysTick + #include "stm32f10x_systick.h" +#endif /*_SysTick */ + +#ifdef _TIM + #include "stm32f10x_tim.h" +#endif /*_TIM */ + +#ifdef _USART + #include "stm32f10x_usart.h" +#endif /*_USART */ + +#ifdef _WWDG + #include "stm32f10x_wwdg.h" +#endif /*_WWDG */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __STM32F10x_LIB_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_map.h b/bsp/stm32/library/inc/stm32f10x_map.h new file mode 100644 index 0000000000..851dff410a --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_map.h @@ -0,0 +1,7603 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_map.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the peripheral register's definitions, +* bits definitions and memory mapping. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_MAP_H +#define __STM32F10x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_conf.h" +#include "stm32f10x_type.h" +#include "cortexm3_macro.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Peripheral registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu32 SR; + vu32 CR1; + vu32 CR2; + vu32 SMPR1; + vu32 SMPR2; + vu32 JOFR1; + vu32 JOFR2; + vu32 JOFR3; + vu32 JOFR4; + vu32 HTR; + vu32 LTR; + vu32 SQR1; + vu32 SQR2; + vu32 SQR3; + vu32 JSQR; + vu32 JDR1; + vu32 JDR2; + vu32 JDR3; + vu32 JDR4; + vu32 DR; +} ADC_TypeDef; + +/*------------------------ Backup Registers ----------------------------------*/ +typedef struct +{ + u32 RESERVED0; + vu16 DR1; + u16 RESERVED1; + vu16 DR2; + u16 RESERVED2; + vu16 DR3; + u16 RESERVED3; + vu16 DR4; + u16 RESERVED4; + vu16 DR5; + u16 RESERVED5; + vu16 DR6; + u16 RESERVED6; + vu16 DR7; + u16 RESERVED7; + vu16 DR8; + u16 RESERVED8; + vu16 DR9; + u16 RESERVED9; + vu16 DR10; + u16 RESERVED10; + vu16 RTCCR; + u16 RESERVED11; + vu16 CR; + u16 RESERVED12; + vu16 CSR; + u16 RESERVED13[5]; + vu16 DR11; + u16 RESERVED14; + vu16 DR12; + u16 RESERVED15; + vu16 DR13; + u16 RESERVED16; + vu16 DR14; + u16 RESERVED17; + vu16 DR15; + u16 RESERVED18; + vu16 DR16; + u16 RESERVED19; + vu16 DR17; + u16 RESERVED20; + vu16 DR18; + u16 RESERVED21; + vu16 DR19; + u16 RESERVED22; + vu16 DR20; + u16 RESERVED23; + vu16 DR21; + u16 RESERVED24; + vu16 DR22; + u16 RESERVED25; + vu16 DR23; + u16 RESERVED26; + vu16 DR24; + u16 RESERVED27; + vu16 DR25; + u16 RESERVED28; + vu16 DR26; + u16 RESERVED29; + vu16 DR27; + u16 RESERVED30; + vu16 DR28; + u16 RESERVED31; + vu16 DR29; + u16 RESERVED32; + vu16 DR30; + u16 RESERVED33; + vu16 DR31; + u16 RESERVED34; + vu16 DR32; + u16 RESERVED35; + vu16 DR33; + u16 RESERVED36; + vu16 DR34; + u16 RESERVED37; + vu16 DR35; + u16 RESERVED38; + vu16 DR36; + u16 RESERVED39; + vu16 DR37; + u16 RESERVED40; + vu16 DR38; + u16 RESERVED41; + vu16 DR39; + u16 RESERVED42; + vu16 DR40; + u16 RESERVED43; + vu16 DR41; + u16 RESERVED44; + vu16 DR42; + u16 RESERVED45; +} BKP_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu32 TIR; + vu32 TDTR; + vu32 TDLR; + vu32 TDHR; +} CAN_TxMailBox_TypeDef; + +typedef struct +{ + vu32 RIR; + vu32 RDTR; + vu32 RDLR; + vu32 RDHR; +} CAN_FIFOMailBox_TypeDef; + +typedef struct +{ + vu32 FR1; + vu32 FR2; +} CAN_FilterRegister_TypeDef; + +typedef struct +{ + vu32 MCR; + vu32 MSR; + vu32 TSR; + vu32 RF0R; + vu32 RF1R; + vu32 IER; + vu32 ESR; + vu32 BTR; + u32 RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + u32 RESERVED1[12]; + vu32 FMR; + vu32 FM1R; + u32 RESERVED2; + vu32 FS1R; + u32 RESERVED3; + vu32 FFA1R; + u32 RESERVED4; + vu32 FA1R; + u32 RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/*------------------------ CRC calculation unit ------------------------------*/ +typedef struct +{ + vu32 DR; + vu8 IDR; + u8 RESERVED0; + u16 RESERVED1; + vu32 CR; +} CRC_TypeDef; + + +/*------------------------ Digital to Analog Converter -----------------------*/ +typedef struct +{ + vu32 CR; + vu32 SWTRIGR; + vu32 DHR12R1; + vu32 DHR12L1; + vu32 DHR8R1; + vu32 DHR12R2; + vu32 DHR12L2; + vu32 DHR8R2; + vu32 DHR12RD; + vu32 DHR12LD; + vu32 DHR8RD; + vu32 DOR1; + vu32 DOR2; +} DAC_TypeDef; + +/*------------------------ Debug MCU -----------------------------------------*/ +typedef struct +{ + vu32 IDCODE; + vu32 CR; +}DBGMCU_TypeDef; + +/*------------------------ DMA Controller ------------------------------------*/ +typedef struct +{ + vu32 CCR; + vu32 CNDTR; + vu32 CPAR; + vu32 CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + vu32 ISR; + vu32 IFCR; +} DMA_TypeDef; + +/*------------------------ External Interrupt/Event Controller ---------------*/ +typedef struct +{ + vu32 IMR; + vu32 EMR; + vu32 RTSR; + vu32 FTSR; + vu32 SWIER; + vu32 PR; +} EXTI_TypeDef; + +/*------------------------ FLASH and Option Bytes Registers ------------------*/ +typedef struct +{ + vu32 ACR; + vu32 KEYR; + vu32 OPTKEYR; + vu32 SR; + vu32 CR; + vu32 AR; + vu32 RESERVED; + vu32 OBR; + vu32 WRPR; +} FLASH_TypeDef; + +typedef struct +{ + vu16 RDP; + vu16 USER; + vu16 Data0; + vu16 Data1; + vu16 WRP0; + vu16 WRP1; + vu16 WRP2; + vu16 WRP3; +} OB_TypeDef; + +/*------------------------ Flexible Static Memory Controller -----------------*/ +typedef struct +{ + vu32 BTCR[8]; +} FSMC_Bank1_TypeDef; + +typedef struct +{ + vu32 BWTR[7]; +} FSMC_Bank1E_TypeDef; + +typedef struct +{ + vu32 PCR2; + vu32 SR2; + vu32 PMEM2; + vu32 PATT2; + u32 RESERVED0; + vu32 ECCR2; +} FSMC_Bank2_TypeDef; + +typedef struct +{ + vu32 PCR3; + vu32 SR3; + vu32 PMEM3; + vu32 PATT3; + u32 RESERVED0; + vu32 ECCR3; +} FSMC_Bank3_TypeDef; + +typedef struct +{ + vu32 PCR4; + vu32 SR4; + vu32 PMEM4; + vu32 PATT4; + vu32 PIO4; +} FSMC_Bank4_TypeDef; + +/*------------------------ General Purpose and Alternate Function IO ---------*/ +typedef struct +{ + vu32 CRL; + vu32 CRH; + vu32 IDR; + vu32 ODR; + vu32 BSRR; + vu32 BRR; + vu32 LCKR; +} GPIO_TypeDef; + +typedef struct +{ + vu32 EVCR; + vu32 MAPR; + vu32 EXTICR[4]; +} AFIO_TypeDef; + +/*------------------------ Inter-integrated Circuit Interface ----------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 OAR1; + u16 RESERVED2; + vu16 OAR2; + u16 RESERVED3; + vu16 DR; + u16 RESERVED4; + vu16 SR1; + u16 RESERVED5; + vu16 SR2; + u16 RESERVED6; + vu16 CCR; + u16 RESERVED7; + vu16 TRISE; + u16 RESERVED8; +} I2C_TypeDef; + +/*------------------------ Independent WATCHDOG ------------------------------*/ +typedef struct +{ + vu32 KR; + vu32 PR; + vu32 RLR; + vu32 SR; +} IWDG_TypeDef; + +/*------------------------ Nested Vectored Interrupt Controller --------------*/ +typedef struct +{ + vu32 ISER[2]; + u32 RESERVED0[30]; + vu32 ICER[2]; + u32 RSERVED1[30]; + vu32 ISPR[2]; + u32 RESERVED2[30]; + vu32 ICPR[2]; + u32 RESERVED3[30]; + vu32 IABR[2]; + u32 RESERVED4[62]; + vu32 IPR[15]; +} NVIC_TypeDef; + +typedef struct +{ + vuc32 CPUID; + vu32 ICSR; + vu32 VTOR; + vu32 AIRCR; + vu32 SCR; + vu32 CCR; + vu32 SHPR[3]; + vu32 SHCSR; + vu32 CFSR; + vu32 HFSR; + vu32 DFSR; + vu32 MMFAR; + vu32 BFAR; + vu32 AFSR; +} SCB_TypeDef; + +/*------------------------ Power Control -------------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CSR; +} PWR_TypeDef; + +/*------------------------ Reset and Clock Control ---------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFGR; + vu32 CIR; + vu32 APB2RSTR; + vu32 APB1RSTR; + vu32 AHBENR; + vu32 APB2ENR; + vu32 APB1ENR; + vu32 BDCR; + vu32 CSR; +} RCC_TypeDef; + +/*------------------------ Real-Time Clock -----------------------------------*/ +typedef struct +{ + vu16 CRH; + u16 RESERVED0; + vu16 CRL; + u16 RESERVED1; + vu16 PRLH; + u16 RESERVED2; + vu16 PRLL; + u16 RESERVED3; + vu16 DIVH; + u16 RESERVED4; + vu16 DIVL; + u16 RESERVED5; + vu16 CNTH; + u16 RESERVED6; + vu16 CNTL; + u16 RESERVED7; + vu16 ALRH; + u16 RESERVED8; + vu16 ALRL; + u16 RESERVED9; +} RTC_TypeDef; + +/*------------------------ SD host Interface ---------------------------------*/ +typedef struct +{ + vu32 POWER; + vu32 CLKCR; + vu32 ARG; + vu32 CMD; + vuc32 RESPCMD; + vuc32 RESP1; + vuc32 RESP2; + vuc32 RESP3; + vuc32 RESP4; + vu32 DTIMER; + vu32 DLEN; + vu32 DCTRL; + vuc32 DCOUNT; + vuc32 STA; + vu32 ICR; + vu32 MASK; + u32 RESERVED0[2]; + vuc32 FIFOCNT; + u32 RESERVED1[13]; + vu32 FIFO; +} SDIO_TypeDef; + +/*------------------------ Serial Peripheral Interface -----------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SR; + u16 RESERVED2; + vu16 DR; + u16 RESERVED3; + vu16 CRCPR; + u16 RESERVED4; + vu16 RXCRCR; + u16 RESERVED5; + vu16 TXCRCR; + u16 RESERVED6; + vu16 I2SCFGR; + u16 RESERVED7; + vu16 I2SPR; + u16 RESERVED8; +} SPI_TypeDef; + +/*------------------------ SystemTick ----------------------------------------*/ +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/*------------------------ TIM -----------------------------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11; + vu16 RCR; + u16 RESERVED12; + vu16 CCR1; + u16 RESERVED13; + vu16 CCR2; + u16 RESERVED14; + vu16 CCR3; + u16 RESERVED15; + vu16 CCR4; + u16 RESERVED16; + vu16 BDTR; + u16 RESERVED17; + vu16 DCR; + u16 RESERVED18; + vu16 DMAR; + u16 RESERVED19; +} TIM_TypeDef; + +/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ +typedef struct +{ + vu16 SR; + u16 RESERVED0; + vu16 DR; + u16 RESERVED1; + vu16 BRR; + u16 RESERVED2; + vu16 CR1; + u16 RESERVED3; + vu16 CR2; + u16 RESERVED4; + vu16 CR3; + u16 RESERVED5; + vu16 GTPR; + u16 RESERVED6; +} USART_TypeDef; + +/*------------------------ Window WATCHDOG -----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFR; + vu32 SR; +} WWDG_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address in the alias region */ +#define PERIPH_BB_BASE ((u32)0x42000000) +#define SRAM_BB_BASE ((u32)0x22000000) + +/* Peripheral and SRAM base address in the bit-band region */ +#define SRAM_BASE ((u32)0x20000000) +#define PERIPH_BASE ((u32)0x40000000) + +/* FSMC registers base address */ +#define FSMC_R_BASE ((u32)0xA0000000) + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +/* Flash registers base address */ +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +/* Flash Option Bytes base address */ +#define OB_BASE ((u32)0x1FFFF800) + +/* FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((u32)0xE0042000) + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/*------------------------ Non Debug Mode ------------------------------------*/ +#ifndef DEBUG +#ifdef _TIM2 + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#endif /*_TIM2 */ + +#ifdef _TIM3 + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#endif /*_TIM3 */ + +#ifdef _TIM4 + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#endif /*_TIM4 */ + +#ifdef _TIM5 + #define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#endif /*_TIM5 */ + +#ifdef _TIM6 + #define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#endif /*_TIM6 */ + +#ifdef _TIM7 + #define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#endif /*_TIM7 */ + +#ifdef _RTC + #define RTC ((RTC_TypeDef *) RTC_BASE) +#endif /*_RTC */ + +#ifdef _WWDG + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#endif /*_WWDG */ + +#ifdef _IWDG + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#endif /*_IWDG */ + +#ifdef _SPI2 + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#endif /*_SPI2 */ + +#ifdef _SPI3 + #define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#endif /*_SPI3 */ + +#ifdef _USART2 + #define USART2 ((USART_TypeDef *) USART2_BASE) +#endif /*_USART2 */ + +#ifdef _USART3 + #define USART3 ((USART_TypeDef *) USART3_BASE) +#endif /*_USART3 */ + +#ifdef _UART4 + #define UART4 ((USART_TypeDef *) UART4_BASE) +#endif /*_UART4 */ + +#ifdef _UART5 + #define UART5 ((USART_TypeDef *) UART5_BASE) +#endif /*_USART5 */ + +#ifdef _I2C1 + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#endif /*_I2C1 */ + +#ifdef _I2C2 + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#endif /*_I2C2 */ + +#ifdef _CAN + #define CAN ((CAN_TypeDef *) CAN_BASE) +#endif /*_CAN */ + +#ifdef _BKP + #define BKP ((BKP_TypeDef *) BKP_BASE) +#endif /*_BKP */ + +#ifdef _PWR + #define PWR ((PWR_TypeDef *) PWR_BASE) +#endif /*_PWR */ + +#ifdef _DAC + #define DAC ((DAC_TypeDef *) DAC_BASE) +#endif /*_DAC */ + +#ifdef _AFIO + #define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#endif /*_AFIO */ + +#ifdef _EXTI + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#endif /*_EXTI */ + +#ifdef _GPIOA + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#endif /*_GPIOA */ + +#ifdef _GPIOB + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#endif /*_GPIOB */ + +#ifdef _GPIOC + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#endif /*_GPIOC */ + +#ifdef _GPIOD + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#endif /*_GPIOD */ + +#ifdef _GPIOE + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#endif /*_GPIOE */ + +#ifdef _GPIOF + #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#endif /*_GPIOF */ + +#ifdef _GPIOG + #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#endif /*_GPIOG */ + +#ifdef _ADC1 + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#endif /*_ADC1 */ + +#ifdef _ADC2 + #define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#endif /*_ADC2 */ + +#ifdef _TIM1 + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#endif /*_TIM1 */ + +#ifdef _SPI1 + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#endif /*_SPI1 */ + +#ifdef _TIM8 + #define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#endif /*_TIM8 */ + +#ifdef _USART1 + #define USART1 ((USART_TypeDef *) USART1_BASE) +#endif /*_USART1 */ + +#ifdef _ADC3 + #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#endif /*_ADC3 */ + +#ifdef _SDIO + #define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#endif /*_SDIO */ + +#ifdef _DMA + #define DMA1 ((DMA_TypeDef *) DMA1_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#endif /*_DMA2_Channel5 */ + +#ifdef _RCC + #define RCC ((RCC_TypeDef *) RCC_BASE) +#endif /*_RCC */ + +#ifdef _CRC + #define CRC ((CRC_TypeDef *) CRC_BASE) +#endif /*_CRC */ + +#ifdef _FLASH + #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) + #define OB ((OB_TypeDef *) OB_BASE) +#endif /*_FLASH */ + +#ifdef _FSMC + #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) + #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) + #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /*_FSMC */ + +#ifdef _DBGMCU + #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#endif /*_DBGMCU */ + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + +#ifdef _NVIC + #define NVIC ((NVIC_TypeDef *) NVIC_BASE) + #define SCB ((SCB_TypeDef *) SCB_BASE) +#endif /*_NVIC */ + +/*------------------------ Debug Mode ----------------------------------------*/ +#else /* DEBUG */ +#ifdef _TIM2 + EXT TIM_TypeDef *TIM2; +#endif /*_TIM2 */ + +#ifdef _TIM3 + EXT TIM_TypeDef *TIM3; +#endif /*_TIM3 */ + +#ifdef _TIM4 + EXT TIM_TypeDef *TIM4; +#endif /*_TIM4 */ + +#ifdef _TIM5 + EXT TIM_TypeDef *TIM5; +#endif /*_TIM5 */ + +#ifdef _TIM6 + EXT TIM_TypeDef *TIM6; +#endif /*_TIM6 */ + +#ifdef _TIM7 + EXT TIM_TypeDef *TIM7; +#endif /*_TIM7 */ + +#ifdef _RTC + EXT RTC_TypeDef *RTC; +#endif /*_RTC */ + +#ifdef _WWDG + EXT WWDG_TypeDef *WWDG; +#endif /*_WWDG */ + +#ifdef _IWDG + EXT IWDG_TypeDef *IWDG; +#endif /*_IWDG */ + +#ifdef _SPI2 + EXT SPI_TypeDef *SPI2; +#endif /*_SPI2 */ + +#ifdef _SPI3 + EXT SPI_TypeDef *SPI3; +#endif /*_SPI3 */ + +#ifdef _USART2 + EXT USART_TypeDef *USART2; +#endif /*_USART2 */ + +#ifdef _USART3 + EXT USART_TypeDef *USART3; +#endif /*_USART3 */ + +#ifdef _UART4 + EXT USART_TypeDef *UART4; +#endif /*_UART4 */ + +#ifdef _UART5 + EXT USART_TypeDef *UART5; +#endif /*_UART5 */ + +#ifdef _I2C1 + EXT I2C_TypeDef *I2C1; +#endif /*_I2C1 */ + +#ifdef _I2C2 + EXT I2C_TypeDef *I2C2; +#endif /*_I2C2 */ + +#ifdef _CAN + EXT CAN_TypeDef *CAN; +#endif /*_CAN */ + +#ifdef _BKP + EXT BKP_TypeDef *BKP; +#endif /*_BKP */ + +#ifdef _PWR + EXT PWR_TypeDef *PWR; +#endif /*_PWR */ + +#ifdef _DAC + EXT DAC_TypeDef *DAC; +#endif /*_DAC */ + +#ifdef _AFIO + EXT AFIO_TypeDef *AFIO; +#endif /*_AFIO */ + +#ifdef _EXTI + EXT EXTI_TypeDef *EXTI; +#endif /*_EXTI */ + +#ifdef _GPIOA + EXT GPIO_TypeDef *GPIOA; +#endif /*_GPIOA */ + +#ifdef _GPIOB + EXT GPIO_TypeDef *GPIOB; +#endif /*_GPIOB */ + +#ifdef _GPIOC + EXT GPIO_TypeDef *GPIOC; +#endif /*_GPIOC */ + +#ifdef _GPIOD + EXT GPIO_TypeDef *GPIOD; +#endif /*_GPIOD */ + +#ifdef _GPIOE + EXT GPIO_TypeDef *GPIOE; +#endif /*_GPIOE */ + +#ifdef _GPIOF + EXT GPIO_TypeDef *GPIOF; +#endif /*_GPIOF */ + +#ifdef _GPIOG + EXT GPIO_TypeDef *GPIOG; +#endif /*_GPIOG */ + +#ifdef _ADC1 + EXT ADC_TypeDef *ADC1; +#endif /*_ADC1 */ + +#ifdef _ADC2 + EXT ADC_TypeDef *ADC2; +#endif /*_ADC2 */ + +#ifdef _TIM1 + EXT TIM_TypeDef *TIM1; +#endif /*_TIM1 */ + +#ifdef _SPI1 + EXT SPI_TypeDef *SPI1; +#endif /*_SPI1 */ + +#ifdef _TIM8 + EXT TIM_TypeDef *TIM8; +#endif /*_TIM8 */ + +#ifdef _USART1 + EXT USART_TypeDef *USART1; +#endif /*_USART1 */ + +#ifdef _ADC3 + EXT ADC_TypeDef *ADC3; +#endif /*_ADC3 */ + +#ifdef _SDIO + EXT SDIO_TypeDef *SDIO; +#endif /*_SDIO */ + +#ifdef _DMA + EXT DMA_TypeDef *DMA1; + EXT DMA_TypeDef *DMA2; +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + EXT DMA_Channel_TypeDef *DMA1_Channel1; +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + EXT DMA_Channel_TypeDef *DMA1_Channel2; +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + EXT DMA_Channel_TypeDef *DMA1_Channel3; +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + EXT DMA_Channel_TypeDef *DMA1_Channel4; +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + EXT DMA_Channel_TypeDef *DMA1_Channel5; +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + EXT DMA_Channel_TypeDef *DMA1_Channel6; +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + EXT DMA_Channel_TypeDef *DMA1_Channel7; +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + EXT DMA_Channel_TypeDef *DMA2_Channel1; +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + EXT DMA_Channel_TypeDef *DMA2_Channel2; +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + EXT DMA_Channel_TypeDef *DMA2_Channel3; +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + EXT DMA_Channel_TypeDef *DMA2_Channel4; +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + EXT DMA_Channel_TypeDef *DMA2_Channel5; +#endif /*_DMA2_Channel5 */ + +#ifdef _RCC + EXT RCC_TypeDef *RCC; +#endif /*_RCC */ + +#ifdef _CRC + EXT CRC_TypeDef *CRC; +#endif /*_CRC */ + +#ifdef _FLASH + EXT FLASH_TypeDef *FLASH; + EXT OB_TypeDef *OB; +#endif /*_FLASH */ + +#ifdef _FSMC + EXT FSMC_Bank1_TypeDef *FSMC_Bank1; + EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E; + EXT FSMC_Bank2_TypeDef *FSMC_Bank2; + EXT FSMC_Bank3_TypeDef *FSMC_Bank3; + EXT FSMC_Bank4_TypeDef *FSMC_Bank4; +#endif /*_FSMC */ + +#ifdef _DBGMCU + EXT DBGMCU_TypeDef *DBGMCU; +#endif /*_DBGMCU */ + +#ifdef _SysTick + EXT SysTick_TypeDef *SysTick; +#endif /*_SysTick */ + +#ifdef _NVIC + EXT NVIC_TypeDef *NVIC; + EXT SCB_TypeDef *SCB; +#endif /*_NVIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((u8)0x01) /* RESET bit */ + + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */ +#define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */ +#define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */ +#define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */ +#define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */ +#define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */ +#define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */ + +/* PVD level configuration */ +#define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */ + +#define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((u16)0xFFFF) /* Backup data */ + + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((u16)0xFFFF) /* Backup data */ + + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((u16)0x007F) /* Calibration value */ +#define BKP_RTCCR_CCO ((u16)0x0080) /* Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((u16)0x0100) /* Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((u16)0x0200) /* Alarm or Second Output Selection */ + + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((u8)0x01) /* TAMPER pin enable */ +#define BKP_CR_TPAL ((u8)0x02) /* TAMPER pin active level */ + + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((u16)0x0001) /* Clear Tamper event */ +#define BKP_CSR_CTI ((u16)0x0002) /* Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((u16)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((u16)0x0100) /* Tamper Event Flag */ +#define BKP_CSR_TIF ((u16)0x0200) /* Tamper Interrupt Flag */ + + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((u32)0x00000001) /* Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((u32)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((u32)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((u32)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */ +#define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((u32)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CR_CSSON ((u32)0x00080000) /* Clock Security System enable */ +#define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */ +#define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +#define RCC_CFGR_SW ((u32)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((u32)0x00000001) /* Bit 0 */ +#define RCC_CFGR_SW_1 ((u32)0x00000002) /* Bit 1 */ + +/* SW configuration */ +#define RCC_CFGR_SW_HSI ((u32)0x00000000) /* HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((u32)0x00000001) /* HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */ + +#define RCC_CFGR_SWS ((u32)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((u32)0x00000004) /* Bit 0 */ +#define RCC_CFGR_SWS_1 ((u32)0x00000008) /* Bit 1 */ + +/* SWS configuration */ +#define RCC_CFGR_SWS_HSI ((u32)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */ + +#define RCC_CFGR_HPRE ((u32)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((u32)0x00000010) /* Bit 0 */ +#define RCC_CFGR_HPRE_1 ((u32)0x00000020) /* Bit 1 */ +#define RCC_CFGR_HPRE_2 ((u32)0x00000040) /* Bit 2 */ +#define RCC_CFGR_HPRE_3 ((u32)0x00000080) /* Bit 3 */ + +/* HPRE configuration */ +#define RCC_CFGR_HPRE_DIV1 ((u32)0x00000000) /* SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((u32)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((u32)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((u32)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((u32)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((u32)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((u32)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((u32)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((u32)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_CFGR_PPRE1 ((u32)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((u32)0x00000100) /* Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((u32)0x00000200) /* Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((u32)0x00000400) /* Bit 2 */ + +/* PPRE1 configuration */ +#define RCC_CFGR_PPRE1_DIV1 ((u32)0x00000000) /* HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((u32)0x00000500) /* HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((u32)0x00000600) /* HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((u32)0x00000700) /* HCLK divided by 16 */ + +#define RCC_CFGR_PPRE2 ((u32)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((u32)0x00000800) /* Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((u32)0x00001000) /* Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((u32)0x00002000) /* Bit 2 */ + +/* PPRE2 configuration */ +#define RCC_CFGR_PPRE2_DIV1 ((u32)0x00000000) /* HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((u32)0x00002000) /* HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((u32)0x00002800) /* HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((u32)0x00003000) /* HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((u32)0x00003800) /* HCLK divided by 16 */ + +#define RCC_CFGR_ADCPRE ((u32)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((u32)0x00004000) /* Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((u32)0x00008000) /* Bit 1 */ + +/* ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_DIV2 ((u32)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((u32)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((u32)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((u32)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE ((u32)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_CFGR_PLLMULL ((u32)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((u32)0x00040000) /* Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((u32)0x00080000) /* Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((u32)0x00100000) /* Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((u32)0x00200000) /* Bit 3 */ + +/* PLLMUL configuration */ +#define RCC_CFGR_PLLMULL2 ((u32)0x00000000) /* PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3 ((u32)0x00040000) /* PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4 ((u32)0x00080000) /* PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5 ((u32)0x000C0000) /* PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6 ((u32)0x00100000) /* PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7 ((u32)0x00140000) /* PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8 ((u32)0x00180000) /* PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10 ((u32)0x00200000) /* PLL input clock10 */ +#define RCC_CFGR_PLLMULL11 ((u32)0x00240000) /* PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12 ((u32)0x00280000) /* PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13 ((u32)0x002C0000) /* PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14 ((u32)0x00300000) /* PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15 ((u32)0x00340000) /* PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16 ((u32)0x00380000) /* PLL input clock*16 */ + +#define RCC_CFGR_USBPRE ((u32)0x00400000) /* USB prescaler */ + +#define RCC_CFGR_MCO ((u32)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 ((u32)0x01000000) /* Bit 0 */ +#define RCC_CFGR_MCO_1 ((u32)0x02000000) /* Bit 1 */ +#define RCC_CFGR_MCO_2 ((u32)0x04000000) /* Bit 2 */ + +/* MCO configuration */ +#define RCC_CFGR_MCO_NOCLOCK ((u32)0x00000000) /* No clock */ +#define RCC_CFGR_MCO_SYSCLK ((u32)0x04000000) /* System clock selected */ +#define RCC_CFGR_MCO_HSI ((u32)0x05000000) /* Internal 8 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCO_HSE ((u32)0x06000000) /* External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCO_PLL ((u32)0x07000000) /* PLL clock divided by 2 selected*/ + + +/******************* Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((u32)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((u32)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((u32)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((u32)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((u32)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((u32)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((u32)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((u32)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((u32)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((u32)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((u32)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((u32)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((u32)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((u32)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((u32)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((u32)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((u32)0x00800000) /* Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((u16)0x0001) /* Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((u16)0x0004) /* I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((u16)0x0008) /* IO port B reset */ +#define RCC_APB2RSTR_IOPCRST ((u16)0x0010) /* IO port C reset */ +#define RCC_APB2RSTR_IOPDRST ((u16)0x0020) /* IO port D reset */ +#define RCC_APB2RSTR_IOPERST ((u16)0x0040) /* IO port E reset */ +#define RCC_APB2RSTR_IOPFRST ((u16)0x0080) /* IO port F reset */ +#define RCC_APB2RSTR_IOPGRST ((u16)0x0100) /* IO port G reset */ +#define RCC_APB2RSTR_ADC1RST ((u16)0x0200) /* ADC 1 interface reset */ +#define RCC_APB2RSTR_ADC2RST ((u16)0x0400) /* ADC 2 interface reset */ +#define RCC_APB2RSTR_TIM1RST ((u16)0x0800) /* TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((u16)0x1000) /* SPI 1 reset */ +#define RCC_APB2RSTR_TIM8RST ((u16)0x2000) /* TIM8 Timer reset */ +#define RCC_APB2RSTR_USART1RST ((u16)0x4000) /* USART1 reset */ +#define RCC_APB2RSTR_ADC3RST ((u16)0x8000) /* ADC3 interface reset */ + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((u32)0x00000001) /* Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((u32)0x00000002) /* Timer 3 reset */ +#define RCC_APB1RSTR_TIM4RST ((u32)0x00000004) /* Timer 4 reset */ +#define RCC_APB1RSTR_TIM5RST ((u32)0x00000008) /* Timer 5 reset */ +#define RCC_APB1RSTR_TIM6RST ((u32)0x00000010) /* Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST ((u32)0x00000020) /* Timer 7 reset */ +#define RCC_APB1RSTR_WWDGRST ((u32)0x00000800) /* Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST ((u32)0x00004000) /* SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST ((u32)0x00008000) /* SPI 3 reset */ +#define RCC_APB1RSTR_USART2RST ((u32)0x00020000) /* USART 2 reset */ +#define RCC_APB1RSTR_USART3RST ((u32)0x00040000) /* RUSART 3 reset */ +#define RCC_APB1RSTR_UART4RST ((u32)0x00080000) /* USART 4 reset */ +#define RCC_APB1RSTR_UART5RST ((u32)0x00100000) /* USART 5 reset */ +#define RCC_APB1RSTR_I2C1RST ((u32)0x00200000) /* I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST ((u32)0x00400000) /* I2C 2 reset */ +#define RCC_APB1RSTR_USBRST ((u32)0x00800000) /* USB reset */ +#define RCC_APB1RSTR_CANRST ((u32)0x02000000) /* CAN reset */ +#define RCC_APB1RSTR_BKPRST ((u32)0x08000000) /* Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((u32)0x10000000) /* Power interface reset */ +#define RCC_APB1RSTR_DACRST ((u32)0x20000000) /* DAC interface reset */ + + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((u16)0x0001) /* DMA1 clock enable */ +#define RCC_AHBENR_DMA2EN ((u16)0x0002) /* DMA2 clock enable */ +#define RCC_AHBENR_SRAMEN ((u16)0x0004) /* SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((u16)0x0010) /* FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((u16)0x0040) /* CRC clock enable */ +#define RCC_AHBENR_FSMCEN ((u16)0x0100) /* FSMC clock enable */ +#define RCC_AHBENR_SDIOEN ((u16)0x0400) /* SDIO clock enable */ + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((u16)0x0001) /* Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((u16)0x0004) /* I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((u16)0x0008) /* I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((u16)0x0010) /* I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((u16)0x0020) /* I/O port D clock enable */ +#define RCC_APB2ENR_IOPEEN ((u16)0x0040) /* I/O port E clock enable */ +#define RCC_APB2ENR_IOPFEN ((u16)0x0080) /* I/O port F clock enable */ +#define RCC_APB2ENR_IOPGEN ((u16)0x0100) /* I/O port G clock enable */ +#define RCC_APB2ENR_ADC1EN ((u16)0x0200) /* ADC 1 interface clock enable */ +#define RCC_APB2ENR_ADC2EN ((u16)0x0400) /* ADC 2 interface clock enable */ +#define RCC_APB2ENR_TIM1EN ((u16)0x0800) /* TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((u16)0x1000) /* SPI 1 clock enable */ +#define RCC_APB2ENR_TIM8EN ((u16)0x2000) /* TIM8 Timer clock enable */ +#define RCC_APB2ENR_USART1EN ((u16)0x4000) /* USART1 clock enable */ +#define RCC_APB2ENR_ADC3EN ((u16)0x8000) /* DMA1 clock enable */ + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((u32)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((u32)0x00000002) /* Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN ((u32)0x00000004) /* Timer 4 clock enable */ +#define RCC_APB1ENR_TIM5EN ((u32)0x00000008) /* Timer 5 clock enable */ +#define RCC_APB1ENR_TIM6EN ((u32)0x00000010) /* Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN ((u32)0x00000020) /* Timer 7 clock enable */ +#define RCC_APB1ENR_WWDGEN ((u32)0x00000800) /* Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN ((u32)0x00004000) /* SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN ((u32)0x00008000) /* SPI 3 clock enable */ +#define RCC_APB1ENR_USART2EN ((u32)0x00020000) /* USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN ((u32)0x00040000) /* USART 3 clock enable */ +#define RCC_APB1ENR_UART4EN ((u32)0x00080000) /* USART 4 clock enable */ +#define RCC_APB1ENR_UART5EN ((u32)0x00100000) /* USART 5 clock enable */ +#define RCC_APB1ENR_I2C1EN ((u32)0x00200000) /* I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN ((u32)0x00400000) /* I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN ((u32)0x00800000) /* USB clock enable */ +#define RCC_APB1ENR_CANEN ((u32)0x02000000) /* CAN clock enable */ +#define RCC_APB1ENR_BKPEN ((u32)0x08000000) /* Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((u32)0x10000000) /* Power interface clock enable */ +#define RCC_APB1ENR_DACEN ((u32)0x20000000) /* DAC interface clock enable */ + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((u32)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((u32)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((u32)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((u32)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((u32)0x00000100) /* Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((u32)0x00000200) /* Bit 1 */ +/* RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((u32)0x00000000) /* No clock */ +#define RCC_BDCR_RTCSEL_LSE ((u32)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((u32)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((u32)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((u32)0x00008000) /* RTC clock enable */ +#define RCC_BDCR_BDRST ((u32)0x00010000) /* Backup domain software reset */ + + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((u32)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((u32)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((u32)0x01000000) /* Remove reset flag */ +#define RCC_CSR_PINRSTF ((u32)0x04000000) /* PIN reset flag */ +#define RCC_CSR_PORRSTF ((u32)0x08000000) /* POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((u32)0x10000000) /* Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((u32)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((u32)0x40000000) /* Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((u32)0x80000000) /* Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function IO */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((u32)0x33333333) /* Port x mode bits */ + +#define GPIO_CRL_MODE0 ((u32)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((u32)0x00000001) /* Bit 0 */ +#define GPIO_CRL_MODE0_1 ((u32)0x00000002) /* Bit 1 */ + +#define GPIO_CRL_MODE1 ((u32)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((u32)0x00000010) /* Bit 0 */ +#define GPIO_CRL_MODE1_1 ((u32)0x00000020) /* Bit 1 */ + +#define GPIO_CRL_MODE2 ((u32)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((u32)0x00000100) /* Bit 0 */ +#define GPIO_CRL_MODE2_1 ((u32)0x00000200) /* Bit 1 */ + +#define GPIO_CRL_MODE3 ((u32)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((u32)0x00001000) /* Bit 0 */ +#define GPIO_CRL_MODE3_1 ((u32)0x00002000) /* Bit 1 */ + +#define GPIO_CRL_MODE4 ((u32)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((u32)0x00010000) /* Bit 0 */ +#define GPIO_CRL_MODE4_1 ((u32)0x00020000) /* Bit 1 */ + +#define GPIO_CRL_MODE5 ((u32)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((u32)0x00100000) /* Bit 0 */ +#define GPIO_CRL_MODE5_1 ((u32)0x00200000) /* Bit 1 */ + +#define GPIO_CRL_MODE6 ((u32)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((u32)0x01000000) /* Bit 0 */ +#define GPIO_CRL_MODE6_1 ((u32)0x02000000) /* Bit 1 */ + +#define GPIO_CRL_MODE7 ((u32)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((u32)0x10000000) /* Bit 0 */ +#define GPIO_CRL_MODE7_1 ((u32)0x20000000) /* Bit 1 */ + + +#define GPIO_CRL_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((u32)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((u32)0x00000004) /* Bit 0 */ +#define GPIO_CRL_CNF0_1 ((u32)0x00000008) /* Bit 1 */ + +#define GPIO_CRL_CNF1 ((u32)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((u32)0x00000040) /* Bit 0 */ +#define GPIO_CRL_CNF1_1 ((u32)0x00000080) /* Bit 1 */ + +#define GPIO_CRL_CNF2 ((u32)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((u32)0x00000400) /* Bit 0 */ +#define GPIO_CRL_CNF2_1 ((u32)0x00000800) /* Bit 1 */ + +#define GPIO_CRL_CNF3 ((u32)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((u32)0x00004000) /* Bit 0 */ +#define GPIO_CRL_CNF3_1 ((u32)0x00008000) /* Bit 1 */ + +#define GPIO_CRL_CNF4 ((u32)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((u32)0x00040000) /* Bit 0 */ +#define GPIO_CRL_CNF4_1 ((u32)0x00080000) /* Bit 1 */ + +#define GPIO_CRL_CNF5 ((u32)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((u32)0x00400000) /* Bit 0 */ +#define GPIO_CRL_CNF5_1 ((u32)0x00800000) /* Bit 1 */ + +#define GPIO_CRL_CNF6 ((u32)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((u32)0x04000000) /* Bit 0 */ +#define GPIO_CRL_CNF6_1 ((u32)0x08000000) /* Bit 1 */ + +#define GPIO_CRL_CNF7 ((u32)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((u32)0x40000000) /* Bit 0 */ +#define GPIO_CRL_CNF7_1 ((u32)0x80000000) /* Bit 1 */ + + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((u32)0x33333333) /* Port x mode bits */ + +#define GPIO_CRH_MODE8 ((u32)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((u32)0x00000001) /* Bit 0 */ +#define GPIO_CRH_MODE8_1 ((u32)0x00000002) /* Bit 1 */ + +#define GPIO_CRH_MODE9 ((u32)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((u32)0x00000010) /* Bit 0 */ +#define GPIO_CRH_MODE9_1 ((u32)0x00000020) /* Bit 1 */ + +#define GPIO_CRH_MODE10 ((u32)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((u32)0x00000100) /* Bit 0 */ +#define GPIO_CRH_MODE10_1 ((u32)0x00000200) /* Bit 1 */ + +#define GPIO_CRH_MODE11 ((u32)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((u32)0x00001000) /* Bit 0 */ +#define GPIO_CRH_MODE11_1 ((u32)0x00002000) /* Bit 1 */ + +#define GPIO_CRH_MODE12 ((u32)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((u32)0x00010000) /* Bit 0 */ +#define GPIO_CRH_MODE12_1 ((u32)0x00020000) /* Bit 1 */ + +#define GPIO_CRH_MODE13 ((u32)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((u32)0x00100000) /* Bit 0 */ +#define GPIO_CRH_MODE13_1 ((u32)0x00200000) /* Bit 1 */ + +#define GPIO_CRH_MODE14 ((u32)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((u32)0x01000000) /* Bit 0 */ +#define GPIO_CRH_MODE14_1 ((u32)0x02000000) /* Bit 1 */ + +#define GPIO_CRH_MODE15 ((u32)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((u32)0x10000000) /* Bit 0 */ +#define GPIO_CRH_MODE15_1 ((u32)0x20000000) /* Bit 1 */ + + +#define GPIO_CRH_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((u32)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((u32)0x00000004) /* Bit 0 */ +#define GPIO_CRH_CNF8_1 ((u32)0x00000008) /* Bit 1 */ + +#define GPIO_CRH_CNF9 ((u32)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((u32)0x00000040) /* Bit 0 */ +#define GPIO_CRH_CNF9_1 ((u32)0x00000080) /* Bit 1 */ + +#define GPIO_CRH_CNF10 ((u32)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((u32)0x00000400) /* Bit 0 */ +#define GPIO_CRH_CNF10_1 ((u32)0x00000800) /* Bit 1 */ + +#define GPIO_CRH_CNF11 ((u32)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((u32)0x00004000) /* Bit 0 */ +#define GPIO_CRH_CNF11_1 ((u32)0x00008000) /* Bit 1 */ + +#define GPIO_CRH_CNF12 ((u32)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((u32)0x00040000) /* Bit 0 */ +#define GPIO_CRH_CNF12_1 ((u32)0x00080000) /* Bit 1 */ + +#define GPIO_CRH_CNF13 ((u32)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((u32)0x00400000) /* Bit 0 */ +#define GPIO_CRH_CNF13_1 ((u32)0x00800000) /* Bit 1 */ + +#define GPIO_CRH_CNF14 ((u32)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((u32)0x04000000) /* Bit 0 */ +#define GPIO_CRH_CNF14_1 ((u32)0x08000000) /* Bit 1 */ + +#define GPIO_CRH_CNF15 ((u32)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((u32)0x40000000) /* Bit 0 */ +#define GPIO_CRH_CNF15_1 ((u32)0x80000000) /* Bit 1 */ + + +/******************* Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((u16)0x0001) /* Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((u16)0x0002) /* Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((u16)0x0004) /* Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((u16)0x0008) /* Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((u16)0x0010) /* Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((u16)0x0020) /* Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((u16)0x0040) /* Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((u16)0x0080) /* Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((u16)0x0100) /* Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((u16)0x0200) /* Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((u16)0x0400) /* Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((u16)0x0800) /* Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((u16)0x1000) /* Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((u16)0x2000) /* Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((u16)0x4000) /* Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((u16)0x8000) /* Port input data, bit 15 */ + + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((u16)0x0001) /* Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((u16)0x0002) /* Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((u16)0x0004) /* Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((u16)0x0008) /* Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((u16)0x0010) /* Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((u16)0x0020) /* Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((u16)0x0040) /* Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((u16)0x0080) /* Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((u16)0x0100) /* Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((u16)0x0200) /* Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((u16)0x0400) /* Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((u16)0x0800) /* Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((u16)0x1000) /* Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((u16)0x2000) /* Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((u16)0x4000) /* Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((u16)0x8000) /* Port output data, bit 15 */ + + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((u32)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((u32)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((u32)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((u32)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((u32)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((u32)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((u32)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((u32)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((u32)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((u32)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((u32)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((u32)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((u32)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((u32)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((u32)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((u32)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((u32)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((u32)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((u32)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((u32)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((u32)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((u32)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((u32)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((u32)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((u32)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((u32)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((u32)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((u32)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((u32)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((u32)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((u32)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((u32)0x80000000) /* Port x Reset bit 15 */ + + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((u16)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((u16)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((u16)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((u16)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((u16)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((u16)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((u16)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((u16)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((u16)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((u16)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((u16)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((u16)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((u16)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((u16)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((u16)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((u16)0x8000) /* Port x Reset bit 15 */ + + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((u32)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((u32)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((u32)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((u32)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((u32)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((u32)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((u32)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((u32)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((u32)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((u32)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((u32)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((u32)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((u32)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((u32)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((u32)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((u32)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((u32)0x00010000) /* Lock key */ + + +/*----------------------------------------------------------------------------*/ + + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((u8)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((u8)0x01) /* Bit 0 */ +#define AFIO_EVCR_PIN_1 ((u8)0x02) /* Bit 1 */ +#define AFIO_EVCR_PIN_2 ((u8)0x04) /* Bit 2 */ +#define AFIO_EVCR_PIN_3 ((u8)0x08) /* Bit 3 */ + +/* PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((u8)0x00) /* Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((u8)0x01) /* Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((u8)0x02) /* Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((u8)0x03) /* Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((u8)0x04) /* Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((u8)0x05) /* Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((u8)0x06) /* Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((u8)0x07) /* Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((u8)0x08) /* Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((u8)0x09) /* Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((u8)0x0A) /* Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((u8)0x0B) /* Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((u8)0x0C) /* Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((u8)0x0D) /* Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((u8)0x0E) /* Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((u8)0x0F) /* Pin 15 selected */ + +#define AFIO_EVCR_PORT ((u8)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((u8)0x10) /* Bit 0 */ +#define AFIO_EVCR_PORT_1 ((u8)0x20) /* Bit 1 */ +#define AFIO_EVCR_PORT_2 ((u8)0x40) /* Bit 2 */ + +/* PORT configuration */ +#define AFIO_EVCR_PORT_PA ((u8)0x00) /* Port A selected */ +#define AFIO_EVCR_PORT_PB ((u8)0x10) /* Port B selected */ +#define AFIO_EVCR_PORT_PC ((u8)0x20) /* Port C selected */ +#define AFIO_EVCR_PORT_PD ((u8)0x30) /* Port D selected */ +#define AFIO_EVCR_PORT_PE ((u8)0x40) /* Port E selected */ + +#define AFIO_EVCR_EVOE ((u8)0x80) /* Event Output Enable */ + + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1 _REMAP ((u32)0x00000001) /* SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((u32)0x00000002) /* I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((u32)0x00000004) /* USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((u32)0x00000008) /* USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((u32)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((u32)0x00000010) /* Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((u32)0x00000020) /* Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((u32)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((u32)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((u32)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((u32)0x00000040) /* Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((u32)0x00000080) /* Bit 1 */ + +/* TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((u32)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((u32)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((u32)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((u32)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((u32)0x00000100) /* Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((u32)0x00000200) /* Bit 1 */ + +/* TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((u32)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((u32)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((u32)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((u32)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((u32)0x00000400) /* Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((u32)0x00000800) /* Bit 1 */ + +/* TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((u32)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((u32)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((u32)0x00001000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +#define AFIO_MAPR_CAN_REMAP ((u32)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((u32)0x00002000) /* Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((u32)0x00004000) /* Bit 1 */ + +/* CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((u32)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((u32)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((u32)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((u32)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((u32)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((u32)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((u32)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((u32)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((u32)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_MAPR_SWJ_CFG ((u32)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((u32)0x01000000) /* Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((u32)0x02000000) /* Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((u32)0x04000000) /* Bit 2 */ + +/* SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_RESET ((u32)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((u32)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((u32)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((u32)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((u16)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((u16)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((u16)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((u16)0xF000) /* EXTI 3 configuration */ + +/* EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((u16)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((u16)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((u16)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((u16)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((u16)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((u16)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((u16)0x0006) /* PG[0] pin */ + +/* EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((u16)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((u16)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((u16)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((u16)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((u16)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((u16)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((u16)0x0060) /* PG[1] pin */ + +/* EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((u16)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((u16)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((u16)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((u16)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((u16)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((u16)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((u16)0x0600) /* PG[2] pin */ + +/* EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((u16)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((u16)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((u16)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((u16)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((u16)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((u16)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((u16)0x6000) /* PG[3] pin */ + + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((u16)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((u16)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((u16)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((u16)0xF000) /* EXTI 7 configuration */ + +/* EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((u16)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((u16)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((u16)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((u16)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((u16)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((u16)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((u16)0x0006) /* PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((u16)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((u16)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((u16)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((u16)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((u16)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((u16)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((u16)0x0060) /* PG[5] pin */ + +/* EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((u16)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((u16)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((u16)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((u16)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((u16)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((u16)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((u16)0x0600) /* PG[6] pin */ + +/* EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((u16)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((u16)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((u16)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((u16)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((u16)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((u16)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((u16)0x6000) /* PG[7] pin */ + + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((u16)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((u16)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((u16)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((u16)0xF000) /* EXTI 11 configuration */ + +/* EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((u16)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((u16)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((u16)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((u16)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((u16)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((u16)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((u16)0x0006) /* PG[8] pin */ + +/* EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((u16)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((u16)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((u16)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((u16)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((u16)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((u16)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((u16)0x0060) /* PG[9] pin */ + +/* EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((u16)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((u16)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((u16)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((u16)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((u16)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((u16)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((u16)0x0600) /* PG[10] pin */ + +/* EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((u16)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((u16)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((u16)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((u16)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((u16)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((u16)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((u16)0x6000) /* PG[11] pin */ + + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((u16)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((u16)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((u16)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((u16)0xF000) /* EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((u16)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((u16)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((u16)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((u16)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((u16)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((u16)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((u16)0x0006) /* PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((u16)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((u16)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((u16)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((u16)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((u16)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((u16)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((u16)0x0060) /* PG[13] pin */ + +/* EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((u16)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((u16)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((u16)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((u16)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((u16)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((u16)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((u16)0x0600) /* PG[14] pin */ + +/* EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((u16)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((u16)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((u16)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((u16)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((u16)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((u16)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((u16)0x6000) /* PG[15] pin */ + + + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */ +#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */ +#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */ + + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ + + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */ + + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */ + + + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((u32)0xFFFFFFFF) /* Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ISER_SETENA_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ISER_SETENA_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ISER_SETENA_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ISER_SETENA_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ISER_SETENA_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ISER_SETENA_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ISER_SETENA_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ISER_SETENA_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ISER_SETENA_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ISER_SETENA_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ISER_SETENA_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ISER_SETENA_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ISER_SETENA_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ISER_SETENA_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ISER_SETENA_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ISER_SETENA_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ISER_SETENA_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ISER_SETENA_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ISER_SETENA_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ISER_SETENA_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ISER_SETENA_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ISER_SETENA_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ISER_SETENA_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ISER_SETENA_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ISER_SETENA_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ISER_SETENA_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ISER_SETENA_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ISER_SETENA_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ISER_SETENA_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ISER_SETENA_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ISER_SETENA_31 ((u32)0x80000000) /* bit 31 */ + + + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((u32)0xFFFFFFFF) /* Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ICER_CLRENA_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ICER_CLRENA_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ICER_CLRENA_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ICER_CLRENA_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ICER_CLRENA_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ICER_CLRENA_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ICER_CLRENA_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ICER_CLRENA_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ICER_CLRENA_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ICER_CLRENA_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ICER_CLRENA_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ICER_CLRENA_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ICER_CLRENA_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ICER_CLRENA_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ICER_CLRENA_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ICER_CLRENA_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ICER_CLRENA_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ICER_CLRENA_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ICER_CLRENA_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ICER_CLRENA_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ICER_CLRENA_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ICER_CLRENA_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ICER_CLRENA_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ICER_CLRENA_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ICER_CLRENA_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ICER_CLRENA_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ICER_CLRENA_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ICER_CLRENA_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ICER_CLRENA_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ICER_CLRENA_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ICER_CLRENA_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((u32)0xFFFFFFFF) /* Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((u32)0xFFFFFFFF) /* Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((u32)0xFFFFFFFF) /* Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((u32)0x000000FF) /* Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((u32)0x0000FF00) /* Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((u32)0x00FF0000) /* Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((u32)0xFF000000) /* Priority of interrupt 3 */ + + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((u32)0x000000FF) /* Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((u32)0x0000FF00) /* Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((u32)0x00FF0000) /* Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((u32)0xFF000000) /* Priority of interrupt 7 */ + + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((u32)0x000000FF) /* Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((u32)0x0000FF00) /* Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((u32)0x00FF0000) /* Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((u32)0xFF000000) /* Priority of interrupt 11 */ + + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((u32)0x000000FF) /* Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((u32)0x0000FF00) /* Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((u32)0x00FF0000) /* Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((u32)0xFF000000) /* Priority of interrupt 15 */ + + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((u32)0x000000FF) /* Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((u32)0x0000FF00) /* Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((u32)0x00FF0000) /* Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((u32)0xFF000000) /* Priority of interrupt 19 */ + + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((u32)0x000000FF) /* Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((u32)0x0000FF00) /* Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((u32)0x00FF0000) /* Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((u32)0xFF000000) /* Priority of interrupt 23 */ + + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((u32)0x000000FF) /* Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((u32)0x0000FF00) /* Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((u32)0x00FF0000) /* Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((u32)0xFF000000) /* Priority of interrupt 27 */ + + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((u32)0x000000FF) /* Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((u32)0x0000FF00) /* Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((u32)0x00FF0000) /* Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((u32)0xFF000000) /* Priority of interrupt 31 */ + + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((u32)0x0000000F) /* Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((u32)0x0000FFF0) /* Number of processor within family */ +#define SCB_CPUID_Constant ((u32)0x000F0000) /* Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((u32)0x00F00000) /* Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((u32)0xFF000000) /* Implementer code. ARM is 0x41 */ + + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((u32)0x000001FF) /* Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((u32)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((u32)0x003FF000) /* Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((u32)0x00400000) /* Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((u32)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((u32)0x02000000) /* Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((u32)0x04000000) /* Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((u32)0x08000000) /* Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((u32)0x10000000) /* Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((u32)0x80000000) /* Set pending NMI bit */ + + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((u32)0x1FFFFF80) /* Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((u32)0x20000000) /* Table base in code(0) or RAM(1) */ + + +/****************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((u32)0x00000001) /* System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((u32)0x00000002) /* Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((u32)0x00000004) /* Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((u32)0x00000700) /* PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((u32)0x00000100) /* Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((u32)0x00000200) /* Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((u32)0x00000400) /* Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((u32)0x00000000) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((u32)0x00000100) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((u32)0x00000200) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((u32)0x00000300) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((u32)0x00000400) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((u32)0x00000500) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((u8)0x02) /* Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((u8)0x04) /* Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((u8)0x10) /* Wake up from WFE */ + + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((u16)0x0001) /* Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((u16)0x0002) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((u16)0x0008) /* Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((u16)0x0010) /* Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((u16)0x0100) /* Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((u16)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((u32)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((u32)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((u32)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((u32)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((u32)0x00000001) /* MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((u32)0x00000002) /* BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((u32)0x00000008) /* UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((u32)0x00000080) /* SVCall is active */ +#define SCB_SHCSR_MONITORACT ((u32)0x00000100) /* Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((u32)0x00000400) /* PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((u32)0x00000800) /* SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((u32)0x00001000) /* Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((u32)0x00002000) /* MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((u32)0x00004000) /* Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((u32)0x00008000) /* SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((u32)0x00010000) /* MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((u32)0x00020000) /* Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((u32)0x00040000) /* UsageFault enable */ + + +/******************* Bit definition for SCB_CFSR register *******************/ +/* MFSR */ +#define SCB_CFSR_IACCVIOL ((u32)0x00000001) /* Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((u32)0x00000002) /* Data access violation */ +#define SCB_CFSR_MUNSTKERR ((u32)0x00000008) /* Unstacking error */ +#define SCB_CFSR_MSTKERR ((u32)0x00000010) /* Stacking error */ +#define SCB_CFSR_MMARVALID ((u32)0x00000080) /* Memory Manage Address Register address valid flag */ +/* BFSR */ +#define SCB_CFSR_IBUSERR ((u32)0x00000100) /* Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((u32)0x00000200) /* Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((u32)0x00000400) /* Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((u32)0x00000800) /* Unstacking error */ +#define SCB_CFSR_STKERR ((u32)0x00001000) /* Stacking error */ +#define SCB_CFSR_BFARVALID ((u32)0x00008000) /* Bus Fault Address Register address valid flag */ +/* UFSR */ +#define SCB_CFSR_UNDEFINSTR ((u32)0x00010000) /* The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((u32)0x00020000) /* Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((u32)0x00040000) /* Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((u32)0x00080000) /* Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((u32)0x01000000) /* Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((u32)0x02000000) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((u32)0x00000002) /* Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((u32)0x40000000) /* Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((u32)0x80000000) /* Fault related to debug */ + + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((u8)0x01) /* Halt request flag */ +#define SCB_DFSR_BKPT ((u8)0x02) /* BKPT flag */ +#define SCB_DFSR_DWTTRAP ((u8)0x04) /* Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((u8)0x08) /* Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((u8)0x10) /* External debug request flag */ + + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((u32)0xFFFFFFFF) /* Mem Manage fault address field */ + + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((u32)0xFFFFFFFF) /* Bus fault address field */ + + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((u32)0xFFFFFFFF) /* Implementation defined */ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((u32)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((u32)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((u32)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((u32)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((u32)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((u32)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((u32)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((u32)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((u32)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((u32)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((u32)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((u32)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((u32)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((u32)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((u32)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((u32)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((u32)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((u32)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((u32)0x00040000) /* Interrupt Mask on line 18 */ + + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((u32)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((u32)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((u32)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((u32)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((u32)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((u32)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((u32)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((u32)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((u32)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((u32)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((u32)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((u32)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((u32)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((u32)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((u32)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((u32)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((u32)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((u32)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((u32)0x00040000) /* Event Mask on line 18 */ + + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((u32)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((u32)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((u32)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((u32)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((u32)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((u32)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((u32)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((u32)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((u32)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((u32)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((u32)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((u32)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((u32)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((u32)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((u32)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((u32)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((u32)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((u32)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((u32)0x00040000) /* Rising trigger event configuration bit of line 18 */ + + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((u32)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((u32)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((u32)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((u32)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((u32)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((u32)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((u32)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((u32)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((u32)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((u32)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((u32)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((u32)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((u32)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((u32)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((u32)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((u32)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((u32)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((u32)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((u32)0x00040000) /* Falling trigger event configuration bit of line 18 */ + + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((u32)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((u32)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((u32)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((u32)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((u32)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((u32)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((u32)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((u32)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((u32)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((u32)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((u32)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((u32)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((u32)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((u32)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((u32)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((u32)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((u32)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((u32)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((u32)0x00040000) /* Software Interrupt on line 18 */ + + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((u32)0x00000001) /* Pending bit 0 */ +#define EXTI_PR_PR1 ((u32)0x00000002) /* Pending bit 1 */ +#define EXTI_PR_PR2 ((u32)0x00000004) /* Pending bit 2 */ +#define EXTI_PR_PR3 ((u32)0x00000008) /* Pending bit 3 */ +#define EXTI_PR_PR4 ((u32)0x00000010) /* Pending bit 4 */ +#define EXTI_PR_PR5 ((u32)0x00000020) /* Pending bit 5 */ +#define EXTI_PR_PR6 ((u32)0x00000040) /* Pending bit 6 */ +#define EXTI_PR_PR7 ((u32)0x00000080) /* Pending bit 7 */ +#define EXTI_PR_PR8 ((u32)0x00000100) /* Pending bit 8 */ +#define EXTI_PR_PR9 ((u32)0x00000200) /* Pending bit 9 */ +#define EXTI_PR_PR10 ((u32)0x00000400) /* Pending bit 10 */ +#define EXTI_PR_PR11 ((u32)0x00000800) /* Pending bit 11 */ +#define EXTI_PR_PR12 ((u32)0x00001000) /* Pending bit 12 */ +#define EXTI_PR_PR13 ((u32)0x00002000) /* Pending bit 13 */ +#define EXTI_PR_PR14 ((u32)0x00004000) /* Pending bit 14 */ +#define EXTI_PR_PR15 ((u32)0x00008000) /* Pending bit 15 */ +#define EXTI_PR_PR16 ((u32)0x00010000) /* Pending bit 16 */ +#define EXTI_PR_PR17 ((u32)0x00020000) /* Pending bit 17 */ +#define EXTI_PR_PR18 ((u32)0x00040000) /* Trigger request occurred on the external interrupt line 18 */ + + + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((u32)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((u32)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((u32)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((u32)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((u32)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((u32)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((u32)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error flag */ + + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((u32)0x00000001) /* Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((u32)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((u32)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((u32)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((u32)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((u32)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((u32)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error clear */ + + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((u16)0x0001) /* Channel enable*/ +#define DMA_CCR1_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR1_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR1_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR1_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR1_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR1_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR1_PL ((u16)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR1_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR2_TCIE ((u16)0x0002) /* ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR2_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR2_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR2_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR2_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR2_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR2_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR2_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR3_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR3_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR3_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR3_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR3_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR3_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR3_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR3_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR4_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR4_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR4_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR4_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR4_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR4_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR4_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR4_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR5_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR5_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR5_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR5_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR5_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR5_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR5_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR5_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ + + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR6_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR6_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR6_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR6_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR6_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR6_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR6_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR6_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR7_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR7_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR7_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR7_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR7_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR7_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR7_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ + + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((u8)0x01) /* Analog watchdog flag */ +#define ADC_SR_EOC ((u8)0x02) /* End of conversion */ +#define ADC_SR_JEOC ((u8)0x04) /* Injected channel end of conversion */ +#define ADC_SR_JSTRT ((u8)0x08) /* Injected channel Start flag */ +#define ADC_SR_STRT ((u8)0x10) /* Regular channel Start flag */ + + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((u32)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_CR1_AWDCH_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_CR1_AWDCH_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_CR1_AWDCH_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_CR1_AWDCH_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_CR1_EOCIE ((u32)0x00000020) /* Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((u32)0x00000040) /* AAnalog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((u32)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((u32)0x00000100) /* Scan mode */ +#define ADC_CR1_AWDSGL ((u32)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((u32)0x00000400) /* Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((u32)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((u32)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((u32)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((u32)0x00002000) /* Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((u32)0x00004000) /* Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((u32)0x00008000) /* Bit 2 */ + +#define ADC_CR1_DUALMOD ((u32)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((u32)0x00010000) /* Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((u32)0x00020000) /* Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((u32)0x00040000) /* Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((u32)0x00080000) /* Bit 3 */ + +#define ADC_CR1_JAWDEN ((u32)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((u32)0x00800000) /* Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((u32)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((u32)0x00000002) /* Continuous Conversion */ +#define ADC_CR2_CAL ((u32)0x00000004) /* A/D Calibration */ +#define ADC_CR2_RSTCAL ((u32)0x00000008) /* Reset Calibration */ +#define ADC_CR2_DMA ((u32)0x00000100) /* Direct Memory access mode */ +#define ADC_CR2_ALIGN ((u32)0x00000800) /* Data Alignment */ + +#define ADC_CR2_JEXTSEL ((u32)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((u32)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((u32)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((u32)0x00020000) /* Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((u32)0x00040000) /* Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((u32)0x00080000) /* Bit 2 */ + +#define ADC_CR2_EXTTRIG ((u32)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((u32)0x00200000) /* Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((u32)0x00400000) /* Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((u32)0x00800000) /* Temperature Sensor and VREFINT Enable */ + + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((u32)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((u32)0x00000004) /* Bit 2 */ + +#define ADC_SMPR1_SMP11 ((u32)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((u32)0x00000008) /* Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((u32)0x00000010) /* Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((u32)0x00000020) /* Bit 2 */ + +#define ADC_SMPR1_SMP12 ((u32)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((u32)0x00000040) /* Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((u32)0x00000080) /* Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((u32)0x00000100) /* Bit 2 */ + +#define ADC_SMPR1_SMP13 ((u32)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((u32)0x00000200) /* Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((u32)0x00000400) /* Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((u32)0x00000800) /* Bit 2 */ + +#define ADC_SMPR1_SMP14 ((u32)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_SMPR1_SMP15 ((u32)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((u32)0x00020000) /* Bit 2 */ + +#define ADC_SMPR1_SMP16 ((u32)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((u32)0x00040000) /* Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((u32)0x00080000) /* Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((u32)0x00100000) /* Bit 2 */ + +#define ADC_SMPR1_SMP17 ((u32)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((u32)0x00200000) /* Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((u32)0x00400000) /* Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((u32)0x00800000) /* Bit 2 */ + + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((u32)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((u32)0x00000004) /* Bit 2 */ + +#define ADC_SMPR2_SMP1 ((u32)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((u32)0x00000008) /* Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((u32)0x00000010) /* Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((u32)0x00000020) /* Bit 2 */ + +#define ADC_SMPR2_SMP2 ((u32)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((u32)0x00000040) /* Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((u32)0x00000080) /* Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((u32)0x00000100) /* Bit 2 */ + +#define ADC_SMPR2_SMP3 ((u32)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((u32)0x00000200) /* Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((u32)0x00000400) /* Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((u32)0x00000800) /* Bit 2 */ + +#define ADC_SMPR2_SMP4 ((u32)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_SMPR2_SMP5 ((u32)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((u32)0x00020000) /* Bit 2 */ + +#define ADC_SMPR2_SMP6 ((u32)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((u32)0x00040000) /* Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((u32)0x00080000) /* Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((u32)0x00100000) /* Bit 2 */ + +#define ADC_SMPR2_SMP7 ((u32)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((u32)0x00200000) /* Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((u32)0x00400000) /* Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((u32)0x00800000) /* Bit 2 */ + +#define ADC_SMPR2_SMP8 ((u32)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((u32)0x01000000) /* Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((u32)0x02000000) /* Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((u32)0x04000000) /* Bit 2 */ + +#define ADC_SMPR2_SMP9 ((u32)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((u32)0x08000000) /* Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((u32)0x10000000) /* Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((u32)0x20000000) /* Bit 2 */ + + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((u16)0x0FFF) /* Data offset for injected channel 1 */ + + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((u16)0x0FFF) /* Data offset for injected channel 2 */ + + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((u16)0x0FFF) /* Data offset for injected channel 3 */ + + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((u16)0x0FFF) /* Data offset for injected channel 4 */ + + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((u16)0x0FFF) /* Analog watchdog high threshold */ + + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((u16)0x0FFF) /* Analog watchdog low threshold */ + + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((u32)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR1_SQ13_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR1_SQ13_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR1_SQ13_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR1_SQ13_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR1_SQ14 ((u32)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR1_SQ14_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR1_SQ14_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR1_SQ14_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR1_SQ14_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR1_SQ15 ((u32)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR1_SQ15_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR1_SQ15_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR1_SQ15_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR1_SQ15_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR1_SQ16 ((u32)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR1_SQ16_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR1_SQ16_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR1_SQ16_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR1_SQ16_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR1_L ((u32)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR1_L_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR1_L_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR1_L_3 ((u32)0x00800000) /* Bit 3 */ + + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((u32)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR2_SQ7_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR2_SQ7_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR2_SQ7_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR2_SQ7_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR2_SQ8 ((u32)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR2_SQ8_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR2_SQ8_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR2_SQ8_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR2_SQ8_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR2_SQ9 ((u32)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR2_SQ9_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR2_SQ9_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR2_SQ9_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR2_SQ9_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR2_SQ10 ((u32)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR2_SQ10_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR2_SQ10_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR2_SQ10_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR2_SQ10_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR2_SQ11 ((u32)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR2_SQ11_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR2_SQ11_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR2_SQ11_3 ((u32)0x00800000) /* Bit 3 */ +#define ADC_SQR2_SQ11_4 ((u32)0x01000000) /* Bit 4 */ + +#define ADC_SQR2_SQ12 ((u32)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((u32)0x02000000) /* Bit 0 */ +#define ADC_SQR2_SQ12_1 ((u32)0x04000000) /* Bit 1 */ +#define ADC_SQR2_SQ12_2 ((u32)0x08000000) /* Bit 2 */ +#define ADC_SQR2_SQ12_3 ((u32)0x10000000) /* Bit 3 */ +#define ADC_SQR2_SQ12_4 ((u32)0x20000000) /* Bit 4 */ + + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((u32)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR3_SQ1_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR3_SQ1_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR3_SQ1_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR3_SQ1_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR3_SQ2 ((u32)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR3_SQ2_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR3_SQ2_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR3_SQ2_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR3_SQ2_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR3_SQ3 ((u32)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR3_SQ3_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR3_SQ3_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR3_SQ3_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR3_SQ3_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR3_SQ4 ((u32)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR3_SQ4_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR3_SQ4_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR3_SQ4_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR3_SQ4_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR3_SQ5 ((u32)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR3_SQ5_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR3_SQ5_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR3_SQ5_3 ((u32)0x00800000) /* Bit 3 */ +#define ADC_SQR3_SQ5_4 ((u32)0x01000000) /* Bit 4 */ + +#define ADC_SQR3_SQ6 ((u32)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((u32)0x02000000) /* Bit 0 */ +#define ADC_SQR3_SQ6_1 ((u32)0x04000000) /* Bit 1 */ +#define ADC_SQR3_SQ6_2 ((u32)0x08000000) /* Bit 2 */ +#define ADC_SQR3_SQ6_3 ((u32)0x10000000) /* Bit 3 */ +#define ADC_SQR3_SQ6_4 ((u32)0x20000000) /* Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((u32)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_JSQR_JSQ2 ((u32)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_JSQR_JSQ3 ((u32)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_JSQR_JSQ4 ((u32)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_JSQR_JL ((u32)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_JSQR_JL_1 ((u32)0x00200000) /* Bit 1 */ + + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((u32)0x0000FFFF) /* Regular data */ +#define ADC_DR_ADC2DATA ((u32)0xFFFF0000) /* ADC2 data */ + + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((u32)0x00000001) /* DAC channel1 enable */ +#define DAC_CR_BOFF1 ((u32)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((u32)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((u32)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((u32)0x00000008) /* Bit 0 */ +#define DAC_CR_TSEL1_1 ((u32)0x00000010) /* Bit 1 */ +#define DAC_CR_TSEL1_2 ((u32)0x00000020) /* Bit 2 */ + +#define DAC_CR_WAVE1 ((u32)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((u32)0x00000040) /* Bit 0 */ +#define DAC_CR_WAVE1_1 ((u32)0x00000080) /* Bit 1 */ + +#define DAC_CR_MAMP1 ((u32)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((u32)0x00000100) /* Bit 0 */ +#define DAC_CR_MAMP1_1 ((u32)0x00000200) /* Bit 1 */ +#define DAC_CR_MAMP1_2 ((u32)0x00000400) /* Bit 2 */ +#define DAC_CR_MAMP1_3 ((u32)0x00000800) /* Bit 3 */ + +#define DAC_CR_DMAEN1 ((u32)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((u32)0x00010000) /* DAC channel2 enable */ +#define DAC_CR_BOFF2 ((u32)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((u32)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((u32)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((u32)0x00080000) /* Bit 0 */ +#define DAC_CR_TSEL2_1 ((u32)0x00100000) /* Bit 1 */ +#define DAC_CR_TSEL2_2 ((u32)0x00200000) /* Bit 2 */ + +#define DAC_CR_WAVE2 ((u32)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((u32)0x00400000) /* Bit 0 */ +#define DAC_CR_WAVE2_1 ((u32)0x00800000) /* Bit 1 */ + +#define DAC_CR_MAMP2 ((u32)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((u32)0x01000000) /* Bit 0 */ +#define DAC_CR_MAMP2_1 ((u32)0x02000000) /* Bit 1 */ +#define DAC_CR_MAMP2_2 ((u32)0x04000000) /* Bit 2 */ +#define DAC_CR_MAMP2_3 ((u32)0x08000000) /* Bit 3 */ + +#define DAC_CR_DMAEN2 ((u32)0x10000000) /* DAC channel2 DMA enabled */ + + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((u8)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((u8)0x02) /* DAC channel2 software trigger */ + + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((u16)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((u16)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((u8)0xFF) /* DAC channel1 8-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((u16)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((u16)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((u8)0xFF) /* DAC channel2 8-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((u32)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((u32)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((u32)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((u32)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((u16)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((u16)0xFF00) /* DAC channel2 8-bit Right aligned data */ + + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((u16)0x0FFF) /* DAC channel1 data output */ + + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((u16)0x0FFF) /* DAC channel2 data output */ + + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((u16)0x0001) /* Counter enable */ +#define TIM_CR1_UDIS ((u16)0x0002) /* Update disable */ +#define TIM_CR1_URS ((u16)0x0004) /* Update request source */ +#define TIM_CR1_OPM ((u16)0x0008) /* One pulse mode */ +#define TIM_CR1_DIR ((u16)0x0010) /* Direction */ + +#define TIM_CR1_CMS ((u16)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((u16)0x0020) /* Bit 0 */ +#define TIM_CR1_CMS_1 ((u16)0x0040) /* Bit 1 */ + +#define TIM_CR1_ARPE ((u16)0x0080) /* Auto-reload preload enable */ + +#define TIM_CR1_CKD ((u16)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CR1_CKD_1 ((u16)0x0200) /* Bit 1 */ + + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((u16)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((u16)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((u16)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((u16)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CR2_MMS_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CR2_MMS_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CR2_TI1S ((u16)0x0080) /* TI1 Selection */ +#define TIM_CR2_OIS1 ((u16)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((u16)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((u16)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((u16)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((u16)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((u16)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((u16)0x4000) /* Output Idle state 4 (OC4 output) */ + + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((u16)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_SMCR_SMS_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_SMCR_SMS_2 ((u16)0x0004) /* Bit 2 */ + +#define TIM_SMCR_TS ((u16)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_SMCR_TS_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_SMCR_TS_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_SMCR_MSM ((u16)0x0080) /* Master/slave mode */ + +#define TIM_SMCR_ETF ((u16)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_SMCR_ETF_1 ((u16)0x0200) /* Bit 1 */ +#define TIM_SMCR_ETF_2 ((u16)0x0400) /* Bit 2 */ +#define TIM_SMCR_ETF_3 ((u16)0x0800) /* Bit 3 */ + +#define TIM_SMCR_ETPS ((u16)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_SMCR_ETPS_1 ((u16)0x2000) /* Bit 1 */ + +#define TIM_SMCR_ECE ((u16)0x4000) /* External clock enable */ +#define TIM_SMCR_ETP ((u16)0x8000) /* External trigger polarity */ + + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((u16)0x0001) /* Update interrupt enable */ +#define TIM_DIER_CC1IE ((u16)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((u16)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((u16)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((u16)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((u16)0x0020) /* COM interrupt enable */ +#define TIM_DIER_TIE ((u16)0x0040) /* Trigger interrupt enable */ +#define TIM_DIER_BIE ((u16)0x0080) /* Break interrupt enable */ +#define TIM_DIER_UDE ((u16)0x0100) /* Update DMA request enable */ +#define TIM_DIER_CC1DE ((u16)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((u16)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((u16)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((u16)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((u16)0x2000) /* COM DMA request enable */ +#define TIM_DIER_TDE ((u16)0x4000) /* Trigger DMA request enable */ + + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((u16)0x0001) /* Update interrupt Flag */ +#define TIM_SR_CC1IF ((u16)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((u16)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((u16)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((u16)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((u16)0x0020) /* COM interrupt Flag */ +#define TIM_SR_TIF ((u16)0x0040) /* Trigger interrupt Flag */ +#define TIM_SR_BIF ((u16)0x0080) /* Break interrupt Flag */ +#define TIM_SR_CC1OF ((u16)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((u16)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((u16)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((u16)0x1000) /* Capture/Compare 4 Overcapture Flag */ + + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((u8)0x01) /* Update Generation */ +#define TIM_EGR_CC1G ((u8)0x02) /* Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((u8)0x04) /* Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((u8)0x08) /* Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((u8)0x10) /* Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((u8)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((u8)0x40) /* Trigger Generation */ +#define TIM_EGR_BG ((u8)0x80) /* Break Generation */ + + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((u16)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((u16)0x0002) /* Bit 1 */ + +#define TIM_CCMR1_OC1FE ((u16)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((u16)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((u16)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CCMR1_OC1CE ((u16)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((u16)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_CCMR1_OC2FE ((u16)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((u16)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((u16)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((u16)0x4000) /* Bit 2 */ + +#define TIM_CCMR1_OC2CE ((u16)0x8000) /* Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((u16)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((u16)0x0004) /* Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((u16)0x0008) /* Bit 1 */ + +#define TIM_CCMR1_IC1F ((u16)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((u16)0x0040) /* Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((u16)0x0080) /* Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((u16)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((u16)0x0400) /* Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((u16)0x0800) /* Bit 1 */ + +#define TIM_CCMR1_IC2F ((u16)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((u16)0x4000) /* Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((u16)0x8000) /* Bit 3 */ + + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((u16)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((u16)0x0002) /* Bit 1 */ + +#define TIM_CCMR2_OC3FE ((u16)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((u16)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((u16)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CCMR2_OC3CE ((u16)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((u16)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_CCMR2_OC4FE ((u16)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((u16)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((u16)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((u16)0x4000) /* Bit 2 */ + +#define TIM_CCMR2_OC4CE ((u16)0x8000) /* Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((u16)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((u16)0x0004) /* Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((u16)0x0008) /* Bit 1 */ + +#define TIM_CCMR2_IC3F ((u16)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((u16)0x0040) /* Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((u16)0x0080) /* Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((u16)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((u16)0x0400) /* Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((u16)0x0800) /* Bit 1 */ + +#define TIM_CCMR2_IC4F ((u16)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((u16)0x4000) /* Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((u16)0x8000) /* Bit 3 */ + + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((u16)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((u16)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((u16)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((u16)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((u16)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((u16)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((u16)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((u16)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((u16)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((u16)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((u16)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((u16)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((u16)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((u16)0x2000) /* Capture/Compare 4 output Polarity */ + + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((u16)0xFFFF) /* Counter Value */ + + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((u16)0xFFFF) /* Prescaler Value */ + + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((u16)0xFFFF) /* actual auto-reload Value */ + + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((u8)0xFF) /* Repetition Counter Value */ + + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((u16)0xFFFF) /* Capture/Compare 1 Value */ + + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((u16)0xFFFF) /* Capture/Compare 2 Value */ + + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((u16)0xFFFF) /* Capture/Compare 3 Value */ + + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((u16)0xFFFF) /* Capture/Compare 4 Value */ + + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((u16)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_BDTR_DTG_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_BDTR_DTG_2 ((u16)0x0004) /* Bit 2 */ +#define TIM_BDTR_DTG_3 ((u16)0x0008) /* Bit 3 */ +#define TIM_BDTR_DTG_4 ((u16)0x0010) /* Bit 4 */ +#define TIM_BDTR_DTG_5 ((u16)0x0020) /* Bit 5 */ +#define TIM_BDTR_DTG_6 ((u16)0x0040) /* Bit 6 */ +#define TIM_BDTR_DTG_7 ((u16)0x0080) /* Bit 7 */ + +#define TIM_BDTR_LOCK ((u16)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_BDTR_LOCK_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_BDTR_OSSI ((u16)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((u16)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((u16)0x1000) /* Break enable */ +#define TIM_BDTR_BKP ((u16)0x2000) /* Break Polarity */ +#define TIM_BDTR_AOE ((u16)0x4000) /* Automatic Output enable */ +#define TIM_BDTR_MOE ((u16)0x8000) /* Main Output enable */ + + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((u16)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_DCR_DBA_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_DCR_DBA_2 ((u16)0x0004) /* Bit 2 */ +#define TIM_DCR_DBA_3 ((u16)0x0008) /* Bit 3 */ +#define TIM_DCR_DBA_4 ((u16)0x0010) /* Bit 4 */ + +#define TIM_DCR_DBL ((u16)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_DCR_DBL_1 ((u16)0x0200) /* Bit 1 */ +#define TIM_DCR_DBL_2 ((u16)0x0400) /* Bit 2 */ +#define TIM_DCR_DBL_3 ((u16)0x0800) /* Bit 3 */ +#define TIM_DCR_DBL_4 ((u16)0x1000) /* Bit 4 */ + + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((u16)0xFFFF) /* DMA register for burst accesses */ + + + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((u8)0x01) /* Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((u8)0x02) /* Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((u8)0x04) /* OverfloW Interrupt Enable */ + + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((u8)0x01) /* Second Flag */ +#define RTC_CRL_ALRF ((u8)0x02) /* Alarm Flag */ +#define RTC_CRL_OWF ((u8)0x04) /* OverfloW Flag */ +#define RTC_CRL_RSF ((u8)0x08) /* Registers Synchronized Flag */ +#define RTC_CRL_CNF ((u8)0x10) /* Configuration Flag */ +#define RTC_CRL_RTOFF ((u8)0x20) /* RTC operation OFF */ + + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((u16)0x000F) /* RTC Prescaler Reload Value High */ + + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((u16)0xFFFF) /* RTC Prescaler Reload Value Low */ + + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((u16)0x000F) /* RTC Clock Divider High */ + + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((u16)0xFFFF) /* RTC Clock Divider Low */ + + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((u16)0xFFFF) /* RTC Counter High */ + + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((u16)0xFFFF) /* RTC Counter Low */ + + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((u16)0xFFFF) /* RTC Alarm High */ + + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((u16)0xFFFF) /* RTC Alarm Low */ + + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((u16)0xFFFF) /* Key value (write only, read 0000h) */ + + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((u8)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((u8)0x01) /* Bit 0 */ +#define IWDG_PR_PR_1 ((u8)0x02) /* Bit 1 */ +#define IWDG_PR_PR_2 ((u8)0x04) /* Bit 2 */ + + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((u16)0x0FFF) /* Watchdog counter reload value */ + + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((u8)0x01) /* Watchdog prescaler value update */ +#define IWDG_SR_RVU ((u8)0x02) /* Watchdog counter reload value update */ + + + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((u8)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((u8)0x01) /* Bit 0 */ +#define WWDG_CR_T1 ((u8)0x02) /* Bit 1 */ +#define WWDG_CR_T2 ((u8)0x04) /* Bit 2 */ +#define WWDG_CR_T3 ((u8)0x08) /* Bit 3 */ +#define WWDG_CR_T4 ((u8)0x10) /* Bit 4 */ +#define WWDG_CR_T5 ((u8)0x20) /* Bit 5 */ +#define WWDG_CR_T6 ((u8)0x40) /* Bit 6 */ + +#define WWDG_CR_WDGA ((u8)0x80) /* Activation bit */ + + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((u16)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((u16)0x0001) /* Bit 0 */ +#define WWDG_CFR_W1 ((u16)0x0002) /* Bit 1 */ +#define WWDG_CFR_W2 ((u16)0x0004) /* Bit 2 */ +#define WWDG_CFR_W3 ((u16)0x0008) /* Bit 3 */ +#define WWDG_CFR_W4 ((u16)0x0010) /* Bit 4 */ +#define WWDG_CFR_W5 ((u16)0x0020) /* Bit 5 */ +#define WWDG_CFR_W6 ((u16)0x0040) /* Bit 6 */ + +#define WWDG_CFR_WDGTB ((u16)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((u16)0x0080) /* Bit 0 */ +#define WWDG_CFR_WDGTB1 ((u16)0x0100) /* Bit 1 */ + +#define WWDG_CFR_EWI ((u16)0x0200) /* Early Wakeup Interrupt */ + + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((u8)0x01) /* Early Wakeup Interrupt Flag */ + + + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR1_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR1_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR1_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR1_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR1_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR1_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR1_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR2_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR2_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR2_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR2_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR2_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR2_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR2_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR3_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR3_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR3_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR3_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR3_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR3_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR3_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR4_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR4_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR4_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR4_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR4_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR4_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR4_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR2_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR2_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR2_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR2_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR2_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR2_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR2_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR2_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR2_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR2_ECCPS ((u32)0x000E0000) /* ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR3_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR3_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR3_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR3_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR3_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR3_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR3_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR3_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR3_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR3_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR4_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR4_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR4_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR4_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR4_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR4_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR4_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR4_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR4_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR4_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR2_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((u8)0x40) /* FIFO empty */ + + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR3_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((u8)0x40) /* FIFO empty */ + + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR4_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((u8)0x40) /* FIFO empty */ + + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((u32)0x000000FF) /* MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((u32)0x0000FF00) /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((u32)0x00FF0000) /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((u32)0xFF000000) /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((u32)0x000000FF) /* MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((u32)0x0000FF00) /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((u32)0x00FF0000) /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((u32)0xFF000000) /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((u32)0x000000FF) /* MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((u32)0x0000FF00) /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((u32)0x00FF0000) /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((u32)0xFF000000) /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((u32)0x000000FF) /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((u32)0x0000FF00) /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((u32)0x00FF0000) /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((u32)0xFF000000) /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((u32)0x000000FF) /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((u32)0x0000FF00) /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((u32)0x00FF0000) /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((u32)0xFF000000) /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((u32)0x000000FF) /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((u32)0x0000FF00) /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((u32)0x00FF0000) /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((u32)0xFF000000) /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((u32)0x000000FF) /* IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((u32)0x0000FF00) /* IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((u32)0x00FF0000) /* IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((u32)0xFF000000) /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((u32)0xFFFFFFFF) /* ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((u32)0xFFFFFFFF) /* ECC result */ + + + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((u8)0x03) /* PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((u8)0x01) /* Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((u8)0x02) /* Bit 1 */ + + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((u16)0x00FF) /* Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((u16)0x0100) /* Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((u16)0x0200) /* Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((u16)0x0400) /* Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((u16)0x1800) /* WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((u16)0x0800) /* Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((u16)0x1000) /* Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((u16)0x2000) /* SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((u16)0x4000) /* HW Flow Control enable */ + + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((u32)0xFFFFFFFF) /* Command argument */ + + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((u16)0x003F) /* Command Index */ + +#define SDIO_CMD_WAITRESP ((u16)0x00C0) /* WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((u16)0x0040) /* Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((u16)0x0080) /* Bit 1 */ + +#define SDIO_CMD_WAITINT ((u16)0x0100) /* CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((u16)0x0200) /* CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((u16)0x0400) /* Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((u16)0x0800) /* SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((u16)0x1000) /* Enable CMD completion */ +#define SDIO_CMD_NIEN ((u16)0x2000) /* Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((u16)0x4000) /* CE-ATA command */ + + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((u8)0x3F) /* Response command index */ + + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((u32)0xFFFFFFFF) /* Data timeout period. */ + + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((u32)0x01FFFFFF) /* Data length value */ + + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((u16)0x0001) /* Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((u16)0x0002) /* Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((u16)0x0004) /* Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((u16)0x0008) /* DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((u16)0x00F0) /* DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((u16)0x0010) /* Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((u16)0x0020) /* Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((u16)0x0040) /* Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((u16)0x0080) /* Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((u16)0x0100) /* Read wait start */ +#define SDIO_DCTRL_RWSTOP ((u16)0x0200) /* Read wait stop */ +#define SDIO_DCTRL_RWMOD ((u16)0x0400) /* Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((u16)0x0800) /* SD I/O enable functions */ + + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((u32)0x01FFFFFF) /* Data count value */ + + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((u32)0x00000001) /* Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((u32)0x00000002) /* Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((u32)0x00000004) /* Command response timeout */ +#define SDIO_STA_DTIMEOUT ((u32)0x00000008) /* Data timeout */ +#define SDIO_STA_TXUNDERR ((u32)0x00000010) /* Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((u32)0x00000020) /* Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((u32)0x00000040) /* Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((u32)0x00000080) /* Command sent (no response required) */ +#define SDIO_STA_DATAEND ((u32)0x00000100) /* Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((u32)0x00000200) /* Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((u32)0x00000400) /* Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((u32)0x00000800) /* Command transfer in progress */ +#define SDIO_STA_TXACT ((u32)0x00001000) /* Data transmit in progress */ +#define SDIO_STA_RXACT ((u32)0x00002000) /* Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((u32)0x00004000) /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((u32)0x00008000) /* Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((u32)0x00010000) /* Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((u32)0x00020000) /* Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((u32)0x00040000) /* Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((u32)0x00080000) /* Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((u32)0x00100000) /* Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((u32)0x00200000) /* Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((u32)0x00400000) /* SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((u32)0x00800000) /* CE-ATA command completion signal received for CMD61 */ + + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((u32)0x00000001) /* CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((u32)0x00000002) /* DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((u32)0x00000004) /* CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((u32)0x00000008) /* DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((u32)0x00000010) /* TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((u32)0x00000020) /* RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((u32)0x00000040) /* CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((u32)0x00000080) /* CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((u32)0x00000100) /* DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((u32)0x00000200) /* STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((u32)0x00000400) /* DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((u32)0x00400000) /* SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((u32)0x00800000) /* CEATAEND flag clear bit */ + + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((u32)0x00000001) /* Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((u32)0x00000002) /* Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((u32)0x00000004) /* Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((u32)0x00000008) /* Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((u32)0x00000010) /* Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((u32)0x00000020) /* Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((u32)0x00000040) /* Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((u32)0x00000080) /* Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((u32)0x00000100) /* Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((u32)0x00000200) /* Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((u32)0x00000400) /* Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((u32)0x00000800) /* CCommand Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((u32)0x00001000) /* Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((u32)0x00002000) /* Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((u32)0x00004000) /* Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((u32)0x00008000) /* Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((u32)0x00010000) /* Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((u32)0x00020000) /* Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((u32)0x00040000) /* Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((u32)0x00080000) /* Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((u32)0x00100000) /* Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((u32)0x00200000) /* Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((u32)0x00400000) /* SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((u32)0x00800000) /* CE-ATA command completion signal received Interrupt Enable */ + + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((u32)0x00FFFFFF) /* Remaining number of words to be written to or read from the FIFO */ + + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((u32)0xFFFFFFFF) /* Receive and transmit FIFO data */ + + + +/******************************************************************************/ +/* */ +/* USB */ +/* */ +/******************************************************************************/ + +/* Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP0R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP0R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP0R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP0R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP1R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP1R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP1R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP1R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP2R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP2R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP2R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP2R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP3R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP3R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP3R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP3R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP4R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP4R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP4R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP4R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP5R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP5R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP5R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP5R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP6R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP6R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP6R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP6R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP7R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP7R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP7R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP7R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/* Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((u16)0x0001) /* Force USB Reset */ +#define USB_CNTR_PDWN ((u16)0x0002) /* Power down */ +#define USB_CNTR_LP_MODE ((u16)0x0004) /* Low-power mode */ +#define USB_CNTR_FSUSP ((u16)0x0008) /* Force suspend */ +#define USB_CNTR_RESUME ((u16)0x0010) /* Resume request */ +#define USB_CNTR_ESOFM ((u16)0x0100) /* Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((u16)0x0200) /* Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((u16)0x0400) /* RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((u16)0x0800) /* Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((u16)0x1000) /* Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((u16)0x2000) /* Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((u16)0x4000) /* Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((u16)0x8000) /* Correct Transfer Interrupt Mask */ + + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((u16)0x000F) /* Endpoint Identifier */ +#define USB_ISTR_DIR ((u16)0x0010) /* Direction of transaction */ +#define USB_ISTR_ESOF ((u16)0x0100) /* Expected Start Of Frame */ +#define USB_ISTR_SOF ((u16)0x0200) /* Start Of Frame */ +#define USB_ISTR_RESET ((u16)0x0400) /* USB RESET request */ +#define USB_ISTR_SUSP ((u16)0x0800) /* Suspend mode request */ +#define USB_ISTR_WKUP ((u16)0x1000) /* Wake up */ +#define USB_ISTR_ERR ((u16)0x2000) /* Error */ +#define USB_ISTR_PMAOVR ((u16)0x4000) /* Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((u16)0x8000) /* Correct Transfer */ + + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((u16)0x07FF) /* Frame Number */ +#define USB_FNR_LSOF ((u16)0x1800) /* Lost SOF */ +#define USB_FNR_LCK ((u16)0x2000) /* Locked */ +#define USB_FNR_RXDM ((u16)0x4000) /* Receive Data - Line Status */ +#define USB_FNR_RXDP ((u16)0x8000) /* Receive Data + Line Status */ + + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((u8)0x7F) /* ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((u8)0x01) /* Bit 0 */ +#define USB_DADDR_ADD1 ((u8)0x02) /* Bit 1 */ +#define USB_DADDR_ADD2 ((u8)0x04) /* Bit 2 */ +#define USB_DADDR_ADD3 ((u8)0x08) /* Bit 3 */ +#define USB_DADDR_ADD4 ((u8)0x10) /* Bit 4 */ +#define USB_DADDR_ADD5 ((u8)0x20) /* Bit 5 */ +#define USB_DADDR_ADD6 ((u8)0x40) /* Bit 6 */ + +#define USB_DADDR_EF ((u8)0x80) /* Enable Function */ + + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((u16)0xFFF8) /* Buffer Table */ + + +/* Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((u16)0xFFFE) /* Transmission Buffer Address 0 */ + + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((u16)0xFFFE) /* Transmission Buffer Address 1 */ + + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((u16)0xFFFE) /* Transmission Buffer Address 2 */ + + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((u16)0xFFFE) /* Transmission Buffer Address 3 */ + + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((u16)0xFFFE) /* Transmission Buffer Address 4 */ + + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((u16)0xFFFE) /* Transmission Buffer Address 5 */ + + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((u16)0xFFFE) /* Transmission Buffer Address 6 */ + + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((u16)0xFFFE) /* Transmission Buffer Address 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((u16)0x03FF) /* Transmission Byte Count 0 */ + + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((u16)0x03FF) /* Transmission Byte Count 1 */ + + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((u16)0x03FF) /* Transmission Byte Count 2 */ + + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((u16)0x03FF) /* Transmission Byte Count 3 */ + + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((u16)0x03FF) /* Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((u16)0x03FF) /* Transmission Byte Count 5 */ + + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((u16)0x03FF) /* Transmission Byte Count 6 */ + + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((u16)0x03FF) /* Transmission Byte Count 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 0 (high) */ + + + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 1 (high) */ + + + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 2 (high) */ + + + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((u16)0x000003FF) /* Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((u16)0x03FF0000) /* Transmission Byte Count 3 (high) */ + + + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 4 (high) */ + + + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 5 (high) */ + + + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 6 (high) */ + + + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 7 (high) */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((u16)0xFFFE) /* Reception Buffer Address 0 */ + + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((u16)0xFFFE) /* Reception Buffer Address 1 */ + + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((u16)0xFFFE) /* Reception Buffer Address 2 */ + + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((u16)0xFFFE) /* Reception Buffer Address 3 */ + + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((u16)0xFFFE) /* Reception Buffer Address 4 */ + + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((u16)0xFFFE) /* Reception Buffer Address 5 */ + + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((u16)0xFFFE) /* Reception Buffer Address 6 */ + + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((u16)0xFFFE) /* Reception Buffer Address 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/*----------------------------------------------------------------------------*/ + + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/* CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((u16)0x0001) /* Initialization Request */ +#define CAN_MCR_SLEEP ((u16)0x0002) /* Sleep Mode Request */ +#define CAN_MCR_TXFP ((u16)0x0004) /* Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((u16)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((u16)0x0010) /* No Automatic Retransmission */ +#define CAN_MCR_AWUM ((u16)0x0020) /* Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((u16)0x0040) /* Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((u16)0x0080) /* Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((u16)0x8000) /* bxCAN software master reset */ + + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((u16)0x0001) /* Initialization Acknowledge */ +#define CAN_MSR_SLAK ((u16)0x0002) /* Sleep Acknowledge */ +#define CAN_MSR_ERRI ((u16)0x0004) /* Error Interrupt */ +#define CAN_MSR_WKUI ((u16)0x0008) /* Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((u16)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((u16)0x0100) /* Transmit Mode */ +#define CAN_MSR_RXM ((u16)0x0200) /* Receive Mode */ +#define CAN_MSR_SAMP ((u16)0x0400) /* Last Sample Point */ +#define CAN_MSR_RX ((u16)0x0800) /* CAN Rx Signal */ + + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((u32)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((u32)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((u32)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((u32)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((u32)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((u32)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((u32)0x03000000) /* Mailbox Code */ + +#define CAN_TSR_TME ((u32)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((u32)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((u32)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((u32)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((u32)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((u8)0x03) /* FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((u8)0x08) /* FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((u8)0x10) /* FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((u8)0x20) /* Release FIFO 0 Output Mailbox */ + + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((u8)0x03) /* FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((u8)0x08) /* FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((u8)0x10) /* FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((u8)0x20) /* Release FIFO 1 Output Mailbox */ + + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((u32)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((u32)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((u32)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((u32)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((u32)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((u32)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((u32)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((u32)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((u32)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((u32)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((u32)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((u32)0x00008000) /* Error Interrupt Enable */ +#define CAN_IER_WKUIE ((u32)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((u32)0x00020000) /* Sleep Interrupt Enable */ + + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((u32)0x00000001) /* Error Warning Flag */ +#define CAN_ESR_EPVF ((u32)0x00000002) /* Error Passive Flag */ +#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-Off Flag */ + +#define CAN_ESR_LEC ((u32)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((u32)0x00000010) /* Bit 0 */ +#define CAN_ESR_LEC_1 ((u32)0x00000020) /* Bit 1 */ +#define CAN_ESR_LEC_2 ((u32)0x00000040) /* Bit 2 */ + +#define CAN_ESR_TEC ((u32)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((u32)0xFF000000) /* Receive Error Counter */ + + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((u32)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((u32)0x000F0000) /* Time Segment 1 */ +#define CAN_BTR_TS2 ((u32)0x00700000) /* Time Segment 2 */ +#define CAN_BTR_SJW ((u32)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((u32)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((u32)0x80000000) /* Silent Mode */ + + +/* Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI0R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_TI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT0R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI1R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI1R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_TI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT1R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI2R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI2R_EXID ((u32)0x001FFFF8) /* Extended identifier */ +#define CAN_TI2R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT2R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT2R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL2R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL2R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL2R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH2R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH2R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH2R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_RI0R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_RI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_RI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_RDT0R_FMI ((u32)0x0000FF00) /* Filter Match Index */ +#define CAN_RDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_RDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_RDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_RDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_RDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_RDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_RDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_RI1R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_RI1R_EXID ((u32)0x001FFFF8) /* Extended identifier */ +#define CAN_RI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_RDT1R_FMI ((u32)0x0000FF00) /* Filter Match Index */ +#define CAN_RDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_RDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_RDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_RDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_RDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_RDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_RDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + +/* CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((u8)0x01) /* Filter Init Mode */ + + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((u16)0x3FFF) /* Filter Mode */ +#define CAN_FM1R_FBM0 ((u16)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((u16)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((u16)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((u16)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((u16)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((u16)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((u16)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((u16)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((u16)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((u16)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((u16)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((u16)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((u16)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((u16)0x2000) /* Filter Init Mode bit 13 */ + + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((u16)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((u16)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((u16)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((u16)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((u16)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((u16)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((u16)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((u16)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((u16)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((u16)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((u16)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((u16)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((u16)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((u16)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((u16)0x2000) /* Filter Scale Configuration bit 13 */ + + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((u16)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((u16)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((u16)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((u16)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((u16)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((u16)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((u16)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((u16)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((u16)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((u16)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((u16)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((u16)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((u16)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((u16)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((u16)0x2000) /* Filter FIFO Assignment for Filter 13 */ + + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((u16)0x3FFF) /* Filter Active */ +#define CAN_FA1R_FACT0 ((u16)0x0001) /* Filter 0 Active */ +#define CAN_FA1R_FACT1 ((u16)0x0002) /* Filter 1 Active */ +#define CAN_FA1R_FACT2 ((u16)0x0004) /* Filter 2 Active */ +#define CAN_FA1R_FACT3 ((u16)0x0008) /* Filter 3 Active */ +#define CAN_FA1R_FACT4 ((u16)0x0010) /* Filter 4 Active */ +#define CAN_FA1R_FACT5 ((u16)0x0020) /* Filter 5 Active */ +#define CAN_FA1R_FACT6 ((u16)0x0040) /* Filter 6 Active */ +#define CAN_FA1R_FACT7 ((u16)0x0080) /* Filter 7 Active */ +#define CAN_FA1R_FACT8 ((u16)0x0100) /* Filter 8 Active */ +#define CAN_FA1R_FACT9 ((u16)0x0200) /* Filter 9 Active */ +#define CAN_FA1R_FACT10 ((u16)0x0400) /* Filter 10 Active */ +#define CAN_FA1R_FACT11 ((u16)0x0800) /* Filter 11 Active */ +#define CAN_FA1R_FACT12 ((u16)0x1000) /* Filter 12 Active */ +#define CAN_FA1R_FACT13 ((u16)0x2000) /* Filter 13 Active */ + + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((u16)0x0001) /* Clock Phase */ +#define SPI_CR1_CPOL ((u16)0x0002) /* Clock Polarity */ +#define SPI_CR1_MSTR ((u16)0x0004) /* Master Selection */ + +#define SPI_CR1_BR ((u16)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((u16)0x0008) /* Bit 0 */ +#define SPI_CR1_BR_1 ((u16)0x0010) /* Bit 1 */ +#define SPI_CR1_BR_2 ((u16)0x0020) /* Bit 2 */ + +#define SPI_CR1_SPE ((u16)0x0040) /* SPI Enable */ +#define SPI_CR1_LSBFIRST ((u16)0x0080) /* Frame Format */ +#define SPI_CR1_SSI ((u16)0x0100) /* Internal slave select */ +#define SPI_CR1_SSM ((u16)0x0200) /* Software slave management */ +#define SPI_CR1_RXONLY ((u16)0x0400) /* Receive only */ +#define SPI_CR1_DFF ((u16)0x0800) /* Data Frame Format */ +#define SPI_CR1_CRCNEXT ((u16)0x1000) /* Transmit CRC next */ +#define SPI_CR1_CRCEN ((u16)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((u16)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((u16)0x8000) /* Bidirectional data mode enable */ + + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((u8)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((u8)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((u8)0x04) /* SS Output Enable */ +#define SPI_CR2_ERRIE ((u8)0x20) /* Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((u8)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((u8)0x80) /* Tx buffer Empty Interrupt Enable */ + + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((u8)0x01) /* Receive buffer Not Empty */ +#define SPI_SR_TXE ((u8)0x02) /* Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((u8)0x04) /* Channel side */ +#define SPI_SR_UDR ((u8)0x08) /* Underrun flag */ +#define SPI_SR_CRCERR ((u8)0x10) /* CRC Error flag */ +#define SPI_SR_MODF ((u8)0x20) /* Mode fault */ +#define SPI_SR_OVR ((u8)0x40) /* Overrun flag */ +#define SPI_SR_BSY ((u8)0x80) /* Busy flag */ + + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((u16)0xFFFF) /* Data Register */ + + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((u16)0xFFFF) /* CRC polynomial register */ + + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((u16)0xFFFF) /* Rx CRC Register */ + + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((u16)0xFFFF) /* Tx CRC Register */ + + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((u16)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((u16)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((u16)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((u16)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((u16)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((u16)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((u16)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((u16)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((u16)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((u16)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((u16)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((u16)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((u16)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((u16)0x0800) /* I2S mode selection */ + + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((u16)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((u16)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((u16)0x0200) /* Master Clock Output Enable */ + + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((u16)0x0001) /* Peripheral Enable */ +#define I2C_CR1_SMBUS ((u16)0x0002) /* SMBus Mode */ +#define I2C_CR1_SMBTYPE ((u16)0x0008) /* SMBus Type */ +#define I2C_CR1_ENARP ((u16)0x0010) /* ARP Enable */ +#define I2C_CR1_ENPEC ((u16)0x0020) /* PEC Enable */ +#define I2C_CR1_ENGC ((u16)0x0040) /* General Call Enable */ +#define I2C_CR1_NOSTRETCH ((u16)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((u16)0x0100) /* Start Generation */ +#define I2C_CR1_STOP ((u16)0x0200) /* Stop Generation */ +#define I2C_CR1_ACK ((u16)0x0400) /* Acknowledge Enable */ +#define I2C_CR1_POS ((u16)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((u16)0x1000) /* Packet Error Checking */ +#define I2C_CR1_ALERT ((u16)0x2000) /* SMBus Alert */ +#define I2C_CR1_SWRST ((u16)0x8000) /* Software Reset */ + + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((u16)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((u16)0x0001) /* Bit 0 */ +#define I2C_CR2_FREQ_1 ((u16)0x0002) /* Bit 1 */ +#define I2C_CR2_FREQ_2 ((u16)0x0004) /* Bit 2 */ +#define I2C_CR2_FREQ_3 ((u16)0x0008) /* Bit 3 */ +#define I2C_CR2_FREQ_4 ((u16)0x0010) /* Bit 4 */ +#define I2C_CR2_FREQ_5 ((u16)0x0020) /* Bit 5 */ + +#define I2C_CR2_ITERREN ((u16)0x0100) /* Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((u16)0x0200) /* Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((u16)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((u16)0x0800) /* DMA Requests Enable */ +#define I2C_CR2_LAST ((u16)0x1000) /* DMA Last Transfer */ + + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((u16)0x00FE) /* Interface Address */ +#define I2C_OAR1_ADD8_9 ((u16)0x0300) /* Interface Address */ + +#define I2C_OAR1_ADD0 ((u16)0x0001) /* Bit 0 */ +#define I2C_OAR1_ADD1 ((u16)0x0002) /* Bit 1 */ +#define I2C_OAR1_ADD2 ((u16)0x0004) /* Bit 2 */ +#define I2C_OAR1_ADD3 ((u16)0x0008) /* Bit 3 */ +#define I2C_OAR1_ADD4 ((u16)0x0010) /* Bit 4 */ +#define I2C_OAR1_ADD5 ((u16)0x0020) /* Bit 5 */ +#define I2C_OAR1_ADD6 ((u16)0x0040) /* Bit 6 */ +#define I2C_OAR1_ADD7 ((u16)0x0080) /* Bit 7 */ +#define I2C_OAR1_ADD8 ((u16)0x0100) /* Bit 8 */ +#define I2C_OAR1_ADD9 ((u16)0x0200) /* Bit 9 */ + +#define I2C_OAR1_ADDMODE ((u16)0x8000) /* Addressing Mode (Slave mode) */ + + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((u8)0x01) /* Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((u8)0xFE) /* Interface address */ + + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((u8)0xFF) /* 8-bit Data Register */ + + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((u16)0x0001) /* Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((u16)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((u16)0x0004) /* Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((u16)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((u16)0x0010) /* Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((u16)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((u16)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((u16)0x0100) /* Bus Error */ +#define I2C_SR1_ARLO ((u16)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((u16)0x0400) /* Acknowledge Failure */ +#define I2C_SR1_OVR ((u16)0x0800) /* Overrun/Underrun */ +#define I2C_SR1_PECERR ((u16)0x1000) /* PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((u16)0x4000) /* Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((u16)0x8000) /* SMBus Alert */ + + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((u16)0x0001) /* Master/Slave */ +#define I2C_SR2_BUSY ((u16)0x0002) /* Bus Busy */ +#define I2C_SR2_TRA ((u16)0x0004) /* Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((u16)0x0010) /* General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((u16)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((u16)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((u16)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((u16)0xFF00) /* Packet Error Checking Register */ + + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((u16)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((u16)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((u16)0x8000) /* I2C Master Mode Selection */ + + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((u8)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((u16)0x0001) /* Parity Error */ +#define USART_SR_FE ((u16)0x0002) /* Framing Error */ +#define USART_SR_NE ((u16)0x0004) /* Noise Error Flag */ +#define USART_SR_ORE ((u16)0x0008) /* OverRun Error */ +#define USART_SR_IDLE ((u16)0x0010) /* IDLE line detected */ +#define USART_SR_RXNE ((u16)0x0020) /* Read Data Register Not Empty */ +#define USART_SR_TC ((u16)0x0040) /* Transmission Complete */ +#define USART_SR_TXE ((u16)0x0080) /* Transmit Data Register Empty */ +#define USART_SR_LBD ((u16)0x0100) /* LIN Break Detection Flag */ +#define USART_SR_CTS ((u16)0x0200) /* CTS Flag */ + + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((u16)0x01FF) /* Data value */ + + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((u16)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((u16)0xFFF0) /* Mantissa of USARTDIV */ + + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((u16)0x0001) /* Send Break */ +#define USART_CR1_RWU ((u16)0x0002) /* Receiver wakeup */ +#define USART_CR1_RE ((u16)0x0004) /* Receiver Enable */ +#define USART_CR1_TE ((u16)0x0008) /* Transmitter Enable */ +#define USART_CR1_IDLEIE ((u16)0x0010) /* IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((u16)0x0020) /* RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((u16)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((u16)0x0080) /* PE Interrupt Enable */ +#define USART_CR1_PEIE ((u16)0x0100) /* PE Interrupt Enable */ +#define USART_CR1_PS ((u16)0x0200) /* Parity Selection */ +#define USART_CR1_PCE ((u16)0x0400) /* Parity Control Enable */ +#define USART_CR1_WAKE ((u16)0x0800) /* Wakeup method */ +#define USART_CR1_M ((u16)0x1000) /* Word length */ +#define USART_CR1_UE ((u16)0x2000) /* USART Enable */ + + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((u16)0x000F) /* Address of the USART node */ +#define USART_CR2_LBDL ((u16)0x0020) /* LIN Break Detection Length */ +#define USART_CR2_LBDIE ((u16)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((u16)0x0100) /* Last Bit Clock pulse */ +#define USART_CR2_CPHA ((u16)0x0200) /* Clock Phase */ +#define USART_CR2_CPOL ((u16)0x0400) /* Clock Polarity */ +#define USART_CR2_CLKEN ((u16)0x0800) /* Clock Enable */ + +#define USART_CR2_STOP ((u16)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((u16)0x1000) /* Bit 0 */ +#define USART_CR2_STOP_1 ((u16)0x2000) /* Bit 1 */ + +#define USART_CR2_LINEN ((u16)0x4000) /* LIN mode enable */ + + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((u16)0x0001) /* Error Interrupt Enable */ +#define USART_CR3_IREN ((u16)0x0002) /* IrDA mode Enable */ +#define USART_CR3_IRLP ((u16)0x0004) /* IrDA Low-Power */ +#define USART_CR3_HDSEL ((u16)0x0008) /* Half-Duplex Selection */ +#define USART_CR3_NACK ((u16)0x0010) /* Smartcard NACK enable */ +#define USART_CR3_SCEN ((u16)0x0020) /* Smartcard mode enable */ +#define USART_CR3_DMAR ((u16)0x0040) /* DMA Enable Receiver */ +#define USART_CR3_DMAT ((u16)0x0080) /* DMA Enable Transmitter */ +#define USART_CR3_RTSE ((u16)0x0100) /* RTS Enable */ +#define USART_CR3_CTSE ((u16)0x0200) /* CTS Enable */ +#define USART_CR3_CTSIE ((u16)0x0400) /* CTS Interrupt Enable */ + + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((u16)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((u16)0x0001) /* Bit 0 */ +#define USART_GTPR_PSC_1 ((u16)0x0002) /* Bit 1 */ +#define USART_GTPR_PSC_2 ((u16)0x0004) /* Bit 2 */ +#define USART_GTPR_PSC_3 ((u16)0x0008) /* Bit 3 */ +#define USART_GTPR_PSC_4 ((u16)0x0010) /* Bit 4 */ +#define USART_GTPR_PSC_5 ((u16)0x0020) /* Bit 5 */ +#define USART_GTPR_PSC_6 ((u16)0x0040) /* Bit 6 */ +#define USART_GTPR_PSC_7 ((u16)0x0080) /* Bit 7 */ + +#define USART_GTPR_GT ((u16)0xFF00) /* Guard time value */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((u32)0x00000FFF) /* Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((u32)0xFFFF0000) /* REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((u32)0x00010000) /* Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((u32)0x00020000) /* Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((u32)0x00040000) /* Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((u32)0x00080000) /* Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((u32)0x00100000) /* Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((u32)0x00200000) /* Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((u32)0x00400000) /* Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((u32)0x00800000) /* Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((u32)0x01000000) /* Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((u32)0x02000000) /* Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((u32)0x04000000) /* Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((u32)0x08000000) /* Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((u32)0x10000000) /* Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((u32)0x20000000) /* Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((u32)0x40000000) /* Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((u32)0x80000000) /* Bit 15 */ + + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((u32)0x00000001) /* Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((u32)0x00000002) /* Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((u32)0x00000004) /* Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((u32)0x00000020) /* Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((u32)0x000000C0) /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((u32)0x00000040) /* Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((u32)0x00000080) /* Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((u32)0x00000100) /* Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((u32)0x00000200) /* Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((u32)0x00000400) /* TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((u32)0x00000800) /* TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((u32)0x00001000) /* TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((u32)0x00002000) /* TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN_STOP ((u32)0x00004000) /* Debug CAN stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) /* SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) /* SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((u32)0x00020000) /* TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((u32)0x00040000) /* TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((u32)0x00080000) /* TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((u32)0x00100000) /* TIM8 counter stopped when core is halted */ + + + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((u8)0x07) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((u8)0x01) /* Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((u8)0x02) /* Bit 1 */ +#define FLASH_ACR_LATENCY_2 ((u8)0x04) /* Bit 2 */ + +#define FLASH_ACR_HLFCYA ((u8)0x08) /* Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((u8)0x10) /* Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((u8)0x20) /* Prefetch Buffer Status */ + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((u32)0xFFFFFFFF) /* FPEC Key */ + + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((u32)0xFFFFFFFF) /* Option Byte Key */ + + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((u8)0x01) /* Busy */ +#define FLASH_SR_PGERR ((u8)0x04) /* Programming Error */ +#define FLASH_SR_WRPRTERR ((u8)0x10) /* Write Protection Error */ +#define FLASH_SR_EOP ((u8)0x20) /* End of operation */ + + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((u16)0x0001) /* Programming */ +#define FLASH_CR_PER ((u16)0x0002) /* Page Erase */ +#define FLASH_CR_MER ((u16)0x0004) /* Mass Erase */ +#define FLASH_CR_OPTPG ((u16)0x0010) /* Option Byte Programming */ +#define FLASH_CR_OPTER ((u16)0x0020) /* Option Byte Erase */ +#define FLASH_CR_STRT ((u16)0x0040) /* Start */ +#define FLASH_CR_LOCK ((u16)0x0080) /* Lock */ +#define FLASH_CR_OPTWRE ((u16)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((u16)0x0400) /* Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((u16)0x1000) /* End of operation interrupt enable */ + + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((u32)0xFFFFFFFF) /* Flash Address */ + + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((u16)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((u16)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((u16)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((u16)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((u16)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((u16)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_Notused ((u16)0x03E0) /* Not used */ + + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((u32)0xFFFFFFFF) /* Write Protect */ + + +/*----------------------------------------------------------------------------*/ + + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((u32)0x000000FF) /* Read protection option byte */ +#define FLASH_RDP_nRDP ((u32)0x0000FF00) /* Read protection complemented option byte */ + + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((u32)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((u32)0xFF000000) /* User complemented option byte */ + + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((u32)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((u32)0x0000FF00) /* User data storage complemented option byte */ + + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((u32)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((u32)0xFF000000) /* User data storage complemented option byte */ + + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((u32)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((u32)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/* Exported macro ------------------------------------------------------------*/ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = 0x0) + +#define WRITE_REG(REG, VAL) ((REG) = VAL) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK))) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_MAP_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_nvic.h b/bsp/stm32/library/inc/stm32f10x_nvic.h new file mode 100644 index 0000000000..5a3ce7ef18 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_nvic.h @@ -0,0 +1,287 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* NVIC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_NVIC_H +#define __STM32F10x_NVIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* NVIC Init Structure definition */ +typedef struct +{ + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ Channels --------------------------------------------------------------*/ +#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ +#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ +#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ +#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ +#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ +#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ +#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ +#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ +#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ +#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ +#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ +#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */ +#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */ +#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */ +#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */ +#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */ +#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */ +#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */ +#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */ +#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ +#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ +#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ +#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ +#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ +#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ +#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ +#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ +#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ +#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ +#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ +#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ +#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ +#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ +#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ +#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ +#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ +#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ +#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ +#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ +#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ +#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ +#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ +#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ +#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */ +#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */ +#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */ +#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */ +#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */ +#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */ +#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */ +#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */ +#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */ +#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */ +#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */ +#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */ +#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */ +#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */ +#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */ +#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */ +#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */ + + +#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \ + ((CHANNEL) == PVD_IRQChannel) || \ + ((CHANNEL) == TAMPER_IRQChannel) || \ + ((CHANNEL) == RTC_IRQChannel) || \ + ((CHANNEL) == FLASH_IRQChannel) || \ + ((CHANNEL) == RCC_IRQChannel) || \ + ((CHANNEL) == EXTI0_IRQChannel) || \ + ((CHANNEL) == EXTI1_IRQChannel) || \ + ((CHANNEL) == EXTI2_IRQChannel) || \ + ((CHANNEL) == EXTI3_IRQChannel) || \ + ((CHANNEL) == EXTI4_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel1_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel2_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel3_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel4_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel5_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel6_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel7_IRQChannel) || \ + ((CHANNEL) == ADC1_2_IRQChannel) || \ + ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \ + ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \ + ((CHANNEL) == CAN_RX1_IRQChannel) || \ + ((CHANNEL) == CAN_SCE_IRQChannel) || \ + ((CHANNEL) == EXTI9_5_IRQChannel) || \ + ((CHANNEL) == TIM1_BRK_IRQChannel) || \ + ((CHANNEL) == TIM1_UP_IRQChannel) || \ + ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \ + ((CHANNEL) == TIM1_CC_IRQChannel) || \ + ((CHANNEL) == TIM2_IRQChannel) || \ + ((CHANNEL) == TIM3_IRQChannel) || \ + ((CHANNEL) == TIM4_IRQChannel) || \ + ((CHANNEL) == I2C1_EV_IRQChannel) || \ + ((CHANNEL) == I2C1_ER_IRQChannel) || \ + ((CHANNEL) == I2C2_EV_IRQChannel) || \ + ((CHANNEL) == I2C2_ER_IRQChannel) || \ + ((CHANNEL) == SPI1_IRQChannel) || \ + ((CHANNEL) == SPI2_IRQChannel) || \ + ((CHANNEL) == USART1_IRQChannel) || \ + ((CHANNEL) == USART2_IRQChannel) || \ + ((CHANNEL) == USART3_IRQChannel) || \ + ((CHANNEL) == EXTI15_10_IRQChannel) || \ + ((CHANNEL) == RTCAlarm_IRQChannel) || \ + ((CHANNEL) == USBWakeUp_IRQChannel) || \ + ((CHANNEL) == TIM8_BRK_IRQChannel) || \ + ((CHANNEL) == TIM8_UP_IRQChannel) || \ + ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \ + ((CHANNEL) == TIM8_CC_IRQChannel) || \ + ((CHANNEL) == ADC3_IRQChannel) || \ + ((CHANNEL) == FSMC_IRQChannel) || \ + ((CHANNEL) == SDIO_IRQChannel) || \ + ((CHANNEL) == TIM5_IRQChannel) || \ + ((CHANNEL) == SPI3_IRQChannel) || \ + ((CHANNEL) == UART4_IRQChannel) || \ + ((CHANNEL) == UART5_IRQChannel) || \ + ((CHANNEL) == TIM6_IRQChannel) || \ + ((CHANNEL) == TIM7_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel1_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel2_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel3_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel4_5_IRQChannel)) + + +/* System Handlers -----------------------------------------------------------*/ +#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ +#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ +#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ +#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ +#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ +#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ +#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ +#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ +#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ + +#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault)) + +#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_SVCall) || \ + ((HANDLER) == SystemHandler_DebugMonitor) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_SVCall)) + +#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_SVCall) || \ + ((HANDLER) == SystemHandler_DebugMonitor) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \ + ((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_DebugMonitor)) + +#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault)) + + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM ((u32)0x20000000) +#define NVIC_VectTab_FLASH ((u32)0x08000000) + +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) + +/* System Low Power ----------------------------------------------------------*/ +#define NVIC_LP_SEVONPEND ((u8)0x10) +#define NVIC_LP_SLEEPDEEP ((u8)0x04) +#define NVIC_LP_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) + +/* Preemption Priority Group -------------------------------------------------*/ +#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) +#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NVIC_DeInit(void); +void NVIC_SCBDeInit(void); +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SETPRIMASK(void); +void NVIC_RESETPRIMASK(void); +void NVIC_SETFAULTMASK(void); +void NVIC_RESETFAULTMASK(void); +void NVIC_BASEPRICONFIG(u32 NewPriority); +u32 NVIC_GetBASEPRI(void); +u16 NVIC_GetCurrentPendingIRQChannel(void); +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); +u16 NVIC_GetCurrentActiveHandler(void); +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); +u32 NVIC_GetCPUID(void); +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); +void NVIC_GenerateSystemReset(void); +void NVIC_GenerateCoreReset(void); +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority); +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); +u32 NVIC_GetFaultAddress(u32 SystemHandler); + +#endif /* __STM32F10x_NVIC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_pwr.h b/bsp/stm32/library/inc/stm32f10x_pwr.h new file mode 100644 index 0000000000..ee94a17ce1 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_pwr.h @@ -0,0 +1,77 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_pwr.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* PWR firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* PVD detection level */ +#define PWR_PVDLevel_2V2 ((u32)0x00000000) +#define PWR_PVDLevel_2V3 ((u32)0x00000020) +#define PWR_PVDLevel_2V4 ((u32)0x00000040) +#define PWR_PVDLevel_2V5 ((u32)0x00000060) +#define PWR_PVDLevel_2V6 ((u32)0x00000080) +#define PWR_PVDLevel_2V7 ((u32)0x000000A0) +#define PWR_PVDLevel_2V8 ((u32)0x000000C0) +#define PWR_PVDLevel_2V9 ((u32)0x000000E0) + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) + +/* Regulator state is STOP mode */ +#define PWR_Regulator_ON ((u32)0x00000000) +#define PWR_Regulator_LowPower ((u32)0x00000001) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) + +/* STOP mode entry */ +#define PWR_STOPEntry_WFI ((u8)0x01) +#define PWR_STOPEntry_WFE ((u8)0x02) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/* PWR Flag */ +#define PWR_FLAG_WU ((u32)0x00000001) +#define PWR_FLAG_SB ((u32)0x00000002) +#define PWR_FLAG_PVDO ((u32)0x00000004) + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(u32 PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG); +void PWR_ClearFlag(u32 PWR_FLAG); + +#endif /* __STM32F10x_PWR_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_rcc.h b/bsp/stm32/library/inc/stm32f10x_rcc.h new file mode 100644 index 0000000000..a256bc9144 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_rcc.h @@ -0,0 +1,288 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* RCC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u32 SYSCLK_Frequency; + u32 HCLK_Frequency; + u32 PCLK1_Frequency; + u32 PCLK2_Frequency; + u32 ADCCLK_Frequency; +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* HSE configuration */ +#define RCC_HSE_OFF ((u32)0x00000000) +#define RCC_HSE_ON ((u32)0x00010000) +#define RCC_HSE_Bypass ((u32)0x00040000) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/* PLL entry clock source */ +#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) + +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) + +/* PLL multiplication factor */ +#define RCC_PLLMul_2 ((u32)0x00000000) +#define RCC_PLLMul_3 ((u32)0x00040000) +#define RCC_PLLMul_4 ((u32)0x00080000) +#define RCC_PLLMul_5 ((u32)0x000C0000) +#define RCC_PLLMul_6 ((u32)0x00100000) +#define RCC_PLLMul_7 ((u32)0x00140000) +#define RCC_PLLMul_8 ((u32)0x00180000) +#define RCC_PLLMul_9 ((u32)0x001C0000) +#define RCC_PLLMul_10 ((u32)0x00200000) +#define RCC_PLLMul_11 ((u32)0x00240000) +#define RCC_PLLMul_12 ((u32)0x00280000) +#define RCC_PLLMul_13 ((u32)0x002C0000) +#define RCC_PLLMul_14 ((u32)0x00300000) +#define RCC_PLLMul_15 ((u32)0x00340000) +#define RCC_PLLMul_16 ((u32)0x00380000) + +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +/* System clock source */ +#define RCC_SYSCLKSource_HSI ((u32)0x00000000) +#define RCC_SYSCLKSource_HSE ((u32)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) + +/* AHB clock source */ +#define RCC_SYSCLK_Div1 ((u32)0x00000000) +#define RCC_SYSCLK_Div2 ((u32)0x00000080) +#define RCC_SYSCLK_Div4 ((u32)0x00000090) +#define RCC_SYSCLK_Div8 ((u32)0x000000A0) +#define RCC_SYSCLK_Div16 ((u32)0x000000B0) +#define RCC_SYSCLK_Div64 ((u32)0x000000C0) +#define RCC_SYSCLK_Div128 ((u32)0x000000D0) +#define RCC_SYSCLK_Div256 ((u32)0x000000E0) +#define RCC_SYSCLK_Div512 ((u32)0x000000F0) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) + +/* APB1/APB2 clock source */ +#define RCC_HCLK_Div1 ((u32)0x00000000) +#define RCC_HCLK_Div2 ((u32)0x00000400) +#define RCC_HCLK_Div4 ((u32)0x00000500) +#define RCC_HCLK_Div8 ((u32)0x00000600) +#define RCC_HCLK_Div16 ((u32)0x00000700) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) + +/* RCC Interrupt source */ +#define RCC_IT_LSIRDY ((u8)0x01) +#define RCC_IT_LSERDY ((u8)0x02) +#define RCC_IT_HSIRDY ((u8)0x04) +#define RCC_IT_HSERDY ((u8)0x08) +#define RCC_IT_PLLRDY ((u8)0x10) +#define RCC_IT_CSS ((u8)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00)) + +/* USB clock source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) + +#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) + +/* ADC clock source */ +#define RCC_PCLK2_Div2 ((u32)0x00000000) +#define RCC_PCLK2_Div4 ((u32)0x00004000) +#define RCC_PCLK2_Div6 ((u32)0x00008000) +#define RCC_PCLK2_Div8 ((u32)0x0000C000) + +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) + +/* LSE configuration */ +#define RCC_LSE_OFF ((u8)0x00) +#define RCC_LSE_ON ((u8)0x01) +#define RCC_LSE_Bypass ((u8)0x04) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) + +/* RTC clock source */ +#define RCC_RTCCLKSource_LSE ((u32)0x00000100) +#define RCC_RTCCLKSource_LSI ((u32)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) + +/* AHB peripheral */ +#define RCC_AHBPeriph_DMA1 ((u32)0x00000001) +#define RCC_AHBPeriph_DMA2 ((u32)0x00000002) +#define RCC_AHBPeriph_SRAM ((u32)0x00000004) +#define RCC_AHBPeriph_FLITF ((u32)0x00000010) +#define RCC_AHBPeriph_CRC ((u32)0x00000040) +#define RCC_AHBPeriph_FSMC ((u32)0x00000100) +#define RCC_AHBPeriph_SDIO ((u32)0x00000400) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) + +/* APB2 peripheral */ +#define RCC_APB2Periph_AFIO ((u32)0x00000001) +#define RCC_APB2Periph_GPIOA ((u32)0x00000004) +#define RCC_APB2Periph_GPIOB ((u32)0x00000008) +#define RCC_APB2Periph_GPIOC ((u32)0x00000010) +#define RCC_APB2Periph_GPIOD ((u32)0x00000020) +#define RCC_APB2Periph_GPIOE ((u32)0x00000040) +#define RCC_APB2Periph_GPIOF ((u32)0x00000080) +#define RCC_APB2Periph_GPIOG ((u32)0x00000100) +#define RCC_APB2Periph_ADC1 ((u32)0x00000200) +#define RCC_APB2Periph_ADC2 ((u32)0x00000400) +#define RCC_APB2Periph_TIM1 ((u32)0x00000800) +#define RCC_APB2Periph_SPI1 ((u32)0x00001000) +#define RCC_APB2Periph_TIM8 ((u32)0x00002000) +#define RCC_APB2Periph_USART1 ((u32)0x00004000) +#define RCC_APB2Periph_ADC3 ((u32)0x00008000) +#define RCC_APB2Periph_ALL ((u32)0x0000FFFD) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) + +/* APB1 peripheral */ +#define RCC_APB1Periph_TIM2 ((u32)0x00000001) +#define RCC_APB1Periph_TIM3 ((u32)0x00000002) +#define RCC_APB1Periph_TIM4 ((u32)0x00000004) +#define RCC_APB1Periph_TIM5 ((u32)0x00000008) +#define RCC_APB1Periph_TIM6 ((u32)0x00000010) +#define RCC_APB1Periph_TIM7 ((u32)0x00000020) +#define RCC_APB1Periph_WWDG ((u32)0x00000800) +#define RCC_APB1Periph_SPI2 ((u32)0x00004000) +#define RCC_APB1Periph_SPI3 ((u32)0x00008000) +#define RCC_APB1Periph_USART2 ((u32)0x00020000) +#define RCC_APB1Periph_USART3 ((u32)0x00040000) +#define RCC_APB1Periph_UART4 ((u32)0x00080000) +#define RCC_APB1Periph_UART5 ((u32)0x00100000) +#define RCC_APB1Periph_I2C1 ((u32)0x00200000) +#define RCC_APB1Periph_I2C2 ((u32)0x00400000) +#define RCC_APB1Periph_USB ((u32)0x00800000) +#define RCC_APB1Periph_CAN ((u32)0x02000000) +#define RCC_APB1Periph_BKP ((u32)0x08000000) +#define RCC_APB1Periph_PWR ((u32)0x10000000) +#define RCC_APB1Periph_DAC ((u32)0x20000000) +#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) + +/* Clock source to output on MCO pin */ +#define RCC_MCO_NoClock ((u8)0x00) +#define RCC_MCO_SYSCLK ((u8)0x04) +#define RCC_MCO_HSI ((u8)0x05) +#define RCC_MCO_HSE ((u8)0x06) +#define RCC_MCO_PLLCLK_Div2 ((u8)0x07) + +#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) + +/* RCC Flag */ +#define RCC_FLAG_HSIRDY ((u8)0x21) +#define RCC_FLAG_HSERDY ((u8)0x31) +#define RCC_FLAG_PLLRDY ((u8)0x39) +#define RCC_FLAG_LSERDY ((u8)0x41) +#define RCC_FLAG_LSIRDY ((u8)0x61) +#define RCC_FLAG_PINRST ((u8)0x7A) +#define RCC_FLAG_PORRST ((u8)0x7B) +#define RCC_FLAG_SFTRST ((u8)0x7C) +#define RCC_FLAG_IWDGRST ((u8)0x7D) +#define RCC_FLAG_WWDGRST ((u8)0x7E) +#define RCC_FLAG_LPWRRST ((u8)0x7F) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RCC_DeInit(void); +void RCC_HSEConfig(u32 RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); +u8 RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(u32 RCC_SYSCLK); +void RCC_PCLK1Config(u32 RCC_HCLK); +void RCC_PCLK2Config(u32 RCC_HCLK); +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(u32 RCC_USBCLKSource); +void RCC_ADCCLKConfig(u32 RCC_PCLK2); +void RCC_LSEConfig(u8 RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(u8 RCC_MCO); +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(u8 RCC_IT); +void RCC_ClearITPendingBit(u8 RCC_IT); + +#endif /* __STM32F10x_RCC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_rtc.h b/bsp/stm32/library/inc/stm32f10x_rtc.h new file mode 100644 index 0000000000..9cd84ace8b --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_rtc.h @@ -0,0 +1,70 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_rtc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* RTC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* RTC interrupts define -----------------------------------------------------*/ +#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */ + +#define IS_RTC_IT(IT) ((((IT) & (u16)0xFFF8) == 0x00) && ((IT) != 0x00)) + +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) + +/* RTC interrupts flags ------------------------------------------------------*/ +#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */ + +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFFF0) == 0x00) && ((FLAG) != 0x00)) + +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) + +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +u32 RTC_GetCounter(void); +void RTC_SetCounter(u32 CounterValue); +void RTC_SetPrescaler(u32 PrescalerValue); +void RTC_SetAlarm(u32 AlarmValue); +u32 RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); +void RTC_ClearFlag(u16 RTC_FLAG); +ITStatus RTC_GetITStatus(u16 RTC_IT); +void RTC_ClearITPendingBit(u16 RTC_IT); + +#endif /* __STM32F10x_RTC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_sdio.h b/bsp/stm32/library/inc/stm32f10x_sdio.h new file mode 100644 index 0000000000..5043049d27 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_sdio.h @@ -0,0 +1,337 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_sdio.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* SDIO firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 SDIO_ClockDiv; + u32 SDIO_ClockEdge; + u32 SDIO_ClockBypass; + u32 SDIO_ClockPowerSave; + u32 SDIO_BusWide; + u32 SDIO_HardwareFlowControl; +} SDIO_InitTypeDef; + +typedef struct +{ + u32 SDIO_Argument; + u32 SDIO_CmdIndex; + u32 SDIO_Response; + u32 SDIO_Wait; + u32 SDIO_CPSM; +} SDIO_CmdInitTypeDef; + +typedef struct +{ + u32 SDIO_DataTimeOut; + u32 SDIO_DataLength; + u32 SDIO_DataBlockSize; + u32 SDIO_TransferDir; + u32 SDIO_TransferMode; + u32 SDIO_DPSM; +} SDIO_DataInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SDIO Clock Edge -----------------------------------------------------------*/ +#define SDIO_ClockEdge_Rising ((u32)0x00000000) +#define SDIO_ClockEdge_Falling ((u32)0x00002000) + +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/* SDIO Clock Bypass ----------------------------------------------------------*/ +#define SDIO_ClockBypass_Disable ((u32)0x00000000) +#define SDIO_ClockBypass_Enable ((u32)0x00000400) + +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) + +/* SDIO Clock Power Save ----------------------------------------------------*/ +#define SDIO_ClockPowerSave_Disable ((u32)0x00000000) +#define SDIO_ClockPowerSave_Enable ((u32)0x00000200) + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) + +/* SDIO Bus Wide -------------------------------------------------------------*/ +#define SDIO_BusWide_1b ((u32)0x00000000) +#define SDIO_BusWide_4b ((u32)0x00000800) +#define SDIO_BusWide_8b ((u32)0x00001000) + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/* SDIO Hardware Flow Control -----------------------------------------------*/ +#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000) + +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) + +/* SDIO Power State ----------------------------------------------------------*/ +#define SDIO_PowerState_OFF ((u32)0x00000000) +#define SDIO_PowerState_ON ((u32)0x00000003) + +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) + +/* SDIO Interrupt soucres ----------------------------------------------------*/ +#define SDIO_IT_CCRCFAIL ((u32)0x00000001) +#define SDIO_IT_DCRCFAIL ((u32)0x00000002) +#define SDIO_IT_CTIMEOUT ((u32)0x00000004) +#define SDIO_IT_DTIMEOUT ((u32)0x00000008) +#define SDIO_IT_TXUNDERR ((u32)0x00000010) +#define SDIO_IT_RXOVERR ((u32)0x00000020) +#define SDIO_IT_CMDREND ((u32)0x00000040) +#define SDIO_IT_CMDSENT ((u32)0x00000080) +#define SDIO_IT_DATAEND ((u32)0x00000100) +#define SDIO_IT_STBITERR ((u32)0x00000200) +#define SDIO_IT_DBCKEND ((u32)0x00000400) +#define SDIO_IT_CMDACT ((u32)0x00000800) +#define SDIO_IT_TXACT ((u32)0x00001000) +#define SDIO_IT_RXACT ((u32)0x00002000) +#define SDIO_IT_TXFIFOHE ((u32)0x00004000) +#define SDIO_IT_RXFIFOHF ((u32)0x00008000) +#define SDIO_IT_TXFIFOF ((u32)0x00010000) +#define SDIO_IT_RXFIFOF ((u32)0x00020000) +#define SDIO_IT_TXFIFOE ((u32)0x00040000) +#define SDIO_IT_RXFIFOE ((u32)0x00080000) +#define SDIO_IT_TXDAVL ((u32)0x00100000) +#define SDIO_IT_RXDAVL ((u32)0x00200000) +#define SDIO_IT_SDIOIT ((u32)0x00400000) +#define SDIO_IT_CEATAEND ((u32)0x00800000) + +#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00)) + +/* SDIO Command Index -------------------------------------------------------*/ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) + +/* SDIO Response Type --------------------------------------------------------*/ +#define SDIO_Response_No ((u32)0x00000000) +#define SDIO_Response_Short ((u32)0x00000040) +#define SDIO_Response_Long ((u32)0x000000C0) + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) + +/* SDIO Wait Interrupt State -------------------------------------------------*/ +#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */ + +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) + +/* SDIO CPSM State -----------------------------------------------------------*/ +#define SDIO_CPSM_Disable ((u32)0x00000000) +#define SDIO_CPSM_Enable ((u32)0x00000400) + +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) + +/* SDIO Response Registers ---------------------------------------------------*/ +#define SDIO_RESP1 ((u32)0x00000000) +#define SDIO_RESP2 ((u32)0x00000004) +#define SDIO_RESP3 ((u32)0x00000008) +#define SDIO_RESP4 ((u32)0x0000000C) + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) + +/* SDIO Data Length ----------------------------------------------------------*/ +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) + +/* SDIO Data Block Size ------------------------------------------------------*/ +#define SDIO_DataBlockSize_1b ((u32)0x00000000) +#define SDIO_DataBlockSize_2b ((u32)0x00000010) +#define SDIO_DataBlockSize_4b ((u32)0x00000020) +#define SDIO_DataBlockSize_8b ((u32)0x00000030) +#define SDIO_DataBlockSize_16b ((u32)0x00000040) +#define SDIO_DataBlockSize_32b ((u32)0x00000050) +#define SDIO_DataBlockSize_64b ((u32)0x00000060) +#define SDIO_DataBlockSize_128b ((u32)0x00000070) +#define SDIO_DataBlockSize_256b ((u32)0x00000080) +#define SDIO_DataBlockSize_512b ((u32)0x00000090) +#define SDIO_DataBlockSize_1024b ((u32)0x000000A0) +#define SDIO_DataBlockSize_2048b ((u32)0x000000B0) +#define SDIO_DataBlockSize_4096b ((u32)0x000000C0) +#define SDIO_DataBlockSize_8192b ((u32)0x000000D0) +#define SDIO_DataBlockSize_16384b ((u32)0x000000E0) + +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) + +/* SDIO Transfer Direction ---------------------------------------------------*/ +#define SDIO_TransferDir_ToCard ((u32)0x00000000) +#define SDIO_TransferDir_ToSDIO ((u32)0x00000002) + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) + +/* SDIO Transfer Type --------------------------------------------------------*/ +#define SDIO_TransferMode_Block ((u32)0x00000000) +#define SDIO_TransferMode_Stream ((u32)0x00000004) + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) + +/* SDIO DPSM State -----------------------------------------------------------*/ +#define SDIO_DPSM_Disable ((u32)0x00000000) +#define SDIO_DPSM_Enable ((u32)0x00000001) + +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) + +/* SDIO Flags ----------------------------------------------------------------*/ +#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008) +#define SDIO_FLAG_TXUNDERR ((u32)0x00000010) +#define SDIO_FLAG_RXOVERR ((u32)0x00000020) +#define SDIO_FLAG_CMDREND ((u32)0x00000040) +#define SDIO_FLAG_CMDSENT ((u32)0x00000080) +#define SDIO_FLAG_DATAEND ((u32)0x00000100) +#define SDIO_FLAG_STBITERR ((u32)0x00000200) +#define SDIO_FLAG_DBCKEND ((u32)0x00000400) +#define SDIO_FLAG_CMDACT ((u32)0x00000800) +#define SDIO_FLAG_TXACT ((u32)0x00001000) +#define SDIO_FLAG_RXACT ((u32)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000) +#define SDIO_FLAG_TXFIFOF ((u32)0x00010000) +#define SDIO_FLAG_RXFIFOF ((u32)0x00020000) +#define SDIO_FLAG_TXFIFOE ((u32)0x00040000) +#define SDIO_FLAG_RXFIFOE ((u32)0x00080000) +#define SDIO_FLAG_TXDAVL ((u32)0x00100000) +#define SDIO_FLAG_RXDAVL ((u32)0x00200000) +#define SDIO_FLAG_SDIOIT ((u32)0x00400000) +#define SDIO_FLAG_CEATAEND ((u32)0x00800000) + +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00)) + +/* SDIO Read Wait Mode -------------------------------------------------------*/ +#define SDIO_ReadWaitMode_CLK ((u32)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001) + +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(u32 SDIO_PowerState); +u32 SDIO_GetPowerState(void); +void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +u8 SDIO_GetCommandResponse(void); +u32 SDIO_GetResponse(u32 SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +u32 SDIO_GetDataCounter(void); +u32 SDIO_ReadData(void); +void SDIO_WriteData(u32 Data); +u32 SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG); +void SDIO_ClearFlag(u32 SDIO_FLAG); +ITStatus SDIO_GetITStatus(u32 SDIO_IT); +void SDIO_ClearITPendingBit(u32 SDIO_IT); + +#endif /* __STM32F10x_SDIO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_spi.h b/bsp/stm32/library/inc/stm32f10x_spi.h new file mode 100644 index 0000000000..a023eebfd9 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_spi.h @@ -0,0 +1,289 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_spi.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SPI Init structure definition */ +typedef struct +{ + u16 SPI_Direction; + u16 SPI_Mode; + u16 SPI_DataSize; + u16 SPI_CPOL; + u16 SPI_CPHA; + u16 SPI_NSS; + u16 SPI_BaudRatePrescaler; + u16 SPI_FirstBit; + u16 SPI_CRCPolynomial; +}SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + u16 I2S_Mode; + u16 I2S_Standard; + u16 I2S_DataFormat; + u16 I2S_MCLKOutput; + u16 I2S_AudioFreq; + u16 I2S_CPOL; +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \ + ((*(u32*)&(PERIPH)) == SPI2_BASE) || \ + ((*(u32*)&(PERIPH)) == SPI3_BASE)) + +#define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \ + ((*(u32*)&(PERIPH)) == SPI3_BASE)) + +/* SPI data direction mode */ +#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000) +#define SPI_Direction_2Lines_RxOnly ((u16)0x0400) +#define SPI_Direction_1Line_Rx ((u16)0x8000) +#define SPI_Direction_1Line_Tx ((u16)0xC000) + +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) + +/* SPI master/slave mode */ +#define SPI_Mode_Master ((u16)0x0104) +#define SPI_Mode_Slave ((u16)0x0000) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) + +/* SPI data size */ +#define SPI_DataSize_16b ((u16)0x0800) +#define SPI_DataSize_8b ((u16)0x0000) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) + +/* SPI Clock Polarity */ +#define SPI_CPOL_Low ((u16)0x0000) +#define SPI_CPOL_High ((u16)0x0002) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) + +/* SPI Clock Phase */ +#define SPI_CPHA_1Edge ((u16)0x0000) +#define SPI_CPHA_2Edge ((u16)0x0001) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) + +/* SPI Slave Select management */ +#define SPI_NSS_Soft ((u16)0x0200) +#define SPI_NSS_Hard ((u16)0x0000) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) + +/* SPI BaudRate Prescaler */ +#define SPI_BaudRatePrescaler_2 ((u16)0x0000) +#define SPI_BaudRatePrescaler_4 ((u16)0x0008) +#define SPI_BaudRatePrescaler_8 ((u16)0x0010) +#define SPI_BaudRatePrescaler_16 ((u16)0x0018) +#define SPI_BaudRatePrescaler_32 ((u16)0x0020) +#define SPI_BaudRatePrescaler_64 ((u16)0x0028) +#define SPI_BaudRatePrescaler_128 ((u16)0x0030) +#define SPI_BaudRatePrescaler_256 ((u16)0x0038) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) + +/* SPI MSB/LSB transmission */ +#define SPI_FirstBit_MSB ((u16)0x0000) +#define SPI_FirstBit_LSB ((u16)0x0080) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) + +/* I2S Mode */ +#define I2S_Mode_SlaveTx ((u16)0x0000) +#define I2S_Mode_SlaveRx ((u16)0x0100) +#define I2S_Mode_MasterTx ((u16)0x0200) +#define I2S_Mode_MasterRx ((u16)0x0300) + +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) + +/* I2S Standard */ +#define I2S_Standard_Phillips ((u16)0x0000) +#define I2S_Standard_MSB ((u16)0x0010) +#define I2S_Standard_LSB ((u16)0x0020) +#define I2S_Standard_PCMShort ((u16)0x0030) +#define I2S_Standard_PCMLong ((u16)0x00B0) + +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) + +/* I2S Data Format */ +#define I2S_DataFormat_16b ((u16)0x0000) +#define I2S_DataFormat_16bextended ((u16)0x0001) +#define I2S_DataFormat_24b ((u16)0x0003) +#define I2S_DataFormat_32b ((u16)0x0005) + +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) + +/* I2S MCLK Output */ +#define I2S_MCLKOutput_Enable ((u16)0x0200) +#define I2S_MCLKOutput_Disable ((u16)0x0000) + +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) + +/* I2S Audio Frequency */ +#define I2S_AudioFreq_48k ((u16)48000) +#define I2S_AudioFreq_44k ((u16)44100) +#define I2S_AudioFreq_22k ((u16)22050) +#define I2S_AudioFreq_16k ((u16)16000) +#define I2S_AudioFreq_8k ((u16)8000) +#define I2S_AudioFreq_Default ((u16)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \ + ((FREQ) == I2S_AudioFreq_44k) || \ + ((FREQ) == I2S_AudioFreq_22k) || \ + ((FREQ) == I2S_AudioFreq_16k) || \ + ((FREQ) == I2S_AudioFreq_8k) || \ + ((FREQ) == I2S_AudioFreq_Default)) + +/* I2S Clock Polarity */ +#define I2S_CPOL_Low ((u16)0x0000) +#define I2S_CPOL_High ((u16)0x0008) + +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) + +/* SPI_I2S DMA transfer requests */ +#define SPI_I2S_DMAReq_Tx ((u16)0x0002) +#define SPI_I2S_DMAReq_Rx ((u16)0x0001) + +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) + +/* SPI NSS internal software mangement */ +#define SPI_NSSInternalSoft_Set ((u16)0x0100) +#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF) + +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) + +/* SPI CRC Transmit/Receive */ +#define SPI_CRC_Tx ((u8)0x00) +#define SPI_CRC_Rx ((u8)0x01) + +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) + +/* SPI direction transmit/receive */ +#define SPI_Direction_Rx ((u16)0xBFFF) +#define SPI_Direction_Tx ((u16)0x4000) + +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) + +/* SPI_I2S interrupts definition */ +#define SPI_I2S_IT_TXE ((u8)0x71) +#define SPI_I2S_IT_RXNE ((u8)0x60) +#define SPI_I2S_IT_ERR ((u8)0x50) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define SPI_I2S_IT_OVR ((u8)0x56) +#define SPI_IT_MODF ((u8)0x55) +#define SPI_IT_CRCERR ((u8)0x54) +#define I2S_IT_UDR ((u8)0x53) + +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) + +/* SPI_I2S flags definition */ +#define SPI_I2S_FLAG_RXNE ((u16)0x0001) +#define SPI_I2S_FLAG_TXE ((u16)0x0002) +#define I2S_FLAG_CHSIDE ((u16)0x0004) +#define I2S_FLAG_UDR ((u16)0x0008) +#define SPI_FLAG_CRCERR ((u16)0x0010) +#define SPI_FLAG_MODF ((u16)0x0020) +#define SPI_I2S_FLAG_OVR ((u16)0x0040) +#define SPI_I2S_FLAG_BSY ((u16)0x0080) + +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) + +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) + +/* SPI CRC polynomial --------------------------------------------------------*/ +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data); +u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC); +u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT); + +#endif /*__STM32F10x_SPI_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_systick.h b/bsp/stm32/library/inc/stm32f10x_systick.h new file mode 100644 index 0000000000..633dd2c401 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_systick.h @@ -0,0 +1,64 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_systick.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* SysTick firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SYSTICK_H +#define __STM32F10x_SYSTICK_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* SysTick clock source */ +#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) + +/* SysTick counter state */ +#define SysTick_Counter_Disable ((u32)0xFFFFFFFE) +#define SysTick_Counter_Enable ((u32)0x00000001) +#define SysTick_Counter_Clear ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \ + ((COUNTER) == SysTick_Counter_Enable) || \ + ((COUNTER) == SysTick_Counter_Clear)) + +/* SysTick Flag */ +#define SysTick_FLAG_COUNT ((u32)0x00000010) +#define SysTick_FLAG_SKEW ((u32)0x0000001E) +#define SysTick_FLAG_NOREF ((u32)0x0000001F) + +#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \ + ((FLAG) == SysTick_FLAG_SKEW) || \ + ((FLAG) == SysTick_FLAG_NOREF)) + +#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource); +void SysTick_SetReload(u32 Reload); +void SysTick_CounterCmd(u32 SysTick_Counter); +void SysTick_ITConfig(FunctionalState NewState); +u32 SysTick_GetCounter(void); +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG); + +#endif /* __STM32F10x_SYSTICK_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_tim.h b/bsp/stm32/library/inc/stm32f10x_tim.h new file mode 100644 index 0000000000..e82ee6f701 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_tim.h @@ -0,0 +1,778 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_tim.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* TIM Time Base Init structure definition */ +typedef struct +{ + u16 TIM_Prescaler; + u16 TIM_CounterMode; + u16 TIM_Period; + u16 TIM_ClockDivision; + u8 TIM_RepetitionCounter; +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + u16 TIM_OCMode; + u16 TIM_OutputState; + u16 TIM_OutputNState; + u16 TIM_Pulse; + u16 TIM_OCPolarity; + u16 TIM_OCNPolarity; + u16 TIM_OCIdleState; + u16 TIM_OCNIdleState; +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + u16 TIM_Channel; + u16 TIM_ICPolarity; + u16 TIM_ICSelection; + u16 TIM_ICPrescaler; + u16 TIM_ICFilter; +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + u16 TIM_OSSRState; + u16 TIM_OSSIState; + u16 TIM_LOCKLevel; + u16 TIM_DeadTime; + u16 TIM_Break; + u16 TIM_BreakPolarity; + u16 TIM_AutomaticOutput; +} TIM_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM2_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM3_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM4_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM5_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM6_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM7_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM8_BASE)) + +#define IS_TIM_18_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM8_BASE)) + +#define IS_TIM_123458_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM2_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM3_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM4_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM5_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM8_BASE)) + +/* TIM Output Compare and PWM modes -----------------------------------------*/ +#define TIM_OCMode_Timing ((u16)0x0000) +#define TIM_OCMode_Active ((u16)0x0010) +#define TIM_OCMode_Inactive ((u16)0x0020) +#define TIM_OCMode_Toggle ((u16)0x0030) +#define TIM_OCMode_PWM1 ((u16)0x0060) +#define TIM_OCMode_PWM2 ((u16)0x0070) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) + +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/* TIM One Pulse Mode -------------------------------------------------------*/ +#define TIM_OPMode_Single ((u16)0x0008) +#define TIM_OPMode_Repetitive ((u16)0x0000) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) + +/* TIM Channel -------------------------------------------------------------*/ +#define TIM_Channel_1 ((u16)0x0000) +#define TIM_Channel_2 ((u16)0x0004) +#define TIM_Channel_3 ((u16)0x0008) +#define TIM_Channel_4 ((u16)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) + +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/* TIM Clock Division CKD --------------------------------------------------*/ +#define TIM_CKD_DIV1 ((u16)0x0000) +#define TIM_CKD_DIV2 ((u16)0x0100) +#define TIM_CKD_DIV4 ((u16)0x0200) + +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) + +/* TIM Counter Mode --------------------------------------------------------*/ +#define TIM_CounterMode_Up ((u16)0x0000) +#define TIM_CounterMode_Down ((u16)0x0010) +#define TIM_CounterMode_CenterAligned1 ((u16)0x0020) +#define TIM_CounterMode_CenterAligned2 ((u16)0x0040) +#define TIM_CounterMode_CenterAligned3 ((u16)0x0060) + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) + +/* TIM Output Compare Polarity ---------------------------------------------*/ +#define TIM_OCPolarity_High ((u16)0x0000) +#define TIM_OCPolarity_Low ((u16)0x0002) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) + +/* TIM Output Compare N Polarity -------------------------------------------*/ +#define TIM_OCNPolarity_High ((u16)0x0000) +#define TIM_OCNPolarity_Low ((u16)0x0008) + +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) + +/* TIM Output Compare states -----------------------------------------------*/ +#define TIM_OutputState_Disable ((u16)0x0000) +#define TIM_OutputState_Enable ((u16)0x0001) + +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) + +/* TIM Output Compare N States ---------------------------------------------*/ +#define TIM_OutputNState_Disable ((u16)0x0000) +#define TIM_OutputNState_Enable ((u16)0x0004) + +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) + +/* TIM Capture Compare States -----------------------------------------------*/ +#define TIM_CCx_Enable ((u16)0x0001) +#define TIM_CCx_Disable ((u16)0x0000) + +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) + +/* TIM Capture Compare N States --------------------------------------------*/ +#define TIM_CCxN_Enable ((u16)0x0004) +#define TIM_CCxN_Disable ((u16)0x0000) + +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) + +/* Break Input enable/disable -----------------------------------------------*/ +#define TIM_Break_Enable ((u16)0x1000) +#define TIM_Break_Disable ((u16)0x0000) + +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) + +/* Break Polarity -----------------------------------------------------------*/ +#define TIM_BreakPolarity_Low ((u16)0x0000) +#define TIM_BreakPolarity_High ((u16)0x2000) + +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) + +/* TIM AOE Bit Set/Reset ---------------------------------------------------*/ +#define TIM_AutomaticOutput_Enable ((u16)0x4000) +#define TIM_AutomaticOutput_Disable ((u16)0x0000) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/* Lock levels --------------------------------------------------------------*/ +#define TIM_LOCKLevel_OFF ((u16)0x0000) +#define TIM_LOCKLevel_1 ((u16)0x0100) +#define TIM_LOCKLevel_2 ((u16)0x0200) +#define TIM_LOCKLevel_3 ((u16)0x0300) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) + +/* OSSI: Off-State Selection for Idle mode states ---------------------------*/ +#define TIM_OSSIState_Enable ((u16)0x0400) +#define TIM_OSSIState_Disable ((u16)0x0000) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) + +/* OSSR: Off-State Selection for Run mode states ----------------------------*/ +#define TIM_OSSRState_Enable ((u16)0x0800) +#define TIM_OSSRState_Disable ((u16)0x0000) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) + +/* TIM Output Compare Idle State -------------------------------------------*/ +#define TIM_OCIdleState_Set ((u16)0x0100) +#define TIM_OCIdleState_Reset ((u16)0x0000) + +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) + +/* TIM Output Compare N Idle State -----------------------------------------*/ +#define TIM_OCNIdleState_Set ((u16)0x0200) +#define TIM_OCNIdleState_Reset ((u16)0x0000) + +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) + +/* TIM Input Capture Polarity ----------------------------------------------*/ +#define TIM_ICPolarity_Rising ((u16)0x0000) +#define TIM_ICPolarity_Falling ((u16)0x0002) + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) + +/* TIM Input Capture Selection ---------------------------------------------*/ +#define TIM_ICSelection_DirectTI ((u16)0x0001) +#define TIM_ICSelection_IndirectTI ((u16)0x0002) +#define TIM_ICSelection_TRC ((u16)0x0003) + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) + +/* TIM Input Capture Prescaler ---------------------------------------------*/ +#define TIM_ICPSC_DIV1 ((u16)0x0000) +#define TIM_ICPSC_DIV2 ((u16)0x0004) +#define TIM_ICPSC_DIV4 ((u16)0x0008) +#define TIM_ICPSC_DIV8 ((u16)0x000C) + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) + +/* TIM interrupt sources ---------------------------------------------------*/ +#define TIM_IT_Update ((u16)0x0001) +#define TIM_IT_CC1 ((u16)0x0002) +#define TIM_IT_CC2 ((u16)0x0004) +#define TIM_IT_CC3 ((u16)0x0008) +#define TIM_IT_CC4 ((u16)0x0010) +#define TIM_IT_COM ((u16)0x0020) +#define TIM_IT_Trigger ((u16)0x0040) +#define TIM_IT_Break ((u16)0x0080) + +#define IS_TIM_IT(IT) ((((IT) & (u16)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \ + (((TIM_IT) & (u16)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \ + (((TIM_IT) & (u16)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \ + (((TIM_IT) & (u16)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000))) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) + +/* TIM DMA Base address ----------------------------------------------------*/ +#define TIM_DMABase_CR1 ((u16)0x0000) +#define TIM_DMABase_CR2 ((u16)0x0001) +#define TIM_DMABase_SMCR ((u16)0x0002) +#define TIM_DMABase_DIER ((u16)0x0003) +#define TIM_DMABase_SR ((u16)0x0004) +#define TIM_DMABase_EGR ((u16)0x0005) +#define TIM_DMABase_CCMR1 ((u16)0x0006) +#define TIM_DMABase_CCMR2 ((u16)0x0007) +#define TIM_DMABase_CCER ((u16)0x0008) +#define TIM_DMABase_CNT ((u16)0x0009) +#define TIM_DMABase_PSC ((u16)0x000A) +#define TIM_DMABase_ARR ((u16)0x000B) +#define TIM_DMABase_RCR ((u16)0x000C) +#define TIM_DMABase_CCR1 ((u16)0x000D) +#define TIM_DMABase_CCR2 ((u16)0x000E) +#define TIM_DMABase_CCR3 ((u16)0x000F) +#define TIM_DMABase_CCR4 ((u16)0x0010) +#define TIM_DMABase_BDTR ((u16)0x0011) +#define TIM_DMABase_DCR ((u16)0x0012) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) + +/* TIM DMA Burst Length ----------------------------------------------------*/ +#define TIM_DMABurstLength_1Byte ((u16)0x0000) +#define TIM_DMABurstLength_2Bytes ((u16)0x0100) +#define TIM_DMABurstLength_3Bytes ((u16)0x0200) +#define TIM_DMABurstLength_4Bytes ((u16)0x0300) +#define TIM_DMABurstLength_5Bytes ((u16)0x0400) +#define TIM_DMABurstLength_6Bytes ((u16)0x0500) +#define TIM_DMABurstLength_7Bytes ((u16)0x0600) +#define TIM_DMABurstLength_8Bytes ((u16)0x0700) +#define TIM_DMABurstLength_9Bytes ((u16)0x0800) +#define TIM_DMABurstLength_10Bytes ((u16)0x0900) +#define TIM_DMABurstLength_11Bytes ((u16)0x0A00) +#define TIM_DMABurstLength_12Bytes ((u16)0x0B00) +#define TIM_DMABurstLength_13Bytes ((u16)0x0C00) +#define TIM_DMABurstLength_14Bytes ((u16)0x0D00) +#define TIM_DMABurstLength_15Bytes ((u16)0x0E00) +#define TIM_DMABurstLength_16Bytes ((u16)0x0F00) +#define TIM_DMABurstLength_17Bytes ((u16)0x1000) +#define TIM_DMABurstLength_18Bytes ((u16)0x1100) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ + ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_18Bytes)) + +/* TIM DMA sources ---------------------------------------------------------*/ +#define TIM_DMA_Update ((u16)0x0100) +#define TIM_DMA_CC1 ((u16)0x0200) +#define TIM_DMA_CC2 ((u16)0x0400) +#define TIM_DMA_CC3 ((u16)0x0800) +#define TIM_DMA_CC4 ((u16)0x1000) +#define TIM_DMA_COM ((u16)0x2000) +#define TIM_DMA_Trigger ((u16)0x4000) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \ + (((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \ + (((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \ + (((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000))) + +/* TIM External Trigger Prescaler ------------------------------------------*/ +#define TIM_ExtTRGPSC_OFF ((u16)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000) + +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) + +/* TIM Internal Trigger Selection ------------------------------------------*/ +#define TIM_TS_ITR0 ((u16)0x0000) +#define TIM_TS_ITR1 ((u16)0x0010) +#define TIM_TS_ITR2 ((u16)0x0020) +#define TIM_TS_ITR3 ((u16)0x0030) +#define TIM_TS_TI1F_ED ((u16)0x0040) +#define TIM_TS_TI1FP1 ((u16)0x0050) +#define TIM_TS_TI2FP2 ((u16)0x0060) +#define TIM_TS_ETRF ((u16)0x0070) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) + +/* TIM TIx External Clock Source -------------------------------------------*/ +#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040) + +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) + +/* TIM External Trigger Polarity -------------------------------------------*/ +#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000) + +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) + +/* TIM Prescaler Reload Mode -----------------------------------------------*/ +#define TIM_PSCReloadMode_Update ((u16)0x0000) +#define TIM_PSCReloadMode_Immediate ((u16)0x0001) + +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) + +/* TIM Forced Action -------------------------------------------------------*/ +#define TIM_ForcedAction_Active ((u16)0x0050) +#define TIM_ForcedAction_InActive ((u16)0x0040) + +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) + +/* TIM Encoder Mode --------------------------------------------------------*/ +#define TIM_EncoderMode_TI1 ((u16)0x0001) +#define TIM_EncoderMode_TI2 ((u16)0x0002) +#define TIM_EncoderMode_TI12 ((u16)0x0003) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) + +/* TIM Event Source --------------------------------------------------------*/ +#define TIM_EventSource_Update ((u16)0x0001) +#define TIM_EventSource_CC1 ((u16)0x0002) +#define TIM_EventSource_CC2 ((u16)0x0004) +#define TIM_EventSource_CC3 ((u16)0x0008) +#define TIM_EventSource_CC4 ((u16)0x0010) +#define TIM_EventSource_COM ((u16)0x0020) +#define TIM_EventSource_Trigger ((u16)0x0040) +#define TIM_EventSource_Break ((u16)0x0080) + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \ + (((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \ + (((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \ + (((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000))) + +/* TIM Update Source --------------------------------------------------------*/ +#define TIM_UpdateSource_Global ((u16)0x0000) +#define TIM_UpdateSource_Regular ((u16)0x0001) + +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) + +/* TIM Ouput Compare Preload State ------------------------------------------*/ +#define TIM_OCPreload_Enable ((u16)0x0008) +#define TIM_OCPreload_Disable ((u16)0x0000) + +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) + +/* TIM Ouput Compare Fast State ---------------------------------------------*/ +#define TIM_OCFast_Enable ((u16)0x0004) +#define TIM_OCFast_Disable ((u16)0x0000) + +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/* TIM Ouput Compare Clear State --------------------------------------------*/ +#define TIM_OCClear_Enable ((u16)0x0080) +#define TIM_OCClear_Disable ((u16)0x0000) + +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) + +/* TIM Trigger Output Source ------------------------------------------------*/ +#define TIM_TRGOSource_Reset ((u16)0x0000) +#define TIM_TRGOSource_Enable ((u16)0x0010) +#define TIM_TRGOSource_Update ((u16)0x0020) +#define TIM_TRGOSource_OC1 ((u16)0x0030) +#define TIM_TRGOSource_OC1Ref ((u16)0x0040) +#define TIM_TRGOSource_OC2Ref ((u16)0x0050) +#define TIM_TRGOSource_OC3Ref ((u16)0x0060) +#define TIM_TRGOSource_OC4Ref ((u16)0x0070) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) + +#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_Reset)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_Enable)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_Update)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC1)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\ + ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC4Ref))) + +/* TIM Slave Mode ----------------------------------------------------------*/ +#define TIM_SlaveMode_Reset ((u16)0x0004) +#define TIM_SlaveMode_Gated ((u16)0x0005) +#define TIM_SlaveMode_Trigger ((u16)0x0006) +#define TIM_SlaveMode_External1 ((u16)0x0007) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) + +/* TIM Master Slave Mode ---------------------------------------------------*/ +#define TIM_MasterSlaveMode_Enable ((u16)0x0080) +#define TIM_MasterSlaveMode_Disable ((u16)0x0000) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) + +/* TIM Flags ---------------------------------------------------------------*/ +#define TIM_FLAG_Update ((u16)0x0001) +#define TIM_FLAG_CC1 ((u16)0x0002) +#define TIM_FLAG_CC2 ((u16)0x0004) +#define TIM_FLAG_CC3 ((u16)0x0008) +#define TIM_FLAG_CC4 ((u16)0x0010) +#define TIM_FLAG_COM ((u16)0x0020) +#define TIM_FLAG_Trigger ((u16)0x0040) +#define TIM_FLAG_Break ((u16)0x0080) +#define TIM_FLAG_CC1OF ((u16)0x0200) +#define TIM_FLAG_CC2OF ((u16)0x0400) +#define TIM_FLAG_CC3OF ((u16)0x0800) +#define TIM_FLAG_CC4OF ((u16)0x1000) + +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\ + (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \ + (((TIM_FLAG) & (u16)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \ + (((TIM_FLAG) & (u16)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\ + (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \ + (((TIM_FLAG) & (u16)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000))) + +#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) ||\ + ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \ + ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\ + (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\ + ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \ + ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\ + ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) ||\ + ((*(u32*)&(PERIPH))==TIM1_BASE)|| ((*(u32*)&(PERIPH))==TIM8_BASE) || \ + ((*(u32*)&(PERIPH))==TIM7_BASE) || ((*(u32*)&(PERIPH))==TIM6_BASE)) && \ + (((TIM_FLAG) == TIM_FLAG_Update))) ||\ + ((((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) &&\ + (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\ + ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \ + ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \ + ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\ + (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\ + ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF)))) + +/* TIM Input Capture Filer Value ---------------------------------------------*/ +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) + +/* TIM External Trigger Filter -----------------------------------------------*/ +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u16 ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u16 ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u16 ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD); +u16 TIM_GetCapture1(TIM_TypeDef* TIMx); +u16 TIM_GetCapture2(TIM_TypeDef* TIMx); +u16 TIM_GetCapture3(TIM_TypeDef* TIMx); +u16 TIM_GetCapture4(TIM_TypeDef* TIMx); +u16 TIM_GetCounter(TIM_TypeDef* TIMx); +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); + +#endif /*__STM32F10x_TIM_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ + + + + + + + + diff --git a/bsp/stm32/library/inc/stm32f10x_type.h b/bsp/stm32/library/inc/stm32f10x_type.h new file mode 100644 index 0000000000..1ca3e5261a --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_usart.h b/bsp/stm32/library/inc/stm32f10x_usart.h new file mode 100644 index 0000000000..a774f09c64 --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_usart.h @@ -0,0 +1,253 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_usart.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* USART Init Structure definition */ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u16 USART_Mode; + u16 USART_HardwareFlowControl; +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + u16 USART_Clock; + u16 USART_CPOL; + u16 USART_CPHA; + u16 USART_LastBit; +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ + ((*(u32*)&(PERIPH)) == USART2_BASE) || \ + ((*(u32*)&(PERIPH)) == USART3_BASE) || \ + ((*(u32*)&(PERIPH)) == UART4_BASE) || \ + ((*(u32*)&(PERIPH)) == UART5_BASE)) + +#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ + ((*(u32*)&(PERIPH)) == USART2_BASE) || \ + ((*(u32*)&(PERIPH)) == USART3_BASE)) + +#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ + ((*(u32*)&(PERIPH)) == USART2_BASE) || \ + ((*(u32*)&(PERIPH)) == USART3_BASE) || \ + ((*(u32*)&(PERIPH)) == UART4_BASE)) + +/* USART Word Length ---------------------------------------------------------*/ +#define USART_WordLength_8b ((u16)0x0000) +#define USART_WordLength_9b ((u16)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) + +/* USART Stop Bits -----------------------------------------------------------*/ +#define USART_StopBits_1 ((u16)0x0000) +#define USART_StopBits_0_5 ((u16)0x1000) +#define USART_StopBits_2 ((u16)0x2000) +#define USART_StopBits_1_5 ((u16)0x3000) + +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/* USART Parity --------------------------------------------------------------*/ +#define USART_Parity_No ((u16)0x0000) +#define USART_Parity_Even ((u16)0x0400) +#define USART_Parity_Odd ((u16)0x0600) + +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) + +/* USART Mode ----------------------------------------------------------------*/ +#define USART_Mode_Rx ((u16)0x0004) +#define USART_Mode_Tx ((u16)0x0008) + +#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00)) + +/* USART Hardware Flow Control -----------------------------------------------*/ +#define USART_HardwareFlowControl_None ((u16)0x0000) +#define USART_HardwareFlowControl_RTS ((u16)0x0100) +#define USART_HardwareFlowControl_CTS ((u16)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300) + +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) + +#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \ + ((*(u32*)&(PERIPH)) != UART5_BASE)) \ + || ((HFC) == USART_HardwareFlowControl_None)) + +/* USART Clock ---------------------------------------------------------------*/ +#define USART_Clock_Disable ((u16)0x0000) +#define USART_Clock_Enable ((u16)0x0800) + +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) + +/* USART Clock Polarity ------------------------------------------------------*/ +#define USART_CPOL_Low ((u16)0x0000) +#define USART_CPOL_High ((u16)0x0400) + +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/* USART Clock Phase ---------------------------------------------------------*/ +#define USART_CPHA_1Edge ((u16)0x0000) +#define USART_CPHA_2Edge ((u16)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/* USART Last Bit ------------------------------------------------------------*/ +#define USART_LastBit_Disable ((u16)0x0000) +#define USART_LastBit_Enable ((u16)0x0100) + +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) + +/* USART Interrupt definition ------------------------------------------------*/ +#define USART_IT_PE ((u16)0x0028) +#define USART_IT_TXE ((u16)0x0727) +#define USART_IT_TC ((u16)0x0626) +#define USART_IT_RXNE ((u16)0x0525) +#define USART_IT_IDLE ((u16)0x0424) +#define USART_IT_LBD ((u16)0x0846) +#define USART_IT_CTS ((u16)0x096A) +#define USART_IT_ERR ((u16)0x0060) +#define USART_IT_ORE ((u16)0x0360) +#define USART_IT_NE ((u16)0x0260) +#define USART_IT_FE ((u16)0x0160) + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) + +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) + +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) + +#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \ + ((*(u32*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_IT) != USART_IT_CTS)) + +/* USART DMA Requests --------------------------------------------------------*/ +#define USART_DMAReq_Tx ((u16)0x0080) +#define USART_DMAReq_Rx ((u16)0x0040) + +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00)) + +/* USART WakeUp methods ------------------------------------------------------*/ +#define USART_WakeUp_IdleLine ((u16)0x0000) +#define USART_WakeUp_AddressMark ((u16)0x0800) + +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) + +/* USART LIN Break Detection Length ------------------------------------------*/ +#define USART_LINBreakDetectLength_10b ((u16)0x0000) +#define USART_LINBreakDetectLength_11b ((u16)0x0020) + +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) + +/* USART IrDA Low Power ------------------------------------------------------*/ +#define USART_IrDAMode_LowPower ((u16)0x0004) +#define USART_IrDAMode_Normal ((u16)0x0000) + +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) + +/* USART Flags ---------------------------------------------------------------*/ +#define USART_FLAG_CTS ((u16)0x0200) +#define USART_FLAG_LBD ((u16)0x0100) +#define USART_FLAG_TXE ((u16)0x0080) +#define USART_FLAG_TC ((u16)0x0040) +#define USART_FLAG_RXNE ((u16)0x0020) +#define USART_FLAG_IDLE ((u16)0x0010) +#define USART_FLAG_ORE ((u16)0x0008) +#define USART_FLAG_NE ((u16)0x0004) +#define USART_FLAG_FE ((u16)0x0002) +#define USART_FLAG_PE ((u16)0x0001) + +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00)) + +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\ + ((*(u32*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT); + +#endif /* __STM32F10x_USART_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/inc/stm32f10x_wwdg.h b/bsp/stm32/library/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000000..2cbf3ceefa --- /dev/null +++ b/bsp/stm32/library/inc/stm32f10x_wwdg.h @@ -0,0 +1,54 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_wwdg.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* WWDG firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* WWDG Prescaler */ +#define WWDG_Prescaler_1 ((u32)0x00000000) +#define WWDG_Prescaler_2 ((u32)0x00000080) +#define WWDG_Prescaler_4 ((u32)0x00000100) +#define WWDG_Prescaler_8 ((u32)0x00000180) + +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) + +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) + +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void WWDG_DeInit(void); +void WWDG_SetPrescaler(u32 WWDG_Prescaler); +void WWDG_SetWindowValue(u8 WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(u8 Counter); +void WWDG_Enable(u8 Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#endif /* __STM32F10x_WWDG_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_adc.c b/bsp/stm32/library/src/stm32f10x_adc.c new file mode 100644 index 0000000000..2141cffa89 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_adc.c @@ -0,0 +1,1402 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_adc.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the ADC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((u32)0x00000800) +#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((u32)0x00000400) +#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((u32)0x00001000) +#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((u32)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((u32)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((u32)0x00000001) +#define CR2_ADON_Reset ((u32)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((u32)0x00000100) +#define CR2_DMA_Reset ((u32)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((u32)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((u32)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((u32)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((u32)0x00100000) +#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((u32)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((u32)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((u32)0x00008000) +#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((u32)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((u32)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((u32)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((u32)0x00800000) +#define CR2_TSVREFE_Reset ((u32)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((u32)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((u32)0x0000001F) +#define SQR2_SQ_Set ((u32)0x0000001F) +#define SQR1_SQ_Set ((u32)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((u32)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((u32)0x00300000) +#define JSQR_JL_Reset ((u32)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((u32)0x00000007) +#define SMPR2_SMP_Set ((u32)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((u8)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((u32)0x4001244C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitializes the ADCx peripheral registers to their default +* reset values. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + switch (*(u32*)&ADCx) + { + case ADC1_BASE: + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + break; + + case ADC2_BASE: + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + break; + + case ADC3_BASE: + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes the ADCx peripheral according to the specified parameters +* in the ADC_InitStruct. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* Output : None +* Return : None +******************************************************************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1); + tmpreg1 |= ((u32)tmpreg2 << 20); + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its default value. +* Input : ADC_InitStruct : pointer to an ADC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Enables or disables the specified ADC peripheral. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the ADCx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_DMACmd +* Description : Enables or disables the specified ADC DMA request. +* Input : - ADCx: where x can be 1 or 3 to select the ADC peripheral. +* Note: ADC2 hasn't a DMA capability. +* - NewState: new state of the selected ADC DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupt sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* - NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState) +{ + u8 itmask = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)ADC_IT; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(u32)itmask); + } +} + +/******************************************************************************* +* Function Name : ADC_ResetCalibration +* Description : Resets the selected ADC calibration registers. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/******************************************************************************* +* Function Name : ADC_GetResetCalibrationStatus +* Description : Gets the selected ADC reset calibration registers status. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC reset calibration registers (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u32)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_StartCalibration +* Description : Starts the selected ADC calibration process. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/******************************************************************************* +* Function Name : ADC_GetCalibrationStatus +* Description : Gets the selected ADC calibration status. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC calibration (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (u32)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + + /* Return the CAL bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_SoftwareStartConvCmd +* Description : Enables or disables the selected ADC software start conversion . +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC software start conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSoftwareStartConvStatus +* Description : Gets the selected ADC Software start conversion Status. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC software start conversion (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (u32)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + + /* Return the SWSTART bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_DiscModeChannelCountConfig +* Description : Configures the discontinuous mode for the selected ADC regular +* group channel. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - Number: specifies the discontinuous mode regular channel +* count value. This number must be between 1 and 8. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number) +{ + u32 tmpreg1 = 0; + u32 tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_DiscModeCmd +* Description : Enables or disables the discontinuous mode on regular group +* channel for the specified ADC +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC discontinuous mode +* on regular group channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_RegularChannelConfig +* Description : Configures for the selected ADC regular channel its corresponding +* rank in the sequencer and its sample time. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* - Rank: The rank in the regular group sequencer. This parameter +* must be between 1 to 16. +* - ADC_SampleTime: The sample time value to be set for the +* selected channel. +* This parameter can be one of the following values: +* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles +* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles +* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles +* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles +* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles +* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles +* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles +* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles +* Output : None +* Return : None +*******************************************************************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime) +{ + u32 tmpreg1 = 0, tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigConvCmd +* Description : Enables or disables the ADCx conversion through external trigger. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC external trigger +* start of conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Returns the last ADCx conversion result data for regular channel. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u16 ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (u16) ADCx->DR; +} + +/******************************************************************************* +* Function Name : ADC_GetDualModeConversionValue +* Description : Returns the last ADC1 and ADC2 conversion result data in dual mode. +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u32 ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(vu32 *) DR_ADDRESS); +} + +/******************************************************************************* +* Function Name : ADC_AutoInjectedConvCmd +* Description : Enables or disables the selected ADC automatic injected group +* conversion after regular one. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC auto injected +* conversion +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_InjectedDiscModeCmd +* Description : Enables or disables the discontinuous mode for injected group +* channel for the specified ADC +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC discontinuous mode +* on injected group channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigInjectedConvConfig +* Description : Configures the ADCx external trigger for injected channels conversion. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_ExternalTrigInjecConv: specifies the ADC trigger to +* start injected conversion. +* This parameter can be one of the following values: +* - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event +* selected (for ADC1, ADC2 and ADC3) +* - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture +* compare4 selected (for ADC1, ADC2 and ADC3) +* - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event +* selected (for ADC1 and ADC2) +* - ADC_External TrigInjecConv_T2_CC1: Timer2 capture +* compare1 selected (for ADC1 and ADC2) +* - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture +* compare4 selected (for ADC1 and ADC2) +* - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event +* selected (for ADC1 and ADC2) +* - ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External +* interrupt line 15 or Timer8 capture compare4 event selected +* (for ADC1 and ADC2) +* - ADC_External TrigInjecConv_T4_CC3: Timer4 capture +* compare3 selected (for ADC3 only) +* - ADC_External TrigInjecConv_T8_CC2: Timer8 capture +* compare2 selected (for ADC3 only) +* - ADC_External TrigInjecConv_T8_CC4: Timer8 capture +* compare4 selected (for ADC3 only) +* - ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event +* selected (for ADC3 only) +* - ADC_External TrigInjecConv_T5_CC4: Timer5 capture +* compare4 selected (for ADC3 only) +* - ADC_ExternalTrigInjecConv_None: Injected conversion +* started by software and not by external trigger (for +* ADC1, ADC2 and ADC3) +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigInjectedConvCmd +* Description : Enables or disables the ADCx injected channels conversion +* through external trigger +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC external trigger +* start of injected conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_SoftwareStartInjectedConvCmd +* Description : Enables or disables the selected ADC start of the injected +* channels conversion. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - NewState: new state of the selected ADC software start +* injected conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSoftwareStartInjectedConvCmdStatus +* Description : Gets the selected ADC Software start injected conversion Status. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC software start injected conversion (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (u32)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_InjectedChannelConfig +* Description : Configures for the selected ADC injected channel its corresponding +* rank in the sequencer and its sample time. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* - Rank: The rank in the injected group sequencer. This parameter +* must be between 1 to 4. +* - ADC_SampleTime: The sample time value to be set for the +* selected channel. +* This parameter can be one of the following values: +* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles +* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles +* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles +* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles +* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles +* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles +* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles +* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime) +{ + u32 tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (u8)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (u32)ADC_Channel << (5 * (u8)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_InjectedSequencerLengthConfig +* Description : Configures the sequencer length for injected channels +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - Length: The sequencer length. +* This parameter must be a number between 1 to 4. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length) +{ + u32 tmpreg1 = 0; + u32 tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_SetInjectedOffset +* Description : Set the injected channels conversion value offset +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_InjectedChannel: the ADC injected channel to set its +* offset. +* This parameter can be one of the following values: +* - ADC_InjectedChannel_1: Injected Channel1 selected +* - ADC_InjectedChannel_2: Injected Channel2 selected +* - ADC_InjectedChannel_3: Injected Channel3 selected +* - ADC_InjectedChannel_4: Injected Channel4 selected +* - Offset: the offset value for the selected ADC injected channel +* This parameter must be a 12bit value. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + /* Set the selected injected channel data offset */ + *((vu32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset; +} + +/******************************************************************************* +* Function Name : ADC_GetInjectedConversionValue +* Description : Returns the ADC injected channel conversion result +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_InjectedChannel: the converted ADC injected channel. +* This parameter can be one of the following values: +* - ADC_InjectedChannel_1: Injected Channel1 selected +* - ADC_InjectedChannel_2: Injected Channel2 selected +* - ADC_InjectedChannel_3: Injected Channel3 selected +* - ADC_InjectedChannel_4: Injected Channel4 selected +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + /* Returns the selected injected channel conversion data value */ + return (u16) (*(vu32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset))); +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogCmd +* Description : Enables or disables the analog watchdog on single/all regular +* or injected channels +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_AnalogWatchdog: the ADC analog watchdog configuration. +* This parameter can be one of the following values: +* - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on +* a single regular channel +* - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on +* a single injected channel +* - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog +* watchdog on a single regular or injected channel +* - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on +* all regular channel +* - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on +* all injected channel +* - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog +* on all regular and injected channels +* - ADC_AnalogWatchdog_None: No channel guarded by the +* analog watchdog +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogThresholdsConfig +* Description : Configures the high and low thresholds of the analog watchdog. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - HighThreshold: the ADC analog watchdog High threshold value. +* This parameter must be a 12bit value. +* - LowThreshold: the ADC analog watchdog Low threshold value. +* This parameter must be a 12bit value. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, + u16 LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogSingleChannelConfig +* Description : Configures the analog watchdog guarded single channel +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure for the analog +* watchdog. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_TempSensorVrefintCmd +* Description : Enables or disables the temperature sensor and Vrefint channel. +* Input : - NewState: new state of the temperature sensor. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - ADC_FLAG_AWD: Analog watchdog flag +* - ADC_FLAG_EOC: End of conversion flag +* - ADC_FLAG_JEOC: End of injected group conversion flag +* - ADC_FLAG_JSTRT: Start of injected group conversion flag +* - ADC_FLAG_STRT: Start of regular group conversion flag +* Output : None +* Return : The new state of ADC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (u8)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_ClearFlag +* Description : Clears the ADCx's pending flags. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - ADC_FLAG_AWD: Analog watchdog flag +* - ADC_FLAG_EOC: End of conversion flag +* - ADC_FLAG_JEOC: End of injected group conversion flag +* - ADC_FLAG_JSTRT: Start of injected group conversion flag +* - ADC_FLAG_STRT: Start of regular group conversion flag +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR = ~(u32)ADC_FLAG; +} + +/******************************************************************************* +* Function Name : ADC_GetITStatus +* Description : Checks whether the specified ADC interrupt has occurred or not. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupt source to check. +* This parameter can be one of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* Output : None +* Return : The new state of ADC_IT (SET or RESET). +*******************************************************************************/ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT) +{ + ITStatus bitstatus = RESET; + u32 itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (u8)ADC_IT) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (u32)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + + /* Return the ADC_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_ClearITPendingBit +* Description : Clears the ADCx’s interrupt pending bits. +* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT) +{ + u8 itmask = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)(ADC_IT >> 8); + + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(u32)itmask; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_bkp.c b/bsp/stm32/library/src/stm32f10x_bkp.c new file mode 100644 index 0000000000..1655c32d26 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_bkp.c @@ -0,0 +1,272 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_bkp.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the BKP firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ BKP registers bit address in the alias region ----------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + + +/* ---------------------- BKP registers bit mask ------------------------ */ +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((u16)0xFF80) +#define RTCCR_Mask ((u16)0xFC7F) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((u16)0x0001) +#define CSR_CTI_Set ((u16)0x0002) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : BKP_DeInit +* Description : Deinitializes the BKP peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/******************************************************************************* +* Function Name : BKP_TamperPinLevelConfig +* Description : Configures the Tamper Pin active level. +* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level. +* This parameter can be one of the following values: +* - BKP_TamperPinLevel_High: Tamper pin active on high level +* - BKP_TamperPinLevel_Low: Tamper pin active on low level +* Output : None +* Return : None +*******************************************************************************/ +void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + + *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/******************************************************************************* +* Function Name : BKP_TamperPinCmd +* Description : Enables or disables the Tamper Pin activation. +* Input : - NewState: new state of the Tamper Pin activation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_TPE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_ITConfig +* Description : Enables or disables the Tamper Pin Interrupt. +* Input : - NewState: new state of the Tamper Pin Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_TPIE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_RTCOutputConfig +* Description : Select the RTC output source to output on the Tamper pin. +* Input : - BKP_RTCOutputSource: specifies the RTC output source. +* This parameter can be one of the following values: +* - BKP_RTCOutputSource_None: no RTC output on the Tamper pin. +* - BKP_RTCOutputSource_CalibClock: output the RTC clock +* with frequency divided by 64 on the Tamper pin. +* - BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse +* signal on the Tamper pin. +* - BKP_RTCOutputSource_Second: output the RTC Second pulse +* signal on the Tamper pin. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + + tmpreg = BKP->RTCCR; + + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_Mask; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/******************************************************************************* +* Function Name : BKP_SetRTCCalibrationValue +* Description : Sets RTC Clock Calibration value. +* Input : - CalibrationValue: specifies the RTC Clock Calibration value. +* This parameter must be a number between 0 and 0x7F. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_SetRTCCalibrationValue(u8 CalibrationValue) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + + tmpreg = BKP->RTCCR; + + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/******************************************************************************* +* Function Name : BKP_WriteBackupRegister +* Description : Writes user data to the specified Data Backup Register. +* Input : - BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 42] +* - Data: data to write +* Output : None +* Return : None +*******************************************************************************/ +void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data) +{ + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + *(vu16 *) (BKP_BASE + BKP_DR) = Data; +} + +/******************************************************************************* +* Function Name : BKP_ReadBackupRegister +* Description : Reads data from the specified Data Backup Register. +* Input : - BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 42] +* Output : None +* Return : The content of the specified Data Backup Register +*******************************************************************************/ +u16 BKP_ReadBackupRegister(u16 BKP_DR) +{ + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + return (*(vu16 *) (BKP_BASE + BKP_DR)); +} + +/******************************************************************************* +* Function Name : BKP_GetFlagStatus +* Description : Checks whether the Tamper Pin Event flag is set or not. +* Input : None +* Output : None +* Return : The new state of the Tamper Pin Event flag (SET or RESET). +*******************************************************************************/ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(vu32 *) CSR_TEF_BB); +} + +/******************************************************************************* +* Function Name : BKP_ClearFlag +* Description : Clears Tamper Pin Event pending flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/******************************************************************************* +* Function Name : BKP_GetITStatus +* Description : Checks whether the Tamper Pin Interrupt has occurred or not. +* Input : None +* Output : None +* Return : The new state of the Tamper Pin Interrupt (SET or RESET). +*******************************************************************************/ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(vu32 *) CSR_TIF_BB); +} + +/******************************************************************************* +* Function Name : BKP_ClearITPendingBit +* Description : Clears Tamper Pin Interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_can.c b/bsp/stm32/library/src/stm32f10x_can.c new file mode 100644 index 0000000000..5a959b2ea7 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_can.c @@ -0,0 +1,907 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_can.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the CAN firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +/* CAN Master Control Register bits */ +#define MCR_INRQ ((u32)0x00000001) /* Initialization request */ +#define MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */ +#define MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */ +#define MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */ +#define MCR_NART ((u32)0x00000010) /* No automatic retransmission */ +#define MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */ +#define MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */ +#define MCR_TTCM ((u32)0x00000080) /* time triggered communication */ + +/* CAN Master Status Register bits */ +#define MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */ +#define MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */ +#define MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */ + +/* CAN Transmit Status Register bits */ +#define TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */ +#define TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */ +#define TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */ +#define TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */ +#define TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */ +#define TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */ +#define TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */ +#define TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */ +#define TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */ +#define TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */ +#define TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */ +#define TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */ + +/* CAN Receive FIFO 0 Register bits */ +#define RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */ +#define RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */ +#define RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */ + +/* CAN Receive FIFO 1 Register bits */ +#define RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */ +#define RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */ +#define RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */ + +/* CAN Error Status Register bits */ +#define ESR_EWGF ((u32)0x00000001) /* Error warning flag */ +#define ESR_EPVF ((u32)0x00000002) /* Error passive flag */ +#define ESR_BOFF ((u32)0x00000004) /* Bus-off flag */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((u32)0x00000001) /* Filter init mode */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit); + +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_DeInit(void) +{ + /* Enable CAN reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE); +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + contains the configuration information for the CAN peripheral. +* Output : None. +* Return : Constant indicates initialization succeed which will be +* CANINITFAILED or CANINITOK. +*******************************************************************************/ +u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + u8 InitStatus = 0; + u16 WaitAck = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Request initialisation */ + CAN->MCR = MCR_INRQ; + + /* ...and check acknowledged */ + if ((CAN->MSR & MSR_INAK) == 0) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CAN->MCR |= MCR_TTCM; + } + else + { + CAN->MCR &= ~MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CAN->MCR |= MCR_ABOM; + } + else + { + CAN->MCR &= ~MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CAN->MCR |= MCR_AWUM; + } + else + { + CAN->MCR &= ~MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CAN->MCR |= MCR_NART; + } + else + { + CAN->MCR &= ~MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CAN->MCR |= MCR_RFLM; + } + else + { + CAN->MCR &= ~MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CAN->MCR |= MCR_TXFP; + } + else + { + CAN->MCR &= ~MCR_TXFP; + } + + /* Set the bit timing register */ + CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) | + ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) | + ((u32)CAN_InitStruct->CAN_Prescaler - 1); + + InitStatus = CANINITOK; + + /* Request leave initialisation */ + CAN->MCR &= ~MCR_INRQ; + + /* Wait the acknowledge */ + for(WaitAck = 0x400; WaitAck > 0x0; WaitAck--) + { + } + + /* ...and check acknowledged */ + if ((CAN->MSR & MSR_INAK) == MSR_INAK) + { + InitStatus = CANINITFAILED; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/******************************************************************************* +* Function Name : CAN_FilterInit +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_FilterInitStruct. +* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef +* structure that contains the configuration information. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + u16 FilterNumber_BitPos = 0; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + FilterNumber_BitPos = + (u16)(((u16)0x0001) << ((u16)CAN_FilterInitStruct->CAN_FilterNumber)); + + /* Initialisation mode for the filter */ + CAN->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN->FA1R &= ~(u32)FilterNumber_BitPos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN->FS1R &= ~(u32)FilterNumber_BitPos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh); + } + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN->FS1R |= FilterNumber_BitPos; + + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow); + + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN->FM1R &= ~(u32)FilterNumber_BitPos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN->FM1R |= (u32)FilterNumber_BitPos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN->FFA1R &= ~(u32)FilterNumber_BitPos; + } + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN->FFA1R |= (u32)FilterNumber_BitPos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN->FA1R |= FilterNumber_BitPos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMR &= ~FMR_FINIT; +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its default value. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/******************************************************************************* +* Function Name : CAN_ITConfig +* Description : Enables or disables the specified CAN interrupts. +* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or +* disabled. +* This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, +* CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, +* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, +* CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or +* CAN_IT_SLK. +* - NewState: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ITConfig(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CAN->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CAN->IER &= ~CAN_IT; + } +} + +/******************************************************************************* +* Function Name : CAN_Transmit +* Description : Initiates the transmission of a message. +* Input : TxMessage: pointer to a structure which contains CAN Id, CAN +* DLC and CAN datas. +* Output : None. +* Return : The number of the mailbox that is used for transmission +* or CAN_NO_MB if there is no empty mailbox. +*******************************************************************************/ +u8 CAN_Transmit(CanTxMsg* TxMessage) +{ + u8 TransmitMailbox = 0; + + /* Check the parameters */ + assert_param(IS_CAN_STDID(TxMessage->StdId)); + assert_param(IS_CAN_EXTID(TxMessage->StdId)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CAN->TSR&TSR_TME0) == TSR_TME0) + { + TransmitMailbox = 0; + } + else if ((CAN->TSR&TSR_TME1) == TSR_TME1) + { + TransmitMailbox = 1; + } + else if ((CAN->TSR&TSR_TME2) == TSR_TME2) + { + TransmitMailbox = 2; + } + else + { + TransmitMailbox = CAN_NO_MB; + } + + if (TransmitMailbox != CAN_NO_MB) + { + /* Set up the Id */ + CAN->sTxMailBox[TransmitMailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_ID_STD) + { + TxMessage->StdId &= (u32)0x000007FF; + TxMessage->StdId = TxMessage->StdId << 21; + + CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->IDE | + TxMessage->RTR); + } + else + { + TxMessage->ExtId &= (u32)0x1FFFFFFF; + TxMessage->ExtId <<= 3; + + CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->ExtId | TxMessage->IDE | + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (u8)0x0000000F; + CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0; + CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | + ((u32)TxMessage->Data[2] << 16) | + ((u32)TxMessage->Data[1] << 8) | + ((u32)TxMessage->Data[0])); + CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | + ((u32)TxMessage->Data[6] << 16) | + ((u32)TxMessage->Data[5] << 8) | + ((u32)TxMessage->Data[4])); + + /* Request transmission */ + CAN->sTxMailBox[TransmitMailbox].TIR |= TMIDxR_TXRQ; + } + + return TransmitMailbox; +} + +/******************************************************************************* +* Function Name : CAN_TransmitStatus +* Description : Checks the transmission of a message. +* Input : TransmitMailbox: the number of the mailbox that is used for +* transmission. +* Output : None. +* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED +* in an other case. +*******************************************************************************/ +u8 CAN_TransmitStatus(u8 TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + u8 State = 0; + + /* Check the parameters */ + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (0): State |= (u8)((CAN->TSR & TSR_RQCP0) << 2); + State |= (u8)((CAN->TSR & TSR_TXOK0) >> 0); + State |= (u8)((CAN->TSR & TSR_TME0) >> 26); + break; + case (1): State |= (u8)((CAN->TSR & TSR_RQCP1) >> 6); + State |= (u8)((CAN->TSR & TSR_TXOK1) >> 8); + State |= (u8)((CAN->TSR & TSR_TME1) >> 27); + break; + case (2): State |= (u8)((CAN->TSR & TSR_RQCP2) >> 14); + State |= (u8)((CAN->TSR & TSR_TXOK2) >> 16); + State |= (u8)((CAN->TSR & TSR_TME2) >> 28); + break; + default: + State = CANTXFAILED; + break; + } + + switch (State) + { + /* transmit pending */ + case (0x0): State = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): State = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): State = CANTXOK; + break; + default: + State = CANTXFAILED; + break; + } + + return State; +} + +/******************************************************************************* +* Function Name : CAN_CancelTransmit +* Description : Cancels a transmit request. +* Input : Mailbox number. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_CancelTransmit(u8 Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + + /* abort transmission */ + switch (Mailbox) + { + case (0): CAN->TSR |= TSR_ABRQ0; + break; + case (1): CAN->TSR |= TSR_ABRQ1; + break; + case (2): CAN->TSR |= TSR_ABRQ2; + break; + default: + break; + } +} + +/******************************************************************************* +* Function Name : CAN_FIFORelease +* Description : Releases a FIFO. +* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_FIFORelease(u8 FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CAN->RF0R = RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CAN->RF1R = RF1R_RFOM1; + } +} + +/******************************************************************************* +* Function Name : CAN_MessagePending +* Description : Returns the number of pending messages. +* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. +* Output : None. +* Return : NbMessage which is the number of pending message. +*******************************************************************************/ +u8 CAN_MessagePending(u8 FIFONumber) +{ + u8 MessagePending=0; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + if (FIFONumber == CAN_FIFO0) + { + MessagePending = (u8)(CAN->RF0R&(u32)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + MessagePending = (u8)(CAN->RF1R&(u32)0x03); + } + else + { + MessagePending = 0; + } + return MessagePending; +} + +/******************************************************************************* +* Function Name : CAN_Receive +* Description : Receives a message. +* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. +* Output : RxMessage: pointer to a structure which contains CAN Id, +* CAN DLC, CAN datas and FMI number. +* Return : None. +*******************************************************************************/ +void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Get the Id */ + RxMessage->IDE = (u8)0x04 & CAN->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_ID_STD) + { + RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (u32)0x1FFFFFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (u8)0x02 & CAN->sFIFOMailBox[FIFONumber].RIR; + + /* Get the DLC */ + RxMessage->DLC = (u8)0x0F & CAN->sFIFOMailBox[FIFONumber].RDTR; + + /* Get the FMI */ + RxMessage->FMI = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8); + + /* Get the data field */ + RxMessage->Data[0] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24); + + RxMessage->Data[4] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + CAN_FIFORelease(FIFONumber); +} + +/******************************************************************************* +* Function Name : CAN_Sleep +* Description : Enters the low power mode. +* Input : None. +* Output : None. +* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. +*******************************************************************************/ +u8 CAN_Sleep(void) +{ + u8 SleepStatus = 0; + + /* Sleep mode entering request */ + CAN->MCR |= MCR_SLEEP; + SleepStatus = CANSLEEPOK; + + /* Sleep mode status */ + if ((CAN->MCR&MCR_SLEEP) == 0) + { + /* Sleep mode not entered */ + SleepStatus = CANSLEEPFAILED; + } + + /* At this step, sleep mode status */ + return SleepStatus; +} + +/******************************************************************************* +* Function Name : CAN_WakeUp +* Description : Wakes the CAN up. +* Input : None. +* Output : None. +* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other +* case. +*******************************************************************************/ +u8 CAN_WakeUp(void) +{ + u8 WakeUpStatus = 0; + + /* Wake up request */ + CAN->MCR &= ~MCR_SLEEP; + WakeUpStatus = CANWAKEUPFAILED; + + /* Sleep mode status */ + if ((CAN->MCR&MCR_SLEEP) == 0) + { + /* Sleep mode exited */ + WakeUpStatus = CANWAKEUPOK; + } + + /* At this step, sleep mode status */ + return WakeUpStatus; +} + +/******************************************************************************* +* Function Name : CAN_GetFlagStatus +* Description : Checks whether the specified CAN flag is set or not. +* Input : CAN_FLAG: specifies the flag to check. +* This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or +* CAN_FLAG_BOF. +* Output : None. +* Return : The new state of CAN_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_FLAG(CAN_FLAG)); + + /* Check the status of the specified CAN flag */ + if ((CAN->ESR & CAN_FLAG) != (u32)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : CAN_ClearFlag +* Description : Clears the CAN's pending flags. +* Input : CAN_FLAG: specifies the flag to clear. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ClearFlag(u32 CAN_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CAN_FLAG(CAN_FLAG)); + + /* Clear the selected CAN flags */ + CAN->ESR &= ~CAN_FLAG; +} + +/******************************************************************************* +* Function Name : CAN_GetITStatus +* Description : Checks whether the specified CAN interrupt has occurred or +* not. +* Input : CAN_IT: specifies the CAN interrupt source to check. +* This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, +* CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, +* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, +* CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. +* Output : None. +* Return : The new state of CAN_IT (SET or RESET). +*******************************************************************************/ +ITStatus CAN_GetITStatus(u32 CAN_IT) +{ + ITStatus pendingbitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ITStatus(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_RQCP0: + pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP0); + break; + case CAN_IT_RQCP1: + pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP1); + break; + case CAN_IT_RQCP2: + pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP2); + break; + case CAN_IT_FF0: + pendingbitstatus = CheckITStatus(CAN->RF0R, RF0R_FULL0); + break; + case CAN_IT_FOV0: + pendingbitstatus = CheckITStatus(CAN->RF0R, RF0R_FOVR0); + break; + case CAN_IT_FF1: + pendingbitstatus = CheckITStatus(CAN->RF1R, RF1R_FULL1); + break; + case CAN_IT_FOV1: + pendingbitstatus = CheckITStatus(CAN->RF1R, RF1R_FOVR1); + break; + case CAN_IT_EWG: + pendingbitstatus = CheckITStatus(CAN->ESR, ESR_EWGF); + break; + case CAN_IT_EPV: + pendingbitstatus = CheckITStatus(CAN->ESR, ESR_EPVF); + break; + case CAN_IT_BOF: + pendingbitstatus = CheckITStatus(CAN->ESR, ESR_BOFF); + break; + case CAN_IT_SLK: + pendingbitstatus = CheckITStatus(CAN->MSR, MSR_SLAKI); + break; + case CAN_IT_WKU: + pendingbitstatus = CheckITStatus(CAN->MSR, MSR_WKUI); + break; + + default : + pendingbitstatus = RESET; + break; + } + + /* Return the CAN_IT status */ + return pendingbitstatus; +} + +/******************************************************************************* +* Function Name : CAN_ClearITPendingBit +* Description : Clears the CAN’s interrupt pending bits. +* Input : CAN_IT: specifies the interrupt pending bit to clear. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ClearITPendingBit(u32 CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ITStatus(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_RQCP0: + CAN->TSR = TSR_RQCP0; /* rc_w1*/ + break; + case CAN_IT_RQCP1: + CAN->TSR = TSR_RQCP1; /* rc_w1*/ + break; + case CAN_IT_RQCP2: + CAN->TSR = TSR_RQCP2; /* rc_w1*/ + break; + case CAN_IT_FF0: + CAN->RF0R = RF0R_FULL0; /* rc_w1*/ + break; + case CAN_IT_FOV0: + CAN->RF0R = RF0R_FOVR0; /* rc_w1*/ + break; + case CAN_IT_FF1: + CAN->RF1R = RF1R_FULL1; /* rc_w1*/ + break; + case CAN_IT_FOV1: + CAN->RF1R = RF1R_FOVR1; /* rc_w1*/ + break; + case CAN_IT_EWG: + CAN->ESR &= ~ ESR_EWGF; /* rw */ + break; + case CAN_IT_EPV: + CAN->ESR &= ~ ESR_EPVF; /* rw */ + break; + case CAN_IT_BOF: + CAN->ESR &= ~ ESR_BOFF; /* rw */ + break; + case CAN_IT_WKU: + CAN->MSR = MSR_WKUI; /* rc_w1*/ + break; + case CAN_IT_SLK: + CAN->MSR = MSR_SLAKI; /* rc_w1*/ + break; + default : + break; + } +} + +/******************************************************************************* +* Function Name : CheckITStatus +* Description : Checks whether the CAN interrupt has occurred or not. +* Input : CAN_Reg: specifies the CAN interrupt register to check. +* It_Bit: specifies the interrupt source bit to check. +* Output : None. +* Return : The new state of the CAN Interrupt (SET or RESET). +*******************************************************************************/ +static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (u32)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_crc.c b/bsp/stm32/library/src/stm32f10x_crc.c new file mode 100644 index 0000000000..29fbdc660c --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_crc.c @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_crc.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the CRC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CR register bit mask */ +#define CR_RESET_Set ((u32)0x00000001) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CRC_ResetDR +* Description : Resets the CRC Data register (DR). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CR_RESET_Set; +} + +/******************************************************************************* +* Function Name : CRC_CalcCRC +* Description : Computes the 32-bit CRC of a given data word(32-bit). +* Input : - Data: data word(32-bit) to compute its CRC +* Output : None +* Return : 32-bit CRC +*******************************************************************************/ +u32 CRC_CalcCRC(u32 Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/******************************************************************************* +* Function Name : CRC_CalcBlockCRC +* Description : Computes the 32-bit CRC of a given buffer of data word(32-bit). +* Input : - pBuffer: pointer to the buffer containing the data to be +* computed +* - BufferLength: length of the buffer to be computed +* Output : None +* Return : 32-bit CRC +*******************************************************************************/ +u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength) +{ + u32 index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + + return (CRC->DR); +} + +/******************************************************************************* +* Function Name : CRC_GetCRC +* Description : Returns the current CRC value. +* Input : None +* Output : None +* Return : 32-bit CRC +*******************************************************************************/ +u32 CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/******************************************************************************* +* Function Name : CRC_SetIDRegister +* Description : Stores a 8-bit data in the Independent Data(ID) register. +* Input : - IDValue: 8-bit value to be stored in the ID register +* Output : None +* Return : None +*******************************************************************************/ +void CRC_SetIDRegister(u8 IDValue) +{ + CRC->IDR = IDValue; +} + +/******************************************************************************* +* Function Name : CRC_GetIDRegister +* Description : Returns the 8-bit data stored in the Independent Data(ID) register +* Input : None +* Output : None +* Return : 8-bit value of the ID register +*******************************************************************************/ +u8 CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_dac.c b/bsp/stm32/library/src/stm32f10x_dac.c new file mode 100644 index 0000000000..041daa5a94 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_dac.c @@ -0,0 +1,389 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dac.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the DAC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* DAC EN mask */ +#define CR_EN_Set ((u32)0x00000001) + +/* DAC DMAEN mask */ +#define CR_DMAEN_Set ((u32)0x00001000) + +/* CR register Mask */ +#define CR_CLEAR_Mask ((u32)0x00000FFE) + +/* DAC SWTRIG mask */ +#define SWTRIGR_SWTRIG_Set ((u32)0x00000001) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_Set ((u32)0x00000003) +#define DUAL_SWTRIG_Reset ((u32)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_Offset ((u32)0x00000008) +#define DHR12R2_Offset ((u32)0x00000014) +#define DHR12RD_Offset ((u32)0x00000020) + +/* DOR register offset */ +#define DOR_Offset ((u32)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DAC_DeInit +* Description : Deinitializes the DAC peripheral registers to their default +* reset values. +* Input : None. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/******************************************************************************* +* Function Name : DAC_Init +* Description : Initializes the DAC peripheral according to the specified +* parameters in the DAC_InitStruct. +* Input : - DAC_Channel: the selected DAC channel. +* This parameter can be one of the following values: +* - DAC_Channel_1: DAC Channel1 selected +* - DAC_Channel_2: DAC Channel2 selected +* - DAC_InitStruct: pointer to a DAC_InitTypeDef structure that +* contains the configuration information for the specified +* DAC channel. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + u32 tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave genration, + mask/amplitude for wave genration */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/******************************************************************************* +* Function Name : DAC_StructInit +* Description : Fills each DAC_InitStruct member with its default value. +* Input : - DAC_InitStruct : pointer to a DAC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/******************************************************************************* +* Function Name : DAC_Cmd +* Description : Enables or disables the specified DAC channel. +* Input - DAC_Channel: the selected DAC channel. +* This parameter can be one of the following values: +* - DAC_Channel_1: DAC Channel1 selected +* - DAC_Channel_2: DAC Channel2 selected +* - NewState: new state of the DAC channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= CR_EN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(CR_EN_Set << DAC_Channel); + } +} + +/******************************************************************************* +* Function Name : DAC_DMACmd +* Description : Enables or disables the specified DAC channel DMA request. +* Input - DAC_Channel: the selected DAC channel. +* This parameter can be one of the following values: +* - DAC_Channel_1: DAC Channel1 selected +* - DAC_Channel_2: DAC Channel2 selected +* - NewState: new state of the selected DAC channel DMA request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= CR_DMAEN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); + } +} + +/******************************************************************************* +* Function Name : DAC_SoftwareTriggerCmd +* Description : Enables or disables the selected DAC channel software trigger. +* Input - DAC_Channel: the selected DAC channel. +* This parameter can be one of the following values: +* - DAC_Channel_1: DAC Channel1 selected +* - DAC_Channel_2: DAC Channel2 selected +* - NewState: new state of the selected DAC channel software trigger. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); + } +} + +/******************************************************************************* +* Function Name : DAC_DualSoftwareTriggerCmd +* Description : Enables or disables simultaneously the two DAC channels software +* triggers. +* Input - NewState: new state of the DAC channels software triggers. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_Set ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : DAC_WaveGenerationCmd +* Description : Enables or disables the selected DAC channel wave generation. +* Input - DAC_Channel: the selected DAC channel. +* This parameter can be one of the following values: +* - DAC_Channel_1: DAC Channel1 selected +* - DAC_Channel_2: DAC Channel2 selected +* - DAC_Wave: Specifies the wave type to enable or disable. +* This parameter can be one of the following values: +* - DAC_Wave_Noise: noise wave generation +* - DAC_Wave_Triangle: triangle wave generation +* - NewState: new state of the selected DAC channel wave generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/******************************************************************************* +* Function Name : DAC_SetChannel1Data +* Description : Set the specified data holding register value for DAC channel1. +* Input : - DAC_Align: Specifies the data alignement for DAC channel1. +* This parameter can be one of the following values: +* - DAC_Align_8b_R: 8bit right data alignement selected +* - DAC_Align_12b_L: 12bit left data alignement selected +* - DAC_Align_12b_R: 12bit right data alignement selected +* - Data : Data to be loaded in the selected data holding +* register. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_SetChannel1Data(u32 DAC_Align, u16 Data) +{ + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + /* Set the DAC channel1 selected data holding register */ + *((vu32 *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (u32)Data; +} + +/******************************************************************************* +* Function Name : DAC_SetChannel2Data +* Description : Set the specified data holding register value for DAC channel2. +* Input : - DAC_Align: Specifies the data alignement for DAC channel2. +* This parameter can be one of the following values: +* - DAC_Align_8b_R: 8bit right data alignement selected +* - DAC_Align_12b_L: 12bit left data alignement selected +* - DAC_Align_12b_R: 12bit right data alignement selected +* - Data : Data to be loaded in the selected data holding +* register. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_SetChannel2Data(u32 DAC_Align, u16 Data) +{ + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + /* Set the DAC channel2 selected data holding register */ + *((vu32 *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (u32)Data; +} + +/******************************************************************************* +* Function Name : DAC_SetDualChannelData +* Description : Set the specified data holding register value for dual channel +* DAC. +* Input : - DAC_Align: Specifies the data alignement for dual channel DAC. +* This parameter can be one of the following values: +* - DAC_Align_8b_R: 8bit right data alignement selected +* - DAC_Align_12b_L: 12bit left data alignement selected +* - DAC_Align_12b_R: 12bit right data alignement selected +* - Data2: Data for DAC Channel2 to be loaded in the selected data +* holding register. +* - Data1: Data for DAC Channel1 to be loaded in the selected data +* holding register. +* Output : None +* Return : None +*******************************************************************************/ +void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1) +{ + u32 data = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((u32)Data2 << 8) | Data1; + } + else + { + data = ((u32)Data2 << 16) | Data1; + } + + /* Set the dual DAC selected data holding register */ + *((vu32 *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data; +} + +/******************************************************************************* +* Function Name : DAC_GetDataOutputValue +* Description : Returns the last data output value of the selected DAC cahnnel. +* Input - DAC_Channel: the selected DAC channel. +* This parameter can be one of the following values: +* - DAC_Channel_1: DAC Channel1 selected +* - DAC_Channel_2: DAC Channel2 selected +* Output : None +* Return : The selected DAC channel data output value. +*******************************************************************************/ +u16 DAC_GetDataOutputValue(u32 DAC_Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + /* Returns the DAC channel data output register value */ + return (u16) (*(vu32*)(DAC_BASE + DOR_Offset + ((u32)DAC_Channel >> 2))); +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_dbgmcu.c b/bsp/stm32/library/src/stm32f10x_dbgmcu.c new file mode 100644 index 0000000000..3fc460ed46 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_dbgmcu.c @@ -0,0 +1,97 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dbgmcu.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the DBGMCU firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define IDCODE_DEVID_Mask ((u32)0x00000FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DBGMCU_GetREVID +* Description : Returns the device revision identifier. +* Input : None +* Output : None +* Return : Device revision identifier +*******************************************************************************/ +u32 DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/******************************************************************************* +* Function Name : DBGMCU_GetDEVID +* Description : Returns the device identifier. +* Input : None +* Output : None +* Return : Device identifier +*******************************************************************************/ +u32 DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); +} + +/******************************************************************************* +* Function Name : DBGMCU_Config +* Description : Configures the specified peripheral and low power mode behavior +* when the MCU under Debug mode. +* Input : - DBGMCU_Periph: specifies the peripheral and low power mode. +* This parameter can be any combination of the following values: +* - DBGMCU_SLEEP: Keep debugger connection during SLEEP mode +* - DBGMCU_STOP: Keep debugger connection during STOP mode +* - DBGMCU_STANDBY: Keep debugger connection during STANDBY mode +* - DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted +* - DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted +* - DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted +* - DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted +* - DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted +* - DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted +* - DBGMCU_CAN_STOP: Debug CAN stopped when Core is halted +* - DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped +* when Core is halted +* - DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped +* when Core is halted +* - DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted +* - DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted +* - DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted +* - DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted +* - NewState: new state of the specified peripheral in Debug mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_dma.c b/bsp/stm32/library/src/stm32f10x_dma.c new file mode 100644 index 0000000000..ab93059405 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_dma.c @@ -0,0 +1,678 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_dma.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the DMA firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((u32)0x00000001) +#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE) + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((u32)0x0000000F) +#define DMA1_Channel2_IT_Mask ((u32)0x000000F0) +#define DMA1_Channel3_IT_Mask ((u32)0x00000F00) +#define DMA1_Channel4_IT_Mask ((u32)0x0000F000) +#define DMA1_Channel5_IT_Mask ((u32)0x000F0000) +#define DMA1_Channel6_IT_Mask ((u32)0x00F00000) +#define DMA1_Channel7_IT_Mask ((u32)0x0F000000) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((u32)0x0000000F) +#define DMA2_Channel2_IT_Mask ((u32)0x000000F0) +#define DMA2_Channel3_IT_Mask ((u32)0x00000F00) +#define DMA2_Channel4_IT_Mask ((u32)0x0000F000) +#define DMA2_Channel5_IT_Mask ((u32)0x000F0000) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((u32)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((u32)0xFFFF800F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DMA_DeInit +* Description : Deinitializes the DMAy Channelx registers to their default reset +* values. +* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + switch (*(u32*)&DMAy_Channelx) + { + case DMA1_Channel1_BASE: + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + break; + + case DMA1_Channel2_BASE: + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + break; + + case DMA1_Channel3_BASE: + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + break; + + case DMA1_Channel4_BASE: + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + break; + + case DMA1_Channel5_BASE: + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + break; + + case DMA1_Channel6_BASE: + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + break; + + case DMA1_Channel7_BASE: + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + break; + + case DMA2_Channel1_BASE: + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + break; + + case DMA2_Channel2_BASE: + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + break; + + case DMA2_Channel3_BASE: + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + break; + + case DMA2_Channel4_BASE: + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + break; + + case DMA2_Channel5_BASE: + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_Init +* Description : Initializes the DMAy Channelx according to the specified +* parameters in the DMA_InitStruct. +* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA Channel. +* Output : None +* Return : None +******************************************************************************/ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/******************************************************************************* +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its default value. +* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/******************************************************************************* +* Function Name : DMA_Cmd +* Description : Enables or disables the specified DMAy Channelx. +* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* - NewState: new state of the DMAy Channelx. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the specified DMAy Channelx interrupts. +* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* - DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - DMA_IT_TC: Transfer complete interrupt mask +* - DMA_IT_HT: Half transfer interrupt mask +* - DMA_IT_TE: Transfer error interrupt mask +* - NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/******************************************************************************* +* Function Name : DMA_GetCurrDataCounter +* Description : Returns the number of remaining data units in the current +* DMAy Channelx transfer. +* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* Output : None +* Return : The number of remaining data units in the current DMAy Channelx +* transfer. +*******************************************************************************/ +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Return the number of remaining data units for DMAy Channelx */ + return ((u16)(DMAy_Channelx->CNDTR)); +} + +/******************************************************************************* +* Function Name : DMA_GetFlagStatus +* Description : Checks whether the specified DMAy Channelx flag is set or not. +* Input : - DMA_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - DMA1_FLAG_GL1: DMA1 Channel1 global flag. +* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. +* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. +* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. +* - DMA1_FLAG_GL2: DMA1 Channel2 global flag. +* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. +* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. +* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. +* - DMA1_FLAG_GL3: DMA1 Channel3 global flag. +* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. +* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. +* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. +* - DMA1_FLAG_GL4: DMA1 Channel4 global flag. +* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. +* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. +* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. +* - DMA1_FLAG_GL5: DMA1 Channel5 global flag. +* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. +* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. +* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. +* - DMA1_FLAG_GL6: DMA1 Channel6 global flag. +* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. +* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. +* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. +* - DMA1_FLAG_GL7: DMA1 Channel7 global flag. +* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. +* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. +* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. +* - DMA2_FLAG_GL1: DMA2 Channel1 global flag. +* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. +* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. +* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. +* - DMA2_FLAG_GL2: DMA2 Channel2 global flag. +* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. +* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. +* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. +* - DMA2_FLAG_GL3: DMA2 Channel3 global flag. +* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. +* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. +* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. +* - DMA2_FLAG_GL4: DMA2 Channel4 global flag. +* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. +* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. +* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. +* - DMA2_FLAG_GL5: DMA2 Channel5 global flag. +* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. +* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. +* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. +* Output : None +* Return : The new state of DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Calculate the used DMA */ + if ((DMA_FLAG & FLAG_Mask) != (u32)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (u32)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : DMA_ClearFlag +* Description : Clears the DMAy Channelx's pending flags. +* Input : - DMA_FLAG: specifies the flag to clear. +* This parameter can be any combination (for the same DMA) of +* the following values: +* - DMA1_FLAG_GL1: DMA1 Channel1 global flag. +* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. +* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. +* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. +* - DMA1_FLAG_GL2: DMA1 Channel2 global flag. +* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. +* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. +* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. +* - DMA1_FLAG_GL3: DMA1 Channel3 global flag. +* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. +* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. +* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. +* - DMA1_FLAG_GL4: DMA1 Channel4 global flag. +* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. +* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. +* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. +* - DMA1_FLAG_GL5: DMA1 Channel5 global flag. +* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. +* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. +* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. +* - DMA1_FLAG_GL6: DMA1 Channel6 global flag. +* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. +* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. +* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. +* - DMA1_FLAG_GL7: DMA1 Channel7 global flag. +* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. +* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. +* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. +* - DMA2_FLAG_GL1: DMA2 Channel1 global flag. +* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. +* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. +* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. +* - DMA2_FLAG_GL2: DMA2 Channel2 global flag. +* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. +* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. +* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. +* - DMA2_FLAG_GL3: DMA2 Channel3 global flag. +* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. +* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. +* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. +* - DMA2_FLAG_GL4: DMA2 Channel4 global flag. +* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. +* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. +* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. +* - DMA2_FLAG_GL5: DMA2 Channel5 global flag. +* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. +* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. +* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearFlag(u32 DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Calculate the used DMA */ + if ((DMA_FLAG & FLAG_Mask) != (u32)RESET) + { + /* Clear the selected DMA flags */ + DMA2->IFCR = DMA_FLAG; + } + else + { + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; + } +} + +/******************************************************************************* +* Function Name : DMA_GetITStatus +* Description : Checks whether the specified DMAy Channelx interrupt has +* occurred or not. +* Input : - DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* - DMA1_IT_GL1: DMA1 Channel1 global interrupt. +* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. +* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. +* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. +* - DMA1_IT_GL2: DMA1 Channel2 global interrupt. +* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. +* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. +* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. +* - DMA1_IT_GL3: DMA1 Channel3 global interrupt. +* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. +* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. +* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. +* - DMA1_IT_GL4: DMA1 Channel4 global interrupt. +* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. +* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. +* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. +* - DMA1_IT_GL5: DMA1 Channel5 global interrupt. +* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. +* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. +* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. +* - DMA1_IT_GL6: DMA1 Channel6 global interrupt. +* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. +* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. +* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. +* - DMA1_IT_GL7: DMA1 Channel7 global interrupt. +* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. +* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. +* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. +* - DMA2_IT_GL1: DMA2 Channel1 global interrupt. +* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. +* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. +* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. +* - DMA2_IT_GL2: DMA2 Channel2 global interrupt. +* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. +* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. +* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. +* - DMA2_IT_GL3: DMA2 Channel3 global interrupt. +* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. +* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. +* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. +* - DMA2_IT_GL4: DMA2 Channel4 global interrupt. +* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. +* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. +* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. +* - DMA2_IT_GL5: DMA2 Channel5 global interrupt. +* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. +* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. +* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. +* Output : None +* Return : The new state of DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus DMA_GetITStatus(u32 DMA_IT) +{ + ITStatus bitstatus = RESET; + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (u32)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (u32)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : DMA_ClearITPendingBit +* Description : Clears the DMAy Channelx’s interrupt pending bits. +* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear. +* This parameter can be any combination (for the same DMA) of +* the following values: +* - DMA1_IT_GL1: DMA1 Channel1 global interrupt. +* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. +* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. +* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. +* - DMA1_IT_GL2: DMA1 Channel2 global interrupt. +* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. +* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. +* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. +* - DMA1_IT_GL3: DMA1 Channel3 global interrupt. +* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. +* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. +* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. +* - DMA1_IT_GL4: DMA1 Channel4 global interrupt. +* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. +* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. +* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. +* - DMA1_IT_GL5: DMA1 Channel5 global interrupt. +* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. +* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. +* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. +* - DMA1_IT_GL6: DMA1 Channel6 global interrupt. +* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. +* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. +* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. +* - DMA1_IT_GL7: DMA1 Channel7 global interrupt. +* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. +* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. +* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. +* - DMA2_IT_GL1: DMA2 Channel1 global interrupt. +* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. +* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. +* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. +* - DMA2_IT_GL2: DMA2 Channel2 global interrupt. +* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. +* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. +* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. +* - DMA2_IT_GL3: DMA2 Channel3 global interrupt. +* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. +* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. +* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. +* - DMA2_IT_GL4: DMA2 Channel4 global interrupt. +* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. +* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. +* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. +* - DMA2_IT_GL5: DMA2 Channel5 global interrupt. +* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. +* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. +* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearITPendingBit(u32 DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (u32)RESET) + { + /* Clear the selected DMA interrupt pending bits */ + DMA2->IFCR = DMA_IT; + } + else + { + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + } +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ + diff --git a/bsp/stm32/library/src/stm32f10x_exti.c b/bsp/stm32/library/src/stm32f10x_exti.c new file mode 100644 index 0000000000..b7820aff50 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_exti.c @@ -0,0 +1,219 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_exti.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the EXTI firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EXTI_DeInit +* Description : Deinitializes the EXTI peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x0007FFFF; +} + +/******************************************************************************* +* Function Name : EXTI_Init +* Description : Initializes the EXTI peripheral according to the specified +* parameters in the EXTI_InitStruct. +* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* that contains the configuration information for the EXTI +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + *(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + *(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line; + } + } + else + { + /* Disable the selected external lines */ + *(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line; + } +} + +/******************************************************************************* +* Function Name : EXTI_StructInit +* Description : Fills each EXTI_InitStruct member with its reset value. +* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EXTI_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - EXTI_Line: specifies the EXTI lines to be enabled or +* disabled. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_GenerateSWInterrupt(u32 EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/******************************************************************************* +* Function Name : EXTI_GetFlagStatus +* Description : Checks whether the specified EXTI line flag is set or not. +* Input : - EXTI_Line: specifies the EXTI line flag to check. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : The new state of EXTI_Line (SET or RESET). +*******************************************************************************/ +FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : EXTI_ClearFlag +* Description : Clears the EXTI’s line pending flags. +* Input : - EXTI_Line: specifies the EXTI lines flags to clear. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_ClearFlag(u32 EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/******************************************************************************* +* Function Name : EXTI_GetITStatus +* Description : Checks whether the specified EXTI line is asserted or not. +* Input : - EXTI_Line: specifies the EXTI line to check. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : The new state of EXTI_Line (SET or RESET). +*******************************************************************************/ +ITStatus EXTI_GetITStatus(u32 EXTI_Line) +{ + ITStatus bitstatus = RESET; + u32 enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + + if (((EXTI->PR & EXTI_Line) != (u32)RESET) && (enablestatus != (u32)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : EXTI_ClearITPendingBit +* Description : Clears the EXTI’s line pending bits. +* Input : - EXTI_Line: specifies the EXTI lines to clear. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_ClearITPendingBit(u32 EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_flash.c b/bsp/stm32/library/src/stm32f10x_flash.c new file mode 100644 index 0000000000..746163387d --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_flash.c @@ -0,0 +1,919 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_flash.c +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file provides all the FLASH firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((u32)0x00000038) +#define ACR_HLFCYA_Mask ((u32)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((u32)0xFFFFFFEF) + +#ifdef _FLASH_PROG +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((u32)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((u32)0x00000001) +#define CR_PG_Reset ((u32)0x00001FFE) + +#define CR_PER_Set ((u32)0x00000002) +#define CR_PER_Reset ((u32)0x00001FFD) + +#define CR_MER_Set ((u32)0x00000004) +#define CR_MER_Reset ((u32)0x00001FFB) + +#define CR_OPTPG_Set ((u32)0x00000010) +#define CR_OPTPG_Reset ((u32)0x00001FEF) + +#define CR_OPTER_Set ((u32)0x00000020) +#define CR_OPTER_Reset ((u32)0x00001FDF) + +#define CR_STRT_Set ((u32)0x00000040) + +#define CR_LOCK_Set ((u32)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((u32)0x00000002) +#define WRP0_Mask ((u32)0x000000FF) +#define WRP1_Mask ((u32)0x0000FF00) +#define WRP2_Mask ((u32)0x00FF0000) +#define WRP3_Mask ((u32)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((u16)0x00A5) +#define FLASH_KEY1 ((u32)0x45670123) +#define FLASH_KEY2 ((u32)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((u32)0x00000FFF) +#define ProgramTimeout ((u32)0x0000000F) +#endif + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#ifdef _FLASH_PROG +static void delay(void); +#endif + +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : FLASH_SetLatency +* Description : Sets the code latency value. +* Input : - FLASH_Latency: specifies the FLASH Latency value. +* This parameter can be one of the following values: +* - FLASH_Latency_0: FLASH Zero Latency cycle +* - FLASH_Latency_1: FLASH One Latency cycle +* - FLASH_Latency_2: FLASH Two Latency cycles +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_SetLatency(u32 FLASH_Latency) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/******************************************************************************* +* Function Name : FLASH_HalfCycleAccessCmd +* Description : Enables or disables the Half cycle flash access. +* Input : - FLASH_HalfCycle: specifies the FLASH Half cycle Access mode. +* This parameter can be one of the following values: +* - FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable +* - FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/******************************************************************************* +* Function Name : FLASH_PrefetchBufferCmd +* Description : Enables or disables the Prefetch Buffer. +* Input : - FLASH_PrefetchBuffer: specifies the Prefetch buffer status. +* This parameter can be one of the following values: +* - FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable +* - FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +#ifdef _FLASH_PROG +/******************************************************************************* +* Function Name : FLASH_Unlock +* Description : Unlocks the FLASH Program Erase Controller. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************* +* Function Name : FLASH_Lock +* Description : Locks the FLASH Program Erase Controller. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the FCR */ + FLASH->CR |= CR_LOCK_Set; +} + +/******************************************************************************* +* Function Name : FLASH_ErasePage +* Description : Erases a specified FLASH page. +* Input : - Page_Address: The page address to be erased. +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_ErasePage(u32 Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_BUSY) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_EraseAllPages +* Description : Erases all FLASH pages. +* Input : None +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_BUSY) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_EraseOptionBytes +* Description : Erases the FLASH option bytes. +* Input : None +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + /* Enable the readout access */ + OB->RDP= RDP_Key; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_BUSY) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_ProgramWord +* Description : Programs a word at a specified address. +* Input : - Address: specifies the address to be programmed. +* - Data: specifies the data to be programmed. +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(vu16*)Address = (u16)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + *(vu16*)(Address + 2) = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_BUSY) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + /* Return the Program Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_ProgramHalfWord +* Description : Programs a half word at a specified address. +* Input : - Address: specifies the address to be programmed. +* - Data: specifies the data to be programmed. +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(vu16*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + /* Return the Program Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_ProgramOptionByteData +* Description : Programs a half word at a specified Option Byte Data address. +* Input : - Address: specifies the address to be programmed. +* This parameter can be 0x1FFFF804 or 0x1FFFF806. +* - Data: specifies the data to be programmed. +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(vu16*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_EnableWriteProtection +* Description : Write protects the desired pages +* Input : - FLASH_Pages: specifies the address of the pages to be +* write protected. This parameter can be: +* - For STM32F10Xxx Medium-density devices (FLASH page size equal to 1 KB) +* - A value between FLASH_WRProt_Pages0to3 and +* FLASH_WRProt_Pages124to127 +* - For STM32F10Xxx High-density devices (FLASH page size equal to 2 KB) +* - A value between FLASH_WRProt_Pages0to1 and +* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 +* - FLASH_WRProt_AllPages +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages) +{ + u16 WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (u32)(~FLASH_Pages); + WRP0_Data = (vu16)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (vu16)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (vu16)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (vu16)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_ReadOutProtection +* Description : Enables or disables the read out protection. +* If the user has already programmed the other option bytes before +* calling this function, he must re-program them since this +* function erases all option bytes. +* Input : - Newstate: new state of the ReadOut Protection. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_BUSY) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_UserOptionByteConfig +* Description : Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / +* RST_STDBY. +* Input : - OB_IWDG: Selects the IWDG mode +* This parameter can be one of the following values: +* - OB_IWDG_SW: Software IWDG selected +* - OB_IWDG_HW: Hardware IWDG selected +* - OB_STOP: Reset event when entering STOP mode. +* This parameter can be one of the following values: +* - OB_STOP_NoRST: No reset generated when entering in STOP +* - OB_STOP_RST: Reset generated when entering in STOP +* - OB_STDBY: Reset event when entering Standby mode. +* This parameter can be one of the following values: +* - OB_STDBY_NoRST: No reset generated when entering in STANDBY +* - OB_STDBY_RST: Reset generated when entering in STANDBY +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = ( OB_IWDG | OB_STOP |OB_STDBY) | (u16)0xF8; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/******************************************************************************* +* Function Name : FLASH_GetUserOptionByte +* Description : Returns the FLASH User Option Bytes values. +* Input : None +* Output : None +* Return : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) +* and RST_STDBY(Bit2). +*******************************************************************************/ +u32 FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (u32)(FLASH->OBR >> 2); +} + +/******************************************************************************* +* Function Name : FLASH_GetWriteProtectionOptionByte +* Description : Returns the FLASH Write Protection Option Bytes Register value. +* Input : None +* Output : None +* Return : The FLASH Write Protection Option Bytes Register value +*******************************************************************************/ +u32 FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (u32)(FLASH->WRPR); +} + +/******************************************************************************* +* Function Name : FLASH_GetReadOutProtectionStatus +* Description : Checks whether the FLASH Read Out Protection Status is set +* or not. +* Input : None +* Output : None +* Return : FLASH ReadOut Protection Status(SET or RESET) +*******************************************************************************/ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + + if ((FLASH->OBR & RDPRT_Mask) != (u32)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/******************************************************************************* +* Function Name : FLASH_GetPrefetchBufferStatus +* Description : Checks whether the FLASH Prefetch Buffer status is set or not. +* Input : None +* Output : None +* Return : FLASH Prefetch Buffer Status (SET or RESET). +*******************************************************************************/ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : FLASH_ITConfig +* Description : Enables or disables the specified FLASH interrupts. +* Input : - FLASH_IT: specifies the FLASH interrupt sources to be +* enabled or disabled. +* This parameter can be any combination of the following values: +* - FLASH_IT_ERROR: FLASH Error Interrupt +* - FLASH_IT_EOP: FLASH end of operation Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(u32)FLASH_IT; + } +} + +/******************************************************************************* +* Function Name : FLASH_GetFlagStatus +* Description : Checks whether the specified FLASH flag is set or not. +* Input : - FLASH_FLAG: specifies the FLASH flag to check. +* This parameter can be one of the following values: +* - FLASH_FLAG_BSY: FLASH Busy flag +* - FLASH_FLAG_PGERR: FLASH Program error flag +* - FLASH_FLAG_WRPRTERR: FLASH Write protected error flag +* - FLASH_FLAG_EOP: FLASH End of Operation flag +* - FLASH_FLAG_OPTERR: FLASH Option Byte error flag +* Output : None +* Return : The new state of FLASH_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : FLASH_ClearFlag +* Description : Clears the FLASH’s pending flags. +* Input : - FLASH_FLAG: specifies the FLASH flags to clear. +* This parameter can be any combination of the following values: +* - FLASH_FLAG_BSY: FLASH Busy flag +* - FLASH_FLAG_PGERR: FLASH Program error flag +* - FLASH_FLAG_WRPRTERR: FLASH Write protected error flag +* - FLASH_FLAG_EOP: FLASH End of Operation flag +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_ClearFlag(u16 FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/******************************************************************************* +* Function Name : FLASH_GetStatus +* Description : Returns the FLASH Status. +* Input : None +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE +*******************************************************************************/ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if(FLASH->SR & FLASH_FLAG_PGERR) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if(FLASH->SR & FLASH_FLAG_WRPRTERR) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/******************************************************************************* +* Function Name : FLASH_WaitForLastOperation +* Description : Waits for a Flash operation to complete or a TIMEOUT to occur. +* Input : - Timeout: FLASH progamming Timeout +* Output : None +* Return : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*******************************************************************************/ +FLASH_Status FLASH_WaitForLastOperation(u32 Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetStatus(); + + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + delay(); + status = FLASH_GetStatus(); + Timeout--; + } + + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + + /* Return the operation status */ + return status; +} + +/******************************************************************************* +* Function Name : delay +* Description : Inserts a time delay. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void delay(void) +{ + vu32 i = 0; + + for(i = 0xFF; i != 0; i--) + { + } +} +#endif + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_fsmc.c b/bsp/stm32/library/src/stm32f10x_fsmc.c new file mode 100644 index 0000000000..0cd37a625c --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_fsmc.c @@ -0,0 +1,851 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_fsmc.c +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file provides all the FSMC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------------------- FSMC registers bit mask ---------------------------- */ +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((u32)0x00000001) +#define BCR_MBKEN_Reset ((u32)0x000FFFFE) +#define BCR_FACCEN_Set ((u32)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((u32)0x00000004) +#define PCR_PBKEN_Reset ((u32)0x000FFFFB) +#define PCR_ECCEN_Set ((u32)0x00000040) +#define PCR_ECCEN_Reset ((u32)0x000FFFBF) +#define PCR_MemoryType_NAND ((u32)0x00000008) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : FSMC_NORSRAMDeInit +* Description : Deinitializes the FSMC NOR/SRAM Banks registers to their default +* reset values. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 +* - FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 +* - FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 +* - FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NORSRAMDeInit(u32 FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/******************************************************************************* +* Function Name : FSMC_NANDDeInit +* Description : Deinitializes the FSMC NAND Banks registers to their default +* reset values. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NANDDeInit(u32 FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/******************************************************************************* +* Function Name : FSMC_PCCARDDeInit +* Description : Deinitializes the FSMC PCCARD Bank registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/******************************************************************************* +* Function Name : FSMC_NORSRAMInit +* Description : Initializes the FSMC NOR/SRAM Banks according to the +* specified parameters in the FSMC_NORSRAMInitStruct. +* Input : - FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef +* structure that contains the configuration information for +* the FSMC NOR/SRAM specified Banks. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (u32)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (u32)BCR_FACCEN_Set; + } + + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (u32)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (u32)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/******************************************************************************* +* Function Name : FSMC_NANDInit +* Description : Initializes the FSMC NAND Banks according to the specified +* parameters in the FSMC_NANDInitStruct. +* Input : - FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef +* structure that contains the configuration information for +* the FSMC NAND specified Banks. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + u32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (u32)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (u32)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (u32)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/******************************************************************************* +* Function Name : FSMC_PCCARDInit +* Description : Initializes the FSMC PCCARD Bank according to the specified +* parameters in the FSMC_PCCARDInitStruct. +* Input : - FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef +* structure that contains the configuration information for +* the FSMC PCCARD Bank. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (u32)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (u32)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (u32)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (u32)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/******************************************************************************* +* Function Name : FSMC_NORSRAMStructInit +* Description : Fills each FSMC_NORSRAMInitStruct member with its default value. +* Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/******************************************************************************* +* Function Name : FSMC_NANDStructInit +* Description : Fills each FSMC_NANDInitStruct member with its default value. +* Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NANDInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/******************************************************************************* +* Function Name : FSMC_PCCARDStructInit +* Description : Fills each FSMC_PCCARDInitStruct member with its default value. +* Input : - FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/******************************************************************************* +* Function Name : FSMC_NORSRAMCmd +* Description : Enables or disables the specified NOR/SRAM Memory Bank. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 +* - FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 +* - FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 +* - FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 +* : - NewState: new state of the FSMC_Bank. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/******************************************************************************* +* Function Name : FSMC_NANDCmd +* Description : Enables or disables the specified NAND Memory Bank. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* : - NewState: new state of the FSMC_Bank. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/******************************************************************************* +* Function Name : FSMC_PCCARDCmd +* Description : Enables or disables the PCCARD Memory Bank. +* Input : - NewState: new state of the PCCARD Memory Bank. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/******************************************************************************* +* Function Name : FSMC_NANDECCCmd +* Description : Enables or disables the FSMC NAND ECC feature. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* : - NewState: new state of the FSMC NAND ECC feature. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/******************************************************************************* +* Function Name : FSMC_GetECC +* Description : Returns the error correction code register value. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* Output : None +* Return : The Error Correction Code (ECC) value. +*******************************************************************************/ +u32 FSMC_GetECC(u32 FSMC_Bank) +{ + u32 eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/******************************************************************************* +* Function Name : FSMC_ITConfig +* Description : Enables or disables the specified FSMC interrupts. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD +* - FSMC_IT: specifies the FSMC interrupt sources to be +* enabled or disabled. +* This parameter can be any combination of the following values: +* - FSMC_IT_RisingEdge: Rising edge detection interrupt. +* - FSMC_IT_Level: Level edge detection interrupt. +* - FSMC_IT_FallingEdge: Falling edge detection interrupt. +* - NewState: new state of the specified FSMC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (u32)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (u32)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (u32)~FSMC_IT; + } + } +} + +/******************************************************************************* +* Function Name : FSMC_GetFlagStatus +* Description : Checks whether the specified FSMC flag is set or not. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD +* - FSMC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - FSMC_FLAG_RisingEdge: Rising egde detection Flag. +* - FSMC_FLAG_Level: Level detection Flag. +* - FSMC_FLAG_FallingEdge: Falling egde detection Flag. +* - FSMC_FLAG_FEMPT: Fifo empty Flag. +* Output : None +* Return : The new state of FSMC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + u32 tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (u16)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : FSMC_ClearFlag +* Description : Clears the FSMC’s pending flags. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD +* - FSMC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - FSMC_FLAG_RisingEdge: Rising egde detection Flag. +* - FSMC_FLAG_Level: Level detection Flag. +* - FSMC_FLAG_FallingEdge: Falling egde detection Flag. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/******************************************************************************* +* Function Name : FSMC_GetITStatus +* Description : Checks whether the specified FSMC interrupt has occurred or not. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD +* - FSMC_IT: specifies the FSMC interrupt source to check. +* This parameter can be one of the following values: +* - FSMC_IT_RisingEdge: Rising edge detection interrupt. +* - FSMC_IT_Level: Level edge detection interrupt. +* - FSMC_IT_FallingEdge: Falling edge detection interrupt. +* Output : None +* Return : The new state of FSMC_IT (SET or RESET). +*******************************************************************************/ +ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT) +{ + ITStatus bitstatus = RESET; + u32 tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + + if ((itstatus != (u32)RESET) && (itenable != (u32)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : FSMC_ClearITPendingBit +* Description : Clears the FSMC’s interrupt pending bits. +* Input : - FSMC_Bank: specifies the FSMC Bank to be used +* This parameter can be one of the following values: +* - FSMC_Bank2_NAND: FSMC Bank2 NAND +* - FSMC_Bank3_NAND: FSMC Bank3 NAND +* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD +* - FSMC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - FSMC_IT_RisingEdge: Rising edge detection interrupt. +* - FSMC_IT_Level: Level edge detection interrupt. +* - FSMC_IT_FallingEdge: Falling edge detection interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_gpio.c b/bsp/stm32/library/src/stm32f10x_gpio.c new file mode 100644 index 0000000000..6c065c9f85 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_gpio.c @@ -0,0 +1,583 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the GPIO firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register ---*/ +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((u8)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + +#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80) +#define LSB_MASK ((u16)0xFFFF) +#define DBGAFR_POSITION_MASK ((u32)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((u32)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((u32)0x00200000) +#define DBGAFR_NUMBITS_MASK ((u32)0x00100000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + switch (*(u32*)&GPIOx) + { + case GPIOA_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + break; + + case GPIOB_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + break; + + case GPIOC_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + break; + + case GPIOD_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + break; + + case GPIOE_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + break; + + case GPIOF_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + break; + + case GPIOG_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_AFIODeInit +* Description : Deinitializes the Alternate Functions (remap, event control +* and EXTI configuration) registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + u32 tmpreg = 0x00, pinmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F); + + if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (u32)GPIO_InitStruct->GPIO_Speed; + } + +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((u32)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((u32)0x0F) << pos; + tmpreg &= ~pinmask; + + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((u32)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((u32)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } + +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((u32)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((u32)0x0F) << pos; + tmpreg &= ~pinmask; + + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Fills each GPIO_InitStruct member with its default value. +* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/******************************************************************************* +* Function Name : GPIO_ReadInputDataBit +* Description : Reads the specified input port pin. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : The input port pin value. +*******************************************************************************/ +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u8 bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET) + { + bitstatus = (u8)Bit_SET; + } + else + { + bitstatus = (u8)Bit_RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : GPIO_ReadInputData +* Description : Reads the specified GPIO input data port. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* Output : None +* Return : GPIO input data port value. +*******************************************************************************/ +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((u16)GPIOx->IDR); +} + +/******************************************************************************* +* Function Name : GPIO_ReadOutputDataBit +* Description : Reads the specified output data port bit. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : The output port pin value. +*******************************************************************************/ +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u8 bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET) + { + bitstatus = (u8)Bit_SET; + } + else + { + bitstatus = (u8)Bit_RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : GPIO_ReadOutputData +* Description : Reads the specified GPIO output data port. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* Output : None +* Return : GPIO output data port value. +*******************************************************************************/ +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((u16)GPIOx->ODR); +} + +/******************************************************************************* +* Function Name : GPIO_SetBits +* Description : Sets the selected data port bits. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bits to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/******************************************************************************* +* Function Name : GPIO_ResetBits +* Description : Clears the selected data port bits. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bits to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be one of GPIO_Pin_x where x can be (0..15). +* - BitVal: specifies the value to be written to the selected bit. +* This parameter can be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes data to the specified GPIO data port. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* - PortVal: specifies the value to be written to the port output +* data register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_PinLockConfig +* Description : Locks GPIO Pins configuration registers. +* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u32 tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/******************************************************************************* +* Function Name : GPIO_EventOutputConfig +* Description : Selects the GPIO pin used as Event output. +* Input : - GPIO_PortSource: selects the GPIO port to be used as source +* for Event output. +* This parameter can be GPIO_PortSourceGPIOx where x can be +* (A..E). +* - GPIO_PinSource: specifies the pin for the Event output. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (u32)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + + AFIO->EVCR = tmpreg; +} + +/******************************************************************************* +* Function Name : GPIO_EventOutputCmd +* Description : Enables or disables the Event Output. +* Input : - NewState: new state of the Event output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) EVCR_EVOE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : GPIO_PinRemapConfig +* Description : Changes the mapping of the specified pin. +* Input : - GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* - GPIO_Remap_SPI1 +* - GPIO_Remap_I2C1 +* - GPIO_Remap_USART1 +* - GPIO_Remap_USART2 +* - GPIO_PartialRemap_USART3 +* - GPIO_FullRemap_USART3 +* - GPIO_PartialRemap_TIM1 +* - GPIO_FullRemap_TIM1 +* - GPIO_PartialRemap1_TIM2 +* - GPIO_PartialRemap2_TIM2 +* - GPIO_FullRemap_TIM2 +* - GPIO_PartialRemap_TIM3 +* - GPIO_FullRemap_TIM3 +* - GPIO_Remap_TIM4 +* - GPIO_Remap1_CAN +* - GPIO_Remap2_CAN +* - GPIO_Remap_PD01 +* - GPIO_Remap_TIM5CH4_LSI +* - GPIO_Remap_ADC1_ETRGINJ +* - GPIO_Remap_ADC1_ETRGREG +* - GPIO_Remap_ADC2_ETRGINJ +* - GPIO_Remap_ADC2_ETRGREG +* - GPIO_Remap_SWJ_NoJTRST +* - GPIO_Remap_SWJ_JTAGDisable +* - GPIO_Remap_SWJ_Disable +* - NewState: new state of the port pin remapping. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState) +{ + u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = AFIO->MAPR; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((u32)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + AFIO->MAPR = tmpreg; +} + +/******************************************************************************* +* Function Name : GPIO_EXTILineConfig +* Description : Selects the GPIO pin used as EXTI Line. +* Input : - GPIO_PortSource: selects the GPIO port to be used as +* source for EXTI lines. +* This parameter can be GPIO_PortSourceGPIOx where x can be +* (A..G). +* - GPIO_PinSource: specifies the EXTI line to be configured. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03)); + + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03))); +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_i2c.c b/bsp/stm32/library/src/stm32f10x_i2c.c new file mode 100644 index 0000000000..8c27db85b9 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_i2c.c @@ -0,0 +1,1216 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_i2c.c +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file provides all the I2C firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* I2C SPE mask */ +#define CR1_PE_Set ((u16)0x0001) +#define CR1_PE_Reset ((u16)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((u16)0x0100) +#define CR1_START_Reset ((u16)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((u16)0x0200) +#define CR1_STOP_Reset ((u16)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((u16)0x0400) +#define CR1_ACK_Reset ((u16)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((u16)0x0040) +#define CR1_ENGC_Reset ((u16)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((u16)0x8000) +#define CR1_SWRST_Reset ((u16)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((u16)0x1000) +#define CR1_PEC_Reset ((u16)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((u16)0x0020) +#define CR1_ENPEC_Reset ((u16)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((u16)0x0010) +#define CR1_ENARP_Reset ((u16)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((u16)0x0080) +#define CR1_NOSTRETCH_Reset ((u16)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((u16)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((u16)0x0800) +#define CR2_DMAEN_Reset ((u16)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((u16)0x1000) +#define CR2_LAST_Reset ((u16)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((u16)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((u16)0x0001) +#define OAR1_ADD0_Reset ((u16)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((u16)0x0001) +#define OAR2_ENDUAL_Reset ((u16)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((u16)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((u16)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((u16)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((u32)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((u32)0x07000000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2Cx peripheral registers to their default +* reset values. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + switch (*(u32*)&I2Cx) + { + case I2C1_BASE: + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + break; + + case I2C2_BASE: + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2Cx peripheral according to the specified +* parameters in the I2C_InitStruct. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified +* I2C peripheral. +* Output : None +* Return : None +******************************************************************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u16 tmpreg = 0, freqrange = 0; + u16 result = 0x04; + u32 pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (u16)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (u16)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= result | CCR_FS_Set; + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1); + } + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Fills each I2C_InitStruct member with its default value. +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the specified I2C peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_DMACmd +* Description : Enables or disables the specified I2C DMA requests. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_DMALastTransferCmd +* Description : Specifies that the next DMA transfer is the last one. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C DMA last transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2Cx communication START condition. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2Cx communication STOP condition. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables the specified I2C acknowledge feature. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C Acknowledgement. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_OwnAddress2Config +* Description : Configures the specified I2C own address2. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Address: specifies the 7bit I2C own address2. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + /* Set I2Cx Own address2 */ + tmpreg |= (u16)(Address & (u16)0x00FE); + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/******************************************************************************* +* Function Name : I2C_DualAddressCmd +* Description : Enables or disables the specified I2C dual addressing mode. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C dual addressing mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GeneralCallCmd +* Description : Enables or disables the specified I2C general call feature. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C General call. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables the specified I2C interrupts. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the I2C interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - I2C_IT_BUF: Buffer interrupt mask +* - I2C_IT_EVT: Event interrupt mask +* - I2C_IT_ERR: Error interrupt mask +* - NewState: new state of the specified I2C interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (u16)~I2C_IT; + } +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Sends a data byte through the I2Cx peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Data: Byte to be transmitted.. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Returns the most recent received data by the I2Cx peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the data in the DR register */ + return (u8)I2Cx->DR; +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Address: specifies the slave address which will be transmitted +* - I2C_Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. +* This parameter can be one of the following values +* - I2C_Direction_Transmitter: Transmitter mode +* - I2C_Direction_Receiver: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads the specified I2C register and returns its value. +* Input1 : - I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* - I2C_Register_CR1: CR1 register. +* - I2C_Register_CR2: CR2 register. +* - I2C_Register_OAR1: OAR1 register. +* - I2C_Register_OAR2: OAR2 register. +* - I2C_Register_DR: DR register. +* - I2C_Register_SR1: SR1 register. +* - I2C_Register_SR2: SR2 register. +* - I2C_Register_CCR: CCR register. +* - I2C_Register_TRISE: TRISE register. +* Output : None +* Return : The value of the read register. +*******************************************************************************/ +u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + /* Return the selected register value */ + return (*(vu16 *)(*((vu32 *)&I2Cx) + I2C_Register)); +} + +/******************************************************************************* +* Function Name : I2C_SoftwareResetCmd +* Description : Enables or disables the specified I2C software reset. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C software reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_SMBusAlertConfig +* Description : Drives the SMBusAlert pin high or low for the specified I2C. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_SMBusAlert: specifies SMBAlert pin level. +* This parameter can be one of the following values: +* - I2C_SMBusAlert_Low: SMBAlert pin driven low +* - I2C_SMBusAlert_High: SMBAlert pin driven high +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/******************************************************************************* +* Function Name : I2C_TransmitPEC +* Description : Enables or disables the specified I2C PEC transfer. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C PEC transmission. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_PECPositionConfig +* Description : Selects the specified I2C PEC position. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_PECPosition: specifies the PEC position. +* This parameter can be one of the following values: +* - I2C_PECPosition_Next: indicates that the next +* byte is PEC +* - I2C_PECPosition_Current: indicates that current +* byte is PEC +* Output : None +* Return : None +*******************************************************************************/ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/******************************************************************************* +* Function Name : I2C_CalculatePEC +* Description : Enables or disables the PEC value calculation of the +* transfered bytes. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx PEC value calculation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GetPEC +* Description : Returns the PEC value for the specified I2C. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The PEC value. +*******************************************************************************/ +u8 I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/******************************************************************************* +* Function Name : I2C_ARPCmd +* Description : Enables or disables the specified I2C ARP. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx ARP. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_StretchClockCmd +* Description : Enables or disables the specified I2C Clock stretching. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx Clock stretching. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_FastModeDutyCycleConfig +* Description : Selects the specified I2C fast mode duty cycle. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_DutyCycle: specifies the fast mode duty cycle. +* This parameter can be one of the following values: +* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 +* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 +* Output : None +* Return : None +*******************************************************************************/ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Returns the last I2Cx Event. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The last event +*******************************************************************************/ +u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + u32 lastevent = 0; + u32 flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the last I2Cx Event is equal to the one passed +* as parameter. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_EVENT: specifies the event to be checked. +* This parameter can be one of the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1 +* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 +* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2 +* - I2C_EVENT_MASTER_MODE_SELECT : EV5 +* - I2C_EVENT_MASTER_MODE_SELECTED : EV6 +* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8 +* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 +* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4 +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_EVENT +* - ERROR: Last event is different from the I2C_EVENT +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT) +{ + u32 lastevent = 0; + u32 flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event is equal to I2C_EVENT */ + if (lastevent == I2C_EVENT ) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + + /* Return status */ + return status; +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - I2C_FLAG_DUALF: Dual flag (Slave mode) +* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode) +* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) +* - I2C_FLAG_GENCALL: General call header flag (Slave mode) +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_MSL: Master/Slave flag +* - I2C_FLAG_SMBALERT: SMBus Alert flag +* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag +* - I2C_FLAG_PECERR: PEC error in reception flag +* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_TXE: Data register empty flag (Transmitter) +* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag +* - I2C_FLAG_STOPF: Stop detection flag (Slave mode) +* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL +* Address matched flag (Slave mode)”ENDAD +* - I2C_FLAG_SB: Start bit flag (Master mode) +* Output : None +* Return : The new state of I2C_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + vu32 i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (*(u32*)&(I2Cx)); + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (u32)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(vu32 *)i2cxbase) & I2C_FLAG) != (u32)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2Cx's pending flags. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following +* values: +* - I2C_FLAG_SMBALERT: SMBus Alert flag +* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag +* - I2C_FLAG_PECERR: PEC error in reception flag +* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode) +* - I2C_FLAG_BERR: Bus error flag +* +* Notes: +* - STOPF (STOP detection) is cleared by software +* sequence: a read operation to I2C_SR1 register +* (I2C_GetFlagStatus()) followed by a write operation +* to I2C_CR1 register (I2C_Cmd() to re-enable the +* I2C peripheral). +* - ADD10 (10-bit header sent) is cleared by software +* sequence: a read operation to I2C_SR1 +* (I2C_GetFlagStatus()) followed by writing the +* second byte of the address in DR register. +* - BTF (Byte Transfer Finished) is cleared by software +* sequence: a read operation to I2C_SR1 register +* (I2C_GetFlagStatus()) followed by a read/write to +* I2C_DR register (I2C_SendData()). +* - ADDR (Address sent) is cleared by software sequence: +* a read operation to I2C_SR1 register +* (I2C_GetFlagStatus()) followed by a read operation to +* I2C_SR2 register ((void)(I2Cx->SR2)). +* - SB (Start Bit) is cleared software sequence: a read +* operation to I2C_SR1 register (I2C_GetFlagStatus()) +* followed by a write operation to I2C_DR reigister +* (I2C_SendData()). +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG) +{ + u32 flagpos = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + + /* Clear the selected I2C flag */ + I2Cx->SR1 = (u16)~flagpos; +} + +/******************************************************************************* +* Function Name : I2C_GetITStatus +* Description : Checks whether the specified I2C interrupt has occurred or not. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - I2C_IT_SMBALERT: SMBus Alert flag +* - I2C_IT_TIMEOUT: Timeout or Tlow error flag +* - I2C_IT_PECERR: PEC error in reception flag +* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_IT_AF: Acknowledge failure flag +* - I2C_IT_ARLO: Arbitration lost flag (Master mode) +* - I2C_IT_BERR: Bus error flag +* - I2C_IT_TXE: Data register empty flag (Transmitter) +* - I2C_IT_RXNE: Data register not empty (Receiver) flag +* - I2C_IT_STOPF: Stop detection flag (Slave mode) +* - I2C_IT_ADD10: 10-bit header sent flag (Master mode) +* - I2C_IT_BTF: Byte transfer finished flag +* - I2C_IT_ADDR: Address sent flag (Master mode) “ADSL +* Address matched flag (Slave mode)”ENDAD +* - I2C_IT_SB: Start bit flag (Master mode) +* Output : None +* Return : The new state of I2C_IT (SET or RESET). +*******************************************************************************/ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT) +{ + ITStatus bitstatus = RESET; + u32 enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (u32)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (u32)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : I2C_ClearITPendingBit +* Description : Clears the I2Cx’s interrupt pending bits. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following +* values: +* - I2C_IT_SMBALERT: SMBus Alert interrupt +* - I2C_IT_TIMEOUT: Timeout or Tlow error interrupt +* - I2C_IT_PECERR: PEC error in reception interrupt +* - I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) +* - I2C_IT_AF: Acknowledge failure interrupt +* - I2C_IT_ARLO: Arbitration lost interrupt (Master mode) +* - I2C_IT_BERR: Bus error interrupt +* +* Notes: +* - STOPF (STOP detection) is cleared by software +* sequence: a read operation to I2C_SR1 register +* (I2C_GetITStatus()) followed by a write operation to +* I2C_CR1 register (I2C_Cmd() to re-enable the I2C +* peripheral). +* - ADD10 (10-bit header sent) is cleared by software +* sequence: a read operation to I2C_SR1 +* (I2C_GetITStatus()) followed by writing the second +* byte of the address in I2C_DR register. +* - BTF (Byte Transfer Finished) is cleared by software +* sequence: a read operation to I2C_SR1 register +* (I2C_GetITStatus()) followed by a read/write to +* I2C_DR register (I2C_SendData()). +* - ADDR (Address sent) is cleared by software sequence: +* a read operation to I2C_SR1 register (I2C_GetITStatus()) +* followed by a read operation to I2C_SR2 register +* ((void)(I2Cx->SR2)). +* - SB (Start Bit) is cleared by software sequence: a +* read operation to I2C_SR1 register (I2C_GetITStatus()) +* followed by a write operation to I2C_DR reigister +* (I2C_SendData()). +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT) +{ + u32 flagpos = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + + /* Clear the selected I2C flag */ + I2Cx->SR1 = (u16)~flagpos; +} + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_iwdg.c b/bsp/stm32/library/src/stm32f10x_iwdg.c new file mode 100644 index 0000000000..b75a4f97cb --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_iwdg.c @@ -0,0 +1,148 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_iwdg.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the IWDG firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- IWDG registers bit mask ------------------------ */ +/* KR register bit mask */ +#define KR_KEY_Reload ((u16)0xAAAA) +#define KR_KEY_Enable ((u16)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : IWDG_WriteAccessCmd +* Description : Enables or disables write access to IWDG_PR and IWDG_RLR +* registers. +* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and +* IWDG_RLR registers. +* This parameter can be one of the following values: +* - IWDG_WriteAccess_Enable: Enable write access to +* IWDG_PR and IWDG_RLR registers +* - IWDG_WriteAccess_Disable: Disable write access to +* IWDG_PR and IWDG_RLR registers +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + + IWDG->KR = IWDG_WriteAccess; +} + +/******************************************************************************* +* Function Name : IWDG_SetPrescaler +* Description : Sets IWDG Prescaler value. +* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value. +* This parameter can be one of the following values: +* - IWDG_Prescaler_4: IWDG prescaler set to 4 +* - IWDG_Prescaler_8: IWDG prescaler set to 8 +* - IWDG_Prescaler_16: IWDG prescaler set to 16 +* - IWDG_Prescaler_32: IWDG prescaler set to 32 +* - IWDG_Prescaler_64: IWDG prescaler set to 64 +* - IWDG_Prescaler_128: IWDG prescaler set to 128 +* - IWDG_Prescaler_256: IWDG prescaler set to 256 +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_SetPrescaler(u8 IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + + IWDG->PR = IWDG_Prescaler; +} + +/******************************************************************************* +* Function Name : IWDG_SetReload +* Description : Sets IWDG Reload value. +* Input : - Reload: specifies the IWDG Reload value. +* This parameter must be a number between 0 and 0x0FFF. +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_SetReload(u16 Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + + IWDG->RLR = Reload; +} + +/******************************************************************************* +* Function Name : IWDG_ReloadCounter +* Description : Reloads IWDG counter with value defined in the reload register +* (write access to IWDG_PR and IWDG_RLR registers disabled). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/******************************************************************************* +* Function Name : IWDG_Enable +* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers +* disabled). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/******************************************************************************* +* Function Name : IWDG_GetFlagStatus +* Description : Checks whether the specified IWDG flag is set or not. +* Input : - IWDG_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - IWDG_FLAG_PVU: Prescaler Value Update on going +* - IWDG_FLAG_RVU: Reload Value Update on going +* Output : None +* Return : The new state of IWDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + + if ((IWDG->SR & IWDG_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_lib.c b/bsp/stm32/library/src/stm32f10x_lib.c new file mode 100644 index 0000000000..c39d38b41a --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_lib.c @@ -0,0 +1,303 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_lib.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#ifdef DEBUG +/******************************************************************************* +* Function Name : debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void debug(void) +{ + +/************************************* ADC ************************************/ +#ifdef _ADC1 + ADC1 = (ADC_TypeDef *) ADC1_BASE; +#endif /*_ADC1 */ + +#ifdef _ADC2 + ADC2 = (ADC_TypeDef *) ADC2_BASE; +#endif /*_ADC2 */ + +#ifdef _ADC3 + ADC3 = (ADC_TypeDef *) ADC3_BASE; +#endif /*_ADC3 */ + +/************************************* BKP ************************************/ +#ifdef _BKP + BKP = (BKP_TypeDef *) BKP_BASE; +#endif /*_BKP */ + +/************************************* CAN ************************************/ +#ifdef _CAN + CAN = (CAN_TypeDef *) CAN_BASE; +#endif /*_CAN */ + +/************************************* CRC ************************************/ +#ifdef _CRC + CRC = (CRC_TypeDef *) CRC_BASE; +#endif /*_CRC */ + +/************************************* DAC ************************************/ +#ifdef _DAC + DAC = (DAC_TypeDef *) DAC_BASE; +#endif /*_DAC */ + +/************************************* DBGMCU**********************************/ +#ifdef _DBGMCU + DBGMCU = (DBGMCU_TypeDef *) DBGMCU_BASE; +#endif /*_DBGMCU */ + +/************************************* DMA ************************************/ +#ifdef _DMA + DMA1 = (DMA_TypeDef *) DMA1_BASE; + DMA2 = (DMA_TypeDef *) DMA2_BASE; +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + DMA1_Channel1 = (DMA_Channel_TypeDef *) DMA1_Channel1_BASE; +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + DMA1_Channel2 = (DMA_Channel_TypeDef *) DMA1_Channel2_BASE; +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + DMA1_Channel3 = (DMA_Channel_TypeDef *) DMA1_Channel3_BASE; +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + DMA1_Channel4 = (DMA_Channel_TypeDef *) DMA1_Channel4_BASE; +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + DMA1_Channel5 = (DMA_Channel_TypeDef *) DMA1_Channel5_BASE; +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + DMA1_Channel6 = (DMA_Channel_TypeDef *) DMA1_Channel6_BASE; +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + DMA1_Channel7 = (DMA_Channel_TypeDef *) DMA1_Channel7_BASE; +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + DMA2_Channel1 = (DMA_Channel_TypeDef *) DMA2_Channel1_BASE; +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + DMA2_Channel2 = (DMA_Channel_TypeDef *) DMA2_Channel2_BASE; +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + DMA2_Channel3 = (DMA_Channel_TypeDef *) DMA2_Channel3_BASE; +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + DMA2_Channel4 = (DMA_Channel_TypeDef *) DMA2_Channel4_BASE; +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + DMA2_Channel5 = (DMA_Channel_TypeDef *) DMA2_Channel5_BASE; +#endif /*_DMA2_Channel5 */ + +/************************************* EXTI ***********************************/ +#ifdef _EXTI + EXTI = (EXTI_TypeDef *) EXTI_BASE; +#endif /*_EXTI */ + +/************************************* FLASH and Option Bytes *****************/ +#ifdef _FLASH + FLASH = (FLASH_TypeDef *) FLASH_R_BASE; + OB = (OB_TypeDef *) OB_BASE; +#endif /*_FLASH */ + +/************************************* FSMC ***********************************/ +#ifdef _FSMC + FSMC_Bank1 = (FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE; + FSMC_Bank1E = (FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE; + FSMC_Bank2 = (FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE; + FSMC_Bank3 = (FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE; + FSMC_Bank4 = (FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE; +#endif /*_FSMC */ + +/************************************* GPIO ***********************************/ +#ifdef _GPIOA + GPIOA = (GPIO_TypeDef *) GPIOA_BASE; +#endif /*_GPIOA */ + +#ifdef _GPIOB + GPIOB = (GPIO_TypeDef *) GPIOB_BASE; +#endif /*_GPIOB */ + +#ifdef _GPIOC + GPIOC = (GPIO_TypeDef *) GPIOC_BASE; +#endif /*_GPIOC */ + +#ifdef _GPIOD + GPIOD = (GPIO_TypeDef *) GPIOD_BASE; +#endif /*_GPIOD */ + +#ifdef _GPIOE + GPIOE = (GPIO_TypeDef *) GPIOE_BASE; +#endif /*_GPIOE */ + +#ifdef _GPIOF + GPIOF = (GPIO_TypeDef *) GPIOF_BASE; +#endif /*_GPIOF */ + +#ifdef _GPIOG + GPIOG = (GPIO_TypeDef *) GPIOG_BASE; +#endif /*_GPIOG */ + +#ifdef _AFIO + AFIO = (AFIO_TypeDef *) AFIO_BASE; +#endif /*_AFIO */ + +/************************************* I2C ************************************/ +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *) I2C1_BASE; +#endif /*_I2C1 */ + +#ifdef _I2C2 + I2C2 = (I2C_TypeDef *) I2C2_BASE; +#endif /*_I2C2 */ + +/************************************* IWDG ***********************************/ +#ifdef _IWDG + IWDG = (IWDG_TypeDef *) IWDG_BASE; +#endif /*_IWDG */ + +/************************************* NVIC ***********************************/ +#ifdef _NVIC + NVIC = (NVIC_TypeDef *) NVIC_BASE; + SCB = (SCB_TypeDef *) SCB_BASE; +#endif /*_NVIC */ + +/************************************* PWR ************************************/ +#ifdef _PWR + PWR = (PWR_TypeDef *) PWR_BASE; +#endif /*_PWR */ + +/************************************* RCC ************************************/ +#ifdef _RCC + RCC = (RCC_TypeDef *) RCC_BASE; +#endif /*_RCC */ + +/************************************* RTC ************************************/ +#ifdef _RTC + RTC = (RTC_TypeDef *) RTC_BASE; +#endif /*_RTC */ + +/************************************* SDIO ***********************************/ +#ifdef _SDIO + SDIO = (SDIO_TypeDef *) SDIO_BASE; +#endif /*_SDIO */ + +/************************************* SPI ************************************/ +#ifdef _SPI1 + SPI1 = (SPI_TypeDef *) SPI1_BASE; +#endif /*_SPI1 */ + +#ifdef _SPI2 + SPI2 = (SPI_TypeDef *) SPI2_BASE; +#endif /*_SPI2 */ + +#ifdef _SPI3 + SPI3 = (SPI_TypeDef *) SPI3_BASE; +#endif /*_SPI3 */ + +/************************************* SysTick ********************************/ +#ifdef _SysTick + SysTick = (SysTick_TypeDef *) SysTick_BASE; +#endif /*_SysTick */ + +/************************************* TIM ************************************/ +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *) TIM1_BASE; +#endif /*_TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *) TIM2_BASE; +#endif /*_TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *) TIM3_BASE; +#endif /*_TIM3 */ + +#ifdef _TIM4 + TIM4 = (TIM_TypeDef *) TIM4_BASE; +#endif /*_TIM4 */ + +#ifdef _TIM5 + TIM5 = (TIM_TypeDef *) TIM5_BASE; +#endif /*_TIM5 */ + +#ifdef _TIM6 + TIM6 = (TIM_TypeDef *) TIM6_BASE; +#endif /*_TIM6 */ + +#ifdef _TIM7 + TIM7 = (TIM_TypeDef *) TIM7_BASE; +#endif /*_TIM7 */ + +#ifdef _TIM8 + TIM8 = (TIM_TypeDef *) TIM8_BASE; +#endif /*_TIM8 */ + +/************************************* USART **********************************/ +#ifdef _USART1 + USART1 = (USART_TypeDef *) USART1_BASE; +#endif /*_USART1 */ + +#ifdef _USART2 + USART2 = (USART_TypeDef *) USART2_BASE; +#endif /*_USART2 */ + +#ifdef _USART3 + USART3 = (USART_TypeDef *) USART3_BASE; +#endif /*_USART3 */ + +#ifdef _UART4 + UART4 = (USART_TypeDef *) UART4_BASE; +#endif /*_UART4 */ + +#ifdef _UART5 + UART5 = (USART_TypeDef *) UART5_BASE; +#endif /*_UART5 */ + +/************************************* WWDG ***********************************/ +#ifdef _WWDG + WWDG = (WWDG_TypeDef *) WWDG_BASE; +#endif /*_WWDG */ +} +#endif /* DEBUG*/ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_nvic.c b/bsp/stm32/library/src/stm32f10x_nvic.c new file mode 100644 index 0000000000..40c6fe324f --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_nvic.c @@ -0,0 +1,751 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the NVIC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_nvic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : NVIC_DeInit +* Description : Deinitializes the NVIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_DeInit(void) +{ + u32 index = 0; + + NVIC->ICER[0] = 0xFFFFFFFF; + NVIC->ICER[1] = 0x0FFFFFFF; + NVIC->ICPR[0] = 0xFFFFFFFF; + NVIC->ICPR[1] = 0x0FFFFFFF; + + for(index = 0; index < 0x0F; index++) + { + NVIC->IPR[index] = 0x00000000; + } +} + +/******************************************************************************* +* Function Name : NVIC_SCBDeInit +* Description : Deinitializes the SCB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SCBDeInit(void) +{ + u32 index = 0x00; + + SCB->ICSR = 0x0A000000; + SCB->VTOR = 0x00000000; + SCB->AIRCR = AIRCR_VECTKEY_MASK; + SCB->SCR = 0x00000000; + SCB->CCR = 0x00000000; + for(index = 0; index < 0x03; index++) + { + SCB->SHPR[index] = 0; + } + SCB->SHCSR = 0x00000000; + SCB->CFSR = 0xFFFFFFFF; + SCB->HFSR = 0xFFFFFFFF; + SCB->DFSR = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : NVIC_PriorityGroupConfig +* Description : Configures the priority grouping: pre-emption priority +* and subpriority. +* Input : - NVIC_PriorityGroup: specifies the priority grouping bits +* length. This parameter can be one of the following values: +* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority +* 4 bits for subpriority +* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority +* 3 bits for subpriority +* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority +* 2 bits for subpriority +* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority +* 1 bits for subpriority +* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority +* 0 bits for subpriority +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/******************************************************************************* +* Function Name : NVIC_Init +* Description : Initializes the NVIC peripheral according to the specified +* parameters in the NVIC_InitStruct. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure +* that contains the configuration information for the +* specified NVIC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00; + u32 tmppre = 0, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + + tmppriority = tmppriority << 0x04; + tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + + tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)]; + tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + tmpreg &= ~tmpmask; + tmppriority &= tmpmask; + tmpreg |= tmppriority; + + NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } +} + +/******************************************************************************* +* Function Name : NVIC_StructInit +* Description : Fills each NVIC_InitStruct member with its default value. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct) +{ + /* NVIC_InitStruct members default value */ + NVIC_InitStruct->NVIC_IRQChannel = 0x00; + NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : NVIC_SETPRIMASK +* Description : Enables the PRIMASK priority: Raises the execution priority to 0. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETPRIMASK(void) +{ + __SETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETPRIMASK +* Description : Disables the PRIMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETPRIMASK(void) +{ + __RESETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_SETFAULTMASK +* Description : Enables the FAULTMASK priority: Raises the execution priority to -1. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETFAULTMASK(void) +{ + __SETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETFAULTMASK +* Description : Disables the FAULTMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETFAULTMASK(void) +{ + __RESETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_BASEPRICONFIG +* Description : The execution priority can be changed from 15 (lowest + configurable priority) to 1. Writing a zero value will disable +* the mask of execution priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_BASEPRICONFIG(u32 NewPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_BASE_PRI(NewPriority)); + + __BASEPRICONFIG(NewPriority << 0x04); +} + +/******************************************************************************* +* Function Name : NVIC_GetBASEPRI +* Description : Returns the BASEPRI mask value. +* Input : None +* Output : None +* Return : BASEPRI register value +*******************************************************************************/ +u32 NVIC_GetBASEPRI(void) +{ + return (__GetBASEPRI()); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentPendingIRQChannel +* Description : Returns the current pending IRQ channel identifier. +* Input : None +* Output : None +* Return : Pending IRQ Channel Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentPendingIRQChannel(void) +{ + return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelPendingBitStatus +* Description : Checks whether the specified IRQ Channel pending bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check. +* Output : None +* Return : The new state of IRQ Channel pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus pendingirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp) + { + pendingirqstatus = SET; + } + else + { + pendingirqstatus = RESET; + } + return pendingirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetIRQChannelPendingBit +* Description : Sets the NVIC’s interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + *(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel; +} + +/******************************************************************************* +* Function Name : NVIC_ClearIRQChannelPendingBit +* Description : Clears the NVIC’s interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentActiveHandler +* Description : Returns the current active Handler (IRQ Channel and +* SystemHandler) identifier. +* Input : None +* Output : None +* Return : Active Handler Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentActiveHandler(void) +{ + return ((u16)(SCB->ICSR & (u32)0x3FF)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelActiveBitStatus +* Description : Checks whether the specified IRQ Channel active bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check. +* Output : None +* Return : The new state of IRQ Channel active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus activeirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp ) + { + activeirqstatus = SET; + } + else + { + activeirqstatus = RESET; + } + return activeirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetCPUID +* Description : Returns the ID number, the version number and the implementation +* details of the Cortex-M3 core. +* Input : None +* Output : None +* Return : CPU ID. +*******************************************************************************/ +u32 NVIC_GetCPUID(void) +{ + return (SCB->CPUID); +} + +/******************************************************************************* +* Function Name : NVIC_SetVectorTable +* Description : Sets the vector table location and Offset. +* Input : - NVIC_VectTab: specifies if the vector table is in RAM or +* FLASH memory. +* This parameter can be one of the following values: +* - NVIC_VectTab_RAM +* - NVIC_VectTab_FLASH +* - Offset: Vector Table base offset field. +* This value must be a multiple of 0x100. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80); +} + +/******************************************************************************* +* Function Name : NVIC_GenerateSystemReset +* Description : Generates a system reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateSystemReset(void) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04; +} + +/******************************************************************************* +* Function Name : NVIC_GenerateCoreReset +* Description : Generates a Core (Core + NVIC) reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateCoreReset(void) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01; +} + +/******************************************************************************* +* Function Name : NVIC_SystemLPConfig +* Description : Selects the condition for the system to enter low power mode. +* Input : - LowPowerMode: Specifies the new mode for the system to enter +* low power mode. +* This parameter can be one of the following values: +* - NVIC_LP_SEVONPEND +* - NVIC_LP_SLEEPDEEP +* - NVIC_LP_SLEEPONEXIT +* - NewState: new state of LP condition. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (u32)(~(u32)LowPowerMode); + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerConfig +* Description : Enables or disables the specified System Handlers. +* Input : - SystemHandler: specifies the system handler to be enabled +* or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - NewState: new state of specified System Handlers. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F); + + if (NewState != DISABLE) + { + SCB->SHCSR |= tmpreg; + } + else + { + SCB->SHCSR &= ~tmpreg; + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerPriorityConfig +* Description : Configures the specified System Handlers priority. +* Input : - SystemHandler: specifies the system handler to be +* enabled or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* - SystemHandlerPreemptionPriority: new priority group of the +* specified system handlers. +* - SystemHandlerSubPriority: new sub priority of the specified +* system handlers. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority) +{ + u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00; + u32 tmppriority = 0x00; + + /* Check the parameters */ + assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority)); + + tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08; + tmp1 = (0x4 - tmppriority); + tmp2 = tmp2 >> tmppriority; + + tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1; + tmppriority |= SystemHandlerSubPriority & tmp2; + + tmppriority = tmppriority << 0x04; + tmp1 = SystemHandler & (u32)0xC0; + tmp1 = tmp1 >> 0x06; + tmp2 = (SystemHandler >> 0x08) & (u32)0x03; + tmppriority = tmppriority << (tmp2 * 0x08); + handlermask = (u32)0xFF << (tmp2 * 0x08); + + SCB->SHPR[tmp1] &= ~handlermask; + SCB->SHPR[tmp1] |= tmppriority; +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerPendingBitStatus +* Description : Checks whether the specified System handlers pending bit is +* set or not. +* Input : - SystemHandler: specifies the system handler pending bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_SVCall +* Output : None +* Return : The new state of System Handler pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert_param(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0A); + tmppos &= (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SHCSR & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetSystemHandlerPendingBit +* Description : Sets System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit +* to be set. +* This parameter can be one of the following values: +* - SystemHandler_NMI +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Set the corresponding System Handler pending bit */ + SCB->ICSR |= ((u32)0x01 << tmp); +} + +/******************************************************************************* +* Function Name : NVIC_ClearSystemHandlerPendingBit +* Description : Clears System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit to +* be clear. +* This parameter can be one of the following values: +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Clear the corresponding System Handler pending bit */ + SCB->ICSR |= ((u32)0x01 << (tmp - 0x01)); +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerActiveBitStatus +* Description : Checks whether the specified System handlers active bit is +* set or not. +* Input : - SystemHandler: specifies the system handler active bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : The new state of System Handler active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert_param(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0E) & (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SHCSR & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultHandlerSources +* Description : Returns the system fault handlers sources. +* Input : - SystemHandler: specifies the system handler to get its fault +* sources. +* This parameter can be one of the following values: +* - SystemHandler_HardFault +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_DebugMonitor +* Output : None +* Return : Source of the fault handler. +*******************************************************************************/ +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler) +{ + u32 faultsources = 0x00; + u32 tmpreg = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler)); + + tmpreg = (SystemHandler >> 0x12) & (u32)0x03; + tmppos = (SystemHandler >> 0x14) & (u32)0x03; + + if (tmpreg == 0x00) + { + faultsources = SCB->HFSR; + } + else if (tmpreg == 0x01) + { + faultsources = SCB->CFSR >> (tmppos * 0x08); + if (tmppos != 0x02) + { + faultsources &= (u32)0x0F; + } + else + { + faultsources &= (u32)0xFF; + } + } + else + { + faultsources = SCB->DFSR; + } + return faultsources; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultAddress +* Description : Returns the address of the location that generated a fault +* handler. +* Input : - SystemHandler: specifies the system handler to get its +* fault address. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* Output : None +* Return : Fault address. +*******************************************************************************/ +u32 NVIC_GetFaultAddress(u32 SystemHandler) +{ + u32 faultaddress = 0x00; + u32 tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler)); + + tmp = (SystemHandler >> 0x16) & (u32)0x01; + + if (tmp == 0x00) + { + faultaddress = SCB->MMFAR; + } + else + { + faultaddress = SCB->BFAR; + } + return faultaddress; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_pwr.c b/bsp/stm32/library/src/stm32f10x_pwr.c new file mode 100644 index 0000000000..b8b4891320 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_pwr.c @@ -0,0 +1,280 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_pwr.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the PWR firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_PDDS_Set ((u32)0x00000002) +#define CR_DS_Mask ((u32)0xFFFFFFFC) +#define CR_CWUF_Set ((u32)0x00000004) +#define CR_PLS_Mask ((u32)0xFFFFFF1F) + +/* --------- Cortex System Control register bit mask ---------------- */ +/* Cortex System Control register address */ +#define SCB_SysCtrl ((u32)0xE000ED10) +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : PWR_DeInit +* Description : Deinitializes the PWR peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/******************************************************************************* +* Function Name : PWR_BackupAccessCmd +* Description : Enables or disables access to the RTC and backup registers. +* Input : - NewState: new state of the access to the RTC and backup +* registers. This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_DBP_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_PVDCmd +* Description : Enables or disables the Power Voltage Detector(PVD). +* Input : - NewState: new state of the PVD. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_PVDE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_PVDLevelConfig +* Description : Configures the voltage threshold detected by the Power Voltage +* Detector(PVD). +* Input : - PWR_PVDLevel: specifies the PVD detection level +* This parameter can be one of the following values: +* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V +* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V +* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V +* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V +* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V +* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V +* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V +* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V +* Output : None +* Return : None +*******************************************************************************/ +void PWR_PVDLevelConfig(u32 PWR_PVDLevel) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/******************************************************************************* +* Function Name : PWR_WakeUpPinCmd +* Description : Enables or disables the WakeUp Pin functionality. +* Input : - NewState: new state of the WakeUp Pin functionality. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_EWUP_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_EnterSTOPMode +* Description : Enters STOP mode. +* Input : - PWR_Regulator: specifies the regulator state in STOP mode. +* This parameter can be one of the following values: +* - PWR_Regulator_ON: STOP mode with regulator ON +* - PWR_Regulator_LowPower: STOP mode with +* regulator in low power mode +* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or +* WFE instruction. +* This parameter can be one of the following values: +* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction +* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction +* Output : None +* Return : None +*******************************************************************************/ +void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/******************************************************************************* +* Function Name : PWR_EnterSTANDBYMode +* Description : Enters STANDBY mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Request Wait For Interrupt */ + __WFI(); +} + +/******************************************************************************* +* Function Name : PWR_GetFlagStatus +* Description : Checks whether the specified PWR flag is set or not. +* Input : - PWR_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - PWR_FLAG_WU: Wake Up flag +* - PWR_FLAG_SB: StandBy flag +* - PWR_FLAG_PVDO: PVD Output +* Output : None +* Return : The new state of PWR_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : PWR_ClearFlag +* Description : Clears the PWR's pending flags. +* Input : - PWR_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - PWR_FLAG_WU: Wake Up flag +* - PWR_FLAG_SB: StandBy flag +* Output : None +* Return : None +*******************************************************************************/ +void PWR_ClearFlag(u32 PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_rcc.c b/bsp/stm32/library/src/stm32f10x_rcc.c new file mode 100644 index 0000000000..ac5ea19c14 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_rcc.c @@ -0,0 +1,1105 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the RCC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) +#define USBPRE_BitNumber 0x16 +#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF) +#define CR_HSEBYP_Set ((u32)0x00040000) +#define CR_HSEON_Reset ((u32)0xFFFEFFFF) +#define CR_HSEON_Set ((u32)0x00010000) +#define CR_HSITRIM_Mask ((u32)0xFFFFFF07) + +/* CFGR register bit mask */ +#define CFGR_PLL_Mask ((u32)0xFFC0FFFF) +#define CFGR_PLLMull_Mask ((u32)0x003C0000) +#define CFGR_PLLSRC_Mask ((u32)0x00010000) +#define CFGR_PLLXTPRE_Mask ((u32)0x00020000) +#define CFGR_SWS_Mask ((u32)0x0000000C) +#define CFGR_SW_Mask ((u32)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((u32)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((u32)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((u32)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((u32)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((u8)0x1F) + +/* Typical Value of the HSI in Hz */ +#define HSI_Value ((u32)8000000) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((u32)0x40021009) +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((u32)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((u32)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +#ifndef HSEStartUp_TimeOut +/* Time out for HSE start up */ +#define HSEStartUp_TimeOut ((u16)0x0500) +#endif + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static uc8 ADCPrescTable[4] = {2, 4, 6, 8}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : RCC_DeInit +* Description : Resets the RCC clock configuration to the default reset state. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (u32)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */ + RCC->CFGR &= (u32)0xF8FF0000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (u32)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (u32)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ + RCC->CFGR &= (u32)0xFF80FFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/******************************************************************************* +* Function Name : RCC_HSEConfig +* Description : Configures the External High Speed oscillator (HSE). +* HSE can not be stopped if it is used directly or through the +* PLL as system clock. +* Input : - RCC_HSE: specifies the new state of the HSE. +* This parameter can be one of the following values: +* - RCC_HSE_OFF: HSE oscillator OFF +* - RCC_HSE_ON: HSE oscillator ON +* - RCC_HSE_Bypass: HSE oscillator bypassed with external +* clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HSEConfig(u32 RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : RCC_WaitForHSEStartUp +* Description : Waits for HSE start-up. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: HSE oscillator is stable and ready to use +* - ERROR: HSE oscillator not yet ready +*******************************************************************************/ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + vu32 StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut)); + + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + return (status); +} + +/******************************************************************************* +* Function Name : RCC_AdjustHSICalibrationValue +* Description : Adjusts the Internal High Speed oscillator (HSI) calibration +* value. +* Input : - HSICalibrationValue: specifies the calibration trimming value. +* This parameter must be a number between 0 and 0x1F. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (u32)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_HSICmd +* Description : Enables or disables the Internal High Speed oscillator (HSI). +* HSI can not be stopped if it is used directly or through the +* PLL as system clock. +* Input : - NewState: new state of the HSI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_HSION_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_PLLConfig +* Description : Configures the PLL clock source and multiplication factor. +* This function must be used only when the PLL is disabled. +* Input : - RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* - RCC_PLLMul: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[2,16] +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PLLCmd +* Description : Enables or disables the PLL. +* The PLL can not be disabled if it is used as system clock. +* Input : - NewState: new state of the PLL. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_PLLON_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_SYSCLKConfig +* Description : Configures the system clock (SYSCLK). +* Input : - RCC_SYSCLKSource: specifies the clock source used as system +* clock. This parameter can be one of the following values: +* - RCC_SYSCLKSource_HSI: HSI selected as system clock +* - RCC_SYSCLKSource_HSE: HSE selected as system clock +* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_GetSYSCLKSource +* Description : Returns the clock source used as system clock. +* Input : None +* Output : None +* Return : The clock source used as system clock. The returned value can +* be one of the following: +* - 0x00: HSI used as system clock +* - 0x04: HSE used as system clock +* - 0x08: PLL used as system clock +*******************************************************************************/ +u8 RCC_GetSYSCLKSource(void) +{ + return ((u8)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/******************************************************************************* +* Function Name : RCC_HCLKConfig +* Description : Configures the AHB clock (HCLK). +* Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is +* derived from the system clock (SYSCLK). +* This parameter can be one of the following values: +* - RCC_SYSCLK_Div1: AHB clock = SYSCLK +* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 +* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 +* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 +* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 +* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 +* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 +* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 +* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HCLKConfig(u32 RCC_SYSCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PCLK1Config +* Description : Configures the Low Speed APB clock (PCLK1). +* Input : - RCC_HCLK: defines the APB1 clock divider. This clock is +* derived from the AHB clock (HCLK). +* This parameter can be one of the following values: +* - RCC_HCLK_Div1: APB1 clock = HCLK +* - RCC_HCLK_Div2: APB1 clock = HCLK/2 +* - RCC_HCLK_Div4: APB1 clock = HCLK/4 +* - RCC_HCLK_Div8: APB1 clock = HCLK/8 +* - RCC_HCLK_Div16: APB1 clock = HCLK/16 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PCLK1Config(u32 RCC_HCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PCLK2Config +* Description : Configures the High Speed APB clock (PCLK2). +* Input : - RCC_HCLK: defines the APB2 clock divider. This clock is +* derived from the AHB clock (HCLK). +* This parameter can be one of the following values: +* - RCC_HCLK_Div1: APB2 clock = HCLK +* - RCC_HCLK_Div2: APB2 clock = HCLK/2 +* - RCC_HCLK_Div4: APB2 clock = HCLK/4 +* - RCC_HCLK_Div8: APB2 clock = HCLK/8 +* - RCC_HCLK_Div16: APB2 clock = HCLK/16 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PCLK2Config(u32 RCC_HCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_ITConfig +* Description : Enables or disables the specified RCC interrupts. +* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - NewState: new state of the specified RCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ + *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ + *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT; + } +} + +/******************************************************************************* +* Function Name : RCC_USBCLKConfig +* Description : Configures the USB clock (USBCLK). +* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock +* is derived from the PLL output. +* This parameter can be one of the following values: +* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 +* selected as USB clock source +* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB +* clock source +* Output : None +* Return : None +*******************************************************************************/ +void RCC_USBCLKConfig(u32 RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} + +/******************************************************************************* +* Function Name : RCC_ADCCLKConfig +* Description : Configures the ADC clock (ADCCLK). +* Input : - RCC_PCLK2: defines the ADC clock divider. This clock is +* derived from the APB2 clock (PCLK2). +* This parameter can be one of the following values: +* - RCC_PCLK2_Div2: ADC clock = PCLK2/2 +* - RCC_PCLK2_Div4: ADC clock = PCLK2/4 +* - RCC_PCLK2_Div6: ADC clock = PCLK2/6 +* - RCC_PCLK2_Div8: ADC clock = PCLK2/8 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ADCCLKConfig(u32 RCC_PCLK2) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + + tmpreg = RCC->CFGR; + + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_LSEConfig +* Description : Configures the External Low Speed oscillator (LSE). +* Input : - RCC_LSE: specifies the new state of the LSE. +* This parameter can be one of the following values: +* - RCC_LSE_OFF: LSE oscillator OFF +* - RCC_LSE_ON: LSE oscillator ON +* - RCC_LSE_Bypass: LSE oscillator bypassed with external +* clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_LSEConfig(u8 RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : RCC_LSICmd +* Description : Enables or disables the Internal Low Speed oscillator (LSI). +* LSI can not be disabled if the IWDG is running. +* Input : - NewState: new state of the LSI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_LSION_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_RTCCLKConfig +* Description : Configures the RTC clock (RTCCLK). +* Once the RTC clock is selected it can’t be changed unless the +* Backup domain is reset. +* Input : - RCC_RTCCLKSource: specifies the RTC clock source. +* This parameter can be one of the following values: +* - RCC_RTCCLKSource_LSE: LSE selected as RTC clock +* - RCC_RTCCLKSource_LSI: LSI selected as RTC clock +* - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 +* selected as RTC clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/******************************************************************************* +* Function Name : RCC_RTCCLKCmd +* Description : Enables or disables the RTC clock. +* This function must be used only after the RTC clock was +* selected using the RCC_RTCCLKConfig function. +* Input : - NewState: new state of the RTC clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) BDCR_RTCEN_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_GetClocksFreq +* Description : Returns the frequencies of different on chip clocks. +* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which +* will hold the clocks frequencies. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllmull = ( pllmull >> 18) + 2; + + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* HSE selected as PLL clock entry */ + + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET) + {/* HSE oscillator clock divided by 2 */ + + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; + } + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/******************************************************************************* +* Function Name : RCC_AHBPeriphClockCmd +* Description : Enables or disables the AHB peripheral clock. +* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. +* This parameter can be any combination of the following values: +* - RCC_AHBPeriph_DMA1 +* - RCC_AHBPeriph_DMA2 +* - RCC_AHBPeriph_SRAM +* - RCC_AHBPeriph_FLITF +* - RCC_AHBPeriph_CRC +* - RCC_AHBPeriph_FSMC +* - RCC_AHBPeriph_SDIO +* SRAM and FLITF clock can be disabled only during sleep mode. +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB2PeriphClockCmd +* Description : Enables or disables the High Speed APB (APB2) peripheral clock. +* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, +* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, +* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, +* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, +* RCC_APB2Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB1PeriphClockCmd +* Description : Enables or disables the Low Speed APB (APB1) peripheral clock. +* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, +* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, +* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, +* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP, +* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB2PeriphResetCmd +* Description : Forces or releases High Speed APB (APB2) peripheral reset. +* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset. +* This parameter can be any combination of the following values: +* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, +* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, +* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, +* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, +* RCC_APB2Periph_ALL +* - NewState: new state of the specified peripheral reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB1PeriphResetCmd +* Description : Forces or releases Low Speed APB (APB1) peripheral reset. +* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset. +* This parameter can be any combination of the following values: +* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, +* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, +* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, +* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP, +* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_BackupResetCmd +* Description : Forces or releases the Backup domain reset. +* Input : - NewState: new state of the Backup domain reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) BDCR_BDRST_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : - NewState: new state of the Clock Security System.. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_CSSON_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_MCOConfig +* Description : Selects the clock source to output on MCO pin. +* Input : - RCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* - RCC_MCO_NoClock: No clock selected +* - RCC_MCO_SYSCLK: System clock selected +* - RCC_MCO_HSI: HSI oscillator clock selected +* - RCC_MCO_HSE: HSE oscillator clock selected +* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected +* Output : None +* Return : None +*******************************************************************************/ +void RCC_MCOConfig(u8 RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO[2:0] bits to select the MCO source */ + *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/******************************************************************************* +* Function Name : RCC_GetFlagStatus +* Description : Checks whether the specified RCC flag is set or not. +* Input : - RCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - RCC_FLAG_HSIRDY: HSI oscillator clock ready +* - RCC_FLAG_HSERDY: HSE oscillator clock ready +* - RCC_FLAG_PLLRDY: PLL clock ready +* - RCC_FLAG_LSERDY: LSE oscillator clock ready +* - RCC_FLAG_LSIRDY: LSI oscillator clock ready +* - RCC_FLAG_PINRST: Pin reset +* - RCC_FLAG_PORRST: POR/PDR reset +* - RCC_FLAG_SFTRST: Software reset +* - RCC_FLAG_IWDGRST: Independent Watchdog reset +* - RCC_FLAG_WWDGRST: Window Watchdog reset +* - RCC_FLAG_LPWRRST: Low Power reset +* Output : None +* Return : The new state of RCC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG) +{ + u32 tmp = 0; + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((u32)1 << tmp)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : RCC_ClearFlag +* Description : Clears the RCC reset flags. +* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, +* RCC_FLAG_LPWRRST +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/******************************************************************************* +* Function Name : RCC_GetITStatus +* Description : Checks whether the specified RCC interrupt has occurred or not. +* Input : - RCC_IT: specifies the RCC interrupt source to check. +* This parameter can be one of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - RCC_IT_CSS: Clock Security System interrupt +* Output : None +* Return : The new state of RCC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RCC_GetITStatus(u8 RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : RCC_ClearITPendingBit +* Description : Clears the RCC’s interrupt pending bits. +* Input : - RCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - RCC_IT_CSS: Clock Security System interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClearITPendingBit(u8 RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_rtc.c b/bsp/stm32/library/src/stm32f10x_rtc.c new file mode 100644 index 0000000000..2284933ca6 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_rtc.c @@ -0,0 +1,320 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_rtc.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the RTC firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */ +#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */ +#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enables or disables the specified RTC interrupts. +* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* - NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (u16)~RTC_IT; + } +} + +/******************************************************************************* +* Function Name : RTC_EnterConfigMode +* Description : Enters the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= CRL_CNF_Set; +} + +/******************************************************************************* +* Function Name : RTC_ExitConfigMode +* Description : Exits from the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= CRL_CNF_Reset; +} + +/******************************************************************************* +* Function Name : RTC_GetCounter +* Description : Gets the RTC counter value. +* Input : None +* Output : None +* Return : RTC counter value. +*******************************************************************************/ +u32 RTC_GetCounter(void) +{ + u16 tmp = 0; + tmp = RTC->CNTL; + + return (((u32)RTC->CNTH << 16 ) | tmp) ; +} + +/******************************************************************************* +* Function Name : RTC_SetCounter +* Description : Sets the RTC counter value. +* Input : - CounterValue: RTC counter new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetCounter(u32 CounterValue) +{ + RTC_EnterConfigMode(); + + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetPrescaler +* Description : Sets the RTC prescaler value. +* Input : - PrescalerValue: RTC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetPrescaler(u32 PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the RTC alarm value. +* Input : - AlarmValue: RTC alarm new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(u32 AlarmValue) +{ + RTC_EnterConfigMode(); + + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetDivider +* Description : Gets the RTC divider value. +* Input : None +* Output : None +* Return : RTC Divider value. +*******************************************************************************/ +u32 RTC_GetDivider(void) +{ + u32 tmp = 0x00; + + tmp = ((u32)RTC->DIVH & (u32)0x000F) << 16; + tmp |= RTC->DIVL; + + return tmp; +} + +/******************************************************************************* +* Function Name : RTC_WaitForLastTask +* Description : Waits until last write operation on RTC registers has finished. +* This function must be called before any write to RTC registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET) + { + } +} + +/******************************************************************************* +* Function Name : RTC_WaitForSynchro +* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* This function must be called before any read operation after +* an APB reset or an APB clock stop. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (u16)~RTC_FLAG_RSF; + + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET) + { + } +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Checks whether the specified RTC flag is set or not. +* Input : - RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* - RTC_FLAG_RTOFF: RTC Operation OFF flag +* - RTC_FLAG_RSF: Registers Synchronized flag +* - RTC_FLAG_OW: Overflow flag +* - RTC_FLAG_ALR: Alarm flag +* - RTC_FLAG_SEC: Second flag +* Output : None +* Return : The new state of RTC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears the RTC’s pending flags. +* Input : - RTC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - RTC_FLAG_RSF: Registers Synchronized flag. This flag +* is cleared only after an APB reset or an APB Clock stop. +* - RTC_FLAG_OW: Overflow flag +* - RTC_FLAG_ALR: Alarm flag +* - RTC_FLAG_SEC: Second flag +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearFlag(u16 RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (u16)~RTC_FLAG; +} + +/******************************************************************************* +* Function Name : RTC_GetITStatus +* Description : Checks whether the specified RTC interrupt has occured or not. +* Input : - RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be one of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* Output : None +* Return : The new state of the RTC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RTC_GetITStatus(u16 RTC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + + if (((RTC->CRH & RTC_IT) != (u16)RESET) && (bitstatus != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : RTC_ClearITPendingBit +* Description : Clears the RTC’s interrupt pending bits. +* Input : - RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearITPendingBit(u16 RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (u16)~RTC_IT; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_sdio.c b/bsp/stm32/library/src/stm32f10x_sdio.c new file mode 100644 index 0000000000..42d4e05f91 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_sdio.c @@ -0,0 +1,832 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_sdio.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the SDIO firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + + +/* ---------------------- SDIO registers bit mask ------------------------ */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((u32)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((u32)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((u32)0xFFFFFF08) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((u32)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((u32)(SDIO_BASE + 0x14)) + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SDIO_DeInit +* Description : Deinitializes the SDIO peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/******************************************************************************* +* Function Name : SDIO_Init +* Description : Initializes the SDIO peripheral according to the specified +* parameters in the SDIO_InitStruct. +* Input : SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure +* that contains the configuration information for the SDIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/******************************************************************************* +* Function Name : SDIO_StructInit +* Description : Fills each SDIO_InitStruct member with its default value. +* Input : SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/******************************************************************************* +* Function Name : SDIO_ClockCmd +* Description : Enables or disables the SDIO Clock. +* Input : NewState: new state of the SDIO Clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CLKCR_CLKEN_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : SDIO_SetPowerState +* Description : Sets the power status of the controller. +* Input : SDIO_PowerState: new state of the Power state. +* This parameter can be one of the following values: +* - SDIO_PowerState_OFF +* - SDIO_PowerState_ON +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_SetPowerState(u32 SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/******************************************************************************* +* Function Name : SDIO_GetPowerState +* Description : Gets the power status of the controller. +* Input : None +* Output : None +* Return : Power status of the controller. The returned value can +* be one of the following: +* - 0x00: Power OFF +* - 0x02: Power UP +* - 0x03: Power ON +*******************************************************************************/ +u32 SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/******************************************************************************* +* Function Name : SDIO_ITConfig +* Description : Enables or disables the SDIO interrupts. +* Input : - SDIO_IT: specifies the SDIO interrupt sources to be +* enabled or disabled. +* This parameter can be one or a combination of the following +* values: +* - SDIO_IT_CCRCFAIL: Command response received (CRC check +* failed) interrupt +* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check +* failed) interrupt +* - SDIO_IT_CTIMEOUT: Command response timeout interrupt +* - SDIO_IT_DTIMEOUT: Data timeout interrupt +* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt +* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt +* - SDIO_IT_CMDREND: Command response received (CRC check +* passed) interrupt +* - SDIO_IT_CMDSENT: Command sent (no response required) +* interrupt +* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is +* zero) interrupt +* - SDIO_IT_STBITERR: Start bit not detected on all data +* signals in wide bus mode interrupt +* - SDIO_IT_DBCKEND: Data block sent/received (CRC check +* passed) interrupt +* - SDIO_IT_CMDACT: Command transfer in progress interrupt +* - SDIO_IT_TXACT: Data transmit in progress interrupt +* - SDIO_IT_RXACT: Data receive in progress interrupt +* - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt +* - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt +* - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt +* - SDIO_IT_RXFIFOF: Receive FIFO full interrupt +* - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt +* - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt +* - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt +* - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt +* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt +* - SDIO_IT_CEATAEND: CE-ATA command completion signal +* received for CMD61 interrupt +* - NewState: new state of the specified SDIO interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/******************************************************************************* +* Function Name : SDIO_DMACmd +* Description : Enables or disables the SDIO DMA request. +* Input : NewState: new state of the selected SDIO DMA request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) DCTRL_DMAEN_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : SDIO_SendCommand +* Description : Initializes the SDIO Command according to the specified +* parameters in the SDIO_CmdInitStruct and send the command. +* Input : SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef +* structure that contains the configuration information +* for the SDIO command. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (u32)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/******************************************************************************* +* Function Name : SDIO_CmdStructInit +* Description : Fills each SDIO_CmdInitStruct member with its default value. +* Input : SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/******************************************************************************* +* Function Name : SDIO_GetCommandResponse +* Description : Returns command index of last command for which response +* received. +* Input : None +* Output : None +* Return : Returns the command index of the last command response received. +*******************************************************************************/ +u8 SDIO_GetCommandResponse(void) +{ + return (u8)(SDIO->RESPCMD); +} + +/******************************************************************************* +* Function Name : SDIO_GetResponse +* Description : Returns response received from the card for the last command. +* Input : - SDIO_RESP: Specifies the SDIO response register. +* This parameter can be one of the following values: +* - SDIO_RESP1: Response Register 1 +* - SDIO_RESP2: Response Register 2 +* - SDIO_RESP3: Response Register 3 +* - SDIO_RESP4: Response Register 4 +* Output : None +* Return : The Corresponding response register value. +*******************************************************************************/ +u32 SDIO_GetResponse(u32 SDIO_RESP) +{ + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + return (*(vu32 *)(SDIO_RESP_ADDR + SDIO_RESP)); +} + +/******************************************************************************* +* Function Name : SDIO_DataConfig +* Description : Initializes the SDIO data path according to the specified +* parameters in the SDIO_DataInitStruct. +* Input : SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef +* structure that contains the configuration information +* for the SDIO command. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/******************************************************************************* +* Function Name : SDIO_DataStructInit +* Description : Fills each SDIO_DataInitStruct member with its default value. +* Input : SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/******************************************************************************* +* Function Name : SDIO_GetDataCounter +* Description : Returns number of remaining data bytes to be transferred. +* Input : None +* Output : None +* Return : Number of remaining data bytes to be transferred +*******************************************************************************/ +u32 SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/******************************************************************************* +* Function Name : SDIO_ReadData +* Description : Read one data word from Rx FIFO. +* Input : None +* Output : None +* Return : Data received +*******************************************************************************/ +u32 SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/******************************************************************************* +* Function Name : SDIO_WriteData +* Description : Write one data word to Tx FIFO. +* Input : Data: 32-bit data word to write. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_WriteData(u32 Data) +{ + SDIO->FIFO = Data; +} + +/******************************************************************************* +* Function Name : SDIO_GetFIFOCount +* Description : Returns the number of words left to be written to or read +* from FIFO. +* Input : None +* Output : None +* Return : Remaining number of words. +*******************************************************************************/ +u32 SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/******************************************************************************* +* Function Name : SDIO_StartSDIOReadWait +* Description : Starts the SD I/O Read Wait operation. +* Input : NewState: new state of the Start SDIO Read Wait operation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) DCTRL_RWSTART_BB = (u32) NewState; +} + +/******************************************************************************* +* Function Name : SDIO_StopSDIOReadWait +* Description : Stops the SD I/O Read Wait operation. +* Input : NewState: new state of the Stop SDIO Read Wait operation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) DCTRL_RWSTOP_BB = (u32) NewState; +} + +/******************************************************************************* +* Function Name : SDIO_SetSDIOReadWaitMode +* Description : Sets one of the two options of inserting read wait interval. +* Input : SDIOReadWaitMode: SD I/O Read Wait operation mode. +* This parametre can be: +* - SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK +* - SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(vu32 *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/******************************************************************************* +* Function Name : SDIO_SetSDIOOperation +* Description : Enables or disables the SD I/O Mode Operation. +* Input : NewState: new state of SDIO specific operation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) DCTRL_SDIOEN_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : SDIO_SendSDIOSuspendCmd +* Description : Enables or disables the SD I/O Mode suspend command sending. +* Input : NewState: new state of the SD I/O Mode suspend command. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CMD_SDIOSUSPEND_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : SDIO_CommandCompletionCmd +* Description : Enables or disables the command completion signal. +* Input : NewState: new state of command completion signal. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CMD_ENCMDCOMPL_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : SDIO_CEATAITCmd +* Description : Enables or disables the CE-ATA interrupt. +* Input : NewState: new state of CE-ATA interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CMD_NIEN_BB = (u32)((~((u32)NewState)) & ((u32)0x1)); +} + +/******************************************************************************* +* Function Name : SDIO_SendCEATACmd +* Description : Sends CE-ATA command (CMD61). +* Input : NewState: new state of CE-ATA command. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CMD_ATACMD_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : SDIO_GetFlagStatus +* Description : Checks whether the specified SDIO flag is set or not. +* Input : SDIO_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SDIO_FLAG_CCRCFAIL: Command response received (CRC check +* failed) +* - SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check +* failed) +* - SDIO_FLAG_CTIMEOUT: Command response timeout +* - SDIO_FLAG_DTIMEOUT: Data timeou +* - SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error +* - SDIO_FLAG_RXOVERR: Received FIFO overrun error +* - SDIO_FLAG_CMDREND: Command response received (CRC check +* passed) +* - SDIO_FLAG_CMDSENT: Command sent (no response required) +* - SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is +* zero) +* - SDIO_FLAG_STBITERR: Start bit not detected on all data +* signals in wide bus mode +* - SDIO_FLAG_DBCKEND: Data block sent/received (CRC check +* passed) +* - SDIO_FLAG_CMDACT: Command transfer in progress +* - SDIO_FLAG_TXACT: Data transmit in progress +* - SDIO_FLAG_RXACT: Data receive in progress +* - SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty +* - SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full +* - SDIO_FLAG_TXFIFOF: Transmit FIFO full +* - SDIO_FLAG_RXFIFOF: Receive FIFO full +* - SDIO_FLAG_TXFIFOE: Transmit FIFO empty +* - SDIO_FLAG_RXFIFOE: Receive FIFO empty +* - SDIO_FLAG_TXDAVL: Data available in transmit FIFO +* - SDIO_FLAG_RXDAVL: Data available in receive FIFO +* - SDIO_FLAG_SDIOIT: SD I/O interrupt received +* - SDIO_FLAG_CEATAEND: CE-ATA command completion signal +* received for CMD61 +* Output : None +* Return : The new state of SDIO_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : SDIO_ClearFlag +* Description : Clears the SDIO's pending flags. +* Input : SDIO_FLAG: specifies the flag to clear. +* This parameter can be one or a combination of the following +* values: +* - SDIO_FLAG_CCRCFAIL: Command response received (CRC check +* failed) +* - SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check +* failed) +* - SDIO_FLAG_CTIMEOUT: Command response timeout +* - SDIO_FLAG_DTIMEOUT: Data timeou +* - SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error +* - SDIO_FLAG_RXOVERR: Received FIFO overrun error +* - SDIO_FLAG_CMDREND: Command response received (CRC check +* passed) +* - SDIO_FLAG_CMDSENT: Command sent (no response required) +* - SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is +* zero) +* - SDIO_FLAG_STBITERR: Start bit not detected on all data +* signals in wide bus mode +* - SDIO_FLAG_DBCKEND: Data block sent/received (CRC check +* passed) +* - SDIO_FLAG_SDIOIT: SD I/O interrupt received +* - SDIO_FLAG_CEATAEND: CE-ATA command completion signal +* received for CMD61 +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_ClearFlag(u32 SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/******************************************************************************* +* Function Name : SDIO_GetITStatus +* Description : Checks whether the specified SDIO interrupt has occurred or not. +* Input : SDIO_IT: specifies the SDIO interrupt source to check. +* This parameter can be one of the following values: +* - SDIO_IT_CCRCFAIL: Command response received (CRC check +* failed) interrupt +* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check +* failed) interrupt +* - SDIO_IT_CTIMEOUT: Command response timeout interrupt +* - SDIO_IT_DTIMEOUT: Data timeout interrupt +* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt +* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt +* - SDIO_IT_CMDREND: Command response received (CRC check +* passed) interrupt +* - SDIO_IT_CMDSENT: Command sent (no response required) +* interrupt +* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is +* zero) interrupt +* - SDIO_IT_STBITERR: Start bit not detected on all data +* signals in wide bus mode interrupt +* - SDIO_IT_DBCKEND: Data block sent/received (CRC check +* passed) interrupt +* - SDIO_IT_CMDACT: Command transfer in progress interrupt +* - SDIO_IT_TXACT: Data transmit in progress interrupt +* - SDIO_IT_RXACT: Data receive in progress interrupt +* - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt +* - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt +* - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt +* - SDIO_IT_RXFIFOF: Receive FIFO full interrupt +* - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt +* - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt +* - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt +* - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt +* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt +* - SDIO_IT_CEATAEND: CE-ATA command completion signal +* received for CMD61 interrupt +* Output : None +* Return : The new state of SDIO_IT (SET or RESET). +*******************************************************************************/ +ITStatus SDIO_GetITStatus(u32 SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + + if ((SDIO->STA & SDIO_IT) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : SDIO_ClearITPendingBit +* Description : Clears the SDIO’s interrupt pending bits. +* Input : SDIO_IT: specifies the interrupt pending bit to clear. +* This parameter can be one or a combination of the following +* values: +* - SDIO_IT_CCRCFAIL: Command response received (CRC check +* failed) interrupt +* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check +* failed) interrupt +* - SDIO_IT_CTIMEOUT: Command response timeout interrupt +* - SDIO_IT_DTIMEOUT: Data timeout interrupt +* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt +* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt +* - SDIO_IT_CMDREND: Command response received (CRC check +* passed) interrupt +* - SDIO_IT_CMDSENT: Command sent (no response required) +* interrupt +* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is +* zero) interrupt +* - SDIO_IT_STBITERR: Start bit not detected on all data +* signals in wide bus mode interrupt +* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt +* - SDIO_IT_CEATAEND: CE-ATA command completion signal +* received for CMD61 +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_ClearITPendingBit(u32 SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_spi.c b/bsp/stm32/library/src/stm32f10x_spi.c new file mode 100644 index 0000000000..0ca5175c4c --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_spi.c @@ -0,0 +1,863 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_spi.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the SPI firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SPI SPE mask */ +#define CR1_SPE_Set ((u16)0x0040) +#define CR1_SPE_Reset ((u16)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((u16)0x0400) +#define I2SCFGR_I2SE_Reset ((u16)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((u16)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((u16)0x2000) +#define CR1_CRCEN_Reset ((u16)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((u16)0x0004) +#define CR2_SSOE_Reset ((u16)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((u16)0x3040) +#define I2SCFGR_CLEAR_Mask ((u16)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((u16)0xF7FF) +#define I2S_Mode_Select ((u16)0x0800) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SPI_I2S_DeInit +* Description : Deinitializes the SPIx peripheral registers to their default +* reset values (Affects also the I2Ss). +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + switch (*(u32*)&SPIx) + { + case SPI1_BASE: + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + break; + + case SPI2_BASE: + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + break; + + case SPI3_BASE: + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : SPI_Init +* Description : Initializes the SPIx peripheral according to the specified +* parameters in the SPI_InitStruct. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that +* contains the configuration information for the specified +* SPI peripheral. +* Output : None +* Return : None +******************************************************************************/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + u16 tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/******************************************************************************* +* Function Name : I2S_Init +* Description : Initializes the SPIx peripheral according to the specified +* parameters in the I2S_InitStruct. +* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral +* (configured in I2S mode). +* - I2S_InitStruct: pointer to an I2S_InitTypeDef structure that +* contains the configuration information for the specified +* SPI peripheral configured in I2S mode. +* Output : None +* Return : None +******************************************************************************/ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + u32 tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (u16)0; + i2sdiv = (u16)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + /* Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flaoting point */ + tmp = tmp/10; + + /* Check the parity of the divider */ + i2sodd = (u16)(tmp & (u16)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (u16)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (u16) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (u16)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \ + I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \ + I2S_InitStruct->I2S_CPOL); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : SPI_StructInit +* Description : Fills each SPI_InitStruct member with its default value. +* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/******************************************************************************* +* Function Name : I2S_StructInit +* Description : Fills each I2S_InitStruct member with its default value. +* Input : - I2S_InitStruct : pointer to a I2S_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/******************************************************************************* +* Function Name : SPI_Cmd +* Description : Enables or disables the specified SPI peripheral. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - NewState: new state of the SPIx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2S_Cmd +* Description : Enables or disables the specified SPI peripheral (in I2S mode). +* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral. +* - NewState: new state of the SPIx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_I2S_ITConfig +* Description : Enables or disables the specified SPI/I2S interrupts. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - 2 or 3 in I2S mode +* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to be +* enabled or disabled. +* This parameter can be one of the following values: +* - SPI_I2S_IT_TXE: Tx buffer empty interrupt mask +* - SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask +* - SPI_I2S_IT_ERR: Error interrupt mask +* - NewState: new state of the specified SPI/I2S interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState) +{ + u16 itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + /* Set the IT mask */ + itmask = (u16)((u16)1 << itpos); + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (u16)~itmask; + } +} + +/******************************************************************************* +* Function Name : SPI_I2S_DMACmd +* Description : Enables or disables the SPIx/I2Sx DMA interface. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - 2 or 3 in I2S mode +* - SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request +* to be enabled or disabled. +* This parameter can be any combination of the following values: +* - SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request +* - SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request +* - NewState: new state of the selected SPI/I2S DMA transfer +* request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (u16)~SPI_I2S_DMAReq; + } +} + +/******************************************************************************* +* Function Name : SPI_I2S_SendData +* Description : Transmits a Data through the SPIx/I2Sx peripheral. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - 2 or 3 in I2S mode +* - Data : Data to be transmitted.. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/******************************************************************************* +* Function Name : SPI_I2S_ReceiveData +* Description : Returns the most recent received data by the SPIx/I2Sx peripheral. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - 2 or 3 in I2S mode +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/******************************************************************************* +* Function Name : SPI_NSSInternalSoftwareConfig +* Description : Configures internally by software the NSS pin for the selected +* SPI. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - SPI_NSSInternalSoft: specifies the SPI NSS internal state. +* This parameter can be one of the following values: +* - SPI_NSSInternalSoft_Set: Set NSS pin internally +* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally +* Output : None +* Return : None +*******************************************************************************/ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_SSOutputCmd +* Description : Enables or disables the SS output for the selected SPI. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - NewState: new state of the SPIx SS output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_DataSizeConfig +* Description : Configures the data size for the selected SPI. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - SPI_DataSize: specifies the SPI data size. +* This parameter can be one of the following values: +* - SPI_DataSize_16b: Set data frame format to 16bit +* - SPI_DataSize_8b: Set data frame format to 8bit +* Output : None +* Return : None +*******************************************************************************/ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + + /* Clear DFF bit */ + SPIx->CR1 &= (u16)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/******************************************************************************* +* Function Name : SPI_TransmitCRC +* Description : Transmit the SPIx CRC value. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/******************************************************************************* +* Function Name : SPI_CalculateCRC +* Description : Enables or disables the CRC value calculation of the +* transfered bytes. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - NewState: new state of the SPIx CRC value calculation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_GetCRC +* Description : Returns the transmit or the receive CRC register value for +* the specified SPI. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - SPI_CRC: specifies the CRC register to be read. +* This parameter can be one of the following values: +* - SPI_CRC_Tx: Selects Tx CRC register +* - SPI_CRC_Rx: Selects Rx CRC register +* Output : None +* Return : The selected CRC register value.. +*******************************************************************************/ +u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC) +{ + u16 crcreg = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + + /* Return the selected CRC register */ + return crcreg; +} + +/******************************************************************************* +* Function Name : SPI_GetCRCPolynomial +* Description : Returns the CRC Polynomial register value for the specified SPI. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* Output : None +* Return : The CRC Polynomial register value. +*******************************************************************************/ +u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/******************************************************************************* +* Function Name : SPI_BiDirectionalLineConfig +* Description : Selects the data transfer direction in bi-directional mode +* for the specified SPI. +* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. +* - SPI_Direction: specifies the data transfer direction in +* bi-directional mode. +* This parameter can be one of the following values: +* - SPI_Direction_Tx: Selects Tx transmission direction +* - SPI_Direction_Rx: Selects Rx receive direction +* Output : None +* Return : None +*******************************************************************************/ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/******************************************************************************* +* Function Name : SPI_I2S_GetFlagStatus +* Description : Checks whether the specified SPI/I2S flag is set or not. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - 2 or 3 in I2S mode +* - SPI_I2S_FLAG: specifies the SPI/I2S flag to check. +* This parameter can be one of the following values: +* - SPI_I2S_FLAG_TXE: Transmit buffer empty flag. +* - SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. +* - SPI_I2S_FLAG_BSY: Busy flag. +* - SPI_I2S_FLAG_OVR: Overrun flag. +* - SPI_FLAG_MODF: Mode Fault flag. +* - SPI_FLAG_CRCERR: CRC Error flag. +* - I2S_FLAG_UDR: Underrun Error flag. +* - I2S_FLAG_CHSIDE: Channel Side flag. +* Output : None +* Return : The new state of SPI_I2S_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (u16)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : SPI_I2S_ClearFlag +* Description : Clears the SPIx CRC Error (CRCERR) flag. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - SPI_I2S_FLAG: specifies the SPI flag to clear. +* This function clears only CRCERR flag. +* Notes: +* - OVR (OverRun error) flag is cleared by software +* sequence: a read operation to SPI_DR register +* (SPI_I2S_ReceiveData()) followed by a read operation +* to SPI_SR register (SPI_I2S_GetFlagStatus()). +* - UDR (UnderRun error) flag is cleared by a read +* operation to SPI_SR register (SPI_I2S_GetFlagStatus()). +* - MODF (Mode Fault) flag is cleared by software sequence: +* a read/write operation to SPI_SR register +* (SPI_I2S_GetFlagStatus()) followed by a write +* operation to SPI_CR1 register (SPI_Cmd() to enable +* the SPI). +* Output : None +* Return : None +*******************************************************************************/ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (u16)~SPI_I2S_FLAG; +} + +/******************************************************************************* +* Function Name : SPI_I2S_GetITStatus +* Description : Checks whether the specified SPI/I2S interrupt has occurred or not. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - 2 or 3 in I2S mode +* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. +* This parameter can be one of the following values: +* - SPI_I2S_IT_TXE: Transmit buffer empty interrupt. +* - SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. +* - SPI_I2S_IT_OVR: Overrun interrupt. +* - SPI_IT_MODF: Mode Fault interrupt. +* - SPI_IT_CRCERR: CRC Error interrupt. +* - I2S_IT_UDR: Underrun Error interrupt. +* Output : None +* Return : The new state of SPI_I2S_IT (SET or RESET). +*******************************************************************************/ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + u16 itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F)); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + /* Set the IT mask */ + itmask = (u16)((u16)0x01 << itmask); + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : SPI_I2S_ClearITPendingBit +* Description : Clears the SPIx CRC Error (CRCERR) interrupt pending bit. +* Input : - SPIx: where x can be : +* - 1, 2 or 3 in SPI mode +* - SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. +* This function clears only CRCERR intetrrupt pending bit. +* Notes: +* - OVR (OverRun Error) interrupt pending bit is cleared +* by software sequence: a read operation to SPI_DR +* register (SPI_I2S_ReceiveData()) followed by a read +* operation to SPI_SR register (SPI_I2S_GetITStatus()). +* - UDR (UnderRun Error) interrupt pending bit is cleared +* by a read operation to SPI_SR register +* (SPI_I2S_GetITStatus()). +* - MODF (Mode Fault) interrupt pending bit is cleared by +* software sequence: a read/write operation to SPI_SR +* register (SPI_I2S_GetITStatus()) followed by a write +* operation to SPI_CR1 register (SPI_Cmd() to enable the +* SPI). +* Output : None +* Return : None +*******************************************************************************/ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT) +{ + u16 itpos = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F)); + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (u16)~itpos; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_systick.c b/bsp/stm32/library/src/stm32f10x_systick.c new file mode 100644 index 0000000000..e3b67df4d1 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_systick.c @@ -0,0 +1,181 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_systick.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the SysTick firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_systick.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- SysTick registers bit mask -------------------- */ +/* CTRL TICKINT Mask */ +#define CTRL_TICKINT_Set ((u32)0x00000002) +#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SysTick_CLKSourceConfig +* Description : Configures the SysTick clock source. +* Input : - SysTick_CLKSource: specifies the SysTick clock source. +* This parameter can be one of the following values: +* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 +* selected as SysTick clock source. +* - SysTick_CLKSource_HCLK: AHB clock selected as +* SysTick clock source. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/******************************************************************************* +* Function Name : SysTick_SetReload +* Description : Sets SysTick Reload value. +* Input : - Reload: SysTick Reload new value. +* This parameter must be a number between 1 and 0xFFFFFF. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_SetReload(u32 Reload) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_RELOAD(Reload)); + + SysTick->LOAD = Reload; +} + +/******************************************************************************* +* Function Name : SysTick_CounterCmd +* Description : Enables or disables the SysTick counter. +* Input : - SysTick_Counter: new state of the SysTick counter. +* This parameter can be one of the following values: +* - SysTick_Counter_Disable: Disable counter +* - SysTick_Counter_Enable: Enable counter +* - SysTick_Counter_Clear: Clear counter value to 0 +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SysTick_Counter_Enable) + { + SysTick->CTRL |= SysTick_Counter_Enable; + } + else if (SysTick_Counter == SysTick_Counter_Disable) + { + SysTick->CTRL &= SysTick_Counter_Disable; + } + else /* SysTick_Counter == SysTick_Counter_Clear */ + { + SysTick->VAL = SysTick_Counter_Clear; + } +} + +/******************************************************************************* +* Function Name : SysTick_ITConfig +* Description : Enables or disables the SysTick Interrupt. +* Input : - NewState: new state of the SysTick Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_Set; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_Reset; + } +} + +/******************************************************************************* +* Function Name : SysTick_GetCounter +* Description : Gets SysTick counter value. +* Input : None +* Output : None +* Return : SysTick current value +*******************************************************************************/ +u32 SysTick_GetCounter(void) +{ + return(SysTick->VAL); +} + +/******************************************************************************* +* Function Name : SysTick_GetFlagStatus +* Description : Checks whether the specified SysTick flag is set or not. +* Input : - SysTick_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SysTick_FLAG_COUNT +* - SysTick_FLAG_SKEW +* - SysTick_FLAG_NOREF +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG) +{ + u32 statusreg = 0, tmp = 0 ; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SYSTICK_FLAG(SysTick_FLAG)); + + /* Get the SysTick register index */ + tmp = SysTick_FLAG >> 3; + + if (tmp == 2) /* The flag to check is in CTRL register */ + { + statusreg = SysTick->CTRL; + } + else /* The flag to check is in CALIB register */ + { + statusreg = SysTick->CALIB; + } + + if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_tim.c b/bsp/stm32/library/src/stm32f10x_tim.c new file mode 100644 index 0000000000..cf27eaa061 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_tim.c @@ -0,0 +1,3219 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : stm32f10x_tim.c +* Author : MCD Application Team +* Version : V2.0.3Patch1 +* Date : 04/06/2009 +* Description : This file provides all the TIM firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- TIM registers bit mask ------------------------ */ +#define CR1_CEN_Set ((u16)0x0001) +#define CR1_CEN_Reset ((u16)0x03FE) +#define CR1_UDIS_Set ((u16)0x0002) +#define CR1_UDIS_Reset ((u16)0x03FD) +#define CR1_URS_Set ((u16)0x0004) +#define CR1_URS_Reset ((u16)0x03FB) +#define CR1_OPM_Reset ((u16)0x03F7) +#define CR1_CounterMode_Mask ((u16)0x038F) +#define CR1_ARPE_Set ((u16)0x0080) +#define CR1_ARPE_Reset ((u16)0x037F) +#define CR1_CKD_Mask ((u16)0x00FF) + +#define CR2_CCPC_Set ((u16)0x0001) +#define CR2_CCPC_Reset ((u16)0xFFFE) +#define CR2_CCUS_Set ((u16)0x0004) +#define CR2_CCUS_Reset ((u16)0xFFFB) +#define CR2_CCDS_Set ((u16)0x0008) +#define CR2_CCDS_Reset ((u16)0xFFF7) +#define CR2_MMS_Mask ((u16)0xFF8F) +#define CR2_TI1S_Set ((u16)0x0080) +#define CR2_TI1S_Reset ((u16)0xFF7F) +#define CR2_OIS1_Reset ((u16)0x7EFF) +#define CR2_OIS1N_Reset ((u16)0x7DFF) +#define CR2_OIS2_Reset ((u16)0x7BFF) +#define CR2_OIS2N_Reset ((u16)0x77FF) +#define CR2_OIS3_Reset ((u16)0x6FFF) +#define CR2_OIS3N_Reset ((u16)0x5FFF) +#define CR2_OIS4_Reset ((u16)0x3FFF) + +#define SMCR_SMS_Mask ((u16)0xFFF8) +#define SMCR_ETR_Mask ((u16)0x00FF) +#define SMCR_TS_Mask ((u16)0xFF8F) +#define SMCR_MSM_Reset ((u16)0xFF7F) +#define SMCR_ECE_Set ((u16)0x4000) + +#define CCMR_CC13S_Mask ((u16)0xFFFC) +#define CCMR_CC24S_Mask ((u16)0xFCFF) +#define CCMR_TI13Direct_Set ((u16)0x0001) +#define CCMR_TI24Direct_Set ((u16)0x0100) +#define CCMR_OC13FE_Reset ((u16)0xFFFB) +#define CCMR_OC24FE_Reset ((u16)0xFBFF) +#define CCMR_OC13PE_Reset ((u16)0xFFF7) +#define CCMR_OC24PE_Reset ((u16)0xF7FF) +#define CCMR_OC13M_Mask ((u16)0xFF8F) +#define CCMR_OC24M_Mask ((u16)0x8FFF) + +#define CCMR_OC13CE_Reset ((u16)0xFF7F) +#define CCMR_OC24CE_Reset ((u16)0x7FFF) + +#define CCMR_IC13PSC_Mask ((u16)0xFFF3) +#define CCMR_IC24PSC_Mask ((u16)0xF3FF) +#define CCMR_IC13F_Mask ((u16)0xFF0F) +#define CCMR_IC24F_Mask ((u16)0x0FFF) + +#define CCMR_Offset ((u16)0x0018) +#define CCER_CCE_Set ((u16)0x0001) +#define CCER_CCNE_Set ((u16)0x0004) + +#define CCER_CC1P_Reset ((u16)0xFFFD) +#define CCER_CC2P_Reset ((u16)0xFFDF) +#define CCER_CC3P_Reset ((u16)0xFDFF) +#define CCER_CC4P_Reset ((u16)0xDFFF) + +#define CCER_CC1NP_Reset ((u16)0xFFF7) +#define CCER_CC2NP_Reset ((u16)0xFF7F) +#define CCER_CC3NP_Reset ((u16)0xF7FF) + +#define CCER_CC1E_Set ((u16)0x0001) +#define CCER_CC1E_Reset ((u16)0xFFFE) + +#define CCER_CC1NE_Reset ((u16)0xFFFB) + +#define CCER_CC2E_Set ((u16)0x0010) +#define CCER_CC2E_Reset ((u16)0xFFEF) + +#define CCER_CC2NE_Reset ((u16)0xFFBF) + +#define CCER_CC3E_Set ((u16)0x0100) +#define CCER_CC3E_Reset ((u16)0xFEFF) + +#define CCER_CC3NE_Reset ((u16)0xFBFF) + +#define CCER_CC4E_Set ((u16)0x1000) +#define CCER_CC4E_Reset ((u16)0xEFFF) + +#define BDTR_MOE_Set ((u16)0x8000) +#define BDTR_MOE_Reset ((u16)0x7FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter); +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Deinitializes the TIMx peripheral registers to their default +* reset values. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + switch (*(u32*)&TIMx) + { + case TIM1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + break; + + case TIM2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + break; + + case TIM3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + break; + + case TIM4_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + break; + + case TIM5_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + break; + + case TIM6_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + break; + + case TIM7_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + break; + + case TIM8_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseInit +* Description : Initializes the TIMx Time Base Unit peripheral according to +* the specified parameters in the TIM_TimeBaseInitStruct. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + /* Select the Counter Mode and set the clock division */ + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler value immediatly */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/******************************************************************************* +* Function Name : TIM_OC1Init +* Description : Initializes the TIMx Channel1 according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= CCER_CC1E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC13M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC1P_Reset; + + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC1NP_Reset; + + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= CCER_CC1NE_Reset; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS1_Reset; + tmpcr2 &= CR2_OIS1N_Reset; + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC2Init +* Description : Initializes the TIMx Channel2 according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC2E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC24M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC2P_Reset; + + /* Set the Output Compare Polarity */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4); + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC2NP_Reset; + + /* Set the Output N Polarity */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= CCER_CC2NE_Reset; + + /* Set the Output N State */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS2_Reset; + tmpcr2 &= CR2_OIS2N_Reset; + + /* Set the Output Idle state */ + tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2); + + /* Set the Output N Idle state */ + tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC3Init +* Description : Initializes the TIMx Channel3 according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC3E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC13M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC3P_Reset; + + /* Set the Output Compare Polarity */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8); + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC3NP_Reset; + + /* Set the Output N Polarity */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + + /* Reset the Output N State */ + tmpccer &= CCER_CC3NE_Reset; + + /* Set the Output N State */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS3_Reset; + tmpcr2 &= CR2_OIS3N_Reset; + + /* Set the Output Idle state */ + tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4); + + /* Set the Output N Idle state */ + tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC4Init +* Description : Initializes the TIMx Channel4 according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= CCER_CC4E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC24M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC4P_Reset; + + /* Set the Output Compare Polarity */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 12); + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= CR2_OIS4_Reset; + + /* Set the Output Idle state */ + tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_ICInit +* Description : Initializes the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TIM_PWMIConfig +* Description : Configures the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct to measure an external PWM +* signal. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + u16 icoppositepolarity = TIM_ICPolarity_Rising; + u16 icoppositeselection = TIM_ICSelection_DirectTI; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TIM_BDTRConfig +* Description : Configures the: Break feature, dead time, Lock level, the OSSI, +* the OSSR State and the AOE(automatic output enable). +* Input :- TIMx: where x can be 1 or 8 to select the TIM +* - TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef +* structure that contains the BDTR Register configuration +* information for the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + TIMx->BDTR = (u32)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; + +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseStructInit +* Description : Fills each TIM_TimeBaseInitStruct member with its default value. +* Input : - TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/******************************************************************************* +* Function Name : TIM_OCStructInit +* Description : Fills each TIM_OCInitStruct member with its default value. +* Input : - TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/******************************************************************************* +* Function Name : TIM_ICStructInit +* Description : Fills each TIM_ICInitStruct member with its default value. +* Input : - TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/******************************************************************************* +* Function Name : TIM_BDTRStructInit +* Description : Fills each TIM_BDTRInitStruct member with its default value. +* Input : - TIM_BDTRInitStruct : pointer to a TIM_BDTRInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 1 to 8 to select the TIMx peripheral. +* - NewState: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= CR1_CEN_Set; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= CR1_CEN_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_CtrlPWMOutputs +* Description : Enables or disables the TIM peripheral Main Outputs. +* Input :- TIMx: where x can be 1 or 8 to select the TIMx peripheral. +* - NewState: new state of the TIM peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= BDTR_MOE_Set; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= BDTR_MOE_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the specified TIM interrupts. +* Input : - TIMx: where x can be 1 to 8 to select the TIMx peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: TIM update Interrupt source +* - TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* - TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* - TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* - TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* - TIM_IT_COM: TIM Commutation Interrupt source +* - TIM_IT_Trigger: TIM Trigger Interrupt source +* - TIM_IT_Break: TIM Break Interrupt source +* - NewState: new state of the TIM interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_TIM_PERIPH_IT((TIMx), (TIM_IT))); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (u16)~TIM_IT; + } +} + +/******************************************************************************* +* Function Name : TIM_GenerateEvent +* Description : Configures the TIMx event to be generate by software. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* - TIM_EventSource_Update: Timer update Event source +* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source +* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source +* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source +* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source +* - TIM_EventSource_Trigger: Timer Trigger Event source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + assert_param(IS_TIM_PERIPH_EVENT((TIMx), (TIM_EventSource))); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIMx’s DMA interface. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_DMABase: DMA Base address. +* This parameter can be one of the following values: +* - TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, +* TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, +* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, +* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, +* TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, +* TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, +* TIM_DMABase_DCR. +* - TIM_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIMx’s DMA Requests. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMA_Update: TIM update Interrupt source +* - TIM_DMA_CC1: TIM Capture Compare 1 DMA source +* - TIM_DMA_CC2: TIM Capture Compare 2 DMA source +* - TIM_DMA_CC3: TIM Capture Compare 3 DMA source +* - TIM_DMA_CC4: TIM Capture Compare 4 DMA source +* - TIM_DMA_COM: TIM Commutation DMA source +* - TIM_DMA_Trigger: TIM Trigger DMA source +* - NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_TIM_PERIPH_DMA(TIMx, TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (u16)~TIM_DMASource; + } +} + +/******************************************************************************* +* Function Name : TIM_InternalClockConfig +* Description : Configures the TIMx interrnal Clock +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= SMCR_SMS_Mask; +} +/******************************************************************************* +* Function Name : TIM_ITRxExternalClockConfig +* Description : Configures the TIMx Internal Trigger as External Clock +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ITRSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} +/******************************************************************************* +* Function Name : TIM_TIxExternalClockConfig +* Description : Configures the TIMx Trigger as External Clock +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector +* - TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 +* - TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 +* - TIM_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u16 ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode1Config +* Description : Configures the External clock Mode1 +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8. +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + u16 tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM_TS_ETRF; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode2Config +* Description : Configures the External clock Mode2 +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= SMCR_ECE_Set; +} + +/******************************************************************************* +* Function Name : TIM_ETRConfig +* Description : Configures the TIMx External Trigger (ETR). +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + u16 tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)(ExtTRGFilter << 8); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : Configures the TIMx Prescaler. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - Prescaler: specifies the Prescaler Register value +* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode +* This parameter can be one of the following values: +* - TIM_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the TIMx Counter Mode to be used. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + u16 tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectInputTrigger +* Description : Selects the Input Trigger source +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_InputTriggerSource: The Input Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_TS_ETRF: External Trigger input +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + u16 tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the TS Bits */ + tmpsmcr &= SMCR_TS_Mask; + + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_EncoderInterfaceConfig +* Description : Configures the TIMx Encoder Interface. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_EncoderMode: specifies the TIMx Encoder Mode. +* This parameter can be one of the following values: +* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* - TIM_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling: IC Falling edge. +* - TIM_ICPolarity_Rising: IC Rising edge. +* - TIM_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling: IC Falling edge. +* - TIM_ICPolarity_Rising: IC Rising edge. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity) +{ + u16 tmpsmcr = 0; + u16 tmpccmr1 = 0; + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset; + tmpccer |= (TIM_IC1Polarity | (u16)(TIM_IC2Polarity << 4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC1Config +* Description : Forces the TIMx output 1 waveform to active or inactive level. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC1REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC1REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1M Bits */ + tmpccmr1 &= CCMR_OC13M_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC2Config +* Description : Forces the TIMx output 2 waveform to active or inactive level. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC2REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC2REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2M Bits */ + tmpccmr1 &= CCMR_OC24M_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (u16)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC3Config +* Description : Forces the TIMx output 3 waveform to active or inactive level. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC3REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC3REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC1M Bits */ + tmpccmr2 &= CCMR_OC13M_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC4Config +* Description : Forces the TIMx output 4 waveform to active or inactive level. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC4REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC4REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC2M Bits */ + tmpccmr2 &= CCMR_OC24M_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (u16)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ARRPreloadConfig +* Description : Enables or disables TIMx peripheral Preload register on ARR. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - NewState: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= CR1_ARPE_Set; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= CR1_ARPE_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectCOM +* Description : Selects the TIM peripheral Commutation event. +* Input :- TIMx: where x can be 1 or 8 to select the TIMx peripheral +* - NewState: new state of the Commutation event. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= CR2_CCUS_Set; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= CR2_CCUS_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectCCDMA +* Description : Selects the TIMx peripheral Capture Compare DMA source. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - NewState: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= CR2_CCDS_Set; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= CR2_CCDS_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_CCPreloadControl +* Description : Sets or Resets the TIM peripheral Capture Compare Preload +* Control bit. +* Input :- TIMx: where x can be 1 or 8 to select the TIMx peripheral +* - NewState: new state of the Capture Compare Preload Control bit +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= CR2_CCPC_Set; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= CR2_CCPC_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_OC1PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR1. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1PE Bit */ + tmpccmr1 &= CCMR_OC13PE_Reset; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR2. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2PE Bit */ + tmpccmr1 &= CCMR_OC24PE_Reset; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (u16)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR3. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3PE Bit */ + tmpccmr2 &= CCMR_OC13PE_Reset; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR4. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4PE Bit */ + tmpccmr2 &= CCMR_OC24PE_Reset; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (u16)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1FastConfig +* Description : Configures the TIMx Output Compare 1 Fast feature. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable: TIM output compare fast enable +* - TIM_OCFast_Disable: TIM output compare fast disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1FE Bit */ + tmpccmr1 &= CCMR_OC13FE_Reset; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2FastConfig +* Description : Configures the TIMx Output Compare 2 Fast feature. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable: TIM output compare fast enable +* - TIM_OCFast_Disable: TIM output compare fast disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2FE Bit */ + tmpccmr1 &= CCMR_OC24FE_Reset; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (u16)(TIM_OCFast << 8); + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3FastConfig +* Description : Configures the TIMx Output Compare 3 Fast feature. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable: TIM output compare fast enable +* - TIM_OCFast_Disable: TIM output compare fast disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3FE Bit */ + tmpccmr2 &= CCMR_OC13FE_Reset; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4FastConfig +* Description : Configures the TIMx Output Compare 4 Fast feature. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable: TIM output compare fast enable +* - TIM_OCFast_Disable: TIM output compare fast disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4FE Bit */ + tmpccmr2 &= CCMR_OC24FE_Reset; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (u16)(TIM_OCFast << 8); + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ClearOC1Ref +* Description : Clears or safeguards the OCREF1 signal on an external event +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCClear_Enable: TIM Output clear enable +* - TIM_OCClear_Disable: TIM Output clear disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= CCMR_OC13CE_Reset; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ClearOC2Ref +* Description : Clears or safeguards the OCREF2 signal on an external event +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCClear_Enable: TIM Output clear enable +* - TIM_OCClear_Disable: TIM Output clear disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) +{ + u16 tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2CE Bit */ + tmpccmr1 &= CCMR_OC24CE_Reset; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (u16)(TIM_OCClear << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ClearOC3Ref +* Description : Clears or safeguards the OCREF3 signal on an external event +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCClear_Enable: TIM Output clear enable +* - TIM_OCClear_Disable: TIM Output clear disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3CE Bit */ + tmpccmr2 &= CCMR_OC13CE_Reset; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ClearOC4Ref +* Description : Clears or safeguards the OCREF4 signal on an external event +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCClear_Enable: TIM Output clear enable +* - TIM_OCClear_Disable: TIM Output clear disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) +{ + u16 tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4CE Bit */ + tmpccmr2 &= CCMR_OC24CE_Reset; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (u16)(TIM_OCClear << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1PolarityConfig +* Description : Configures the TIMx channel 1 polarity. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= CCER_CC1P_Reset; + tmpccer |= TIM_OCPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC1NPolarityConfig +* Description : Configures the TIMx Channel 1N polarity. +* Input : - TIMx: where x can be 1 or 8 to select the TIM peripheral. +* - TIM_OCNPolarity: specifies the OC1N Polarity +* This parmeter can be one of the following values: +* - TIM_OCNPolarity_High: Output Compare active high +* - TIM_OCNPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1NP Bit */ + tmpccer &= CCER_CC1NP_Reset; + tmpccer |= TIM_OCNPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC2PolarityConfig +* Description : Configures the TIMx channel 2 polarity. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= CCER_CC2P_Reset; + tmpccer |= (u16)(TIM_OCPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC2NPolarityConfig +* Description : Configures the TIMx Channel 2N polarity. +* Input : - TIMx: where x can be 1 or 8 to select the TIM peripheral. +* - TIM_OCNPolarity: specifies the OC2N Polarity +* This parmeter can be one of the following values: +* - TIM_OCNPolarity_High: Output Compare active high +* - TIM_OCNPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2NP Bit */ + tmpccer &= CCER_CC2NP_Reset; + tmpccer |= (u16)(TIM_OCNPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC3PolarityConfig +* Description : Configures the TIMx channel 3 polarity. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= CCER_CC3P_Reset; + tmpccer |= (u16)(TIM_OCPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC3NPolarityConfig +* Description : Configures the TIMx Channel 3N polarity. +* Input : - TIMx: where x can be 1 or 8 to select the TIM peripheral. +* - TIM_OCNPolarity: specifies the OC3N Polarity +* This parmeter can be one of the following values: +* - TIM_OCNPolarity_High: Output Compare active high +* - TIM_OCNPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3NP Bit */ + tmpccer &= CCER_CC3NP_Reset; + tmpccer |= (u16)(TIM_OCNPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC4PolarityConfig +* Description : Configures the TIMx channel 4 polarity. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u16 tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= CCER_CC4P_Reset; + tmpccer |= (u16)(TIM_OCPolarity << 12); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_CCxCmd +* Description : Enables or disables the TIM Capture Compare Channel x. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 +* - TIM_Channel_2: TIM Channel 2 +* - TIM_Channel_3: TIM Channel 3 +* - TIM_Channel_4: TIM Channel 4 +* - TIM_CCx: specifies the TIM Channel CCxE bit new state. +* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + /* Reset the CCxE Bit */ + TIMx->CCER &= (u16)(~((u16)(CCER_CCE_Set << TIM_Channel))); + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (u16)(TIM_CCx << TIM_Channel); +} + +/******************************************************************************* +* Function Name : TIM_CCxNCmd +* Description : Enables or disables the TIM Capture Compare Channel xN. +* Input :- TIMx: where x can be 1 or 8 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 +* - TIM_Channel_2: TIM Channel 2 +* - TIM_Channel_3: TIM Channel 3 +* - TIM_CCx: specifies the TIM Channel CCxNE bit new state. +* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (u16)(~((u16)(CCER_CCNE_Set << TIM_Channel))); + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (u16)(TIM_CCxN << TIM_Channel); +} + +/******************************************************************************* +* Function Name : TIM_SelectOCxM +* Description : Selects the TIM Ouput Compare Mode. +* This function disables the selected channel before changing +* the Ouput Compare Mode. User has to enable this channel using +* TIM_CCxCmd and TIM_CCxNCmd functions. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 +* - TIM_Channel_2: TIM Channel 2 +* - TIM_Channel_3: TIM Channel 3 +* - TIM_Channel_4: TIM Channel 4 +* - TIM_OCMode: specifies the TIM Output Compare Mode. +* This paramter can be one of the following values: +* - TIM_OCMode_Timing +* - TIM_OCMode_Active +* - TIM_OCMode_Toggle +* - TIM_OCMode_PWM1 +* - TIM_OCMode_PWM2 +* - TIM_ForcedAction_Active +* - TIM_ForcedAction_InActive +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (u16)(~((u16)(CCER_CCE_Set << TIM_Channel))); + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + /* Reset the OCxM bits in the CCMRx register */ + *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + (TIM_Channel>>1))) &= CCMR_OC13M_Mask; + + /* Configure the OCxM bits in the CCMRx register */ + *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + (TIM_Channel>>1))) |= TIM_OCMode; + + } + else + { + /* Reset the OCxM bits in the CCMRx register */ + *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + ((u16)(TIM_Channel - 4)>> 1))) &= CCMR_OC24M_Mask; + + /* Configure the OCxM bits in the CCMRx register */ + *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + ((u16)(TIM_Channel - 4)>> 1))) |= (u16)(TIM_OCMode << 8); + } +} + +/******************************************************************************* +* Function Name : TIM_UpdateDisableConfig +* Description : Enables or Disables the TIMx Update event. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - NewState: new state of the TIMx UDIS bit +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= CR1_UDIS_Set; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= CR1_UDIS_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_UpdateRequestConfig +* Description : Configures the TIMx Update Request Interrupt source. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* - TIM_UpdateSource_Regular +* - TIM_UpdateSource_Global +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= CR1_URS_Set; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= CR1_URS_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectHallSensor +* Description : Enables or disables the TIMx’s Hall sensor interface. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. +* - NewState: new state of the TIMx Hall sensor interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= CR2_TI1S_Set; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= CR2_TI1S_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectOnePulseMode +* Description : Selects the TIMx’s One Pulse Mode. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* - TIM_OPMode_Single +* - TIM_OPMode_Repetitive +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= CR1_OPM_Reset; + + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/******************************************************************************* +* Function Name : TIM_SelectOutputTrigger +* Description : Selects the TIMx Trigger Output Mode. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_TRGOSource: specifies the Trigger Output source. +* This paramter can be as follow: +* 1/ For TIM1 to TIM8: +* - TIM_TRGOSource_Reset +* - TIM_TRGOSource_Enable +* - TIM_TRGOSource_Update +* 2/ These parameters are available for all TIMx except +* TIM6 and TIM7: +* - TIM_TRGOSource_OC1 +* - TIM_TRGOSource_OC1Ref +* - TIM_TRGOSource_OC2Ref +* - TIM_TRGOSource_OC3Ref +* - TIM_TRGOSource_OC4Ref +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + assert_param(IS_TIM_PERIPH_TRGO(TIMx, TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= CR2_MMS_Mask; + + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/******************************************************************************* +* Function Name : TIM_SelectSlaveMode +* Description : Selects the TIMx Slave Mode. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_SlaveMode: specifies the Timer Slave Mode. +* This paramter can be one of the following values: +* - TIM_SlaveMode_Reset +* - TIM_SlaveMode_Gated +* - TIM_SlaveMode_Trigger +* - TIM_SlaveMode_External1 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= SMCR_SMS_Mask; + + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/******************************************************************************* +* Function Name : TIM_SelectMasterSlaveMode +* Description : Sets or Resets the TIMx Master/Slave Mode. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. +* This paramter can be one of the following values: +* - TIM_MasterSlaveMode_Enable: synchronization between the +* current timer and its slaves (through TRGO). +* - TIM_MasterSlaveMode_Disable: No action +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= SMCR_MSM_Reset; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/******************************************************************************* +* Function Name : TIM_SetCounter +* Description : Sets the TIMx Counter Register value +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - Counter: specifies the Counter register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/******************************************************************************* +* Function Name : TIM_SetAutoreload +* Description : Sets the TIMx Autoreload Register value +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - Autoreload: specifies the Autoreload register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare1 +* Description : Sets the TIMx Capture Compare1 Register value +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - Compare1: specifies the Capture Compare1 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare2 +* Description : Sets the TIMx Capture Compare2 Register value +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - Compare2: specifies the Capture Compare2 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare3 +* Description : Sets the TIMx Capture Compare3 Register value +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - Compare3: specifies the Capture Compare3 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare4 +* Description : Sets the TIMx Capture Compare4 Register value +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - Compare4: specifies the Capture Compare4 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/******************************************************************************* +* Function Name : TIM_SetIC1Prescaler +* Description : Sets the TIMx Input Capture 1 prescaler. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPSC: specifies the Input Capture1 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= CCMR_IC13PSC_Mask; + + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/******************************************************************************* +* Function Name : TIM_SetIC2Prescaler +* Description : Sets the TIMx Input Capture 2 prescaler. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPSC: specifies the Input Capture2 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= CCMR_IC24PSC_Mask; + + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (u16)(TIM_ICPSC << 8); +} + +/******************************************************************************* +* Function Name : TIM_SetIC3Prescaler +* Description : Sets the TIMx Input Capture 3 prescaler. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPSC: specifies the Input Capture3 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= CCMR_IC13PSC_Mask; + + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/******************************************************************************* +* Function Name : TIM_SetIC4Prescaler +* Description : Sets the TIMx Input Capture 4 prescaler. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPSC: specifies the Input Capture4 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= CCMR_IC24PSC_Mask; + + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (u16)(TIM_ICPSC << 8); +} + +/******************************************************************************* +* Function Name : TIM_SetClockDivision +* Description : Sets the TIMx Clock Division value. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* - TIM_CKD_DIV1: TDTS = Tck_tim +* - TIM_CKD_DIV2: TDTS = 2*Tck_tim +* - TIM_CKD_DIV4: TDTS = 4*Tck_tim +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= CR1_CKD_Mask; + + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} +/******************************************************************************* +* Function Name : TIM_GetCapture1 +* Description : Gets the TIMx Input Capture 1 value. +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* Output : None +* Return : Capture Compare 1 Register value. +*******************************************************************************/ +u16 TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture2 +* Description : Gets the TIMx Input Capture 2 value. +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* Output : None +* Return : Capture Compare 2 Register value. +*******************************************************************************/ +u16 TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture3 +* Description : Gets the TIMx Input Capture 3 value. +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* Output : None +* Return : Capture Compare 3 Register value. +*******************************************************************************/ +u16 TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture4 +* Description : Gets the TIMx Input Capture 4 value. +* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* Output : None +* Return : Capture Compare 4 Register value. +*******************************************************************************/ +u16 TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/******************************************************************************* +* Function Name : TIM_GetCounter +* Description : Gets the TIMx Counter value. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* Output : None +* Return : Counter Register value. +*******************************************************************************/ +u16 TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/******************************************************************************* +* Function Name : TIM_GetPrescaler +* Description : Gets the TIMx Prescaler value. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* Output : None +* Return : Prescaler Register value. +*******************************************************************************/ +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIM flag is set or not. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_Update: TIM update Flag +* - TIM_FLAG_CC1: TIM Capture Compare 1 Flag +* - TIM_FLAG_CC2: TIM Capture Compare 2 Flag +* - TIM_FLAG_CC3: TIM Capture Compare 3 Flag +* - TIM_FLAG_CC4: TIM Capture Compare 4 Flag +* - TIM_FLAG_COM: TIM Commutation Flag +* - TIM_FLAG_Trigger: TIM Trigger Flag +* - TIM_FLAG_Break: TIM Break Flag +* - TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + assert_param(IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_Update: TIM update Flag +* - TIM_FLAG_CC1: TIM Capture Compare 1 Flag +* - TIM_FLAG_CC2: TIM Capture Compare 2 Flag +* - TIM_FLAG_CC3: TIM Capture Compare 3 Flag +* - TIM_FLAG_CC4: TIM Capture Compare 4 Flag +* - TIM_FLAG_COM: TIM Commutation Flag +* - TIM_FLAG_Trigger: TIM Trigger Flag +* - TIM_FLAG_Break: TIM Break Flag +* - TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIMx, TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (u16)~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the TIM interrupt has occurred or not. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_Update: TIM update Interrupt source +* - TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* - TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* - TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* - TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* - TIM_IT_COM: TIM Commutation Interrupt +* source +* - TIM_IT_Trigger: TIM Trigger Interrupt source +* - TIM_IT_Break: TIM Break Interrupt source +* Output : None +* Return : The new state of the TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + ITStatus bitstatus = RESET; + u16 itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + + if ((itstatus != (u16)RESET) && (itenable != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIMx's interrupt pending bits. +* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. +* - TIM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: TIM1 update Interrupt source +* - TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* - TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* - TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* - TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* - TIM_IT_COM: TIM Commutation Interrupt +* source +* - TIM_IT_Trigger: TIM Trigger Interrupt source +* - TIM_IT_Break: TIM Break Interrupt source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR = (u16)~TIM_IT; +} + +/******************************************************************************* +* Function Name : TI1_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to +* be connected to IC1. +* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to +* be connected to IC2. +* - TIM_ICSelection_TRC: TIM Input 1 is selected to be +* connected to TRC. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter) +{ + u16 tmpccmr1 = 0, tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= CCER_CC1E_Reset; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= CCER_CC1P_Reset; + tmpccer |= TIM_ICPolarity | CCER_CC1E_Set; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TI2_Config +* Description : Configure the TI2 as Input. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to +* be connected to IC2. +* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to +* be connected to IC1. +* - TIM_ICSelection_TRC: TIM Input 2 is selected to be +* connected to TRC. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter) +{ + u16 tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC2E_Reset; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (u16)(TIM_ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (u16)(TIM_ICFilter << 12); + tmpccmr1 |= (u16)(TIM_ICSelection << 8); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= CCER_CC2P_Reset; + tmpccer |= tmp | CCER_CC2E_Set; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TI3_Config +* Description : Configure the TI3 as Input. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to +* be connected to IC3. +* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to +* be connected to IC4. +* - TIM_ICSelection_TRC: TIM Input 3 is selected to be +* connected to TRC. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter) +{ + u16 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= CCER_CC3E_Reset; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)(TIM_ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= CCER_CC3P_Reset; + tmpccer |= tmp | CCER_CC3E_Set; + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/******************************************************************************* +* Function Name : TI4_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM +* peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to +* be connected to IC4. +* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to +* be connected to IC3. +* - TIM_ICSelection_TRC: TIM Input 4 is selected to be +* connected to TRC. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u16 TIM_ICFilter) +{ + u16 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= CCER_CC4E_Reset; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (u16)(TIM_ICSelection << 8) | (u16)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= CCER_CC4P_Reset; + tmpccer |= tmp | CCER_CC4E_Set; + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_usart.c b/bsp/stm32/library/src/stm32f10x_usart.c new file mode 100644 index 0000000000..c49c78fb30 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_usart.c @@ -0,0 +1,1001 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_usart.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the USART firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* USART UE Mask */ +#define CR1_UE_Set ((u16)0x2000) /* USART Enable Mask */ +#define CR1_UE_Reset ((u16)0xDFFF) /* USART Disable Mask */ + +/* USART WakeUp Method */ +#define CR1_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */ + +/* USART RWU Mask */ +#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */ + +#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */ + +#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */ + +#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */ + +/* USART LIN Mask */ +#define CR2_LINEN_Set ((u16)0x4000) /* USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */ + +/* USART LIN Break detection */ +#define CR2_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */ + +#define CR2_STOP_CLEAR_Mask ((u16)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((u16)0xF0FF) /* USART CR2 Clock Mask */ + +/* USART SC Mask */ +#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */ +#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */ + +/* USART SC NACK Mask */ +#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */ + +/* USART Half-Duplex Mask */ +#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */ + +/* USART IrDA Mask */ +#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */ + +#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */ + +/* USART IrDA Mask */ +#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */ + +#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */ + +#define IT_Mask ((u16)0x001F) /* USART Interrupt Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : USART_DeInit +* Description : Deinitializes the USARTx peripheral registers to their +* default reset values. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* Output : None +* Return : None +*******************************************************************************/ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + switch (*(u32*)&USARTx) + { + case USART1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + break; + + case USART2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + break; + + case USART3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + break; + + case UART4_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + break; + + case UART5_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : USART_Init +* Description : Initializes the USARTx peripheral according to the specified +* parameters in the USART_InitStruct . +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_InitStruct: pointer to a USART_InitTypeDef structure +* that contains the configuration information for the +* specified USART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 tmpreg = 0x00, apbclock = 0x00; + u32 integerdivider = 0x00; + u32 fractionaldivider = 0x00; + u32 usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl)); + + usartxbase = (*(u32*)&USARTx); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (u32)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (u16)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (u16)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (u16)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 0x64) << 0x04; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04)); + tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F); + + /* Write to USART BRR */ + USARTx->BRR = (u16)tmpreg; +} + +/******************************************************************************* +* Function Name : USART_StructInit +* Description : Fills each USART_InitStruct member with its default value. +* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/******************************************************************************* +* Function Name : USART_ClockInit +* Description : Initializes the USARTx peripheral Clock according to the +* specified parameters in the USART_ClockInitStruct . +* Input : - USARTx: where x can be 1, 2, 3 to select the USART peripheral. +* Note: The Smart Card mode is not available for UART4 and UART5. +* - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef +* structure that contains the configuration information for +* the specified USART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (u32)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + + /* Write to USART CR2 */ + USARTx->CR2 = (u16)tmpreg; +} + +/******************************************************************************* +* Function Name : USART_ClockStructInit +* Description : Fills each USART_ClockInitStruct member with its default value. +* Input : - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/******************************************************************************* +* Function Name : USART_Cmd +* Description : Enables or disables the specified USART peripheral. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* : - NewState: new state of the USARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_ITConfig +* Description : Enables or disables the specified USART interrupts. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_IT: specifies the USART interrupt sources to be +* enabled or disabled. +* This parameter can be one of the following values: +* - USART_IT_CTS: CTS change interrupt (not available for +* UART4 and UART5) +* - USART_IT_LBD: LIN Break detection interrupt +* - USART_IT_TXE: Tansmit Data Register empty interrupt +* - USART_IT_TC: Transmission complete interrupt +* - USART_IT_RXNE: Receive Data register not empty +* interrupt +* - USART_IT_IDLE: Idle line detection interrupt +* - USART_IT_PE: Parity Error interrupt +* - USART_IT_ERR: Error interrupt(Frame error, noise +* error, overrun error) +* - NewState: new state of the specified USARTx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState) +{ + u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00; + u32 usartxbase = 0x00; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + usartxbase = (*(u32*)&(USARTx)); + + /* Get the USART register index */ + usartreg = (((u8)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + + itmask = (((u32)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(vu32*)usartxbase |= itmask; + } + else + { + *(vu32*)usartxbase &= ~itmask; + } +} + +/******************************************************************************* +* Function Name : USART_DMACmd +* Description : Enables or disables the USART’s DMA interface. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3 or UART4. +* Note: The DMA mode is not available for UART5. +* - USART_DMAReq: specifies the DMA request. +* This parameter can be any combination of the following values: +* - USART_DMAReq_Tx: USART DMA transmit request +* - USART_DMAReq_Rx: USART DMA receive request +* - NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1234_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (u16)~USART_DMAReq; + } +} + +/******************************************************************************* +* Function Name : USART_SetAddress +* Description : Sets the address of the USART node. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_Address: Indicates the address of the USART node. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/******************************************************************************* +* Function Name : USART_WakeUpConfig +* Description : Selects the USART WakeUp method. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_WakeUp: specifies the USART wakeup method. +* This parameter can be one of the following values: +* - USART_WakeUp_IdleLine: WakeUp by an idle line detection +* - USART_WakeUp_AddressMark: WakeUp by an address mark +* Output : None +* Return : None +*******************************************************************************/ +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/******************************************************************************* +* Function Name : USART_ReceiverWakeUpCmd +* Description : Determines if the USART is in mute mode or not. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - NewState: new state of the USART mute mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_LINBreakDetectLengthConfig +* Description : Sets the USART LIN Break detection length. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_LINBreakDetectLength: specifies the LIN break +* detection length. +* This parameter can be one of the following values: +* - USART_LINBreakDetectLength_10b: 10-bit break detection +* - USART_LINBreakDetectLength_11b: 11-bit break detection +* Output : None +* Return : None +*******************************************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/******************************************************************************* +* Function Name : USART_LINCmd +* Description : Enables or disables the USART’s LIN mode. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - NewState: new state of the USART LIN mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_SendData +* Description : Transmits single data through the USARTx peripheral. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - Data: the data to transmit. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SendData(USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (u16)0x01FF); +} + +/******************************************************************************* +* Function Name : USART_ReceiveData +* Description : Returns the most recent received data by the USARTx peripheral. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* Output : None +* Return : The received data. +*******************************************************************************/ +u16 USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (u16)(USARTx->DR & (u16)0x01FF); +} + +/******************************************************************************* +* Function Name : USART_SendBreak +* Description : Transmits break characters. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/******************************************************************************* +* Function Name : USART_SetGuardTime +* Description : Sets the specified USART guard time. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Note: The guard time bits are not available for UART4 and UART5. +* - USART_GuardTime: specifies the guard time. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08); +} + +/******************************************************************************* +* Function Name : USART_SetPrescaler +* Description : Sets the system clock prescaler. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* Note: The function is used for IrDA mode with UART4 and UART5. +* - USART_Prescaler: specifies the prescaler clock. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/******************************************************************************* +* Function Name : USART_SmartCardCmd +* Description : Enables or disables the USART’s Smart Card mode. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Note: The Smart Card mode is not available for UART4 and UART5. +* - NewState: new state of the Smart Card mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_SmartCardNACKCmd +* Description : Enables or disables NACK transmission. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Note: The Smart Card mode is not available for UART4 and UART5. +* - NewState: new state of the NACK transmission. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_HalfDuplexCmd +* Description : Enables or disables the USART’s Half Duplex communication. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - NewState: new state of the USART Communication. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_IrDAConfig +* Description : Configures the USART’s IrDA interface. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_IrDAMode: specifies the IrDA mode. +* This parameter can be one of the following values: +* - USART_IrDAMode_LowPower +* - USART_IrDAMode_Normal +* Output : None +* Return : None +*******************************************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/******************************************************************************* +* Function Name : USART_IrDACmd +* Description : Enables or disables the USART’s IrDA interface. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - NewState: new state of the IrDA mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_GetFlagStatus +* Description : Checks whether the specified USART flag is set or not. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - USART_FLAG_CTS: CTS Change flag (not available for +* UART4 and UART5) +* - USART_FLAG_LBD: LIN Break detection flag +* - USART_FLAG_TXE: Transmit data register empty flag +* - USART_FLAG_TC: Transmission Complete flag +* - USART_FLAG_RXNE: Receive data register not empty flag +* - USART_FLAG_IDLE: Idle Line detection flag +* - USART_FLAG_ORE: OverRun Error flag +* - USART_FLAG_NE: Noise Error flag +* - USART_FLAG_FE: Framing Error flag +* - USART_FLAG_PE: Parity Error flag +* Output : None +* Return : The new state of USART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ + + if ((USARTx->SR & USART_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : USART_ClearFlag +* Description : Clears the USARTx's pending flags. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - USART_FLAG_CTS: CTS Change flag (not available for +* UART4 and UART5). +* - USART_FLAG_LBD: LIN Break detection flag. +* - USART_FLAG_TC: Transmission Complete flag. +* - USART_FLAG_RXNE: Receive data register not empty flag. +* +* Notes: +* - PE (Parity error), FE (Framing error), NE (Noise error), +* ORE (OverRun error) and IDLE (Idle line detected) +* flags are cleared by software sequence: a read +* operation to USART_SR register (USART_GetFlagStatus()) +* followed by a read operation to USART_DR register +* (USART_ReceiveData()). +* - RXNE flag can be also cleared by a read to the +* USART_DR register (USART_ReceiveData()). +* - TC flag can be also cleared by software sequence: a +* read operation to USART_SR register +* (USART_GetFlagStatus()) followed by a write operation +* to USART_DR register (USART_SendData()). +* - TXE flag is cleared only by a write to the USART_DR +* register (USART_SendData()). +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ + + USARTx->SR = (u16)~USART_FLAG; +} + +/******************************************************************************* +* Function Name : USART_GetITStatus +* Description : Checks whether the specified USART interrupt has occurred or not. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_IT: specifies the USART interrupt source to check. +* This parameter can be one of the following values: +* - USART_IT_CTS: CTS change interrupt (not available for +* UART4 and UART5) +* - USART_IT_LBD: LIN Break detection interrupt +* - USART_IT_TXE: Tansmit Data Register empty interrupt +* - USART_IT_TC: Transmission complete interrupt +* - USART_IT_RXNE: Receive Data register not empty +* interrupt +* - USART_IT_IDLE: Idle line detection interrupt +* - USART_IT_ORE: OverRun Error interrupt +* - USART_IT_NE: Noise Error interrupt +* - USART_IT_FE: Framing Error interrupt +* - USART_IT_PE: Parity Error interrupt +* Output : None +* Return : The new state of USART_IT (SET or RESET). +*******************************************************************************/ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT) +{ + u32 bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ + + /* Get the USART register index */ + usartreg = (((u8)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + + itmask = (u32)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + + bitpos = (u32)0x01 << bitpos; + bitpos &= USARTx->SR; + + if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/******************************************************************************* +* Function Name : USART_ClearITPendingBit +* Description : Clears the USARTx’s interrupt pending bits. +* Input : - USARTx: Select the USART or the UART peripheral. +* This parameter can be one of the following values: +* - USART1, USART2, USART3, UART4 or UART5. +* - USART_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* - USART_IT_CTS: CTS change interrupt (not available for +* UART4 and UART5) +* - USART_IT_LBD: LIN Break detection interrupt +* - USART_IT_TC: Transmission complete interrupt. +* - USART_IT_RXNE: Receive Data register not empty interrupt. +* +* Notes: +* - PE (Parity error), FE (Framing error), NE (Noise error), +* ORE (OverRun error) and IDLE (Idle line detected) +* pending bits are cleared by software sequence: a read +* operation to USART_SR register (USART_GetITStatus()) +* followed by a read operation to USART_DR register +* (USART_ReceiveData()). +* - RXNE pending bit can be also cleared by a read to the +* USART_DR register (USART_ReceiveData()). +* - TC pending bit can be also cleared by software +* sequence: a read operation to USART_SR register +* (USART_GetITStatus()) followed by a write operation +* to USART_DR register (USART_SendData()). +* - TXE pending bit is cleared only by a write to the +* USART_DR register (USART_SendData()). +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT) +{ + u16 bitpos = 0x00, itmask = 0x00; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ + + bitpos = USART_IT >> 0x08; + + itmask = (u16)((u16)0x01 << bitpos); + USARTx->SR = (u16)~itmask; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/library/src/stm32f10x_wwdg.c b/bsp/stm32/library/src/stm32f10x_wwdg.c new file mode 100644 index 0000000000..7fe7f64869 --- /dev/null +++ b/bsp/stm32/library/src/stm32f10x_wwdg.c @@ -0,0 +1,185 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_wwdg.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the WWDG firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_WDGA_Set ((u32)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F) +#define CFR_W_Mask ((u32)0xFFFFFF80) + +#define BIT_Mask ((u8)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : WWDG_DeInit +* Description : Deinitializes the WWDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/******************************************************************************* +* Function Name : WWDG_SetPrescaler +* Description : Sets the WWDG Prescaler. +* Input : - WWDG_Prescaler: specifies the WWDG Prescaler. +* This parameter can be one of the following values: +* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 +* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 +* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 +* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetPrescaler(u32 WWDG_Prescaler) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/******************************************************************************* +* Function Name : WWDG_SetWindowValue +* Description : Sets the WWDG window value. +* Input : - WindowValue: specifies the window value to be compared to +* the downcounter. +* This parameter value must be lower than 0x80. +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetWindowValue(u8 WindowValue) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + + /* Clear W[6:0] bits */ + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/******************************************************************************* +* Function Name : WWDG_EnableIT +* Description : Enables the WWDG Early Wakeup interrupt(EWI). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_EnableIT(void) +{ + *(vu32 *) CFR_EWI_BB = (u32)ENABLE; +} + +/******************************************************************************* +* Function Name : WWDG_SetCounter +* Description : Sets the WWDG counter value. +* Input : - Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetCounter(u8 Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/******************************************************************************* +* Function Name : WWDG_Enable +* Description : Enables WWDG and load the counter value. +* - Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_Enable(u8 Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + + WWDG->CR = CR_WDGA_Set | Counter; +} + +/******************************************************************************* +* Function Name : WWDG_GetFlagStatus +* Description : Checks whether the Early Wakeup interrupt flag is set or not. +* Input : None +* Output : None +* Return : The new state of the Early Wakeup interrupt flag (SET or RESET) +*******************************************************************************/ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/******************************************************************************* +* Function Name : WWDG_ClearFlag +* Description : Clears Early Wakeup interrupt flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (u32)RESET; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/project.Opt b/bsp/stm32/project.Opt new file mode 100644 index 0000000000..953a28e978 --- /dev/null +++ b/bsp/stm32/project.Opt @@ -0,0 +1,197 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (RT-Thread/STM32), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Startup),0,0,0 +GRPOPT 2,(Library),0,0,0 +GRPOPT 3,(Kernel),0,0,0 +GRPOPT 4,(STM32),0,0,0 +GRPOPT 5,(finsh),0,0,0 +GRPOPT 6,(Filesystem),0,0,0 +GRPOPT 7,(LwIP),0,0,0 +GRPOPT 8,(GoAhead),0,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<.\application.c> +OPTFFF 1,2,1,0,0,0,0,0,<.\board.c> +OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c> +OPTFFF 1,4,2,0,0,0,0,0,<.\cortexm3_macro.s> +OPTFFF 1,5,1,184549376,0,0,0,0,<.\stm32f10x_it.c> +OPTFFF 1,6,5,0,0,0,0,0,<.\stm32f10x_conf.h> +OPTFFF 1,7,5,268435456,0,0,0,0,<.\rtconfig.h> +OPTFFF 1,8,1,0,0,0,0,0,<.\usart.c> +OPTFFF 1,9,1,0,0,0,0,0,<.\sdcard.c> +OPTFFF 1,10,1,0,0,0,0,0,<.\enc28j60.c> +OPTFFF 1,11,1,0,0,0,0,0,<.\rtc.c> +OPTFFF 2,12,1,0,0,0,0,0,<.\library\src\stm32f10x_adc.c> +OPTFFF 2,13,1,0,0,0,0,0,<.\library\src\stm32f10x_bkp.c> +OPTFFF 2,14,1,0,0,0,0,0,<.\library\src\stm32f10x_can.c> +OPTFFF 2,15,1,0,0,0,0,0,<.\library\src\stm32f10x_crc.c> +OPTFFF 2,16,1,0,0,0,0,0,<.\library\src\stm32f10x_dac.c> +OPTFFF 2,17,1,0,0,0,0,0,<.\library\src\stm32f10x_dbgmcu.c> +OPTFFF 2,18,1,0,0,0,0,0,<.\library\src\stm32f10x_dma.c> +OPTFFF 2,19,1,0,0,0,0,0,<.\library\src\stm32f10x_exti.c> +OPTFFF 2,20,1,0,0,0,0,0,<.\library\src\stm32f10x_flash.c> +OPTFFF 2,21,1,0,0,0,0,0,<.\library\src\stm32f10x_fsmc.c> +OPTFFF 2,22,1,0,0,0,0,0,<.\library\src\stm32f10x_gpio.c> +OPTFFF 2,23,1,0,0,0,0,0,<.\library\src\stm32f10x_i2c.c> +OPTFFF 2,24,1,0,0,0,0,0,<.\library\src\stm32f10x_iwdg.c> +OPTFFF 2,25,1,0,0,0,0,0,<.\library\src\stm32f10x_lib.c> +OPTFFF 2,26,1,0,0,0,0,0,<.\library\src\stm32f10x_nvic.c> +OPTFFF 2,27,1,0,0,0,0,0,<.\library\src\stm32f10x_pwr.c> +OPTFFF 2,28,1,0,0,0,0,0,<.\library\src\stm32f10x_rcc.c> +OPTFFF 2,29,1,0,0,0,0,0,<.\library\src\stm32f10x_rtc.c> +OPTFFF 2,30,1,0,0,0,0,0,<.\library\src\stm32f10x_sdio.c> +OPTFFF 2,31,1,0,0,0,0,0,<.\library\src\stm32f10x_spi.c> +OPTFFF 2,32,1,0,0,0,0,0,<.\library\src\stm32f10x_systick.c> +OPTFFF 2,33,1,0,0,0,0,0,<.\library\src\stm32f10x_tim.c> +OPTFFF 2,34,1,0,0,0,0,0,<.\library\src\stm32f10x_usart.c> +OPTFFF 2,35,1,0,0,0,0,0,<.\library\src\stm32f10x_wwdg.c> +OPTFFF 3,36,1,0,0,0,0,0,<..\..\src\clock.c> +OPTFFF 3,37,1,0,0,0,0,0,<..\..\src\idle.c> +OPTFFF 3,38,1,0,0,0,0,0,<..\..\src\ipc.c> +OPTFFF 3,39,1,16777216,0,0,0,0,<..\..\src\mem.c> +OPTFFF 3,40,1,0,0,0,0,0,<..\..\src\mempool.c> +OPTFFF 3,41,1,0,0,0,0,0,<..\..\src\object.c> +OPTFFF 3,42,1,0,0,0,0,0,<..\..\src\scheduler.c> +OPTFFF 3,43,1,0,0,0,0,0,<..\..\src\thread.c> +OPTFFF 3,44,1,0,0,0,0,0,<..\..\src\timer.c> +OPTFFF 3,45,1,0,0,0,0,0,<..\..\src\irq.c> +OPTFFF 3,46,1,33554432,0,0,0,0,<..\..\src\kservice.c> +OPTFFF 3,47,1,0,0,0,0,0,<..\..\src\device.c> +OPTFFF 3,48,1,0,0,0,0,0,<..\..\src\slab.c> +OPTFFF 4,49,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\stack.c> +OPTFFF 4,50,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\interrupt.c> +OPTFFF 4,51,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\cpu.c> +OPTFFF 4,52,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\serial.c> +OPTFFF 4,53,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\context_rvds.S> +OPTFFF 4,54,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\start_rvds.s> +OPTFFF 4,55,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault.c> +OPTFFF 4,56,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault_rvds.S> +OPTFFF 5,57,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c> +OPTFFF 5,58,1,0,0,0,0,0,<..\..\finsh\finsh_error.c> +OPTFFF 5,59,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c> +OPTFFF 5,60,1,0,0,0,0,0,<..\..\finsh\finsh_init.c> +OPTFFF 5,61,1,0,0,0,0,0,<..\..\finsh\finsh_node.c> +OPTFFF 5,62,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c> +OPTFFF 5,63,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c> +OPTFFF 5,64,1,0,0,0,0,0,<..\..\finsh\finsh_token.c> +OPTFFF 5,65,1,0,0,0,0,0,<..\..\finsh\finsh_var.c> +OPTFFF 5,66,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c> +OPTFFF 5,67,1,0,0,0,0,0,<..\..\finsh\shell.c> +OPTFFF 5,68,1,0,0,0,0,0,<..\..\finsh\symbol.c> +OPTFFF 5,69,1,0,0,0,0,0,<..\..\finsh\cmd.c> +OPTFFF 6,70,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c> +OPTFFF 6,71,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c> +OPTFFF 6,72,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c> +OPTFFF 6,73,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c> +OPTFFF 6,74,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c> +OPTFFF 6,75,1,268435456,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c> +OPTFFF 6,76,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c> +OPTFFF 6,77,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c> +OPTFFF 6,78,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c> +OPTFFF 6,79,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c> +OPTFFF 6,80,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c> +OPTFFF 6,81,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c> +OPTFFF 6,82,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c> +OPTFFF 6,83,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c> +OPTFFF 6,84,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c> +OPTFFF 6,85,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c> +OPTFFF 6,86,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c> +OPTFFF 7,87,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c> +OPTFFF 7,88,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c> +OPTFFF 7,89,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c> +OPTFFF 7,90,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c> +OPTFFF 7,91,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c> +OPTFFF 7,92,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c> +OPTFFF 7,93,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c> +OPTFFF 7,94,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c> +OPTFFF 7,95,1,301989888,0,0,0,0,<..\..\net\lwip\src\core\tcp.c> +OPTFFF 7,96,1,352321536,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c> +OPTFFF 7,97,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c> +OPTFFF 7,98,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c> +OPTFFF 7,99,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c> +OPTFFF 7,100,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c> +OPTFFF 7,101,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c> +OPTFFF 7,102,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c> +OPTFFF 7,103,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c> +OPTFFF 7,104,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c> +OPTFFF 7,105,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c> +OPTFFF 7,106,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c> +OPTFFF 7,107,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c> +OPTFFF 7,108,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c> +OPTFFF 7,109,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c> +OPTFFF 7,110,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c> +OPTFFF 7,111,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c> +OPTFFF 7,112,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c> +OPTFFF 7,113,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c> +OPTFFF 7,114,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c> +OPTFFF 7,115,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c> +OPTFFF 7,116,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c> +OPTFFF 7,117,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c> +OPTFFF 7,118,1,0,0,0,0,0,<..\..\net\lwip\src\netif\loopif.c> +OPTFFF 7,119,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c> +OPTFFF 7,120,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c> +OPTFFF 7,121,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c> +OPTFFF 7,122,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c> +OPTFFF 8,123,1,0,0,0,0,0,<..\..\net\webserver\websuemf.c> +OPTFFF 8,124,1,0,0,0,0,0,<..\..\net\webserver\asp.c> +OPTFFF 8,125,1,0,0,0,0,0,<..\..\net\webserver\balloc.c> +OPTFFF 8,126,1,0,0,0,0,0,<..\..\net\webserver\base64.c> +OPTFFF 8,127,1,0,0,0,0,0,<..\..\net\webserver\default.c> +OPTFFF 8,128,1,0,0,0,0,0,<..\..\net\webserver\ejlex.c> +OPTFFF 8,129,1,0,0,0,0,0,<..\..\net\webserver\ejparse.c> +OPTFFF 8,130,1,0,0,0,0,0,<..\..\net\webserver\emfdb.c> +OPTFFF 8,131,1,0,0,0,0,0,<..\..\net\webserver\form.c> +OPTFFF 8,132,1,0,0,0,0,0,<..\..\net\webserver\h.c> +OPTFFF 8,133,1,0,0,0,0,0,<..\..\net\webserver\handler.c> +OPTFFF 8,134,1,0,0,0,0,0,<..\..\net\webserver\mime.c> +OPTFFF 8,135,1,0,0,0,0,0,<..\..\net\webserver\misc.c> +OPTFFF 8,136,1,0,0,0,0,0,<..\..\net\webserver\page.c> +OPTFFF 8,137,1,0,0,0,0,0,<..\..\net\webserver\ringq.c> +OPTFFF 8,138,1,0,0,0,0,0,<..\..\net\webserver\rom.c> +OPTFFF 8,139,1,0,0,0,0,0,<..\..\net\webserver\security.c> +OPTFFF 8,140,1,0,0,0,0,0,<..\..\net\webserver\sock.c> +OPTFFF 8,141,1,0,0,0,0,0,<..\..\net\webserver\sockGen.c> +OPTFFF 8,142,1,0,0,0,0,0,<..\..\net\webserver\sym.c> +OPTFFF 8,143,1,0,0,0,0,0,<..\..\net\webserver\uemf.c> +OPTFFF 8,144,1,33554432,0,0,0,0,<..\..\net\webserver\um.c> +OPTFFF 8,145,1,0,0,0,0,0,<..\..\net\webserver\umui.c> +OPTFFF 8,146,1,0,0,0,0,0,<..\..\net\webserver\url.c> +OPTFFF 8,147,1,0,0,0,0,0,<..\..\net\webserver\value.c> +OPTFFF 8,148,1,0,0,0,0,0,<..\..\net\webserver\webs.c> +OPTFFF 8,149,1,0,0,0,0,0,<..\..\net\webserver\RTT\main.c> + + +TARGOPT 1, (RT-Thread/STM32) + ADSCLK=8000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\obj\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 0 + OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE) + OPTDBG 48118,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() + OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)) + OPTKEY 0,(JL2CM3)(-U20090110 -O206 -S0 -C0 -JU1 -JI127.0.0.1 -JP0 -N00("ARM CoreSight SW-DP") -D00(3BA00477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000) + OPTKEY 0,(DLGTARM)((1010=477,119,843,669,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=75,107,486,505,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=180,221,497,575,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)() + OPTKEY 0,(JLTAgdi)(-O1070 -J1 -Y1000 -Z1 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000) + OPTKEY 0,(JLTDLG)() + OPTMM 1,2,(0x2000629c) + OPTDF 0x84 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/bsp/stm32/project.Uv2 b/bsp/stm32/project.Uv2 new file mode 100644 index 0000000000..ef56fd99f5 --- /dev/null +++ b/bsp/stm32/project.Uv2 @@ -0,0 +1,277 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (RT-Thread/STM32), 0x0004 // Tools: 'ARM-ADS' + +Group (Startup) +Group (Library) +Group (Kernel) +Group (STM32) +Group (finsh) +Group (Filesystem) +Group (LwIP) +Group (GoAhead) + +File 1,1,<.\application.c> +File 1,1,<.\board.c> +File 1,1,<.\startup.c> +File 1,2,<.\cortexm3_macro.s> +File 1,1,<.\stm32f10x_it.c> +File 1,5,<.\stm32f10x_conf.h> +File 1,5,<.\rtconfig.h> +File 1,1,<.\usart.c> +File 1,1,<.\sdcard.c> +File 1,1,<.\enc28j60.c> +File 1,1,<.\rtc.c> +File 2,1,<.\library\src\stm32f10x_adc.c> +File 2,1,<.\library\src\stm32f10x_bkp.c> +File 2,1,<.\library\src\stm32f10x_can.c> +File 2,1,<.\library\src\stm32f10x_crc.c> +File 2,1,<.\library\src\stm32f10x_dac.c> +File 2,1,<.\library\src\stm32f10x_dbgmcu.c> +File 2,1,<.\library\src\stm32f10x_dma.c> +File 2,1,<.\library\src\stm32f10x_exti.c> +File 2,1,<.\library\src\stm32f10x_flash.c> +File 2,1,<.\library\src\stm32f10x_fsmc.c> +File 2,1,<.\library\src\stm32f10x_gpio.c> +File 2,1,<.\library\src\stm32f10x_i2c.c> +File 2,1,<.\library\src\stm32f10x_iwdg.c> +File 2,1,<.\library\src\stm32f10x_lib.c> +File 2,1,<.\library\src\stm32f10x_nvic.c> +File 2,1,<.\library\src\stm32f10x_pwr.c> +File 2,1,<.\library\src\stm32f10x_rcc.c> +File 2,1,<.\library\src\stm32f10x_rtc.c> +File 2,1,<.\library\src\stm32f10x_sdio.c> +File 2,1,<.\library\src\stm32f10x_spi.c> +File 2,1,<.\library\src\stm32f10x_systick.c> +File 2,1,<.\library\src\stm32f10x_tim.c> +File 2,1,<.\library\src\stm32f10x_usart.c> +File 2,1,<.\library\src\stm32f10x_wwdg.c> +File 3,1,<..\..\src\clock.c> +File 3,1,<..\..\src\idle.c> +File 3,1,<..\..\src\ipc.c> +File 3,1,<..\..\src\mem.c> +File 3,1,<..\..\src\mempool.c> +File 3,1,<..\..\src\object.c> +File 3,1,<..\..\src\scheduler.c> +File 3,1,<..\..\src\thread.c> +File 3,1,<..\..\src\timer.c> +File 3,1,<..\..\src\irq.c> +File 3,1,<..\..\src\kservice.c> +File 3,1,<..\..\src\device.c> +File 3,1,<..\..\src\slab.c> +File 4,1,<..\..\libcpu\arm\stm32\stack.c> +File 4,1,<..\..\libcpu\arm\stm32\interrupt.c> +File 4,1,<..\..\libcpu\arm\stm32\cpu.c> +File 4,1,<..\..\libcpu\arm\stm32\serial.c> +File 4,2,<..\..\libcpu\arm\stm32\context_rvds.S> +File 4,2,<..\..\libcpu\arm\stm32\start_rvds.s> +File 4,1,<..\..\libcpu\arm\stm32\fault.c> +File 4,2,<..\..\libcpu\arm\stm32\fault_rvds.S> +File 5,1,<..\..\finsh\finsh_compiler.c> +File 5,1,<..\..\finsh\finsh_error.c> +File 5,1,<..\..\finsh\finsh_heap.c> +File 5,1,<..\..\finsh\finsh_init.c> +File 5,1,<..\..\finsh\finsh_node.c> +File 5,1,<..\..\finsh\finsh_ops.c> +File 5,1,<..\..\finsh\finsh_parser.c> +File 5,1,<..\..\finsh\finsh_token.c> +File 5,1,<..\..\finsh\finsh_var.c> +File 5,1,<..\..\finsh\finsh_vm.c> +File 5,1,<..\..\finsh\shell.c> +File 5,1,<..\..\finsh\symbol.c> +File 5,1,<..\..\finsh\cmd.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_init.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_fs.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_raw.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_util.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_cache.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_posix.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c> +File 7,1,<..\..\net\lwip\src\core\dhcp.c> +File 7,1,<..\..\net\lwip\src\core\dns.c> +File 7,1,<..\..\net\lwip\src\core\init.c> +File 7,1,<..\..\net\lwip\src\core\netif.c> +File 7,1,<..\..\net\lwip\src\core\pbuf.c> +File 7,1,<..\..\net\lwip\src\core\raw.c> +File 7,1,<..\..\net\lwip\src\core\stats.c> +File 7,1,<..\..\net\lwip\src\core\sys.c> +File 7,1,<..\..\net\lwip\src\core\tcp.c> +File 7,1,<..\..\net\lwip\src\core\tcp_in.c> +File 7,1,<..\..\net\lwip\src\core\tcp_out.c> +File 7,1,<..\..\net\lwip\src\core\udp.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\autoip.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\icmp.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\igmp.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\inet.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\inet_chksum.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\ip.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\ip_addr.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\ip_frag.c> +File 7,1,<..\..\net\lwip\src\core\snmp\msg_in.c> +File 7,1,<..\..\net\lwip\src\core\snmp\msg_out.c> +File 7,1,<..\..\net\lwip\src\api\api_lib.c> +File 7,1,<..\..\net\lwip\src\api\api_msg.c> +File 7,1,<..\..\net\lwip\src\api\err.c> +File 7,1,<..\..\net\lwip\src\api\netbuf.c> +File 7,1,<..\..\net\lwip\src\api\netdb.c> +File 7,1,<..\..\net\lwip\src\api\netifapi.c> +File 7,1,<..\..\net\lwip\src\api\tcpip.c> +File 7,1,<..\..\net\lwip\src\netif\etharp.c> +File 7,1,<..\..\net\lwip\src\netif\ethernetif.c> +File 7,1,<..\..\net\lwip\src\netif\loopif.c> +File 7,1,<..\..\net\lwip\src\arch\sys_arch_init.c> +File 7,1,<..\..\net\lwip\src\arch\sys_arch.c> +File 7,1,<..\..\net\lwip\src\api\sockets.c> +File 7,1,<..\..\net\lwip\src\core\memp_tiny.c> +File 8,1,<..\..\net\webserver\websuemf.c> +File 8,1,<..\..\net\webserver\asp.c> +File 8,1,<..\..\net\webserver\balloc.c> +File 8,1,<..\..\net\webserver\base64.c> +File 8,1,<..\..\net\webserver\default.c> +File 8,1,<..\..\net\webserver\ejlex.c> +File 8,1,<..\..\net\webserver\ejparse.c> +File 8,1,<..\..\net\webserver\emfdb.c> +File 8,1,<..\..\net\webserver\form.c> +File 8,1,<..\..\net\webserver\h.c> +File 8,1,<..\..\net\webserver\handler.c> +File 8,1,<..\..\net\webserver\mime.c> +File 8,1,<..\..\net\webserver\misc.c> +File 8,1,<..\..\net\webserver\page.c> +File 8,1,<..\..\net\webserver\ringq.c> +File 8,1,<..\..\net\webserver\rom.c> +File 8,1,<..\..\net\webserver\security.c> +File 8,1,<..\..\net\webserver\sock.c> +File 8,1,<..\..\net\webserver\sockGen.c> +File 8,1,<..\..\net\webserver\sym.c> +File 8,1,<..\..\net\webserver\uemf.c> +File 8,1,<..\..\net\webserver\um.c> +File 8,1,<..\..\net\webserver\umui.c> +File 8,1,<..\..\net\webserver\url.c> +File 8,1,<..\..\net\webserver\value.c> +File 8,1,<..\..\net\webserver\webs.c> +File 8,1,<..\..\net\webserver\RTT\main.c> + + +Options 1,0,0 // Target 'RT-Thread/STM32' + Device (STM32F103ZE) + Vendor (STMicroelectronics) + Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")) + FlashDR (UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)) + DevID (4216) + Rgf (stm32f10x_lib.h) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿST\STM32F10x\) + OrgReg (ÿST\STM32F10x\) + TgStat=16 + OutDir (.\obj\) + OutName (rtthread-stm32) + GenApp=1 + GenLib=0 + GenHex=1 + Debug=1 + Browse=1 + LstDir (.\obj\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } + OCMADSIROM { 1,0,0,0,8,0,0,8,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 5,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN () + ADSCUDEF () + ADSCINCD (.\library\inc;.\library\src;..\stm32;..\..\include;..\..\libcpu\arm\stm32;..\..\finsh;..\..\rtgui\include;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\net\lwip\src;..\..\net\lwip\src\include;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x08000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--keep __fsym_* --keep __vsym_*) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE) + OPTDBG 48118,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() + FLASH1 { 9,0,0,0,1,0,0,0,5,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (Segger\JL2CM3.dll) + FLASH3 ("" ()) + FLASH4 () +EndOpt + +Options 1,8,0 // Group 'GoAhead' + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=2 + AlwaysBuild=2 + GenAsm=2 + AsmAsm=2 + PublicsOnly=2 + StopCode=11 + CustArgs () + LibMods () + ADSCCFLG { 2,84,85,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (WEBS, UEMF, RTT, __NO_FCNTL=1,USER_MANAGEMENT_SUPPORT) + ADSCUDEF () + ADSCINCD (..\..\net\webserver) + ADSASFLG { 170,42,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () +EndOpt + diff --git a/bsp/stm32/project.ewd b/bsp/stm32/project.ewd new file mode 100644 index 0000000000..48f562856f --- /dev/null +++ b/bsp/stm32/project.ewd @@ -0,0 +1,1299 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 0 + 1 + 1 + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + JLINK_ID + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 0 + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 0 + 1 + 0 + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/bsp/stm32/project.ewp b/bsp/stm32/project.ewp new file mode 100644 index 0000000000..274a87b87e --- /dev/null +++ b/bsp/stm32/project.ewp @@ -0,0 +1,1805 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 7 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + finsh + + $PROJ_DIR$\..\..\finsh\cmd.c + + + $PROJ_DIR$\..\..\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\finsh\shell.c + + + $PROJ_DIR$\..\..\finsh\symbol.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + Library + + $PROJ_DIR$\library\src\stm32f10x_adc.c + + + $PROJ_DIR$\library\src\stm32f10x_bkp.c + + + $PROJ_DIR$\library\src\stm32f10x_can.c + + + $PROJ_DIR$\library\src\stm32f10x_crc.c + + + $PROJ_DIR$\library\src\stm32f10x_dac.c + + + $PROJ_DIR$\library\src\stm32f10x_dbgmcu.c + + + $PROJ_DIR$\library\src\stm32f10x_dma.c + + + $PROJ_DIR$\library\src\stm32f10x_exti.c + + + $PROJ_DIR$\library\src\stm32f10x_flash.c + + + $PROJ_DIR$\library\src\stm32f10x_fsmc.c + + + $PROJ_DIR$\library\src\stm32f10x_gpio.c + + + $PROJ_DIR$\library\src\stm32f10x_i2c.c + + + $PROJ_DIR$\library\src\stm32f10x_iwdg.c + + + $PROJ_DIR$\library\src\stm32f10x_lib.c + + + $PROJ_DIR$\library\src\stm32f10x_nvic.c + + + $PROJ_DIR$\library\src\stm32f10x_pwr.c + + + $PROJ_DIR$\library\src\stm32f10x_rcc.c + + + $PROJ_DIR$\library\src\stm32f10x_rtc.c + + + $PROJ_DIR$\library\src\stm32f10x_sdio.c + + + $PROJ_DIR$\library\src\stm32f10x_spi.c + + + $PROJ_DIR$\library\src\stm32f10x_systick.c + + + $PROJ_DIR$\library\src\stm32f10x_tim.c + + + $PROJ_DIR$\library\src\stm32f10x_usart.c + + + $PROJ_DIR$\library\src\stm32f10x_wwdg.c + + + + Startup + + $PROJ_DIR$\application.c + + + $PROJ_DIR$\board.c + + + $PROJ_DIR$\rtconfig.h + + + $PROJ_DIR$\sdcard.c + + + $PROJ_DIR$\startup.c + + + $PROJ_DIR$\stm32f10x_it.c + + + $PROJ_DIR$\usart.c + + + + STM32 + + $PROJ_DIR$\..\..\libcpu\arm\stm32\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\stm32\cpu.c + + + $PROJ_DIR$\..\..\libcpu\arm\stm32\interrupt.c + + + $PROJ_DIR$\..\..\libcpu\arm\stm32\serial.c + + + $PROJ_DIR$\..\..\libcpu\arm\stm32\stack.c + + + $PROJ_DIR$\..\..\libcpu\arm\stm32\start_iar.c + + + + + diff --git a/bsp/stm32/project.eww b/bsp/stm32/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/stm32/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/rtc.c b/bsp/stm32/rtc.c new file mode 100644 index 0000000000..30adb4cf76 --- /dev/null +++ b/bsp/stm32/rtc.c @@ -0,0 +1,217 @@ +#include +#include "stm32f10x_lib.h" + +static struct rt_device rtc; +static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + if (dev->rx_indicate != RT_NULL) + { + /* Open Interrupt */ + } + + return RT_EOK; +} + +static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + rt_time_t *time; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + time = (rt_time_t *)args; + /* read device */ + *time = RTC_GetCounter(); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + time = (rt_time_t *)args; + + /* Enable PWR and BKP clocks */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + + /* Allow access to BKP Domain */ + PWR_BackupAccessCmd(ENABLE); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + /* Change the current time */ + RTC_SetCounter(*time); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + BKP_WriteBackupRegister(BKP_DR1, 0xA5A5); + } + break; + } + + return RT_EOK; +} + +/******************************************************************************* +* Function Name : RTC_Configuration +* Description : Configures the RTC. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_Configuration(void) +{ + /* Enable PWR and BKP clocks */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + + /* Allow access to BKP Domain */ + PWR_BackupAccessCmd(ENABLE); + + /* Reset Backup Domain */ + BKP_DeInit(); + + /* Enable LSE */ + RCC_LSEConfig(RCC_LSE_ON); + /* Wait till LSE is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select LSE as RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + /* Enable RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC registers synchronization */ + RTC_WaitForSynchro(); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + /* Set RTC prescaler: set RTC period to 1sec */ + RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */ + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); +} + +void rt_hw_rtc_init(void) +{ + rtc.type = RT_Device_Class_RTC; + + if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5) + { + rt_kprintf("rtc is not configured\n"); + rt_kprintf("please configure with set_date and set_time\n"); + RTC_Configuration(); + } + else + { + /* Wait for RTC registers synchronization */ + RTC_WaitForSynchro(); + } + + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rt_rtc_open; + rtc.close = RT_NULL; + rtc.read = rt_rtc_read; + rtc.write = RT_NULL; + rtc.control = rt_rtc_control; + + /* no private */ + rtc.private = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + + return; +} + +#ifdef RT_USING_FINSH +#include +#include +time_t time(time_t* t) +{ + rt_device_t device; + time_t time; + + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + if (t != RT_NULL) *t = time; + } + + return time; +} + +void set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day) +{ + time_t now; + struct tm* ti; + rt_device_t device; + + ti = RT_NULL; + /* get current time */ + time(&now); + + ti = localtime(&now); + if (ti != RT_NULL) + { + ti->tm_year = year - 1900; + ti->tm_mon = month; + ti->tm_mday = day; + } + + now = mktime(ti); + + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_rtc_control(device, RT_DEVICE_CTRL_RTC_SET_TIME, &now); + } +} +FINSH_FUNCTION_EXPORT(set_date, set date) + +void set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second) +{ + time_t now; + struct tm* ti; + rt_device_t device; + + ti = RT_NULL; + /* get current time */ + time(&now); + + ti = localtime(&now); + if (ti != RT_NULL) + { + ti->tm_hour = hour; + ti->tm_min = minute; + ti->tm_sec = second; + } + + now = mktime(ti); + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_rtc_control(device, RT_DEVICE_CTRL_RTC_SET_TIME, &now); + } +} +FINSH_FUNCTION_EXPORT(set_time, set second) + +void list_date() +{ + time_t now; + + time(&now); + rt_kprintf("%s\n", ctime(&now)); +} +FINSH_FUNCTION_EXPORT(list_date, set date) +#endif diff --git a/bsp/stm32/rtc.h b/bsp/stm32/rtc.h new file mode 100644 index 0000000000..29154aef94 --- /dev/null +++ b/bsp/stm32/rtc.h @@ -0,0 +1,6 @@ +#ifndef __RTC_H__ +#define __RTC_H__ + +void rt_hw_rtc_init(void); + +#endif diff --git a/bsp/stm32/rtconfig.h b/bsp/stm32/rtconfig.h new file mode 100644 index 0000000000..aee46399bd --- /dev/null +++ b/bsp/stm32/rtconfig.h @@ -0,0 +1,158 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX*/ +#define RT_THREAD_PRIORITY_MAX 256 + +/* Tick per Second*/ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug*/ +#define RT_DEBUG +#define RT_THREAD_DEBUG + +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook*/ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore*/ +#define RT_USING_SEMAPHORE + +/* Using Mutex*/ +#define RT_USING_MUTEX + +/* Using Event*/ +#define RT_USING_EVENT + +/* Using Faset Event*/ +/* #define RT_USING_FASTEVENT */ + +/* Using MailBox*/ +#define RT_USING_MAILBOX + +/* Using Message Queue*/ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management*/ +#define RT_USING_HEAP + +/* Using Small MM*/ +#define RT_USING_SMALL_MEM + +/* Using SLAB Allocator*/ +/* #define RT_USING_SLAB */ + +/* SECTION: Device System */ +/* Using Device System*/ +#define RT_USING_DEVICE +#define RT_USING_UART1 +// #define RT_USING_UART2 +// #define RT_USING_UART3 + +/* SECTION: Console options */ +/* the buffer size of console*/ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: FinSH shell options */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION + +/* SECTION: a mini libc */ +/* Using mini libc library*/ +/* #define RT_USING_MINILIBC */ + +/* SECTION: C++ support */ +/* Using C++ support*/ +/* #define RT_USING_CPLUSPLUS */ + +/* #define RT_USING_RTGUI */ + +#define RT_USING_DFS +/* SECTION: DFS options */ +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 8 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 8 + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +/* Using lighweight TCP/IP protocol stack*/ +#define RT_USING_LWIP +#define RT_USING_WEBSERVER + +/* Trace LwIP protocol*/ +/* #define RT_LWIP_DEBUG */ + +/* Enable ICMP protocol*/ +#define RT_LWIP_ICMP + +/* Enable IGMP protocol*/ +/* #define RT_LWIP_IGMP */ + +/* Enable UDP protocol*/ +#define RT_LWIP_UDP + +/* Enable TCP protocol*/ +#define RT_LWIP_TCP + +/* the number of simulatenously active TCP connections*/ +#define RT_LWIP_TCP_PCB_NUM 5 + +/* TCP sender buffer space*/ +#define RT_LWIP_TCP_SND_BUF 1500 + +/* Enable SNMP protocol*/ +/* #define RT_LWIP_SNMP */ + +/* Using DHCP*/ +/* #define RT_LWIP_DHCP */ + +#define RT_LWIP_DNS + +/* ip address of target*/ +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 + +/* gateway address of target*/ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target*/ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +/* tcp thread options */ +#define RT_LWIP_TCPTHREAD_PRIORITY 120 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 + +/* ethernet if thread options */ +#define RT_LWIP_ETHTHREAD_PRIORITY 128 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 + +#endif diff --git a/bsp/stm32/sdcard.c b/bsp/stm32/sdcard.c new file mode 100644 index 0000000000..df1442c8c0 --- /dev/null +++ b/bsp/stm32/sdcard.c @@ -0,0 +1,3108 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : sdcard.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the SD Card driver firmware +* functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "sdcard.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define NULL 0 +#define SDIO_STATIC_FLAGS ((u32)0x000005FF) +#define SDIO_CMD0TIMEOUT ((u32)0x00002710) +#define SDIO_FIFO_Address ((u32)0x40018080) + +/* Mask for errors Card Status R1 (OCR Register) */ +#define SD_OCR_ADDR_OUT_OF_RANGE ((u32)0x80000000) +#define SD_OCR_ADDR_MISALIGNED ((u32)0x40000000) +#define SD_OCR_BLOCK_LEN_ERR ((u32)0x20000000) +#define SD_OCR_ERASE_SEQ_ERR ((u32)0x10000000) +#define SD_OCR_BAD_ERASE_PARAM ((u32)0x08000000) +#define SD_OCR_WRITE_PROT_VIOLATION ((u32)0x04000000) +#define SD_OCR_LOCK_UNLOCK_FAILED ((u32)0x01000000) +#define SD_OCR_COM_CRC_FAILED ((u32)0x00800000) +#define SD_OCR_ILLEGAL_CMD ((u32)0x00400000) +#define SD_OCR_CARD_ECC_FAILED ((u32)0x00200000) +#define SD_OCR_CC_ERROR ((u32)0x00100000) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((u32)0x00080000) +#define SD_OCR_STREAM_READ_UNDERRUN ((u32)0x00040000) +#define SD_OCR_STREAM_WRITE_OVERRUN ((u32)0x00020000) +#define SD_OCR_CID_CSD_OVERWRIETE ((u32)0x00010000) +#define SD_OCR_WP_ERASE_SKIP ((u32)0x00008000) +#define SD_OCR_CARD_ECC_DISABLED ((u32)0x00004000) +#define SD_OCR_ERASE_RESET ((u32)0x00002000) +#define SD_OCR_AKE_SEQ_ERROR ((u32)0x00000008) +#define SD_OCR_ERRORBITS ((u32)0xFDFFE008) + +/* Masks for R6 Response */ +#define SD_R6_GENERAL_UNKNOWN_ERROR ((u32)0x00002000) +#define SD_R6_ILLEGAL_CMD ((u32)0x00004000) +#define SD_R6_COM_CRC_FAILED ((u32)0x00008000) + +#define SD_VOLTAGE_WINDOW_SD ((u32)0x80100000) +#define SD_HIGH_CAPACITY ((u32)0x40000000) +#define SD_STD_CAPACITY ((u32)0x00000000) +#define SD_CHECK_PATTERN ((u32)0x000001AA) + +#define SD_MAX_VOLT_TRIAL ((u32)0x0000FFFF) +#define SD_ALLZERO ((u32)0x00000000) + +#define SD_WIDE_BUS_SUPPORT ((u32)0x00040000) +#define SD_SINGLE_BUS_SUPPORT ((u32)0x00010000) +#define SD_CARD_LOCKED ((u32)0x02000000) +#define SD_CARD_PROGRAMMING ((u32)0x00000007) +#define SD_CARD_RECEIVING ((u32)0x00000006) +#define SD_DATATIMEOUT ((u32)0x000FFFFF) +#define SD_0TO7BITS ((u32)0x000000FF) +#define SD_8TO15BITS ((u32)0x0000FF00) +#define SD_16TO23BITS ((u32)0x00FF0000) +#define SD_24TO31BITS ((u32)0xFF000000) +#define SD_MAX_DATA_LENGTH ((u32)0x01FFFFFF) + +#define SD_HALFFIFO ((u32)0x00000008) +#define SD_HALFFIFOBYTES ((u32)0x00000020) + +/* Command Class Supported */ +#define SD_CCCC_LOCK_UNLOCK ((u32)0x00000080) +#define SD_CCCC_WRITE_PROT ((u32)0x00000040) +#define SD_CCCC_ERASE ((u32)0x00000020) + +/* Following commands are SD Card Specific commands. + SDIO_APP_CMD should be sent before sending these commands. */ +#define SDIO_SEND_IF_COND ((u32)0x00000008) + +#define SDIO_INIT_CLK_DIV ((u8)0xB2) +#define SDIO_TRANSFER_CLK_DIV ((u8)0x1) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static u32 CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; +static u32 CSD_Tab[4], CID_Tab[4], RCA = 0; +static u32 DeviceMode = SD_DMA_MODE; +static u32 TotalNumberOfBytes = 0, StopCondition = 0; +u32 *SrcBuffer, *DestBuffer; +volatile SD_Error TransferError = SD_OK; +vu32 TransferEnd = 0; +vu32 NumberOfBytes = 0; +SDIO_InitTypeDef SDIO_InitStructure; +SDIO_CmdInitTypeDef SDIO_CmdInitStructure; +SDIO_DataInitTypeDef SDIO_DataInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +static SD_Error CmdError(void); +static SD_Error CmdResp1Error(u8 cmd); +static SD_Error CmdResp7Error(void); +static SD_Error CmdResp3Error(void); +static SD_Error CmdResp2Error(void); +static SD_Error CmdResp6Error(u8 cmd, u16 *prca); +static SD_Error SDEnWideBus(FunctionalState NewState); +static SD_Error IsCardProgramming(u8 *pstatus); +static SD_Error FindSCR(u16 rca, u32 *pscr); +static u8 convert_from_bytes_to_power_of_two(u16 NumberOfBytes); +static void GPIO_Configuration(void); +static void DMA_TxConfiguration(u32 *BufferSRC, u32 BufferSize); +static void DMA_RxConfiguration(u32 *BufferDST, u32 BufferSize); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SD_Init +* Description : Initializes the SD Card and put it into StandBy State (Ready +* for data transfer). +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_Init(void) +{ + SD_Error errorstatus = SD_OK; + + /* Configure SDIO interface GPIO */ + GPIO_Configuration(); + + /* Enable the SDIO AHB Clock */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, ENABLE); + + /* Enable the DMA2 Clock */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE); + + SDIO_DeInit(); + + errorstatus = SD_PowerON(); + + if (errorstatus != SD_OK) + { + /* CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + errorstatus = SD_InitializeCards(); + + if (errorstatus != SD_OK) + { + /* CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + /* Configure the SDIO peripheral */ + /* HCLK = 72 MHz, SDIOCLK = 72 MHz, SDIO_CK = HCLK/(2 + 1) = 24 MHz */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_PowerON +* Description : Enquires cards about their operating voltage and configures +* clock controls. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_PowerON(void) +{ + SD_Error errorstatus = SD_OK; + u32 response = 0, count = 0; + bool validvoltage = FALSE; + u32 SDType = SD_STD_CAPACITY; + + /* Power ON Sequence -------------------------------------------------------*/ + /* Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV; /* HCLK = 72MHz, SDIOCLK = 72MHz, SDIO_CK = HCLK/(178 + 2) = 400 KHz */ + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + + /* Set Power State to ON */ + SDIO_SetPowerState(SDIO_PowerState_ON); + + /* Enable SDIO Clock */ + SDIO_ClockCmd(ENABLE); + + /* CMD0: GO_IDLE_STATE -------------------------------------------------------*/ + /* No CMD response required */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_GO_IDLE_STATE; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdError(); + + if (errorstatus != SD_OK) + { + /* CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + /* CMD8: SEND_IF_COND --------------------------------------------------------*/ + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp7Error(); + + if (errorstatus == SD_OK) + { + CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /* SD Card 2.0 */ + SDType = SD_HIGH_CAPACITY; + } + else + { + /* CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SDIO_APP_CMD); + } + /* CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + /* If errorstatus is Command TimeOut, it is a MMC card */ + /* If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + if (errorstatus == SD_OK) + { + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) + { + + /* SEND CMD55 APP_CMD with RCA as 0 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SD_APP_OP_COND; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp3Error(); + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + response = SDIO_GetResponse(SDIO_RESP1); + validvoltage = (bool) (((response >> 31) == 1) ? 1 : 0); + count++; + } + if (count >= SD_MAX_VOLT_TRIAL) + { + errorstatus = SD_INVALID_VOLTRANGE; + return(errorstatus); + } + + if (response &= SD_HIGH_CAPACITY) + { + CardType = SDIO_HIGH_CAPACITY_SD_CARD; + } + + }/* else MMC Card */ + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_PowerOFF +* Description : Turns the SDIO output signals off. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_PowerOFF(void) +{ + SD_Error errorstatus = SD_OK; + + /* Set Power State to OFF */ + SDIO_SetPowerState(SDIO_PowerState_OFF); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_InitializeCards +* Description : Intialises all cards or single card as the case may be. +* Card(s) come into standby state. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_InitializeCards(void) +{ + SD_Error errorstatus = SD_OK; + u16 rca = 0x01; + + if (SDIO_GetPowerState() == SDIO_PowerState_OFF) + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + + if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) + { + /* Send CMD2 ALL_SEND_CID */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_ALL_SEND_CID; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp2Error(); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1); + CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2); + CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3); + CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4); + } + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType) + || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_REL_ADDR; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp6Error(SDIO_SET_REL_ADDR, &rca); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + } + + if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) + { + RCA = rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (u32)(rca << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_CSD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp2Error(); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1); + CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2); + CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3); + CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4); + } + + errorstatus = SD_OK; /* All cards get intialized */ + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_GetCardInfo +* Description : Returns information about specific card. +* Input : cardinfo : pointer to a SD_CardInfo structure +* that contains all SD card information. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) +{ + SD_Error errorstatus = SD_OK; + u8 tmp = 0; + + cardinfo->CardType = (u8)CardType; + cardinfo->RCA = (u16)RCA; + + /* Byte 0 */ + tmp = (u8)((CSD_Tab[0] & 0xFF000000) >> 24); + cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6; + cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; + cardinfo->SD_csd.Reserved1 = tmp & 0x03; + + /* Byte 1 */ + tmp = (u8)((CSD_Tab[0] & 0x00FF0000) >> 16); + cardinfo->SD_csd.TAAC = tmp; + + /* Byte 2 */ + tmp = (u8)((CSD_Tab[0] & 0x0000FF00) >> 8); + cardinfo->SD_csd.NSAC = tmp; + + /* Byte 3 */ + tmp = (u8)(CSD_Tab[0] & 0x000000FF); + cardinfo->SD_csd.MaxBusClkFrec = tmp; + + /* Byte 4 */ + tmp = (u8)((CSD_Tab[1] & 0xFF000000) >> 24); + cardinfo->SD_csd.CardComdClasses = tmp << 4; + + /* Byte 5 */ + tmp = (u8)((CSD_Tab[1] & 0x00FF0000) >> 16); + cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; + cardinfo->SD_csd.RdBlockLen = tmp & 0x0F; + + /* Byte 6 */ + tmp = (u8)((CSD_Tab[1] & 0x0000FF00) >> 8); + cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7; + cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; + cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; + cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4; + cardinfo->SD_csd.Reserved2 = 0; /* Reserved */ + + if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + { + cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /* Byte 7 */ + tmp = (u8)(CSD_Tab[1] & 0x000000FF); + cardinfo->SD_csd.DeviceSize |= (tmp) << 2; + + /* Byte 8 */ + tmp = (u8)((CSD_Tab[2] & 0xFF000000) >> 24); + + cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /* Byte 9 */ + tmp = (u8)((CSD_Tab[2] & 0x00FF0000) >> 16); + cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + + /* Byte 10 */ + tmp = (u8)((CSD_Tab[2] & 0x0000FF00) >> 8); + cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; + cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); + cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); + cardinfo->CardCapacity *= cardinfo->CardBlockSize; + } + else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + /* Byte 7 */ + tmp = (u8)(CSD_Tab[1] & 0x000000FF); + cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /* Byte 8 */ + tmp = (u8)((CSD_Tab[2] & 0xFF000000) >> 24); + + cardinfo->SD_csd.DeviceSize |= (tmp << 8); + + /* Byte 9 */ + tmp = (u8)((CSD_Tab[2] & 0x00FF0000) >> 16); + + cardinfo->SD_csd.DeviceSize |= (tmp); + + /* Byte 10 */ + tmp = (u8)((CSD_Tab[2] & 0x0000FF00) >> 8); + + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; + cardinfo->CardBlockSize = 512; + } + + + cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /* Byte 11 */ + tmp = (u8)(CSD_Tab[2] & 0x000000FF); + cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /* Byte 12 */ + tmp = (u8)((CSD_Tab[3] & 0xFF000000) >> 24); + cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /* Byte 13 */ + tmp = (u8)((CSD_Tab[3] & 0x00FF0000) >> 16); + cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + cardinfo->SD_csd.Reserved3 = 0; + cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01); + + /* Byte 14 */ + tmp = (u8)((CSD_Tab[3] & 0x0000FF00) >> 8); + cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; + cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; + cardinfo->SD_csd.ECC = (tmp & 0x03); + + /* Byte 15 */ + tmp = (u8)(CSD_Tab[3] & 0x000000FF); + cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; + cardinfo->SD_csd.Reserved4 = 1; + + + /* Byte 0 */ + tmp = (u8)((CID_Tab[0] & 0xFF000000) >> 24); + cardinfo->SD_cid.ManufacturerID = tmp; + + /* Byte 1 */ + tmp = (u8)((CID_Tab[0] & 0x00FF0000) >> 16); + cardinfo->SD_cid.OEM_AppliID = tmp << 8; + + /* Byte 2 */ + tmp = (u8)((CID_Tab[0] & 0x000000FF00) >> 8); + cardinfo->SD_cid.OEM_AppliID |= tmp; + + /* Byte 3 */ + tmp = (u8)(CID_Tab[0] & 0x000000FF); + cardinfo->SD_cid.ProdName1 = tmp << 24; + + /* Byte 4 */ + tmp = (u8)((CID_Tab[1] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdName1 |= tmp << 16; + + /* Byte 5 */ + tmp = (u8)((CID_Tab[1] & 0x00FF0000) >> 16); + cardinfo->SD_cid.ProdName1 |= tmp << 8; + + /* Byte 6 */ + tmp = (u8)((CID_Tab[1] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ProdName1 |= tmp; + + /* Byte 7 */ + tmp = (u8)(CID_Tab[1] & 0x000000FF); + cardinfo->SD_cid.ProdName2 = tmp; + + /* Byte 8 */ + tmp = (u8)((CID_Tab[2] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdRev = tmp; + + /* Byte 9 */ + tmp = (u8)((CID_Tab[2] & 0x00FF0000) >> 16); + cardinfo->SD_cid.ProdSN = tmp << 24; + + /* Byte 10 */ + tmp = (u8)((CID_Tab[2] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ProdSN |= tmp << 16; + + /* Byte 11 */ + tmp = (u8)(CID_Tab[2] & 0x000000FF); + cardinfo->SD_cid.ProdSN |= tmp << 8; + + /* Byte 12 */ + tmp = (u8)((CID_Tab[3] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdSN |= tmp; + + /* Byte 13 */ + tmp = (u8)((CID_Tab[3] & 0x00FF0000) >> 16); + cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /* Byte 14 */ + tmp = (u8)((CID_Tab[3] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ManufactDate |= tmp; + + /* Byte 15 */ + tmp = (u8)(CID_Tab[3] & 0x000000FF); + cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; + cardinfo->SD_cid.Reserved2 = 1; + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_EnableWideBusOperation +* Description : Enables wide bus opeartion for the requeseted card if +* supported by card. +* Input : WideMode: Specifies the SD card wide bus mode. +* This parameter can be one of the following values: +* - SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) +* - SDIO_BusWide_4b: 4-bit data transfer +* - SDIO_BusWide_1b: 1-bit data transfer +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_EnableWideBusOperation(u32 WideMode) +{ + SD_Error errorstatus = SD_OK; + + /* MMC Card doesn't support this feature */ + if (SDIO_MULTIMEDIA_CARD == CardType) + { + errorstatus = SD_UNSUPPORTED_FEATURE; + return(errorstatus); + } + else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + if (SDIO_BusWide_8b == WideMode) + { + errorstatus = SD_UNSUPPORTED_FEATURE; + return(errorstatus); + } + else if (SDIO_BusWide_4b == WideMode) + { + errorstatus = SDEnWideBus(ENABLE); + + if (SD_OK == errorstatus) + { + /* Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + } + } + else + { + errorstatus = SDEnWideBus(DISABLE); + + if (SD_OK == errorstatus) + { + /* Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + } + } + } + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_SetDeviceMode +* Description : Sets device mode whether to operate in Polling, Interrupt or +* DMA mode. +* Input : Mode: Specifies the Data Transfer mode. +* This parameter can be one of the following values: +* - SD_DMA_MODE: Data transfer using DMA. +* - SD_INTERRUPT_MODE: Data transfer using interrupts. +* - SD_POLLING_MODE: Data transfer using flags. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_SetDeviceMode(u32 Mode) +{ + SD_Error errorstatus = SD_OK; + + if ((Mode == SD_DMA_MODE) || (Mode == SD_INTERRUPT_MODE) || (Mode == SD_POLLING_MODE)) + { + DeviceMode = Mode; + } + else + { + errorstatus = SD_INVALID_PARAMETER; + } + return(errorstatus); + +} + +/******************************************************************************* +* Function Name : SD_SelectDeselect +* Description : Selects od Deselects the corresponding card. +* Input : addr: Address of the Card to be selected. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_SelectDeselect(u32 addr) +{ + SD_Error errorstatus = SD_OK; + + /* Send CMD7 SDIO_SEL_DESEL_CARD */ + SDIO_CmdInitStructure.SDIO_Argument = addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEL_DESEL_CARD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SEL_DESEL_CARD); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_ReadBlock +* Description : Allows to read one block from a specified address in a card. +* Input : - addr: Address from where data are to be read. +* - readbuff: pointer to the buffer that will contain the +* received data +* - blocksize: the SD card Data block size. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_ReadBlock(u32 addr, u32 *readbuff, u16 BlockSize) +{ + SD_Error errorstatus = SD_OK; + u32 count = 0, *tempbuff = readbuff; + u8 power = 0; + + if (NULL == readbuff) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + TransferError = SD_OK; + TransferEnd = 0; + TotalNumberOfBytes = 0; + + /* Clear all DPSM configuration */ + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 0; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Disable; + SDIO_DataConfig(&SDIO_DataInitStructure); + SDIO_DMACmd(DISABLE); + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + addr /= 512; + } + if ((BlockSize > 0) && (BlockSize <= 2048) && ((BlockSize & (BlockSize - 1)) == 0)) + { + power = convert_from_bytes_to_power_of_two(BlockSize); + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + } + else + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (u32) power << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + TotalNumberOfBytes = BlockSize; + StopCondition = 0; + DestBuffer = readbuff; + + /* Send CMD17 READ_SINGLE_BLOCK */ + SDIO_CmdInitStructure.SDIO_Argument = (u32)addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_READ_SINGLE_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_READ_SINGLE_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + /* In case of single block transfer, no need of stop transfer at all.*/ + if (DeviceMode == SD_POLLING_MODE) + { + /* Polling mode */ + while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) + { + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDIO_ReadData(); + } + tempbuff += 8; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) + { + *tempbuff = SDIO_ReadData(); + tempbuff++; + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + } + else if (DeviceMode == SD_INTERRUPT_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR, ENABLE); + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + else if (DeviceMode == SD_DMA_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + DMA_RxConfiguration(readbuff, BlockSize); + while (DMA_GetFlagStatus(DMA2_FLAG_TC4) == RESET) + {} + } + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_ReadMultiBlocks +* Description : Allows to read blocks from a specified address in a card. +* Input : - addr: Address from where data are to be read. +* - readbuff: pointer to the buffer that will contain the +* received data. +* - BlockSize: the SD card Data block size. +* - NumberOfBlocks: number of blocks to be read. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_ReadMultiBlocks(u32 addr, u32 *readbuff, u16 BlockSize, u32 NumberOfBlocks) +{ + SD_Error errorstatus = SD_OK; + u32 count = 0, *tempbuff = readbuff; + u8 power = 0; + + if (NULL == readbuff) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + TransferError = SD_OK; + TransferEnd = 0; + TotalNumberOfBytes = 0; + + /* Clear all DPSM configuration */ + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 0; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Disable; + SDIO_DataConfig(&SDIO_DataInitStructure); + SDIO_DMACmd(DISABLE); + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + addr /= 512; + } + + if ((BlockSize > 0) && (BlockSize <= 2048) && (0 == (BlockSize & (BlockSize - 1)))) + { + power = convert_from_bytes_to_power_of_two(BlockSize); + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + } + else + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + if (NumberOfBlocks > 1) + { + /* Common to all modes */ + if (NumberOfBlocks * BlockSize > SD_MAX_DATA_LENGTH) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + TotalNumberOfBytes = NumberOfBlocks * BlockSize; + StopCondition = 1; + DestBuffer = readbuff; + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (u32) power << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /* Send CMD18 READ_MULT_BLOCK with argument data address */ + SDIO_CmdInitStructure.SDIO_Argument = (u32)addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_READ_MULT_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_READ_MULT_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + if (DeviceMode == SD_POLLING_MODE) + { + /* Polling mode */ + while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DATAEND | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) + { + for (count = 0; count < SD_HALFFIFO; count++) + { + *(tempbuff + count) = SDIO_ReadData(); + } + tempbuff += SD_HALFFIFO; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) + { + *tempbuff = SDIO_ReadData(); + tempbuff++; + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DATAEND) != RESET) + { + /* In Case Of SD-CARD Send Command STOP_TRANSMISSION */ + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType)) + { + /* Send CMD12 STOP_TRANSMISSION */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_STOP_TRANSMISSION; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_STOP_TRANSMISSION); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + } + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + } + else if (DeviceMode == SD_INTERRUPT_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR, ENABLE); + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + else if (DeviceMode == SD_DMA_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + DMA_RxConfiguration(readbuff, (NumberOfBlocks * BlockSize)); + while (DMA_GetFlagStatus(DMA2_FLAG_TC4) == RESET) + {} + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + } + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_WriteBlock +* Description : Allows to write one block starting from a specified address +* in a card. +* Input : - addr: Address from where data are to be read. +* - writebuff: pointer to the buffer that contain the data to be +* transferred. +* - BlockSize: the SD card Data block size. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_WriteBlock(u32 addr, u32 *writebuff, u16 BlockSize) +{ + SD_Error errorstatus = SD_OK; + u8 power = 0, cardstate = 0; + u32 timeout = 0, bytestransferred = 0; + u32 cardstatus = 0, count = 0, restwords = 0; + u32 *tempbuff = writebuff; + + if (writebuff == NULL) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + TransferError = SD_OK; + TransferEnd = 0; + TotalNumberOfBytes = 0; + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 0; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Disable; + SDIO_DataConfig(&SDIO_DataInitStructure); + SDIO_DMACmd(DISABLE); + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + addr /= 512; + } + + /* Set the block size, both on controller and card */ + if ((BlockSize > 0) && (BlockSize <= 2048) && ((BlockSize & (BlockSize - 1)) == 0)) + { + power = convert_from_bytes_to_power_of_two(BlockSize); + + SDIO_CmdInitStructure.SDIO_Argument = (u32) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + else + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + /* Wait till card is ready for data Added */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) (RCA << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SEND_STATUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + cardstatus = SDIO_GetResponse(SDIO_RESP1); + + timeout = SD_DATATIMEOUT; + + while (((cardstatus & 0x00000100) == 0) && (timeout > 0)) + { + timeout--; + SDIO_CmdInitStructure.SDIO_Argument = (u32) (RCA << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SEND_STATUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + cardstatus = SDIO_GetResponse(SDIO_RESP1); + } + + if (timeout == 0) + { + return(SD_ERROR); + } + + /* Send CMD24 WRITE_SINGLE_BLOCK */ + SDIO_CmdInitStructure.SDIO_Argument = addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_WRITE_SINGLE_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_WRITE_SINGLE_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + TotalNumberOfBytes = BlockSize; + StopCondition = 0; + SrcBuffer = writebuff; + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (u32) power << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /* In case of single data block transfer no need of stop command at all */ + if (DeviceMode == SD_POLLING_MODE) + { + while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET) + { + if ((TotalNumberOfBytes - bytestransferred) < 32) + { + restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes - bytestransferred) / 4 + 1); + + for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4) + { + SDIO_WriteData(*tempbuff); + } + } + else + { + for (count = 0; count < 8; count++) + { + SDIO_WriteData(*(tempbuff + count)); + } + tempbuff += 8; + bytestransferred += 32; + } + } + } + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_TXUNDERR); + errorstatus = SD_TX_UNDERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + } + else if (DeviceMode == SD_INTERRUPT_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR, ENABLE); + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + else if (DeviceMode == SD_DMA_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR, ENABLE); + DMA_TxConfiguration(writebuff, BlockSize); + SDIO_DMACmd(ENABLE); + while (DMA_GetFlagStatus(DMA2_FLAG_TC4) == RESET) + {} + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /* Wait till the card is in programming state */ + errorstatus = IsCardProgramming(&cardstate); + + while ((errorstatus == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + { + errorstatus = IsCardProgramming(&cardstate); + } + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_WriteMultiBlocks +* Description : Allows to write blocks starting from a specified address in +* a card. +* Input : - addr: Address from where data are to be read. +* - writebuff: pointer to the buffer that contain the data to be +* transferred. +* - BlockSize: the SD card Data block size. +* - NumberOfBlocks: number of blocks to be written. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_WriteMultiBlocks(u32 addr, u32 *writebuff, u16 BlockSize, u32 NumberOfBlocks) +{ + SD_Error errorstatus = SD_OK; + u8 power = 0, cardstate = 0; + u32 bytestransferred = 0; + u32 count = 0, restwords = 0; + u32 *tempbuff = writebuff; + + if (writebuff == NULL) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + TransferError = SD_OK; + TransferEnd = 0; + TotalNumberOfBytes = 0; + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 0; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Disable; + SDIO_DataConfig(&SDIO_DataInitStructure); + SDIO_DMACmd(DISABLE); + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + addr /= 512; + } + + /* Set the block size, both on controller and card */ + if ((BlockSize > 0) && (BlockSize <= 2048) && ((BlockSize & (BlockSize - 1)) == 0)) + { + power = convert_from_bytes_to_power_of_two(BlockSize); + + SDIO_CmdInitStructure.SDIO_Argument = (u32) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + else + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + /* Wait till card is ready for data Added */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) (RCA << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SEND_STATUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + if (NumberOfBlocks > 1) + { + /* Common to all modes */ + if (NumberOfBlocks * BlockSize > SD_MAX_DATA_LENGTH) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /* To improve performance */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) (RCA << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + /* To improve performance */ + SDIO_CmdInitStructure.SDIO_Argument = (u32)NumberOfBlocks; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCK_COUNT; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCK_COUNT); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + + /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ + SDIO_CmdInitStructure.SDIO_Argument = (u32)addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_WRITE_MULT_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_WRITE_MULT_BLOCK); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + TotalNumberOfBytes = NumberOfBlocks * BlockSize; + StopCondition = 1; + SrcBuffer = writebuff; + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (u32) power << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + if (DeviceMode == SD_POLLING_MODE) + { + while (!(SDIO->STA & (SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DATAEND | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET) + { + if (!((TotalNumberOfBytes - bytestransferred) < SD_HALFFIFOBYTES)) + { + for (count = 0; count < SD_HALFFIFO; count++) + { + SDIO_WriteData(*(tempbuff + count)); + } + tempbuff += SD_HALFFIFO; + bytestransferred += SD_HALFFIFOBYTES; + } + else + { + restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : + ((TotalNumberOfBytes - bytestransferred) / 4 + 1); + + for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4) + { + SDIO_WriteData(*tempbuff); + } + } + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_TXUNDERR); + errorstatus = SD_TX_UNDERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DATAEND) != RESET) + { + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /* Send CMD12 STOP_TRANSMISSION */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_STOP_TRANSMISSION; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SDIO_STOP_TRANSMISSION); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + } + } + else if (DeviceMode == SD_INTERRUPT_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_TXFIFOHE | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR, ENABLE); + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + else if (DeviceMode == SD_DMA_MODE) + { + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + DMA_TxConfiguration(writebuff, (NumberOfBlocks * BlockSize)); + while (DMA_GetFlagStatus(DMA2_FLAG_TC4) == RESET) + {} + while ((TransferEnd == 0) && (TransferError == SD_OK)) + {} + if (TransferError != SD_OK) + { + return(TransferError); + } + } + } + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /* Wait till the card is in programming state */ + errorstatus = IsCardProgramming(&cardstate); + + while ((errorstatus == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + { + errorstatus = IsCardProgramming(&cardstate); + } + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_GetTransferState +* Description : Gets the cuurent data transfer state. +* Input : None +* Output : None +* Return : SDTransferState: Data Transfer state. +* This value can be: +* - SD_NO_TRANSFER: No data transfer is acting +* - SD_TRANSFER_IN_PROGRESS: Data transfer is acting +*******************************************************************************/ +SDTransferState SD_GetTransferState(void) +{ + if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT)) + { + return(SD_TRANSFER_IN_PROGRESS); + } + else + { + return(SD_NO_TRANSFER); + } +} + +/******************************************************************************* +* Function Name : SD_StopTransfer +* Description : Aborts an ongoing data transfer. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_StopTransfer(void) +{ + SD_Error errorstatus = SD_OK; + + /* Send CMD12 STOP_TRANSMISSION */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_STOP_TRANSMISSION; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_STOP_TRANSMISSION); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_Erase +* Description : Allows to erase memory area specified for the given card. +* Input : - startaddr: the start address. +* - endaddr: the end address. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_Erase(u32 startaddr, u32 endaddr) +{ + SD_Error errorstatus = SD_OK; + u32 delay = 0; + vu32 maxdelay = 0; + u8 cardstate = 0; + + /* Check if the card coomnd class supports erase command */ + if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0) + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + + maxdelay = 72000 / ((SDIO->CLKCR & 0xFF) + 2); + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + startaddr /= 512; + endaddr /= 512; + } + + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + SDIO_CmdInitStructure.SDIO_Argument = startaddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SD_ERASE_GRP_START; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SD_ERASE_GRP_START); + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + SDIO_CmdInitStructure.SDIO_Argument = endaddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SD_ERASE_GRP_END; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SD_ERASE_GRP_END); + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + + /* Send CMD38 ERASE */ + SDIO_CmdInitStructure.SDIO_Argument = 0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_ERASE; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_ERASE); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + for (delay = 0; delay < maxdelay; delay++) + {} + + /* Wait till the card is in programming state */ + errorstatus = IsCardProgramming(&cardstate); + + while ((errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) + { + errorstatus = IsCardProgramming(&cardstate); + } + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_SendStatus +* Description : Returns the current card's status. +* Input : pcardstatus: pointer to the buffer that will contain the SD +* card status (Card Status register). +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_SendStatus(u32 *pcardstatus) +{ + SD_Error errorstatus = SD_OK; + + if (pcardstatus == NULL) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + SDIO_CmdInitStructure.SDIO_Argument = (u32) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SDIO_SEND_STATUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + *pcardstatus = SDIO_GetResponse(SDIO_RESP1); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_SendSDStatus +* Description : Returns the current SD card's status. +* Input : psdstatus: pointer to the buffer that will contain the SD +* card status (SD Status register). +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_SendSDStatus(u32 *psdstatus) +{ + SD_Error errorstatus = SD_OK; + u32 count = 0; + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + /* Set block size for card if it is not equal to current block size for card. */ + SDIO_CmdInitStructure.SDIO_Argument = 64; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /* CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 64; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + + /* Send ACMD13 SD_APP_STAUS with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = 0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SD_APP_STAUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SDIO_SD_APP_STAUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) + { + for (count = 0; count < 8; count++) + { + *(psdstatus + count) = SDIO_ReadData(); + } + psdstatus += 8; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + + while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) + { + *psdstatus = SDIO_ReadData(); + psdstatus++; + } + + /* Clear all the static status flags*/ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + psdstatus -= 16; + for (count = 0; count < 16; count++) + { + psdstatus[count] = ((psdstatus[count] & SD_0TO7BITS) << 24) |((psdstatus[count] & SD_8TO15BITS) << 8) | + ((psdstatus[count] & SD_16TO23BITS) >> 8) |((psdstatus[count] & SD_24TO31BITS) >> 24); + } + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SD_ProcessIRQSrc +* Description : Allows to process all the interrupts that are high. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +SD_Error SD_ProcessIRQSrc(void) +{ + u32 count = 0, restwords = 0; + + if (DeviceMode == SD_INTERRUPT_MODE) + { + if (SDIO_GetITStatus(SDIO_IT_RXFIFOHF) != RESET) + { + for (count = 0; count < SD_HALFFIFO; count++) + { + *(DestBuffer + count) = SDIO_ReadData(); + } + DestBuffer += SD_HALFFIFO; + NumberOfBytes += SD_HALFFIFOBYTES; + } + else if (SDIO_GetITStatus(SDIO_IT_TXFIFOHE) != RESET) + { + if ((TotalNumberOfBytes - NumberOfBytes) < SD_HALFFIFOBYTES) + { + restwords = ((TotalNumberOfBytes - NumberOfBytes) % 4 == 0) ? + ((TotalNumberOfBytes - NumberOfBytes) / 4) : + ((TotalNumberOfBytes - NumberOfBytes) / 4 + 1); + + for (count = 0; count < restwords; count++, SrcBuffer++, NumberOfBytes += 4) + { + SDIO_WriteData(*SrcBuffer); + } + } + else + { + for (count = 0; count < SD_HALFFIFO; count++) + { + SDIO_WriteData(*(SrcBuffer + count)); + } + + SrcBuffer += SD_HALFFIFO; + NumberOfBytes += SD_HALFFIFOBYTES; + } + } + } + + if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET) + { + if (DeviceMode != SD_DMA_MODE) + { + while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (NumberOfBytes < TotalNumberOfBytes)) + { + *DestBuffer = SDIO_ReadData(); + DestBuffer++; + NumberOfBytes += 4; + } + } + + if (StopCondition == 1) + { + TransferError = SD_StopTransfer(); + } + else + { + TransferError = SD_OK; + } + SDIO_ClearITPendingBit(SDIO_IT_DATAEND); + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + TransferEnd = 1; + NumberOfBytes = 0; + return(TransferError); + } + + if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL); + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + NumberOfBytes = 0; + TransferError = SD_DATA_CRC_FAIL; + return(SD_DATA_CRC_FAIL); + } + + if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT); + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + NumberOfBytes = 0; + TransferError = SD_DATA_TIMEOUT; + return(SD_DATA_TIMEOUT); + } + + if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_RXOVERR); + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + NumberOfBytes = 0; + TransferError = SD_RX_OVERRUN; + return(SD_RX_OVERRUN); + } + + if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR); + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + NumberOfBytes = 0; + TransferError = SD_TX_UNDERRUN; + return(SD_TX_UNDERRUN); + } + + if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_STBITERR); + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + NumberOfBytes = 0; + TransferError = SD_START_BIT_ERR; + return(SD_START_BIT_ERR); + } + + return(SD_OK); +} + +/******************************************************************************* +* Function Name : CmdError +* Description : Checks for error conditions for CMD0. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error CmdError(void) +{ + SD_Error errorstatus = SD_OK; + u32 timeout; + + timeout = SDIO_CMD0TIMEOUT; /* 10000 */ + + while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET)) + { + timeout--; + } + + if (timeout == 0) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + return(errorstatus); + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : CmdResp7Error +* Description : Checks for error conditions for R7. +* response. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error CmdResp7Error(void) +{ + SD_Error errorstatus = SD_OK; + u32 status; + u32 timeout = SDIO_CMD0TIMEOUT; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0)) + { + timeout--; + status = SDIO->STA; + } + + if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT)) + { + /* Card is not V2.0 complient or card does not support the set voltage range */ + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + + if (status & SDIO_FLAG_CMDREND) + { + /* Card is SD V2.0 compliant */ + errorstatus = SD_OK; + SDIO_ClearFlag(SDIO_FLAG_CMDREND); + return(errorstatus); + } + return(errorstatus); +} + +/******************************************************************************* +* Function Name : CmdResp1Error +* Description : Checks for error conditions for R1. +* response +* Input : cmd: The sent command index. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error CmdResp1Error(u8 cmd) +{ + SD_Error errorstatus = SD_OK; + u32 status; + u32 response_r1; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /* Check response received is of desired command */ + if (SDIO_GetCommandResponse() != cmd) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /* We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return(errorstatus); + } + + if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if (response_r1 & SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if (response_r1 & SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if (response_r1 & SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if (response_r1 & SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if (response_r1 & SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if (response_r1 & SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (response_r1 & SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if (response_r1 & SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if (response_r1 & SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if (response_r1 & SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if (response_r1 & SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if (response_r1 & SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + return(errorstatus); +} + +/******************************************************************************* +* Function Name : CmdResp3Error +* Description : Checks for error conditions for R3 (OCR). +* response. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error CmdResp3Error(void) +{ + SD_Error errorstatus = SD_OK; + u32 status; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + return(errorstatus); +} + +/******************************************************************************* +* Function Name : CmdResp2Error +* Description : Checks for error conditions for R2 (CID or CSD). +* response. +* Input : None +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error CmdResp2Error(void) +{ + SD_Error errorstatus = SD_OK; + u32 status; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : CmdResp6Error +* Description : Checks for error conditions for R6 (RCA). +* response. +* Input : - cmd: The sent command index. +* - prca: pointer to the variable that will contain the SD +* card relative address RCA. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error CmdResp6Error(u8 cmd, u16 *prca) +{ + SD_Error errorstatus = SD_OK; + u32 status; + u32 response_r1; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /* Check response received is of desired command */ + if (SDIO_GetCommandResponse() != cmd) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) + { + *prca = (u16) (response_r1 >> 16); + return(errorstatus); + } + + if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (response_r1 & SD_R6_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (response_r1 & SD_R6_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : SDEnWideBus +* Description : Enables or disables the SDIO wide bus mode. +* Input : NewState: new state of the SDIO wide bus mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error SDEnWideBus(FunctionalState NewState) +{ + SD_Error errorstatus = SD_OK; + + u32 scr[2] = {0, 0}; + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + /* Get SCR Register */ + errorstatus = FindSCR(RCA, scr); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /* If wide bus operation to be enabled */ + if (NewState == ENABLE) + { + /* If requested card supports wide bus operation */ + if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = (u32) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + SDIO_CmdInitStructure.SDIO_Argument = 0x2; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_SD_SET_BUSWIDTH; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_APP_SD_SET_BUSWIDTH); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + return(errorstatus); + } + else + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + } /* If wide bus operation to be disabled */ + else + { + /* If requested card supports 1 bit mode operation */ + if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = (u32) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_SD_SET_BUSWIDTH; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_APP_SD_SET_BUSWIDTH); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + return(errorstatus); + } + else + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + } +} + +/******************************************************************************* +* Function Name : IsCardProgramming +* Description : Checks if the SD card is in programming state. +* Input : pstatus: pointer to the variable that will contain the SD +* card state. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error IsCardProgramming(u8 *pstatus) +{ + SD_Error errorstatus = SD_OK; + vu32 respR1 = 0, status = 0; + + SDIO_CmdInitStructure.SDIO_Argument = (u32) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + status = SDIO->STA; + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + status = (u32)SDIO_GetCommandResponse(); + + /* Check response received is of desired command */ + if (status != SDIO_SEND_STATUS) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + + /* We have received response, retrieve it for analysis */ + respR1 = SDIO_GetResponse(SDIO_RESP1); + + /* Find out card status */ + *pstatus = (u8) ((respR1 >> 9) & 0x0000000F); + + if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return(errorstatus); + } + + if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if (respR1 & SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if (respR1 & SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if (respR1 & SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if (respR1 & SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if (respR1 & SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if (respR1 & SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if (respR1 & SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (respR1 & SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if (respR1 & SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (respR1 & SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if (respR1 & SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if (respR1 & SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if (respR1 & SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if (respR1 & SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if (respR1 & SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : FindSCR +* Description : Find the SD card SCR register value. +* Input : - rca: selected card address. +* - pscr: pointer to the buffer that will contain the SCR value. +* Output : None +* Return : SD_Error: SD Card Error code. +*******************************************************************************/ +static SD_Error FindSCR(u16 rca, u32 *pscr) +{ + u32 index = 0; + SD_Error errorstatus = SD_OK; + u32 tempscr[2] = {0, 0}; + + /* Set Block Size To 8 Bytes */ + /* Send CMD55 APP_CMD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (u32)8; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /* Send CMD55 APP_CMD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (u32) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 8; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SD_APP_SEND_SCR; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SDIO_SD_APP_SEND_SCR); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) + { + *(tempscr + index) = SDIO_ReadData(); + index++; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + + /* Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); + + *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); + + return(errorstatus); +} + +/******************************************************************************* +* Function Name : convert_from_bytes_to_power_of_two +* Description : Converts the number of bytes in power of two and returns the +* power. +* Input : NumberOfBytes: number of bytes. +* Output : None +* Return : None +*******************************************************************************/ +static u8 convert_from_bytes_to_power_of_two(u16 NumberOfBytes) +{ + u8 count = 0; + + while (NumberOfBytes != 1) + { + NumberOfBytes >>= 1; + count++; + } + return(count); +} + +/******************************************************************************* +* Function Name : GPIO_Configuration +* Description : Configures the SDIO Corresponding GPIO Ports +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOC and GPIOD Periph clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE); + + /* Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Configure PD.02 CMD line */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOD, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : DMA_TxConfiguration +* Description : Configures the DMA2 Channel4 for SDIO Tx request. +* Input : - BufferSRC: pointer to the source buffer +* - BufferSize: buffer size +* Output : None +* Return : None +*******************************************************************************/ +static void DMA_TxConfiguration(u32 *BufferSRC, u32 BufferSize) +{ + DMA_InitTypeDef DMA_InitStructure; + + DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4); + + /* DMA2 Channel4 disable */ + DMA_Cmd(DMA2_Channel4, DISABLE); + + /* DMA2 Channel4 Config */ + DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)SDIO_FIFO_Address; + DMA_InitStructure.DMA_MemoryBaseAddr = (u32)BufferSRC; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; + DMA_InitStructure.DMA_BufferSize = BufferSize / 4; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + DMA_Init(DMA2_Channel4, &DMA_InitStructure); + + /* DMA2 Channel4 enable */ + DMA_Cmd(DMA2_Channel4, ENABLE); +} + +/******************************************************************************* +* Function Name : DMA_RxConfiguration +* Description : Configures the DMA2 Channel4 for SDIO Rx request. +* Input : - BufferDST: pointer to the destination buffer +* - BufferSize: buffer size +* Output : None +* Return : None +*******************************************************************************/ +static void DMA_RxConfiguration(u32 *BufferDST, u32 BufferSize) +{ + DMA_InitTypeDef DMA_InitStructure; + + DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4); + + /* DMA2 Channel4 disable */ + DMA_Cmd(DMA2_Channel4, DISABLE); + + /* DMA2 Channel4 Config */ + DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)SDIO_FIFO_Address; + DMA_InitStructure.DMA_MemoryBaseAddr = (u32)BufferDST; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_BufferSize = BufferSize / 4; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + DMA_Init(DMA2_Channel4, &DMA_InitStructure); + + /* DMA2 Channel4 enable */ + DMA_Cmd(DMA2_Channel4, ENABLE); +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ + +/* + * RT-Thread SD Card Driver + * 20090417 Bernard + */ +#include +#include + +struct rt_device sdcard_device; +SD_CardInfo SDCardInfo; +struct dfs_partition part; + +/* RT-Thread Device Driver Interface */ +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* set sector size to 512 */ +#define SECTOR_SIZE 512 +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + SD_Error status; + rt_uint32_t i; + + // rt_kprintf("read: 0x%x, size %d\n", pos, size); + + /* read all sectors */ + for (i = 0; i < size / SECTOR_SIZE; i ++) + { + status = SD_ReadBlock((part.offset + i)* SECTOR_SIZE + pos, + (rt_uint32_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE), + SECTOR_SIZE); + if (status != SD_OK) + { + rt_kprintf("sd card read failed\n"); + return 0; + } + } + + if (status == SD_OK) return size; + + rt_kprintf("read failed: %d\n", status); + return 0; +} + +static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + SD_Error status; + rt_uint32_t i; + + // rt_kprintf("write: 0x%x, size %d\n", pos, size); + + /* read all sectors */ + for (i = 0; i < size / SECTOR_SIZE; i ++) + { + status = SD_WriteBlock((part.offset + i)* SECTOR_SIZE + pos, + (rt_uint32_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE), + SECTOR_SIZE); + if (status != SD_OK) + { + rt_kprintf("sd card write failed\n"); + return 0; + } + } + + if (status == SD_OK) return size; + + rt_kprintf("write failed: %d\n", status); + return 0; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +void rt_hw_sdcard_init() +{ + if (SD_Init()) + { + SD_Error status; + rt_uint8_t *sector; + + status = SD_GetCardInfo(&SDCardInfo); + if (status != SD_OK) goto __return; + + status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16)); + if (status != SD_OK) goto __return; + + SD_EnableWideBusOperation(SDIO_BusWide_4b); + SD_SetDeviceMode(SD_DMA_MODE); + + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + status = SD_ReadBlock(0, (rt_uint32_t*)sector, 512); + if (status == SD_OK) + { + /* get the first partition */ + if (dfs_filesystem_get_partition(&part, sector, 0) != 0) + { + /* there is no partition */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + /* release sector buffer */ + rt_free(sector); + + /* register sdcard device */ + sdcard_device.init = rt_sdcard_init; + sdcard_device.open = rt_sdcard_open; + sdcard_device.close = rt_sdcard_close; + sdcard_device.read = rt_sdcard_read; + sdcard_device.write = rt_sdcard_write; + sdcard_device.control = rt_sdcard_control; + + /* no private */ + sdcard_device.private = RT_NULL; + + rt_device_register(&sdcard_device, "sd0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + return; + } + +__return: + rt_kprintf("sdcard init failed\n"); +} diff --git a/bsp/stm32/sdcard.h b/bsp/stm32/sdcard.h new file mode 100644 index 0000000000..172fb6579d --- /dev/null +++ b/bsp/stm32/sdcard.h @@ -0,0 +1,264 @@ + /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : sdcard.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* SD Card driver firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SDCARD_H +#define __SDCARD_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +typedef enum +{ + /* SDIO specific error defines */ + SD_CMD_CRC_FAIL = (1), /* Command response received (but CRC check failed) */ + SD_DATA_CRC_FAIL = (2), /* Data bock sent/received (CRC check Failed) */ + SD_CMD_RSP_TIMEOUT = (3), /* Command response timeout */ + SD_DATA_TIMEOUT = (4), /* Data time out */ + SD_TX_UNDERRUN = (5), /* Transmit FIFO under-run */ + SD_RX_OVERRUN = (6), /* Receive FIFO over-run */ + SD_START_BIT_ERR = (7), /* Start bit not detected on all data signals in widE bus mode */ + SD_CMD_OUT_OF_RANGE = (8), /* CMD's argument was out of range.*/ + SD_ADDR_MISALIGNED = (9), /* Misaligned address */ + SD_BLOCK_LEN_ERR = (10), /* Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ + SD_ERASE_SEQ_ERR = (11), /* An error in the sequence of erase command occurs.*/ + SD_BAD_ERASE_PARAM = (12), /* An Invalid selection for erase groups */ + SD_WRITE_PROT_VIOLATION = (13), /* Attempt to program a write protect block */ + SD_LOCK_UNLOCK_FAILED = (14), /* Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ + SD_COM_CRC_FAILED = (15), /* CRC check of the previous command failed */ + SD_ILLEGAL_CMD = (16), /* Command is not legal for the card state */ + SD_CARD_ECC_FAILED = (17), /* Card internal ECC was applied but failed to correct the data */ + SD_CC_ERROR = (18), /* Internal card controller error */ + SD_GENERAL_UNKNOWN_ERROR = (19), /* General or Unknown error */ + SD_STREAM_READ_UNDERRUN = (20), /* The card could not sustain data transfer in stream read operation. */ + SD_STREAM_WRITE_OVERRUN = (21), /* The card could not sustain data programming in stream mode */ + SD_CID_CSD_OVERWRITE = (22), /* CID/CSD overwrite error */ + SD_WP_ERASE_SKIP = (23), /* only partial address space was erased */ + SD_CARD_ECC_DISABLED = (24), /* Command has been executed without using internal ECC */ + SD_ERASE_RESET = (25), /* Erase sequence was cleared before executing because an out of erase sequence command was received */ + SD_AKE_SEQ_ERROR = (26), /* Error in sequence of authentication. */ + SD_INVALID_VOLTRANGE = (27), + SD_ADDR_OUT_OF_RANGE = (28), + SD_SWITCH_ERROR = (29), + SD_SDIO_DISABLED = (30), + SD_SDIO_FUNCTION_BUSY = (31), + SD_SDIO_FUNCTION_FAILED = (32), + SD_SDIO_UNKNOWN_FUNCTION = (33), + + /* Standard error defines */ + SD_INTERNAL_ERROR, + SD_NOT_CONFIGURED, + SD_REQUEST_PENDING, + SD_REQUEST_NOT_APPLICABLE, + SD_INVALID_PARAMETER, + SD_UNSUPPORTED_FEATURE, + SD_UNSUPPORTED_HW, + SD_ERROR, + SD_OK, +} SD_Error; + +/* SDIO Commands Index */ +#define SDIO_GO_IDLE_STATE ((u8)0) +#define SDIO_SEND_OP_COND ((u8)1) +#define SDIO_ALL_SEND_CID ((u8)2) +#define SDIO_SET_REL_ADDR ((u8)3) /* SDIO_SEND_REL_ADDR for SD Card */ +#define SDIO_SET_DSR ((u8)4) +#define SDIO_SDIO_SEN_OP_COND ((u8)5) +#define SDIO_HS_SWITCH ((u8)6) +#define SDIO_SEL_DESEL_CARD ((u8)7) +#define SDIO_HS_SEND_EXT_CSD ((u8)8) +#define SDIO_SEND_CSD ((u8)9) +#define SDIO_SEND_CID ((u8)10) +#define SDIO_READ_DAT_UNTIL_STOP ((u8)11) /* SD Card doesn't support it */ +#define SDIO_STOP_TRANSMISSION ((u8)12) +#define SDIO_SEND_STATUS ((u8)13) +#define SDIO_HS_BUSTEST_READ ((u8)14) +#define SDIO_GO_INACTIVE_STATE ((u8)15) +#define SDIO_SET_BLOCKLEN ((u8)16) +#define SDIO_READ_SINGLE_BLOCK ((u8)17) +#define SDIO_READ_MULT_BLOCK ((u8)18) +#define SDIO_HS_BUSTEST_WRITE ((u8)19) +#define SDIO_WRITE_DAT_UNTIL_STOP ((u8)20) /* SD Card doesn't support it */ +#define SDIO_SET_BLOCK_COUNT ((u8)23) /* SD Card doesn't support it */ +#define SDIO_WRITE_SINGLE_BLOCK ((u8)24) +#define SDIO_WRITE_MULT_BLOCK ((u8)25) +#define SDIO_PROG_CID ((u8)26) /* reserved for manufacturers */ +#define SDIO_PROG_CSD ((u8)27) +#define SDIO_SET_WRITE_PROT ((u8)28) +#define SDIO_CLR_WRITE_PROT ((u8)29) +#define SDIO_SEND_WRITE_PROT ((u8)30) +#define SDIO_SD_ERASE_GRP_START ((u8)32) /* To set the address of the first write + block to be erased. (For SD card only) */ +#define SDIO_SD_ERASE_GRP_END ((u8)33) /* To set the address of the last write block of the + continuous range to be erased. (For SD card only) */ +#define SDIO_ERASE_GRP_START ((u8)35) /* To set the address of the first write block to be erased. + (For MMC card only spec 3.31) */ + +#define SDIO_ERASE_GRP_END ((u8)36) /* To set the address of the last write block of the + continuous range to be erased. (For MMC card only spec 3.31) */ + +#define SDIO_ERASE ((u8)38) +#define SDIO_FAST_IO ((u8)39) /* SD Card doesn't support it */ +#define SDIO_GO_IRQ_STATE ((u8)40) /* SD Card doesn't support it */ +#define SDIO_LOCK_UNLOCK ((u8)42) +#define SDIO_APP_CMD ((u8)55) +#define SDIO_GEN_CMD ((u8)56) +#define SDIO_NO_CMD ((u8)64) + +/* Following commands are SD Card Specific commands. + SDIO_APP_CMD should be sent before sending these + commands. */ +#define SDIO_APP_SD_SET_BUSWIDTH ((u8)6) /* For SD Card only */ +#define SDIO_SD_APP_STAUS ((u8)13) /* For SD Card only */ +#define SDIO_SD_APP_SEND_NUM_WRITE_BLOCKS ((u8)22) /* For SD Card only */ +#define SDIO_SD_APP_OP_COND ((u8)41) /* For SD Card only */ +#define SDIO_SD_APP_SET_CLR_CARD_DETECT ((u8)42) /* For SD Card only */ +#define SDIO_SD_APP_SEND_SCR ((u8)51) /* For SD Card only */ +#define SDIO_SDIO_RW_DIRECT ((u8)52) /* For SD I/O Card only */ +#define SDIO_SDIO_RW_EXTENDED ((u8)53) /* For SD I/O Card only */ + +/* Following commands are SD Card Specific security commands. + SDIO_APP_CMD should be sent before sending these commands. */ +#define SDIO_SD_APP_GET_MKB ((u8)43) /* For SD Card only */ +#define SDIO_SD_APP_GET_MID ((u8)44) /* For SD Card only */ +#define SDIO_SD_APP_SET_CER_RN1 ((u8)45) /* For SD Card only */ +#define SDIO_SD_APP_GET_CER_RN2 ((u8)46) /* For SD Card only */ +#define SDIO_SD_APP_SET_CER_RES2 ((u8)47) /* For SD Card only */ +#define SDIO_SD_APP_GET_CER_RES1 ((u8)48) /* For SD Card only */ +#define SDIO_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((u8)18) /* For SD Card only */ +#define SDIO_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((u8)25) /* For SD Card only */ +#define SDIO_SD_APP_SECURE_ERASE ((u8)38) /* For SD Card only */ +#define SDIO_SD_APP_CHANGE_SECURE_AREA ((u8)49) /* For SD Card only */ +#define SDIO_SD_APP_SECURE_WRITE_MKB ((u8)48) /* For SD Card only */ + +typedef enum +{ + SD_NO_TRANSFER = 0, + SD_TRANSFER_IN_PROGRESS +} SDTransferState; + +typedef struct +{ + u16 TransferredBytes; + SD_Error TransferError; + u8 padding; +} SDLastTransferInfo; + +typedef struct /* Card Specific Data */ +{ + vu8 CSDStruct; /* CSD structure */ + vu8 SysSpecVersion; /* System specification version */ + vu8 Reserved1; /* Reserved */ + vu8 TAAC; /* Data read access-time 1 */ + vu8 NSAC; /* Data read access-time 2 in CLK cycles */ + vu8 MaxBusClkFrec; /* Max. bus clock frequency */ + vu16 CardComdClasses; /* Card command classes */ + vu8 RdBlockLen; /* Max. read data block length */ + vu8 PartBlockRead; /* Partial blocks for read allowed */ + vu8 WrBlockMisalign; /* Write block misalignment */ + vu8 RdBlockMisalign; /* Read block misalignment */ + vu8 DSRImpl; /* DSR implemented */ + vu8 Reserved2; /* Reserved */ + vu32 DeviceSize; /* Device Size */ + vu8 MaxRdCurrentVDDMin; /* Max. read current @ VDD min */ + vu8 MaxRdCurrentVDDMax; /* Max. read current @ VDD max */ + vu8 MaxWrCurrentVDDMin; /* Max. write current @ VDD min */ + vu8 MaxWrCurrentVDDMax; /* Max. write current @ VDD max */ + vu8 DeviceSizeMul; /* Device size multiplier */ + vu8 EraseGrSize; /* Erase group size */ + vu8 EraseGrMul; /* Erase group size multiplier */ + vu8 WrProtectGrSize; /* Write protect group size */ + vu8 WrProtectGrEnable; /* Write protect group enable */ + vu8 ManDeflECC; /* Manufacturer default ECC */ + vu8 WrSpeedFact; /* Write speed factor */ + vu8 MaxWrBlockLen; /* Max. write data block length */ + vu8 WriteBlockPaPartial; /* Partial blocks for write allowed */ + vu8 Reserved3; /* Reserded */ + vu8 ContentProtectAppli; /* Content protection application */ + vu8 FileFormatGrouop; /* File format group */ + vu8 CopyFlag; /* Copy flag (OTP) */ + vu8 PermWrProtect; /* Permanent write protection */ + vu8 TempWrProtect; /* Temporary write protection */ + vu8 FileFormat; /* File Format */ + vu8 ECC; /* ECC code */ + vu8 CSD_CRC; /* CSD CRC */ + vu8 Reserved4; /* always 1*/ +} SD_CSD; + +typedef struct /*Card Identification Data*/ +{ + vu8 ManufacturerID; /* ManufacturerID */ + vu16 OEM_AppliID; /* OEM/Application ID */ + vu32 ProdName1; /* Product Name part1 */ + vu8 ProdName2; /* Product Name part2*/ + vu8 ProdRev; /* Product Revision */ + vu32 ProdSN; /* Product Serial Number */ + vu8 Reserved1; /* Reserved1 */ + vu16 ManufactDate; /* Manufacturing Date */ + vu8 CID_CRC; /* CID CRC */ + vu8 Reserved2; /* always 1 */ +} SD_CID; + +typedef struct +{ + SD_CSD SD_csd; + SD_CID SD_cid; + u32 CardCapacity; /* Card Capacity */ + u32 CardBlockSize; /* Card Block Size */ + u16 RCA; + u8 CardType; +} SD_CardInfo; + +/* Exported constants --------------------------------------------------------*/ +#define SD_DMA_MODE ((u32)0x00000000) +#define SD_INTERRUPT_MODE ((u32)0x00000001) +#define SD_POLLING_MODE ((u32)0x00000002) + +/* Supported Memory Cards */ +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((u32)0x0) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((u32)0x1) +#define SDIO_HIGH_CAPACITY_SD_CARD ((u32)0x2) +#define SDIO_MULTIMEDIA_CARD ((u32)0x3) +#define SDIO_SECURE_DIGITAL_IO_CARD ((u32)0x4) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((u32)0x5) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((u32)0x6) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((u32)0x7) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +SD_Error SD_Init(void); +SD_Error SD_PowerON(void); +SD_Error SD_PowerOFF(void); +SD_Error SD_InitializeCards(void); +SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); +SD_Error SD_EnableWideBusOperation(u32 WideMode); +SD_Error SD_SetDeviceMode(u32 Mode); +SD_Error SD_SelectDeselect(u32 addr); +SD_Error SD_ReadBlock(u32 addr, u32 *readbuff, u16 BlockSize); +SD_Error SD_ReadMultiBlocks(u32 addr, u32 *readbuff, u16 BlockSize, u32 NumberOfBlocks); +SD_Error SD_WriteBlock(u32 addr, u32 *writebuff, u16 BlockSize); +SD_Error SD_WriteMultiBlocks(u32 addr, u32 *writebuff, u16 BlockSize, u32 NumberOfBlocks); +SDTransferState SD_GetTransferState(void); +SD_Error SD_StopTransfer(void); +SD_Error SD_Erase(u32 startaddr, u32 endaddr); +SD_Error SD_SendStatus(u32 *pcardstatus); +SD_Error SD_SendSDStatus(u32 *psdstatus); +SD_Error SD_ProcessIRQSrc(void); + +#endif /* __SDCARD_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/startup.c b/bsp/stm32/startup.c new file mode 100644 index 0000000000..e1caec079a --- /dev/null +++ b/bsp/stm32/startup.c @@ -0,0 +1,150 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "rtc.h" + +#ifdef RT_USING_LWIP +#include +#include "enc28j60.h" +#endif + +/** + * @addtogroup STM32 + */ + +/*@{*/ +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +extern void finsh_set_device(char* device); +#endif + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert error has occurred. +* Input : - file: pointer to the source file name +* - line: assert error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(u8* file, u32 line) +{ + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); + + while (1) ; +} +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20010000); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)0x20010000); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)0x20010000); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_LWIP + eth_system_device_init(); + + /* register ethernetif device */ + rt_hw_enc28j60_init(); +#endif + + rt_hw_rtc_init(); + + /* init hardware serial device */ + rt_hw_usart_init(); +#ifdef RT_USING_DFS + rt_hw_sdcard_init(); +#endif + + /* init all device */ + rt_device_init_all(); + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); +#ifdef RT_USING_DEVICE + finsh_set_device("uart1"); +#endif +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + rt_uint32_t UNUSED level; + + /* disable interrupt first */ + level = rt_hw_interrupt_disable(); + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/stm32/stm32f10x_conf.h b/bsp/stm32/stm32f10x_conf.h new file mode 100644 index 0000000000..f62bb06cd5 --- /dev/null +++ b/bsp/stm32/stm32f10x_conf.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Version : V1.1.2 +* Date : 09/22/2008 +* Description : Library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the library in DEBUG mode, this will expanse + the "assert_param" macro in the firmware library code (see "Exported macro" + section below) */ +/* #define DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +#define _ADC +#define _ADC1 +#define _ADC2 +#define _ADC3 + +/************************************* BKP ************************************/ +#define _BKP + +/************************************* CAN ************************************/ +#define _CAN + +/************************************* CRC ************************************/ +#define _CRC + +/************************************* DAC ************************************/ +#define _DAC + +/************************************* DBGMCU *********************************/ +#define _DBGMCU + +/************************************* DMA ************************************/ +#define _DMA +#define _DMA1_Channel1 +#define _DMA1_Channel2 +#define _DMA1_Channel3 +#define _DMA1_Channel4 +#define _DMA1_Channel5 +#define _DMA1_Channel6 +#define _DMA1_Channel7 +#define _DMA2_Channel1 +#define _DMA2_Channel2 +#define _DMA2_Channel3 +#define _DMA2_Channel4 +#define _DMA2_Channel5 + +/************************************* EXTI ***********************************/ +#define _EXTI + +/************************************* FLASH and Option Bytes *****************/ +#define _FLASH +/* Uncomment the line below to enable FLASH program/erase/protections functions, + otherwise only FLASH configuration (latency, prefetch, half cycle) functions + are enabled */ +/* #define _FLASH_PROG */ + +/************************************* FSMC ***********************************/ +#define _FSMC + +/************************************* GPIO ***********************************/ +#define _GPIO +#define _GPIOA +#define _GPIOB +#define _GPIOC +#define _GPIOD +#define _GPIOE +#define _GPIOF +#define _GPIOG +#define _AFIO + +/************************************* I2C ************************************/ +#define _I2C +#define _I2C1 +#define _I2C2 + +/************************************* IWDG ***********************************/ +#define _IWDG + +/************************************* NVIC ***********************************/ +#define _NVIC + +/************************************* PWR ************************************/ +#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +#define _RTC + +/************************************* SDIO ***********************************/ +#define _SDIO + +/************************************* SPI ************************************/ +#define _SPI +#define _SPI1 +#define _SPI2 +#define _SPI3 + +/************************************* SysTick ********************************/ +#define _SysTick + +/************************************* TIM ************************************/ +#define _TIM +#define _TIM1 +#define _TIM2 +#define _TIM3 +#define _TIM4 +#define _TIM5 +#define _TIM6 +#define _TIM7 +#define _TIM8 + +/************************************* USART **********************************/ +#define _USART +#define _USART1 +#define _USART2 +#define _USART3 +#define _UART4 +#define _UART5 + +/************************************* WWDG ***********************************/ +#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value */ +#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef DEBUG +/******************************************************************************* +* Macro Name : assert_param +* Description : The assert_param macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert_param(expr) ((void)0) +#endif /* DEBUG */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f10x_flash.icf b/bsp/stm32/stm32f10x_flash.icf new file mode 100644 index 0000000000..c32afef5fb --- /dev/null +++ b/bsp/stm32/stm32f10x_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, last block HEAP}; diff --git a/bsp/stm32/stm32f10x_it.c b/bsp/stm32/stm32f10x_it.c new file mode 100644 index 0000000000..bb5f38cda8 --- /dev/null +++ b/bsp/stm32/stm32f10x_it.c @@ -0,0 +1,919 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_it.c +* Author : MCD Application Team +* Version : V1.1.2 +* Date : 09/22/2008 +* Description : Main Interrupt Service Routines. +* This file provides template for all exceptions handler +* and peripherals interrupt service routine. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +extern void rt_hw_timer_handler(void); +extern void rt_hw_interrupt_thread_switch(void); + +/******************************************************************************* +* Function Name : NMIException +* Description : This function handles NMI exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NMIException(void) +{ +} + +/******************************************************************************* +* Function Name : HardFaultException +* Description : This function handles Hard Fault exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void HardFaultException(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + rt_kprintf("hard fault exception\n"); + while (1) + { + } +} + +/******************************************************************************* +* Function Name : MemManageException +* Description : This function handles Memory Manage exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MemManageException(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + rt_kprintf("memory manage exception\n"); + while (1) + { + } +} + +/******************************************************************************* +* Function Name : BusFaultException +* Description : This function handles Bus Fault exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BusFaultException(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + rt_kprintf("bus fault exception\n"); + while (1) + { + } +} + +/******************************************************************************* +* Function Name : UsageFaultException +* Description : This function handles Usage Fault exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UsageFaultException(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + rt_kprintf("usage fault exception\n"); + while (1) + { + } +} + +/******************************************************************************* +* Function Name : DebugMonitor +* Description : This function handles Debug Monitor exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DebugMonitor(void) +{ +} + +/******************************************************************************* +* Function Name : SVCHandler +* Description : This function handles SVCall exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SVCHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SysTickHandler +* Description : This function handles SysTick Handler. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SysTickHandler(void) +{ + /* handle os tick */ + rt_hw_timer_handler(); +} + +/******************************************************************************* +* Function Name : WWDG_IRQHandler +* Description : This function handles WWDG interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PVD_IRQHandler +* Description : This function handles PVD interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PVD_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TAMPER_IRQHandler +* Description : This function handles Tamper interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TAMPER_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles RTC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ + if (RTC_GetITStatus(RTC_IT_SEC) != RESET) + { + /* Clear the RTC Second interrupt */ + RTC_ClearITPendingBit(RTC_IT_SEC); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + /* Reset RTC Counter when Time is 23:59:59 */ + if (RTC_GetCounter() == 0x00015180) + { + RTC_SetCounter(0x0); + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + } + } +} + +/******************************************************************************* +* Function Name : FLASH_IRQHandler +* Description : This function handles Flash interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RCC_IRQHandler +* Description : This function handles RCC interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI0_IRQHandler +* Description : This function handles External interrupt Line 0 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI0_IRQHandler(void) +{ + extern void enc28j60_isr(void); + + /* enter interrupt */ + rt_interrupt_enter(); + + enc28j60_isr(); + + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(EXTI_Line0); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +} + +/******************************************************************************* +* Function Name : EXTI1_IRQHandler +* Description : This function handles External interrupt Line 1 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI2_IRQHandler +* Description : This function handles External interrupt Line 2 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI3_IRQHandler +* Description : This function handles External interrupt Line 3 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI4_IRQHandler +* Description : This function handles External interrupt Line 4 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA1_Channel1_IRQHandler +* Description : This function handles DMA1 Channel 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA1_Channel2_IRQHandler +* Description : This function handles DMA1 Channel 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel2_IRQHandler(void) +{ +#ifdef RT_USING_UART3 + extern struct rt_device uart3_device; + + /* enter interrupt */ + rt_interrupt_enter(); + + if (DMA_GetITStatus(DMA1_IT_TC2)) + { + /* transmission complete, invoke serial dma tx isr */ + rt_hw_serial_dma_tx_isr(&uart3_device); + } + + /* clear DMA flag */ + DMA_ClearFlag(DMA1_FLAG_TC2 | DMA1_FLAG_TE2); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +#endif +} + +/******************************************************************************* +* Function Name : DMA1_Channel3_IRQHandler +* Description : This function handles DMA1 Channel 3 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA1_Channel4_IRQHandler +* Description : This function handles DMA1 Channel 4 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA1_Channel5_IRQHandler +* Description : This function handles DMA1 Channel 5 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel5_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA1_Channel6_IRQHandler +* Description : This function handles DMA1 Channel 6 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel6_IRQHandler(void) +{ +#ifdef RT_USING_UART2 + extern struct rt_device uart2_device; + + /* enter interrupt */ + rt_interrupt_enter(); + + /* clear DMA flag */ + DMA_ClearFlag(DMA1_FLAG_TC6 | DMA1_FLAG_TE6); + rt_hw_serial_dma_rx_isr(&uart2_device); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +#endif +} + +/******************************************************************************* +* Function Name : DMA1_Channel7_IRQHandler +* Description : This function handles DMA1 Channel 7 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA1_Channel7_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : ADC1_2_IRQHandler +* Description : This function handles ADC1 and ADC2 global interrupts requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC1_2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USB_HP_CAN_TX_IRQHandler +* Description : This function handles USB High Priority or CAN TX interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_HP_CAN_TX_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USB_LP_CAN_RX0_IRQHandler +* Description : This function handles USB Low Priority or CAN RX0 interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_LP_CAN_RX0_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_RX1_IRQHandler +* Description : This function handles CAN RX1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_RX1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_SCE_IRQHandler +* Description : This function handles CAN SCE interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SCE_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI9_5_IRQHandler +* Description : This function handles External lines 9 to 5 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI9_5_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_BRK_IRQHandler +* Description : This function handles TIM1 Break interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_BRK_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_UP_IRQHandler +* Description : This function handles TIM1 overflow and update interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_TRG_COM_IRQHandler +* Description : This function handles TIM1 Trigger and commutation interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TRG_COM_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_CC_IRQHandler +* Description : This function handles TIM1 capture compare interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles TIM2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles TIM3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM4_IRQHandler +* Description : This function handles TIM4 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C1_EV_IRQHandler +* Description : This function handles I2C1 Event interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_EV_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C1_ER_IRQHandler +* Description : This function handles I2C1 Error interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_ER_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C2_EV_IRQHandler +* Description : This function handles I2C2 Event interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C2_EV_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C2_ER_IRQHandler +* Description : This function handles I2C2 Error interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C2_ER_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SPI1_IRQHandler +* Description : This function handles SPI1 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SPI2_IRQHandler +* Description : This function handles SPI2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USART1_IRQHandler +* Description : This function handles USART1 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USART1_IRQHandler(void) +{ +#ifdef RT_USING_UART1 + extern struct rt_device uart1_device; + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_serial_isr(&uart1_device); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +#endif +} + +/******************************************************************************* +* Function Name : USART2_IRQHandler +* Description : This function handles USART2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USART2_IRQHandler(void) +{ +#ifdef RT_USING_UART2 + extern struct rt_device uart2_device; + + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_serial_isr(&uart2_device); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +#endif +} + +/******************************************************************************* +* Function Name : USART3_IRQHandler +* Description : This function handles USART3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USART3_IRQHandler(void) +{ +#ifdef RT_USING_UART3 + extern struct rt_device uart3_device; + + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_serial_isr(&uart3_device); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +#endif +} + +/******************************************************************************* +* Function Name : EXTI15_10_IRQHandler +* Description : This function handles External lines 15 to 10 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI15_10_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RTCAlarm_IRQHandler +* Description : This function handles RTC Alarm interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTCAlarm_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USBWakeUp_IRQHandler +* Description : This function handles USB WakeUp interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWakeUp_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM8_BRK_IRQHandler +* Description : This function handles TIM8 Break interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_BRK_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM8_UP_IRQHandler +* Description : This function handles TIM8 overflow and update interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM8_TRG_COM_IRQHandler +* Description : This function handles TIM8 Trigger and commutation interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_TRG_COM_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM8_CC_IRQHandler +* Description : This function handles TIM8 capture compare interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM8_CC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : ADC3_IRQHandler +* Description : This function handles ADC3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : FSMC_IRQHandler +* Description : This function handles FSMC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FSMC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SDIO_IRQHandler +* Description : This function handles SDIO global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SDIO_IRQHandler(void) +{ +#ifdef RT_USING_DFS + extern int SD_ProcessIRQSrc(void); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* Process All SDIO Interrupt Sources */ + SD_ProcessIRQSrc(); + + /* leave interrupt */ + rt_interrupt_leave(); + rt_hw_interrupt_thread_switch(); +#endif +} + +/******************************************************************************* +* Function Name : TIM5_IRQHandler +* Description : This function handles TIM5 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM5_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SPI3_IRQHandler +* Description : This function handles SPI3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART4_IRQHandler +* Description : This function handles UART4 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART5_IRQHandler +* Description : This function handles UART5 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART5_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM6_IRQHandler +* Description : This function handles TIM6 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM6_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM7_IRQHandler +* Description : This function handles TIM7 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM7_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA2_Channel1_IRQHandler +* Description : This function handles DMA2 Channel 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA2_Channel2_IRQHandler +* Description : This function handles DMA2 Channel 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA2_Channel3_IRQHandler +* Description : This function handles DMA2 Channel 3 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA2_Channel4_5_IRQHandler +* Description : This function handles DMA2 Channel 4 and DMA2 Channel 5 +* interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA2_Channel4_5_IRQHandler(void) +{ +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f10x_it.h b/bsp/stm32/stm32f10x_it.h new file mode 100644 index 0000000000..11740669fa --- /dev/null +++ b/bsp/stm32/stm32f10x_it.h @@ -0,0 +1,100 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_it.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains the headers of the interrupt handlers. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMIException(void); +void HardFaultException(void); +void MemManageException(void); +void BusFaultException(void); +void UsageFaultException(void); +void DebugMonitor(void); +void SVCHandler(void); +void rt_hw_pend_sv(void); +void SysTickHandler(void); +void WWDG_IRQHandler(void); +void PVD_IRQHandler(void); +void TAMPER_IRQHandler(void); +void RTC_IRQHandler(void); +void FLASH_IRQHandler(void); +void RCC_IRQHandler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void EXTI2_IRQHandler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); +void DMA1_Channel1_IRQHandler(void); +void DMA1_Channel2_IRQHandler(void); +void DMA1_Channel3_IRQHandler(void); +void DMA1_Channel4_IRQHandler(void); +void DMA1_Channel5_IRQHandler(void); +void DMA1_Channel6_IRQHandler(void); +void DMA1_Channel7_IRQHandler(void); +void ADC1_2_IRQHandler(void); +void USB_HP_CAN_TX_IRQHandler(void); +void USB_LP_CAN_RX0_IRQHandler(void); +void CAN_RX1_IRQHandler(void); +void CAN_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void TIM1_BRK_IRQHandler(void); +void TIM1_UP_IRQHandler(void); +void TIM1_TRG_COM_IRQHandler(void); +void TIM1_CC_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void TIM4_IRQHandler(void); +void I2C1_EV_IRQHandler(void); +void I2C1_ER_IRQHandler(void); +void I2C2_EV_IRQHandler(void); +void I2C2_ER_IRQHandler(void); +void SPI1_IRQHandler(void); +void SPI2_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void USART3_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void RTCAlarm_IRQHandler(void); +void USBWakeUp_IRQHandler(void); +void TIM8_BRK_IRQHandler(void); +void TIM8_UP_IRQHandler(void); +void TIM8_TRG_COM_IRQHandler(void); +void TIM8_CC_IRQHandler(void); +void ADC3_IRQHandler(void); +void FSMC_IRQHandler(void); +void SDIO_IRQHandler(void); +void TIM5_IRQHandler(void); +void SPI3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void TIM6_IRQHandler(void); +void TIM7_IRQHandler(void); +void DMA2_Channel1_IRQHandler(void); +void DMA2_Channel2_IRQHandler(void); +void DMA2_Channel3_IRQHandler(void); +void DMA2_Channel4_5_IRQHandler(void); + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/usart.c b/bsp/stm32/usart.c new file mode 100644 index 0000000000..5a87dd4274 --- /dev/null +++ b/bsp/stm32/usart.c @@ -0,0 +1,341 @@ +#include "usart.h" +#include + +#include +#include + +/* + * Use UART1 as console output and finsh input + * interrupt Rx and poll Tx (stream mode) + * + * Use UART2 with DMA Rx and poll Tx -- DMA channel 6 + * Use UART3 with DMA Tx and interrupt Rx -- DMA channel 2 + * + * USART DMA setting on STM32 + * USART1 Tx --> DMA Channel 4 + * USART1 Rx --> DMA Channel 5 + * USART2 Tx --> DMA Channel 7 + * USART2 Rx --> DMA Channel 6 + * USART3 Tx --> DMA Channel 2 + * USART3 Rx --> DMA Channel 3 + */ + +#ifdef RT_USING_UART1 +struct stm32_serial_int_rx uart1_int_rx; +struct stm32_serial_device uart1 = +{ + USART1, + &uart1_int_rx, + RT_NULL, + RT_NULL, + RT_NULL +}; +struct rt_device uart1_device; +#endif + +#ifdef RT_USING_UART2 +struct stm32_serial_int_rx uart2_int_rx; +struct stm32_serial_dma_rx uart2_dma_rx; +struct stm32_serial_device uart2 = +{ + USART2, + &uart2_int_rx, + &uart2_dma_rx, + RT_NULL, + RT_NULL +}; +struct rt_device uart2_device; +#endif + +#ifdef RT_USING_UART3 +struct stm32_serial_int_rx uart3_int_rx; +struct stm32_serial_dma_tx uart3_dma_tx; +struct stm32_serial_device uart3 = +{ + USART3, + &uart3_int_rx, + RT_NULL, + RT_NULL, + &uart3_dma_tx +}; +struct rt_device uart3_device; +#endif + +#define USART1_DR_Base 0x40013804 +#define USART2_DR_Base 0x40004404 +#define USART3_DR_Base 0x40004804 + +/* USART1_REMAP = 0 */ +#define UART1_GPIO_TX GPIO_Pin_9 +#define UART1_GPIO_RX GPIO_Pin_10 +#define UART1_GPIO GPIOA +#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1 +#define UART1_TX_DMA DMA1_Channel4 +#define UART1_RX_DMA DMA1_Channel5 + +/* USART2_REMAP = 0 */ +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_GPIO GPIOA +#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 +#define UART2_TX_DMA DMA1_Channel7 +#define UART2_RX_DMA DMA1_Channel6 + +/* USART3_REMAP[1:0] = 00 */ +#define UART3_GPIO_RX GPIO_Pin_11 +#define UART3_GPIO_TX GPIO_Pin_10 +#define UART3_GPIO GPIOB +#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3 +#define UART3_TX_DMA DMA1_Channel2 +#define UART3_RX_DMA DMA1_Channel3 + +static void RCC_Configuration(void) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + +#ifdef RT_USING_UART1 + /* Enable USART1 and GPIOA clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); +#endif + +#ifdef RT_USING_UART2 + /* Enable GPIOD clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); + /* Enable USART2 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); +#endif + +#ifdef RT_USING_UART3 + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + /* Enable USART3 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); +#endif + +#if defined (RT_USING_UART2) || defined (RT_USING_UART3) + /* DMA clock enable */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); +#endif +} + +static void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + +#ifdef RT_USING_UART1 + /* Configure USART1 Rx (PA.10) as input floating */ + GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); + + /* Configure USART1 Tx (PA.09) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); +#endif + +#ifdef RT_USING_UART2 + /* Configure USART2 Rx as input floating */ + GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(UART2_GPIO, &GPIO_InitStructure); + + /* Configure USART2 Tx as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(UART2_GPIO, &GPIO_InitStructure); +#endif + +#ifdef RT_USING_UART3 + /* Configure USART3 Rx as input floating */ + GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(UART3_GPIO, &GPIO_InitStructure); + + /* Configure USART3 Tx as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(UART3_GPIO, &GPIO_InitStructure); +#endif +} + +static void NVIC_Configuration(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Configure the NVIC Preemption Priority Bits */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0); + +#ifdef RT_USING_UART1 + /* Enable the USART1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +#endif + +#ifdef RT_USING_UART2 + /* Enable the USART2 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable the DMA1 Channel6 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel6_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +#endif + +#ifdef RT_USING_UART3 + /* Enable the USART3 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable the DMA1 Channel2 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel2_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +#endif +} + +static void DMA_Configuration(void) +{ +#if defined(RT_USING_UART2) || defined (RT_USING_UART3) + DMA_InitTypeDef DMA_InitStructure; + + /* fill init structure */ + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; +#endif + +#ifdef RT_USING_UART2 + /* DMA1 Channel4 (triggered by USART2 Rx event) Config */ + DMA_DeInit(UART2_RX_DMA); + DMA_InitStructure.DMA_PeripheralBaseAddr = USART2_DR_Base; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0; + DMA_InitStructure.DMA_BufferSize = 0; + DMA_Init(UART2_RX_DMA, &DMA_InitStructure); + DMA_ITConfig(UART2_RX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE); + DMA_ClearFlag(DMA1_FLAG_TC4); +#endif + +#ifdef RT_USING_UART3 + /* DMA1 Channel5 (triggered by USART3 Tx event) Config */ + DMA_DeInit(UART3_TX_DMA); + DMA_InitStructure.DMA_PeripheralBaseAddr = USART3_DR_Base; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; + DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0; + DMA_InitStructure.DMA_BufferSize = 0; + DMA_Init(UART3_TX_DMA, &DMA_InitStructure); + DMA_ITConfig(UART3_TX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE); + DMA_ClearFlag(DMA1_FLAG_TC5); +#endif +} + +/* + * Init all related hardware in here + * rt_hw_serial_init() will register all supported USART device + */ +void rt_hw_usart_init() +{ + USART_InitTypeDef USART_InitStructure; + USART_ClockInitTypeDef USART_ClockInitStructure; + + RCC_Configuration(); + + GPIO_Configuration(); + + NVIC_Configuration(); + + DMA_Configuration(); + + /* uart init */ +#ifdef RT_USING_UART1 + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_ClockInitStructure.USART_Clock = USART_Clock_Disable; + USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low; + USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge; + USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable; + USART_Init(USART1, &USART_InitStructure); + USART_ClockInit(USART1, &USART_ClockInitStructure); + + /* register uart1 */ + rt_hw_serial_register(&uart1_device, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); + + /* enable interrupt */ + USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); +#endif + +#ifdef RT_USING_UART2 + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_ClockInitStructure.USART_Clock = USART_Clock_Disable; + USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low; + USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge; + USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable; + USART_Init(USART2, &USART_InitStructure); + USART_ClockInit(USART2, &USART_ClockInitStructure); + + uart2_dma_rx.dma_channel= UART2_RX_DMA; + + /* register uart2 */ + rt_hw_serial_register(&uart2_device, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_RX, + &uart2); + + /* Enable USART2 DMA Rx request */ + USART_DMACmd(USART2, USART_DMAReq_Rx , ENABLE); +#endif + +#ifdef RT_USING_UART3 + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_ClockInitStructure.USART_Clock = USART_Clock_Disable; + USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low; + USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge; + USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable; + USART_Init(USART3, &USART_InitStructure); + USART_ClockInit(USART3, &USART_ClockInitStructure); + + uart3_dma_tx.dma_channel= UART3_TX_DMA; + + /* register uart3 */ + rt_hw_serial_register(&uart3_device, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_TX, + &uart3); + + /* Enable USART3 DMA Tx request */ + USART_DMACmd(USART3, USART_DMAReq_Tx , ENABLE); + + /* enable interrupt */ + USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); +#endif +} diff --git a/bsp/stm32/usart.h b/bsp/stm32/usart.h new file mode 100644 index 0000000000..ae74ffde71 --- /dev/null +++ b/bsp/stm32/usart.h @@ -0,0 +1,9 @@ +#ifndef __USART_H__ +#define __USART_H__ + +#include +#include + +void rt_hw_usart_init(void); + +#endif -- GitLab