提交 ff772b27 编写于 作者: J Jay Cliburn 提交者: Jeff Garzik

atl1: add PHY power save mode

Using vendor-provided magic, add code to enter power save mode
on the PHY.  We'll need this for suspend and wake-on-lan.
Signed-off-by: NJay Cliburn <jacliburn@bellsouth.net>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
上级 f403ede7
......@@ -638,21 +638,18 @@ static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
}
/*
*TODO: do something or get rid of this
* Force the PHY into power saving mode using vendor magic.
*/
#ifdef CONFIG_PM
static s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
static void atl1_phy_enter_power_saving(struct atl1_hw *hw)
{
/* s32 ret_val;
* u16 phy_data;
*/
atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
atl1_write_phy_reg(hw, MII_DBG_ADDR, 2);
atl1_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
atl1_write_phy_reg(hw, MII_DBG_ADDR, 3);
atl1_write_phy_reg(hw, MII_DBG_DATA, 0);
/*
ret_val = atl1_write_phy_reg(hw, ...);
ret_val = atl1_write_phy_reg(hw, ...);
....
*/
return 0;
}
#endif
......
......@@ -460,6 +460,9 @@ MODULE_VERSION(ATLX_DRIVER_VERSION);
#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
#define MII_DBG_ADDR 0x1D
#define MII_DBG_DATA 0x1E
/* PCI Command Register Bit Definitions */
#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
#define CMD_IO_SPACE 0x0001
......
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