OMAP2/3: I2C: Errata ID i207: Clear wrong RDR interrupt
Under certain rare conditions, I2C_STAT[13].RDR bit may be set and the corresponding interrupt fire, even there is no data in the receive FIFO, or the I2C data transfer is still ongoing. These spurious RDR events must be ignored by the software. This patch handles and ignores RDR spurious interrupts. The below sequence is required in interrupt handler for handling this errata: 1. If RDR is set to 1, clear RDR 2. Read I2C status register and check for BusBusy bit. If BusBusy bit is set, skip remaining steps. 3. If BusBusy bit is not set, perform read operation on I2C status register. 4. If RDR is set, clear the same. Check RDR again and clear if it sets RDR bit again. 5. Perform I2C Data Read operation N number of times(where N is value read from the register BUFSTAT-RXSTAT bit fields). Note: This errata is not applicable for omap2420 and omap4. It is applicable for: 1. omap2430 2. omap34xx(including omap3630). Signed-off-by: NManjunatha GK <manjugk@ti.com> Cc: Hema Kalliguddi <hemahk@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Aaro Koskinen <Aaro.Koskinen@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NBen Dooks <ben-linux@fluff.org>
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