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体验新版 GitCode,发现更多精彩内容 >>
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c00bfd97
编写于
6月 03, 2014
作者:
V
Vineet Gupta
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电子邮件补丁
差异文件
ARC: [arcfpga] Get rid of legacy BVCI latency unit support
Signed-off-by:
N
Vineet Gupta
<
vgupta@synopsys.com
>
上级
26bc8a9f
变更
2
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2 changed file
with
0 addition
and
87 deletion
+0
-87
arch/arc/plat-arcfpga/Kconfig
arch/arc/plat-arcfpga/Kconfig
+0
-32
arch/arc/plat-arcfpga/platform.c
arch/arc/plat-arcfpga/platform.c
+0
-55
未找到文件。
arch/arc/plat-arcfpga/Kconfig
浏览文件 @
c00bfd97
...
...
@@ -48,36 +48,4 @@ config ARC_SERIAL_BAUD
help
Baud rate for the ARC UART
menuconfig ARC_HAS_BVCI_LAT_UNIT
bool "BVCI Bus Latency Unit"
depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
help
IP to add artificial latency to BVCI Bus Based FPGA builds.
The default latency (even worst case) for FPGA is non-realistic
(~10 SDRAM, ~5 SSRAM).
config BVCI_LAT_UNITS
hex "Latency Unit(s) Bitmap"
default "0x0"
depends on ARC_HAS_BVCI_LAT_UNIT
help
There are multiple Latency Units corresponding to the many
interfaces of the system bus arbiter (both CPU side as well as
the peripheral side).
To add latency to ALL memory transaction, choose Unit 0, otherwise
for finer grainer - interface wise latency, specify a bitmap (1 bit
per unit) of all units. e.g. 1,2,12 will be 0x1003
Unit 0 - System Arb and Mem Controller
Unit 1 - I$ and System Bus
Unit 2 - D$ and System Bus
..
Unit 12 - IDE Disk controller and System Bus
config BVCI_LAT_CYCLES
int "Latency Value in cycles"
range 0 63
default "30"
depends on ARC_HAS_BVCI_LAT_UNIT
endif
arch/arc/plat-arcfpga/platform.c
浏览文件 @
c00bfd97
...
...
@@ -22,59 +22,6 @@
#include <plat/smp.h>
#include <plat/irq.h>
/*-----------------------BVCI Latency Unit -----------------------------*/
#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT
int
lat_cycles
=
CONFIG_BVCI_LAT_CYCLES
;
/* BVCI Bus Profiler: Latency Unit */
static
void
__init
setup_bvci_lat_unit
(
void
)
{
#define MAX_BVCI_UNITS 12
unsigned
int
i
;
unsigned
int
*
base
=
(
unsigned
int
*
)
BVCI_LAT_UNIT_BASE
;
const
unsigned
long
units_req
=
CONFIG_BVCI_LAT_UNITS
;
const
unsigned
int
REG_UNIT
=
21
;
const
unsigned
int
REG_VAL
=
22
;
/*
* There are multiple Latency Units corresponding to the many
* interfaces of the system bus arbiter (both CPU side as well as
* the peripheral side).
*
* Unit 0 - System Arb and Mem Controller - adds latency to all
* memory trasactions
* Unit 1 - I$ and System Bus
* Unit 2 - D$ and System Bus
* ..
* Unit 12 - IDE Disk controller and System Bus
*
* The programmers model requires writing to lat_unit reg first
* and then the latency value (cycles) to lat_value reg
*/
if
(
CONFIG_BVCI_LAT_UNITS
==
0
)
{
writel
(
0
,
base
+
REG_UNIT
);
writel
(
lat_cycles
,
base
+
REG_VAL
);
pr_info
(
"BVCI Latency for all Memory Transactions %d cycles
\n
"
,
lat_cycles
);
}
else
{
for_each_set_bit
(
i
,
&
units_req
,
MAX_BVCI_UNITS
)
{
writel
(
i
+
1
,
base
+
REG_UNIT
);
/* loop is 0 based */
writel
(
lat_cycles
,
base
+
REG_VAL
);
pr_info
(
"BVCI Latency for Unit[%d] = %d cycles
\n
"
,
(
i
+
1
),
lat_cycles
);
}
}
}
#else
static
void
__init
setup_bvci_lat_unit
(
void
)
{
}
#endif
/*----------------------- Platform Devices -----------------------------*/
#if IS_ENABLED(CONFIG_SERIAL_ARC)
...
...
@@ -165,8 +112,6 @@ static void __init plat_fpga_early_init(void)
{
pr_info
(
"[plat-arcfpga]: registering early dev resources
\n
"
);
setup_bvci_lat_unit
();
arc_fpga_serial_init
();
#ifdef CONFIG_ISS_SMP_EXTN
...
...
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