diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index c4625440409ed6e23da7f369256b082ca78f32ab..dcfbed7bcc497e1deeec39868f74e478e37056b0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -24,10 +24,7 @@ if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] if GetDepend(['RT_USING_QSPI']): - src += ['drv_qspi.c'] - -if GetDepend(['RT_USING_USB_DEVICE']): - src += ['drv_usb.c'] + src += ['drv_qspi.c'] if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): src += ['drv_soft_i2c.c'] @@ -71,6 +68,9 @@ if GetDepend(['BSP_USING_WDT']): if GetDepend(['BSP_USING_SDIO']): src += ['drv_sdio.c'] +if GetDepend(['BSP_USING_USBD_FS']): + src += ['drv_usbd_fs.c'] + src += ['drv_common.c'] path = [cwd] diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h new file mode 100644 index 0000000000000000000000000000000000000000..8450dc257f493a2f40cb07b01e68c2b5b44cd44b --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-22 zylx first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = QUADSPI, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \ + .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE, \ + } +#endif /* QSPI_BUS_CONFIG */ +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ + .Init.Direction = DMA_PERIPH_TO_MEMORY, \ + .Init.PeriphInc = DMA_PINC_DISABLE, \ + .Init.MemInc = DMA_MINC_ENABLE, \ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ + .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ + .Init.Mode = DMA_NORMAL, \ + .Init.Priority = DMA_PRIORITY_LOW \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ + +#define QSPI_IRQn QUADSPI_IRQn +#define QSPI_IRQHandler QUADSPI_IRQHandler + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_fs_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_fs_config.h new file mode 100644 index 0000000000000000000000000000000000000000..b987356c7d38fb93c26decaa58cd48c81afafecd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_fs_config.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-10 ZYH first version + */ +#ifndef __USBD_FS_CONFIG_H__ +#define __USBD_FS_CONFIG_H__ + +#define USBD_FS_IRQ_HANDLER OTG_FS_IRQHandler +#define USBD_INSTANCE USB_OTG_FS +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 8157f4f61e5e65ac07bc6474aa3f42f3f3818ba7..fa077a3c76e11987977b2ff7c6082e7cc899399d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -37,6 +37,8 @@ extern "C" { #include "f4/dma_config.h" #include "f4/uart_config.h" #include "f4/spi_config.h" +#include "f4/qspi_config.h" +#include "f4/usbd_fs_config.h" #include "f4/adc_config.h" #include "f4/tim_config.h" #include "f4/sdio_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbd_fs.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbd_fs.c new file mode 100644 index 0000000000000000000000000000000000000000..91371a38ec309024909ec7366ba65b5212f4a8ed --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbd_fs.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-10 ZYH first version + */ + +#include + +#ifdef BSP_USING_USBD_FS +#include +#include "board.h" +#include +#include + +static PCD_HandleTypeDef _stm_pcd; +static struct udcd _stm_udc; +static struct ep_id _ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, +#if !defined(SOC_SERIES_STM32F1) + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, +#endif + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; + +void USBD_FS_IRQ_HANDLER(void) +{ + rt_interrupt_enter(); + HAL_PCD_IRQHandler(&_stm_pcd); + /* leave interrupt */ + rt_interrupt_leave(); + +} + +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *pcd) +{ + /* open ep0 OUT and IN */ + HAL_PCD_EP_Open(pcd, 0x00, 0x40, EP_TYPE_CTRL); + HAL_PCD_EP_Open(pcd, 0x80, 0x40, EP_TYPE_CTRL); + rt_usbd_reset_handler(&_stm_udc); +} + +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest *)hpcd->Setup); +} + +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + if (epnum == 0) + { + rt_usbd_ep0_in_handler(&_stm_udc); + } + else + { + rt_usbd_ep_in_handler(&_stm_udc, 0x80 | epnum, hpcd->IN_ep[epnum].xfer_count); + } +} + +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + rt_usbd_connect_handler(&_stm_udc); +} + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + rt_usbd_sof_handler(&_stm_udc); +} + +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + rt_usbd_disconnect_handler(&_stm_udc); +} + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + if (epnum != 0) + { + rt_usbd_ep_out_handler(&_stm_udc, epnum, hpcd->OUT_ep[epnum].xfer_count); + } + else + { + rt_usbd_ep0_out_handler(&_stm_udc, hpcd->OUT_ep[0].xfer_count); + } +} + +void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) +{ + if (state == 1) + { +#if defined(SOC_SERIES_STM32F1) + rt_pin_mode(BSP_USB_CONNECT_PIN,PIN_MODE_OUTPUT); + rt_pin_write(BSP_USB_CONNECT_PIN, PIN_HIGH); +#endif + } + else + { +#if defined(SOC_SERIES_STM32F1) + rt_pin_mode(BSP_USB_CONNECT_PIN,PIN_MODE_OUTPUT); + rt_pin_write(BSP_USB_CONNECT_PIN, PIN_LOW); +#endif + } +} + +static rt_err_t _ep_set_stall(rt_uint8_t address) +{ + HAL_PCD_EP_SetStall(&_stm_pcd, address); + return RT_EOK; +} + +static rt_err_t _ep_clear_stall(rt_uint8_t address) +{ + HAL_PCD_EP_ClrStall(&_stm_pcd, address); + return RT_EOK; +} + +static rt_err_t _set_address(rt_uint8_t address) +{ + HAL_PCD_SetAddress(&_stm_pcd, address); + return RT_EOK; +} + +static rt_err_t _set_config(rt_uint8_t address) +{ + return RT_EOK; +} + +static rt_err_t _ep_enable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + HAL_PCD_EP_Open(&_stm_pcd, ep->ep_desc->bEndpointAddress, + ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes); + return RT_EOK; +} + +static rt_err_t _ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + HAL_PCD_EP_Close(&_stm_pcd, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} + +static rt_size_t _ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + RT_ASSERT(buffer != RT_NULL); + return size; +} + +static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + HAL_PCD_EP_Receive(&_stm_pcd, address, buffer, size); + return size; +} + +static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + HAL_PCD_EP_Transmit(&_stm_pcd, address, buffer, size); + return size; +} + +static rt_err_t _ep0_send_status(void) +{ + HAL_PCD_EP_Transmit(&_stm_pcd, 0x00, NULL, 0); + return RT_EOK; +} + +static rt_err_t _suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _wakeup(void) +{ + return RT_EOK; +} + +static rt_err_t _init(rt_device_t device) +{ + PCD_HandleTypeDef *pcd; + /* Set LL Driver parameters */ + pcd = (PCD_HandleTypeDef *)device->user_data; + pcd->Instance = USBD_INSTANCE; + memset(&pcd->Init, 0, sizeof pcd->Init); + pcd->Init.dev_endpoints = 8; + pcd->Init.speed = PCD_SPEED_FULL; + pcd->Init.ep0_mps = DEP0CTL_MPS_64; +#if !defined(SOC_SERIES_STM32F1) + pcd->Init.phy_itface = PCD_PHY_EMBEDDED; +#endif + /* Initialize LL Driver */ + HAL_PCD_Init(pcd); +#if !defined(SOC_SERIES_STM32F1) + HAL_PCDEx_SetRxFiFo(pcd, 0x80); + HAL_PCDEx_SetTxFiFo(pcd, 0, 0x40); + HAL_PCDEx_SetTxFiFo(pcd, 1, 0x40); + HAL_PCDEx_SetTxFiFo(pcd, 2, 0x40); + HAL_PCDEx_SetTxFiFo(pcd, 3, 0x40); +#else + HAL_PCDEx_PMAConfig(pcd, 0x00, PCD_SNG_BUF, 0x18); + HAL_PCDEx_PMAConfig(pcd, 0x80, PCD_SNG_BUF, 0x58); + HAL_PCDEx_PMAConfig(pcd, 0x81, PCD_SNG_BUF, 0x98); + HAL_PCDEx_PMAConfig(pcd, 0x01, PCD_SNG_BUF, 0x118); + HAL_PCDEx_PMAConfig(pcd, 0x82, PCD_SNG_BUF, 0xD8); + HAL_PCDEx_PMAConfig(pcd, 0x02, PCD_SNG_BUF, 0x158); + HAL_PCDEx_PMAConfig(pcd, 0x83, PCD_SNG_BUF, 0x198); +#endif + HAL_PCD_Start(pcd); + return RT_EOK; +} + +const static struct udcd_ops _udc_ops = +{ + _set_address, + _set_config, + _ep_set_stall, + _ep_clear_stall, + _ep_enable, + _ep_disable, + _ep_read_prepare, + _ep_read, + _ep_write, + _ep0_send_status, + _suspend, + _wakeup, +}; + +int stm_usbd_register(void) +{ + rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd)); + _stm_udc.parent.type = RT_Device_Class_USBDevice; + _stm_udc.parent.init = _init; + _stm_udc.parent.user_data = &_stm_pcd; + _stm_udc.ops = &_udc_ops; + /* Register endpoint infomation */ + _stm_udc.ep_pool = _ep_pool; + _stm_udc.ep0.id = &_ep_pool[0]; + rt_device_register((rt_device_t)&_stm_udc, "usbd", 0); + rt_usb_device_init(); + return RT_EOK; +} +INIT_DEVICE_EXPORT(stm_usbd_register); +#endif